1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing. 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// Subtarget features. 20//===----------------------------------------------------------------------===// 21include "AArch64Features.td" 22include "AArch64FMV.td" 23 24//===----------------------------------------------------------------------===// 25// Register File Description 26//===----------------------------------------------------------------------===// 27 28include "AArch64RegisterInfo.td" 29include "AArch64RegisterBanks.td" 30include "AArch64CallingConvention.td" 31 32//===----------------------------------------------------------------------===// 33// Instruction Descriptions 34//===----------------------------------------------------------------------===// 35 36include "AArch64Schedule.td" 37include "AArch64InstrInfo.td" 38include "AArch64SchedPredicates.td" 39include "AArch64SchedPredExynos.td" 40include "AArch64SchedPredNeoverse.td" 41include "AArch64Combine.td" 42 43def AArch64InstrInfo : InstrInfo; 44 45//===----------------------------------------------------------------------===// 46// Named operands for MRS/MSR/TLBI/... 47//===----------------------------------------------------------------------===// 48 49include "AArch64SystemOperands.td" 50 51//===----------------------------------------------------------------------===// 52// AArch64 Processors supported. 53// 54 55//===----------------------------------------------------------------------===// 56// Unsupported features to disable for scheduling models 57//===----------------------------------------------------------------------===// 58 59class AArch64Unsupported { list<Predicate> F; } 60 61let F = [HasSVE2p1, HasSVE2p1_or_SME2, HasSVE2p1_or_SME2p1] in 62def SVE2p1Unsupported : AArch64Unsupported; 63 64def SVE2Unsupported : AArch64Unsupported { 65 let F = !listconcat([HasSVE2, HasSVE2_or_SME, HasSVE2_or_SME2, HasSSVE_FP8FMA, HasSMEF8F16, 66 HasSMEF8F32, HasSVEAES, HasSVE2SHA3, HasSVE2SM4, HasSVEBitPerm, 67 HasSVEB16B16], 68 SVE2p1Unsupported.F); 69} 70 71def SVEUnsupported : AArch64Unsupported { 72 let F = !listconcat([HasSVE, HasSVE_or_SME], 73 SVE2Unsupported.F); 74} 75 76let F = [HasSME2p2, HasSVE2p2_or_SME2p2, HasNonStreamingSVE_or_SME2p2, 77 HasNonStreamingSVE2p2_or_SME2p2, HasNonStreamingSVE2_or_SSVE_BitPerm, 78 HasSME_MOP4, HasSME_TMOP] in 79def SME2p2Unsupported : AArch64Unsupported; 80 81def SME2p1Unsupported : AArch64Unsupported { 82 let F = !listconcat([HasSME2p1, HasSVE2p1_or_SME2p1, HasNonStreamingSVE2p1_or_SSVE_AES], 83 SME2p2Unsupported.F); 84} 85 86def SME2Unsupported : AArch64Unsupported { 87 let F = !listconcat([HasSME2, HasSVE2_or_SME2, HasSVE2p1_or_SME2, HasSSVE_FP8FMA, 88 HasSMEF8F16, HasSMEF8F32, HasSMEF16F16_or_SMEF8F16, HasSMEB16B16], 89 SME2p1Unsupported.F); 90} 91 92def SMEUnsupported : AArch64Unsupported { 93 let F = !listconcat([HasSME, HasSMEI16I64, HasSMEF16F16, HasSMEF64F64, HasSMEFA64], 94 SME2Unsupported.F); 95} 96 97def MTEUnsupported : AArch64Unsupported { 98 let F = [HasMTE]; 99} 100 101let F = [HasPAuth, HasPAuthLR] in 102def PAUnsupported : AArch64Unsupported; 103 104include "AArch64SchedA53.td" 105include "AArch64SchedA55.td" 106include "AArch64SchedA510.td" 107include "AArch64SchedA57.td" 108include "AArch64SchedCyclone.td" 109include "AArch64SchedFalkor.td" 110include "AArch64SchedKryo.td" 111include "AArch64SchedExynosM3.td" 112include "AArch64SchedExynosM4.td" 113include "AArch64SchedExynosM5.td" 114include "AArch64SchedThunderX.td" 115include "AArch64SchedThunderX2T99.td" 116include "AArch64SchedA64FX.td" 117include "AArch64SchedThunderX3T110.td" 118include "AArch64SchedTSV110.td" 119include "AArch64SchedAmpere1.td" 120include "AArch64SchedAmpere1B.td" 121include "AArch64SchedNeoverseN1.td" 122include "AArch64SchedNeoverseN2.td" 123include "AArch64SchedNeoverseN3.td" 124include "AArch64SchedNeoverseV1.td" 125include "AArch64SchedNeoverseV2.td" 126include "AArch64SchedOryon.td" 127 128include "AArch64Processors.td" 129 130//===----------------------------------------------------------------------===// 131// Assembly parser 132//===----------------------------------------------------------------------===// 133 134def GenericAsmParserVariant : AsmParserVariant { 135 int Variant = 0; 136 string Name = "generic"; 137 string BreakCharacters = "."; 138 string TokenizingCharacters = "[]*!/"; 139} 140 141def AppleAsmParserVariant : AsmParserVariant { 142 int Variant = 1; 143 string Name = "apple-neon"; 144 string BreakCharacters = "."; 145 string TokenizingCharacters = "[]*!/"; 146} 147 148//===----------------------------------------------------------------------===// 149// Assembly printer 150//===----------------------------------------------------------------------===// 151// AArch64 Uses the MC printer for asm output, so make sure the TableGen 152// AsmWriter bits get associated with the correct class. 153def GenericAsmWriter : AsmWriter { 154 string AsmWriterClassName = "InstPrinter"; 155 int PassSubtarget = 1; 156 int Variant = 0; 157 bit isMCAsmWriter = 1; 158} 159 160def AppleAsmWriter : AsmWriter { 161 let AsmWriterClassName = "AppleInstPrinter"; 162 int PassSubtarget = 1; 163 int Variant = 1; 164 int isMCAsmWriter = 1; 165} 166 167//===----------------------------------------------------------------------===// 168// Target Declaration 169//===----------------------------------------------------------------------===// 170 171def AArch64 : Target { 172 let InstructionSet = AArch64InstrInfo; 173 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant]; 174 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter]; 175 let AllowRegisterRenaming = 1; 176} 177 178//===----------------------------------------------------------------------===// 179// Pfm Counters 180//===----------------------------------------------------------------------===// 181 182include "AArch64PfmCounters.td" 183