1 //===- llvm/CodeGen/GlobalISel/RegisterBank.cpp - Register Bank --*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements the RegisterBank class. 10 //===----------------------------------------------------------------------===// 11 12 #include "llvm/CodeGen/RegisterBank.h" 13 #include "llvm/ADT/StringExtras.h" 14 #include "llvm/CodeGen/RegisterBankInfo.h" 15 #include "llvm/CodeGen/TargetRegisterInfo.h" 16 #include "llvm/Config/llvm-config.h" 17 #include "llvm/Support/Debug.h" 18 19 #define DEBUG_TYPE "registerbank" 20 21 using namespace llvm; 22 23 RegisterBank::RegisterBank(unsigned ID, const char *Name, 24 const uint32_t *CoveredClasses, 25 unsigned NumRegClasses) 26 : ID(ID), Name(Name) { 27 ContainedRegClasses.resize(NumRegClasses); 28 ContainedRegClasses.setBitsInMask(CoveredClasses); 29 } 30 31 bool RegisterBank::verify(const RegisterBankInfo &RBI, 32 const TargetRegisterInfo &TRI) const { 33 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) { 34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); 35 36 if (!covers(RC)) 37 continue; 38 // Verify that the register bank covers all the sub classes of the 39 // classes it covers. 40 41 // Use a different (slow in that case) method than 42 // RegisterBankInfo to find the subclasses of RC, to make sure 43 // both agree on the covers. 44 for (unsigned SubRCId = 0; SubRCId != End; ++SubRCId) { 45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); 46 47 if (!RC.hasSubClassEq(&SubRC)) 48 continue; 49 50 // Verify that the Size of the register bank is big enough to cover 51 // all the register classes it covers. 52 assert(RBI.getMaximumSize(getID()) >= TRI.getRegSizeInBits(SubRC) && 53 "Size is not big enough for all the subclasses!"); 54 assert(covers(SubRC) && "Not all subclasses are covered"); 55 } 56 } 57 return true; 58 } 59 60 bool RegisterBank::covers(const TargetRegisterClass &RC) const { 61 return ContainedRegClasses.test(RC.getID()); 62 } 63 64 bool RegisterBank::operator==(const RegisterBank &OtherRB) const { 65 // There must be only one instance of a given register bank alive 66 // for the whole compilation. 67 // The RegisterBankInfo is supposed to enforce that. 68 assert((OtherRB.getID() != getID() || &OtherRB == this) && 69 "ID does not uniquely identify a RegisterBank"); 70 return &OtherRB == this; 71 } 72 73 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 74 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const { 75 print(dbgs(), /* IsForDebug */ true, TRI); 76 } 77 #endif 78 79 void RegisterBank::print(raw_ostream &OS, bool IsForDebug, 80 const TargetRegisterInfo *TRI) const { 81 OS << getName(); 82 if (!IsForDebug) 83 return; 84 OS << "(ID:" << getID() << ")\n" 85 << "Number of Covered register classes: " << ContainedRegClasses.count() 86 << '\n'; 87 // Print all the subclasses if we can. 88 // This register classes may not be properly initialized yet. 89 if (!TRI || ContainedRegClasses.empty()) 90 return; 91 assert(ContainedRegClasses.size() == TRI->getNumRegClasses() && 92 "TRI does not match the initialization process?"); 93 OS << "Covered register classes:\n"; 94 ListSeparator LS; 95 for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) { 96 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); 97 98 if (covers(RC)) 99 OS << LS << TRI->getRegClassName(&RC); 100 } 101 } 102