1.. 2 ************************************************** 3 * * 4 * Automatically generated file, do not edit! * 5 * * 6 ************************************************** 7 8.. _amdgpu_synid_gfx9_hwreg: 9 10hwreg 11===== 12 13Bits of a hardware register being accessed. 14 15The bits of this operand have the following meaning: 16 17 ======= ===================== ============ 18 Bits Description Value Range 19 ======= ===================== ============ 20 5:0 Register *id*. 0..63 21 10:6 First bit *offset*. 0..31 22 15:11 *Size* in bits. 1..32 23 ======= ===================== ============ 24 25This operand may be specified as one of the following: 26 27* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from 0 to 0xFFFF. 28* An *hwreg* value which is described below. 29 30 ==================================== =============================================================================== 31 Hwreg Value Syntax Description 32 ==================================== =============================================================================== 33 hwreg({0..63}) All bits of a register indicated by the register *id*. 34 hwreg(<*name*>) All bits of a register indicated by the register *name*. 35 hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by the register *id*, first bit *offset* and *size*. 36 hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by the register *name*, first bit *offset* and *size*. 37 ==================================== =============================================================================== 38 39Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>` 40or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`. 41 42Predefined register *names* include: 43 44 ============================== ========================================== 45 Name Description 46 ============================== ========================================== 47 HW_REG_MODE Shader writable mode bits. 48 HW_REG_STATUS Shader read-only status. 49 HW_REG_TRAPSTS Trap status. 50 HW_REG_HW_ID Id of wave, simd, compute unit, etc. 51 HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation. 52 HW_REG_LDS_ALLOC Per-wave LDS allocation. 53 HW_REG_IB_STS Counters of outstanding instructions. 54 HW_REG_SH_MEM_BASES Memory aperture. 55 HW_REG_TBA_LO tba_lo register. 56 HW_REG_TBA_HI tba_hi register. 57 HW_REG_TMA_LO tma_lo register. 58 HW_REG_TMA_HI tma_hi register. 59 ============================== ========================================== 60 61Examples: 62 63.. parsed-literal:: 64 65 reg = 1 66 offset = 2 67 size = 4 68 hwreg_enc = reg | (offset << 6) | ((size - 1) << 11) 69 70 s_getreg_b32 s2, 0x1881 71 s_getreg_b32 s2, hwreg_enc // the same as above 72 s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above 73 s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above 74 75 s_getreg_b32 s2, hwreg(15) 76 s_getreg_b32 s2, hwreg(51, 1, 31) 77 s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) 78