1# REQUIRES: riscv 2# RUN: rm -rf %t && split-file %s %t && cd %t 3# RUN: llvm-mc -filetype=obj -triple=riscv64 --defsym PAD=0 -mattr=+c,+relax a.s -o a.64.o 4# RUN: llvm-mc -filetype=obj -triple=riscv64 --defsym PAD=5000 -mattr=+c,+relax a.s -o aa.64.o 5# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax c.s -o c.64.o 6# RUN: ld.lld -shared -soname=c.64.so c.64.o -o c.64.so 7 8# RUN: ld.lld -shared -z now a.64.o c.64.o -o a.64.so -z separate-code 9# RUN: llvm-objdump --no-show-raw-insn -M no-aliases -h -d a.64.so | FileCheck %s --check-prefix=GD64 10 11## Test the TLSDESC to LE optimization. Also check --emit-relocs. 12# RUN: ld.lld -e 0 -z now a.64.o c.64.o -o a.64.le -z separate-code --emit-relocs 13# RUN: llvm-objdump --no-show-raw-insn -M no-aliases -hdr a.64.le | FileCheck %s --check-prefix=LE64 14# RUN: ld.lld -e 0 -z now aa.64.o c.64.o -o aa.64.le -z separate-code 15# RUN: llvm-objdump --no-show-raw-insn -M no-aliases -h -d aa.64.le | FileCheck %s --check-prefix=LE64A 16 17## Test the TLSDESC to IE optimization. 18# RUN: ld.lld -e 0 -z now a.64.o c.64.so -o a.64.ie -z separate-code 19# RUN: llvm-objdump --no-show-raw-insn -M no-aliases -h -d a.64.ie | FileCheck %s --check-prefix=IE64 20 21# GD64: .got 00000018 00000000000020c0 22# GD64-LABEL: <_start>: 23# GD64-NEXT: jal {{.*}} <foo> 24# GD64-LABEL: <foo>: 25## &.got[c]-. = 0x20c0+8 - 0x1004 = 0x10c4 26# GD64: 1004: auipc a2, 0x1 27# GD64-NEXT: c.add a7, a7 28# GD64-NEXT: ld a3, 0xc4(a2) 29# GD64-NEXT: c.add a7, a7 30# GD64-NEXT: addi a0, a2, 0xc4 31# GD64-NEXT: c.add a7, a7 32# GD64-NEXT: jalr t0, 0x0(a3) 33# GD64-NEXT: c.add a0, tp 34# GD64-NEXT: jal {{.*}} <foo> 35## &.got[c]-. = 0x20c0+8 - 0x1020 = 0x10a8 36# GD64-LABEL: <.Ltlsdesc_hi1>: 37# GD64-NEXT: 1020: auipc a4, 0x1 38# GD64-NEXT: ld a5, 0xa8(a4) 39# GD64-NEXT: addi a0, a4, 0xa8 40# GD64-NEXT: jalr t0, 0x0(a5) 41# GD64-NEXT: c.add a0, tp 42## &.got[c]-. = 0x20c0+8 - 0x1032 = 0x1096 43# GD64-LABEL: <.Ltlsdesc_hi2>: 44# GD64-NEXT: 1032: auipc a6, 0x1 45# GD64-NEXT: ld a7, 0x96(a6) 46# GD64-NEXT: addi a0, a6, 0x96 47# GD64-NEXT: jalr t0, 0x0(a7) 48# GD64-NEXT: c.add a0, tp 49 50# LE64-LABEL: <_start>: 51# LE64-NEXT: jal {{.*}} <foo> 52# LE64-LABEL: <foo>: 53# LE64-NEXT: c.add a7, a7 54# LE64-NEXT: R_RISCV_TLSDESC_HI20 b 55# LE64-NEXT: R_RISCV_RELAX *ABS* 56# LE64-NEXT: c.add a7, a7 57# LE64-NEXT: R_RISCV_TLSDESC_LOAD_LO12 .Ltlsdesc_hi0 58# LE64-NEXT: R_RISCV_RELAX *ABS* 59# LE64-NEXT: 11008: c.add a7, a7 60# LE64-NEXT: R_RISCV_TLSDESC_ADD_LO12 .Ltlsdesc_hi0 61# LE64-NEXT: R_RISCV_RELAX *ABS* 62# LE64-NEXT: addi a0, zero, 0x7ff 63# LE64-NEXT: R_RISCV_TLSDESC_CALL .Ltlsdesc_hi0 64# LE64-NEXT: R_RISCV_RELAX *ABS* 65# LE64-NEXT: c.add a0, tp 66# LE64-NEXT: jal {{.*}} <foo> 67# LE64-NEXT: R_RISCV_JAL foo 68# LE64-NEXT: R_RISCV_RELAX *ABS* 69# LE64-LABEL: <.Ltlsdesc_hi1>: 70# LE64-NEXT: addi a0, zero, 0x7ff 71# LE64-NEXT: R_RISCV_TLSDESC_HI20 b 72# LE64-NEXT: R_RISCV_RELAX *ABS* 73# LE64-NEXT: R_RISCV_TLSDESC_LOAD_LO12 .Ltlsdesc_hi1 74# LE64-NEXT: R_RISCV_TLSDESC_ADD_LO12 .Ltlsdesc_hi1 75# LE64-NEXT: R_RISCV_TLSDESC_CALL .Ltlsdesc_hi1 76# LE64-NEXT: c.add a0, tp 77# LE64-LABEL: <.Ltlsdesc_hi2>: 78# LE64-NEXT: addi zero, zero, 0x0 79# LE64-NEXT: R_RISCV_TLSDESC_HI20 b 80# LE64-NEXT: addi zero, zero, 0x0 81# LE64-NEXT: R_RISCV_TLSDESC_LOAD_LO12 .Ltlsdesc_hi2 82# LE64-NEXT: R_RISCV_RELAX *ABS* 83# LE64-NEXT: addi zero, zero, 0x0 84# LE64-NEXT: R_RISCV_TLSDESC_ADD_LO12 .Ltlsdesc_hi2 85# LE64-NEXT: R_RISCV_RELAX *ABS* 86# LE64-NEXT: addi a0, zero, 0x7ff 87# LE64-NEXT: R_RISCV_TLSDESC_CALL .Ltlsdesc_hi2 88# LE64-NEXT: c.add a0, tp 89 90# LE64A-LABEL: <_start>: 91# LE64A-NEXT: jal {{.*}} <foo> 92# LE64A-LABEL: <foo>: 93# LE64A-NEXT: c.add a7, a7 94# LE64A-NEXT: c.add a7, a7 95# LE64A-NEXT: 11008: lui a0, 0x2 96# LE64A-NEXT: c.add a7, a7 97# LE64A-NEXT: addi a0, a0, -0x479 98# LE64A-NEXT: c.add a0, tp 99# LE64A-NEXT: jal {{.*}} <foo> 100# LE64A-LABEL: <.Ltlsdesc_hi1>: 101# LE64A-NEXT: lui a0, 0x2 102# LE64A-NEXT: addi a0, a0, -0x479 103# LE64A-NEXT: c.add a0, tp 104# LE64A-LABEL: <.Ltlsdesc_hi2>: 105# LE64A-NEXT: addi zero, zero, 0x0 106# LE64A-NEXT: addi zero, zero, 0x0 107# LE64A-NEXT: lui a0, 0x2 108# LE64A-NEXT: addi a0, a0, -0x479 109# LE64A-NEXT: c.add a0, tp 110 111# IE64: .got 00000010 00000000000120e0 112# IE64-LABEL: <_start>: 113# IE64-NEXT: jal {{.*}} <foo> 114# IE64-LABEL: <foo>: 115# IE64-NEXT: c.add a7, a7 116# IE64-NEXT: c.add a7, a7 117## &.got[c]-. = 0x120e0+8 - 0x11008 = 0x10e0 118# IE64-NEXT: 11008: auipc a0, 0x1 119# IE64-NEXT: c.add a7, a7 120# IE64-NEXT: ld a0, 0xe0(a0) 121# IE64-NEXT: c.add a0, tp 122# IE64-NEXT: jal {{.*}} <foo> 123## &.got[c]-. = 0x120e0+8 - 0x11018 = 0x10d0 124# IE64-LABEL: <.Ltlsdesc_hi1>: 125# IE64-NEXT: 11018: auipc a0, 0x1 126# IE64-NEXT: ld a0, 0xd0(a0) 127# IE64-NEXT: c.add a0, tp 128## &.got[c]-. = 0x120e0+8 - 0x1102a = 0x10be 129# IE64-LABEL: <.Ltlsdesc_hi2>: 130# IE64-NEXT: addi zero, zero, 0x0 131# IE64-NEXT: addi zero, zero, 0x0 132# IE64-NEXT: 1102a: auipc a0, 0x1 133# IE64-NEXT: ld a0, 0xbe(a0) 134# IE64-NEXT: c.add a0, tp 135 136#--- a.s 137.globl _start 138_start: 139.balign 16 140 call foo 141 142foo: 143.Ltlsdesc_hi0: 144.option norelax 145## All 4 instructions have an R_RISCV_RELAX. 146## Check that optimization/relaxation are not affected by irrelevant instructions. 147 auipc a2, %tlsdesc_hi(b) 148 .reloc .-4, R_RISCV_RELAX, 0 149 c.add a7, a7 150 ld a3, %tlsdesc_load_lo(.Ltlsdesc_hi0)(a2) 151 .reloc .-4, R_RISCV_RELAX, 0 152 c.add a7, a7 153 addi a0, a2, %tlsdesc_add_lo(.Ltlsdesc_hi0) 154 .reloc .-4, R_RISCV_RELAX, 0 155 c.add a7, a7 156 jalr t0, 0(a3), %tlsdesc_call(.Ltlsdesc_hi0) 157 .reloc .-4, R_RISCV_RELAX, 0 158 add a0, a0, tp 159.option relax 160 161 call foo 162 163.Ltlsdesc_hi1: 164.option norelax 165## AUIPC has an R_RISCV_RELAX. We perform relaxation, ignoring whether other 166## instructions have R_RISCV_RELAX. 167 auipc a4, %tlsdesc_hi(b) 168 .reloc .-4, R_RISCV_RELAX, 0 169 ld a5, %tlsdesc_load_lo(.Ltlsdesc_hi1)(a4) 170 addi a0, a4, %tlsdesc_add_lo(.Ltlsdesc_hi1) 171 jalr t0, 0(a5), %tlsdesc_call(.Ltlsdesc_hi1) 172 add a0, a0, tp 173.option relax 174 175.Ltlsdesc_hi2: 176.option norelax 177## AUIPC does not have R_RISCV_RELAX. No relaxation. 178 auipc a6, %tlsdesc_hi(b) 179 ld a7, %tlsdesc_load_lo(.Ltlsdesc_hi2)(a6) 180 .reloc .-4, R_RISCV_RELAX, 0 181 addi a0, a6, %tlsdesc_add_lo(.Ltlsdesc_hi2) 182 .reloc .-4, R_RISCV_RELAX, 0 183 jalr t0, 0(a7), %tlsdesc_call(.Ltlsdesc_hi2) 184 add a0, a0, tp 185.option relax 186 187.section .tbss 188.globl a 189.zero 8 190a: 191.zero 2039+PAD ## Place b at 0x7ff+PAD 192 193#--- c.s 194.tbss 195.globl b 196b: 197.zero 4 198