1! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-LE","LLVM" %s 2! RUN: %flang_fc1 -triple powerpc64le-unknown-unknown -target-cpu pwr9 -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR_P9","LLVM" %s 3! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-BE","LLVM" %s 4! REQUIRES: target=powerpc{{.*}} 5 6!---------------------- 7! vec_ld 8!---------------------- 9 10! LLVM-LABEL: @vec_ld_testi8 11subroutine vec_ld_testi8(arg1, arg2, res) 12 integer(1) :: arg1 13 vector(integer(1)) :: arg2, res 14 res = vec_ld(arg1, arg2) 15 16! LLVMIR: %[[arg1:.*]] = load i8, ptr %{{.*}}, align 1 17! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]] 18! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]]) 19! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <16 x i8> 20! LLVMIR: store <16 x i8> %[[bc]], ptr %2, align 16 21end subroutine vec_ld_testi8 22 23! LLVM-LABEL: @vec_ld_testi16 24subroutine vec_ld_testi16(arg1, arg2, res) 25 integer(2) :: arg1 26 vector(integer(2)) :: arg2, res 27 res = vec_ld(arg1, arg2) 28 29! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2 30! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]] 31! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]]) 32! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <8 x i16> 33! LLVMIR: store <8 x i16> %[[bc]], ptr %2, align 16 34end subroutine vec_ld_testi16 35 36! LLVM-LABEL: @vec_ld_testi32 37subroutine vec_ld_testi32(arg1, arg2, res) 38 integer(4) :: arg1 39 vector(integer(4)) :: arg2, res 40 res = vec_ld(arg1, arg2) 41 42! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4 43! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]] 44! LLVMIR: %[[bc:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]]) 45! LLVMIR: store <4 x i32> %[[bc]], ptr %2, align 16 46end subroutine vec_ld_testi32 47 48! LLVM-LABEL: @vec_ld_testf32 49subroutine vec_ld_testf32(arg1, arg2, res) 50 integer(8) :: arg1 51 vector(real(4)) :: arg2, res 52 res = vec_ld(arg1, arg2) 53 54! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8 55! LLVMIR: %[[arg1i32:.*]] = trunc i64 %[[arg1]] to i32 56! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1i32]] 57! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]]) 58! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <4 x float> 59! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16 60end subroutine vec_ld_testf32 61 62! LLVM-LABEL: @vec_ld_testu32 63subroutine vec_ld_testu32(arg1, arg2, res) 64 integer(1) :: arg1 65 vector(unsigned(4)) :: arg2, res 66 res = vec_ld(arg1, arg2) 67 68! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1 69! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]] 70! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]]) 71! LLVMIR: store <4 x i32> %[[call]], ptr %2, align 16 72end subroutine vec_ld_testu32 73 74! LLVM-LABEL: @vec_ld_testi32a 75subroutine vec_ld_testi32a(arg1, arg2, res) 76 integer(4) :: arg1 77 integer(4) :: arg2(10) 78 vector(integer(4)) :: res 79 res = vec_ld(arg1, arg2) 80 81! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4 82! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]] 83! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]]) 84! LLVMIR: store <4 x i32> %[[call]], ptr %2, align 16 85end subroutine vec_ld_testi32a 86 87! LLVM-LABEL: @vec_ld_testf32av 88subroutine vec_ld_testf32av(arg1, arg2, res) 89 integer(8) :: arg1 90 vector(real(4)) :: arg2(2, 4, 8) 91 vector(real(4)) :: res 92 res = vec_ld(arg1, arg2) 93 94! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8 95! LLVMIR: %[[arg1i32:.*]] = trunc i64 %[[arg1]] to i32 96! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1i32]] 97! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]]) 98! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <4 x float> 99! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16 100end subroutine vec_ld_testf32av 101 102! LLVM-LABEL: @vec_ld_testi32s 103subroutine vec_ld_testi32s(arg1, arg2, res) 104 integer(4) :: arg1 105 real(4) :: arg2 106 vector(real(4)) :: res 107 res = vec_ld(arg1, arg2) 108 109! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4 110! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]] 111! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]]) 112! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <4 x float> 113! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16 114end subroutine vec_ld_testi32s 115 116!---------------------- 117! vec_lde 118!---------------------- 119 120! LLVM-LABEL: @vec_lde_testi8s 121subroutine vec_lde_testi8s(arg1, arg2, res) 122 integer(1) :: arg1 123 integer(1) :: arg2 124 vector(integer(1)) :: res 125 res = vec_lde(arg1, arg2) 126 127! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1 128! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]] 129! LLVMIR: %[[call:.*]] = call <16 x i8> @llvm.ppc.altivec.lvebx(ptr %[[addr]]) 130! LLVMIR: store <16 x i8> %[[call]], ptr %2, align 16 131end subroutine vec_lde_testi8s 132 133! LLVM-LABEL: @vec_lde_testi16a 134subroutine vec_lde_testi16a(arg1, arg2, res) 135 integer(2) :: arg1 136 integer(2) :: arg2(2, 4, 8) 137 vector(integer(2)) :: res 138 res = vec_lde(arg1, arg2) 139 140! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2 141! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]] 142! LLVMIR: %[[call:.*]] = call <8 x i16> @llvm.ppc.altivec.lvehx(ptr %[[addr]]) 143! LLVMIR: store <8 x i16> %[[call]], ptr %2, align 16 144end subroutine vec_lde_testi16a 145 146! LLVM-LABEL: @vec_lde_testi32a 147subroutine vec_lde_testi32a(arg1, arg2, res) 148 integer(4) :: arg1 149 integer(4) :: arg2(4) 150 vector(integer(4)) :: res 151 res = vec_lde(arg1, arg2) 152 153! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4 154! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]] 155! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvewx(ptr %[[addr]]) 156! LLVMIR: store <4 x i32> %[[call]], ptr %2, align 16 157end subroutine vec_lde_testi32a 158 159! LLVM-LABEL: @vec_lde_testf32a 160subroutine vec_lde_testf32a(arg1, arg2, res) 161 integer(8) :: arg1 162 real(4) :: arg2(4) 163 vector(real(4)) :: res 164 res = vec_lde(arg1, arg2) 165 166! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8 167! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]] 168! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvewx(ptr %[[addr]]) 169! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <4 x float> 170! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16 171end subroutine vec_lde_testf32a 172 173!---------------------- 174! vec_ldl 175!---------------------- 176 177! LLVM-LABEL: @vec_ldl_testi8 178subroutine vec_ldl_testi8(arg1, arg2, res) 179 integer(1) :: arg1 180 vector(integer(1)) :: arg2, res 181 res = vec_ldl(arg1, arg2) 182 183! LLVMIR: %[[arg1:.*]] = load i8, ptr %{{.*}}, align 1 184! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]] 185! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvxl(ptr %[[addr]]) 186! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <16 x i8> 187! LLVMIR: store <16 x i8> %[[bc]], ptr %2, align 16 188end subroutine vec_ldl_testi8 189 190! LLVM-LABEL: @vec_ldl_testi16 191subroutine vec_ldl_testi16(arg1, arg2, res) 192 integer(2) :: arg1 193 vector(integer(2)) :: arg2, res 194 res = vec_ldl(arg1, arg2) 195 196! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2 197! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]] 198! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvxl(ptr %[[addr]]) 199! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <8 x i16> 200! LLVMIR: store <8 x i16> %[[bc]], ptr %2, align 16 201end subroutine vec_ldl_testi16 202 203! LLVM-LABEL: @vec_ldl_testi32 204subroutine vec_ldl_testi32(arg1, arg2, res) 205 integer(4) :: arg1 206 vector(integer(4)) :: arg2, res 207 res = vec_ldl(arg1, arg2) 208 209! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4 210! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]] 211! LLVMIR: %[[bc:.*]] = call <4 x i32> @llvm.ppc.altivec.lvxl(ptr %[[addr]]) 212! LLVMIR: store <4 x i32> %[[bc]], ptr %2, align 16 213end subroutine vec_ldl_testi32 214 215! LLVM-LABEL: @vec_ldl_testf32 216subroutine vec_ldl_testf32(arg1, arg2, res) 217 integer(8) :: arg1 218 vector(real(4)) :: arg2, res 219 res = vec_ldl(arg1, arg2) 220 221 222! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8 223! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]] 224! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvxl(ptr %[[addr]]) 225! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <4 x float> 226! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16 227end subroutine vec_ldl_testf32 228 229! LLVM-LABEL: @vec_ldl_testu32 230subroutine vec_ldl_testu32(arg1, arg2, res) 231 integer(1) :: arg1 232 vector(unsigned(4)) :: arg2, res 233 res = vec_ldl(arg1, arg2) 234 235! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1 236! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]] 237! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvxl(ptr %[[addr]]) 238! LLVMIR: store <4 x i32> %[[call]], ptr %2, align 16 239end subroutine vec_ldl_testu32 240 241! LLVM-LABEL: @vec_ldl_testi32a 242subroutine vec_ldl_testi32a(arg1, arg2, res) 243 integer(4) :: arg1 244 integer(4) :: arg2(10) 245 vector(integer(4)) :: res 246 res = vec_ldl(arg1, arg2) 247 248! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4 249! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]] 250! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvxl(ptr %[[addr]]) 251! LLVMIR: store <4 x i32> %[[call]], ptr %2, align 16 252end subroutine vec_ldl_testi32a 253 254! LLVM-LABEL: @vec_ldl_testf32av 255subroutine vec_ldl_testf32av(arg1, arg2, res) 256 integer(8) :: arg1 257 vector(real(4)) :: arg2(2, 4, 8) 258 vector(real(4)) :: res 259 res = vec_ldl(arg1, arg2) 260 261! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8 262! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]] 263! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvxl(ptr %[[addr]]) 264! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <4 x float> 265! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16 266end subroutine vec_ldl_testf32av 267 268! LLVM-LABEL: @vec_ldl_testi32s 269subroutine vec_ldl_testi32s(arg1, arg2, res) 270 integer(4) :: arg1 271 real(4) :: arg2 272 vector(real(4)) :: res 273 res = vec_ldl(arg1, arg2) 274 275! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4 276! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]] 277! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvxl(ptr %[[addr]]) 278! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <4 x float> 279! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16 280end subroutine vec_ldl_testi32s 281 282!---------------------- 283! vec_lvsl 284!---------------------- 285 286! LLVM-LABEL: @vec_lvsl_testi8s 287subroutine vec_lvsl_testi8s(arg1, arg2, res) 288 integer(1) :: arg1 289 integer(1) :: arg2 290 vector(unsigned(1)) :: res 291 res = vec_lvsl(arg1, arg2) 292 293! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1 294! LLVMIR: %[[ext:.*]] = sext i8 %[[arg1]] to i64 295! LLVMIR: %[[lshft:.*]] = shl i64 %[[ext]], 56 296! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56 297! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]] 298! LLVMIR: %[[ld:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr %[[addr]]) 299! LLVMIR-LE: %[[sv:.*]] = shufflevector <16 x i8> %[[ld]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> 300! LLVMIR-LE: store <16 x i8> %[[sv]], ptr %2, align 16 301! LLVMIR-BE: store <16 x i8> %[[ld]], ptr %2, align 16 302end subroutine vec_lvsl_testi8s 303 304! LLVM-LABEL: @vec_lvsl_testi16a 305subroutine vec_lvsl_testi16a(arg1, arg2, res) 306 integer(2) :: arg1 307 integer(2) :: arg2(4) 308 vector(unsigned(1)) :: res 309 res = vec_lvsl(arg1, arg2) 310 311! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2 312! LLVMIR: %[[ext:.*]] = sext i16 %[[arg1]] to i64 313! LLVMIR: %[[lshft:.*]] = shl i64 %[[ext]], 56 314! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56 315! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]] 316! LLVMIR: %[[ld:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr %[[addr]]) 317! LLVMIR-LE: %[[sv:.*]] = shufflevector <16 x i8> %[[ld]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> 318! LLVMIR-LE: store <16 x i8> %[[sv]], ptr %2, align 16 319! LLVMIR-BE: store <16 x i8> %[[ld]], ptr %2, align 16 320end subroutine vec_lvsl_testi16a 321 322! LLVM-LABEL: @vec_lvsl_testi32a 323subroutine vec_lvsl_testi32a(arg1, arg2, res) 324 integer(4) :: arg1 325 integer(4) :: arg2(2, 3, 4) 326 vector(unsigned(1)) :: res 327 res = vec_lvsl(arg1, arg2) 328 329! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4 330! LLVMIR: %[[ext:.*]] = sext i32 %[[arg1]] to i64 331! LLVMIR: %[[lshft:.*]] = shl i64 %[[ext]], 56 332! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56 333! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]] 334! LLVMIR: %[[ld:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr %[[addr]]) 335! LLVMIR-LE: %[[sv:.*]] = shufflevector <16 x i8> %[[ld]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> 336! LLVMIR-LE: store <16 x i8> %[[sv]], ptr %2, align 16 337! LLVMIR-BE: store <16 x i8> %[[ld]], ptr %2, align 16 338end subroutine vec_lvsl_testi32a 339 340! LLVM-LABEL: @vec_lvsl_testf32a 341subroutine vec_lvsl_testf32a(arg1, arg2, res) 342 integer(8) :: arg1 343 real(4) :: arg2(4) 344 vector(unsigned(1)) :: res 345 res = vec_lvsl(arg1, arg2) 346 347! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8 348! LLVMIR: %[[lshft:.*]] = shl i64 %[[arg1]], 56 349! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56 350! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]] 351! LLVMIR: %[[ld:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr %[[addr]]) 352! LLVMIR-LE: %[[sv:.*]] = shufflevector <16 x i8> %[[ld]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> 353! LLVMIR-LE: store <16 x i8> %[[sv]], ptr %2, align 16 354! LLVMIR-BE: store <16 x i8> %[[ld]], ptr %2, align 16 355end subroutine vec_lvsl_testf32a 356 357!---------------------- 358! vec_lvsr 359!---------------------- 360 361! LLVM-LABEL: @vec_lvsr_testi8s 362subroutine vec_lvsr_testi8s(arg1, arg2, res) 363 integer(1) :: arg1 364 integer(1) :: arg2 365 vector(unsigned(1)) :: res 366 res = vec_lvsr(arg1, arg2) 367 368! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1 369! LLVMIR: %[[ext:.*]] = sext i8 %[[arg1]] to i64 370! LLVMIR: %[[lshft:.*]] = shl i64 %[[ext]], 56 371! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56 372! LLVMIR: %[[ld:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]] 373! LLVMIR: %[[addr:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr %[[ld]]) 374! LLVMIR-LE: %[[sv:.*]] = shufflevector <16 x i8> %[[addr]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> 375! LLVMIR-LE: store <16 x i8> %[[sv]], ptr %2, align 16 376! LLVMIR-BE: store <16 x i8> %[[addr]], ptr %2, align 16 377end subroutine vec_lvsr_testi8s 378 379! LLVM-LABEL: @vec_lvsr_testi16a 380subroutine vec_lvsr_testi16a(arg1, arg2, res) 381 integer(2) :: arg1 382 integer(2) :: arg2(4) 383 vector(unsigned(1)) :: res 384 res = vec_lvsr(arg1, arg2) 385 386! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2 387! LLVMIR: %[[ext:.*]] = sext i16 %[[arg1]] to i64 388! LLVMIR: %[[lshft:.*]] = shl i64 %[[ext]], 56 389! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56 390! LLVMIR: %[[ld:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]] 391! LLVMIR: %[[addr:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr %[[ld]]) 392! LLVMIR-LE: %[[sv:.*]] = shufflevector <16 x i8> %[[addr]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> 393! LLVMIR-LE: store <16 x i8> %[[sv]], ptr %2, align 16 394! LLVMIR-BE: store <16 x i8> %[[addr]], ptr %2, align 16 395end subroutine vec_lvsr_testi16a 396 397! LLVM-LABEL: @vec_lvsr_testi32a 398subroutine vec_lvsr_testi32a(arg1, arg2, res) 399 integer(4) :: arg1 400 integer(4) :: arg2(2, 3, 4) 401 vector(unsigned(1)) :: res 402 res = vec_lvsr(arg1, arg2) 403 404! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4 405! LLVMIR: %[[ext:.*]] = sext i32 %[[arg1]] to i64 406! LLVMIR: %[[lshft:.*]] = shl i64 %[[ext]], 56 407! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56 408! LLVMIR: %[[ld:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]] 409! LLVMIR: %[[addr:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr %[[ld]]) 410! LLVMIR-LE: %[[sv:.*]] = shufflevector <16 x i8> %[[addr]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> 411! LLVMIR-LE: store <16 x i8> %[[sv]], ptr %2, align 16 412! LLVMIR-BE: store <16 x i8> %[[addr]], ptr %2, align 16 413end subroutine vec_lvsr_testi32a 414 415! LLVM-LABEL: @vec_lvsr_testf32a 416subroutine vec_lvsr_testf32a(arg1, arg2, res) 417 integer(8) :: arg1 418 real(4) :: arg2(4) 419 vector(unsigned(1)) :: res 420 res = vec_lvsr(arg1, arg2) 421 422! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8 423! LLVMIR: %[[lshft:.*]] = shl i64 %[[arg1]], 56 424! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56 425! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]] 426! LLVMIR: %[[ld:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr %[[addr]]) 427! LLVMIR-LE: %[[sv:.*]] = shufflevector <16 x i8> %[[ld]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> 428! LLVMIR-LE: store <16 x i8> %[[sv]], ptr %2, align 16 429! LLVMIR-BE: store <16 x i8> %[[ld]], ptr %2, align 16 430end subroutine vec_lvsr_testf32a 431 432!---------------------- 433! vec_lxv 434!---------------------- 435 436! LLVM-LABEL: @vec_lxv_testi8a 437subroutine vec_lxv_testi8a(arg1, arg2, res) 438 integer(1) :: arg1 439 integer(1) :: arg2(4) 440 vector(integer(1)) :: res 441 res = vec_lxv(arg1, arg2) 442 443! LLVMIR_P9: %[[arg1:.*]] = load i8, ptr %0, align 1 444! LLVMIR_P9: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]] 445! LLVMIR_P9: %[[ld:.*]] = load <16 x i8>, ptr %[[addr]], align 1 446! LLVMIR_P9: store <16 x i8> %[[ld]], ptr %2, align 16 447end subroutine vec_lxv_testi8a 448 449! LLVM-LABEL: @vec_lxv_testi16a 450subroutine vec_lxv_testi16a(arg1, arg2, res) 451 integer(2) :: arg1 452 integer(2) :: arg2(2, 4, 8) 453 vector(integer(2)) :: res 454 res = vec_lxv(arg1, arg2) 455 456! LLVMIR_P9: %[[arg1:.*]] = load i16, ptr %0, align 2 457! LLVMIR_P9: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]] 458! LLVMIR_P9: %[[ld:.*]] = load <8 x i16>, ptr %[[addr]], align 1 459! LLVMIR_P9: store <8 x i16> %[[ld]], ptr %2, align 16 460end subroutine vec_lxv_testi16a 461 462! LLVM-LABEL: @vec_lxv_testi32a 463subroutine vec_lxv_testi32a(arg1, arg2, res) 464 integer(4) :: arg1 465 integer(4) :: arg2(2, 4, 8) 466 vector(integer(4)) :: res 467 res = vec_lxv(arg1, arg2) 468 469! LLVMIR_P9: %[[arg1:.*]] = load i32, ptr %0, align 4 470! LLVMIR_P9: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]] 471! LLVMIR_P9: %[[ld:.*]] = load <4 x i32>, ptr %[[addr]], align 1 472! LLVMIR_P9: store <4 x i32> %[[ld]], ptr %2, align 16 473end subroutine vec_lxv_testi32a 474 475! LLVM-LABEL: @vec_lxv_testf32a 476subroutine vec_lxv_testf32a(arg1, arg2, res) 477 integer(2) :: arg1 478 real(4) :: arg2(4) 479 vector(real(4)) :: res 480 res = vec_lxv(arg1, arg2) 481 482! LLVMIR_P9: %[[arg1:.*]] = load i16, ptr %0, align 2 483! LLVMIR_P9: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]] 484! LLVMIR_P9: %[[ld:.*]] = load <4 x float>, ptr %[[addr]], align 1 485! LLVMIR_P9: store <4 x float> %[[ld]], ptr %2, align 16 486end subroutine vec_lxv_testf32a 487 488! LLVM-LABEL: @vec_lxv_testf64a 489subroutine vec_lxv_testf64a(arg1, arg2, res) 490 integer(8) :: arg1 491 real(8) :: arg2(4) 492 vector(real(8)) :: res 493 res = vec_lxv(arg1, arg2) 494 495! LLVMIR_P9: %[[arg1:.*]] = load i64, ptr %0, align 8 496! LLVMIR_P9: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]] 497! LLVMIR_P9: %[[ld:.*]] = load <2 x double>, ptr %[[addr]], align 1 498! LLVMIR_P9: store <2 x double> %[[ld]], ptr %2, align 16 499end subroutine vec_lxv_testf64a 500 501!---------------------- 502! vec_xld2 503!---------------------- 504 505! LLVM-LABEL: @vec_xld2_testi8a 506subroutine vec_xld2_testi8a(arg1, arg2, res) 507 integer(1) :: arg1 508 vector(integer(1)) :: arg2(4) 509 vector(integer(1)) :: res 510 res = vec_xld2(arg1, arg2) 511 512! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1 513! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]] 514! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x(ptr %[[addr]]) 515! LLVMIR: %[[bc:.*]] = bitcast <2 x double> %[[ld]] to <16 x i8> 516! LLVMIR: store <16 x i8> %[[bc]], ptr %2, align 16 517end subroutine vec_xld2_testi8a 518 519! LLVM-LABEL: @vec_xld2_testi16 520subroutine vec_xld2_testi16(arg1, arg2, res) 521 integer :: arg1 522 vector(integer(2)) :: arg2 523 vector(integer(2)) :: res 524 res = vec_xld2(arg1, arg2) 525 526! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4 527! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]] 528! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x(ptr %[[addr]]) 529! LLVMIR: %[[bc:.*]] = bitcast <2 x double> %[[ld]] to <8 x i16> 530! LLVMIR: store <8 x i16> %[[bc]], ptr %2, align 16 531end subroutine vec_xld2_testi16 532 533! LLVM-LABEL: @vec_xld2_testi32a 534subroutine vec_xld2_testi32a(arg1, arg2, res) 535 integer(4) :: arg1 536 vector(integer(4)) :: arg2(41) 537 vector(integer(4)) :: res 538 res = vec_xld2(arg1, arg2) 539 540! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4 541! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]] 542! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x(ptr %[[addr]]) 543! LLVMIR: %[[bc:.*]] = bitcast <2 x double> %[[ld]] to <4 x i32> 544! LLVMIR: store <4 x i32> %[[bc]], ptr %2, align 16 545end subroutine vec_xld2_testi32a 546 547! LLVM-LABEL: @vec_xld2_testi64a 548subroutine vec_xld2_testi64a(arg1, arg2, res) 549 integer(8) :: arg1 550 vector(integer(8)) :: arg2(4) 551 vector(integer(8)) :: res 552 res = vec_xld2(arg1, arg2) 553 554! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8 555! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]] 556! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x(ptr %[[addr]]) 557! LLVMIR: %[[bc:.*]] = bitcast <2 x double> %[[ld]] to <2 x i64> 558! LLVMIR: store <2 x i64> %[[bc]], ptr %2, align 16 559end subroutine vec_xld2_testi64a 560 561! LLVM-LABEL: @vec_xld2_testf32a 562subroutine vec_xld2_testf32a(arg1, arg2, res) 563 integer(2) :: arg1 564 vector(real(4)) :: arg2(4) 565 vector(real(4)) :: res 566 res = vec_xld2(arg1, arg2) 567 568! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2 569! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]] 570! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x(ptr %[[addr]]) 571! LLVMIR: %[[bc:.*]] = bitcast <2 x double> %[[ld]] to <4 x float> 572! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16 573end subroutine vec_xld2_testf32a 574 575! LLVM-LABEL: @vec_xld2_testf64a 576subroutine vec_xld2_testf64a(arg1, arg2, res) 577 integer(8) :: arg1 578 vector(real(8)) :: arg2(4) 579 vector(real(8)) :: res 580 res = vec_xld2(arg1, arg2) 581 582! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8 583! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]] 584! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x(ptr %[[addr]]) 585! LLVMIR: store <2 x double> %[[ld]], ptr %2, align 16 586end subroutine vec_xld2_testf64a 587 588!---------------------- 589! vec_xl 590!---------------------- 591 592! LLVM-LABEL: @vec_xl_testi8a 593subroutine vec_xl_testi8a(arg1, arg2, res) 594 integer(1) :: arg1 595 integer(1) :: arg2(4) 596 vector(integer(1)) :: res 597 res = vec_xl(arg1, arg2) 598 599! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1 600! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]] 601! LLVMIR: %[[ld:.*]] = load <16 x i8>, ptr %[[addr]], align 1 602! LLVMIR: store <16 x i8> %[[ld]], ptr %2, align 16 603end subroutine vec_xl_testi8a 604 605! LLVM-LABEL: @vec_xl_testi16a 606subroutine vec_xl_testi16a(arg1, arg2, res) 607 integer(2) :: arg1 608 integer(2) :: arg2(2, 4, 8) 609 vector(integer(2)) :: res 610 res = vec_xl(arg1, arg2) 611 612! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2 613! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]] 614! LLVMIR: %[[ld:.*]] = load <8 x i16>, ptr %[[addr]], align 1 615! LLVMIR: store <8 x i16> %[[ld]], ptr %2, align 16 616end subroutine vec_xl_testi16a 617 618! LLVM-LABEL: @vec_xl_testi32a 619subroutine vec_xl_testi32a(arg1, arg2, res) 620 integer(4) :: arg1 621 integer(4) :: arg2(2, 4, 8) 622 vector(integer(4)) :: res 623 res = vec_xl(arg1, arg2) 624 625! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4 626! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]] 627! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.vsx.lxvw4x(ptr %[[addr]]) 628! LLVMIR: store <4 x i32> %[[ld]], ptr %2, align 16 629end subroutine vec_xl_testi32a 630 631! LLVM-LABEL: @vec_xl_testi64a 632subroutine vec_xl_testi64a(arg1, arg2, res) 633 integer(8) :: arg1 634 integer(8) :: arg2(2, 4, 8) 635 vector(integer(8)) :: res 636 res = vec_xl(arg1, arg2) 637 638! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8 639! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]] 640! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x(ptr %[[addr]]) 641! LLVMIR: %[[bc:.*]] = bitcast <2 x double> %[[ld]] to <2 x i64> 642! LLVMIR: store <2 x i64> %[[bc]], ptr %2, align 16 643end subroutine vec_xl_testi64a 644 645! LLVM-LABEL: @vec_xl_testf32a 646subroutine vec_xl_testf32a(arg1, arg2, res) 647 integer(2) :: arg1 648 real(4) :: arg2(4) 649 vector(real(4)) :: res 650 res = vec_xl(arg1, arg2) 651 652! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2 653! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]] 654! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.vsx.lxvw4x(ptr %[[addr]]) 655! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[ld]] to <4 x float> 656! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16 657end subroutine vec_xl_testf32a 658 659! LLVM-LABEL: @vec_xl_testf64a 660subroutine vec_xl_testf64a(arg1, arg2, res) 661 integer(8) :: arg1 662 real(8) :: arg2 663 vector(real(8)) :: res 664 res = vec_xl(arg1, arg2) 665 666! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8 667! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]] 668! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x(ptr %[[addr]]) 669! LLVMIR: store <2 x double> %[[ld]], ptr %2, align 16 670end subroutine vec_xl_testf64a 671 672!---------------------- 673! vec_xlds 674!---------------------- 675 676! LLVM-LABEL: @vec_xlds_testi64a 677subroutine vec_xlds_testi64a(arg1, arg2, res) 678 integer(8) :: arg1 679 vector(integer(8)) :: arg2(4) 680 vector(integer(8)) :: res 681 res = vec_xlds(arg1, arg2) 682 683! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8 684! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]] 685! LLVMIR: %[[ld:.*]] = load i64, ptr %[[addr]], align 8 686! LLVMIR: %[[insrt:.*]] = insertelement <2 x i64> undef, i64 %[[ld]], i32 0 687! LLVMIR: %[[shfl:.*]] = shufflevector <2 x i64> %[[insrt]], <2 x i64> undef, <2 x i32> zeroinitializer 688! LLVMIR: store <2 x i64> %[[shfl]], ptr %2, align 16 689end subroutine vec_xlds_testi64a 690 691! LLVM-LABEL: @vec_xlds_testf64a 692subroutine vec_xlds_testf64a(arg1, arg2, res) 693 integer(8) :: arg1 694 vector(real(8)) :: arg2(4) 695 vector(real(8)) :: res 696 res = vec_xlds(arg1, arg2) 697 698! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8 699! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]] 700! LLVMIR: %[[ld:.*]] = load i64, ptr %[[addr]], align 8 701! LLVMIR: %[[insrt:.*]] = insertelement <2 x i64> undef, i64 %[[ld]], i32 0 702! LLVMIR: %[[shfl:.*]] = shufflevector <2 x i64> %[[insrt]], <2 x i64> undef, <2 x i32> zeroinitializer 703! LLVMIR: %[[bc:.*]] = bitcast <2 x i64> %[[shfl]] to <2 x double> 704! LLVMIR: store <2 x double> %[[bc]], ptr %2, align 16 705end subroutine vec_xlds_testf64a 706 707!---------------------- 708! vec_xl_be 709!---------------------- 710 711! LLVM-LABEL: @vec_xl_be_testi8a 712subroutine vec_xl_be_testi8a(arg1, arg2, res) 713 integer(1) :: arg1 714 integer(1) :: arg2(2, 4, 8) 715 vector(integer(1)) :: res 716 res = vec_xl_be(arg1, arg2) 717 718! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1 719! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]] 720! LLVMIR: %[[ld:.*]] = load <16 x i8>, ptr %[[addr]], align 1 721! LLVMIR-LE: %[[shff:.*]] = shufflevector <16 x i8> %[[ld]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> 722! LLVMIR-LE: store <16 x i8> %[[shff]], ptr %2, align 16 723! LLVMIR-BE: store <16 x i8> %[[ld]], ptr %2, align 16 724end subroutine vec_xl_be_testi8a 725 726! LLVM-LABEL: @vec_xl_be_testi16a 727subroutine vec_xl_be_testi16a(arg1, arg2, res) 728 integer(2) :: arg1 729 integer(2) :: arg2(2, 4, 8) 730 vector(integer(2)) :: res 731 res = vec_xl_be(arg1, arg2) 732 733! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2 734! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]] 735! LLVMIR: %[[ld:.*]] = load <8 x i16>, ptr %[[addr]], align 1 736! LLVMIR-LE: %[[shff:.*]] = shufflevector <8 x i16> %[[ld]], <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> 737! LLVMIR-LE: store <8 x i16> %[[shff]], ptr %2, align 16 738! LLVMIR-BE: store <8 x i16> %[[ld]], ptr %2, align 16 739end subroutine vec_xl_be_testi16a 740 741! LLVM-LABEL: @vec_xl_be_testi32a 742subroutine vec_xl_be_testi32a(arg1, arg2, res) 743 integer(4) :: arg1 744 integer(4) :: arg2(2, 4, 8) 745 vector(integer(4)) :: res 746 res = vec_xl_be(arg1, arg2) 747 748! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4 749! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]] 750! LLVMIR: %[[ld:.*]] = load <4 x i32>, ptr %[[addr]], align 1 751! LLVMIR-LE: %[[shff:.*]] = shufflevector <4 x i32> %[[ld]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> 752! LLVMIR-LE: store <4 x i32> %[[shff]], ptr %2, align 16 753! LLVMIR-BE: store <4 x i32> %[[ld]], ptr %2, align 16 754end subroutine vec_xl_be_testi32a 755 756! LLVM-LABEL: @vec_xl_be_testi64a 757subroutine vec_xl_be_testi64a(arg1, arg2, res) 758 integer(8) :: arg1 759 integer(8) :: arg2(2, 4, 8) 760 vector(integer(8)) :: res 761 res = vec_xl_be(arg1, arg2) 762 763! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8 764! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]] 765! LLVMIR: %[[ld:.*]] = load <2 x i64>, ptr %[[addr]], align 1 766! LLVMIR-LE: %[[shff:.*]] = shufflevector <2 x i64> %[[ld]], <2 x i64> undef, <2 x i32> <i32 1, i32 0> 767! LLVMIR-LE: store <2 x i64> %[[shff]], ptr %2, align 16 768! LLVMIR-BE: store <2 x i64> %[[ld]], ptr %2, align 16 769end subroutine vec_xl_be_testi64a 770 771! LLVM-LABEL: @vec_xl_be_testf32a 772subroutine vec_xl_be_testf32a(arg1, arg2, res) 773 integer(2) :: arg1 774 real(4) :: arg2(4) 775 vector(real(4)) :: res 776 res = vec_xl_be(arg1, arg2) 777 778! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2 779! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]] 780! LLVMIR: %[[ld:.*]] = load <4 x float>, ptr %[[addr]], align 1 781! LLVMIR-LE: %[[shff:.*]] = shufflevector <4 x float> %[[ld]], <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> 782! LLVMIR-LE: store <4 x float> %[[shff]], ptr %2, align 16 783! LLVMIR-BE: store <4 x float> %[[ld]], ptr %2, align 16 784end subroutine vec_xl_be_testf32a 785 786! LLVM-LABEL: @vec_xl_be_testf64a 787subroutine vec_xl_be_testf64a(arg1, arg2, res) 788 integer(8) :: arg1 789 real(8) :: arg2(7) 790 vector(real(8)) :: res 791 res = vec_xl_be(arg1, arg2) 792 793! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8 794! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]] 795! LLVMIR: %[[ld:.*]] = load <2 x double>, ptr %[[addr]], align 1 796! LLVMIR-LE: %[[shff:.*]] = shufflevector <2 x double> %[[ld]], <2 x double> undef, <2 x i32> <i32 1, i32 0> 797! LLVMIR-LE: store <2 x double> %[[shff]], ptr %2, align 16 798! LLVMIR-BE: store <2 x double> %[[ld]], ptr %2, align 16 799end subroutine vec_xl_be_testf64a 800 801!---------------------- 802! vec_xlw4 803!---------------------- 804 805! LLVM-LABEL: @vec_xlw4_testi8a 806subroutine vec_xlw4_testi8a(arg1, arg2, res) 807 integer(1) :: arg1 808 vector(integer(1)) :: arg2(2, 4, 8) 809 vector(integer(1)) :: res 810 res = vec_xlw4(arg1, arg2) 811 812! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1 813! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]] 814! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.vsx.lxvw4x(ptr %[[addr]]) 815! LLVMIR: %[[res:.*]] = bitcast <4 x i32> %[[ld]] to <16 x i8> 816! LLVMIR: store <16 x i8> %[[res]], ptr %2, align 16 817end subroutine vec_xlw4_testi8a 818 819! LLVM-LABEL: @vec_xlw4_testi16a 820subroutine vec_xlw4_testi16a(arg1, arg2, res) 821 integer(2) :: arg1 822 vector(integer(2)) :: arg2(2, 4, 8) 823 vector(integer(2)) :: res 824 res = vec_xlw4(arg1, arg2) 825 826! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2 827! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]] 828! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.vsx.lxvw4x(ptr %[[addr]]) 829! LLVMIR: %[[res:.*]] = bitcast <4 x i32> %[[ld]] to <8 x i16> 830! LLVMIR: store <8 x i16> %[[res]], ptr %2, align 16 831end subroutine vec_xlw4_testi16a 832 833! LLVM-LABEL: @vec_xlw4_testu32a 834subroutine vec_xlw4_testu32a(arg1, arg2, res) 835 integer(4) :: arg1 836 vector(unsigned(4)) :: arg2(2, 4, 8) 837 vector(unsigned(4)) :: res 838 res = vec_xlw4(arg1, arg2) 839 840! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4 841! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]] 842! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.vsx.lxvw4x(ptr %[[addr]]) 843! LLVMIR: store <4 x i32> %[[ld]], ptr %2, align 16 844end subroutine vec_xlw4_testu32a 845 846! LLVM-LABEL: @vec_xlw4_testf32a 847subroutine vec_xlw4_testf32a(arg1, arg2, res) 848 integer(2) :: arg1 849 vector(real(4)) :: arg2(4) 850 vector(real(4)) :: res 851 res = vec_xlw4(arg1, arg2) 852 853! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2 854! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]] 855! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.vsx.lxvw4x(ptr %[[addr]]) 856! LLVMIR: %[[res:.*]] = bitcast <4 x i32> %[[ld]] to <4 x float> 857! LLVMIR: store <4 x float> %[[res]], ptr %2, align 16 858end subroutine vec_xlw4_testf32a 859