1 //===- unittest/Format/FormatTestVerilog.cpp ------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "FormatTestUtils.h" 10 #include "clang/Format/Format.h" 11 #include "llvm/Support/Debug.h" 12 #include "gtest/gtest.h" 13 14 #define DEBUG_TYPE "format-test" 15 16 namespace clang { 17 namespace format { 18 19 class FormatTestVerilog : public ::testing::Test { 20 protected: 21 static std::string format(llvm::StringRef Code, unsigned Offset, 22 unsigned Length, const FormatStyle &Style) { 23 LLVM_DEBUG(llvm::errs() << "---\n"); 24 LLVM_DEBUG(llvm::errs() << Code << "\n\n"); 25 std::vector<tooling::Range> Ranges(1, tooling::Range(Offset, Length)); 26 tooling::Replacements Replaces = reformat(Style, Code, Ranges); 27 auto Result = applyAllReplacements(Code, Replaces); 28 EXPECT_TRUE(static_cast<bool>(Result)); 29 LLVM_DEBUG(llvm::errs() << "\n" << *Result << "\n\n"); 30 return *Result; 31 } 32 33 static std::string 34 format(llvm::StringRef Code, 35 const FormatStyle &Style = getLLVMStyle(FormatStyle::LK_Verilog)) { 36 return format(Code, 0, Code.size(), Style); 37 } 38 39 static void verifyFormat( 40 llvm::StringRef Code, 41 const FormatStyle &Style = getLLVMStyle(FormatStyle::LK_Verilog)) { 42 EXPECT_EQ(Code.str(), format(Code, Style)) << "Expected code is not stable"; 43 EXPECT_EQ(Code.str(), 44 format(test::messUp(Code, /*HandleHash=*/false), Style)); 45 } 46 }; 47 48 TEST_F(FormatTestVerilog, Align) { 49 FormatStyle Style = getLLVMStyle(FormatStyle::LK_Verilog); 50 Style.AlignConsecutiveAssignments.Enabled = true; 51 verifyFormat("x <= x;\n" 52 "sfdbddfbdfbb <= x;\n" 53 "x = x;", 54 Style); 55 verifyFormat("x = x;\n" 56 "sfdbddfbdfbb = x;\n" 57 "x = x;", 58 Style); 59 // Compound assignments are not aligned by default. '<=' is not a compound 60 // assignment. 61 verifyFormat("x <= x;\n" 62 "sfdbddfbdfbb <= x;", 63 Style); 64 verifyFormat("x += x;\n" 65 "sfdbddfbdfbb <= x;", 66 Style); 67 verifyFormat("x <<= x;\n" 68 "sfdbddfbdfbb <= x;", 69 Style); 70 verifyFormat("x <<<= x;\n" 71 "sfdbddfbdfbb <= x;", 72 Style); 73 verifyFormat("x >>= x;\n" 74 "sfdbddfbdfbb <= x;", 75 Style); 76 verifyFormat("x >>>= x;\n" 77 "sfdbddfbdfbb <= x;", 78 Style); 79 Style.AlignConsecutiveAssignments.AlignCompound = true; 80 verifyFormat("x <= x;\n" 81 "sfdbddfbdfbb <= x;", 82 Style); 83 verifyFormat("x += x;\n" 84 "sfdbddfbdfbb <= x;", 85 Style); 86 verifyFormat("x <<= x;\n" 87 "sfdbddfbdfbb <= x;", 88 Style); 89 verifyFormat("x <<<= x;\n" 90 "sfdbddfbdfbb <= x;", 91 Style); 92 verifyFormat("x >>= x;\n" 93 "sfdbddfbdfbb <= x;", 94 Style); 95 verifyFormat("x >>>= x;\n" 96 "sfdbddfbdfbb <= x;", 97 Style); 98 } 99 100 TEST_F(FormatTestVerilog, Assign) { 101 verifyFormat("assign mynet = enable;"); 102 verifyFormat("assign (strong1, pull0) #1 mynet = enable;"); 103 verifyFormat("assign #1 mynet = enable;"); 104 verifyFormat("assign mynet = enable;"); 105 // Test that assignments are on separate lines. 106 verifyFormat("assign mynet = enable,\n" 107 " mynet1 = enable1;"); 108 // Test that `<=` and `,` don't confuse it. 109 verifyFormat("assign mynet = enable1 <= enable2;"); 110 verifyFormat("assign mynet = enable1 <= enable2,\n" 111 " mynet1 = enable3;"); 112 verifyFormat("assign mynet = enable,\n" 113 " mynet1 = enable2 <= enable3;"); 114 verifyFormat("assign mynet = enable(enable1, enable2);"); 115 } 116 117 TEST_F(FormatTestVerilog, BasedLiteral) { 118 verifyFormat("x = '0;"); 119 verifyFormat("x = '1;"); 120 verifyFormat("x = 'X;"); 121 verifyFormat("x = 'x;"); 122 verifyFormat("x = 'Z;"); 123 verifyFormat("x = 'z;"); 124 verifyFormat("x = 659;"); 125 verifyFormat("x = 'h837ff;"); 126 verifyFormat("x = 'o7460;"); 127 verifyFormat("x = 4'b1001;"); 128 verifyFormat("x = 5'D3;"); 129 verifyFormat("x = 3'b01x;"); 130 verifyFormat("x = 12'hx;"); 131 verifyFormat("x = 16'hz;"); 132 verifyFormat("x = -8'd6;"); 133 verifyFormat("x = 4'shf;"); 134 verifyFormat("x = -4'sd15;"); 135 verifyFormat("x = 16'sd?;"); 136 } 137 138 TEST_F(FormatTestVerilog, Block) { 139 verifyFormat("begin\n" 140 " x = x;\n" 141 "end"); 142 verifyFormat("begin : x\n" 143 " x = x;\n" 144 "end : x"); 145 verifyFormat("begin\n" 146 " x = x;\n" 147 " x = x;\n" 148 "end"); 149 verifyFormat("fork\n" 150 " x = x;\n" 151 "join"); 152 verifyFormat("fork\n" 153 " x = x;\n" 154 "join_any"); 155 verifyFormat("fork\n" 156 " x = x;\n" 157 "join_none"); 158 verifyFormat("generate\n" 159 " x = x;\n" 160 "endgenerate"); 161 verifyFormat("generate : x\n" 162 " x = x;\n" 163 "endgenerate : x"); 164 // Nested blocks. 165 verifyFormat("begin\n" 166 " begin\n" 167 " end\n" 168 "end"); 169 verifyFormat("begin : x\n" 170 " begin\n" 171 " end\n" 172 "end : x"); 173 verifyFormat("begin : x\n" 174 " begin : x\n" 175 " end : x\n" 176 "end : x"); 177 verifyFormat("begin\n" 178 " begin : x\n" 179 " end : x\n" 180 "end"); 181 // Test that 'disable fork' and 'rand join' don't get mistaken as blocks. 182 verifyFormat("disable fork;\n" 183 "x = x;"); 184 verifyFormat("rand join x x;\n" 185 "x = x;"); 186 } 187 188 TEST_F(FormatTestVerilog, Case) { 189 verifyFormat("case (data)\n" 190 "endcase"); 191 verifyFormat("casex (data)\n" 192 "endcase"); 193 verifyFormat("casez (data)\n" 194 "endcase"); 195 verifyFormat("case (data) inside\n" 196 "endcase"); 197 verifyFormat("case (data)\n" 198 " 16'd0:\n" 199 " result = 10'b0111111111;\n" 200 "endcase"); 201 verifyFormat("case (data)\n" 202 " xxxxxxxx:\n" 203 " result = 10'b0111111111;\n" 204 "endcase"); 205 // Test labels with multiple options. 206 verifyFormat("case (data)\n" 207 " 16'd0, 16'd1:\n" 208 " result = 10'b0111111111;\n" 209 "endcase"); 210 verifyFormat("case (data)\n" 211 " 16'd0, //\n" 212 " 16'd1:\n" 213 " result = 10'b0111111111;\n" 214 "endcase"); 215 // Test that blocks following labels are indented. 216 verifyFormat("case (data)\n" 217 " 16'd1: fork\n" 218 " result = 10'b1011111111;\n" 219 " join\n" 220 "endcase\n"); 221 verifyFormat("case (data)\n" 222 " 16'd1: fork : x\n" 223 " result = 10'b1011111111;\n" 224 " join : x\n" 225 "endcase\n"); 226 // Test default. 227 verifyFormat("case (data)\n" 228 " default\n" 229 " result = 10'b1011111111;\n" 230 "endcase"); 231 verifyFormat("case (data)\n" 232 " default:\n" 233 " result = 10'b1011111111;\n" 234 "endcase"); 235 // Test that question marks and colons don't get mistaken as labels. 236 verifyFormat("case (data)\n" 237 " 8'b1???????:\n" 238 " instruction1(ir);\n" 239 "endcase"); 240 verifyFormat("case (data)\n" 241 " x ? 8'b1??????? : 1:\n" 242 " instruction3(ir);\n" 243 "endcase"); 244 // Test indention options. 245 auto Style = getLLVMStyle(FormatStyle::LK_Verilog); 246 Style.IndentCaseLabels = false; 247 verifyFormat("case (data)\n" 248 "16'd0:\n" 249 " result = 10'b0111111111;\n" 250 "endcase", 251 Style); 252 verifyFormat("case (data)\n" 253 "16'd0: begin\n" 254 " result = 10'b0111111111;\n" 255 "end\n" 256 "endcase", 257 Style); 258 Style.IndentCaseLabels = true; 259 verifyFormat("case (data)\n" 260 " 16'd0:\n" 261 " result = 10'b0111111111;\n" 262 "endcase", 263 Style); 264 verifyFormat("case (data)\n" 265 " 16'd0: begin\n" 266 " result = 10'b0111111111;\n" 267 " end\n" 268 "endcase", 269 Style); 270 // Other colons should not be mistaken as case colons. 271 Style = getLLVMStyle(FormatStyle::LK_Verilog); 272 Style.BitFieldColonSpacing = FormatStyle::BFCS_None; 273 verifyFormat("case (x[1:0])\n" 274 "endcase", 275 Style); 276 verifyFormat("default:\n" 277 " x[1:0] = x[1:0];", 278 Style); 279 Style.BitFieldColonSpacing = FormatStyle::BFCS_Both; 280 verifyFormat("case (x[1 : 0])\n" 281 "endcase", 282 Style); 283 verifyFormat("default:\n" 284 " x[1 : 0] = x[1 : 0];", 285 Style); 286 Style = getLLVMStyle(FormatStyle::LK_Verilog); 287 Style.SpacesInContainerLiterals = true; 288 verifyFormat("case ('{x : x, default : 9})\n" 289 "endcase", 290 Style); 291 verifyFormat("x = '{x : x, default : 9};\n", Style); 292 verifyFormat("default:\n" 293 " x = '{x : x, default : 9};\n", 294 Style); 295 Style.SpacesInContainerLiterals = false; 296 verifyFormat("case ('{x: x, default: 9})\n" 297 "endcase", 298 Style); 299 verifyFormat("x = '{x: x, default: 9};\n", Style); 300 verifyFormat("default:\n" 301 " x = '{x: x, default: 9};\n", 302 Style); 303 } 304 305 TEST_F(FormatTestVerilog, Coverage) { 306 verifyFormat("covergroup x\n" 307 " @@(begin x);\n" 308 "endgroup"); 309 } 310 311 TEST_F(FormatTestVerilog, Declaration) { 312 verifyFormat("wire mynet;"); 313 verifyFormat("wire mynet, mynet1;"); 314 verifyFormat("wire mynet, //\n" 315 " mynet1;"); 316 verifyFormat("wire mynet = enable;"); 317 verifyFormat("wire mynet = enable, mynet1;"); 318 verifyFormat("wire mynet = enable, //\n" 319 " mynet1;"); 320 verifyFormat("wire mynet, mynet1 = enable;"); 321 verifyFormat("wire mynet, //\n" 322 " mynet1 = enable;"); 323 verifyFormat("wire mynet = enable, mynet1 = enable;"); 324 verifyFormat("wire mynet = enable, //\n" 325 " mynet1 = enable;"); 326 verifyFormat("wire (strong1, pull0) mynet;"); 327 verifyFormat("wire (strong1, pull0) mynet, mynet1;"); 328 verifyFormat("wire (strong1, pull0) mynet, //\n" 329 " mynet1;"); 330 verifyFormat("wire (strong1, pull0) mynet = enable;"); 331 verifyFormat("wire (strong1, pull0) mynet = enable, mynet1;"); 332 verifyFormat("wire (strong1, pull0) mynet = enable, //\n" 333 " mynet1;"); 334 verifyFormat("wire (strong1, pull0) mynet, mynet1 = enable;"); 335 verifyFormat("wire (strong1, pull0) mynet, //\n" 336 " mynet1 = enable;"); 337 } 338 339 TEST_F(FormatTestVerilog, Delay) { 340 // Delay by the default unit. 341 verifyFormat("#0;"); 342 verifyFormat("#1;"); 343 verifyFormat("#10;"); 344 verifyFormat("#1.5;"); 345 // Explicit unit. 346 verifyFormat("#1fs;"); 347 verifyFormat("#1.5fs;"); 348 verifyFormat("#1ns;"); 349 verifyFormat("#1.5ns;"); 350 verifyFormat("#1us;"); 351 verifyFormat("#1.5us;"); 352 verifyFormat("#1ms;"); 353 verifyFormat("#1.5ms;"); 354 verifyFormat("#1s;"); 355 verifyFormat("#1.5s;"); 356 // The following expression should be on the same line. 357 verifyFormat("#1 x = x;"); 358 EXPECT_EQ("#1 x = x;", format("#1\n" 359 "x = x;")); 360 } 361 362 TEST_F(FormatTestVerilog, Headers) { 363 // Test headers with multiple ports. 364 verifyFormat("module mh1\n" 365 " (input var int in1,\n" 366 " input var shortreal in2,\n" 367 " output tagged_st out);\n" 368 "endmodule"); 369 // Ports should be grouped by types. 370 verifyFormat("module test\n" 371 " (input [7 : 0] a,\n" 372 " input signed [7 : 0] b, c, d);\n" 373 "endmodule"); 374 verifyFormat("module test\n" 375 " (input [7 : 0] a,\n" 376 " (* x = x *) input signed [7 : 0] b, c, d);\n" 377 "endmodule"); 378 verifyFormat("module test\n" 379 " (input [7 : 0] a = 0,\n" 380 " input signed [7 : 0] b = 0, c = 0, d = 0);\n" 381 "endmodule"); 382 verifyFormat("module test\n" 383 " #(parameter x)\n" 384 " (input [7 : 0] a,\n" 385 " input signed [7 : 0] b, c, d);\n" 386 "endmodule"); 387 // When a line needs to be broken, ports of the same type should be aligned to 388 // the same column. 389 verifyFormat("module test\n" 390 " (input signed [7 : 0] b, c, //\n" 391 " d);\n" 392 "endmodule"); 393 verifyFormat("module test\n" 394 " ((* x = x *) input signed [7 : 0] b, c, //\n" 395 " d);\n" 396 "endmodule"); 397 verifyFormat("module test\n" 398 " (input signed [7 : 0] b = 0, c, //\n" 399 " d);\n" 400 "endmodule"); 401 verifyFormat("module test\n" 402 " (input signed [7 : 0] b, c = 0, //\n" 403 " d);\n" 404 "endmodule"); 405 verifyFormat("module test\n" 406 " (input signed [7 : 0] b, c, //\n" 407 " d = 0);\n" 408 "endmodule"); 409 verifyFormat("module test\n" 410 " (input wire logic signed [7 : 0][0 : 1] b, c, //\n" 411 " d);\n" 412 "endmodule"); 413 verifyFormat("module test\n" 414 " (input signed [7 : 0] b, //\n" 415 " c, //\n" 416 " d);\n" 417 "endmodule"); 418 verifyFormat("module test\n" 419 " (input [7 : 0] a,\n" 420 " input signed [7 : 0] b, //\n" 421 " c, //\n" 422 " d);\n" 423 "endmodule"); 424 verifyFormat("module test\n" 425 " (input signed [7 : 0] b, //\n" 426 " c, //\n" 427 " d,\n" 428 " output signed [7 : 0] h);\n" 429 "endmodule"); 430 // With a modport. 431 verifyFormat("module m\n" 432 " (i2.master i);\n" 433 "endmodule"); 434 verifyFormat("module m\n" 435 " (i2.master i, ii);\n" 436 "endmodule"); 437 verifyFormat("module m\n" 438 " (i2.master i, //\n" 439 " ii);\n" 440 "endmodule"); 441 verifyFormat("module m\n" 442 " (i2.master i,\n" 443 " input ii);\n" 444 "endmodule"); 445 verifyFormat("module m\n" 446 " (i2::i2.master i);\n" 447 "endmodule"); 448 verifyFormat("module m\n" 449 " (i2::i2.master i, ii);\n" 450 "endmodule"); 451 verifyFormat("module m\n" 452 " (i2::i2.master i, //\n" 453 " ii);\n" 454 "endmodule"); 455 verifyFormat("module m\n" 456 " (i2::i2.master i,\n" 457 " input ii);\n" 458 "endmodule"); 459 verifyFormat("module m\n" 460 " (i2::i2 i);\n" 461 "endmodule"); 462 verifyFormat("module m\n" 463 " (i2::i2 i, ii);\n" 464 "endmodule"); 465 verifyFormat("module m\n" 466 " (i2::i2 i, //\n" 467 " ii);\n" 468 "endmodule"); 469 verifyFormat("module m\n" 470 " (i2::i2 i,\n" 471 " input ii);\n" 472 "endmodule"); 473 // With a macro in the names. 474 verifyFormat("module m\n" 475 " (input var `x a, b);\n" 476 "endmodule"); 477 verifyFormat("module m\n" 478 " (input var `x a, //\n" 479 " b);\n" 480 "endmodule"); 481 verifyFormat("module m\n" 482 " (input var x `a, b);\n" 483 "endmodule"); 484 verifyFormat("module m\n" 485 " (input var x `a, //\n" 486 " b);\n" 487 "endmodule"); 488 // With a concatenation in the names. 489 auto Style = getLLVMStyle(FormatStyle::LK_Verilog); 490 Style.ColumnLimit = 40; 491 verifyFormat("`define X(x) \\\n" 492 " module test \\\n" 493 " (input var x``x a, b);", 494 Style); 495 verifyFormat("`define X(x) \\\n" 496 " module test \\\n" 497 " (input var x``x aaaaaaaaaaaaaaa, \\\n" 498 " b);", 499 Style); 500 verifyFormat("`define X(x) \\\n" 501 " module test \\\n" 502 " (input var x a``x, b);", 503 Style); 504 verifyFormat("`define X(x) \\\n" 505 " module test \\\n" 506 " (input var x aaaaaaaaaaaaaaa``x, \\\n" 507 " b);", 508 Style); 509 } 510 511 TEST_F(FormatTestVerilog, Hierarchy) { 512 verifyFormat("module x;\n" 513 "endmodule"); 514 // Test that the end label is on the same line as the end keyword. 515 verifyFormat("module x;\n" 516 "endmodule : x"); 517 // Test that things inside are indented. 518 verifyFormat("module x;\n" 519 " generate\n" 520 " endgenerate\n" 521 "endmodule"); 522 verifyFormat("program x;\n" 523 " generate\n" 524 " endgenerate\n" 525 "endprogram"); 526 verifyFormat("interface x;\n" 527 " generate\n" 528 " endgenerate\n" 529 "endinterface"); 530 verifyFormat("task x;\n" 531 " generate\n" 532 " endgenerate\n" 533 "endtask"); 534 verifyFormat("function x;\n" 535 " generate\n" 536 " endgenerate\n" 537 "endfunction"); 538 verifyFormat("class x;\n" 539 " generate\n" 540 " endgenerate\n" 541 "endclass"); 542 // Test that they nest. 543 verifyFormat("module x;\n" 544 " program x;\n" 545 " program x;\n" 546 " endprogram\n" 547 " endprogram\n" 548 "endmodule"); 549 // Test that an extern declaration doesn't change the indentation. 550 verifyFormat("extern module x;\n" 551 "x = x;"); 552 // Test complex headers 553 verifyFormat("extern module x\n" 554 " import x.x::x::*;\n" 555 " import x;\n" 556 " #(parameter x)\n" 557 " (output x);"); 558 verifyFormat("module x\n" 559 " import x.x::x::*;\n" 560 " import x;\n" 561 " #(parameter x)\n" 562 " (output x);\n" 563 " generate\n" 564 " endgenerate\n" 565 "endmodule : x"); 566 verifyFormat("virtual class x\n" 567 " (x)\n" 568 " extends x(x)\n" 569 " implements x, x, x;\n" 570 " generate\n" 571 " endgenerate\n" 572 "endclass : x\n"); 573 verifyFormat("function automatic logic [1 : 0] x\n" 574 " (input x);\n" 575 " generate\n" 576 " endgenerate\n" 577 "endfunction : x"); 578 } 579 580 TEST_F(FormatTestVerilog, If) { 581 verifyFormat("if (x)\n" 582 " x = x;"); 583 verifyFormat("unique if (x)\n" 584 " x = x;"); 585 verifyFormat("unique0 if (x)\n" 586 " x = x;"); 587 verifyFormat("priority if (x)\n" 588 " x = x;"); 589 verifyFormat("if (x)\n" 590 " x = x;\n" 591 "x = x;"); 592 593 // Test else 594 verifyFormat("if (x)\n" 595 " x = x;\n" 596 "else if (x)\n" 597 " x = x;\n" 598 "else\n" 599 " x = x;"); 600 verifyFormat("if (x) begin\n" 601 " x = x;\n" 602 "end else if (x) begin\n" 603 " x = x;\n" 604 "end else begin\n" 605 " x = x;\n" 606 "end"); 607 verifyFormat("if (x) begin : x\n" 608 " x = x;\n" 609 "end : x else if (x) begin : x\n" 610 " x = x;\n" 611 "end : x else begin : x\n" 612 " x = x;\n" 613 "end : x"); 614 615 // Test block keywords. 616 verifyFormat("if (x) begin\n" 617 " x = x;\n" 618 "end"); 619 verifyFormat("if (x) begin : x\n" 620 " x = x;\n" 621 "end : x"); 622 verifyFormat("if (x) begin\n" 623 " x = x;\n" 624 " x = x;\n" 625 "end"); 626 verifyFormat("if (x) fork\n" 627 " x = x;\n" 628 "join"); 629 verifyFormat("if (x) fork\n" 630 " x = x;\n" 631 "join_any"); 632 verifyFormat("if (x) fork\n" 633 " x = x;\n" 634 "join_none"); 635 verifyFormat("if (x) generate\n" 636 " x = x;\n" 637 "endgenerate"); 638 verifyFormat("if (x) generate : x\n" 639 " x = x;\n" 640 "endgenerate : x"); 641 642 // Test that concatenation braces don't get regarded as blocks. 643 verifyFormat("if (x)\n" 644 " {x} = x;"); 645 verifyFormat("if (x)\n" 646 " x = {x};"); 647 verifyFormat("if (x)\n" 648 " x = {x};\n" 649 "else\n" 650 " {x} = {x};"); 651 652 // With attributes. 653 verifyFormat("(* x *) if (x)\n" 654 " x = x;"); 655 verifyFormat("(* x = \"x\" *) if (x)\n" 656 " x = x;"); 657 verifyFormat("(* x, x = \"x\" *) if (x)\n" 658 " x = x;"); 659 } 660 661 TEST_F(FormatTestVerilog, Operators) { 662 // Test that unary operators are not followed by space. 663 verifyFormat("x = +x;"); 664 verifyFormat("x = -x;"); 665 verifyFormat("x = !x;"); 666 verifyFormat("x = ~x;"); 667 verifyFormat("x = &x;"); 668 verifyFormat("x = ~&x;"); 669 verifyFormat("x = |x;"); 670 verifyFormat("x = ~|x;"); 671 verifyFormat("x = ^x;"); 672 verifyFormat("x = ~^x;"); 673 verifyFormat("x = ^~x;"); 674 verifyFormat("x = ++x;"); 675 verifyFormat("x = --x;"); 676 677 // Test that `*` and `*>` are binary. 678 verifyFormat("x = x * x;"); 679 verifyFormat("x = (x * x);"); 680 verifyFormat("(opcode *> o1) = 6.1;"); 681 verifyFormat("(C, D *> Q) = 18;"); 682 // The wildcard import is not a binary operator. 683 verifyFormat("import p::*;"); 684 685 // Test that operators don't get split. 686 verifyFormat("x = x++;"); 687 verifyFormat("x = x--;"); 688 verifyFormat("x = x ** x;"); 689 verifyFormat("x = x << x;"); 690 verifyFormat("x = x >> x;"); 691 verifyFormat("x = x <<< x;"); 692 verifyFormat("x = x >>> x;"); 693 verifyFormat("x = x <= x;"); 694 verifyFormat("x = x >= x;"); 695 verifyFormat("x = x == x;"); 696 verifyFormat("x = x != x;"); 697 verifyFormat("x = x === x;"); 698 verifyFormat("x = x !== x;"); 699 verifyFormat("x = x ==? x;"); 700 verifyFormat("x = x !=? x;"); 701 verifyFormat("x = x ~^ x;"); 702 verifyFormat("x = x ^~ x;"); 703 verifyFormat("x = x && x;"); 704 verifyFormat("x = x || x;"); 705 verifyFormat("x = x->x;"); 706 verifyFormat("x = x <-> x;"); 707 verifyFormat("x += x;"); 708 verifyFormat("x -= x;"); 709 verifyFormat("x *= x;"); 710 verifyFormat("x /= x;"); 711 verifyFormat("x %= x;"); 712 verifyFormat("x &= x;"); 713 verifyFormat("x ^= x;"); 714 verifyFormat("x |= x;"); 715 verifyFormat("x <<= x;"); 716 verifyFormat("x >>= x;"); 717 verifyFormat("x <<<= x;"); 718 verifyFormat("x >>>= x;"); 719 verifyFormat("x <= x;"); 720 721 // Test that space is added between operators. 722 EXPECT_EQ("x = x < -x;", format("x=x<-x;")); 723 EXPECT_EQ("x = x << -x;", format("x=x<<-x;")); 724 EXPECT_EQ("x = x <<< -x;", format("x=x<<<-x;")); 725 726 // Test that operators that are C++ identifiers get treated as operators. 727 verifyFormat("solve s before d;"); // before 728 verifyFormat("binsof(i) intersect {0};"); // intersect 729 verifyFormat("req dist {1};"); // dist 730 verifyFormat("a inside {b, c};"); // inside 731 verifyFormat("bus.randomize() with { atype == low; };"); // with 732 } 733 734 TEST_F(FormatTestVerilog, Preprocessor) { 735 auto Style = getLLVMStyle(FormatStyle::LK_Verilog); 736 Style.ColumnLimit = 20; 737 738 // Macro definitions. 739 EXPECT_EQ("`define X \\\n" 740 " if (x) \\\n" 741 " x = x;", 742 format("`define X if(x)x=x;", Style)); 743 EXPECT_EQ("`define X(x) \\\n" 744 " if (x) \\\n" 745 " x = x;", 746 format("`define X(x) if(x)x=x;", Style)); 747 EXPECT_EQ("`define X \\\n" 748 " x = x; \\\n" 749 " x = x;", 750 format("`define X x=x;x=x;", Style)); 751 // Macro definitions with invocations inside. 752 EXPECT_EQ("`define LIST \\\n" 753 " `ENTRY \\\n" 754 " `ENTRY", 755 format("`define LIST \\\n" 756 "`ENTRY \\\n" 757 "`ENTRY", 758 Style)); 759 EXPECT_EQ("`define LIST \\\n" 760 " `x = `x; \\\n" 761 " `x = `x;", 762 format("`define LIST \\\n" 763 "`x = `x; \\\n" 764 "`x = `x;", 765 Style)); 766 EXPECT_EQ("`define LIST \\\n" 767 " `x = `x; \\\n" 768 " `x = `x;", 769 format("`define LIST `x=`x;`x=`x;", Style)); 770 // Macro invocations. 771 verifyFormat("`x = (`x1 + `x2 + x);"); 772 // Lines starting with a preprocessor directive should not be indented. 773 std::string Directives[] = { 774 "begin_keywords", 775 "celldefine", 776 "default_nettype", 777 "define", 778 "else", 779 "elsif", 780 "end_keywords", 781 "endcelldefine", 782 "endif", 783 "ifdef", 784 "ifndef", 785 "include", 786 "line", 787 "nounconnected_drive", 788 "pragma", 789 "resetall", 790 "timescale", 791 "unconnected_drive", 792 "undef", 793 "undefineall", 794 }; 795 for (auto &Name : Directives) { 796 EXPECT_EQ("if (x)\n" 797 "`" + 798 Name + 799 "\n" 800 " ;", 801 format("if (x)\n" 802 "`" + 803 Name + 804 "\n" 805 ";", 806 Style)); 807 } 808 // Lines starting with a regular macro invocation should be indented as a 809 // normal line. 810 EXPECT_EQ("if (x)\n" 811 " `x = `x;\n" 812 "`timescale 1ns / 1ps", 813 format("if (x)\n" 814 "`x = `x;\n" 815 "`timescale 1ns / 1ps", 816 Style)); 817 EXPECT_EQ("if (x)\n" 818 "`timescale 1ns / 1ps\n" 819 " `x = `x;", 820 format("if (x)\n" 821 "`timescale 1ns / 1ps\n" 822 "`x = `x;", 823 Style)); 824 std::string NonDirectives[] = { 825 // For `__FILE__` and `__LINE__`, although the standard classifies them as 826 // preprocessor directives, they are used like regular macros. 827 "__FILE__", "__LINE__", "elif", "foo", "x", 828 }; 829 for (auto &Name : NonDirectives) { 830 EXPECT_EQ("if (x)\n" 831 " `" + 832 Name + ";", 833 format("if (x)\n" 834 "`" + 835 Name + 836 "\n" 837 ";", 838 Style)); 839 } 840 } 841 842 TEST_F(FormatTestVerilog, Primitive) { 843 verifyFormat("primitive multiplexer\n" 844 " (mux, control, dataA, dataB);\n" 845 " output mux;\n" 846 " input control, dataA, dataB;\n" 847 " table\n" 848 " 0 1 ? : 1;\n" 849 " 0 0 ? : 0;\n" 850 " 1 ? 1 : 1;\n" 851 " 1 ? 0 : 0;\n" 852 " x 0 0 : 0;\n" 853 " x 1 1 : 1;\n" 854 " endtable\n" 855 "endprimitive"); 856 verifyFormat("primitive latch\n" 857 " (q, ena_, data);\n" 858 " output q;\n" 859 " reg q;\n" 860 " input ena_, data;\n" 861 " table\n" 862 " 0 1 : ? : 1;\n" 863 " 0 0 : ? : 0;\n" 864 " 1 ? : ? : -;\n" 865 " ? * : ? : -;\n" 866 " endtable\n" 867 "endprimitive"); 868 verifyFormat("primitive d\n" 869 " (q, clock, data);\n" 870 " output q;\n" 871 " reg q;\n" 872 " input clock, data;\n" 873 " table\n" 874 " (01) 0 : ? : 0;\n" 875 " (01) 1 : ? : 1;\n" 876 " (0?) 1 : 1 : 1;\n" 877 " (0?) 0 : 0 : 0;\n" 878 " (?0) ? : ? : -;\n" 879 " (?\?) ? : ? : -;\n" 880 " endtable\n" 881 "endprimitive"); 882 } 883 884 TEST_F(FormatTestVerilog, Streaming) { 885 verifyFormat("x = {>>{j}};"); 886 verifyFormat("x = {>>byte{j}};"); 887 verifyFormat("x = {<<{j}};"); 888 verifyFormat("x = {<<byte{j}};"); 889 verifyFormat("x = {<<16{j}};"); 890 verifyFormat("x = {<<{8'b0011_0101}};"); 891 verifyFormat("x = {<<4{6'b11_0101}};"); 892 verifyFormat("x = {>>4{6'b11_0101}};"); 893 verifyFormat("x = {<<2{{<<{4'b1101}}}};"); 894 verifyFormat("bit [96 : 1] y = {>>{a, b, c}};"); 895 verifyFormat("int j = {>>{a, b, c}};"); 896 verifyFormat("{>>{a, b, c}} = 23'b1;"); 897 verifyFormat("{>>{a, b, c}} = x;"); 898 verifyFormat("{>>{j}} = x;"); 899 verifyFormat("{>>byte{j}} = x;"); 900 verifyFormat("{<<{j}} = x;"); 901 verifyFormat("{<<byte{j}} = x;"); 902 } 903 904 TEST_F(FormatTestVerilog, StructuredProcedure) { 905 // Blocks should be indented correctly. 906 verifyFormat("initial begin\n" 907 "end"); 908 verifyFormat("initial begin\n" 909 " x <= x;\n" 910 " x <= x;\n" 911 "end"); 912 verifyFormat("initial\n" 913 " x <= x;\n" 914 "x <= x;"); 915 verifyFormat("always @(x) begin\n" 916 "end"); 917 verifyFormat("always @(x) begin\n" 918 " x <= x;\n" 919 " x <= x;\n" 920 "end"); 921 verifyFormat("always @(x)\n" 922 " x <= x;\n" 923 "x <= x;"); 924 // Various keywords. 925 verifyFormat("always @(x)\n" 926 " x <= x;"); 927 verifyFormat("always @(posedge x)\n" 928 " x <= x;"); 929 verifyFormat("always\n" 930 " x <= x;"); 931 verifyFormat("always @*\n" 932 " x <= x;"); 933 verifyFormat("always @(*)\n" 934 " x <= x;"); 935 verifyFormat("always_comb\n" 936 " x <= x;"); 937 verifyFormat("always_latch @(x)\n" 938 " x <= x;"); 939 verifyFormat("always_ff @(posedge x)\n" 940 " x <= x;"); 941 verifyFormat("initial\n" 942 " x <= x;"); 943 verifyFormat("final\n" 944 " x <= x;"); 945 verifyFormat("forever\n" 946 " x <= x;"); 947 } 948 } // namespace format 949 } // end namespace clang 950