1 //===- unittest/Format/FormatTestVerilog.cpp ------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "FormatTestUtils.h" 10 #include "clang/Format/Format.h" 11 #include "llvm/Support/Debug.h" 12 #include "gtest/gtest.h" 13 14 #define DEBUG_TYPE "format-test" 15 16 namespace clang { 17 namespace format { 18 19 class FormatTestVerilog : public ::testing::Test { 20 protected: 21 static std::string format(llvm::StringRef Code, unsigned Offset, 22 unsigned Length, const FormatStyle &Style) { 23 LLVM_DEBUG(llvm::errs() << "---\n"); 24 LLVM_DEBUG(llvm::errs() << Code << "\n\n"); 25 std::vector<tooling::Range> Ranges(1, tooling::Range(Offset, Length)); 26 tooling::Replacements Replaces = reformat(Style, Code, Ranges); 27 auto Result = applyAllReplacements(Code, Replaces); 28 EXPECT_TRUE(static_cast<bool>(Result)); 29 LLVM_DEBUG(llvm::errs() << "\n" << *Result << "\n\n"); 30 return *Result; 31 } 32 33 static std::string 34 format(llvm::StringRef Code, 35 const FormatStyle &Style = getLLVMStyle(FormatStyle::LK_Verilog)) { 36 return format(Code, 0, Code.size(), Style); 37 } 38 39 static void verifyFormat( 40 llvm::StringRef Code, 41 const FormatStyle &Style = getLLVMStyle(FormatStyle::LK_Verilog)) { 42 EXPECT_EQ(Code.str(), format(Code, Style)) << "Expected code is not stable"; 43 EXPECT_EQ(Code.str(), 44 format(test::messUp(Code, /*HandleHash=*/false), Style)); 45 } 46 }; 47 48 TEST_F(FormatTestVerilog, Align) { 49 FormatStyle Style = getLLVMStyle(FormatStyle::LK_Verilog); 50 Style.AlignConsecutiveAssignments.Enabled = true; 51 verifyFormat("x <= x;\n" 52 "sfdbddfbdfbb <= x;\n" 53 "x = x;", 54 Style); 55 verifyFormat("x = x;\n" 56 "sfdbddfbdfbb = x;\n" 57 "x = x;", 58 Style); 59 // Compound assignments are not aligned by default. '<=' is not a compound 60 // assignment. 61 verifyFormat("x <= x;\n" 62 "sfdbddfbdfbb <= x;", 63 Style); 64 verifyFormat("x += x;\n" 65 "sfdbddfbdfbb <= x;", 66 Style); 67 verifyFormat("x <<= x;\n" 68 "sfdbddfbdfbb <= x;", 69 Style); 70 verifyFormat("x <<<= x;\n" 71 "sfdbddfbdfbb <= x;", 72 Style); 73 verifyFormat("x >>= x;\n" 74 "sfdbddfbdfbb <= x;", 75 Style); 76 verifyFormat("x >>>= x;\n" 77 "sfdbddfbdfbb <= x;", 78 Style); 79 Style.AlignConsecutiveAssignments.AlignCompound = true; 80 verifyFormat("x <= x;\n" 81 "sfdbddfbdfbb <= x;", 82 Style); 83 verifyFormat("x += x;\n" 84 "sfdbddfbdfbb <= x;", 85 Style); 86 verifyFormat("x <<= x;\n" 87 "sfdbddfbdfbb <= x;", 88 Style); 89 verifyFormat("x <<<= x;\n" 90 "sfdbddfbdfbb <= x;", 91 Style); 92 verifyFormat("x >>= x;\n" 93 "sfdbddfbdfbb <= x;", 94 Style); 95 verifyFormat("x >>>= x;\n" 96 "sfdbddfbdfbb <= x;", 97 Style); 98 } 99 100 TEST_F(FormatTestVerilog, BasedLiteral) { 101 verifyFormat("x = '0;"); 102 verifyFormat("x = '1;"); 103 verifyFormat("x = 'X;"); 104 verifyFormat("x = 'x;"); 105 verifyFormat("x = 'Z;"); 106 verifyFormat("x = 'z;"); 107 verifyFormat("x = 659;"); 108 verifyFormat("x = 'h837ff;"); 109 verifyFormat("x = 'o7460;"); 110 verifyFormat("x = 4'b1001;"); 111 verifyFormat("x = 5'D3;"); 112 verifyFormat("x = 3'b01x;"); 113 verifyFormat("x = 12'hx;"); 114 verifyFormat("x = 16'hz;"); 115 verifyFormat("x = -8'd6;"); 116 verifyFormat("x = 4'shf;"); 117 verifyFormat("x = -4'sd15;"); 118 verifyFormat("x = 16'sd?;"); 119 } 120 121 TEST_F(FormatTestVerilog, Block) { 122 verifyFormat("begin\n" 123 " x = x;\n" 124 "end"); 125 verifyFormat("begin : x\n" 126 " x = x;\n" 127 "end : x"); 128 verifyFormat("begin\n" 129 " x = x;\n" 130 " x = x;\n" 131 "end"); 132 verifyFormat("fork\n" 133 " x = x;\n" 134 "join"); 135 verifyFormat("fork\n" 136 " x = x;\n" 137 "join_any"); 138 verifyFormat("fork\n" 139 " x = x;\n" 140 "join_none"); 141 verifyFormat("generate\n" 142 " x = x;\n" 143 "endgenerate"); 144 verifyFormat("generate : x\n" 145 " x = x;\n" 146 "endgenerate : x"); 147 // Nested blocks. 148 verifyFormat("begin\n" 149 " begin\n" 150 " end\n" 151 "end"); 152 verifyFormat("begin : x\n" 153 " begin\n" 154 " end\n" 155 "end : x"); 156 verifyFormat("begin : x\n" 157 " begin : x\n" 158 " end : x\n" 159 "end : x"); 160 verifyFormat("begin\n" 161 " begin : x\n" 162 " end : x\n" 163 "end"); 164 // Test that 'disable fork' and 'rand join' don't get mistaken as blocks. 165 verifyFormat("disable fork;\n" 166 "x = x;"); 167 verifyFormat("rand join x x;\n" 168 "x = x;"); 169 } 170 171 TEST_F(FormatTestVerilog, Case) { 172 verifyFormat("case (data)\n" 173 "endcase"); 174 verifyFormat("casex (data)\n" 175 "endcase"); 176 verifyFormat("casez (data)\n" 177 "endcase"); 178 verifyFormat("case (data) inside\n" 179 "endcase"); 180 verifyFormat("case (data)\n" 181 " 16'd0:\n" 182 " result = 10'b0111111111;\n" 183 "endcase"); 184 verifyFormat("case (data)\n" 185 " xxxxxxxx:\n" 186 " result = 10'b0111111111;\n" 187 "endcase"); 188 // Test labels with multiple options. 189 verifyFormat("case (data)\n" 190 " 16'd0, 16'd1:\n" 191 " result = 10'b0111111111;\n" 192 "endcase"); 193 verifyFormat("case (data)\n" 194 " 16'd0, //\n" 195 " 16'd1:\n" 196 " result = 10'b0111111111;\n" 197 "endcase"); 198 // Test that blocks following labels are indented. 199 verifyFormat("case (data)\n" 200 " 16'd1: fork\n" 201 " result = 10'b1011111111;\n" 202 " join\n" 203 "endcase\n"); 204 verifyFormat("case (data)\n" 205 " 16'd1: fork : x\n" 206 " result = 10'b1011111111;\n" 207 " join : x\n" 208 "endcase\n"); 209 // Test default. 210 verifyFormat("case (data)\n" 211 " default\n" 212 " result = 10'b1011111111;\n" 213 "endcase"); 214 verifyFormat("case (data)\n" 215 " default:\n" 216 " result = 10'b1011111111;\n" 217 "endcase"); 218 // Test that question marks and colons don't get mistaken as labels. 219 verifyFormat("case (data)\n" 220 " 8'b1???????:\n" 221 " instruction1(ir);\n" 222 "endcase"); 223 verifyFormat("case (data)\n" 224 " x ? 8'b1??????? : 1:\n" 225 " instruction3(ir);\n" 226 "endcase"); 227 // Test indention options. 228 auto Style = getLLVMStyle(FormatStyle::LK_Verilog); 229 Style.IndentCaseLabels = false; 230 verifyFormat("case (data)\n" 231 "16'd0:\n" 232 " result = 10'b0111111111;\n" 233 "endcase", 234 Style); 235 verifyFormat("case (data)\n" 236 "16'd0: begin\n" 237 " result = 10'b0111111111;\n" 238 "end\n" 239 "endcase", 240 Style); 241 Style.IndentCaseLabels = true; 242 verifyFormat("case (data)\n" 243 " 16'd0:\n" 244 " result = 10'b0111111111;\n" 245 "endcase", 246 Style); 247 verifyFormat("case (data)\n" 248 " 16'd0: begin\n" 249 " result = 10'b0111111111;\n" 250 " end\n" 251 "endcase", 252 Style); 253 // Other colons should not be mistaken as case colons. 254 Style = getLLVMStyle(FormatStyle::LK_Verilog); 255 Style.BitFieldColonSpacing = FormatStyle::BFCS_None; 256 verifyFormat("case (x[1:0])\n" 257 "endcase", 258 Style); 259 verifyFormat("default:\n" 260 " x[1:0] = x[1:0];", 261 Style); 262 Style.BitFieldColonSpacing = FormatStyle::BFCS_Both; 263 verifyFormat("case (x[1 : 0])\n" 264 "endcase", 265 Style); 266 verifyFormat("default:\n" 267 " x[1 : 0] = x[1 : 0];", 268 Style); 269 Style = getLLVMStyle(FormatStyle::LK_Verilog); 270 Style.SpacesInContainerLiterals = true; 271 verifyFormat("case ('{x : x, default : 9})\n" 272 "endcase", 273 Style); 274 verifyFormat("x = '{x : x, default : 9};\n", Style); 275 verifyFormat("default:\n" 276 " x = '{x : x, default : 9};\n", 277 Style); 278 Style.SpacesInContainerLiterals = false; 279 verifyFormat("case ('{x: x, default: 9})\n" 280 "endcase", 281 Style); 282 verifyFormat("x = '{x: x, default: 9};\n", Style); 283 verifyFormat("default:\n" 284 " x = '{x: x, default: 9};\n", 285 Style); 286 } 287 288 TEST_F(FormatTestVerilog, Coverage) { 289 verifyFormat("covergroup x\n" 290 " @@(begin x);\n" 291 "endgroup"); 292 } 293 294 TEST_F(FormatTestVerilog, Declaration) { 295 verifyFormat("wire mynet;"); 296 verifyFormat("wire mynet, mynet1;"); 297 verifyFormat("wire mynet, //\n" 298 " mynet1;"); 299 verifyFormat("wire mynet = enable;"); 300 verifyFormat("wire mynet = enable, mynet1;"); 301 verifyFormat("wire mynet = enable, //\n" 302 " mynet1;"); 303 verifyFormat("wire mynet, mynet1 = enable;"); 304 verifyFormat("wire mynet, //\n" 305 " mynet1 = enable;"); 306 verifyFormat("wire mynet = enable, mynet1 = enable;"); 307 verifyFormat("wire mynet = enable, //\n" 308 " mynet1 = enable;"); 309 verifyFormat("wire (strong1, pull0) mynet;"); 310 verifyFormat("wire (strong1, pull0) mynet, mynet1;"); 311 verifyFormat("wire (strong1, pull0) mynet, //\n" 312 " mynet1;"); 313 verifyFormat("wire (strong1, pull0) mynet = enable;"); 314 verifyFormat("wire (strong1, pull0) mynet = enable, mynet1;"); 315 verifyFormat("wire (strong1, pull0) mynet = enable, //\n" 316 " mynet1;"); 317 verifyFormat("wire (strong1, pull0) mynet, mynet1 = enable;"); 318 verifyFormat("wire (strong1, pull0) mynet, //\n" 319 " mynet1 = enable;"); 320 } 321 322 TEST_F(FormatTestVerilog, Delay) { 323 // Delay by the default unit. 324 verifyFormat("#0;"); 325 verifyFormat("#1;"); 326 verifyFormat("#10;"); 327 verifyFormat("#1.5;"); 328 // Explicit unit. 329 verifyFormat("#1fs;"); 330 verifyFormat("#1.5fs;"); 331 verifyFormat("#1ns;"); 332 verifyFormat("#1.5ns;"); 333 verifyFormat("#1us;"); 334 verifyFormat("#1.5us;"); 335 verifyFormat("#1ms;"); 336 verifyFormat("#1.5ms;"); 337 verifyFormat("#1s;"); 338 verifyFormat("#1.5s;"); 339 // The following expression should be on the same line. 340 verifyFormat("#1 x = x;"); 341 EXPECT_EQ("#1 x = x;", format("#1\n" 342 "x = x;")); 343 } 344 345 TEST_F(FormatTestVerilog, Headers) { 346 // Test headers with multiple ports. 347 verifyFormat("module mh1\n" 348 " (input var int in1,\n" 349 " input var shortreal in2,\n" 350 " output tagged_st out);\n" 351 "endmodule"); 352 // Ports should be grouped by types. 353 verifyFormat("module test\n" 354 " (input [7 : 0] a,\n" 355 " input signed [7 : 0] b, c, d);\n" 356 "endmodule"); 357 verifyFormat("module test\n" 358 " (input [7 : 0] a,\n" 359 " (* x = x *) input signed [7 : 0] b, c, d);\n" 360 "endmodule"); 361 verifyFormat("module test\n" 362 " (input [7 : 0] a = 0,\n" 363 " input signed [7 : 0] b = 0, c = 0, d = 0);\n" 364 "endmodule"); 365 verifyFormat("module test\n" 366 " #(parameter x)\n" 367 " (input [7 : 0] a,\n" 368 " input signed [7 : 0] b, c, d);\n" 369 "endmodule"); 370 // When a line needs to be broken, ports of the same type should be aligned to 371 // the same column. 372 verifyFormat("module test\n" 373 " (input signed [7 : 0] b, c, //\n" 374 " d);\n" 375 "endmodule"); 376 verifyFormat("module test\n" 377 " ((* x = x *) input signed [7 : 0] b, c, //\n" 378 " d);\n" 379 "endmodule"); 380 verifyFormat("module test\n" 381 " (input signed [7 : 0] b = 0, c, //\n" 382 " d);\n" 383 "endmodule"); 384 verifyFormat("module test\n" 385 " (input signed [7 : 0] b, c = 0, //\n" 386 " d);\n" 387 "endmodule"); 388 verifyFormat("module test\n" 389 " (input signed [7 : 0] b, c, //\n" 390 " d = 0);\n" 391 "endmodule"); 392 verifyFormat("module test\n" 393 " (input wire logic signed [7 : 0][0 : 1] b, c, //\n" 394 " d);\n" 395 "endmodule"); 396 verifyFormat("module test\n" 397 " (input signed [7 : 0] b, //\n" 398 " c, //\n" 399 " d);\n" 400 "endmodule"); 401 verifyFormat("module test\n" 402 " (input [7 : 0] a,\n" 403 " input signed [7 : 0] b, //\n" 404 " c, //\n" 405 " d);\n" 406 "endmodule"); 407 verifyFormat("module test\n" 408 " (input signed [7 : 0] b, //\n" 409 " c, //\n" 410 " d,\n" 411 " output signed [7 : 0] h);\n" 412 "endmodule"); 413 // With a modport. 414 verifyFormat("module m\n" 415 " (i2.master i);\n" 416 "endmodule"); 417 verifyFormat("module m\n" 418 " (i2.master i, ii);\n" 419 "endmodule"); 420 verifyFormat("module m\n" 421 " (i2.master i, //\n" 422 " ii);\n" 423 "endmodule"); 424 verifyFormat("module m\n" 425 " (i2.master i,\n" 426 " input ii);\n" 427 "endmodule"); 428 verifyFormat("module m\n" 429 " (i2::i2.master i);\n" 430 "endmodule"); 431 verifyFormat("module m\n" 432 " (i2::i2.master i, ii);\n" 433 "endmodule"); 434 verifyFormat("module m\n" 435 " (i2::i2.master i, //\n" 436 " ii);\n" 437 "endmodule"); 438 verifyFormat("module m\n" 439 " (i2::i2.master i,\n" 440 " input ii);\n" 441 "endmodule"); 442 verifyFormat("module m\n" 443 " (i2::i2 i);\n" 444 "endmodule"); 445 verifyFormat("module m\n" 446 " (i2::i2 i, ii);\n" 447 "endmodule"); 448 verifyFormat("module m\n" 449 " (i2::i2 i, //\n" 450 " ii);\n" 451 "endmodule"); 452 verifyFormat("module m\n" 453 " (i2::i2 i,\n" 454 " input ii);\n" 455 "endmodule"); 456 // With a macro in the names. 457 verifyFormat("module m\n" 458 " (input var `x a, b);\n" 459 "endmodule"); 460 verifyFormat("module m\n" 461 " (input var `x a, //\n" 462 " b);\n" 463 "endmodule"); 464 verifyFormat("module m\n" 465 " (input var x `a, b);\n" 466 "endmodule"); 467 verifyFormat("module m\n" 468 " (input var x `a, //\n" 469 " b);\n" 470 "endmodule"); 471 // With a concatenation in the names. 472 auto Style = getLLVMStyle(FormatStyle::LK_Verilog); 473 Style.ColumnLimit = 40; 474 verifyFormat("`define X(x) \\\n" 475 " module test \\\n" 476 " (input var x``x a, b);", 477 Style); 478 verifyFormat("`define X(x) \\\n" 479 " module test \\\n" 480 " (input var x``x aaaaaaaaaaaaaaa, \\\n" 481 " b);", 482 Style); 483 verifyFormat("`define X(x) \\\n" 484 " module test \\\n" 485 " (input var x a``x, b);", 486 Style); 487 verifyFormat("`define X(x) \\\n" 488 " module test \\\n" 489 " (input var x aaaaaaaaaaaaaaa``x, \\\n" 490 " b);", 491 Style); 492 } 493 494 TEST_F(FormatTestVerilog, Hierarchy) { 495 verifyFormat("module x;\n" 496 "endmodule"); 497 // Test that the end label is on the same line as the end keyword. 498 verifyFormat("module x;\n" 499 "endmodule : x"); 500 // Test that things inside are indented. 501 verifyFormat("module x;\n" 502 " generate\n" 503 " endgenerate\n" 504 "endmodule"); 505 verifyFormat("program x;\n" 506 " generate\n" 507 " endgenerate\n" 508 "endprogram"); 509 verifyFormat("interface x;\n" 510 " generate\n" 511 " endgenerate\n" 512 "endinterface"); 513 verifyFormat("task x;\n" 514 " generate\n" 515 " endgenerate\n" 516 "endtask"); 517 verifyFormat("function x;\n" 518 " generate\n" 519 " endgenerate\n" 520 "endfunction"); 521 verifyFormat("class x;\n" 522 " generate\n" 523 " endgenerate\n" 524 "endclass"); 525 // Test that they nest. 526 verifyFormat("module x;\n" 527 " program x;\n" 528 " program x;\n" 529 " endprogram\n" 530 " endprogram\n" 531 "endmodule"); 532 // Test that an extern declaration doesn't change the indentation. 533 verifyFormat("extern module x;\n" 534 "x = x;"); 535 // Test complex headers 536 verifyFormat("extern module x\n" 537 " import x.x::x::*;\n" 538 " import x;\n" 539 " #(parameter x)\n" 540 " (output x);"); 541 verifyFormat("module x\n" 542 " import x.x::x::*;\n" 543 " import x;\n" 544 " #(parameter x)\n" 545 " (output x);\n" 546 " generate\n" 547 " endgenerate\n" 548 "endmodule : x"); 549 verifyFormat("virtual class x\n" 550 " (x)\n" 551 " extends x(x)\n" 552 " implements x, x, x;\n" 553 " generate\n" 554 " endgenerate\n" 555 "endclass : x\n"); 556 verifyFormat("function automatic logic [1 : 0] x\n" 557 " (input x);\n" 558 " generate\n" 559 " endgenerate\n" 560 "endfunction : x"); 561 } 562 563 TEST_F(FormatTestVerilog, If) { 564 verifyFormat("if (x)\n" 565 " x = x;"); 566 verifyFormat("unique if (x)\n" 567 " x = x;"); 568 verifyFormat("unique0 if (x)\n" 569 " x = x;"); 570 verifyFormat("priority if (x)\n" 571 " x = x;"); 572 verifyFormat("if (x)\n" 573 " x = x;\n" 574 "x = x;"); 575 576 // Test else 577 verifyFormat("if (x)\n" 578 " x = x;\n" 579 "else if (x)\n" 580 " x = x;\n" 581 "else\n" 582 " x = x;"); 583 verifyFormat("if (x) begin\n" 584 " x = x;\n" 585 "end else if (x) begin\n" 586 " x = x;\n" 587 "end else begin\n" 588 " x = x;\n" 589 "end"); 590 verifyFormat("if (x) begin : x\n" 591 " x = x;\n" 592 "end : x else if (x) begin : x\n" 593 " x = x;\n" 594 "end : x else begin : x\n" 595 " x = x;\n" 596 "end : x"); 597 598 // Test block keywords. 599 verifyFormat("if (x) begin\n" 600 " x = x;\n" 601 "end"); 602 verifyFormat("if (x) begin : x\n" 603 " x = x;\n" 604 "end : x"); 605 verifyFormat("if (x) begin\n" 606 " x = x;\n" 607 " x = x;\n" 608 "end"); 609 verifyFormat("if (x) fork\n" 610 " x = x;\n" 611 "join"); 612 verifyFormat("if (x) fork\n" 613 " x = x;\n" 614 "join_any"); 615 verifyFormat("if (x) fork\n" 616 " x = x;\n" 617 "join_none"); 618 verifyFormat("if (x) generate\n" 619 " x = x;\n" 620 "endgenerate"); 621 verifyFormat("if (x) generate : x\n" 622 " x = x;\n" 623 "endgenerate : x"); 624 625 // Test that concatenation braces don't get regarded as blocks. 626 verifyFormat("if (x)\n" 627 " {x} = x;"); 628 verifyFormat("if (x)\n" 629 " x = {x};"); 630 verifyFormat("if (x)\n" 631 " x = {x};\n" 632 "else\n" 633 " {x} = {x};"); 634 635 // With attributes. 636 verifyFormat("(* x *) if (x)\n" 637 " x = x;"); 638 verifyFormat("(* x = \"x\" *) if (x)\n" 639 " x = x;"); 640 verifyFormat("(* x, x = \"x\" *) if (x)\n" 641 " x = x;"); 642 } 643 644 TEST_F(FormatTestVerilog, Operators) { 645 // Test that unary operators are not followed by space. 646 verifyFormat("x = +x;"); 647 verifyFormat("x = -x;"); 648 verifyFormat("x = !x;"); 649 verifyFormat("x = ~x;"); 650 verifyFormat("x = &x;"); 651 verifyFormat("x = ~&x;"); 652 verifyFormat("x = |x;"); 653 verifyFormat("x = ~|x;"); 654 verifyFormat("x = ^x;"); 655 verifyFormat("x = ~^x;"); 656 verifyFormat("x = ^~x;"); 657 verifyFormat("x = ++x;"); 658 verifyFormat("x = --x;"); 659 660 // Test that operators don't get split. 661 verifyFormat("x = x++;"); 662 verifyFormat("x = x--;"); 663 verifyFormat("x = x ** x;"); 664 verifyFormat("x = x << x;"); 665 verifyFormat("x = x >> x;"); 666 verifyFormat("x = x <<< x;"); 667 verifyFormat("x = x >>> x;"); 668 verifyFormat("x = x <= x;"); 669 verifyFormat("x = x >= x;"); 670 verifyFormat("x = x == x;"); 671 verifyFormat("x = x != x;"); 672 verifyFormat("x = x === x;"); 673 verifyFormat("x = x !== x;"); 674 verifyFormat("x = x ==? x;"); 675 verifyFormat("x = x !=? x;"); 676 verifyFormat("x = x ~^ x;"); 677 verifyFormat("x = x ^~ x;"); 678 verifyFormat("x = x && x;"); 679 verifyFormat("x = x || x;"); 680 verifyFormat("x = x->x;"); 681 verifyFormat("x = x <-> x;"); 682 verifyFormat("x += x;"); 683 verifyFormat("x -= x;"); 684 verifyFormat("x *= x;"); 685 verifyFormat("x /= x;"); 686 verifyFormat("x %= x;"); 687 verifyFormat("x &= x;"); 688 verifyFormat("x ^= x;"); 689 verifyFormat("x |= x;"); 690 verifyFormat("x <<= x;"); 691 verifyFormat("x >>= x;"); 692 verifyFormat("x <<<= x;"); 693 verifyFormat("x >>>= x;"); 694 verifyFormat("x <= x;"); 695 696 // Test that space is added between operators. 697 EXPECT_EQ("x = x < -x;", format("x=x<-x;")); 698 EXPECT_EQ("x = x << -x;", format("x=x<<-x;")); 699 EXPECT_EQ("x = x <<< -x;", format("x=x<<<-x;")); 700 } 701 702 TEST_F(FormatTestVerilog, Preprocessor) { 703 auto Style = getLLVMStyle(FormatStyle::LK_Verilog); 704 Style.ColumnLimit = 20; 705 706 // Macro definitions. 707 EXPECT_EQ("`define X \\\n" 708 " if (x) \\\n" 709 " x = x;", 710 format("`define X if(x)x=x;", Style)); 711 EXPECT_EQ("`define X(x) \\\n" 712 " if (x) \\\n" 713 " x = x;", 714 format("`define X(x) if(x)x=x;", Style)); 715 EXPECT_EQ("`define X \\\n" 716 " x = x; \\\n" 717 " x = x;", 718 format("`define X x=x;x=x;", Style)); 719 // Macro definitions with invocations inside. 720 EXPECT_EQ("`define LIST \\\n" 721 " `ENTRY \\\n" 722 " `ENTRY", 723 format("`define LIST \\\n" 724 "`ENTRY \\\n" 725 "`ENTRY", 726 Style)); 727 EXPECT_EQ("`define LIST \\\n" 728 " `x = `x; \\\n" 729 " `x = `x;", 730 format("`define LIST \\\n" 731 "`x = `x; \\\n" 732 "`x = `x;", 733 Style)); 734 EXPECT_EQ("`define LIST \\\n" 735 " `x = `x; \\\n" 736 " `x = `x;", 737 format("`define LIST `x=`x;`x=`x;", Style)); 738 // Macro invocations. 739 verifyFormat("`x = (`x1 + `x2 + x);"); 740 // Lines starting with a preprocessor directive should not be indented. 741 std::string Directives[] = { 742 "begin_keywords", 743 "celldefine", 744 "default_nettype", 745 "define", 746 "else", 747 "elsif", 748 "end_keywords", 749 "endcelldefine", 750 "endif", 751 "ifdef", 752 "ifndef", 753 "include", 754 "line", 755 "nounconnected_drive", 756 "pragma", 757 "resetall", 758 "timescale", 759 "unconnected_drive", 760 "undef", 761 "undefineall", 762 }; 763 for (auto &Name : Directives) { 764 EXPECT_EQ("if (x)\n" 765 "`" + 766 Name + 767 "\n" 768 " ;", 769 format("if (x)\n" 770 "`" + 771 Name + 772 "\n" 773 ";", 774 Style)); 775 } 776 // Lines starting with a regular macro invocation should be indented as a 777 // normal line. 778 EXPECT_EQ("if (x)\n" 779 " `x = `x;\n" 780 "`timescale 1ns / 1ps", 781 format("if (x)\n" 782 "`x = `x;\n" 783 "`timescale 1ns / 1ps", 784 Style)); 785 EXPECT_EQ("if (x)\n" 786 "`timescale 1ns / 1ps\n" 787 " `x = `x;", 788 format("if (x)\n" 789 "`timescale 1ns / 1ps\n" 790 "`x = `x;", 791 Style)); 792 std::string NonDirectives[] = { 793 // For `__FILE__` and `__LINE__`, although the standard classifies them as 794 // preprocessor directives, they are used like regular macros. 795 "__FILE__", "__LINE__", "elif", "foo", "x", 796 }; 797 for (auto &Name : NonDirectives) { 798 EXPECT_EQ("if (x)\n" 799 " `" + 800 Name + ";", 801 format("if (x)\n" 802 "`" + 803 Name + 804 "\n" 805 ";", 806 Style)); 807 } 808 } 809 810 TEST_F(FormatTestVerilog, Primitive) { 811 verifyFormat("primitive multiplexer\n" 812 " (mux, control, dataA, dataB);\n" 813 " output mux;\n" 814 " input control, dataA, dataB;\n" 815 " table\n" 816 " 0 1 ? : 1;\n" 817 " 0 0 ? : 0;\n" 818 " 1 ? 1 : 1;\n" 819 " 1 ? 0 : 0;\n" 820 " x 0 0 : 0;\n" 821 " x 1 1 : 1;\n" 822 " endtable\n" 823 "endprimitive"); 824 verifyFormat("primitive latch\n" 825 " (q, ena_, data);\n" 826 " output q;\n" 827 " reg q;\n" 828 " input ena_, data;\n" 829 " table\n" 830 " 0 1 : ? : 1;\n" 831 " 0 0 : ? : 0;\n" 832 " 1 ? : ? : -;\n" 833 " ? * : ? : -;\n" 834 " endtable\n" 835 "endprimitive"); 836 verifyFormat("primitive d\n" 837 " (q, clock, data);\n" 838 " output q;\n" 839 " reg q;\n" 840 " input clock, data;\n" 841 " table\n" 842 " (01) 0 : ? : 0;\n" 843 " (01) 1 : ? : 1;\n" 844 " (0?) 1 : 1 : 1;\n" 845 " (0?) 0 : 0 : 0;\n" 846 " (?0) ? : ? : -;\n" 847 " (?\?) ? : ? : -;\n" 848 " endtable\n" 849 "endprimitive"); 850 } 851 852 TEST_F(FormatTestVerilog, StructuredProcedure) { 853 // Blocks should be indented correctly. 854 verifyFormat("initial begin\n" 855 "end"); 856 verifyFormat("initial begin\n" 857 " x <= x;\n" 858 " x <= x;\n" 859 "end"); 860 verifyFormat("initial\n" 861 " x <= x;\n" 862 "x <= x;"); 863 verifyFormat("always @(x) begin\n" 864 "end"); 865 verifyFormat("always @(x) begin\n" 866 " x <= x;\n" 867 " x <= x;\n" 868 "end"); 869 verifyFormat("always @(x)\n" 870 " x <= x;\n" 871 "x <= x;"); 872 // Various keywords. 873 verifyFormat("always @(x)\n" 874 " x <= x;"); 875 verifyFormat("always @(posedge x)\n" 876 " x <= x;"); 877 verifyFormat("always\n" 878 " x <= x;"); 879 verifyFormat("always @*\n" 880 " x <= x;"); 881 verifyFormat("always @(*)\n" 882 " x <= x;"); 883 verifyFormat("always_comb\n" 884 " x <= x;"); 885 verifyFormat("always_latch @(x)\n" 886 " x <= x;"); 887 verifyFormat("always_ff @(posedge x)\n" 888 " x <= x;"); 889 verifyFormat("initial\n" 890 " x <= x;"); 891 verifyFormat("final\n" 892 " x <= x;"); 893 verifyFormat("forever\n" 894 " x <= x;"); 895 } 896 } // namespace format 897 } // end namespace clang 898