1 //===- unittest/Format/FormatTestVerilog.cpp ------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "FormatTestUtils.h" 10 #include "clang/Format/Format.h" 11 #include "llvm/Support/Debug.h" 12 #include "gtest/gtest.h" 13 14 #define DEBUG_TYPE "format-test" 15 16 namespace clang { 17 namespace format { 18 19 class FormatTestVerilog : public ::testing::Test { 20 protected: 21 static std::string format(llvm::StringRef Code, unsigned Offset, 22 unsigned Length, const FormatStyle &Style) { 23 LLVM_DEBUG(llvm::errs() << "---\n"); 24 LLVM_DEBUG(llvm::errs() << Code << "\n\n"); 25 std::vector<tooling::Range> Ranges(1, tooling::Range(Offset, Length)); 26 tooling::Replacements Replaces = reformat(Style, Code, Ranges); 27 auto Result = applyAllReplacements(Code, Replaces); 28 EXPECT_TRUE(static_cast<bool>(Result)); 29 LLVM_DEBUG(llvm::errs() << "\n" << *Result << "\n\n"); 30 return *Result; 31 } 32 33 static std::string 34 format(llvm::StringRef Code, 35 const FormatStyle &Style = getLLVMStyle(FormatStyle::LK_Verilog)) { 36 return format(Code, 0, Code.size(), Style); 37 } 38 39 static void verifyFormat( 40 llvm::StringRef Code, 41 const FormatStyle &Style = getLLVMStyle(FormatStyle::LK_Verilog)) { 42 EXPECT_EQ(Code.str(), format(Code, Style)) << "Expected code is not stable"; 43 EXPECT_EQ(Code.str(), 44 format(test::messUp(Code, /*HandleHash=*/false), Style)); 45 } 46 }; 47 48 TEST_F(FormatTestVerilog, Align) { 49 FormatStyle Style = getLLVMStyle(FormatStyle::LK_Verilog); 50 Style.AlignConsecutiveAssignments.Enabled = true; 51 verifyFormat("x <= x;\n" 52 "sfdbddfbdfbb <= x;\n" 53 "x = x;", 54 Style); 55 verifyFormat("x = x;\n" 56 "sfdbddfbdfbb = x;\n" 57 "x = x;", 58 Style); 59 // Compound assignments are not aligned by default. '<=' is not a compound 60 // assignment. 61 verifyFormat("x <= x;\n" 62 "sfdbddfbdfbb <= x;", 63 Style); 64 verifyFormat("x += x;\n" 65 "sfdbddfbdfbb <= x;", 66 Style); 67 verifyFormat("x <<= x;\n" 68 "sfdbddfbdfbb <= x;", 69 Style); 70 verifyFormat("x <<<= x;\n" 71 "sfdbddfbdfbb <= x;", 72 Style); 73 verifyFormat("x >>= x;\n" 74 "sfdbddfbdfbb <= x;", 75 Style); 76 verifyFormat("x >>>= x;\n" 77 "sfdbddfbdfbb <= x;", 78 Style); 79 Style.AlignConsecutiveAssignments.AlignCompound = true; 80 verifyFormat("x <= x;\n" 81 "sfdbddfbdfbb <= x;", 82 Style); 83 verifyFormat("x += x;\n" 84 "sfdbddfbdfbb <= x;", 85 Style); 86 verifyFormat("x <<= x;\n" 87 "sfdbddfbdfbb <= x;", 88 Style); 89 verifyFormat("x <<<= x;\n" 90 "sfdbddfbdfbb <= x;", 91 Style); 92 verifyFormat("x >>= x;\n" 93 "sfdbddfbdfbb <= x;", 94 Style); 95 verifyFormat("x >>>= x;\n" 96 "sfdbddfbdfbb <= x;", 97 Style); 98 } 99 100 TEST_F(FormatTestVerilog, BasedLiteral) { 101 verifyFormat("x = '0;"); 102 verifyFormat("x = '1;"); 103 verifyFormat("x = 'X;"); 104 verifyFormat("x = 'x;"); 105 verifyFormat("x = 'Z;"); 106 verifyFormat("x = 'z;"); 107 verifyFormat("x = 659;"); 108 verifyFormat("x = 'h837ff;"); 109 verifyFormat("x = 'o7460;"); 110 verifyFormat("x = 4'b1001;"); 111 verifyFormat("x = 5'D3;"); 112 verifyFormat("x = 3'b01x;"); 113 verifyFormat("x = 12'hx;"); 114 verifyFormat("x = 16'hz;"); 115 verifyFormat("x = -8'd6;"); 116 verifyFormat("x = 4'shf;"); 117 verifyFormat("x = -4'sd15;"); 118 verifyFormat("x = 16'sd?;"); 119 } 120 121 TEST_F(FormatTestVerilog, Block) { 122 verifyFormat("begin\n" 123 " x = x;\n" 124 "end"); 125 verifyFormat("begin : x\n" 126 " x = x;\n" 127 "end : x"); 128 verifyFormat("begin\n" 129 " x = x;\n" 130 " x = x;\n" 131 "end"); 132 verifyFormat("fork\n" 133 " x = x;\n" 134 "join"); 135 verifyFormat("fork\n" 136 " x = x;\n" 137 "join_any"); 138 verifyFormat("fork\n" 139 " x = x;\n" 140 "join_none"); 141 verifyFormat("generate\n" 142 " x = x;\n" 143 "endgenerate"); 144 verifyFormat("generate : x\n" 145 " x = x;\n" 146 "endgenerate : x"); 147 // Nested blocks. 148 verifyFormat("begin\n" 149 " begin\n" 150 " end\n" 151 "end"); 152 verifyFormat("begin : x\n" 153 " begin\n" 154 " end\n" 155 "end : x"); 156 verifyFormat("begin : x\n" 157 " begin : x\n" 158 " end : x\n" 159 "end : x"); 160 verifyFormat("begin\n" 161 " begin : x\n" 162 " end : x\n" 163 "end"); 164 // Test that 'disable fork' and 'rand join' don't get mistaken as blocks. 165 verifyFormat("disable fork;\n" 166 "x = x;"); 167 verifyFormat("rand join x x;\n" 168 "x = x;"); 169 } 170 171 TEST_F(FormatTestVerilog, Case) { 172 verifyFormat("case (data)\n" 173 "endcase"); 174 verifyFormat("casex (data)\n" 175 "endcase"); 176 verifyFormat("casez (data)\n" 177 "endcase"); 178 verifyFormat("case (data) inside\n" 179 "endcase"); 180 verifyFormat("case (data)\n" 181 " 16'd0:\n" 182 " result = 10'b0111111111;\n" 183 "endcase"); 184 verifyFormat("case (data)\n" 185 " xxxxxxxx:\n" 186 " result = 10'b0111111111;\n" 187 "endcase"); 188 // Test labels with multiple options. 189 verifyFormat("case (data)\n" 190 " 16'd0, 16'd1:\n" 191 " result = 10'b0111111111;\n" 192 "endcase"); 193 verifyFormat("case (data)\n" 194 " 16'd0, //\n" 195 " 16'd1:\n" 196 " result = 10'b0111111111;\n" 197 "endcase"); 198 // Test that blocks following labels are indented. 199 verifyFormat("case (data)\n" 200 " 16'd1: fork\n" 201 " result = 10'b1011111111;\n" 202 " join\n" 203 "endcase\n"); 204 verifyFormat("case (data)\n" 205 " 16'd1: fork : x\n" 206 " result = 10'b1011111111;\n" 207 " join : x\n" 208 "endcase\n"); 209 // Test default. 210 verifyFormat("case (data)\n" 211 " default\n" 212 " result = 10'b1011111111;\n" 213 "endcase"); 214 verifyFormat("case (data)\n" 215 " default:\n" 216 " result = 10'b1011111111;\n" 217 "endcase"); 218 // Test that question marks and colons don't get mistaken as labels. 219 verifyFormat("case (data)\n" 220 " 8'b1???????:\n" 221 " instruction1(ir);\n" 222 "endcase"); 223 verifyFormat("case (data)\n" 224 " x ? 8'b1??????? : 1:\n" 225 " instruction3(ir);\n" 226 "endcase"); 227 // Test indention options. 228 auto Style = getLLVMStyle(FormatStyle::LK_Verilog); 229 Style.IndentCaseLabels = false; 230 verifyFormat("case (data)\n" 231 "16'd0:\n" 232 " result = 10'b0111111111;\n" 233 "endcase", 234 Style); 235 verifyFormat("case (data)\n" 236 "16'd0: begin\n" 237 " result = 10'b0111111111;\n" 238 "end\n" 239 "endcase", 240 Style); 241 Style.IndentCaseLabels = true; 242 verifyFormat("case (data)\n" 243 " 16'd0:\n" 244 " result = 10'b0111111111;\n" 245 "endcase", 246 Style); 247 verifyFormat("case (data)\n" 248 " 16'd0: begin\n" 249 " result = 10'b0111111111;\n" 250 " end\n" 251 "endcase", 252 Style); 253 } 254 255 TEST_F(FormatTestVerilog, Coverage) { 256 verifyFormat("covergroup x\n" 257 " @@(begin x);\n" 258 "endgroup"); 259 } 260 261 TEST_F(FormatTestVerilog, Declaration) { 262 verifyFormat("wire mynet;"); 263 verifyFormat("wire mynet, mynet1;"); 264 verifyFormat("wire mynet, //\n" 265 " mynet1;"); 266 verifyFormat("wire mynet = enable;"); 267 verifyFormat("wire mynet = enable, mynet1;"); 268 verifyFormat("wire mynet = enable, //\n" 269 " mynet1;"); 270 verifyFormat("wire mynet, mynet1 = enable;"); 271 verifyFormat("wire mynet, //\n" 272 " mynet1 = enable;"); 273 verifyFormat("wire mynet = enable, mynet1 = enable;"); 274 verifyFormat("wire mynet = enable, //\n" 275 " mynet1 = enable;"); 276 verifyFormat("wire (strong1, pull0) mynet;"); 277 verifyFormat("wire (strong1, pull0) mynet, mynet1;"); 278 verifyFormat("wire (strong1, pull0) mynet, //\n" 279 " mynet1;"); 280 verifyFormat("wire (strong1, pull0) mynet = enable;"); 281 verifyFormat("wire (strong1, pull0) mynet = enable, mynet1;"); 282 verifyFormat("wire (strong1, pull0) mynet = enable, //\n" 283 " mynet1;"); 284 verifyFormat("wire (strong1, pull0) mynet, mynet1 = enable;"); 285 verifyFormat("wire (strong1, pull0) mynet, //\n" 286 " mynet1 = enable;"); 287 } 288 289 TEST_F(FormatTestVerilog, Delay) { 290 // Delay by the default unit. 291 verifyFormat("#0;"); 292 verifyFormat("#1;"); 293 verifyFormat("#10;"); 294 verifyFormat("#1.5;"); 295 // Explicit unit. 296 verifyFormat("#1fs;"); 297 verifyFormat("#1.5fs;"); 298 verifyFormat("#1ns;"); 299 verifyFormat("#1.5ns;"); 300 verifyFormat("#1us;"); 301 verifyFormat("#1.5us;"); 302 verifyFormat("#1ms;"); 303 verifyFormat("#1.5ms;"); 304 verifyFormat("#1s;"); 305 verifyFormat("#1.5s;"); 306 // The following expression should be on the same line. 307 verifyFormat("#1 x = x;"); 308 EXPECT_EQ("#1 x = x;", format("#1\n" 309 "x = x;")); 310 } 311 312 TEST_F(FormatTestVerilog, Headers) { 313 // Test headers with multiple ports. 314 verifyFormat("module mh1\n" 315 " (input var int in1,\n" 316 " input var shortreal in2,\n" 317 " output tagged_st out);\n" 318 "endmodule"); 319 // Ports should be grouped by types. 320 verifyFormat("module test\n" 321 " (input [7 : 0] a,\n" 322 " input signed [7 : 0] b, c, d);\n" 323 "endmodule"); 324 verifyFormat("module test\n" 325 " (input [7 : 0] a,\n" 326 " (* x = x *) input signed [7 : 0] b, c, d);\n" 327 "endmodule"); 328 verifyFormat("module test\n" 329 " (input [7 : 0] a = 0,\n" 330 " input signed [7 : 0] b = 0, c = 0, d = 0);\n" 331 "endmodule"); 332 verifyFormat("module test\n" 333 " #(parameter x)\n" 334 " (input [7 : 0] a,\n" 335 " input signed [7 : 0] b, c, d);\n" 336 "endmodule"); 337 // When a line needs to be broken, ports of the same type should be aligned to 338 // the same column. 339 verifyFormat("module test\n" 340 " (input signed [7 : 0] b, c, //\n" 341 " d);\n" 342 "endmodule"); 343 verifyFormat("module test\n" 344 " ((* x = x *) input signed [7 : 0] b, c, //\n" 345 " d);\n" 346 "endmodule"); 347 verifyFormat("module test\n" 348 " (input signed [7 : 0] b = 0, c, //\n" 349 " d);\n" 350 "endmodule"); 351 verifyFormat("module test\n" 352 " (input signed [7 : 0] b, c = 0, //\n" 353 " d);\n" 354 "endmodule"); 355 verifyFormat("module test\n" 356 " (input signed [7 : 0] b, c, //\n" 357 " d = 0);\n" 358 "endmodule"); 359 verifyFormat("module test\n" 360 " (input wire logic signed [7 : 0][0 : 1] b, c, //\n" 361 " d);\n" 362 "endmodule"); 363 verifyFormat("module test\n" 364 " (input signed [7 : 0] b, //\n" 365 " c, //\n" 366 " d);\n" 367 "endmodule"); 368 verifyFormat("module test\n" 369 " (input [7 : 0] a,\n" 370 " input signed [7 : 0] b, //\n" 371 " c, //\n" 372 " d);\n" 373 "endmodule"); 374 verifyFormat("module test\n" 375 " (input signed [7 : 0] b, //\n" 376 " c, //\n" 377 " d,\n" 378 " output signed [7 : 0] h);\n" 379 "endmodule"); 380 // With a modport. 381 verifyFormat("module m\n" 382 " (i2.master i);\n" 383 "endmodule"); 384 verifyFormat("module m\n" 385 " (i2.master i, ii);\n" 386 "endmodule"); 387 verifyFormat("module m\n" 388 " (i2.master i, //\n" 389 " ii);\n" 390 "endmodule"); 391 verifyFormat("module m\n" 392 " (i2.master i,\n" 393 " input ii);\n" 394 "endmodule"); 395 verifyFormat("module m\n" 396 " (i2::i2.master i);\n" 397 "endmodule"); 398 verifyFormat("module m\n" 399 " (i2::i2.master i, ii);\n" 400 "endmodule"); 401 verifyFormat("module m\n" 402 " (i2::i2.master i, //\n" 403 " ii);\n" 404 "endmodule"); 405 verifyFormat("module m\n" 406 " (i2::i2.master i,\n" 407 " input ii);\n" 408 "endmodule"); 409 verifyFormat("module m\n" 410 " (i2::i2 i);\n" 411 "endmodule"); 412 verifyFormat("module m\n" 413 " (i2::i2 i, ii);\n" 414 "endmodule"); 415 verifyFormat("module m\n" 416 " (i2::i2 i, //\n" 417 " ii);\n" 418 "endmodule"); 419 verifyFormat("module m\n" 420 " (i2::i2 i,\n" 421 " input ii);\n" 422 "endmodule"); 423 // With a macro in the names. 424 verifyFormat("module m\n" 425 " (input var `x a, b);\n" 426 "endmodule"); 427 verifyFormat("module m\n" 428 " (input var `x a, //\n" 429 " b);\n" 430 "endmodule"); 431 verifyFormat("module m\n" 432 " (input var x `a, b);\n" 433 "endmodule"); 434 verifyFormat("module m\n" 435 " (input var x `a, //\n" 436 " b);\n" 437 "endmodule"); 438 // With a concatenation in the names. 439 auto Style = getLLVMStyle(FormatStyle::LK_Verilog); 440 Style.ColumnLimit = 40; 441 verifyFormat("`define X(x) \\\n" 442 " module test \\\n" 443 " (input var x``x a, b);", 444 Style); 445 verifyFormat("`define X(x) \\\n" 446 " module test \\\n" 447 " (input var x``x aaaaaaaaaaaaaaa, \\\n" 448 " b);", 449 Style); 450 verifyFormat("`define X(x) \\\n" 451 " module test \\\n" 452 " (input var x a``x, b);", 453 Style); 454 verifyFormat("`define X(x) \\\n" 455 " module test \\\n" 456 " (input var x aaaaaaaaaaaaaaa``x, \\\n" 457 " b);", 458 Style); 459 } 460 461 TEST_F(FormatTestVerilog, Hierarchy) { 462 verifyFormat("module x;\n" 463 "endmodule"); 464 // Test that the end label is on the same line as the end keyword. 465 verifyFormat("module x;\n" 466 "endmodule : x"); 467 // Test that things inside are indented. 468 verifyFormat("module x;\n" 469 " generate\n" 470 " endgenerate\n" 471 "endmodule"); 472 verifyFormat("program x;\n" 473 " generate\n" 474 " endgenerate\n" 475 "endprogram"); 476 verifyFormat("interface x;\n" 477 " generate\n" 478 " endgenerate\n" 479 "endinterface"); 480 verifyFormat("task x;\n" 481 " generate\n" 482 " endgenerate\n" 483 "endtask"); 484 verifyFormat("function x;\n" 485 " generate\n" 486 " endgenerate\n" 487 "endfunction"); 488 verifyFormat("class x;\n" 489 " generate\n" 490 " endgenerate\n" 491 "endclass"); 492 // Test that they nest. 493 verifyFormat("module x;\n" 494 " program x;\n" 495 " program x;\n" 496 " endprogram\n" 497 " endprogram\n" 498 "endmodule"); 499 // Test that an extern declaration doesn't change the indentation. 500 verifyFormat("extern module x;\n" 501 "x = x;"); 502 // Test complex headers 503 verifyFormat("extern module x\n" 504 " import x.x::x::*;\n" 505 " import x;\n" 506 " #(parameter x)\n" 507 " (output x);"); 508 verifyFormat("module x\n" 509 " import x.x::x::*;\n" 510 " import x;\n" 511 " #(parameter x)\n" 512 " (output x);\n" 513 " generate\n" 514 " endgenerate\n" 515 "endmodule : x"); 516 verifyFormat("virtual class x\n" 517 " (x)\n" 518 " extends x(x)\n" 519 " implements x, x, x;\n" 520 " generate\n" 521 " endgenerate\n" 522 "endclass : x\n"); 523 verifyFormat("function automatic logic [1 : 0] x\n" 524 " (input x);\n" 525 " generate\n" 526 " endgenerate\n" 527 "endfunction : x"); 528 } 529 530 TEST_F(FormatTestVerilog, If) { 531 verifyFormat("if (x)\n" 532 " x = x;"); 533 verifyFormat("unique if (x)\n" 534 " x = x;"); 535 verifyFormat("unique0 if (x)\n" 536 " x = x;"); 537 verifyFormat("priority if (x)\n" 538 " x = x;"); 539 verifyFormat("if (x)\n" 540 " x = x;\n" 541 "x = x;"); 542 543 // Test else 544 verifyFormat("if (x)\n" 545 " x = x;\n" 546 "else if (x)\n" 547 " x = x;\n" 548 "else\n" 549 " x = x;"); 550 verifyFormat("if (x) begin\n" 551 " x = x;\n" 552 "end else if (x) begin\n" 553 " x = x;\n" 554 "end else begin\n" 555 " x = x;\n" 556 "end"); 557 verifyFormat("if (x) begin : x\n" 558 " x = x;\n" 559 "end : x else if (x) begin : x\n" 560 " x = x;\n" 561 "end : x else begin : x\n" 562 " x = x;\n" 563 "end : x"); 564 565 // Test block keywords. 566 verifyFormat("if (x) begin\n" 567 " x = x;\n" 568 "end"); 569 verifyFormat("if (x) begin : x\n" 570 " x = x;\n" 571 "end : x"); 572 verifyFormat("if (x) begin\n" 573 " x = x;\n" 574 " x = x;\n" 575 "end"); 576 verifyFormat("if (x) fork\n" 577 " x = x;\n" 578 "join"); 579 verifyFormat("if (x) fork\n" 580 " x = x;\n" 581 "join_any"); 582 verifyFormat("if (x) fork\n" 583 " x = x;\n" 584 "join_none"); 585 verifyFormat("if (x) generate\n" 586 " x = x;\n" 587 "endgenerate"); 588 verifyFormat("if (x) generate : x\n" 589 " x = x;\n" 590 "endgenerate : x"); 591 592 // Test that concatenation braces don't get regarded as blocks. 593 verifyFormat("if (x)\n" 594 " {x} = x;"); 595 verifyFormat("if (x)\n" 596 " x = {x};"); 597 verifyFormat("if (x)\n" 598 " x = {x};\n" 599 "else\n" 600 " {x} = {x};"); 601 602 // With attributes. 603 verifyFormat("(* x *) if (x)\n" 604 " x = x;"); 605 verifyFormat("(* x = \"x\" *) if (x)\n" 606 " x = x;"); 607 verifyFormat("(* x, x = \"x\" *) if (x)\n" 608 " x = x;"); 609 } 610 611 TEST_F(FormatTestVerilog, Operators) { 612 // Test that unary operators are not followed by space. 613 verifyFormat("x = +x;"); 614 verifyFormat("x = -x;"); 615 verifyFormat("x = !x;"); 616 verifyFormat("x = ~x;"); 617 verifyFormat("x = &x;"); 618 verifyFormat("x = ~&x;"); 619 verifyFormat("x = |x;"); 620 verifyFormat("x = ~|x;"); 621 verifyFormat("x = ^x;"); 622 verifyFormat("x = ~^x;"); 623 verifyFormat("x = ^~x;"); 624 verifyFormat("x = ++x;"); 625 verifyFormat("x = --x;"); 626 627 // Test that operators don't get split. 628 verifyFormat("x = x++;"); 629 verifyFormat("x = x--;"); 630 verifyFormat("x = x ** x;"); 631 verifyFormat("x = x << x;"); 632 verifyFormat("x = x >> x;"); 633 verifyFormat("x = x <<< x;"); 634 verifyFormat("x = x >>> x;"); 635 verifyFormat("x = x <= x;"); 636 verifyFormat("x = x >= x;"); 637 verifyFormat("x = x == x;"); 638 verifyFormat("x = x != x;"); 639 verifyFormat("x = x === x;"); 640 verifyFormat("x = x !== x;"); 641 verifyFormat("x = x ==? x;"); 642 verifyFormat("x = x !=? x;"); 643 verifyFormat("x = x ~^ x;"); 644 verifyFormat("x = x ^~ x;"); 645 verifyFormat("x = x && x;"); 646 verifyFormat("x = x || x;"); 647 verifyFormat("x = x->x;"); 648 verifyFormat("x = x <-> x;"); 649 verifyFormat("x += x;"); 650 verifyFormat("x -= x;"); 651 verifyFormat("x *= x;"); 652 verifyFormat("x /= x;"); 653 verifyFormat("x %= x;"); 654 verifyFormat("x &= x;"); 655 verifyFormat("x ^= x;"); 656 verifyFormat("x |= x;"); 657 verifyFormat("x <<= x;"); 658 verifyFormat("x >>= x;"); 659 verifyFormat("x <<<= x;"); 660 verifyFormat("x >>>= x;"); 661 verifyFormat("x <= x;"); 662 663 // Test that space is added between operators. 664 EXPECT_EQ("x = x < -x;", format("x=x<-x;")); 665 EXPECT_EQ("x = x << -x;", format("x=x<<-x;")); 666 EXPECT_EQ("x = x <<< -x;", format("x=x<<<-x;")); 667 } 668 669 TEST_F(FormatTestVerilog, Preprocessor) { 670 auto Style = getLLVMStyle(FormatStyle::LK_Verilog); 671 Style.ColumnLimit = 20; 672 673 // Macro definitions. 674 EXPECT_EQ("`define X \\\n" 675 " if (x) \\\n" 676 " x = x;", 677 format("`define X if(x)x=x;", Style)); 678 EXPECT_EQ("`define X(x) \\\n" 679 " if (x) \\\n" 680 " x = x;", 681 format("`define X(x) if(x)x=x;", Style)); 682 EXPECT_EQ("`define X \\\n" 683 " x = x; \\\n" 684 " x = x;", 685 format("`define X x=x;x=x;", Style)); 686 // Macro definitions with invocations inside. 687 EXPECT_EQ("`define LIST \\\n" 688 " `ENTRY \\\n" 689 " `ENTRY", 690 format("`define LIST \\\n" 691 "`ENTRY \\\n" 692 "`ENTRY", 693 Style)); 694 EXPECT_EQ("`define LIST \\\n" 695 " `x = `x; \\\n" 696 " `x = `x;", 697 format("`define LIST \\\n" 698 "`x = `x; \\\n" 699 "`x = `x;", 700 Style)); 701 EXPECT_EQ("`define LIST \\\n" 702 " `x = `x; \\\n" 703 " `x = `x;", 704 format("`define LIST `x=`x;`x=`x;", Style)); 705 // Macro invocations. 706 verifyFormat("`x = (`x1 + `x2 + x);"); 707 // Lines starting with a preprocessor directive should not be indented. 708 std::string Directives[] = { 709 "begin_keywords", 710 "celldefine", 711 "default_nettype", 712 "define", 713 "else", 714 "elsif", 715 "end_keywords", 716 "endcelldefine", 717 "endif", 718 "ifdef", 719 "ifndef", 720 "include", 721 "line", 722 "nounconnected_drive", 723 "pragma", 724 "resetall", 725 "timescale", 726 "unconnected_drive", 727 "undef", 728 "undefineall", 729 }; 730 for (auto &Name : Directives) { 731 EXPECT_EQ("if (x)\n" 732 "`" + 733 Name + 734 "\n" 735 " ;", 736 format("if (x)\n" 737 "`" + 738 Name + 739 "\n" 740 ";", 741 Style)); 742 } 743 // Lines starting with a regular macro invocation should be indented as a 744 // normal line. 745 EXPECT_EQ("if (x)\n" 746 " `x = `x;\n" 747 "`timescale 1ns / 1ps", 748 format("if (x)\n" 749 "`x = `x;\n" 750 "`timescale 1ns / 1ps", 751 Style)); 752 EXPECT_EQ("if (x)\n" 753 "`timescale 1ns / 1ps\n" 754 " `x = `x;", 755 format("if (x)\n" 756 "`timescale 1ns / 1ps\n" 757 "`x = `x;", 758 Style)); 759 std::string NonDirectives[] = { 760 // For `__FILE__` and `__LINE__`, although the standard classifies them as 761 // preprocessor directives, they are used like regular macros. 762 "__FILE__", "__LINE__", "elif", "foo", "x", 763 }; 764 for (auto &Name : NonDirectives) { 765 EXPECT_EQ("if (x)\n" 766 " `" + 767 Name + ";", 768 format("if (x)\n" 769 "`" + 770 Name + 771 "\n" 772 ";", 773 Style)); 774 } 775 } 776 777 TEST_F(FormatTestVerilog, Primitive) { 778 verifyFormat("primitive multiplexer\n" 779 " (mux, control, dataA, dataB);\n" 780 " output mux;\n" 781 " input control, dataA, dataB;\n" 782 " table\n" 783 " 0 1 ? : 1;\n" 784 " 0 0 ? : 0;\n" 785 " 1 ? 1 : 1;\n" 786 " 1 ? 0 : 0;\n" 787 " x 0 0 : 0;\n" 788 " x 1 1 : 1;\n" 789 " endtable\n" 790 "endprimitive"); 791 verifyFormat("primitive latch\n" 792 " (q, ena_, data);\n" 793 " output q;\n" 794 " reg q;\n" 795 " input ena_, data;\n" 796 " table\n" 797 " 0 1 : ? : 1;\n" 798 " 0 0 : ? : 0;\n" 799 " 1 ? : ? : -;\n" 800 " ? * : ? : -;\n" 801 " endtable\n" 802 "endprimitive"); 803 verifyFormat("primitive d\n" 804 " (q, clock, data);\n" 805 " output q;\n" 806 " reg q;\n" 807 " input clock, data;\n" 808 " table\n" 809 " (01) 0 : ? : 0;\n" 810 " (01) 1 : ? : 1;\n" 811 " (0?) 1 : 1 : 1;\n" 812 " (0?) 0 : 0 : 0;\n" 813 " (?0) ? : ? : -;\n" 814 " (?\?) ? : ? : -;\n" 815 " endtable\n" 816 "endprimitive"); 817 } 818 819 TEST_F(FormatTestVerilog, StructuredProcedure) { 820 // Blocks should be indented correctly. 821 verifyFormat("initial begin\n" 822 "end"); 823 verifyFormat("initial begin\n" 824 " x <= x;\n" 825 " x <= x;\n" 826 "end"); 827 verifyFormat("initial\n" 828 " x <= x;\n" 829 "x <= x;"); 830 verifyFormat("always @(x) begin\n" 831 "end"); 832 verifyFormat("always @(x) begin\n" 833 " x <= x;\n" 834 " x <= x;\n" 835 "end"); 836 verifyFormat("always @(x)\n" 837 " x <= x;\n" 838 "x <= x;"); 839 // Various keywords. 840 verifyFormat("always @(x)\n" 841 " x <= x;"); 842 verifyFormat("always @(posedge x)\n" 843 " x <= x;"); 844 verifyFormat("always\n" 845 " x <= x;"); 846 verifyFormat("always @*\n" 847 " x <= x;"); 848 verifyFormat("always @(*)\n" 849 " x <= x;"); 850 verifyFormat("always_comb\n" 851 " x <= x;"); 852 verifyFormat("always_latch @(x)\n" 853 " x <= x;"); 854 verifyFormat("always_ff @(posedge x)\n" 855 " x <= x;"); 856 verifyFormat("initial\n" 857 " x <= x;"); 858 verifyFormat("final\n" 859 " x <= x;"); 860 verifyFormat("forever\n" 861 " x <= x;"); 862 } 863 } // namespace format 864 } // end namespace clang 865