1 //===- unittest/Format/FormatTestVerilog.cpp ------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "FormatTestBase.h" 10 11 #define DEBUG_TYPE "format-test" 12 13 namespace clang { 14 namespace format { 15 namespace test { 16 namespace { 17 class FormatTestVerilog : public test::FormatTestBase { 18 protected: 19 FormatStyle getDefaultStyle() const override { 20 return getLLVMStyle(FormatStyle::LK_Verilog); 21 } 22 std::string messUp(llvm::StringRef Code) const override { 23 return test::messUp(Code, /*HandleHash=*/false); 24 } 25 }; 26 27 TEST_F(FormatTestVerilog, Align) { 28 FormatStyle Style = getDefaultStyle(); 29 Style.AlignConsecutiveAssignments.Enabled = true; 30 verifyFormat("x <= x;\n" 31 "sfdbddfbdfbb <= x;\n" 32 "x = x;", 33 Style); 34 verifyFormat("x = x;\n" 35 "sfdbddfbdfbb = x;\n" 36 "x = x;", 37 Style); 38 // Compound assignments are not aligned by default. '<=' is not a compound 39 // assignment. 40 verifyFormat("x <= x;\n" 41 "sfdbddfbdfbb <= x;", 42 Style); 43 verifyFormat("x += x;\n" 44 "sfdbddfbdfbb <= x;", 45 Style); 46 verifyFormat("x <<= x;\n" 47 "sfdbddfbdfbb <= x;", 48 Style); 49 verifyFormat("x <<<= x;\n" 50 "sfdbddfbdfbb <= x;", 51 Style); 52 verifyFormat("x >>= x;\n" 53 "sfdbddfbdfbb <= x;", 54 Style); 55 verifyFormat("x >>>= x;\n" 56 "sfdbddfbdfbb <= x;", 57 Style); 58 Style.AlignConsecutiveAssignments.AlignCompound = true; 59 verifyFormat("x <= x;\n" 60 "sfdbddfbdfbb <= x;", 61 Style); 62 verifyFormat("x += x;\n" 63 "sfdbddfbdfbb <= x;", 64 Style); 65 verifyFormat("x <<= x;\n" 66 "sfdbddfbdfbb <= x;", 67 Style); 68 verifyFormat("x <<<= x;\n" 69 "sfdbddfbdfbb <= x;", 70 Style); 71 verifyFormat("x >>= x;\n" 72 "sfdbddfbdfbb <= x;", 73 Style); 74 verifyFormat("x >>>= x;\n" 75 "sfdbddfbdfbb <= x;", 76 Style); 77 } 78 79 TEST_F(FormatTestVerilog, Assign) { 80 verifyFormat("assign mynet = enable;"); 81 verifyFormat("assign (strong1, pull0) #1 mynet = enable;"); 82 verifyFormat("assign #1 mynet = enable;"); 83 verifyFormat("assign mynet = enable;"); 84 // Test that assignments are on separate lines. 85 verifyFormat("assign mynet = enable,\n" 86 " mynet1 = enable1;"); 87 // Test that `<=` and `,` don't confuse it. 88 verifyFormat("assign mynet = enable1 <= enable2;"); 89 verifyFormat("assign mynet = enable1 <= enable2,\n" 90 " mynet1 = enable3;"); 91 verifyFormat("assign mynet = enable,\n" 92 " mynet1 = enable2 <= enable3;"); 93 verifyFormat("assign mynet = enable(enable1, enable2);"); 94 } 95 96 TEST_F(FormatTestVerilog, BasedLiteral) { 97 verifyFormat("x = '0;"); 98 verifyFormat("x = '1;"); 99 verifyFormat("x = 'X;"); 100 verifyFormat("x = 'x;"); 101 verifyFormat("x = 'Z;"); 102 verifyFormat("x = 'z;"); 103 verifyFormat("x = 659;"); 104 verifyFormat("x = 'h837ff;"); 105 verifyFormat("x = 'o7460;"); 106 verifyFormat("x = 4'b1001;"); 107 verifyFormat("x = 5'D3;"); 108 verifyFormat("x = 3'b01x;"); 109 verifyFormat("x = 12'hx;"); 110 verifyFormat("x = 16'hz;"); 111 verifyFormat("x = -8'd6;"); 112 verifyFormat("x = 4'shf;"); 113 verifyFormat("x = -4'sd15;"); 114 verifyFormat("x = 16'sd?;"); 115 } 116 117 TEST_F(FormatTestVerilog, Block) { 118 verifyFormat("begin\n" 119 " x = x;\n" 120 "end"); 121 verifyFormat("begin : x\n" 122 " x = x;\n" 123 "end : x"); 124 verifyFormat("begin\n" 125 " x = x;\n" 126 " x = x;\n" 127 "end"); 128 verifyFormat("fork\n" 129 " x = x;\n" 130 "join"); 131 verifyFormat("fork\n" 132 " x = x;\n" 133 "join_any"); 134 verifyFormat("fork\n" 135 " x = x;\n" 136 "join_none"); 137 verifyFormat("generate\n" 138 " x = x;\n" 139 "endgenerate"); 140 verifyFormat("generate : x\n" 141 " x = x;\n" 142 "endgenerate : x"); 143 // Nested blocks. 144 verifyFormat("begin\n" 145 " begin\n" 146 " end\n" 147 "end"); 148 verifyFormat("begin : x\n" 149 " begin\n" 150 " end\n" 151 "end : x"); 152 verifyFormat("begin : x\n" 153 " begin : x\n" 154 " end : x\n" 155 "end : x"); 156 verifyFormat("begin\n" 157 " begin : x\n" 158 " end : x\n" 159 "end"); 160 // Test that 'disable fork' and 'rand join' don't get mistaken as blocks. 161 verifyFormat("disable fork;\n" 162 "x = x;"); 163 verifyFormat("rand join x x;\n" 164 "x = x;"); 165 } 166 167 TEST_F(FormatTestVerilog, Case) { 168 verifyFormat("case (data)\n" 169 "endcase"); 170 verifyFormat("casex (data)\n" 171 "endcase"); 172 verifyFormat("casez (data)\n" 173 "endcase"); 174 verifyFormat("case (data) inside\n" 175 "endcase"); 176 verifyFormat("case (data)\n" 177 " 16'd0:\n" 178 " result = 10'b0111111111;\n" 179 "endcase"); 180 verifyFormat("case (data)\n" 181 " xxxxxxxx:\n" 182 " result = 10'b0111111111;\n" 183 "endcase"); 184 // Test labels with multiple options. 185 verifyFormat("case (data)\n" 186 " 16'd0, 16'd1:\n" 187 " result = 10'b0111111111;\n" 188 "endcase"); 189 verifyFormat("case (data)\n" 190 " 16'd0, //\n" 191 " 16'd1:\n" 192 " result = 10'b0111111111;\n" 193 "endcase"); 194 // Test that blocks following labels are indented. 195 verifyFormat("case (data)\n" 196 " 16'd1: fork\n" 197 " result = 10'b1011111111;\n" 198 " join\n" 199 "endcase\n"); 200 verifyFormat("case (data)\n" 201 " 16'd1: fork : x\n" 202 " result = 10'b1011111111;\n" 203 " join : x\n" 204 "endcase\n"); 205 // Test default. 206 verifyFormat("case (data)\n" 207 " default\n" 208 " result = 10'b1011111111;\n" 209 "endcase"); 210 verifyFormat("case (data)\n" 211 " default:\n" 212 " result = 10'b1011111111;\n" 213 "endcase"); 214 // Test that question marks and colons don't get mistaken as labels. 215 verifyFormat("case (data)\n" 216 " 8'b1???????:\n" 217 " instruction1(ir);\n" 218 "endcase"); 219 verifyFormat("case (data)\n" 220 " x ? 8'b1??????? : 1:\n" 221 " instruction3(ir);\n" 222 "endcase"); 223 // Test indention options. 224 auto Style = getDefaultStyle(); 225 Style.IndentCaseLabels = false; 226 verifyFormat("case (data)\n" 227 "16'd0:\n" 228 " result = 10'b0111111111;\n" 229 "endcase", 230 Style); 231 verifyFormat("case (data)\n" 232 "16'd0: begin\n" 233 " result = 10'b0111111111;\n" 234 "end\n" 235 "endcase", 236 Style); 237 Style.IndentCaseLabels = true; 238 verifyFormat("case (data)\n" 239 " 16'd0:\n" 240 " result = 10'b0111111111;\n" 241 "endcase", 242 Style); 243 verifyFormat("case (data)\n" 244 " 16'd0: begin\n" 245 " result = 10'b0111111111;\n" 246 " end\n" 247 "endcase", 248 Style); 249 // Other colons should not be mistaken as case colons. 250 Style = getDefaultStyle(); 251 Style.BitFieldColonSpacing = FormatStyle::BFCS_None; 252 verifyFormat("case (x[1:0])\n" 253 "endcase", 254 Style); 255 verifyFormat("default:\n" 256 " x[1:0] = x[1:0];", 257 Style); 258 Style.BitFieldColonSpacing = FormatStyle::BFCS_Both; 259 verifyFormat("case (x[1 : 0])\n" 260 "endcase", 261 Style); 262 verifyFormat("default:\n" 263 " x[1 : 0] = x[1 : 0];", 264 Style); 265 Style = getDefaultStyle(); 266 Style.SpacesInContainerLiterals = true; 267 verifyFormat("case ('{x : x, default : 9})\n" 268 "endcase", 269 Style); 270 verifyFormat("x = '{x : x, default : 9};\n", Style); 271 verifyFormat("default:\n" 272 " x = '{x : x, default : 9};\n", 273 Style); 274 Style.SpacesInContainerLiterals = false; 275 verifyFormat("case ('{x: x, default: 9})\n" 276 "endcase", 277 Style); 278 verifyFormat("x = '{x: x, default: 9};\n", Style); 279 verifyFormat("default:\n" 280 " x = '{x: x, default: 9};\n", 281 Style); 282 } 283 284 TEST_F(FormatTestVerilog, Coverage) { 285 verifyFormat("covergroup x\n" 286 " @@(begin x);\n" 287 "endgroup"); 288 } 289 290 TEST_F(FormatTestVerilog, Declaration) { 291 verifyFormat("wire mynet;"); 292 verifyFormat("wire mynet, mynet1;"); 293 verifyFormat("wire mynet, //\n" 294 " mynet1;"); 295 verifyFormat("wire mynet = enable;"); 296 verifyFormat("wire mynet = enable, mynet1;"); 297 verifyFormat("wire mynet = enable, //\n" 298 " mynet1;"); 299 verifyFormat("wire mynet, mynet1 = enable;"); 300 verifyFormat("wire mynet, //\n" 301 " mynet1 = enable;"); 302 verifyFormat("wire mynet = enable, mynet1 = enable;"); 303 verifyFormat("wire mynet = enable, //\n" 304 " mynet1 = enable;"); 305 verifyFormat("wire (strong1, pull0) mynet;"); 306 verifyFormat("wire (strong1, pull0) mynet, mynet1;"); 307 verifyFormat("wire (strong1, pull0) mynet, //\n" 308 " mynet1;"); 309 verifyFormat("wire (strong1, pull0) mynet = enable;"); 310 verifyFormat("wire (strong1, pull0) mynet = enable, mynet1;"); 311 verifyFormat("wire (strong1, pull0) mynet = enable, //\n" 312 " mynet1;"); 313 verifyFormat("wire (strong1, pull0) mynet, mynet1 = enable;"); 314 verifyFormat("wire (strong1, pull0) mynet, //\n" 315 " mynet1 = enable;"); 316 } 317 318 TEST_F(FormatTestVerilog, Delay) { 319 // Delay by the default unit. 320 verifyFormat("#0;"); 321 verifyFormat("#1;"); 322 verifyFormat("#10;"); 323 verifyFormat("#1.5;"); 324 // Explicit unit. 325 verifyFormat("#1fs;"); 326 verifyFormat("#1.5fs;"); 327 verifyFormat("#1ns;"); 328 verifyFormat("#1.5ns;"); 329 verifyFormat("#1us;"); 330 verifyFormat("#1.5us;"); 331 verifyFormat("#1ms;"); 332 verifyFormat("#1.5ms;"); 333 verifyFormat("#1s;"); 334 verifyFormat("#1.5s;"); 335 // The following expression should be on the same line. 336 verifyFormat("#1 x = x;"); 337 verifyFormat("#1 x = x;", "#1\n" 338 "x = x;"); 339 } 340 341 TEST_F(FormatTestVerilog, Enum) { 342 verifyFormat("enum { x } x;"); 343 verifyFormat("typedef enum { x } x;"); 344 verifyFormat("enum { red, yellow, green } x;"); 345 verifyFormat("typedef enum { red, yellow, green } x;"); 346 verifyFormat("enum integer { x } x;"); 347 verifyFormat("typedef enum { x = 0 } x;"); 348 verifyFormat("typedef enum { red = 0, yellow = 1, green = 2 } x;"); 349 verifyFormat("typedef enum integer { x } x;"); 350 verifyFormat("typedef enum bit [0 : 1] { x } x;"); 351 verifyFormat("typedef enum { add = 10, sub[5], jmp[6 : 8] } E1;"); 352 verifyFormat("typedef enum { add = 10, sub[5] = 0, jmp[6 : 8] = 1 } E1;"); 353 } 354 355 TEST_F(FormatTestVerilog, Headers) { 356 // Test headers with multiple ports. 357 verifyFormat("module mh1\n" 358 " (input var int in1,\n" 359 " input var shortreal in2,\n" 360 " output tagged_st out);\n" 361 "endmodule"); 362 // Ports should be grouped by types. 363 verifyFormat("module test\n" 364 " (input [7 : 0] a,\n" 365 " input signed [7 : 0] b, c, d);\n" 366 "endmodule"); 367 verifyFormat("module test\n" 368 " (input [7 : 0] a,\n" 369 " (* x = x *) input signed [7 : 0] b, c, d);\n" 370 "endmodule"); 371 verifyFormat("module test\n" 372 " (input [7 : 0] a = 0,\n" 373 " input signed [7 : 0] b = 0, c = 0, d = 0);\n" 374 "endmodule"); 375 verifyFormat("module test\n" 376 " #(parameter x)\n" 377 " (input [7 : 0] a,\n" 378 " input signed [7 : 0] b, c, d);\n" 379 "endmodule"); 380 // When a line needs to be broken, ports of the same type should be aligned to 381 // the same column. 382 verifyFormat("module test\n" 383 " (input signed [7 : 0] b, c, //\n" 384 " d);\n" 385 "endmodule"); 386 verifyFormat("module test\n" 387 " ((* x = x *) input signed [7 : 0] b, c, //\n" 388 " d);\n" 389 "endmodule"); 390 verifyFormat("module test\n" 391 " (input signed [7 : 0] b = 0, c, //\n" 392 " d);\n" 393 "endmodule"); 394 verifyFormat("module test\n" 395 " (input signed [7 : 0] b, c = 0, //\n" 396 " d);\n" 397 "endmodule"); 398 verifyFormat("module test\n" 399 " (input signed [7 : 0] b, c, //\n" 400 " d = 0);\n" 401 "endmodule"); 402 verifyFormat("module test\n" 403 " (input wire logic signed [7 : 0][0 : 1] b, c, //\n" 404 " d);\n" 405 "endmodule"); 406 verifyFormat("module test\n" 407 " (input signed [7 : 0] b, //\n" 408 " c, //\n" 409 " d);\n" 410 "endmodule"); 411 verifyFormat("module test\n" 412 " (input [7 : 0] a,\n" 413 " input signed [7 : 0] b, //\n" 414 " c, //\n" 415 " d);\n" 416 "endmodule"); 417 verifyFormat("module test\n" 418 " (input signed [7 : 0] b, //\n" 419 " c, //\n" 420 " d,\n" 421 " output signed [7 : 0] h);\n" 422 "endmodule"); 423 // With a modport. 424 verifyFormat("module m\n" 425 " (i2.master i);\n" 426 "endmodule"); 427 verifyFormat("module m\n" 428 " (i2.master i, ii);\n" 429 "endmodule"); 430 verifyFormat("module m\n" 431 " (i2.master i, //\n" 432 " ii);\n" 433 "endmodule"); 434 verifyFormat("module m\n" 435 " (i2.master i,\n" 436 " input ii);\n" 437 "endmodule"); 438 verifyFormat("module m\n" 439 " (i2::i2.master i);\n" 440 "endmodule"); 441 verifyFormat("module m\n" 442 " (i2::i2.master i, ii);\n" 443 "endmodule"); 444 verifyFormat("module m\n" 445 " (i2::i2.master i, //\n" 446 " ii);\n" 447 "endmodule"); 448 verifyFormat("module m\n" 449 " (i2::i2.master i,\n" 450 " input ii);\n" 451 "endmodule"); 452 verifyFormat("module m\n" 453 " (i2::i2 i);\n" 454 "endmodule"); 455 verifyFormat("module m\n" 456 " (i2::i2 i, ii);\n" 457 "endmodule"); 458 verifyFormat("module m\n" 459 " (i2::i2 i, //\n" 460 " ii);\n" 461 "endmodule"); 462 verifyFormat("module m\n" 463 " (i2::i2 i,\n" 464 " input ii);\n" 465 "endmodule"); 466 // With a macro in the names. 467 verifyFormat("module m\n" 468 " (input var `x a, b);\n" 469 "endmodule"); 470 verifyFormat("module m\n" 471 " (input var `x a, //\n" 472 " b);\n" 473 "endmodule"); 474 verifyFormat("module m\n" 475 " (input var x `a, b);\n" 476 "endmodule"); 477 verifyFormat("module m\n" 478 " (input var x `a, //\n" 479 " b);\n" 480 "endmodule"); 481 // With a concatenation in the names. 482 auto Style = getDefaultStyle(); 483 Style.ColumnLimit = 40; 484 verifyFormat("`define X(x) \\\n" 485 " module test \\\n" 486 " (input var x``x a, b);", 487 Style); 488 verifyFormat("`define X(x) \\\n" 489 " module test \\\n" 490 " (input var x``x aaaaaaaaaaaaaaa, \\\n" 491 " b);", 492 Style); 493 verifyFormat("`define X(x) \\\n" 494 " module test \\\n" 495 " (input var x a``x, b);", 496 Style); 497 verifyFormat("`define X(x) \\\n" 498 " module test \\\n" 499 " (input var x aaaaaaaaaaaaaaa``x, \\\n" 500 " b);", 501 Style); 502 } 503 504 TEST_F(FormatTestVerilog, Hierarchy) { 505 verifyFormat("module x;\n" 506 "endmodule"); 507 // Test that the end label is on the same line as the end keyword. 508 verifyFormat("module x;\n" 509 "endmodule : x"); 510 // Test that things inside are indented. 511 verifyFormat("module x;\n" 512 " generate\n" 513 " endgenerate\n" 514 "endmodule"); 515 verifyFormat("program x;\n" 516 " generate\n" 517 " endgenerate\n" 518 "endprogram"); 519 verifyFormat("interface x;\n" 520 " generate\n" 521 " endgenerate\n" 522 "endinterface"); 523 verifyFormat("task x;\n" 524 " generate\n" 525 " endgenerate\n" 526 "endtask"); 527 verifyFormat("function x;\n" 528 " generate\n" 529 " endgenerate\n" 530 "endfunction"); 531 verifyFormat("class x;\n" 532 " generate\n" 533 " endgenerate\n" 534 "endclass"); 535 // Test that they nest. 536 verifyFormat("module x;\n" 537 " program x;\n" 538 " program x;\n" 539 " endprogram\n" 540 " endprogram\n" 541 "endmodule"); 542 // Test that an extern declaration doesn't change the indentation. 543 verifyFormat("extern module x;\n" 544 "x = x;"); 545 // Test complex headers 546 verifyFormat("extern module x\n" 547 " import x.x::x::*;\n" 548 " import x;\n" 549 " #(parameter x)\n" 550 " (output x);"); 551 verifyFormat("module x\n" 552 " import x.x::x::*;\n" 553 " import x;\n" 554 " #(parameter x)\n" 555 " (output x);\n" 556 " generate\n" 557 " endgenerate\n" 558 "endmodule : x"); 559 verifyFormat("virtual class x\n" 560 " (x)\n" 561 " extends x(x)\n" 562 " implements x, x, x;\n" 563 " generate\n" 564 " endgenerate\n" 565 "endclass : x\n"); 566 verifyFormat("function automatic logic [1 : 0] x\n" 567 " (input x);\n" 568 " generate\n" 569 " endgenerate\n" 570 "endfunction : x"); 571 } 572 573 TEST_F(FormatTestVerilog, Identifiers) { 574 // Escaped identifiers should not be split. 575 verifyFormat("\\busa+index"); 576 verifyFormat("\\-clock"); 577 verifyFormat("\\***error-condition***"); 578 verifyFormat("\\net1\\/net2"); 579 verifyFormat("\\{a,b}"); 580 verifyFormat("\\a*(b+c)"); 581 // Escaped identifiers can't be joined with the next token. Extra space 582 // should be removed. 583 verifyFormat("\\busa+index ;", "\\busa+index\n" 584 ";"); 585 verifyFormat("\\busa+index ;", "\\busa+index\r\n" 586 ";"); 587 verifyFormat("\\busa+index ;", "\\busa+index ;"); 588 verifyFormat("\\busa+index ;", "\\busa+index\n" 589 " ;"); 590 verifyFormat("\\busa+index ;"); 591 verifyFormat("(\\busa+index );"); 592 verifyFormat("\\busa+index \\busa+index ;"); 593 } 594 595 TEST_F(FormatTestVerilog, If) { 596 verifyFormat("if (x)\n" 597 " x = x;"); 598 verifyFormat("unique if (x)\n" 599 " x = x;"); 600 verifyFormat("unique0 if (x)\n" 601 " x = x;"); 602 verifyFormat("priority if (x)\n" 603 " x = x;"); 604 verifyFormat("if (x)\n" 605 " x = x;\n" 606 "x = x;"); 607 608 // Test else 609 verifyFormat("if (x)\n" 610 " x = x;\n" 611 "else if (x)\n" 612 " x = x;\n" 613 "else\n" 614 " x = x;"); 615 verifyFormat("if (x) begin\n" 616 " x = x;\n" 617 "end else if (x) begin\n" 618 " x = x;\n" 619 "end else begin\n" 620 " x = x;\n" 621 "end"); 622 verifyFormat("if (x) begin : x\n" 623 " x = x;\n" 624 "end : x else if (x) begin : x\n" 625 " x = x;\n" 626 "end : x else begin : x\n" 627 " x = x;\n" 628 "end : x"); 629 630 // Test block keywords. 631 verifyFormat("if (x) begin\n" 632 " x = x;\n" 633 "end"); 634 verifyFormat("if (x) begin : x\n" 635 " x = x;\n" 636 "end : x"); 637 verifyFormat("if (x) begin\n" 638 " x = x;\n" 639 " x = x;\n" 640 "end"); 641 verifyFormat("if (x) fork\n" 642 " x = x;\n" 643 "join"); 644 verifyFormat("if (x) fork\n" 645 " x = x;\n" 646 "join_any"); 647 verifyFormat("if (x) fork\n" 648 " x = x;\n" 649 "join_none"); 650 verifyFormat("if (x) generate\n" 651 " x = x;\n" 652 "endgenerate"); 653 verifyFormat("if (x) generate : x\n" 654 " x = x;\n" 655 "endgenerate : x"); 656 657 // Test that concatenation braces don't get regarded as blocks. 658 verifyFormat("if (x)\n" 659 " {x} = x;"); 660 verifyFormat("if (x)\n" 661 " x = {x};"); 662 verifyFormat("if (x)\n" 663 " x = {x};\n" 664 "else\n" 665 " {x} = {x};"); 666 667 // With attributes. 668 verifyFormat("(* x *) if (x)\n" 669 " x = x;"); 670 verifyFormat("(* x = \"x\" *) if (x)\n" 671 " x = x;"); 672 verifyFormat("(* x, x = \"x\" *) if (x)\n" 673 " x = x;"); 674 } 675 676 TEST_F(FormatTestVerilog, Operators) { 677 // Test that unary operators are not followed by space. 678 verifyFormat("x = +x;"); 679 verifyFormat("x = -x;"); 680 verifyFormat("x = !x;"); 681 verifyFormat("x = ~x;"); 682 verifyFormat("x = &x;"); 683 verifyFormat("x = ~&x;"); 684 verifyFormat("x = |x;"); 685 verifyFormat("x = ~|x;"); 686 verifyFormat("x = ^x;"); 687 verifyFormat("x = ~^x;"); 688 verifyFormat("x = ^~x;"); 689 verifyFormat("x = ++x;"); 690 verifyFormat("x = --x;"); 691 692 // Test that `*` and `*>` are binary. 693 verifyFormat("x = x * x;"); 694 verifyFormat("x = (x * x);"); 695 verifyFormat("(opcode *> o1) = 6.1;"); 696 verifyFormat("(C, D *> Q) = 18;"); 697 // The wildcard import is not a binary operator. 698 verifyFormat("import p::*;"); 699 700 // Test that operators don't get split. 701 verifyFormat("x = x++;"); 702 verifyFormat("x = x--;"); 703 verifyFormat("x = x ** x;"); 704 verifyFormat("x = x << x;"); 705 verifyFormat("x = x >> x;"); 706 verifyFormat("x = x <<< x;"); 707 verifyFormat("x = x >>> x;"); 708 verifyFormat("x = x <= x;"); 709 verifyFormat("x = x >= x;"); 710 verifyFormat("x = x == x;"); 711 verifyFormat("x = x != x;"); 712 verifyFormat("x = x === x;"); 713 verifyFormat("x = x !== x;"); 714 verifyFormat("x = x ==? x;"); 715 verifyFormat("x = x !=? x;"); 716 verifyFormat("x = x ~^ x;"); 717 verifyFormat("x = x ^~ x;"); 718 verifyFormat("x = x && x;"); 719 verifyFormat("x = x || x;"); 720 verifyFormat("x = x->x;"); 721 verifyFormat("x = x <-> x;"); 722 verifyFormat("x += x;"); 723 verifyFormat("x -= x;"); 724 verifyFormat("x *= x;"); 725 verifyFormat("x /= x;"); 726 verifyFormat("x %= x;"); 727 verifyFormat("x &= x;"); 728 verifyFormat("x ^= x;"); 729 verifyFormat("x |= x;"); 730 verifyFormat("x <<= x;"); 731 verifyFormat("x >>= x;"); 732 verifyFormat("x <<<= x;"); 733 verifyFormat("x >>>= x;"); 734 verifyFormat("x <= x;"); 735 736 // Test that space is added between operators. 737 verifyFormat("x = x < -x;", "x=x<-x;"); 738 verifyFormat("x = x << -x;", "x=x<<-x;"); 739 verifyFormat("x = x <<< -x;", "x=x<<<-x;"); 740 741 // Test that operators that are C++ identifiers get treated as operators. 742 verifyFormat("solve s before d;"); // before 743 verifyFormat("binsof(i) intersect {0};"); // intersect 744 verifyFormat("req dist {1};"); // dist 745 verifyFormat("a inside {b, c};"); // inside 746 verifyFormat("bus.randomize() with { atype == low; };"); // with 747 } 748 749 TEST_F(FormatTestVerilog, Preprocessor) { 750 auto Style = getDefaultStyle(); 751 Style.ColumnLimit = 20; 752 753 // Macro definitions. 754 verifyFormat("`define X \\\n" 755 " if (x) \\\n" 756 " x = x;", 757 "`define X if(x)x=x;", Style); 758 verifyFormat("`define X(x) \\\n" 759 " if (x) \\\n" 760 " x = x;", 761 "`define X(x) if(x)x=x;", Style); 762 verifyFormat("`define X \\\n" 763 " x = x; \\\n" 764 " x = x;", 765 "`define X x=x;x=x;", Style); 766 // Macro definitions with invocations inside. 767 verifyFormat("`define LIST \\\n" 768 " `ENTRY \\\n" 769 " `ENTRY", 770 "`define LIST \\\n" 771 "`ENTRY \\\n" 772 "`ENTRY", 773 Style); 774 verifyFormat("`define LIST \\\n" 775 " `x = `x; \\\n" 776 " `x = `x;", 777 "`define LIST \\\n" 778 "`x = `x; \\\n" 779 "`x = `x;", 780 Style); 781 verifyFormat("`define LIST \\\n" 782 " `x = `x; \\\n" 783 " `x = `x;", 784 "`define LIST `x=`x;`x=`x;", Style); 785 // Macro invocations. 786 verifyFormat("`x = (`x1 + `x2 + x);"); 787 // Lines starting with a preprocessor directive should not be indented. 788 std::string Directives[] = { 789 "begin_keywords", 790 "celldefine", 791 "default_nettype", 792 "define", 793 "else", 794 "elsif", 795 "end_keywords", 796 "endcelldefine", 797 "endif", 798 "ifdef", 799 "ifndef", 800 "include", 801 "line", 802 "nounconnected_drive", 803 "pragma", 804 "resetall", 805 "timescale", 806 "unconnected_drive", 807 "undef", 808 "undefineall", 809 }; 810 for (auto &Name : Directives) { 811 verifyFormat("if (x)\n" 812 "`" + 813 Name + 814 "\n" 815 " ;", 816 "if (x)\n" 817 "`" + 818 Name + 819 "\n" 820 ";", 821 Style); 822 } 823 // Lines starting with a regular macro invocation should be indented as a 824 // normal line. 825 verifyFormat("if (x)\n" 826 " `x = `x;\n" 827 "`timescale 1ns / 1ps", 828 "if (x)\n" 829 "`x = `x;\n" 830 "`timescale 1ns / 1ps", 831 Style); 832 verifyFormat("if (x)\n" 833 "`timescale 1ns / 1ps\n" 834 " `x = `x;", 835 "if (x)\n" 836 "`timescale 1ns / 1ps\n" 837 "`x = `x;", 838 Style); 839 std::string NonDirectives[] = { 840 // For `__FILE__` and `__LINE__`, although the standard classifies them as 841 // preprocessor directives, they are used like regular macros. 842 "__FILE__", "__LINE__", "elif", "foo", "x", 843 }; 844 for (auto &Name : NonDirectives) { 845 verifyFormat("if (x)\n" 846 " `" + 847 Name + ";", 848 "if (x)\n" 849 "`" + 850 Name + 851 "\n" 852 ";", 853 Style); 854 } 855 } 856 857 TEST_F(FormatTestVerilog, Primitive) { 858 verifyFormat("primitive multiplexer\n" 859 " (mux, control, dataA, dataB);\n" 860 " output mux;\n" 861 " input control, dataA, dataB;\n" 862 " table\n" 863 " 0 1 ? : 1;\n" 864 " 0 0 ? : 0;\n" 865 " 1 ? 1 : 1;\n" 866 " 1 ? 0 : 0;\n" 867 " x 0 0 : 0;\n" 868 " x 1 1 : 1;\n" 869 " endtable\n" 870 "endprimitive"); 871 verifyFormat("primitive latch\n" 872 " (q, ena_, data);\n" 873 " output q;\n" 874 " reg q;\n" 875 " input ena_, data;\n" 876 " table\n" 877 " 0 1 : ? : 1;\n" 878 " 0 0 : ? : 0;\n" 879 " 1 ? : ? : -;\n" 880 " ? * : ? : -;\n" 881 " endtable\n" 882 "endprimitive"); 883 verifyFormat("primitive d\n" 884 " (q, clock, data);\n" 885 " output q;\n" 886 " reg q;\n" 887 " input clock, data;\n" 888 " table\n" 889 " (01) 0 : ? : 0;\n" 890 " (01) 1 : ? : 1;\n" 891 " (0?) 1 : 1 : 1;\n" 892 " (0?) 0 : 0 : 0;\n" 893 " (?0) ? : ? : -;\n" 894 " (?\?) ? : ? : -;\n" 895 " endtable\n" 896 "endprimitive"); 897 } 898 899 TEST_F(FormatTestVerilog, Streaming) { 900 verifyFormat("x = {>>{j}};"); 901 verifyFormat("x = {>>byte{j}};"); 902 verifyFormat("x = {<<{j}};"); 903 verifyFormat("x = {<<byte{j}};"); 904 verifyFormat("x = {<<16{j}};"); 905 verifyFormat("x = {<<{8'b0011_0101}};"); 906 verifyFormat("x = {<<4{6'b11_0101}};"); 907 verifyFormat("x = {>>4{6'b11_0101}};"); 908 verifyFormat("x = {<<2{{<<{4'b1101}}}};"); 909 verifyFormat("bit [96 : 1] y = {>>{a, b, c}};"); 910 verifyFormat("int j = {>>{a, b, c}};"); 911 verifyFormat("{>>{a, b, c}} = 23'b1;"); 912 verifyFormat("{>>{a, b, c}} = x;"); 913 verifyFormat("{>>{j}} = x;"); 914 verifyFormat("{>>byte{j}} = x;"); 915 verifyFormat("{<<{j}} = x;"); 916 verifyFormat("{<<byte{j}} = x;"); 917 } 918 919 TEST_F(FormatTestVerilog, StructuredProcedure) { 920 // Blocks should be indented correctly. 921 verifyFormat("initial begin\n" 922 "end"); 923 verifyFormat("initial begin\n" 924 " x <= x;\n" 925 " x <= x;\n" 926 "end"); 927 verifyFormat("initial\n" 928 " x <= x;\n" 929 "x <= x;"); 930 verifyFormat("always @(x) begin\n" 931 "end"); 932 verifyFormat("always @(x) begin\n" 933 " x <= x;\n" 934 " x <= x;\n" 935 "end"); 936 verifyFormat("always @(x)\n" 937 " x <= x;\n" 938 "x <= x;"); 939 // Various keywords. 940 verifyFormat("always @(x)\n" 941 " x <= x;"); 942 verifyFormat("always @(posedge x)\n" 943 " x <= x;"); 944 verifyFormat("always\n" 945 " x <= x;"); 946 verifyFormat("always @*\n" 947 " x <= x;"); 948 verifyFormat("always @(*)\n" 949 " x <= x;"); 950 verifyFormat("always_comb\n" 951 " x <= x;"); 952 verifyFormat("always_latch @(x)\n" 953 " x <= x;"); 954 verifyFormat("always_ff @(posedge x)\n" 955 " x <= x;"); 956 verifyFormat("initial\n" 957 " x <= x;"); 958 verifyFormat("final\n" 959 " x <= x;"); 960 verifyFormat("forever\n" 961 " x <= x;"); 962 } 963 } // namespace 964 } // namespace test 965 } // namespace format 966 } // namespace clang 967