1 //===- unittest/Format/FormatTestVerilog.cpp ------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "FormatTestUtils.h" 10 #include "clang/Format/Format.h" 11 #include "llvm/Support/Debug.h" 12 #include "gtest/gtest.h" 13 14 #define DEBUG_TYPE "format-test" 15 16 namespace clang { 17 namespace format { 18 19 class FormatTestVerilog : public ::testing::Test { 20 protected: 21 static std::string format(llvm::StringRef Code, unsigned Offset, 22 unsigned Length, const FormatStyle &Style) { 23 LLVM_DEBUG(llvm::errs() << "---\n"); 24 LLVM_DEBUG(llvm::errs() << Code << "\n\n"); 25 std::vector<tooling::Range> Ranges(1, tooling::Range(Offset, Length)); 26 tooling::Replacements Replaces = reformat(Style, Code, Ranges); 27 auto Result = applyAllReplacements(Code, Replaces); 28 EXPECT_TRUE(static_cast<bool>(Result)); 29 LLVM_DEBUG(llvm::errs() << "\n" << *Result << "\n\n"); 30 return *Result; 31 } 32 33 static std::string 34 format(llvm::StringRef Code, 35 const FormatStyle &Style = getLLVMStyle(FormatStyle::LK_Verilog)) { 36 return format(Code, 0, Code.size(), Style); 37 } 38 39 static void verifyFormat( 40 llvm::StringRef Code, 41 const FormatStyle &Style = getLLVMStyle(FormatStyle::LK_Verilog)) { 42 EXPECT_EQ(Code.str(), format(Code, Style)) << "Expected code is not stable"; 43 EXPECT_EQ(Code.str(), 44 format(test::messUp(Code, /*HandleHash=*/false), Style)); 45 } 46 }; 47 48 TEST_F(FormatTestVerilog, Align) { 49 FormatStyle Style = getLLVMStyle(FormatStyle::LK_Verilog); 50 Style.AlignConsecutiveAssignments.Enabled = true; 51 verifyFormat("x <= x;\n" 52 "sfdbddfbdfbb <= x;\n" 53 "x = x;", 54 Style); 55 verifyFormat("x = x;\n" 56 "sfdbddfbdfbb = x;\n" 57 "x = x;", 58 Style); 59 // Compound assignments are not aligned by default. '<=' is not a compound 60 // assignment. 61 verifyFormat("x <= x;\n" 62 "sfdbddfbdfbb <= x;", 63 Style); 64 verifyFormat("x += x;\n" 65 "sfdbddfbdfbb <= x;", 66 Style); 67 verifyFormat("x <<= x;\n" 68 "sfdbddfbdfbb <= x;", 69 Style); 70 verifyFormat("x <<<= x;\n" 71 "sfdbddfbdfbb <= x;", 72 Style); 73 verifyFormat("x >>= x;\n" 74 "sfdbddfbdfbb <= x;", 75 Style); 76 verifyFormat("x >>>= x;\n" 77 "sfdbddfbdfbb <= x;", 78 Style); 79 Style.AlignConsecutiveAssignments.AlignCompound = true; 80 verifyFormat("x <= x;\n" 81 "sfdbddfbdfbb <= x;", 82 Style); 83 verifyFormat("x += x;\n" 84 "sfdbddfbdfbb <= x;", 85 Style); 86 verifyFormat("x <<= x;\n" 87 "sfdbddfbdfbb <= x;", 88 Style); 89 verifyFormat("x <<<= x;\n" 90 "sfdbddfbdfbb <= x;", 91 Style); 92 verifyFormat("x >>= x;\n" 93 "sfdbddfbdfbb <= x;", 94 Style); 95 verifyFormat("x >>>= x;\n" 96 "sfdbddfbdfbb <= x;", 97 Style); 98 } 99 100 TEST_F(FormatTestVerilog, BasedLiteral) { 101 verifyFormat("x = '0;"); 102 verifyFormat("x = '1;"); 103 verifyFormat("x = 'X;"); 104 verifyFormat("x = 'x;"); 105 verifyFormat("x = 'Z;"); 106 verifyFormat("x = 'z;"); 107 verifyFormat("x = 659;"); 108 verifyFormat("x = 'h837ff;"); 109 verifyFormat("x = 'o7460;"); 110 verifyFormat("x = 4'b1001;"); 111 verifyFormat("x = 5'D3;"); 112 verifyFormat("x = 3'b01x;"); 113 verifyFormat("x = 12'hx;"); 114 verifyFormat("x = 16'hz;"); 115 verifyFormat("x = -8'd6;"); 116 verifyFormat("x = 4'shf;"); 117 verifyFormat("x = -4'sd15;"); 118 verifyFormat("x = 16'sd?;"); 119 } 120 121 TEST_F(FormatTestVerilog, Block) { 122 verifyFormat("begin\n" 123 " x = x;\n" 124 "end"); 125 verifyFormat("begin : x\n" 126 " x = x;\n" 127 "end : x"); 128 verifyFormat("begin\n" 129 " x = x;\n" 130 " x = x;\n" 131 "end"); 132 verifyFormat("fork\n" 133 " x = x;\n" 134 "join"); 135 verifyFormat("fork\n" 136 " x = x;\n" 137 "join_any"); 138 verifyFormat("fork\n" 139 " x = x;\n" 140 "join_none"); 141 verifyFormat("generate\n" 142 " x = x;\n" 143 "endgenerate"); 144 verifyFormat("generate : x\n" 145 " x = x;\n" 146 "endgenerate : x"); 147 // Nested blocks. 148 verifyFormat("begin\n" 149 " begin\n" 150 " end\n" 151 "end"); 152 verifyFormat("begin : x\n" 153 " begin\n" 154 " end\n" 155 "end : x"); 156 verifyFormat("begin : x\n" 157 " begin : x\n" 158 " end : x\n" 159 "end : x"); 160 verifyFormat("begin\n" 161 " begin : x\n" 162 " end : x\n" 163 "end"); 164 // Test that 'disable fork' and 'rand join' don't get mistaken as blocks. 165 verifyFormat("disable fork;\n" 166 "x = x;"); 167 verifyFormat("rand join x x;\n" 168 "x = x;"); 169 } 170 171 TEST_F(FormatTestVerilog, Case) { 172 verifyFormat("case (data)\n" 173 "endcase"); 174 verifyFormat("casex (data)\n" 175 "endcase"); 176 verifyFormat("casez (data)\n" 177 "endcase"); 178 verifyFormat("case (data) inside\n" 179 "endcase"); 180 verifyFormat("case (data)\n" 181 " 16'd0:\n" 182 " result = 10'b0111111111;\n" 183 "endcase"); 184 verifyFormat("case (data)\n" 185 " xxxxxxxx:\n" 186 " result = 10'b0111111111;\n" 187 "endcase"); 188 // Test labels with multiple options. 189 verifyFormat("case (data)\n" 190 " 16'd0, 16'd1:\n" 191 " result = 10'b0111111111;\n" 192 "endcase"); 193 verifyFormat("case (data)\n" 194 " 16'd0, //\n" 195 " 16'd1:\n" 196 " result = 10'b0111111111;\n" 197 "endcase"); 198 // Test that blocks following labels are indented. 199 verifyFormat("case (data)\n" 200 " 16'd1: fork\n" 201 " result = 10'b1011111111;\n" 202 " join\n" 203 "endcase\n"); 204 verifyFormat("case (data)\n" 205 " 16'd1: fork : x\n" 206 " result = 10'b1011111111;\n" 207 " join : x\n" 208 "endcase\n"); 209 // Test default. 210 verifyFormat("case (data)\n" 211 " default\n" 212 " result = 10'b1011111111;\n" 213 "endcase"); 214 verifyFormat("case (data)\n" 215 " default:\n" 216 " result = 10'b1011111111;\n" 217 "endcase"); 218 // Test that question marks and colons don't get mistaken as labels. 219 verifyFormat("case (data)\n" 220 " 8'b1???????:\n" 221 " instruction1(ir);\n" 222 "endcase"); 223 verifyFormat("case (data)\n" 224 " x ? 8'b1??????? : 1:\n" 225 " instruction3(ir);\n" 226 "endcase"); 227 // Test indention options. 228 auto Style = getLLVMStyle(FormatStyle::LK_Verilog); 229 Style.IndentCaseLabels = false; 230 verifyFormat("case (data)\n" 231 "16'd0:\n" 232 " result = 10'b0111111111;\n" 233 "endcase", 234 Style); 235 verifyFormat("case (data)\n" 236 "16'd0: begin\n" 237 " result = 10'b0111111111;\n" 238 "end\n" 239 "endcase", 240 Style); 241 Style.IndentCaseLabels = true; 242 verifyFormat("case (data)\n" 243 " 16'd0:\n" 244 " result = 10'b0111111111;\n" 245 "endcase", 246 Style); 247 verifyFormat("case (data)\n" 248 " 16'd0: begin\n" 249 " result = 10'b0111111111;\n" 250 " end\n" 251 "endcase", 252 Style); 253 } 254 255 TEST_F(FormatTestVerilog, Declaration) { 256 verifyFormat("wire mynet;"); 257 verifyFormat("wire mynet, mynet1;"); 258 verifyFormat("wire mynet, //\n" 259 " mynet1;"); 260 verifyFormat("wire mynet = enable;"); 261 verifyFormat("wire mynet = enable, mynet1;"); 262 verifyFormat("wire mynet = enable, //\n" 263 " mynet1;"); 264 verifyFormat("wire mynet, mynet1 = enable;"); 265 verifyFormat("wire mynet, //\n" 266 " mynet1 = enable;"); 267 verifyFormat("wire mynet = enable, mynet1 = enable;"); 268 verifyFormat("wire mynet = enable, //\n" 269 " mynet1 = enable;"); 270 verifyFormat("wire (strong1, pull0) mynet;"); 271 verifyFormat("wire (strong1, pull0) mynet, mynet1;"); 272 verifyFormat("wire (strong1, pull0) mynet, //\n" 273 " mynet1;"); 274 verifyFormat("wire (strong1, pull0) mynet = enable;"); 275 verifyFormat("wire (strong1, pull0) mynet = enable, mynet1;"); 276 verifyFormat("wire (strong1, pull0) mynet = enable, //\n" 277 " mynet1;"); 278 verifyFormat("wire (strong1, pull0) mynet, mynet1 = enable;"); 279 verifyFormat("wire (strong1, pull0) mynet, //\n" 280 " mynet1 = enable;"); 281 } 282 283 TEST_F(FormatTestVerilog, Delay) { 284 // Delay by the default unit. 285 verifyFormat("#0;"); 286 verifyFormat("#1;"); 287 verifyFormat("#10;"); 288 verifyFormat("#1.5;"); 289 // Explicit unit. 290 verifyFormat("#1fs;"); 291 verifyFormat("#1.5fs;"); 292 verifyFormat("#1ns;"); 293 verifyFormat("#1.5ns;"); 294 verifyFormat("#1us;"); 295 verifyFormat("#1.5us;"); 296 verifyFormat("#1ms;"); 297 verifyFormat("#1.5ms;"); 298 verifyFormat("#1s;"); 299 verifyFormat("#1.5s;"); 300 // The following expression should be on the same line. 301 verifyFormat("#1 x = x;"); 302 EXPECT_EQ("#1 x = x;", format("#1\n" 303 "x = x;")); 304 } 305 306 TEST_F(FormatTestVerilog, Headers) { 307 // Test headers with multiple ports. 308 verifyFormat("module mh1\n" 309 " (input var int in1,\n" 310 " input var shortreal in2,\n" 311 " output tagged_st out);\n" 312 "endmodule"); 313 // Ports should be grouped by types. 314 verifyFormat("module test\n" 315 " (input [7 : 0] a,\n" 316 " input signed [7 : 0] b, c, d);\n" 317 "endmodule"); 318 verifyFormat("module test\n" 319 " (input [7 : 0] a,\n" 320 " (* x = x *) input signed [7 : 0] b, c, d);\n" 321 "endmodule"); 322 verifyFormat("module test\n" 323 " (input [7 : 0] a = 0,\n" 324 " input signed [7 : 0] b = 0, c = 0, d = 0);\n" 325 "endmodule"); 326 verifyFormat("module test\n" 327 " #(parameter x)\n" 328 " (input [7 : 0] a,\n" 329 " input signed [7 : 0] b, c, d);\n" 330 "endmodule"); 331 // When a line needs to be broken, ports of the same type should be aligned to 332 // the same column. 333 verifyFormat("module test\n" 334 " (input signed [7 : 0] b, c, //\n" 335 " d);\n" 336 "endmodule"); 337 verifyFormat("module test\n" 338 " ((* x = x *) input signed [7 : 0] b, c, //\n" 339 " d);\n" 340 "endmodule"); 341 verifyFormat("module test\n" 342 " (input signed [7 : 0] b = 0, c, //\n" 343 " d);\n" 344 "endmodule"); 345 verifyFormat("module test\n" 346 " (input signed [7 : 0] b, c = 0, //\n" 347 " d);\n" 348 "endmodule"); 349 verifyFormat("module test\n" 350 " (input signed [7 : 0] b, c, //\n" 351 " d = 0);\n" 352 "endmodule"); 353 verifyFormat("module test\n" 354 " (input wire logic signed [7 : 0][0 : 1] b, c, //\n" 355 " d);\n" 356 "endmodule"); 357 verifyFormat("module test\n" 358 " (input signed [7 : 0] b, //\n" 359 " c, //\n" 360 " d);\n" 361 "endmodule"); 362 verifyFormat("module test\n" 363 " (input [7 : 0] a,\n" 364 " input signed [7 : 0] b, //\n" 365 " c, //\n" 366 " d);\n" 367 "endmodule"); 368 verifyFormat("module test\n" 369 " (input signed [7 : 0] b, //\n" 370 " c, //\n" 371 " d,\n" 372 " output signed [7 : 0] h);\n" 373 "endmodule"); 374 // With a modport. 375 verifyFormat("module m\n" 376 " (i2.master i);\n" 377 "endmodule"); 378 verifyFormat("module m\n" 379 " (i2.master i, ii);\n" 380 "endmodule"); 381 verifyFormat("module m\n" 382 " (i2.master i, //\n" 383 " ii);\n" 384 "endmodule"); 385 verifyFormat("module m\n" 386 " (i2.master i,\n" 387 " input ii);\n" 388 "endmodule"); 389 verifyFormat("module m\n" 390 " (i2::i2.master i);\n" 391 "endmodule"); 392 verifyFormat("module m\n" 393 " (i2::i2.master i, ii);\n" 394 "endmodule"); 395 verifyFormat("module m\n" 396 " (i2::i2.master i, //\n" 397 " ii);\n" 398 "endmodule"); 399 verifyFormat("module m\n" 400 " (i2::i2.master i,\n" 401 " input ii);\n" 402 "endmodule"); 403 verifyFormat("module m\n" 404 " (i2::i2 i);\n" 405 "endmodule"); 406 verifyFormat("module m\n" 407 " (i2::i2 i, ii);\n" 408 "endmodule"); 409 verifyFormat("module m\n" 410 " (i2::i2 i, //\n" 411 " ii);\n" 412 "endmodule"); 413 verifyFormat("module m\n" 414 " (i2::i2 i,\n" 415 " input ii);\n" 416 "endmodule"); 417 // With a macro in the names. 418 verifyFormat("module m\n" 419 " (input var `x a, b);\n" 420 "endmodule"); 421 verifyFormat("module m\n" 422 " (input var `x a, //\n" 423 " b);\n" 424 "endmodule"); 425 verifyFormat("module m\n" 426 " (input var x `a, b);\n" 427 "endmodule"); 428 verifyFormat("module m\n" 429 " (input var x `a, //\n" 430 " b);\n" 431 "endmodule"); 432 // With a concatenation in the names. 433 auto Style = getLLVMStyle(FormatStyle::LK_Verilog); 434 Style.ColumnLimit = 40; 435 verifyFormat("`define X(x) \\\n" 436 " module test \\\n" 437 " (input var x``x a, b);", 438 Style); 439 verifyFormat("`define X(x) \\\n" 440 " module test \\\n" 441 " (input var x``x aaaaaaaaaaaaaaa, \\\n" 442 " b);", 443 Style); 444 verifyFormat("`define X(x) \\\n" 445 " module test \\\n" 446 " (input var x a``x, b);", 447 Style); 448 verifyFormat("`define X(x) \\\n" 449 " module test \\\n" 450 " (input var x aaaaaaaaaaaaaaa``x, \\\n" 451 " b);", 452 Style); 453 } 454 455 TEST_F(FormatTestVerilog, Hierarchy) { 456 verifyFormat("module x;\n" 457 "endmodule"); 458 // Test that the end label is on the same line as the end keyword. 459 verifyFormat("module x;\n" 460 "endmodule : x"); 461 // Test that things inside are indented. 462 verifyFormat("module x;\n" 463 " generate\n" 464 " endgenerate\n" 465 "endmodule"); 466 verifyFormat("program x;\n" 467 " generate\n" 468 " endgenerate\n" 469 "endprogram"); 470 verifyFormat("interface x;\n" 471 " generate\n" 472 " endgenerate\n" 473 "endinterface"); 474 verifyFormat("task x;\n" 475 " generate\n" 476 " endgenerate\n" 477 "endtask"); 478 verifyFormat("function x;\n" 479 " generate\n" 480 " endgenerate\n" 481 "endfunction"); 482 verifyFormat("class x;\n" 483 " generate\n" 484 " endgenerate\n" 485 "endclass"); 486 // Test that they nest. 487 verifyFormat("module x;\n" 488 " program x;\n" 489 " program x;\n" 490 " endprogram\n" 491 " endprogram\n" 492 "endmodule"); 493 // Test that an extern declaration doesn't change the indentation. 494 verifyFormat("extern module x;\n" 495 "x = x;"); 496 // Test complex headers 497 verifyFormat("extern module x\n" 498 " import x.x::x::*;\n" 499 " import x;\n" 500 " #(parameter x)\n" 501 " (output x);"); 502 verifyFormat("module x\n" 503 " import x.x::x::*;\n" 504 " import x;\n" 505 " #(parameter x)\n" 506 " (output x);\n" 507 " generate\n" 508 " endgenerate\n" 509 "endmodule : x"); 510 verifyFormat("virtual class x\n" 511 " (x)\n" 512 " extends x(x)\n" 513 " implements x, x, x;\n" 514 " generate\n" 515 " endgenerate\n" 516 "endclass : x\n"); 517 verifyFormat("function automatic logic [1 : 0] x\n" 518 " (input x);\n" 519 " generate\n" 520 " endgenerate\n" 521 "endfunction : x"); 522 } 523 524 TEST_F(FormatTestVerilog, If) { 525 verifyFormat("if (x)\n" 526 " x = x;"); 527 verifyFormat("unique if (x)\n" 528 " x = x;"); 529 verifyFormat("unique0 if (x)\n" 530 " x = x;"); 531 verifyFormat("priority if (x)\n" 532 " x = x;"); 533 verifyFormat("if (x)\n" 534 " x = x;\n" 535 "x = x;"); 536 537 // Test else 538 verifyFormat("if (x)\n" 539 " x = x;\n" 540 "else if (x)\n" 541 " x = x;\n" 542 "else\n" 543 " x = x;"); 544 verifyFormat("if (x) begin\n" 545 " x = x;\n" 546 "end else if (x) begin\n" 547 " x = x;\n" 548 "end else begin\n" 549 " x = x;\n" 550 "end"); 551 verifyFormat("if (x) begin : x\n" 552 " x = x;\n" 553 "end : x else if (x) begin : x\n" 554 " x = x;\n" 555 "end : x else begin : x\n" 556 " x = x;\n" 557 "end : x"); 558 559 // Test block keywords. 560 verifyFormat("if (x) begin\n" 561 " x = x;\n" 562 "end"); 563 verifyFormat("if (x) begin : x\n" 564 " x = x;\n" 565 "end : x"); 566 verifyFormat("if (x) begin\n" 567 " x = x;\n" 568 " x = x;\n" 569 "end"); 570 verifyFormat("if (x) fork\n" 571 " x = x;\n" 572 "join"); 573 verifyFormat("if (x) fork\n" 574 " x = x;\n" 575 "join_any"); 576 verifyFormat("if (x) fork\n" 577 " x = x;\n" 578 "join_none"); 579 verifyFormat("if (x) generate\n" 580 " x = x;\n" 581 "endgenerate"); 582 verifyFormat("if (x) generate : x\n" 583 " x = x;\n" 584 "endgenerate : x"); 585 586 // Test that concatenation braces don't get regarded as blocks. 587 verifyFormat("if (x)\n" 588 " {x} = x;"); 589 verifyFormat("if (x)\n" 590 " x = {x};"); 591 verifyFormat("if (x)\n" 592 " x = {x};\n" 593 "else\n" 594 " {x} = {x};"); 595 596 // With attributes. 597 verifyFormat("(* x *) if (x)\n" 598 " x = x;"); 599 verifyFormat("(* x = \"x\" *) if (x)\n" 600 " x = x;"); 601 verifyFormat("(* x, x = \"x\" *) if (x)\n" 602 " x = x;"); 603 } 604 605 TEST_F(FormatTestVerilog, Operators) { 606 // Test that unary operators are not followed by space. 607 verifyFormat("x = +x;"); 608 verifyFormat("x = -x;"); 609 verifyFormat("x = !x;"); 610 verifyFormat("x = ~x;"); 611 verifyFormat("x = &x;"); 612 verifyFormat("x = ~&x;"); 613 verifyFormat("x = |x;"); 614 verifyFormat("x = ~|x;"); 615 verifyFormat("x = ^x;"); 616 verifyFormat("x = ~^x;"); 617 verifyFormat("x = ^~x;"); 618 verifyFormat("x = ++x;"); 619 verifyFormat("x = --x;"); 620 621 // Test that operators don't get split. 622 verifyFormat("x = x++;"); 623 verifyFormat("x = x--;"); 624 verifyFormat("x = x ** x;"); 625 verifyFormat("x = x << x;"); 626 verifyFormat("x = x >> x;"); 627 verifyFormat("x = x <<< x;"); 628 verifyFormat("x = x >>> x;"); 629 verifyFormat("x = x <= x;"); 630 verifyFormat("x = x >= x;"); 631 verifyFormat("x = x == x;"); 632 verifyFormat("x = x != x;"); 633 verifyFormat("x = x === x;"); 634 verifyFormat("x = x !== x;"); 635 verifyFormat("x = x ==? x;"); 636 verifyFormat("x = x !=? x;"); 637 verifyFormat("x = x ~^ x;"); 638 verifyFormat("x = x ^~ x;"); 639 verifyFormat("x = x && x;"); 640 verifyFormat("x = x || x;"); 641 verifyFormat("x = x->x;"); 642 verifyFormat("x = x <-> x;"); 643 verifyFormat("x += x;"); 644 verifyFormat("x -= x;"); 645 verifyFormat("x *= x;"); 646 verifyFormat("x /= x;"); 647 verifyFormat("x %= x;"); 648 verifyFormat("x &= x;"); 649 verifyFormat("x ^= x;"); 650 verifyFormat("x |= x;"); 651 verifyFormat("x <<= x;"); 652 verifyFormat("x >>= x;"); 653 verifyFormat("x <<<= x;"); 654 verifyFormat("x >>>= x;"); 655 verifyFormat("x <= x;"); 656 657 // Test that space is added between operators. 658 EXPECT_EQ("x = x < -x;", format("x=x<-x;")); 659 EXPECT_EQ("x = x << -x;", format("x=x<<-x;")); 660 EXPECT_EQ("x = x <<< -x;", format("x=x<<<-x;")); 661 } 662 663 TEST_F(FormatTestVerilog, Preprocessor) { 664 auto Style = getLLVMStyle(FormatStyle::LK_Verilog); 665 Style.ColumnLimit = 20; 666 667 // Macro definitions. 668 EXPECT_EQ("`define X \\\n" 669 " if (x) \\\n" 670 " x = x;", 671 format("`define X if(x)x=x;", Style)); 672 EXPECT_EQ("`define X(x) \\\n" 673 " if (x) \\\n" 674 " x = x;", 675 format("`define X(x) if(x)x=x;", Style)); 676 EXPECT_EQ("`define X \\\n" 677 " x = x; \\\n" 678 " x = x;", 679 format("`define X x=x;x=x;", Style)); 680 // Macro definitions with invocations inside. 681 EXPECT_EQ("`define LIST \\\n" 682 " `ENTRY \\\n" 683 " `ENTRY", 684 format("`define LIST \\\n" 685 "`ENTRY \\\n" 686 "`ENTRY", 687 Style)); 688 EXPECT_EQ("`define LIST \\\n" 689 " `x = `x; \\\n" 690 " `x = `x;", 691 format("`define LIST \\\n" 692 "`x = `x; \\\n" 693 "`x = `x;", 694 Style)); 695 EXPECT_EQ("`define LIST \\\n" 696 " `x = `x; \\\n" 697 " `x = `x;", 698 format("`define LIST `x=`x;`x=`x;", Style)); 699 // Macro invocations. 700 verifyFormat("`x = (`x1 + `x2 + x);"); 701 // Lines starting with a preprocessor directive should not be indented. 702 std::string Directives[] = { 703 "begin_keywords", 704 "celldefine", 705 "default_nettype", 706 "define", 707 "else", 708 "elsif", 709 "end_keywords", 710 "endcelldefine", 711 "endif", 712 "ifdef", 713 "ifndef", 714 "include", 715 "line", 716 "nounconnected_drive", 717 "pragma", 718 "resetall", 719 "timescale", 720 "unconnected_drive", 721 "undef", 722 "undefineall", 723 }; 724 for (auto &Name : Directives) { 725 EXPECT_EQ("if (x)\n" 726 "`" + 727 Name + 728 "\n" 729 " ;", 730 format("if (x)\n" 731 "`" + 732 Name + 733 "\n" 734 ";", 735 Style)); 736 } 737 // Lines starting with a regular macro invocation should be indented as a 738 // normal line. 739 EXPECT_EQ("if (x)\n" 740 " `x = `x;\n" 741 "`timescale 1ns / 1ps", 742 format("if (x)\n" 743 "`x = `x;\n" 744 "`timescale 1ns / 1ps", 745 Style)); 746 EXPECT_EQ("if (x)\n" 747 "`timescale 1ns / 1ps\n" 748 " `x = `x;", 749 format("if (x)\n" 750 "`timescale 1ns / 1ps\n" 751 "`x = `x;", 752 Style)); 753 std::string NonDirectives[] = { 754 // For `__FILE__` and `__LINE__`, although the standard classifies them as 755 // preprocessor directives, they are used like regular macros. 756 "__FILE__", "__LINE__", "elif", "foo", "x", 757 }; 758 for (auto &Name : NonDirectives) { 759 EXPECT_EQ("if (x)\n" 760 " `" + 761 Name + ";", 762 format("if (x)\n" 763 "`" + 764 Name + 765 "\n" 766 ";", 767 Style)); 768 } 769 } 770 771 TEST_F(FormatTestVerilog, Primitive) { 772 verifyFormat("primitive multiplexer\n" 773 " (mux, control, dataA, dataB);\n" 774 " output mux;\n" 775 " input control, dataA, dataB;\n" 776 " table\n" 777 " 0 1 ? : 1;\n" 778 " 0 0 ? : 0;\n" 779 " 1 ? 1 : 1;\n" 780 " 1 ? 0 : 0;\n" 781 " x 0 0 : 0;\n" 782 " x 1 1 : 1;\n" 783 " endtable\n" 784 "endprimitive"); 785 verifyFormat("primitive latch\n" 786 " (q, ena_, data);\n" 787 " output q;\n" 788 " reg q;\n" 789 " input ena_, data;\n" 790 " table\n" 791 " 0 1 : ? : 1;\n" 792 " 0 0 : ? : 0;\n" 793 " 1 ? : ? : -;\n" 794 " ? * : ? : -;\n" 795 " endtable\n" 796 "endprimitive"); 797 verifyFormat("primitive d\n" 798 " (q, clock, data);\n" 799 " output q;\n" 800 " reg q;\n" 801 " input clock, data;\n" 802 " table\n" 803 " (01) 0 : ? : 0;\n" 804 " (01) 1 : ? : 1;\n" 805 " (0?) 1 : 1 : 1;\n" 806 " (0?) 0 : 0 : 0;\n" 807 " (?0) ? : ? : -;\n" 808 " (?\?) ? : ? : -;\n" 809 " endtable\n" 810 "endprimitive"); 811 } 812 } // namespace format 813 } // end namespace clang 814