1 //===- unittest/Format/FormatTestVerilog.cpp ------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "FormatTestBase.h" 10 11 #define DEBUG_TYPE "format-test" 12 13 namespace clang { 14 namespace format { 15 namespace test { 16 namespace { 17 class FormatTestVerilog : public test::FormatTestBase { 18 protected: 19 FormatStyle getDefaultStyle() const override { 20 return getLLVMStyle(FormatStyle::LK_Verilog); 21 } 22 std::string messUp(llvm::StringRef Code) const override { 23 return test::messUp(Code, /*HandleHash=*/false); 24 } 25 }; 26 27 TEST_F(FormatTestVerilog, Align) { 28 FormatStyle Style = getDefaultStyle(); 29 Style.AlignConsecutiveAssignments.Enabled = true; 30 verifyFormat("x <= x;\n" 31 "sfdbddfbdfbb <= x;\n" 32 "x = x;", 33 Style); 34 verifyFormat("x = x;\n" 35 "sfdbddfbdfbb = x;\n" 36 "x = x;", 37 Style); 38 // Compound assignments are not aligned by default. '<=' is not a compound 39 // assignment. 40 verifyFormat("x <= x;\n" 41 "sfdbddfbdfbb <= x;", 42 Style); 43 verifyFormat("x += x;\n" 44 "sfdbddfbdfbb <= x;", 45 Style); 46 verifyFormat("x <<= x;\n" 47 "sfdbddfbdfbb <= x;", 48 Style); 49 verifyFormat("x <<<= x;\n" 50 "sfdbddfbdfbb <= x;", 51 Style); 52 verifyFormat("x >>= x;\n" 53 "sfdbddfbdfbb <= x;", 54 Style); 55 verifyFormat("x >>>= x;\n" 56 "sfdbddfbdfbb <= x;", 57 Style); 58 Style.AlignConsecutiveAssignments.AlignCompound = true; 59 verifyFormat("x <= x;\n" 60 "sfdbddfbdfbb <= x;", 61 Style); 62 verifyFormat("x += x;\n" 63 "sfdbddfbdfbb <= x;", 64 Style); 65 verifyFormat("x <<= x;\n" 66 "sfdbddfbdfbb <= x;", 67 Style); 68 verifyFormat("x <<<= x;\n" 69 "sfdbddfbdfbb <= x;", 70 Style); 71 verifyFormat("x >>= x;\n" 72 "sfdbddfbdfbb <= x;", 73 Style); 74 verifyFormat("x >>>= x;\n" 75 "sfdbddfbdfbb <= x;", 76 Style); 77 } 78 79 TEST_F(FormatTestVerilog, Assign) { 80 verifyFormat("assign mynet = enable;"); 81 verifyFormat("assign (strong1, pull0) #1 mynet = enable;"); 82 verifyFormat("assign #1 mynet = enable;"); 83 verifyFormat("assign mynet = enable;"); 84 // Test that assignments are on separate lines. 85 verifyFormat("assign mynet = enable,\n" 86 " mynet1 = enable1;"); 87 // Test that `<=` and `,` don't confuse it. 88 verifyFormat("assign mynet = enable1 <= enable2;"); 89 verifyFormat("assign mynet = enable1 <= enable2,\n" 90 " mynet1 = enable3;"); 91 verifyFormat("assign mynet = enable,\n" 92 " mynet1 = enable2 <= enable3;"); 93 verifyFormat("assign mynet = enable(enable1, enable2);"); 94 } 95 96 TEST_F(FormatTestVerilog, BasedLiteral) { 97 verifyFormat("x = '0;"); 98 verifyFormat("x = '1;"); 99 verifyFormat("x = 'X;"); 100 verifyFormat("x = 'x;"); 101 verifyFormat("x = 'Z;"); 102 verifyFormat("x = 'z;"); 103 verifyFormat("x = 659;"); 104 verifyFormat("x = 'h837ff;"); 105 verifyFormat("x = 'o7460;"); 106 verifyFormat("x = 4'b1001;"); 107 verifyFormat("x = 5'D3;"); 108 verifyFormat("x = 3'b01x;"); 109 verifyFormat("x = 12'hx;"); 110 verifyFormat("x = 16'hz;"); 111 verifyFormat("x = -8'd6;"); 112 verifyFormat("x = 4'shf;"); 113 verifyFormat("x = -4'sd15;"); 114 verifyFormat("x = 16'sd?;"); 115 } 116 117 TEST_F(FormatTestVerilog, Block) { 118 verifyFormat("begin\n" 119 " x = x;\n" 120 "end"); 121 verifyFormat("begin : x\n" 122 " x = x;\n" 123 "end : x"); 124 verifyFormat("begin\n" 125 " x = x;\n" 126 " x = x;\n" 127 "end"); 128 verifyFormat("fork\n" 129 " x = x;\n" 130 "join"); 131 verifyFormat("fork\n" 132 " x = x;\n" 133 "join_any"); 134 verifyFormat("fork\n" 135 " x = x;\n" 136 "join_none"); 137 verifyFormat("generate\n" 138 " x = x;\n" 139 "endgenerate"); 140 verifyFormat("generate : x\n" 141 " x = x;\n" 142 "endgenerate : x"); 143 // Nested blocks. 144 verifyFormat("begin\n" 145 " begin\n" 146 " end\n" 147 "end"); 148 verifyFormat("begin : x\n" 149 " begin\n" 150 " end\n" 151 "end : x"); 152 verifyFormat("begin : x\n" 153 " begin : x\n" 154 " end : x\n" 155 "end : x"); 156 verifyFormat("begin\n" 157 " begin : x\n" 158 " end : x\n" 159 "end"); 160 // Test that 'disable fork' and 'rand join' don't get mistaken as blocks. 161 verifyFormat("disable fork;\n" 162 "x = x;"); 163 verifyFormat("rand join x x;\n" 164 "x = x;"); 165 } 166 167 TEST_F(FormatTestVerilog, Case) { 168 verifyFormat("case (data)\n" 169 "endcase"); 170 verifyFormat("casex (data)\n" 171 "endcase"); 172 verifyFormat("casez (data)\n" 173 "endcase"); 174 verifyFormat("case (data) inside\n" 175 "endcase"); 176 verifyFormat("case (data)\n" 177 " 16'd0:\n" 178 " result = 10'b0111111111;\n" 179 "endcase"); 180 verifyFormat("case (data)\n" 181 " xxxxxxxx:\n" 182 " result = 10'b0111111111;\n" 183 "endcase"); 184 // Test labels with multiple options. 185 verifyFormat("case (data)\n" 186 " 16'd0, 16'd1:\n" 187 " result = 10'b0111111111;\n" 188 "endcase"); 189 verifyFormat("case (data)\n" 190 " 16'd0, //\n" 191 " 16'd1:\n" 192 " result = 10'b0111111111;\n" 193 "endcase"); 194 // Test that blocks following labels are indented. 195 verifyFormat("case (data)\n" 196 " 16'd1: fork\n" 197 " result = 10'b1011111111;\n" 198 " join\n" 199 "endcase\n"); 200 verifyFormat("case (data)\n" 201 " 16'd1: fork : x\n" 202 " result = 10'b1011111111;\n" 203 " join : x\n" 204 "endcase\n"); 205 // Test default. 206 verifyFormat("case (data)\n" 207 " default\n" 208 " result = 10'b1011111111;\n" 209 "endcase"); 210 verifyFormat("case (data)\n" 211 " default:\n" 212 " result = 10'b1011111111;\n" 213 "endcase"); 214 // Test that question marks and colons don't get mistaken as labels. 215 verifyFormat("case (data)\n" 216 " 8'b1???????:\n" 217 " instruction1(ir);\n" 218 "endcase"); 219 verifyFormat("case (data)\n" 220 " x ? 8'b1??????? : 1:\n" 221 " instruction3(ir);\n" 222 "endcase"); 223 // Test indention options. 224 auto Style = getDefaultStyle(); 225 Style.IndentCaseLabels = false; 226 verifyFormat("case (data)\n" 227 "16'd0:\n" 228 " result = 10'b0111111111;\n" 229 "endcase", 230 Style); 231 verifyFormat("case (data)\n" 232 "16'd0: begin\n" 233 " result = 10'b0111111111;\n" 234 "end\n" 235 "endcase", 236 Style); 237 Style.IndentCaseLabels = true; 238 verifyFormat("case (data)\n" 239 " 16'd0:\n" 240 " result = 10'b0111111111;\n" 241 "endcase", 242 Style); 243 verifyFormat("case (data)\n" 244 " 16'd0: begin\n" 245 " result = 10'b0111111111;\n" 246 " end\n" 247 "endcase", 248 Style); 249 // Other colons should not be mistaken as case colons. 250 Style = getDefaultStyle(); 251 Style.BitFieldColonSpacing = FormatStyle::BFCS_None; 252 verifyFormat("case (x[1:0])\n" 253 "endcase", 254 Style); 255 verifyFormat("default:\n" 256 " x[1:0] = x[1:0];", 257 Style); 258 Style.BitFieldColonSpacing = FormatStyle::BFCS_Both; 259 verifyFormat("case (x[1 : 0])\n" 260 "endcase", 261 Style); 262 verifyFormat("default:\n" 263 " x[1 : 0] = x[1 : 0];", 264 Style); 265 Style = getDefaultStyle(); 266 Style.SpacesInContainerLiterals = true; 267 verifyFormat("case ('{x : x, default : 9})\n" 268 "endcase", 269 Style); 270 verifyFormat("x = '{x : x, default : 9};\n", Style); 271 verifyFormat("default:\n" 272 " x = '{x : x, default : 9};\n", 273 Style); 274 Style.SpacesInContainerLiterals = false; 275 verifyFormat("case ('{x: x, default: 9})\n" 276 "endcase", 277 Style); 278 verifyFormat("x = '{x: x, default: 9};\n", Style); 279 verifyFormat("default:\n" 280 " x = '{x: x, default: 9};\n", 281 Style); 282 } 283 284 TEST_F(FormatTestVerilog, Coverage) { 285 verifyFormat("covergroup x\n" 286 " @@(begin x);\n" 287 "endgroup"); 288 } 289 290 TEST_F(FormatTestVerilog, Declaration) { 291 verifyFormat("wire mynet;"); 292 verifyFormat("wire mynet, mynet1;"); 293 verifyFormat("wire mynet, //\n" 294 " mynet1;"); 295 verifyFormat("wire mynet = enable;"); 296 verifyFormat("wire mynet = enable, mynet1;"); 297 verifyFormat("wire mynet = enable, //\n" 298 " mynet1;"); 299 verifyFormat("wire mynet, mynet1 = enable;"); 300 verifyFormat("wire mynet, //\n" 301 " mynet1 = enable;"); 302 verifyFormat("wire mynet = enable, mynet1 = enable;"); 303 verifyFormat("wire mynet = enable, //\n" 304 " mynet1 = enable;"); 305 verifyFormat("wire (strong1, pull0) mynet;"); 306 verifyFormat("wire (strong1, pull0) mynet, mynet1;"); 307 verifyFormat("wire (strong1, pull0) mynet, //\n" 308 " mynet1;"); 309 verifyFormat("wire (strong1, pull0) mynet = enable;"); 310 verifyFormat("wire (strong1, pull0) mynet = enable, mynet1;"); 311 verifyFormat("wire (strong1, pull0) mynet = enable, //\n" 312 " mynet1;"); 313 verifyFormat("wire (strong1, pull0) mynet, mynet1 = enable;"); 314 verifyFormat("wire (strong1, pull0) mynet, //\n" 315 " mynet1 = enable;"); 316 } 317 318 TEST_F(FormatTestVerilog, Delay) { 319 // Delay by the default unit. 320 verifyFormat("#0;"); 321 verifyFormat("#1;"); 322 verifyFormat("#10;"); 323 verifyFormat("#1.5;"); 324 // Explicit unit. 325 verifyFormat("#1fs;"); 326 verifyFormat("#1.5fs;"); 327 verifyFormat("#1ns;"); 328 verifyFormat("#1.5ns;"); 329 verifyFormat("#1us;"); 330 verifyFormat("#1.5us;"); 331 verifyFormat("#1ms;"); 332 verifyFormat("#1.5ms;"); 333 verifyFormat("#1s;"); 334 verifyFormat("#1.5s;"); 335 // The following expression should be on the same line. 336 verifyFormat("#1 x = x;"); 337 verifyFormat("#1 x = x;", "#1\n" 338 "x = x;"); 339 } 340 341 TEST_F(FormatTestVerilog, Headers) { 342 // Test headers with multiple ports. 343 verifyFormat("module mh1\n" 344 " (input var int in1,\n" 345 " input var shortreal in2,\n" 346 " output tagged_st out);\n" 347 "endmodule"); 348 // Ports should be grouped by types. 349 verifyFormat("module test\n" 350 " (input [7 : 0] a,\n" 351 " input signed [7 : 0] b, c, d);\n" 352 "endmodule"); 353 verifyFormat("module test\n" 354 " (input [7 : 0] a,\n" 355 " (* x = x *) input signed [7 : 0] b, c, d);\n" 356 "endmodule"); 357 verifyFormat("module test\n" 358 " (input [7 : 0] a = 0,\n" 359 " input signed [7 : 0] b = 0, c = 0, d = 0);\n" 360 "endmodule"); 361 verifyFormat("module test\n" 362 " #(parameter x)\n" 363 " (input [7 : 0] a,\n" 364 " input signed [7 : 0] b, c, d);\n" 365 "endmodule"); 366 // When a line needs to be broken, ports of the same type should be aligned to 367 // the same column. 368 verifyFormat("module test\n" 369 " (input signed [7 : 0] b, c, //\n" 370 " d);\n" 371 "endmodule"); 372 verifyFormat("module test\n" 373 " ((* x = x *) input signed [7 : 0] b, c, //\n" 374 " d);\n" 375 "endmodule"); 376 verifyFormat("module test\n" 377 " (input signed [7 : 0] b = 0, c, //\n" 378 " d);\n" 379 "endmodule"); 380 verifyFormat("module test\n" 381 " (input signed [7 : 0] b, c = 0, //\n" 382 " d);\n" 383 "endmodule"); 384 verifyFormat("module test\n" 385 " (input signed [7 : 0] b, c, //\n" 386 " d = 0);\n" 387 "endmodule"); 388 verifyFormat("module test\n" 389 " (input wire logic signed [7 : 0][0 : 1] b, c, //\n" 390 " d);\n" 391 "endmodule"); 392 verifyFormat("module test\n" 393 " (input signed [7 : 0] b, //\n" 394 " c, //\n" 395 " d);\n" 396 "endmodule"); 397 verifyFormat("module test\n" 398 " (input [7 : 0] a,\n" 399 " input signed [7 : 0] b, //\n" 400 " c, //\n" 401 " d);\n" 402 "endmodule"); 403 verifyFormat("module test\n" 404 " (input signed [7 : 0] b, //\n" 405 " c, //\n" 406 " d,\n" 407 " output signed [7 : 0] h);\n" 408 "endmodule"); 409 // With a modport. 410 verifyFormat("module m\n" 411 " (i2.master i);\n" 412 "endmodule"); 413 verifyFormat("module m\n" 414 " (i2.master i, ii);\n" 415 "endmodule"); 416 verifyFormat("module m\n" 417 " (i2.master i, //\n" 418 " ii);\n" 419 "endmodule"); 420 verifyFormat("module m\n" 421 " (i2.master i,\n" 422 " input ii);\n" 423 "endmodule"); 424 verifyFormat("module m\n" 425 " (i2::i2.master i);\n" 426 "endmodule"); 427 verifyFormat("module m\n" 428 " (i2::i2.master i, ii);\n" 429 "endmodule"); 430 verifyFormat("module m\n" 431 " (i2::i2.master i, //\n" 432 " ii);\n" 433 "endmodule"); 434 verifyFormat("module m\n" 435 " (i2::i2.master i,\n" 436 " input ii);\n" 437 "endmodule"); 438 verifyFormat("module m\n" 439 " (i2::i2 i);\n" 440 "endmodule"); 441 verifyFormat("module m\n" 442 " (i2::i2 i, ii);\n" 443 "endmodule"); 444 verifyFormat("module m\n" 445 " (i2::i2 i, //\n" 446 " ii);\n" 447 "endmodule"); 448 verifyFormat("module m\n" 449 " (i2::i2 i,\n" 450 " input ii);\n" 451 "endmodule"); 452 // With a macro in the names. 453 verifyFormat("module m\n" 454 " (input var `x a, b);\n" 455 "endmodule"); 456 verifyFormat("module m\n" 457 " (input var `x a, //\n" 458 " b);\n" 459 "endmodule"); 460 verifyFormat("module m\n" 461 " (input var x `a, b);\n" 462 "endmodule"); 463 verifyFormat("module m\n" 464 " (input var x `a, //\n" 465 " b);\n" 466 "endmodule"); 467 // With a concatenation in the names. 468 auto Style = getDefaultStyle(); 469 Style.ColumnLimit = 40; 470 verifyFormat("`define X(x) \\\n" 471 " module test \\\n" 472 " (input var x``x a, b);", 473 Style); 474 verifyFormat("`define X(x) \\\n" 475 " module test \\\n" 476 " (input var x``x aaaaaaaaaaaaaaa, \\\n" 477 " b);", 478 Style); 479 verifyFormat("`define X(x) \\\n" 480 " module test \\\n" 481 " (input var x a``x, b);", 482 Style); 483 verifyFormat("`define X(x) \\\n" 484 " module test \\\n" 485 " (input var x aaaaaaaaaaaaaaa``x, \\\n" 486 " b);", 487 Style); 488 } 489 490 TEST_F(FormatTestVerilog, Hierarchy) { 491 verifyFormat("module x;\n" 492 "endmodule"); 493 // Test that the end label is on the same line as the end keyword. 494 verifyFormat("module x;\n" 495 "endmodule : x"); 496 // Test that things inside are indented. 497 verifyFormat("module x;\n" 498 " generate\n" 499 " endgenerate\n" 500 "endmodule"); 501 verifyFormat("program x;\n" 502 " generate\n" 503 " endgenerate\n" 504 "endprogram"); 505 verifyFormat("interface x;\n" 506 " generate\n" 507 " endgenerate\n" 508 "endinterface"); 509 verifyFormat("task x;\n" 510 " generate\n" 511 " endgenerate\n" 512 "endtask"); 513 verifyFormat("function x;\n" 514 " generate\n" 515 " endgenerate\n" 516 "endfunction"); 517 verifyFormat("class x;\n" 518 " generate\n" 519 " endgenerate\n" 520 "endclass"); 521 // Test that they nest. 522 verifyFormat("module x;\n" 523 " program x;\n" 524 " program x;\n" 525 " endprogram\n" 526 " endprogram\n" 527 "endmodule"); 528 // Test that an extern declaration doesn't change the indentation. 529 verifyFormat("extern module x;\n" 530 "x = x;"); 531 // Test complex headers 532 verifyFormat("extern module x\n" 533 " import x.x::x::*;\n" 534 " import x;\n" 535 " #(parameter x)\n" 536 " (output x);"); 537 verifyFormat("module x\n" 538 " import x.x::x::*;\n" 539 " import x;\n" 540 " #(parameter x)\n" 541 " (output x);\n" 542 " generate\n" 543 " endgenerate\n" 544 "endmodule : x"); 545 verifyFormat("virtual class x\n" 546 " (x)\n" 547 " extends x(x)\n" 548 " implements x, x, x;\n" 549 " generate\n" 550 " endgenerate\n" 551 "endclass : x\n"); 552 verifyFormat("function automatic logic [1 : 0] x\n" 553 " (input x);\n" 554 " generate\n" 555 " endgenerate\n" 556 "endfunction : x"); 557 } 558 559 TEST_F(FormatTestVerilog, Identifiers) { 560 // Escaped identifiers should not be split. 561 verifyFormat("\\busa+index"); 562 verifyFormat("\\-clock"); 563 verifyFormat("\\***error-condition***"); 564 verifyFormat("\\net1\\/net2"); 565 verifyFormat("\\{a,b}"); 566 verifyFormat("\\a*(b+c)"); 567 // Escaped identifiers can't be joined with the next token. Extra space 568 // should be removed. 569 verifyFormat("\\busa+index ;", "\\busa+index\n" 570 ";"); 571 verifyFormat("\\busa+index ;", "\\busa+index\r\n" 572 ";"); 573 verifyFormat("\\busa+index ;", "\\busa+index ;"); 574 verifyFormat("\\busa+index ;", "\\busa+index\n" 575 " ;"); 576 verifyFormat("\\busa+index ;"); 577 verifyFormat("(\\busa+index );"); 578 verifyFormat("\\busa+index \\busa+index ;"); 579 } 580 581 TEST_F(FormatTestVerilog, If) { 582 verifyFormat("if (x)\n" 583 " x = x;"); 584 verifyFormat("unique if (x)\n" 585 " x = x;"); 586 verifyFormat("unique0 if (x)\n" 587 " x = x;"); 588 verifyFormat("priority if (x)\n" 589 " x = x;"); 590 verifyFormat("if (x)\n" 591 " x = x;\n" 592 "x = x;"); 593 594 // Test else 595 verifyFormat("if (x)\n" 596 " x = x;\n" 597 "else if (x)\n" 598 " x = x;\n" 599 "else\n" 600 " x = x;"); 601 verifyFormat("if (x) begin\n" 602 " x = x;\n" 603 "end else if (x) begin\n" 604 " x = x;\n" 605 "end else begin\n" 606 " x = x;\n" 607 "end"); 608 verifyFormat("if (x) begin : x\n" 609 " x = x;\n" 610 "end : x else if (x) begin : x\n" 611 " x = x;\n" 612 "end : x else begin : x\n" 613 " x = x;\n" 614 "end : x"); 615 616 // Test block keywords. 617 verifyFormat("if (x) begin\n" 618 " x = x;\n" 619 "end"); 620 verifyFormat("if (x) begin : x\n" 621 " x = x;\n" 622 "end : x"); 623 verifyFormat("if (x) begin\n" 624 " x = x;\n" 625 " x = x;\n" 626 "end"); 627 verifyFormat("if (x) fork\n" 628 " x = x;\n" 629 "join"); 630 verifyFormat("if (x) fork\n" 631 " x = x;\n" 632 "join_any"); 633 verifyFormat("if (x) fork\n" 634 " x = x;\n" 635 "join_none"); 636 verifyFormat("if (x) generate\n" 637 " x = x;\n" 638 "endgenerate"); 639 verifyFormat("if (x) generate : x\n" 640 " x = x;\n" 641 "endgenerate : x"); 642 643 // Test that concatenation braces don't get regarded as blocks. 644 verifyFormat("if (x)\n" 645 " {x} = x;"); 646 verifyFormat("if (x)\n" 647 " x = {x};"); 648 verifyFormat("if (x)\n" 649 " x = {x};\n" 650 "else\n" 651 " {x} = {x};"); 652 653 // With attributes. 654 verifyFormat("(* x *) if (x)\n" 655 " x = x;"); 656 verifyFormat("(* x = \"x\" *) if (x)\n" 657 " x = x;"); 658 verifyFormat("(* x, x = \"x\" *) if (x)\n" 659 " x = x;"); 660 } 661 662 TEST_F(FormatTestVerilog, Operators) { 663 // Test that unary operators are not followed by space. 664 verifyFormat("x = +x;"); 665 verifyFormat("x = -x;"); 666 verifyFormat("x = !x;"); 667 verifyFormat("x = ~x;"); 668 verifyFormat("x = &x;"); 669 verifyFormat("x = ~&x;"); 670 verifyFormat("x = |x;"); 671 verifyFormat("x = ~|x;"); 672 verifyFormat("x = ^x;"); 673 verifyFormat("x = ~^x;"); 674 verifyFormat("x = ^~x;"); 675 verifyFormat("x = ++x;"); 676 verifyFormat("x = --x;"); 677 678 // Test that `*` and `*>` are binary. 679 verifyFormat("x = x * x;"); 680 verifyFormat("x = (x * x);"); 681 verifyFormat("(opcode *> o1) = 6.1;"); 682 verifyFormat("(C, D *> Q) = 18;"); 683 // The wildcard import is not a binary operator. 684 verifyFormat("import p::*;"); 685 686 // Test that operators don't get split. 687 verifyFormat("x = x++;"); 688 verifyFormat("x = x--;"); 689 verifyFormat("x = x ** x;"); 690 verifyFormat("x = x << x;"); 691 verifyFormat("x = x >> x;"); 692 verifyFormat("x = x <<< x;"); 693 verifyFormat("x = x >>> x;"); 694 verifyFormat("x = x <= x;"); 695 verifyFormat("x = x >= x;"); 696 verifyFormat("x = x == x;"); 697 verifyFormat("x = x != x;"); 698 verifyFormat("x = x === x;"); 699 verifyFormat("x = x !== x;"); 700 verifyFormat("x = x ==? x;"); 701 verifyFormat("x = x !=? x;"); 702 verifyFormat("x = x ~^ x;"); 703 verifyFormat("x = x ^~ x;"); 704 verifyFormat("x = x && x;"); 705 verifyFormat("x = x || x;"); 706 verifyFormat("x = x->x;"); 707 verifyFormat("x = x <-> x;"); 708 verifyFormat("x += x;"); 709 verifyFormat("x -= x;"); 710 verifyFormat("x *= x;"); 711 verifyFormat("x /= x;"); 712 verifyFormat("x %= x;"); 713 verifyFormat("x &= x;"); 714 verifyFormat("x ^= x;"); 715 verifyFormat("x |= x;"); 716 verifyFormat("x <<= x;"); 717 verifyFormat("x >>= x;"); 718 verifyFormat("x <<<= x;"); 719 verifyFormat("x >>>= x;"); 720 verifyFormat("x <= x;"); 721 722 // Test that space is added between operators. 723 verifyFormat("x = x < -x;", "x=x<-x;"); 724 verifyFormat("x = x << -x;", "x=x<<-x;"); 725 verifyFormat("x = x <<< -x;", "x=x<<<-x;"); 726 727 // Test that operators that are C++ identifiers get treated as operators. 728 verifyFormat("solve s before d;"); // before 729 verifyFormat("binsof(i) intersect {0};"); // intersect 730 verifyFormat("req dist {1};"); // dist 731 verifyFormat("a inside {b, c};"); // inside 732 verifyFormat("bus.randomize() with { atype == low; };"); // with 733 } 734 735 TEST_F(FormatTestVerilog, Preprocessor) { 736 auto Style = getDefaultStyle(); 737 Style.ColumnLimit = 20; 738 739 // Macro definitions. 740 verifyFormat("`define X \\\n" 741 " if (x) \\\n" 742 " x = x;", 743 "`define X if(x)x=x;", Style); 744 verifyFormat("`define X(x) \\\n" 745 " if (x) \\\n" 746 " x = x;", 747 "`define X(x) if(x)x=x;", Style); 748 verifyFormat("`define X \\\n" 749 " x = x; \\\n" 750 " x = x;", 751 "`define X x=x;x=x;", Style); 752 // Macro definitions with invocations inside. 753 verifyFormat("`define LIST \\\n" 754 " `ENTRY \\\n" 755 " `ENTRY", 756 "`define LIST \\\n" 757 "`ENTRY \\\n" 758 "`ENTRY", 759 Style); 760 verifyFormat("`define LIST \\\n" 761 " `x = `x; \\\n" 762 " `x = `x;", 763 "`define LIST \\\n" 764 "`x = `x; \\\n" 765 "`x = `x;", 766 Style); 767 verifyFormat("`define LIST \\\n" 768 " `x = `x; \\\n" 769 " `x = `x;", 770 "`define LIST `x=`x;`x=`x;", Style); 771 // Macro invocations. 772 verifyFormat("`x = (`x1 + `x2 + x);"); 773 // Lines starting with a preprocessor directive should not be indented. 774 std::string Directives[] = { 775 "begin_keywords", 776 "celldefine", 777 "default_nettype", 778 "define", 779 "else", 780 "elsif", 781 "end_keywords", 782 "endcelldefine", 783 "endif", 784 "ifdef", 785 "ifndef", 786 "include", 787 "line", 788 "nounconnected_drive", 789 "pragma", 790 "resetall", 791 "timescale", 792 "unconnected_drive", 793 "undef", 794 "undefineall", 795 }; 796 for (auto &Name : Directives) { 797 verifyFormat("if (x)\n" 798 "`" + 799 Name + 800 "\n" 801 " ;", 802 "if (x)\n" 803 "`" + 804 Name + 805 "\n" 806 ";", 807 Style); 808 } 809 // Lines starting with a regular macro invocation should be indented as a 810 // normal line. 811 verifyFormat("if (x)\n" 812 " `x = `x;\n" 813 "`timescale 1ns / 1ps", 814 "if (x)\n" 815 "`x = `x;\n" 816 "`timescale 1ns / 1ps", 817 Style); 818 verifyFormat("if (x)\n" 819 "`timescale 1ns / 1ps\n" 820 " `x = `x;", 821 "if (x)\n" 822 "`timescale 1ns / 1ps\n" 823 "`x = `x;", 824 Style); 825 std::string NonDirectives[] = { 826 // For `__FILE__` and `__LINE__`, although the standard classifies them as 827 // preprocessor directives, they are used like regular macros. 828 "__FILE__", "__LINE__", "elif", "foo", "x", 829 }; 830 for (auto &Name : NonDirectives) { 831 verifyFormat("if (x)\n" 832 " `" + 833 Name + ";", 834 "if (x)\n" 835 "`" + 836 Name + 837 "\n" 838 ";", 839 Style); 840 } 841 } 842 843 TEST_F(FormatTestVerilog, Primitive) { 844 verifyFormat("primitive multiplexer\n" 845 " (mux, control, dataA, dataB);\n" 846 " output mux;\n" 847 " input control, dataA, dataB;\n" 848 " table\n" 849 " 0 1 ? : 1;\n" 850 " 0 0 ? : 0;\n" 851 " 1 ? 1 : 1;\n" 852 " 1 ? 0 : 0;\n" 853 " x 0 0 : 0;\n" 854 " x 1 1 : 1;\n" 855 " endtable\n" 856 "endprimitive"); 857 verifyFormat("primitive latch\n" 858 " (q, ena_, data);\n" 859 " output q;\n" 860 " reg q;\n" 861 " input ena_, data;\n" 862 " table\n" 863 " 0 1 : ? : 1;\n" 864 " 0 0 : ? : 0;\n" 865 " 1 ? : ? : -;\n" 866 " ? * : ? : -;\n" 867 " endtable\n" 868 "endprimitive"); 869 verifyFormat("primitive d\n" 870 " (q, clock, data);\n" 871 " output q;\n" 872 " reg q;\n" 873 " input clock, data;\n" 874 " table\n" 875 " (01) 0 : ? : 0;\n" 876 " (01) 1 : ? : 1;\n" 877 " (0?) 1 : 1 : 1;\n" 878 " (0?) 0 : 0 : 0;\n" 879 " (?0) ? : ? : -;\n" 880 " (?\?) ? : ? : -;\n" 881 " endtable\n" 882 "endprimitive"); 883 } 884 885 TEST_F(FormatTestVerilog, Streaming) { 886 verifyFormat("x = {>>{j}};"); 887 verifyFormat("x = {>>byte{j}};"); 888 verifyFormat("x = {<<{j}};"); 889 verifyFormat("x = {<<byte{j}};"); 890 verifyFormat("x = {<<16{j}};"); 891 verifyFormat("x = {<<{8'b0011_0101}};"); 892 verifyFormat("x = {<<4{6'b11_0101}};"); 893 verifyFormat("x = {>>4{6'b11_0101}};"); 894 verifyFormat("x = {<<2{{<<{4'b1101}}}};"); 895 verifyFormat("bit [96 : 1] y = {>>{a, b, c}};"); 896 verifyFormat("int j = {>>{a, b, c}};"); 897 verifyFormat("{>>{a, b, c}} = 23'b1;"); 898 verifyFormat("{>>{a, b, c}} = x;"); 899 verifyFormat("{>>{j}} = x;"); 900 verifyFormat("{>>byte{j}} = x;"); 901 verifyFormat("{<<{j}} = x;"); 902 verifyFormat("{<<byte{j}} = x;"); 903 } 904 905 TEST_F(FormatTestVerilog, StructuredProcedure) { 906 // Blocks should be indented correctly. 907 verifyFormat("initial begin\n" 908 "end"); 909 verifyFormat("initial begin\n" 910 " x <= x;\n" 911 " x <= x;\n" 912 "end"); 913 verifyFormat("initial\n" 914 " x <= x;\n" 915 "x <= x;"); 916 verifyFormat("always @(x) begin\n" 917 "end"); 918 verifyFormat("always @(x) begin\n" 919 " x <= x;\n" 920 " x <= x;\n" 921 "end"); 922 verifyFormat("always @(x)\n" 923 " x <= x;\n" 924 "x <= x;"); 925 // Various keywords. 926 verifyFormat("always @(x)\n" 927 " x <= x;"); 928 verifyFormat("always @(posedge x)\n" 929 " x <= x;"); 930 verifyFormat("always\n" 931 " x <= x;"); 932 verifyFormat("always @*\n" 933 " x <= x;"); 934 verifyFormat("always @(*)\n" 935 " x <= x;"); 936 verifyFormat("always_comb\n" 937 " x <= x;"); 938 verifyFormat("always_latch @(x)\n" 939 " x <= x;"); 940 verifyFormat("always_ff @(posedge x)\n" 941 " x <= x;"); 942 verifyFormat("initial\n" 943 " x <= x;"); 944 verifyFormat("final\n" 945 " x <= x;"); 946 verifyFormat("forever\n" 947 " x <= x;"); 948 } 949 } // namespace 950 } // namespace test 951 } // namespace format 952 } // namespace clang 953