1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -DBODY -triple x86_64-unknown-unknown -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=CHECK1 3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fnoopenmp-use-tls -DBODY -triple x86_64-unknown-unknown -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=CHECK2 4 5 // RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -DBODY -triple x86_64-unknown-unknown -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck --check-prefix SIMD1 %s 6 // RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 7 // RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -DBODY -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD2 %s 8 // RUN: %clang_cc1 -verify -fopenmp -DBODY -triple x86_64-unknown-unknown -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=CHECK-TLS1 9 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -DBODY -triple x86_64-unknown-unknown -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=CHECK-TLS2 10 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 11 // RUN: %clang_cc1 -fopenmp -DBODY -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefixes=CHECK-TLS3 %s 12 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 13 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -DBODY -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefixes=CHECK-TLS4 %s 14 15 // RUN: %clang_cc1 -verify -fopenmp-simd -DBODY -triple x86_64-unknown-unknown -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck --check-prefix SIMD3 %s 16 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 17 // RUN: %clang_cc1 -fopenmp-simd -DBODY -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD4 %s 18 19 // RUN: %clang_cc1 -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 20 // RUN: %clang_cc1 -fopenmp -fnoopenmp-use-tls -DBODY -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefixes=DEBUG1 %s 21 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 22 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fnoopenmp-use-tls -DBODY -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefixes=DEBUG2 %s 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 struct S1 { 28 int a; 29 S1() 30 : a(0) { 31 } 32 S1(int a) 33 : a(a) { 34 } 35 S1(const S1 &s) { 36 a = 12 + s.a; 37 } 38 ~S1() { 39 a = 0; 40 } 41 }; 42 43 struct S2 { 44 int a; 45 double b; 46 S2() 47 : a(0) { 48 } 49 S2(int a) 50 : a(a) { 51 } 52 S2(const S2 &s) { 53 a = 12 + s.a; 54 } 55 ~S2() { 56 a = 0; 57 } 58 }; 59 60 struct S3 { 61 int a; 62 float b; 63 S3() 64 : a(0) { 65 } 66 S3(int a) 67 : a(a) { 68 } 69 S3(const S3 &s) { 70 a = 12 + s.a; 71 } 72 ~S3() { 73 a = 0; 74 } 75 }; 76 77 struct S4 { 78 int a, b; 79 S4() 80 : a(0) { 81 } 82 S4(int a) 83 : a(a) { 84 } 85 S4(const S4 &s) { 86 a = 12 + s.a; 87 } 88 ~S4() { 89 a = 0; 90 } 91 }; 92 93 struct S5 { 94 int a, b, c; 95 S5() 96 : a(0) { 97 } 98 S5(int a) 99 : a(a) { 100 } 101 S5(const S5 &s) { 102 a = 12 + s.a; 103 } 104 ~S5() { 105 a = 0; 106 } 107 }; 108 109 // CHECK-DAG: [[GS1:@.+]] = internal global [[S1]] zeroinitializer 110 // CHECK-DAG: [[GS1]].cache. = common{{.*}} global ptr null 111 // CHECK-DAG: [[DEFAULT_LOC:@.+]] = private unnamed_addr constant [[IDENT]] { i32 0, i32 2, i32 0, i32 0, ptr {{@.+}} } 112 // CHECK-DAG: [[GS2:@.+]] = internal global [[S2]] zeroinitializer 113 // CHECK-DAG: [[ARR_X:@.+]] ={{.*}} global [2 x [3 x [[S1]]]] zeroinitializer 114 // CHECK-DAG: [[ARR_X]].cache. = common{{.*}} global ptr null 115 // CHECK-DAG: [[SM:@.+]] = internal global [[SMAIN]] zeroinitializer 116 // CHECK-DAG: [[SM]].cache. = common{{.*}} global ptr null 117 // CHECK-DAG: [[STATIC_S:@.+]] = external global [[S3]] 118 // CHECK-DAG: [[STATIC_S]].cache. = common{{.*}} global ptr null 119 // CHECK-DAG: [[GS3:@.+]] = external global [[S5]] 120 // CHECK-DAG: [[GS3]].cache. = common{{.*}} global ptr null 121 // CHECK-DAG: [[ST_INT_ST:@.+]] = linkonce_odr global i32 23 122 // CHECK-DAG: [[ST_INT_ST]].cache. = common{{.*}} global ptr null 123 // CHECK-DAG: [[ST_FLOAT_ST:@.+]] = linkonce_odr global float 2.300000e+01 124 // CHECK-DAG: [[ST_FLOAT_ST]].cache. = common{{.*}} global ptr null 125 // CHECK-DAG: [[ST_S4_ST:@.+]] = linkonce_odr global %struct.S4 zeroinitializer 126 // CHECK-DAG: [[ST_S4_ST]].cache. = common{{.*}} global ptr null 127 // CHECK-NOT: .cache. = common{{.*}} global ptr null 128 // There is no cache for gs2 - it is not threadprivate. Check that there is only 129 // 8 caches created (for Static::s, gs1, gs3, arr_x, main::sm, ST<int>::st, 130 // ST<float>::st, ST<S4>::st) 131 // CHECK-DEBUG-DAG: [[GS1:@.+]] = internal global [[S1]] zeroinitializer 132 // CHECK-DEBUG-DAG: [[GS2:@.+]] = internal global [[S2]] zeroinitializer 133 // CHECK-DEBUG-DAG: [[ARR_X:@.+]] ={{.*}} global [2 x [3 x [[S1]]]] zeroinitializer 134 // CHECK-DEBUG-DAG: [[SM:@.+]] = internal global [[SMAIN]] zeroinitializer 135 // CHECK-DEBUG-DAG: [[STATIC_S:@.+]] = external global [[S3]] 136 // CHECK-DEBUG-DAG: [[GS3:@.+]] = external global [[S5]] 137 // CHECK-DEBUG-DAG: [[ST_INT_ST:@.+]] = linkonce_odr global i32 23 138 // CHECK-DEBUG-DAG: [[ST_FLOAT_ST:@.+]] = linkonce_odr global float 2.300000e+01 139 // CHECK-DEBUG-DAG: [[ST_S4_ST:@.+]] = linkonce_odr global %struct.S4 zeroinitializer 140 141 // CHECK-DEBUG-DAG: [[LOC1:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;;249;1;;\00" 142 // CHECK-DEBUG-DAG: [[ID1:@.*]] = private unnamed_addr constant %struct.ident_t { {{.*}} [[LOC1]] 143 // CHECK-DEBUG-DAG: [[LOC2:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;;304;1;;\00" 144 // CHECK-DEBUG-DAG: [[ID2:@.*]] = private unnamed_addr constant %struct.ident_t { {{.*}} [[LOC2]] 145 // CHECK-DEBUG-DAG: [[LOC3:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;;422;19;;\00" 146 // CHECK-DEBUG-DAG: [[LOC4:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;main;459;1;;\00" 147 // CHECK-DEBUG-DAG: [[LOC5:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;main;476;9;;\00" 148 // CHECK-DEBUG-DAG: [[LOC6:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;main;498;10;;\00" 149 // CHECK-DEBUG-DAG: [[LOC7:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;main;521;10;;\00" 150 // CHECK-DEBUG-DAG: [[LOC8:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;main;557;10;;\00" 151 // CHECK-DEBUG-DAG: [[LOC9:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;main;586;10;;\00" 152 // CHECK-DEBUG-DAG: [[LOC10:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;main;606;10;;\00" 153 // CHECK-DEBUG-DAG: [[LOC11:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;main;629;27;;\00" 154 // CHECK-DEBUG-DAG: [[LOC12:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;main;652;10;;\00" 155 // CHECK-DEBUG-DAG: [[LOC13:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;foobar;774;9;;\00" 156 // CHECK-DEBUG-DAG: [[LOC14:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;foobar;797;10;;\00" 157 // CHECK-DEBUG-DAG: [[LOC15:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;foobar;833;10;;\00" 158 // CHECK-DEBUG-DAG: [[LOC16:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;foobar;862;10;;\00" 159 // CHECK-DEBUG-DAG: [[LOC17:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;foobar;882;10;;\00" 160 // CHECK-DEBUG-DAG: [[LOC18:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;foobar;905;27;;\00" 161 // CHECK-DEBUG-DAG: [[LOC19:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;foobar;928;10;;\00" 162 // CHECK-DEBUG-DAG: [[LOC20:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;;363;1;;\00" 163 164 // CHECK-TLS-DAG: [[GS1:@.+]] = internal thread_local global [[S1]] zeroinitializer 165 // CHECK-TLS-DAG: [[GS2:@.+]] = internal global [[S2]] zeroinitializer 166 // CHECK-TLS-DAG: [[ARR_X:@.+]] ={{.*}} thread_local global [2 x [3 x [[S1]]]] zeroinitializer 167 // CHECK-TLS-DAG: [[SM:@.+]] = internal thread_local global [[SMAIN]] zeroinitializer 168 // CHECK-TLS-DAG: [[SM_GUARD:@_ZGVZ4mainE2sm]] = internal thread_local global i8 0 169 // CHECK-TLS-DAG: [[STATIC_S:@.+]] = external thread_local global [[S3]] 170 // CHECK-TLS-DAG: [[GS3:@.+]] = external thread_local global [[S5]] 171 // CHECK-TLS-DAG: [[ST_INT_ST:@.+]] = linkonce_odr thread_local global i32 23 172 // CHECK-TLS-DAG: [[ST_FLOAT_ST:@.+]] = linkonce_odr thread_local global float 2.300000e+01 173 // CHECK-TLS-DAG: [[ST_S4_ST:@.+]] = linkonce_odr thread_local global %struct.S4 zeroinitializer 174 // CHECK-TLS-DAG: [[ST_S4_ST_GUARD:@_ZGVN2STI2S4E2stE]] = linkonce_odr thread_local global i64 0 175 // CHECK-TLS-DAG: @__tls_guard = internal thread_local global i8 0 176 // CHECK-TLS-DAG: @__dso_handle = external hidden global i8 177 // CHECK-TLS-DAG: [[GS1_TLS_INIT:@_ZTHL3gs1]] = internal alias void (), ptr @__tls_init 178 // CHECK-TLS-DAG: [[ARR_X_TLS_INIT:@_ZTH5arr_x]] ={{.*}} alias void (), ptr @__tls_init 179 // CHECK-TLS-DAG: [[ST_S4_ST_TLS_INIT:@_ZTHN2STI2S4E2stE]] = linkonce_odr alias void (), ptr [[ST_S4_ST_CXX_INIT:@[^, ]*]] 180 181 // OMP50-TLS: define internal void [[GS1_CXX_INIT:@.*]]() 182 // OMP50-TLS: call void [[GS1_CTOR1:@.*]](ptr {{[^,]*}} [[GS1]], i32 5) 183 // OMP50-TLS: call i32 @__cxa_thread_atexit(ptr [[GS1_DTOR1:.*]], ptr [[GS1]] 184 // OMP50-TLS: } 185 // OMP50-TLS: define {{.*}}void [[GS1_CTOR1]](ptr {{.*}}, i32 {{.*}}) 186 // OMP50-TLS: call void [[GS1_CTOR2:@.*]](ptr {{.*}}, i32 {{.*}}) 187 // OMP50-TLS: } 188 // OMP50-TLS: define {{.*}}void [[GS1_DTOR1]](ptr {{.*}}) 189 // OMP50-TLS: call void [[GS1_DTOR2:@.*]](ptr {{.*}}) 190 // OMP50-TLS: } 191 // OMP50-TLS: define {{.*}}void [[GS1_CTOR2]](ptr {{.*}}, i32 {{.*}}) 192 // OMP50-TLS: define {{.*}}void [[GS1_DTOR2]](ptr {{.*}}) 193 194 // OMP50-TLS: define internal void [[GS2_CXX_INIT:@.*]]() 195 // OMP50-TLS: call void [[GS2_CTOR1:@.*]](ptr {{[^,]*}} [[GS2]], i32 27) 196 // OMP50-TLS: call i32 @__cxa_atexit(ptr [[GS2_DTOR1:.*]], ptr [[GS2]] 197 // OMP50-TLS: } 198 // OMP50-TLS: define {{.*}}void [[GS2_CTOR1]](ptr {{.*}}, i32 {{.*}}) 199 // OMP50-TLS: call void [[GS2_CTOR2:@.*]](ptr {{.*}}, i32 {{.*}}) 200 // OMP50-TLS: } 201 // OMP50-TLS: define {{.*}}void [[GS2_DTOR1]](ptr {{.*}}) 202 // OMP50-TLS: call void [[GS2_DTOR2:@.*]](ptr {{.*}}) 203 // OMP50-TLS: } 204 // OMP50-TLS: define {{.*}}void [[GS2_CTOR2]](ptr {{.*}}, i32 {{.*}}) 205 // OMP50-TLS: define {{.*}}void [[GS2_DTOR2]](ptr {{.*}}) 206 207 // OMP50-TLS: define internal void [[ARR_X_CXX_INIT:@.*]]() 208 // OMP50-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 0, i{{.*}} 0), i{{.*}} 1) 209 // OMP50-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 0, i{{.*}} 1), i{{.*}} 2) 210 // OMP50-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 0, i{{.*}} 2), i{{.*}} 3) 211 // OMP50-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 1, i{{.*}} 0), i{{.*}} 4) 212 // OMP50-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 1, i{{.*}} 1), i{{.*}} 5) 213 // OMP50-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 1, i{{.*}} 2), i{{.*}} 6) 214 // OMP50-TLS: call i32 @__cxa_thread_atexit(ptr [[ARR_X_CXX_DTOR:@[^,]+]] 215 // OMP50-TLS: define internal void [[ARR_X_CXX_DTOR]](ptr %0) 216 // OMP50-TLS: void [[GS1_DTOR1]](ptr {{.*}}) 217 218 struct Static { 219 static S3 s; 220 #pragma omp threadprivate(s) 221 }; 222 223 static S1 gs1(5); 224 #pragma omp threadprivate(gs1) 225 #pragma omp threadprivate(gs1) 226 // CHECK: define {{.*}} [[S1_CTOR:@.*]](ptr {{.*}}, 227 // CHECK: define {{.*}} [[S1_DTOR:@.*]](ptr {{.*}}) 228 // CHECK: define internal {{.*}}ptr [[GS1_CTOR:@\.__kmpc_global_ctor_\..*]](ptr %0) 229 // CHECK: store ptr %0, ptr [[ARG_ADDR:%.*]], 230 // CHECK: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 231 // CHECK-NEXT: call {{.*}} [[S1_CTOR]](ptr {{[^,]*}} [[ARG]], {{.*}} 5) 232 // CHECK: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 233 // CHECK: ret ptr [[ARG]] 234 // CHECK-NEXT: } 235 // CHECK: define internal {{.*}}void [[GS1_DTOR:@\.__kmpc_global_dtor_\..*]](ptr %0) 236 // CHECK: store ptr %0, ptr [[ARG_ADDR:%.*]], 237 // CHECK: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 238 // CHECK-NEXT: call {{.*}} [[S1_DTOR]](ptr {{[^,]*}} [[ARG]]) 239 // CHECK-NEXT: ret void 240 // CHECK-NEXT: } 241 // CHECK: define internal {{.*}}void [[GS1_INIT:@\.__omp_threadprivate_init_\..*]]() 242 // CHECK: call {{.*}}void @__kmpc_threadprivate_register(ptr [[DEFAULT_LOC]], ptr [[GS1]], ptr [[GS1_CTOR]], ptr null, ptr [[GS1_DTOR]]) 243 // CHECK-NEXT: ret void 244 // CHECK-NEXT: } 245 246 247 248 // CHECK-DEBUG: @__kmpc_global_thread_num 249 // CHECK-DEBUG: call {{.*}}void @__kmpc_threadprivate_register(ptr [[ID1]], ptr [[GS1]], ptr [[GS1_CTOR:@\.__kmpc_global_ctor_\..*]], ptr null, ptr [[GS1_DTOR:@\.__kmpc_global_dtor_\..*]]) 250 // CHECK-DEBUG: define internal {{.*}}ptr [[GS1_CTOR]](ptr %0) 251 // CHECK-DEBUG: store ptr %0, ptr [[ARG_ADDR:%.*]], 252 // CHECK-DEBUG: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 253 // CHECK-DEBUG-NEXT: call {{.*}} [[S1_CTOR:@.+]](ptr {{[^,]*}} [[ARG]], {{.*}} 5){{.*}}, !dbg 254 // CHECK-DEBUG: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 255 // CHECK-DEBUG: ret ptr [[ARG]] 256 // CHECK-DEBUG-NEXT: } 257 // CHECK-DEBUG: define {{.*}} [[S1_CTOR]](ptr {{.*}}, 258 // CHECK-DEBUG: define internal {{.*}}void [[GS1_DTOR]](ptr %0) 259 // CHECK-DEBUG: store ptr %0, ptr [[ARG_ADDR:%.*]], 260 // CHECK-DEBUG: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 261 // CHECK-DEBUG-NEXT: call {{.*}} [[S1_DTOR:@.+]](ptr {{[^,]*}} [[ARG]]){{.*}}, !dbg 262 // CHECK-DEBUG-NEXT: ret void 263 // CHECK-DEBUG-NEXT: } 264 // CHECK-DEBUG: define {{.*}} [[S1_DTOR]](ptr {{.*}}) 265 static S2 gs2(27); 266 // CHECK: define {{.*}} [[S2_CTOR:@.*]](ptr {{.*}}, 267 // CHECK: define {{.*}} [[S2_DTOR:@.*]](ptr {{.*}}) 268 // No another call for S2 constructor because it is not threadprivate 269 // CHECK-NOT: call {{.*}} [[S2_CTOR]](ptr 270 // CHECK-DEBUG: define {{.*}} [[S2_CTOR:@.*]](ptr {{.*}}, 271 // CHECK-DEBUG: define {{.*}} [[S2_DTOR:@.*]](ptr {{.*}}) 272 // No another call for S2 constructor because it is not threadprivate 273 // CHECK-DEBUG-NOT: call {{.*}} [[S2_CTOR]](ptr 274 S1 arr_x[2][3] = { { 1, 2, 3 }, { 4, 5, 6 } }; 275 #pragma omp threadprivate(arr_x) 276 // CHECK: define internal {{.*}}ptr [[ARR_X_CTOR:@\.__kmpc_global_ctor_\..*]](ptr %0) 277 // CHECK: store ptr %0, ptr [[ARG_ADDR:%.*]], 278 // CHECK: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 279 // CHECK: [[ARR1:%.*]] = getelementptr inbounds [2 x [3 x [[S1]]]], ptr [[ARG]], i{{.*}} 0, i{{.*}} 0 280 // CHECK: [[ARR:%.*]] = getelementptr inbounds [3 x [[S1]]], ptr [[ARR1]], i{{.*}} 0, i{{.*}} 0 281 // CHECK: invoke {{.*}} [[S1_CTOR]](ptr {{[^,]*}} [[ARR]], [[INT]] {{.*}}1) 282 // CHECK: [[ARR_ELEMENT:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR]], i{{.*}} 1 283 // CHECK: invoke {{.*}} [[S1_CTOR]](ptr {{[^,]*}} [[ARR_ELEMENT]], [[INT]] {{.*}}2) 284 // CHECK: [[ARR_ELEMENT2:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_ELEMENT]], i{{.*}} 1 285 // CHECK: invoke {{.*}} [[S1_CTOR]](ptr {{[^,]*}} [[ARR_ELEMENT2]], [[INT]] {{.*}}3) 286 // CHECK: [[ARR_ELEMENT3:%.*]] = getelementptr inbounds [3 x [[S1]]], ptr [[ARR1]], i{{.*}} 1 287 // CHECK: [[ARR_:%.*]] = getelementptr inbounds [3 x [[S1]]], ptr [[ARR_ELEMENT3]], i{{.*}} 0, i{{.*}} 0 288 // CHECK: invoke {{.*}} [[S1_CTOR]](ptr {{[^,]*}} [[ARR_]], [[INT]] {{.*}}4) 289 // CHECK: [[ARR_ELEMENT:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_]], i{{.*}} 1 290 // CHECK: invoke {{.*}} [[S1_CTOR]](ptr {{[^,]*}} [[ARR_ELEMENT]], [[INT]] {{.*}}5) 291 // CHECK: [[ARR_ELEMENT2:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_ELEMENT]], i{{.*}} 1 292 // CHECK: invoke {{.*}} [[S1_CTOR]](ptr {{[^,]*}} [[ARR_ELEMENT2]], [[INT]] {{.*}}6) 293 // CHECK: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 294 // CHECK: ret ptr [[ARG]] 295 // CHECK: } 296 // CHECK: define internal {{.*}}void [[ARR_X_DTOR:@\.__kmpc_global_dtor_\..*]](ptr %0) 297 // CHECK: store ptr %0, ptr [[ARG_ADDR:%.*]], 298 // CHECK: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 299 // CHECK-NEXT: [[ARR_CUR:%.*]] = getelementptr inbounds [[S1]], ptr [[ARG]], i{{.*}} 6 300 // CHECK-NEXT: br label %[[ARR_LOOP:.*]] 301 // CHECK: {{.*}}[[ARR_LOOP]]{{.*}} 302 // CHECK-NEXT: [[ARR_ELEMENTPAST:%.*]] = phi ptr [ [[ARR_CUR]], {{.*}} ], [ [[ARR_ELEMENT:%.*]], {{.*}} ] 303 // CHECK-NEXT: [[ARR_ELEMENT:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_ELEMENTPAST]], i{{.*}} -1 304 // CHECK-NEXT: {{call|invoke}} {{.*}} [[S1_DTOR]](ptr {{[^,]*}} [[ARR_ELEMENT]]) 305 // CHECK: [[ARR_DONE:%.*]] = icmp eq ptr [[ARR_ELEMENT]], [[ARG]] 306 // CHECK-NEXT: br i1 [[ARR_DONE]], label %[[ARR_EXIT:.*]], label %[[ARR_LOOP]] 307 // CHECK: {{.*}}[[ARR_EXIT]]{{.*}} 308 // CHECK-NEXT: ret void 309 // CHECK: } 310 // CHECK: define internal {{.*}}void [[ARR_X_INIT:@\.__omp_threadprivate_init_\..*]]() 311 // CHECK: call {{.*}}void @__kmpc_threadprivate_register(ptr [[DEFAULT_LOC]], ptr [[ARR_X]], ptr [[ARR_X_CTOR]], ptr null, ptr [[ARR_X_DTOR]]) 312 // CHECK-NEXT: ret void 313 // CHECK-NEXT: } 314 315 316 317 // CHECK-DEBUG: @__kmpc_global_thread_num 318 // CHECK-DEBUG: call {{.*}}void @__kmpc_threadprivate_register(ptr [[ID2]], ptr [[ARR_X]], ptr [[ARR_X_CTOR:@\.__kmpc_global_ctor_\..*]], ptr null, ptr [[ARR_X_DTOR:@\.__kmpc_global_dtor_\..*]]) 319 // CHECK-DEBUG: define internal {{.*}}ptr [[ARR_X_CTOR]](ptr %0) 320 // CHECK-DEBUG: } 321 // CHECK-DEBUG: define internal {{.*}}void [[ARR_X_DTOR]](ptr %0) 322 // CHECK-DEBUG: } 323 extern S5 gs3; 324 #pragma omp threadprivate(gs3) 325 // No call for S5 constructor because gs3 has just declaration, not a definition. 326 // CHECK-NOT: call {{.*}}(ptr 327 // CHECK-DEBUG-NOT: call {{.*}}(ptr 328 329 template <class T> 330 struct ST { 331 static T st; 332 #pragma omp threadprivate(st) 333 }; 334 335 336 337 338 339 // OMP50-DEBUG: @__kmpc_global_thread_num 340 // OMP50-DEBUG: call {{.*}}void @__kmpc_threadprivate_register(ptr {{.*}}, ptr [[ST_S4_ST]], ptr [[ST_S4_ST_CTOR:@\.__kmpc_global_ctor_\..+]], ptr null, ptr [[ST_S4_ST_DTOR:@\.__kmpc_global_dtor_\..+]]) 341 // OMP50-DEBUG: define internal {{.*}}ptr [[ST_S4_ST_CTOR]](ptr %0) 342 // OMP50-DEBUG: } 343 // OMP50-DEBUG: define {{.*}} [[S4_CTOR:@.*]](ptr {{.*}}, 344 // OMP50-DEBUG: define internal {{.*}}void [[ST_S4_ST_DTOR]](ptr %0) 345 // OMP50-DEBUG: } 346 // OMP50-DEBUG: define {{.*}} [[S4_DTOR:@.*]](ptr {{.*}}) 347 348 // OMP50: call {{.*}}void @__kmpc_threadprivate_register(ptr [[DEFAULT_LOC]], ptr [[ST_S4_ST]], ptr [[ST_S4_ST_CTOR:@\.__kmpc_global_ctor_\..+]], ptr null, ptr [[ST_S4_ST_DTOR:@\.__kmpc_global_dtor_\..+]]) 349 // OMP50: define internal {{.*}}ptr [[ST_S4_ST_CTOR]](ptr %0) 350 // OMP50: store ptr %0, ptr [[ARG_ADDR:%.*]], 351 // OMP50: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 352 // OMP50-NEXT: call {{.*}} [[S4_CTOR:@.+]](ptr {{[^,]*}} [[ARG]], {{.*}} 23) 353 // OMP50: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 354 // OMP50-NEXT: ret ptr [[ARG]] 355 // OMP50-NEXT: } 356 // OMP50: define {{.*}} [[S4_CTOR]](ptr {{.*}}, 357 // OMP50: define internal {{.*}}void [[ST_S4_ST_DTOR]](ptr %0) 358 // OMP50: store ptr %0, ptr [[ARG_ADDR:%.*]], 359 // OMP50: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 360 // OMP50-NEXT: call {{.*}} [[S4_DTOR:@.+]](ptr {{[^,]*}} [[ARG]]) 361 // OMP50-NEXT: ret void 362 // OMP50-NEXT: } 363 // OMP50: define {{.*}} [[S4_DTOR]](ptr {{[^,]*}} {{.*}}) 364 template <class T> 365 T ST<T>::st(23); 366 367 // CHECK-LABEL: @main() 368 // CHECK-DEBUG-LABEL: @main() 369 int main() { 370 371 int Res; 372 struct Smain { 373 int a; 374 double b, c; 375 Smain() 376 : a(0) { 377 } 378 Smain(int a) 379 : a(a) { 380 } 381 Smain(const Smain &s) { 382 a = 12 + s.a; 383 } 384 ~Smain() { 385 a = 0; 386 } 387 }; 388 389 static Smain sm(gs1.a); 390 // CHECK: [[THREAD_NUM:%.+]] = call {{.*}}i32 @__kmpc_global_thread_num(ptr [[DEFAULT_LOC]]) 391 // CHECK: call {{.*}}i{{.*}} @__cxa_guard_acquire 392 // CHECK: call {{.*}}i32 @__kmpc_global_thread_num(ptr [[DEFAULT_LOC]]) 393 // CHECK: call {{.*}}void @__kmpc_threadprivate_register(ptr [[DEFAULT_LOC]], ptr [[SM]], ptr [[SM_CTOR:@\.__kmpc_global_ctor_\..+]], ptr null, ptr [[SM_DTOR:@\.__kmpc_global_dtor_\..+]]) 394 // CHECK: [[GS1_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[GS1]], i{{.*}} {{[0-9]+}}, ptr [[GS1]].cache.) 395 // CHECK-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 396 // CHECK-NEXT: [[GS1_A:%.*]] = load [[INT]], ptr [[GS1_A_ADDR]] 397 // CHECK-NEXT: invoke {{.*}} [[SMAIN_CTOR:.*]](ptr {{[^,]*}} [[SM]], [[INT]] {{.*}}[[GS1_A]]) 398 // CHECK: call {{.*}}void @__cxa_guard_release 399 400 401 402 // CHECK-DEBUG: call {{.*}}i{{.*}} @__cxa_guard_acquire 403 // CHECK-DEBUG: call {{.*}}i32 @__kmpc_global_thread_num(ptr [[KMPC_LOC:@.+]]) 404 // CHECK-DEBUG: call {{.*}}void @__kmpc_threadprivate_register(ptr [[KMPC_LOC]], ptr [[SM]], ptr [[SM_CTOR:@\.__kmpc_global_ctor_\..+]], ptr null, ptr [[SM_DTOR:@\.__kmpc_global_dtor_\..+]]) 405 // CHECK-DEBUG: [[GS1_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[GS1]], i{{.*}} {{[0-9]+}}, ptr 406 407 408 // CHECK-DEBUG-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 409 // CHECK-DEBUG-NEXT: [[GS1_A:%.*]] = load [[INT]], ptr [[GS1_A_ADDR]] 410 // CHECK-DEBUG-NEXT: invoke {{.*}} [[SMAIN_CTOR:.*]](ptr {{[^,]*}} [[SM]], [[INT]] {{.*}}[[GS1_A]]) 411 // CHECK-DEBUG: call {{.*}}void @__cxa_guard_release 412 // CHECK-TLS: [[IS_INIT_INT:%.*]] = load i8, ptr [[SM_GUARD]] 413 // CHECK-TLS-NEXT: [[IS_INIT_BOOL:%.*]] = icmp eq i8 [[IS_INIT_INT]], 0 414 // CHECK-TLS-NEXT: br i1 [[IS_INIT_BOOL]], label %[[INIT_LABEL:.*]], label %[[INIT_DONE:[^,]+]]{{.*}} 415 // CHECK-TLS: [[INIT_LABEL]] 416 // CHECK-TLS-NEXT: [[GS1_ADDR:%.*]] = call ptr [[GS1_TLS_INITD:@[^,]+]] 417 // CHECK-TLS-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_ADDR]], i32 0, i32 0 418 // CHECK-TLS-NEXT: [[GS1_A_VAL:%.*]] = load i32, ptr [[GS1_A_ADDR]] 419 // CHECK-TLS-NEXT: call void [[SM_CTOR1:@.*]](ptr {{[^,]*}} [[SM]], i32 [[GS1_A_VAL]]) 420 // CHECK-TLS-NEXT: call i32 @__cxa_thread_atexit(ptr [[SM_DTOR1:@.*]], ptr [[SM]], ptr @__dso_handle) 421 // CHECK-TLS-NEXT: store i8 1, ptr [[SM_GUARD]] 422 // CHECK-TLS-NEXT: br label %[[INIT_DONE]] 423 // CHECK-TLS: [[INIT_DONE]] 424 #pragma omp threadprivate(sm) 425 // CHECK: [[STATIC_S_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[STATIC_S]], i{{.*}} {{[0-9]+}}, ptr [[STATIC_S]].cache.) 426 // CHECK-NEXT: [[STATIC_S_A_ADDR:%.*]] = getelementptr inbounds [[S3]], ptr [[STATIC_S_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 427 // CHECK-NEXT: [[STATIC_S_A:%.*]] = load [[INT]], ptr [[STATIC_S_A_ADDR]] 428 // CHECK-NEXT: store [[INT]] [[STATIC_S_A]], ptr [[RES_ADDR:[^,]+]] 429 // CHECK-DEBUG:[[STATIC_S_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[STATIC_S]], i{{.*}} {{[0-9]+}}, ptr 430 431 432 // CHECK-DEBUG-NEXT: [[STATIC_S_A_ADDR:%.*]] = getelementptr inbounds [[S3]], ptr [[STATIC_S_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 433 // CHECK-DEBUG-NEXT: [[STATIC_S_A:%.*]] = load [[INT]], ptr [[STATIC_S_A_ADDR]] 434 // CHECK-DEBUG-NEXT: store [[INT]] [[STATIC_S_A]], ptr [[RES_ADDR:[^,]+]] 435 // CHECK-TLS: [[STATIC_S_ADDR:%.*]] = call ptr [[STATIC_S_TLS_INITD:@[^,]+]] 436 // CHECK-TLS-NEXT: [[STATIC_S_A_ADDR:%.*]] = getelementptr inbounds [[S3]], ptr [[STATIC_S_ADDR]], i{{.*}} 0, i{{.*}} 0 437 // CHECK-TLS-NEXT: [[STATIC_S_A:%.*]] = load i32, ptr [[STATIC_S_A_ADDR]] 438 // CHECK-TLS-NEXT: store i32 [[STATIC_S_A]], ptr [[RES_ADDR:[^,]+]] 439 Res = Static::s.a; 440 // CHECK: [[SM_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[SM]], i{{.*}} {{[0-9]+}}, ptr [[SM]].cache.) 441 // CHECK-NEXT: [[SM_A_ADDR:%.*]] = getelementptr inbounds [[SMAIN]], ptr [[SM_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 442 // CHECK-NEXT: [[SM_A:%.*]] = load [[INT]], ptr [[SM_A_ADDR]] 443 // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 444 // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[SM_A]] 445 // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 446 // CHECK-DEBUG-NEXT: [[SM_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[SM]], i{{.*}} {{[0-9]+}}, ptr 447 448 449 // CHECK-DEBUG-NEXT: [[SM_A_ADDR:%.*]] = getelementptr inbounds [[SMAIN]], ptr [[SM_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 450 // CHECK-DEBUG-NEXT: [[SM_A:%.*]] = load [[INT]], ptr [[SM_A_ADDR]] 451 // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 452 // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[SM_A]] 453 // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 454 // [[SM]] was initialized already, so it can be used directly 455 // CHECK-TLS: [[SM_A:%.*]] = load i32, ptr getelementptr inbounds ([[SMAIN]], ptr [[SM]], i{{.*}} 0, i{{.*}} 0) 456 // CHECK-TLS-NEXT: [[RES:%.*]] = load i32, ptr [[RES_ADDR]] 457 // CHECK-TLS-NEXT: [[ADD:%.*]] = add {{.*}} i32 [[RES]], [[SM_A]] 458 // CHECK-TLS-NEXT: store i32 [[ADD]], ptr [[RES_ADDR]] 459 Res += sm.a; 460 // CHECK: [[GS1_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[GS1]], i{{.*}} {{[0-9]+}}, ptr [[GS1]].cache.) 461 // CHECK-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 462 // CHECK-NEXT: [[GS1_A:%.*]] = load [[INT]], ptr [[GS1_A_ADDR]] 463 // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 464 // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS1_A]] 465 // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 466 // CHECK-DEBUG-NEXT: [[GS1_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[GS1]], i{{.*}} {{[0-9]+}}, ptr 467 468 469 // CHECK-DEBUG-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 470 // CHECK-DEBUG-NEXT: [[GS1_A:%.*]] = load [[INT]], ptr [[GS1_A_ADDR]] 471 // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 472 // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS1_A]] 473 // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 474 // CHECK-TLS: [[GS1_ADDR:%.*]] = call ptr [[GS1_TLS_INITD]] 475 // CHECK-TLS-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_ADDR]], i{{.*}} 0, i{{.*}} 0 476 // CHECK-TLS-NEXT: [[GS1_A:%.*]] = load i32, ptr [[GS1_A_ADDR]] 477 // CHECK-TLS-NEXT: [[RES:%.*]] = load i32, ptr [[RES_ADDR]] 478 // CHECK-TLS-NEXT: [[ADD:%.*]] = add {{.*}} i32 [[RES]], [[GS1_A]] 479 // CHECK-TLS-NEXT: store i32 [[ADD]], ptr [[RES_ADDR]] 480 Res += gs1.a; 481 // CHECK: [[GS2_A:%.*]] = load [[INT]], ptr getelementptr inbounds ([[S2]], ptr [[GS2]], i{{.*}} 0, i{{.*}} 0) 482 // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 483 // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS2_A]] 484 // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 485 // CHECK-DEBUG: [[GS2_A:%.*]] = load [[INT]], ptr getelementptr inbounds ([[S2]], ptr [[GS2]], i{{.*}} 0, i{{.*}} 0) 486 // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 487 // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS2_A]] 488 // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 489 // CHECK-TLS: [[GS2_A:%.*]] = load [[INT]], ptr getelementptr inbounds ([[S2]], ptr [[GS2]], i{{.*}} 0, i{{.*}} 0) 490 // CHECK-TLS-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 491 // CHECK-TLS-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS2_A]] 492 // CHECK-TLS-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 493 Res += gs2.a; 494 // CHECK: [[GS3_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[GS3]], i{{.*}} {{[0-9]+}}, ptr [[GS3]].cache.) 495 // CHECK-NEXT: [[GS3_A_ADDR:%.*]] = getelementptr inbounds [[S5]], ptr [[GS3_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 496 // CHECK-NEXT: [[GS3_A:%.*]] = load [[INT]], ptr [[GS3_A_ADDR]] 497 // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 498 // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS3_A]] 499 // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 500 // CHECK-DEBUG-NEXT: [[GS3_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[GS3]], i{{.*}} {{[0-9]+}}, ptr 501 502 503 // CHECK-DEBUG-NEXT: [[GS3_A_ADDR:%.*]] = getelementptr inbounds [[S5]], ptr [[GS3_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 504 // CHECK-DEBUG-NEXT: [[GS3_A:%.*]] = load [[INT]], ptr [[GS3_A_ADDR]] 505 // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 506 // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS3_A]] 507 // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 508 // CHECK-TLS: [[GS3_ADDR:%.*]] = call ptr [[GS3_TLS_INITD:[^,]+]] 509 // CHECK-TLS-NEXT: [[GS3_A_ADDR:%.*]] = getelementptr inbounds [[S5]], ptr [[GS3_ADDR]], i{{.*}} 0, i{{.*}} 0 510 // CHECK-TLS-NEXT: [[GS3_A:%.*]] = load i32, ptr [[GS3_A_ADDR]] 511 // CHECK-TLS-NEXT: [[RES:%.*]] = load i32, ptr [[RES_ADDR]] 512 // CHECK-TLS-NEXT: [[ADD:%.*]] = add nsw i32 [[RES]], [[GS3_A]] 513 // CHECK-TLS-NEXT: store i32 [[ADD]], ptr [[RES_ADDR]] 514 Res += gs3.a; 515 // CHECK: [[ARR_X_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[ARR_X]], i{{.*}} {{[0-9]+}}, ptr [[ARR_X]].cache.) 516 // CHECK-NEXT: [[ARR_X_1_ADDR:%.*]] = getelementptr inbounds [2 x [3 x [[S1]]]], ptr [[ARR_X_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 1 517 // CHECK-NEXT: [[ARR_X_1_1_ADDR:%.*]] = getelementptr inbounds [3 x [[S1]]], ptr [[ARR_X_1_ADDR]], i{{.*}} 0, i{{.*}} 1 518 // CHECK-NEXT: [[ARR_X_1_1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_X_1_1_ADDR]], i{{.*}} 0, i{{.*}} 0 519 // CHECK-NEXT: [[ARR_X_1_1_A:%.*]] = load [[INT]], ptr [[ARR_X_1_1_A_ADDR]] 520 // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 521 // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ARR_X_1_1_A]] 522 // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 523 // CHECK-DEBUG-NEXT: [[ARR_X_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[ARR_X]], i{{.*}} {{[0-9]+}}, ptr 524 525 526 // CHECK-DEBUG-NEXT: [[ARR_X_1_ADDR:%.*]] = getelementptr inbounds [2 x [3 x [[S1]]]], ptr [[ARR_X_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 1 527 // CHECK-DEBUG-NEXT: [[ARR_X_1_1_ADDR:%.*]] = getelementptr inbounds [3 x [[S1]]], ptr [[ARR_X_1_ADDR]], i{{.*}} 0, i{{.*}} 1 528 // CHECK-DEBUG-NEXT: [[ARR_X_1_1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_X_1_1_ADDR]], i{{.*}} 0, i{{.*}} 0 529 // CHECK-DEBUG-NEXT: [[ARR_X_1_1_A:%.*]] = load [[INT]], ptr [[ARR_X_1_1_A_ADDR]] 530 // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 531 // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ARR_X_1_1_A]] 532 // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 533 // CHECK-TLS: [[ARR_X_ADDR:%.*]] = call ptr [[ARR_X_TLS_INITD:[^,]+]] 534 // CHECK-TLS-NEXT: [[ARR_X_1_ADDR:%.*]] = getelementptr inbounds [2 x [3 x [[S1]]]], ptr [[ARR_X_ADDR]], i{{.*}} 0, i{{.*}} 1 535 // CHECK-TLS-NEXT: [[ARR_X_1_1_ADDR:%.*]] = getelementptr inbounds [3 x [[S1]]], ptr [[ARR_X_1_ADDR]], i{{.*}} 0, i{{.*}} 1 536 // CHECK-TLS-NEXT: [[ARR_X_1_1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_X_1_1_ADDR]], i{{.*}} 0, i{{.*}} 0 537 // CHECK-TLS-NEXT: [[ARR_X_1_1_A:%.*]] = load i32, ptr [[ARR_X_1_1_A_ADDR]] 538 // CHECK-TLS-NEXT: [[RES:%.*]] = load i32, ptr [[RES_ADDR]] 539 // CHECK-TLS-NEXT: [[ADD:%.*]] = add {{.*}} i32 [[RES]], [[ARR_X_1_1_A]] 540 // CHECK-TLS-NEXT: store i32 [[ADD]], ptr [[RES_ADDR]] 541 Res += arr_x[1][1].a; 542 // CHECK: [[ST_INT_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[ST_INT_ST]], i{{.*}} {{[0-9]+}}, ptr [[ST_INT_ST]].cache.) 543 // CHECK-NEXT: [[ST_INT_ST_VAL:%.*]] = load [[INT]], ptr [[ST_INT_ST_TEMP_ADDR]] 544 // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 545 // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_INT_ST_VAL]] 546 // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 547 // CHECK-DEBUG-NEXT: [[ST_INT_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[ST_INT_ST]], i{{.*}} {{[0-9]+}}, ptr 548 549 550 // CHECK-DEBUG-NEXT: [[ST_INT_ST_VAL:%.*]] = load [[INT]], ptr [[ST_INT_ST_TEMP_ADDR]] 551 // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 552 // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_INT_ST_VAL]] 553 // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 554 // CHECK-TLS: [[ST_INT_ST_VAL:%.*]] = load i32, ptr [[ST_INT_ST_ADDR:[^,]+]] 555 // CHECK-TLS-NEXT: [[RES:%.*]] = load i32, ptr [[RES_ADDR]] 556 // CHECK-TLS-NEXT: [[ADD:%.*]] = add {{.*}} i32 [[RES]], [[ST_INT_ST_VAL]] 557 // CHECK-TLS-NEXT: store i32 [[ADD]], ptr [[RES_ADDR]] 558 Res += ST<int>::st; 559 // CHECK: [[ST_FLOAT_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[ST_FLOAT_ST]], i{{.*}} {{[0-9]+}}, ptr [[ST_FLOAT_ST]].cache.) 560 // CHECK-NEXT: [[ST_FLOAT_ST_VAL:%.*]] = load float, ptr [[ST_FLOAT_ST_TEMP_ADDR]] 561 // CHECK-NEXT: [[FLOAT_TO_INT_CONV:%.*]] = fptosi float [[ST_FLOAT_ST_VAL]] to [[INT]] 562 // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 563 // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[FLOAT_TO_INT_CONV]] 564 // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 565 // CHECK-DEBUG-NEXT: [[ST_FLOAT_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[ST_FLOAT_ST]], i{{.*}} {{[0-9]+}}, ptr 566 567 568 // CHECK-DEBUG-NEXT: [[ST_FLOAT_ST_VAL:%.*]] = load float, ptr [[ST_FLOAT_ST_TEMP_ADDR]] 569 // CHECK-DEBUG-NEXT: [[FLOAT_TO_INT_CONV:%.*]] = fptosi float [[ST_FLOAT_ST_VAL]] to [[INT]] 570 // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 571 // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[FLOAT_TO_INT_CONV]] 572 // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 573 // CHECK-TLS: [[ST_FLOAT_ST_VAL:%.*]] = load float, ptr [[ST_FLOAT_ST_ADDR:[^,]+]] 574 // CHECK-TLS-NEXT: [[FLOAT_TO_INT_CONV:%.*]] = fptosi float [[ST_FLOAT_ST_VAL]] to i32 575 // CHECK-TLS-NEXT: [[RES:%.*]] = load i32, ptr [[RES_ADDR]] 576 // CHECK-TLS-NEXT: [[ADD:%.*]] = add {{.*}} i32 [[RES]], [[FLOAT_TO_INT_CONV]] 577 // CHECK-TLS-NEXT: store i32 [[ADD]], ptr [[RES_ADDR]] 578 Res += static_cast<int>(ST<float>::st); 579 // CHECK: [[ST_S4_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[ST_S4_ST]], i{{.*}} {{[0-9]+}}, ptr [[ST_S4_ST]].cache.) 580 // CHECK-NEXT: [[ST_S4_ST_A_ADDR:%.*]] = getelementptr inbounds [[S4]], ptr [[ST_S4_ST_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 581 // CHECK-NEXT: [[ST_S4_ST_A:%.*]] = load [[INT]], ptr [[ST_S4_ST_A_ADDR]] 582 // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 583 // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_S4_ST_A]] 584 // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 585 // CHECK-DEBUG-NEXT: [[ST_S4_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[ST_S4_ST]], i{{.*}} {{[0-9]+}}, ptr 586 587 588 // CHECK-DEBUG-NEXT: [[ST_S4_ST_A_ADDR:%.*]] = getelementptr inbounds [[S4]], ptr [[ST_S4_ST_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 589 // CHECK-DEBUG-NEXT: [[ST_S4_ST_A:%.*]] = load [[INT]], ptr [[ST_S4_ST_A_ADDR]] 590 // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 591 // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_S4_ST_A]] 592 // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 593 // CHECK-TLS: [[ST_S4_ST_ADDR:%.*]] = call ptr [[ST_S4_ST_TLS_INITD:[^,]+]] 594 // CHECK-TLS-NEXT: [[ST_S4_ST_A_ADDR:%.*]] = getelementptr inbounds [[S4]], ptr [[ST_S4_ST_ADDR]], i{{.*}} 0, i{{.*}} 0 595 // CHECK-TLS-NEXT: [[ST_S4_ST_A:%.*]] = load i32, ptr [[ST_S4_ST_A_ADDR]] 596 // CHECK-TLS-NEXT: [[RES:%.*]] = load i32, ptr [[RES_ADDR]] 597 // CHECK-TLS-NEXT: [[ADD:%.*]] = add {{.*}} i32 [[RES]], [[ST_S4_ST_A]] 598 // CHECK-TLS-NEXT: store i32 [[ADD]], ptr [[RES_ADDR]] 599 Res += ST<S4>::st.a; 600 // CHECK: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 601 // CHECK-NEXT: ret [[INT]] [[RES]] 602 // CHECK-DEBUG: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 603 // CHECK-DEBUG-NEXT: ret [[INT]] [[RES]] 604 // CHECK-TLS: [[RES:%.*]] = load i32, ptr [[RES_ADDR]] 605 // CHECK-TLS-NEXT: ret i32 [[RES]] 606 return Res; 607 } 608 // CHECK: } 609 610 // CHECK: define internal {{.*}}ptr [[SM_CTOR]](ptr %0) 611 // CHECK: [[THREAD_NUM:%.+]] = call {{.*}}i32 @__kmpc_global_thread_num(ptr [[DEFAULT_LOC]]) 612 // CHECK: store ptr %0, ptr [[ARG_ADDR:%.*]], 613 // CHECK: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 614 // CHECK: [[GS1_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[GS1]], i{{.*}} {{[0-9]+}}, ptr [[GS1]].cache.) 615 // CHECK-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 616 // CHECK-NEXT: [[GS1_A:%.*]] = load [[INT]], ptr [[GS1_A_ADDR]] 617 // CHECK-NEXT: call {{.*}} [[SMAIN_CTOR:@.+]](ptr {{[^,]*}} [[ARG]], [[INT]] {{.*}}[[GS1_A]]) 618 // CHECK: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 619 // CHECK-NEXT: ret ptr [[ARG]] 620 // CHECK-NEXT: } 621 // CHECK: define {{.*}} [[SMAIN_CTOR]](ptr {{.*}}, 622 // CHECK: define internal {{.*}}void [[SM_DTOR]](ptr %0) 623 // CHECK: store ptr %0, ptr [[ARG_ADDR:%.*]], 624 // CHECK: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 625 // CHECK-NEXT: call {{.*}} [[SMAIN_DTOR:@.+]](ptr {{[^,]*}} [[ARG]]) 626 // CHECK-NEXT: ret void 627 // CHECK-NEXT: } 628 // CHECK: define {{.*}} [[SMAIN_DTOR]](ptr {{.*}}) 629 // CHECK-DEBUG: define internal {{.*}}ptr [[SM_CTOR]](ptr %0) 630 // CHECK-DEBUG: [[THREAD_NUM:%.+]] = call {{.*}}i32 @__kmpc_global_thread_num(ptr {{.*}}) 631 632 633 634 // CHECK-DEBUG: store ptr %0, ptr [[ARG_ADDR:%.*]], 635 // CHECK-DEBUG: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 636 // CHECK-DEBUG: [[GS1_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[GS1]], i{{.*}} {{[0-9]+}}, ptr 637 638 639 // CHECK-DEBUG-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 640 // CHECK-DEBUG-NEXT: [[GS1_A:%.*]] = load [[INT]], ptr [[GS1_A_ADDR]] 641 // CHECK-DEBUG-NEXT: call {{.*}} [[SMAIN_CTOR:@.+]](ptr {{[^,]*}} [[ARG]], [[INT]] {{.*}}[[GS1_A]]) 642 // CHECK-DEBUG: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 643 // CHECK-DEBUG-NEXT: ret ptr [[ARG]] 644 // CHECK-DEBUG-NEXT: } 645 // CHECK-DEBUG: define {{.*}} [[SMAIN_CTOR]](ptr {{.*}}, 646 // CHECK-DEBUG: define internal {{.*}} [[SM_DTOR:@.+]](ptr %0) 647 // CHECK-DEBUG: call {{.*}} [[SMAIN_DTOR:@.+]](ptr 648 // CHECK-DEBUG: } 649 // CHECK-DEBUG: define {{.*}} [[SMAIN_DTOR]](ptr {{.*}}) 650 // CHECK-TLS: define internal ptr [[GS1_TLS_INITD]] {{#[0-9]+}} { 651 // CHECK-TLS-NEXT: call void [[GS1_TLS_INIT]] 652 // CHECK-TLS-NEXT: ret ptr [[GS1]] 653 // CHECK-TLS-NEXT: } 654 // CHECK-TLS: define internal void [[SM_CTOR1]](ptr {{[^,]*}} %this, i32 {{.*}}) {{.*}} { 655 // CHECK-TLS: void [[SM_CTOR2:@.*]](ptr {{.*}}, i32 {{.*}}) 656 // CHECK-TLS: } 657 // CHECK-TLS: define internal void [[SM_DTOR1]](ptr {{[^,]*}} %this) {{.*}} { 658 // CHECK-TLS: void [[SM_DTOR2:@.*]](ptr {{.*}}) 659 // CHECK-TLS: } 660 // CHECK-TLS: define {{.*}} ptr [[STATIC_S_TLS_INITD]] 661 // CHECK-TLS: call void [[STATIC_S_TLS_INIT:[^,]+]] 662 // CHECK-TLS: ret ptr [[STATIC_S]] 663 // CHECK-TLS: } 664 // CHECK-TLS: define {{.*}} ptr [[GS3_TLS_INITD]] 665 // CHECK-TLS: call void [[GS3_TLS_INIT:@[^,]+]] 666 // CHECK-TLS: ret ptr [[GS3]] 667 // CHECK-TLS: } 668 // CHECK-TLS: define {{.*}} ptr [[ARR_X_TLS_INITD]] 669 // CHECK-TLS: call void [[ARR_X_TLS_INIT]] 670 // CHECK-TLS: ret ptr [[ARR_X]] 671 // CHECK-TLS: } 672 // CHECK-TLS: define {{.*}} ptr [[ST_S4_ST_TLS_INITD]] {{#[0-9]+}} comdat { 673 // CHECK-TLS: call void [[ST_S4_ST_TLS_INIT]] 674 // CHECK-TLS: ret ptr [[ST_S4_ST]] 675 // CHECK-TLS: } 676 677 #endif 678 // OMP50-TLS: define {{.*}}void [[SM_CTOR2]](ptr {{.*}}, i32 {{.*}}) 679 // OMP50-TLS: define {{.*}}void [[SM_DTOR2]](ptr {{.*}}) 680 681 #ifdef BODY 682 // CHECK-LABEL: @{{.*}}foobar{{.*}}() 683 // CHECK-DEBUG-LABEL: @{{.*}}foobar{{.*}}() 684 // CHECK-TLS-LABEL: @{{.*}}foobar{{.*}}() 685 int foobar() { 686 687 int Res; 688 // CHECK: [[THREAD_NUM:%.+]] = call {{.*}}i32 @__kmpc_global_thread_num(ptr [[DEFAULT_LOC]]) 689 // CHECK: [[STATIC_S_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[STATIC_S]], i{{.*}} {{[0-9]+}}, ptr [[STATIC_S]].cache.) 690 // CHECK-NEXT: [[STATIC_S_A_ADDR:%.*]] = getelementptr inbounds [[S3]], ptr [[STATIC_S_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 691 // CHECK-NEXT: [[STATIC_S_A:%.*]] = load [[INT]], ptr [[STATIC_S_A_ADDR]] 692 // CHECK-NEXT: store [[INT]] [[STATIC_S_A]], ptr [[RES_ADDR:[^,]+]] 693 // CHECK-DEBUG: [[THREAD_NUM:%.+]] = call {{.*}}i32 @__kmpc_global_thread_num(ptr {{.*}}) 694 // CHECK-DEBUG: [[STATIC_S_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[STATIC_S]], i{{.*}} {{[0-9]+}}, ptr 695 696 697 698 699 // CHECK-DEBUG-NEXT: [[STATIC_S_A_ADDR:%.*]] = getelementptr inbounds [[S3]], ptr [[STATIC_S_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 700 // CHECK-DEBUG-NEXT: [[STATIC_S_A:%.*]] = load [[INT]], ptr [[STATIC_S_A_ADDR]] 701 // CHECK-DEBUG-NEXT: store [[INT]] [[STATIC_S_A]], ptr [[RES_ADDR:[^,]+]] 702 // CHECK-TLS: [[STATIC_S_ADDR:%.*]] = call ptr [[STATIC_S_TLS_INITD]] 703 // CHECK-TLS-NEXT: [[STATIC_S_A_ADDR:%.*]] = getelementptr inbounds [[S3]], ptr [[STATIC_S_ADDR]], i{{.*}} 0, i{{.*}} 0 704 // CHECK-TLS-NEXT: [[STATIC_S_A:%.*]] = load i32, ptr [[STATIC_S_A_ADDR]] 705 // CHECK-TLS-NEXT: store i32 [[STATIC_S_A]], ptr [[RES_ADDR:[^,]+]] 706 Res = Static::s.a; 707 // CHECK: [[GS1_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[GS1]], i{{.*}} {{[0-9]+}}, ptr [[GS1]].cache.) 708 // CHECK-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 709 // CHECK-NEXT: [[GS1_A:%.*]] = load [[INT]], ptr [[GS1_A_ADDR]] 710 // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 711 // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS1_A]] 712 // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 713 // CHECK-DEBUG-NEXT: [[GS1_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[GS1]], i{{.*}} {{[0-9]+}}, ptr 714 715 716 // CHECK-DEBUG-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 717 // CHECK-DEBUG-NEXT: [[GS1_A:%.*]] = load [[INT]], ptr [[GS1_A_ADDR]] 718 // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 719 // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS1_A]] 720 // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 721 // CHECK-TLS: [[GS1_ADDR:%.*]] = call ptr [[GS1_TLS_INITD]] 722 // CHECK-TLS-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_ADDR]], i{{.*}} 0, i{{.*}} 0 723 // CHECK-TLS-NEXT: [[GS1_A:%.*]] = load i32, ptr [[GS1_A_ADDR]] 724 // CHECK-TLS-NEXT: [[RES:%.*]] = load i32, ptr [[RES_ADDR]] 725 // CHECK-TLS-NEXT: [[ADD:%.*]] = add {{.*}} i32 [[RES]], [[GS1_A]] 726 // CHECK-TLS-NEXT: store i32 [[ADD]], ptr [[RES_ADDR]] 727 Res += gs1.a; 728 // CHECK: [[GS2_A:%.*]] = load [[INT]], ptr getelementptr inbounds ([[S2]], ptr [[GS2]], i{{.*}} 0, i{{.*}} 0) 729 // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 730 // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS2_A]] 731 // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 732 // CHECK-DEBUG: [[GS2_A:%.*]] = load [[INT]], ptr getelementptr inbounds ([[S2]], ptr [[GS2]], i{{.*}} 0, i{{.*}} 0) 733 // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 734 // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS2_A]] 735 // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 736 // CHECK-TLS: [[GS2_A:%.*]] = load i32, ptr getelementptr inbounds ([[S2]], ptr [[GS2]], i{{.*}} 0, i{{.*}} 0) 737 // CHECK-TLS-NEXT: [[RES:%.*]] = load i32, ptr [[RES_ADDR]] 738 // CHECK-TLS-NEXT: [[ADD:%.*]] = add {{.*}} i32 [[RES]], [[GS2_A]] 739 // CHECK-TLS-NEXT: store i32 [[ADD]], ptr [[RES:.+]] 740 Res += gs2.a; 741 // CHECK: [[GS3_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[GS3]], i{{.*}} {{[0-9]+}}, ptr [[GS3]].cache.) 742 // CHECK-NEXT: [[GS3_A_ADDR:%.*]] = getelementptr inbounds [[S5]], ptr [[GS3_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 743 // CHECK-NEXT: [[GS3_A:%.*]] = load [[INT]], ptr [[GS3_A_ADDR]] 744 // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 745 // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS3_A]] 746 // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 747 // CHECK-DEBUG-NEXT: [[GS3_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[GS3]], i{{.*}} {{[0-9]+}}, ptr 748 749 750 // CHECK-DEBUG-NEXT: [[GS3_A_ADDR:%.*]] = getelementptr inbounds [[S5]], ptr [[GS3_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 751 // CHECK-DEBUG-NEXT: [[GS3_A:%.*]] = load [[INT]], ptr [[GS3_A_ADDR]] 752 // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 753 // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS3_A]] 754 // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 755 // CHECK-TLS: [[GS3_ADDR:%.*]] = call ptr [[GS3_TLS_INITD]] 756 // CHECK-TLS-DEBUG: [[GS3_A_ADDR:%.*]] = getelementptr inbounds [[S5]], ptr [[GS3_ADDR]], i{{.*}} 0, i{{.*}} 0 757 // CHECK-TLS-DEBUG: [[GS3_A:%.*]] = load i32, ptr [[GS3_A_ADDR]] 758 // CHECK-TLS-DEBUG: [[RES:%.*]] = load i32, ptr [[RES_ADDR]] 759 // CHECK-TLS-DEBUG: [[ADD:%.*]]= add nsw i32 [[RES]], [[GS3_A]] 760 // CHECK-TLS-DEBUG: store i32 [[ADD]], ptr [[RES_ADDR]] 761 Res += gs3.a; 762 // CHECK: [[ARR_X_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[ARR_X]], i{{.*}} {{[0-9]+}}, ptr [[ARR_X]].cache.) 763 // CHECK-NEXT: [[ARR_X_1_ADDR:%.*]] = getelementptr inbounds [2 x [3 x [[S1]]]], ptr [[ARR_X_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 1 764 // CHECK-NEXT: [[ARR_X_1_1_ADDR:%.*]] = getelementptr inbounds [3 x [[S1]]], ptr [[ARR_X_1_ADDR]], i{{.*}} 0, i{{.*}} 1 765 // CHECK-NEXT: [[ARR_X_1_1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_X_1_1_ADDR]], i{{.*}} 0, i{{.*}} 0 766 // CHECK-NEXT: [[ARR_X_1_1_A:%.*]] = load [[INT]], ptr [[ARR_X_1_1_A_ADDR]] 767 // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 768 // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ARR_X_1_1_A]] 769 // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 770 // CHECK-DEBUG-NEXT: [[ARR_X_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[ARR_X]], i{{.*}} {{[0-9]+}}, ptr 771 772 773 // CHECK-DEBUG-NEXT: [[ARR_X_1_ADDR:%.*]] = getelementptr inbounds [2 x [3 x [[S1]]]], ptr [[ARR_X_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 1 774 // CHECK-DEBUG-NEXT: [[ARR_X_1_1_ADDR:%.*]] = getelementptr inbounds [3 x [[S1]]], ptr [[ARR_X_1_ADDR]], i{{.*}} 0, i{{.*}} 1 775 // CHECK-DEBUG-NEXT: [[ARR_X_1_1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_X_1_1_ADDR]], i{{.*}} 0, i{{.*}} 0 776 // CHECK-DEBUG-NEXT: [[ARR_X_1_1_A:%.*]] = load [[INT]], ptr [[ARR_X_1_1_A_ADDR]] 777 // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 778 // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ARR_X_1_1_A]] 779 // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 780 // CHECK-TLS: [[ARR_X_ADDR:%.*]] = call ptr [[ARR_X_TLS_INITD]] 781 // CHECK-TLS-NEXT: [[ARR_X_1_ADDR:%.*]] = getelementptr inbounds [2 x [3 x [[S1]]]], ptr [[ARR_X_ADDR]], i{{.*}} 0, i{{.*}} 1 782 // CHECK-TLS-NEXT: [[ARR_X_1_1_ADDR:%.*]] = getelementptr inbounds [3 x [[S1]]], ptr [[ARR_X_1_ADDR]], i{{.*}} 0, i{{.*}} 1 783 // CHECK-TLS-NEXT: [[ARR_X_1_1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_X_1_1_ADDR]], i{{.*}} 0, i{{.*}} 0 784 // CHECK-TLS-NEXT: [[ARR_X_1_1_A:%.*]] = load [[INT]], ptr [[ARR_X_1_1_A_ADDR]] 785 // CHECK-TLS-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 786 // CHECK-TLS-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ARR_X_1_1_A]] 787 // CHECK-TLS-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 788 Res += arr_x[1][1].a; 789 // CHECK: [[ST_INT_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[ST_INT_ST]], i{{.*}} {{[0-9]+}}, ptr [[ST_INT_ST]].cache.) 790 // CHECK-NEXT: [[ST_INT_ST_VAL:%.*]] = load [[INT]], ptr [[ST_INT_ST_TEMP_ADDR]] 791 // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 792 // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_INT_ST_VAL]] 793 // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 794 // CHECK-DEBUG-NEXT: [[ST_INT_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[ST_INT_ST]], i{{.*}} {{[0-9]+}}, ptr 795 796 797 // CHECK-DEBUG-NEXT: [[ST_INT_ST_VAL:%.*]] = load [[INT]], ptr [[ST_INT_ST_TEMP_ADDR]] 798 // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 799 // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_INT_ST_VAL]] 800 // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 801 // OMP45-TLS: [[ST_INT_ST_VAL:%.*]] = load [[INT]], ptr [[ST_INT_ST_ADDR:[^,]+]] 802 // OMP45-TLS-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 803 // OMP45-TLS-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_INT_ST_VAL]] 804 // OMP45-TLS-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 805 Res += ST<int>::st; 806 // CHECK: [[ST_FLOAT_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[ST_FLOAT_ST]], i{{.*}} {{[0-9]+}}, ptr [[ST_FLOAT_ST]].cache.) 807 // CHECK-NEXT: [[ST_FLOAT_ST_VAL:%.*]] = load float, ptr [[ST_FLOAT_ST_TEMP_ADDR]] 808 // CHECK-NEXT: [[FLOAT_TO_INT_CONV:%.*]] = fptosi float [[ST_FLOAT_ST_VAL]] to [[INT]] 809 // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 810 // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[FLOAT_TO_INT_CONV]] 811 // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 812 // CHECK-DEBUG-NEXT: [[ST_FLOAT_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[ST_FLOAT_ST]], i{{.*}} {{[0-9]+}}, ptr 813 814 815 // CHECK-DEBUG-NEXT: [[ST_FLOAT_ST_VAL:%.*]] = load float, ptr [[ST_FLOAT_ST_TEMP_ADDR]] 816 // CHECK-DEBUG-NEXT: [[FLOAT_TO_INT_CONV:%.*]] = fptosi float [[ST_FLOAT_ST_VAL]] to [[INT]] 817 // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 818 // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[FLOAT_TO_INT_CONV]] 819 // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 820 // OMP45-TLS: [[ST_FLOAT_ST_VAL:%.*]] = load float, ptr [[ST_FLOAT_ST_ADDR:[^,]+]] 821 // OMP45-TLS-NEXT: [[FLOAT_TO_INT_CONV:%.*]] = fptosi float [[ST_FLOAT_ST_VAL]] to [[INT]] 822 // OMP45-TLS-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 823 // OMP45-TLS-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[FLOAT_TO_INT_CONV]] 824 // OMP45-TLS-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 825 Res += static_cast<int>(ST<float>::st); 826 // CHECK: [[ST_S4_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[ST_S4_ST]], i{{.*}} {{[0-9]+}}, ptr [[ST_S4_ST]].cache.) 827 // CHECK-NEXT: [[ST_S4_ST_A_ADDR:%.*]] = getelementptr inbounds [[S4]], ptr [[ST_S4_ST_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 828 // CHECK-NEXT: [[ST_S4_ST_A:%.*]] = load [[INT]], ptr [[ST_S4_ST_A_ADDR]] 829 // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 830 // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_S4_ST_A]] 831 // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 832 // CHECK-DEBUG-NEXT: [[ST_S4_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[ST_S4_ST]], i{{.*}} {{[0-9]+}}, ptr 833 834 835 // CHECK-DEBUG-NEXT: [[ST_S4_ST_A_ADDR:%.*]] = getelementptr inbounds [[S4]], ptr [[ST_S4_ST_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0 836 // CHECK-DEBUG-NEXT: [[ST_S4_ST_A:%.*]] = load [[INT]], ptr [[ST_S4_ST_A_ADDR]] 837 // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 838 // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_S4_ST_A]] 839 // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 840 // CHECK-TLS: [[ST_S4_ST_ADDR:%.*]] = call ptr [[ST_S4_ST_TLS_INITD]] 841 // CHECK-TLS-NEXT: [[ST_S4_ST_A_ADDR:%.*]] = getelementptr inbounds [[S4]], ptr [[ST_S4_ST_ADDR]], i{{.*}} 0, i{{.*}} 0 842 // CHECK-TLS-NEXT: [[ST_S4_ST_A:%.*]] = load [[INT]], ptr [[ST_S4_ST_A_ADDR]] 843 // CHECK-TLS-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 844 // CHECK-TLS-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_S4_ST_A]] 845 // CHECK-TLS-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]] 846 Res += ST<S4>::st.a; 847 // CHECK: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 848 // CHECK-NEXT: ret [[INT]] [[RES]] 849 // CHECK-DEBUG: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 850 // CHECK-DEBUG-NEXT: ret [[INT]] [[RES]] 851 // CHECK-TLS: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]] 852 // CHECK-TLS-NEXT: ret [[INT]] [[RES]] 853 return Res; 854 } 855 #endif 856 857 // OMP45: call {{.*}}void @__kmpc_threadprivate_register(ptr [[DEFAULT_LOC]], ptr [[ST_S4_ST]], ptr [[ST_S4_ST_CTOR:@\.__kmpc_global_ctor_\..+]], ptr null, ptr [[ST_S4_ST_DTOR:@\.__kmpc_global_dtor_\..+]]) 858 // OMP45: define internal {{.*}}ptr [[ST_S4_ST_CTOR]](ptr %0) 859 // OMP45: store ptr %0, ptr [[ARG_ADDR:%.*]], 860 // OMP45: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 861 // OMP45-NEXT: call {{.*}} [[S4_CTOR:@.+]](ptr {{[^,]*}} [[ARG]], {{.*}} 23) 862 // OMP45: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 863 // OMP45-NEXT: ret ptr [[ARG]] 864 // OMP45-NEXT: } 865 // OMP45: define {{.*}} [[S4_CTOR]](ptr {{.*}}, 866 // OMP45: define internal {{.*}}void [[ST_S4_ST_DTOR]](ptr %0) 867 // OMP45: store ptr %0, ptr [[ARG_ADDR:%.*]], 868 // OMP45: [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]] 869 // OMP45-NEXT: call {{.*}} [[S4_DTOR:@.+]](ptr {{[^,]*}} [[ARG]]) 870 // OMP45-NEXT: ret void 871 // OMP45-NEXT: } 872 // OMP45: define {{.*}} [[S4_DTOR]](ptr {{.*}}) 873 874 875 876 877 // OMP45-DEBUG: @__kmpc_global_thread_num 878 // OMP45-DEBUG: call {{.*}}void @__kmpc_threadprivate_register(ptr {{.*}}, ptr [[ST_S4_ST]], ptr [[ST_S4_ST_CTOR:@\.__kmpc_global_ctor_\..+]], ptr null, ptr [[ST_S4_ST_DTOR:@\.__kmpc_global_dtor_\..+]]) 879 // OMP45-DEBUG: define internal {{.*}}ptr [[ST_S4_ST_CTOR]](ptr %0) 880 // OMP45-DEBUG: } 881 // OMP45-DEBUG: define {{.*}} [[S4_CTOR:@.*]](ptr {{.*}}, 882 // OMP45-DEBUG: define internal {{.*}}void [[ST_S4_ST_DTOR]](ptr %0) 883 // OMP45-DEBUG: } 884 // OMP45-DEBUG: define {{.*}} [[S4_DTOR:@.*]](ptr {{.*}}) 885 886 // CHECK: define internal {{.*}}void {{@.*}}() 887 // CHECK-DAG: call {{.*}}void [[GS1_INIT]]() 888 // CHECK-DAG: call {{.*}}void [[ARR_X_INIT]]() 889 // CHECK: ret void 890 // CHECK-DEBUG: define internal {{.*}}void {{@.*}}() 891 // CHECK-DEBUG: ret void 892 893 // OMP45-TLS: define internal void [[GS1_CXX_INIT:@.*]]() 894 // OMP45-TLS: call void [[GS1_CTOR1:@.*]](ptr {{[^,]*}} [[GS1]], i32 5) 895 // OMP45-TLS: call i32 @__cxa_thread_atexit(ptr [[GS1_DTOR1:.*]], ptr [[GS1]] 896 // OMP45-TLS: } 897 // OMP45-TLS: define {{.*}}void [[GS1_CTOR1]](ptr {{.*}}, i32 {{.*}}) 898 // OMP45-TLS: call void [[GS1_CTOR2:@.*]](ptr {{.*}}, i32 {{.*}}) 899 // OMP45-TLS: } 900 // OMP45-TLS: define {{.*}}void [[GS1_DTOR1]](ptr {{.*}}) 901 // OMP45-TLS: call void [[GS1_DTOR2:@.*]](ptr {{.*}}) 902 // OMP45-TLS: } 903 // OMP45-TLS: define {{.*}}void [[GS1_CTOR2]](ptr {{.*}}, i32 {{.*}}) 904 // OMP45-TLS: define {{.*}}void [[GS1_DTOR2]](ptr {{.*}}) 905 906 // OMP45-TLS: define internal void [[GS2_CXX_INIT:@.*]]() 907 // OMP45-TLS: call void [[GS2_CTOR1:@.*]](ptr {{[^,]*}} [[GS2]], i32 27) 908 // OMP45-TLS: call i32 @__cxa_atexit(ptr [[GS2_DTOR1:.*]], ptr [[GS2]] 909 // OMP45-TLS: } 910 // OMP45-TLS: define {{.*}}void [[GS2_CTOR1]](ptr {{.*}}, i32 {{.*}}) 911 // OMP45-TLS: call void [[GS2_CTOR2:@.*]](ptr {{.*}}, i32 {{.*}}) 912 // OMP45-TLS: } 913 // OMP45-TLS: define {{.*}}void [[GS2_DTOR1]](ptr {{.*}}) 914 // OMP45-TLS: call void [[GS2_DTOR2:@.*]](ptr {{.*}}) 915 // OMP45-TLS: } 916 // OMP45-TLS: define {{.*}}void [[GS2_CTOR2]](ptr {{.*}}, i32 {{.*}}) 917 // OMP45-TLS: define {{.*}}void [[GS2_DTOR2]](ptr {{.*}}) 918 919 // OMP45-TLS: define internal void [[ARR_X_CXX_INIT:@.*]]() 920 // OMP45-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 0, i{{.*}} 0), i{{.*}} 1) 921 // OMP45-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 0, i{{.*}} 1), i{{.*}} 2) 922 // OMP45-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 0, i{{.*}} 2), i{{.*}} 3) 923 // OMP45-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 1, i{{.*}} 0), i{{.*}} 4) 924 // OMP45-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 1, i{{.*}} 1), i{{.*}} 5) 925 // OMP45-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 1, i{{.*}} 2), i{{.*}} 6) 926 // OMP45-TLS: call i32 @__cxa_thread_atexit(ptr [[ARR_X_CXX_DTOR:@[^,]+]] 927 // OMP45-TLS: define internal void [[ARR_X_CXX_DTOR]](ptr %0) 928 // OMP45-TLS: void [[GS1_DTOR1]](ptr {{.*}}) 929 930 // OMP45-TLS: define {{.*}}void [[SM_CTOR2]](ptr {{.*}}, i32 {{.*}}) 931 // OMP45-TLS: define {{.*}}void [[SM_DTOR2]](ptr {{.*}}) 932 933 // OMP45-TLS: define internal void [[ST_S4_ST_CXX_INIT]]() 934 // OMP45-TLS: call void [[ST_S4_ST_CTOR1:@.*]](ptr {{[^,]*}} [[ST_S4_ST]], i32 23) 935 // OMP45-TLS: call i32 @__cxa_thread_atexit(ptr [[ST_S4_ST_DTOR1:.*]], ptr [[ST_S4_ST]] 936 // OMP45-TLS: } 937 // OMP45-TLS: define {{.*}}void [[ST_S4_ST_CTOR1]](ptr {{.*}}, i32 {{.*}}) 938 // OMP45-TLS: call void [[ST_S4_ST_CTOR2:@.*]](ptr {{.*}}, i32 {{.*}}) 939 // OMP45-TLS: } 940 // OMP45-TLS: define {{.*}}void [[ST_S4_ST_DTOR1]](ptr {{.*}}) 941 // OMP45-TLS: call void [[ST_S4_ST_DTOR2:@.*]](ptr {{.*}}) 942 // OMP45-TLS: } 943 // OMP45-TLS: define {{.*}}void [[ST_S4_ST_CTOR2]](ptr {{.*}}, i32 {{.*}}) 944 // OMP45-TLS: define {{.*}}void [[ST_S4_ST_DTOR2]](ptr {{.*}}) 945 946 // OMP50-TLS: define internal void [[ST_S4_ST_CXX_INIT]]() 947 // OMP50-TLS: call void [[ST_S4_ST_CTOR1:@.*]](ptr {{[^,]*}} [[ST_S4_ST]], i32 23) 948 949 // OMP50-TLS: call i32 @__cxa_thread_atexit(ptr [[ST_S4_ST_DTOR1:.*]], ptr [[ST_S4_ST]] 950 // OMP50-TLS: } 951 // OMP50-TLS: define {{.*}}void [[ST_S4_ST_CTOR1]](ptr {{.*}}, i32 {{.*}}) 952 // OMP50-TLS: call void [[ST_S4_ST_CTOR2:@.*]](ptr {{.*}}, i32 {{.*}}) 953 // OMP50-TLS: } 954 // OMP50-TLS: define {{.*}}void [[ST_S4_ST_DTOR1]](ptr {{.*}}) 955 // OMP50-TLS: call void [[ST_S4_ST_DTOR2:@.*]](ptr {{.*}}) 956 // OMP50-TLS: } 957 // OMP50-TLS: define {{.*}}void [[ST_S4_ST_CTOR2]](ptr {{.*}}, i32 {{.*}}) 958 // OMP50-TLS: define {{.*}}void [[ST_S4_ST_DTOR2]](ptr {{.*}}) 959 960 // CHECK-TLS: define internal void @__tls_init() 961 // CHECK-TLS: [[GRD:%.*]] = load i8, ptr @__tls_guard 962 // CHECK-TLS-NEXT: [[IS_INIT:%.*]] = icmp eq i8 [[GRD]], 0 963 // CHECK-TLS-NEXT: br i1 [[IS_INIT]], label %[[INIT_LABEL:[^,]+]], label %[[DONE_LABEL:[^,]+]]{{.*}} 964 // CHECK-TLS: [[INIT_LABEL]] 965 // CHECK-TLS-NEXT: store i8 1, ptr @__tls_guard 966 // CHECK-TLS: call void [[GS1_CXX_INIT]] 967 // CHECK-TLS-NOT: call void [[GS2_CXX_INIT]] 968 // CHECK-TLS: call void [[ARR_X_CXX_INIT]] 969 // CHECK-TLS-NOT: call void [[ST_S4_ST_CXX_INIT]] 970 // CHECK-TLS: [[DONE_LABEL]] 971 972 // CHECK-TLS-DAG: declare {{.*}} void [[GS3_TLS_INIT]] 973 // CHECK-TLS-DAG: declare {{.*}} void [[STATIC_S_TLS_INIT]] 974 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_. 975 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] { 976 // CHECK1-NEXT: entry: 977 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 978 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 979 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 980 // CHECK1-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 5) 981 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 982 // CHECK1-NEXT: ret ptr [[TMP2]] 983 // 984 // 985 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S1C1Ei 986 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 987 // CHECK1-NEXT: entry: 988 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 989 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 990 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 991 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 992 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 993 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 994 // CHECK1-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 995 // CHECK1-NEXT: ret void 996 // 997 // 998 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_. 999 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1000 // CHECK1-NEXT: entry: 1001 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1002 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1003 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1004 // CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR3:[0-9]+]] 1005 // CHECK1-NEXT: ret void 1006 // 1007 // 1008 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S1D1Ev 1009 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { 1010 // CHECK1-NEXT: entry: 1011 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1012 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1013 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1014 // CHECK1-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] 1015 // CHECK1-NEXT: ret void 1016 // 1017 // 1018 // CHECK1-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_. 1019 // CHECK1-SAME: () #[[ATTR0]] { 1020 // CHECK1-NEXT: entry: 1021 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) 1022 // CHECK1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZL3gs1, ptr @.__kmpc_global_ctor_., ptr null, ptr @.__kmpc_global_dtor_.) 1023 // CHECK1-NEXT: ret void 1024 // 1025 // 1026 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..1 1027 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] personality ptr @__gxx_personality_v0 { 1028 // CHECK1-NEXT: entry: 1029 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1030 // CHECK1-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 1031 // CHECK1-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 1032 // CHECK1-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 1033 // CHECK1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 1034 // CHECK1-NEXT: [[ARRAYINIT_ENDOFINIT7:%.*]] = alloca ptr, align 8 1035 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1036 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1037 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[ARRAYINIT_ENDOFINIT]], align 8 1038 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8 1039 // CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 1) 1040 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] 1041 // CHECK1: invoke.cont: 1042 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 1 1043 // CHECK1-NEXT: store ptr [[ARRAYINIT_ELEMENT]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8 1044 // CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1045 // CHECK1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]] 1046 // CHECK1: invoke.cont2: 1047 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP1]], i64 2 1048 // CHECK1-NEXT: store ptr [[ARRAYINIT_ELEMENT3]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8 1049 // CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT3]], i32 noundef 3) 1050 // CHECK1-NEXT: to label [[INVOKE_CONT4:%.*]] unwind label [[LPAD]] 1051 // CHECK1: invoke.cont4: 1052 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT6:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP1]], i64 1 1053 // CHECK1-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT]], align 8 1054 // CHECK1-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8 1055 // CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT6]], i32 noundef 4) 1056 // CHECK1-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD8:%.*]] 1057 // CHECK1: invoke.cont9: 1058 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT10:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT6]], i64 1 1059 // CHECK1-NEXT: store ptr [[ARRAYINIT_ELEMENT10]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8 1060 // CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT10]], i32 noundef 5) 1061 // CHECK1-NEXT: to label [[INVOKE_CONT11:%.*]] unwind label [[LPAD8]] 1062 // CHECK1: invoke.cont11: 1063 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT12:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT6]], i64 2 1064 // CHECK1-NEXT: store ptr [[ARRAYINIT_ELEMENT12]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8 1065 // CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT12]], i32 noundef 6) 1066 // CHECK1-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[LPAD8]] 1067 // CHECK1: invoke.cont13: 1068 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1069 // CHECK1-NEXT: ret ptr [[TMP2]] 1070 // CHECK1: lpad: 1071 // CHECK1-NEXT: [[TMP3:%.*]] = landingpad { ptr, i32 } 1072 // CHECK1-NEXT: cleanup 1073 // CHECK1-NEXT: [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 0 1074 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[EXN_SLOT]], align 8 1075 // CHECK1-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 1 1076 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[EHSELECTOR_SLOT]], align 4 1077 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8 1078 // CHECK1-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP6]] 1079 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY:%.*]] 1080 // CHECK1: arraydestroy.body: 1081 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1082 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1083 // CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 1084 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]] 1085 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5]], label [[ARRAYDESTROY_BODY]] 1086 // CHECK1: arraydestroy.done5: 1087 // CHECK1-NEXT: br label [[EHCLEANUP:%.*]] 1088 // CHECK1: lpad8: 1089 // CHECK1-NEXT: [[TMP7:%.*]] = landingpad { ptr, i32 } 1090 // CHECK1-NEXT: cleanup 1091 // CHECK1-NEXT: [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 0 1092 // CHECK1-NEXT: store ptr [[TMP8]], ptr [[EXN_SLOT]], align 8 1093 // CHECK1-NEXT: [[TMP9:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 1 1094 // CHECK1-NEXT: store i32 [[TMP9]], ptr [[EHSELECTOR_SLOT]], align 4 1095 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT7]], align 8 1096 // CHECK1-NEXT: [[ARRAYDESTROY_ISEMPTY14:%.*]] = icmp eq ptr [[ARRAYINIT_ELEMENT6]], [[TMP10]] 1097 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY14]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15:%.*]] 1098 // CHECK1: arraydestroy.body15: 1099 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi ptr [ [[TMP10]], [[LPAD8]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] 1100 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST16]], i64 -1 1101 // CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] 1102 // CHECK1-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT17]], [[ARRAYINIT_ELEMENT6]] 1103 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_BODY15]] 1104 // CHECK1: arraydestroy.done19: 1105 // CHECK1-NEXT: br label [[EHCLEANUP]] 1106 // CHECK1: ehcleanup: 1107 // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8 1108 // CHECK1-NEXT: [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP1]], i64 0, i64 0 1109 // CHECK1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP11]], i64 0, i64 0 1110 // CHECK1-NEXT: [[ARRAYDESTROY_ISEMPTY20:%.*]] = icmp eq ptr [[PAD_ARRAYBEGIN]], [[PAD_ARRAYEND]] 1111 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY20]], label [[ARRAYDESTROY_DONE25:%.*]], label [[ARRAYDESTROY_BODY21:%.*]] 1112 // CHECK1: arraydestroy.body21: 1113 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST22:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT23:%.*]], [[ARRAYDESTROY_BODY21]] ] 1114 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT23]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST22]], i64 -1 1115 // CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT23]]) #[[ATTR3]] 1116 // CHECK1-NEXT: [[ARRAYDESTROY_DONE24:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT23]], [[PAD_ARRAYBEGIN]] 1117 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE24]], label [[ARRAYDESTROY_DONE25]], label [[ARRAYDESTROY_BODY21]] 1118 // CHECK1: arraydestroy.done25: 1119 // CHECK1-NEXT: br label [[EH_RESUME:%.*]] 1120 // CHECK1: eh.resume: 1121 // CHECK1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 1122 // CHECK1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 1123 // CHECK1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 1124 // CHECK1-NEXT: [[LPAD_VAL26:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 1125 // CHECK1-NEXT: resume { ptr, i32 } [[LPAD_VAL26]] 1126 // 1127 // 1128 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..2 1129 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1130 // CHECK1-NEXT: entry: 1131 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1132 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1133 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1134 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 6 1135 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1136 // CHECK1: arraydestroy.body: 1137 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1138 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1139 // CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 1140 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]] 1141 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1142 // CHECK1: arraydestroy.done1: 1143 // CHECK1-NEXT: ret void 1144 // 1145 // 1146 // CHECK1-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_..3 1147 // CHECK1-SAME: () #[[ATTR0]] { 1148 // CHECK1-NEXT: entry: 1149 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 1150 // CHECK1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @arr_x, ptr @.__kmpc_global_ctor_..1, ptr null, ptr @.__kmpc_global_dtor_..2) 1151 // CHECK1-NEXT: ret void 1152 // 1153 // 1154 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 1155 // CHECK1-SAME: () #[[ATTR0]] { 1156 // CHECK1-NEXT: entry: 1157 // CHECK1-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5) 1158 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3]] 1159 // CHECK1-NEXT: ret void 1160 // 1161 // 1162 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S1C2Ei 1163 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 1164 // CHECK1-NEXT: entry: 1165 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1166 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1167 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1168 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1169 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1170 // CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 1171 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1172 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4 1173 // CHECK1-NEXT: ret void 1174 // 1175 // 1176 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S1D2Ev 1177 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 1178 // CHECK1-NEXT: entry: 1179 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1180 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1181 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1182 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 1183 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 1184 // CHECK1-NEXT: ret void 1185 // 1186 // 1187 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.4 1188 // CHECK1-SAME: () #[[ATTR0]] { 1189 // CHECK1-NEXT: entry: 1190 // CHECK1-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27) 1191 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]] 1192 // CHECK1-NEXT: ret void 1193 // 1194 // 1195 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S2C1Ei 1196 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1197 // CHECK1-NEXT: entry: 1198 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1199 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1200 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1201 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1202 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1203 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1204 // CHECK1-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]) 1205 // CHECK1-NEXT: ret void 1206 // 1207 // 1208 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S2D1Ev 1209 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 1210 // CHECK1-NEXT: entry: 1211 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1212 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1213 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1214 // CHECK1-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]] 1215 // CHECK1-NEXT: ret void 1216 // 1217 // 1218 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S2C2Ei 1219 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 1220 // CHECK1-NEXT: entry: 1221 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1222 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1223 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1224 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1225 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1226 // CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0 1227 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1228 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8 1229 // CHECK1-NEXT: ret void 1230 // 1231 // 1232 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S2D2Ev 1233 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 1234 // CHECK1-NEXT: entry: 1235 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1236 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1237 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1238 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0 1239 // CHECK1-NEXT: store i32 0, ptr [[A]], align 8 1240 // CHECK1-NEXT: ret void 1241 // 1242 // 1243 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.5 1244 // CHECK1-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 { 1245 // CHECK1-NEXT: entry: 1246 // CHECK1-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 1247 // CHECK1-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 1248 // CHECK1-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 1249 // CHECK1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 1250 // CHECK1-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 1251 // CHECK1-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8 1252 // CHECK1-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8 1253 // CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) 1254 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] 1255 // CHECK1: invoke.cont: 1256 // CHECK1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8 1257 // CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) 1258 // CHECK1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]] 1259 // CHECK1: invoke.cont2: 1260 // CHECK1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8 1261 // CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) 1262 // CHECK1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] 1263 // CHECK1: invoke.cont3: 1264 // CHECK1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8 1265 // CHECK1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 1266 // CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) 1267 // CHECK1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]] 1268 // CHECK1: invoke.cont7: 1269 // CHECK1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 1270 // CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) 1271 // CHECK1-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]] 1272 // CHECK1: invoke.cont8: 1273 // CHECK1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 1274 // CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) 1275 // CHECK1-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]] 1276 // CHECK1: invoke.cont9: 1277 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]] 1278 // CHECK1-NEXT: ret void 1279 // CHECK1: lpad: 1280 // CHECK1-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } 1281 // CHECK1-NEXT: cleanup 1282 // CHECK1-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0 1283 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8 1284 // CHECK1-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1 1285 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4 1286 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8 1287 // CHECK1-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]] 1288 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]] 1289 // CHECK1: arraydestroy.body: 1290 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1291 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1292 // CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 1293 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x 1294 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]] 1295 // CHECK1: arraydestroy.done4: 1296 // CHECK1-NEXT: br label [[EHCLEANUP:%.*]] 1297 // CHECK1: lpad6: 1298 // CHECK1-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } 1299 // CHECK1-NEXT: cleanup 1300 // CHECK1-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0 1301 // CHECK1-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8 1302 // CHECK1-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1 1303 // CHECK1-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4 1304 // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8 1305 // CHECK1-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]] 1306 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]] 1307 // CHECK1: arraydestroy.body11: 1308 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ] 1309 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1 1310 // CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] 1311 // CHECK1-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1) 1312 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]] 1313 // CHECK1: arraydestroy.done15: 1314 // CHECK1-NEXT: br label [[EHCLEANUP]] 1315 // CHECK1: ehcleanup: 1316 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8 1317 // CHECK1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0 1318 // CHECK1-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]] 1319 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]] 1320 // CHECK1: arraydestroy.body17: 1321 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] 1322 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 1323 // CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] 1324 // CHECK1-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x 1325 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] 1326 // CHECK1: arraydestroy.done21: 1327 // CHECK1-NEXT: br label [[EH_RESUME:%.*]] 1328 // CHECK1: eh.resume: 1329 // CHECK1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 1330 // CHECK1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 1331 // CHECK1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 1332 // CHECK1-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 1333 // CHECK1-NEXT: resume { ptr, i32 } [[LPAD_VAL22]] 1334 // 1335 // 1336 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1337 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1338 // CHECK1-NEXT: entry: 1339 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1340 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1341 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1342 // CHECK1: arraydestroy.body: 1343 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1344 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1345 // CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 1346 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x 1347 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1348 // CHECK1: arraydestroy.done1: 1349 // CHECK1-NEXT: ret void 1350 // 1351 // 1352 // CHECK1-LABEL: define {{[^@]+}}@main 1353 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] personality ptr @__gxx_personality_v0 { 1354 // CHECK1-NEXT: entry: 1355 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1356 // CHECK1-NEXT: [[RES:%.*]] = alloca i32, align 4 1357 // CHECK1-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 1358 // CHECK1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 1359 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 1360 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 1361 // CHECK1-NEXT: [[TMP1:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8 1362 // CHECK1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP1]], 0 1363 // CHECK1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]] 1364 // CHECK1: init.check: 1365 // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]] 1366 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 1367 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] 1368 // CHECK1: init: 1369 // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 1370 // CHECK1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZZ4mainE2sm, ptr @.__kmpc_global_ctor_..6, ptr null, ptr @.__kmpc_global_dtor_..7) 1371 // CHECK1-NEXT: [[TMP4:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.) 1372 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP4]], i32 0, i32 0 1373 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 1374 // CHECK1-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP5]]) 1375 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] 1376 // CHECK1: invoke.cont: 1377 // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]] 1378 // CHECK1-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]] 1379 // CHECK1-NEXT: br label [[INIT_END]] 1380 // CHECK1: init.end: 1381 // CHECK1-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.) 1382 // CHECK1-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP7]], i32 0, i32 0 1383 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4 1384 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[RES]], align 4 1385 // CHECK1-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZZ4mainE2sm, i64 24, ptr @_ZZ4mainE2sm.cache.) 1386 // CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[TMP9]], i32 0, i32 0 1387 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A2]], align 8 1388 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4 1389 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP10]] 1390 // CHECK1-NEXT: store i32 [[ADD]], ptr [[RES]], align 4 1391 // CHECK1-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.) 1392 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP12]], i32 0, i32 0 1393 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[A3]], align 4 1394 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4 1395 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 1396 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 1397 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZL3gs2, align 8 1398 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4 1399 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 1400 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4 1401 // CHECK1-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.) 1402 // CHECK1-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP17]], i32 0, i32 0 1403 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A6]], align 4 1404 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4 1405 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]] 1406 // CHECK1-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4 1407 // CHECK1-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.) 1408 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], i64 0, i64 1 1409 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 1410 // CHECK1-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0 1411 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A9]], align 4 1412 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4 1413 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP21]] 1414 // CHECK1-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4 1415 // CHECK1-NEXT: [[TMP23:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.) 1416 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4 1417 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4 1418 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP25]], [[TMP24]] 1419 // CHECK1-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4 1420 // CHECK1-NEXT: [[TMP26:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.) 1421 // CHECK1-NEXT: [[TMP27:%.*]] = load float, ptr [[TMP26]], align 4 1422 // CHECK1-NEXT: [[CONV:%.*]] = fptosi float [[TMP27]] to i32 1423 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4 1424 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[CONV]] 1425 // CHECK1-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4 1426 // CHECK1-NEXT: [[TMP29:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.) 1427 // CHECK1-NEXT: [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP29]], i32 0, i32 0 1428 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[A13]], align 4 1429 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[RES]], align 4 1430 // CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP31]], [[TMP30]] 1431 // CHECK1-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4 1432 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[RES]], align 4 1433 // CHECK1-NEXT: ret i32 [[TMP32]] 1434 // CHECK1: lpad: 1435 // CHECK1-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 } 1436 // CHECK1-NEXT: cleanup 1437 // CHECK1-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0 1438 // CHECK1-NEXT: store ptr [[TMP34]], ptr [[EXN_SLOT]], align 8 1439 // CHECK1-NEXT: [[TMP35:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 1 1440 // CHECK1-NEXT: store i32 [[TMP35]], ptr [[EHSELECTOR_SLOT]], align 4 1441 // CHECK1-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]] 1442 // CHECK1-NEXT: br label [[EH_RESUME:%.*]] 1443 // CHECK1: eh.resume: 1444 // CHECK1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 1445 // CHECK1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 1446 // CHECK1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 1447 // CHECK1-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 1448 // CHECK1-NEXT: resume { ptr, i32 } [[LPAD_VAL15]] 1449 // 1450 // 1451 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..6 1452 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1453 // CHECK1-NEXT: entry: 1454 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1455 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 1456 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1457 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1458 // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.) 1459 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0 1460 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4 1461 // CHECK1-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) [[TMP2]], i32 noundef [[TMP4]]) 1462 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1463 // CHECK1-NEXT: ret ptr [[TMP5]] 1464 // 1465 // 1466 // CHECK1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei 1467 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1468 // CHECK1-NEXT: entry: 1469 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1470 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1471 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1472 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1473 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1474 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1475 // CHECK1-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]) 1476 // CHECK1-NEXT: ret void 1477 // 1478 // 1479 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..7 1480 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1481 // CHECK1-NEXT: entry: 1482 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1483 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1484 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1485 // CHECK1-NEXT: call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[TMP1]]) #[[ATTR3]] 1486 // CHECK1-NEXT: ret void 1487 // 1488 // 1489 // CHECK1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev 1490 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 1491 // CHECK1-NEXT: entry: 1492 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1493 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1494 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1495 // CHECK1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] 1496 // CHECK1-NEXT: ret void 1497 // 1498 // 1499 // CHECK1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei 1500 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 1501 // CHECK1-NEXT: entry: 1502 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1503 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1504 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1505 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1506 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1507 // CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0 1508 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1509 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8 1510 // CHECK1-NEXT: ret void 1511 // 1512 // 1513 // CHECK1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev 1514 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 1515 // CHECK1-NEXT: entry: 1516 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1517 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1518 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1519 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0 1520 // CHECK1-NEXT: store i32 0, ptr [[A]], align 8 1521 // CHECK1-NEXT: ret void 1522 // 1523 // 1524 // CHECK1-LABEL: define {{[^@]+}}@_Z6foobarv 1525 // CHECK1-SAME: () #[[ATTR2]] { 1526 // CHECK1-NEXT: entry: 1527 // CHECK1-NEXT: [[RES:%.*]] = alloca i32, align 4 1528 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 1529 // CHECK1-NEXT: [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.) 1530 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP1]], i32 0, i32 0 1531 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1532 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[RES]], align 4 1533 // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.) 1534 // CHECK1-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0 1535 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A1]], align 4 1536 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[RES]], align 4 1537 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 1538 // CHECK1-NEXT: store i32 [[ADD]], ptr [[RES]], align 4 1539 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr @_ZL3gs2, align 8 1540 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[RES]], align 4 1541 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] 1542 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4 1543 // CHECK1-NEXT: [[TMP8:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.) 1544 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP8]], i32 0, i32 0 1545 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A3]], align 4 1546 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4 1547 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 1548 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 1549 // CHECK1-NEXT: [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.) 1550 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], i64 0, i64 1 1551 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 1552 // CHECK1-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0 1553 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[A6]], align 4 1554 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4 1555 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP13]], [[TMP12]] 1556 // CHECK1-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4 1557 // CHECK1-NEXT: [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.) 1558 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 1559 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4 1560 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 1561 // CHECK1-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4 1562 // CHECK1-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.) 1563 // CHECK1-NEXT: [[TMP18:%.*]] = load float, ptr [[TMP17]], align 4 1564 // CHECK1-NEXT: [[CONV:%.*]] = fptosi float [[TMP18]] to i32 1565 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4 1566 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], [[CONV]] 1567 // CHECK1-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4 1568 // CHECK1-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.) 1569 // CHECK1-NEXT: [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP20]], i32 0, i32 0 1570 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A10]], align 4 1571 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4 1572 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]] 1573 // CHECK1-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4 1574 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[RES]], align 4 1575 // CHECK1-NEXT: ret i32 [[TMP23]] 1576 // 1577 // 1578 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.8 1579 // CHECK1-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) { 1580 // CHECK1-NEXT: entry: 1581 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8 1582 // CHECK1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 1583 // CHECK1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]] 1584 // CHECK1: init.check: 1585 // CHECK1-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8 1586 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 1587 // CHECK1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZN2STI2S4E2stE, ptr @.__kmpc_global_ctor_..9, ptr null, ptr @.__kmpc_global_dtor_..10) 1588 // CHECK1-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23) 1589 // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]] 1590 // CHECK1-NEXT: br label [[INIT_END]] 1591 // CHECK1: init.end: 1592 // CHECK1-NEXT: ret void 1593 // 1594 // 1595 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..9 1596 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1597 // CHECK1-NEXT: entry: 1598 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1599 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1600 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1601 // CHECK1-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]], i32 noundef 23) 1602 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1603 // CHECK1-NEXT: ret ptr [[TMP2]] 1604 // 1605 // 1606 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S4C1Ei 1607 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1608 // CHECK1-NEXT: entry: 1609 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1610 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1611 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1612 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1613 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1614 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1615 // CHECK1-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]) 1616 // CHECK1-NEXT: ret void 1617 // 1618 // 1619 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..10 1620 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1621 // CHECK1-NEXT: entry: 1622 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1623 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1624 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1625 // CHECK1-NEXT: call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]]) #[[ATTR3]] 1626 // CHECK1-NEXT: ret void 1627 // 1628 // 1629 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S4D1Ev 1630 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 1631 // CHECK1-NEXT: entry: 1632 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1633 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1634 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1635 // CHECK1-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] 1636 // CHECK1-NEXT: ret void 1637 // 1638 // 1639 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S4C2Ei 1640 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 1641 // CHECK1-NEXT: entry: 1642 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1643 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1644 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1645 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1646 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1647 // CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0 1648 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1649 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4 1650 // CHECK1-NEXT: ret void 1651 // 1652 // 1653 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S4D2Ev 1654 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 1655 // CHECK1-NEXT: entry: 1656 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1657 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1658 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1659 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0 1660 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 1661 // CHECK1-NEXT: ret void 1662 // 1663 // 1664 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp 1665 // CHECK1-SAME: () #[[ATTR0]] { 1666 // CHECK1-NEXT: entry: 1667 // CHECK1-NEXT: call void @__cxx_global_var_init() 1668 // CHECK1-NEXT: call void @.__omp_threadprivate_init_.() 1669 // CHECK1-NEXT: call void @__cxx_global_var_init.4() 1670 // CHECK1-NEXT: call void @__cxx_global_var_init.5() 1671 // CHECK1-NEXT: call void @.__omp_threadprivate_init_..3() 1672 // CHECK1-NEXT: ret void 1673 // 1674 // 1675 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init 1676 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 1677 // CHECK2-NEXT: entry: 1678 // CHECK2-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5) 1679 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]] 1680 // CHECK2-NEXT: ret void 1681 // 1682 // 1683 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S1C1Ei 1684 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1685 // CHECK2-NEXT: entry: 1686 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1687 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1688 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1689 // CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1690 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1691 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1692 // CHECK2-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1693 // CHECK2-NEXT: ret void 1694 // 1695 // 1696 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S1D1Ev 1697 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { 1698 // CHECK2-NEXT: entry: 1699 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1700 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1701 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1702 // CHECK2-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] 1703 // CHECK2-NEXT: ret void 1704 // 1705 // 1706 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_. 1707 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1708 // CHECK2-NEXT: entry: 1709 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1710 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1711 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1712 // CHECK2-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 5) 1713 // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1714 // CHECK2-NEXT: ret ptr [[TMP2]] 1715 // 1716 // 1717 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_. 1718 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1719 // CHECK2-NEXT: entry: 1720 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1721 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1722 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1723 // CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR3]] 1724 // CHECK2-NEXT: ret void 1725 // 1726 // 1727 // CHECK2-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_. 1728 // CHECK2-SAME: () #[[ATTR0]] { 1729 // CHECK2-NEXT: entry: 1730 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) 1731 // CHECK2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZL3gs1, ptr @.__kmpc_global_ctor_., ptr null, ptr @.__kmpc_global_dtor_.) 1732 // CHECK2-NEXT: ret void 1733 // 1734 // 1735 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1736 // CHECK2-SAME: () #[[ATTR0]] { 1737 // CHECK2-NEXT: entry: 1738 // CHECK2-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27) 1739 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]] 1740 // CHECK2-NEXT: ret void 1741 // 1742 // 1743 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S2C1Ei 1744 // CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1745 // CHECK2-NEXT: entry: 1746 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1747 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1748 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1749 // CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1750 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1751 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1752 // CHECK2-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]) 1753 // CHECK2-NEXT: ret void 1754 // 1755 // 1756 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S2D1Ev 1757 // CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 1758 // CHECK2-NEXT: entry: 1759 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1760 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1761 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1762 // CHECK2-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]] 1763 // CHECK2-NEXT: ret void 1764 // 1765 // 1766 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1767 // CHECK2-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 { 1768 // CHECK2-NEXT: entry: 1769 // CHECK2-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 1770 // CHECK2-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 1771 // CHECK2-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 1772 // CHECK2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 1773 // CHECK2-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 1774 // CHECK2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8 1775 // CHECK2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8 1776 // CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) 1777 // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] 1778 // CHECK2: invoke.cont: 1779 // CHECK2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8 1780 // CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) 1781 // CHECK2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]] 1782 // CHECK2: invoke.cont2: 1783 // CHECK2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8 1784 // CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) 1785 // CHECK2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] 1786 // CHECK2: invoke.cont3: 1787 // CHECK2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8 1788 // CHECK2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 1789 // CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) 1790 // CHECK2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]] 1791 // CHECK2: invoke.cont7: 1792 // CHECK2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 1793 // CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) 1794 // CHECK2-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]] 1795 // CHECK2: invoke.cont8: 1796 // CHECK2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 1797 // CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) 1798 // CHECK2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]] 1799 // CHECK2: invoke.cont9: 1800 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]] 1801 // CHECK2-NEXT: ret void 1802 // CHECK2: lpad: 1803 // CHECK2-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } 1804 // CHECK2-NEXT: cleanup 1805 // CHECK2-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0 1806 // CHECK2-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8 1807 // CHECK2-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1 1808 // CHECK2-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4 1809 // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8 1810 // CHECK2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]] 1811 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]] 1812 // CHECK2: arraydestroy.body: 1813 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1814 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1815 // CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 1816 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x 1817 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]] 1818 // CHECK2: arraydestroy.done4: 1819 // CHECK2-NEXT: br label [[EHCLEANUP:%.*]] 1820 // CHECK2: lpad6: 1821 // CHECK2-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } 1822 // CHECK2-NEXT: cleanup 1823 // CHECK2-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0 1824 // CHECK2-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8 1825 // CHECK2-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1 1826 // CHECK2-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4 1827 // CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8 1828 // CHECK2-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]] 1829 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]] 1830 // CHECK2: arraydestroy.body11: 1831 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ] 1832 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1 1833 // CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] 1834 // CHECK2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1) 1835 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]] 1836 // CHECK2: arraydestroy.done15: 1837 // CHECK2-NEXT: br label [[EHCLEANUP]] 1838 // CHECK2: ehcleanup: 1839 // CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8 1840 // CHECK2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0 1841 // CHECK2-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]] 1842 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]] 1843 // CHECK2: arraydestroy.body17: 1844 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] 1845 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 1846 // CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] 1847 // CHECK2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x 1848 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] 1849 // CHECK2: arraydestroy.done21: 1850 // CHECK2-NEXT: br label [[EH_RESUME:%.*]] 1851 // CHECK2: eh.resume: 1852 // CHECK2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 1853 // CHECK2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 1854 // CHECK2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 1855 // CHECK2-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 1856 // CHECK2-NEXT: resume { ptr, i32 } [[LPAD_VAL22]] 1857 // 1858 // 1859 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1860 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1861 // CHECK2-NEXT: entry: 1862 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1863 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1864 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1865 // CHECK2: arraydestroy.body: 1866 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1867 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1868 // CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 1869 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x 1870 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1871 // CHECK2: arraydestroy.done1: 1872 // CHECK2-NEXT: ret void 1873 // 1874 // 1875 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..3 1876 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] personality ptr @__gxx_personality_v0 { 1877 // CHECK2-NEXT: entry: 1878 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1879 // CHECK2-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 1880 // CHECK2-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 1881 // CHECK2-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 1882 // CHECK2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 1883 // CHECK2-NEXT: [[ARRAYINIT_ENDOFINIT7:%.*]] = alloca ptr, align 8 1884 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1885 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1886 // CHECK2-NEXT: store ptr [[TMP1]], ptr [[ARRAYINIT_ENDOFINIT]], align 8 1887 // CHECK2-NEXT: store ptr [[TMP1]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8 1888 // CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 1) 1889 // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] 1890 // CHECK2: invoke.cont: 1891 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 1 1892 // CHECK2-NEXT: store ptr [[ARRAYINIT_ELEMENT]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8 1893 // CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1894 // CHECK2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]] 1895 // CHECK2: invoke.cont2: 1896 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP1]], i64 2 1897 // CHECK2-NEXT: store ptr [[ARRAYINIT_ELEMENT3]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8 1898 // CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT3]], i32 noundef 3) 1899 // CHECK2-NEXT: to label [[INVOKE_CONT4:%.*]] unwind label [[LPAD]] 1900 // CHECK2: invoke.cont4: 1901 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT6:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP1]], i64 1 1902 // CHECK2-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT]], align 8 1903 // CHECK2-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8 1904 // CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT6]], i32 noundef 4) 1905 // CHECK2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD8:%.*]] 1906 // CHECK2: invoke.cont9: 1907 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT10:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT6]], i64 1 1908 // CHECK2-NEXT: store ptr [[ARRAYINIT_ELEMENT10]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8 1909 // CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT10]], i32 noundef 5) 1910 // CHECK2-NEXT: to label [[INVOKE_CONT11:%.*]] unwind label [[LPAD8]] 1911 // CHECK2: invoke.cont11: 1912 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT12:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT6]], i64 2 1913 // CHECK2-NEXT: store ptr [[ARRAYINIT_ELEMENT12]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8 1914 // CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT12]], i32 noundef 6) 1915 // CHECK2-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[LPAD8]] 1916 // CHECK2: invoke.cont13: 1917 // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1918 // CHECK2-NEXT: ret ptr [[TMP2]] 1919 // CHECK2: lpad: 1920 // CHECK2-NEXT: [[TMP3:%.*]] = landingpad { ptr, i32 } 1921 // CHECK2-NEXT: cleanup 1922 // CHECK2-NEXT: [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 0 1923 // CHECK2-NEXT: store ptr [[TMP4]], ptr [[EXN_SLOT]], align 8 1924 // CHECK2-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 1 1925 // CHECK2-NEXT: store i32 [[TMP5]], ptr [[EHSELECTOR_SLOT]], align 4 1926 // CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8 1927 // CHECK2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP6]] 1928 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY:%.*]] 1929 // CHECK2: arraydestroy.body: 1930 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1931 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1932 // CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 1933 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]] 1934 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5]], label [[ARRAYDESTROY_BODY]] 1935 // CHECK2: arraydestroy.done5: 1936 // CHECK2-NEXT: br label [[EHCLEANUP:%.*]] 1937 // CHECK2: lpad8: 1938 // CHECK2-NEXT: [[TMP7:%.*]] = landingpad { ptr, i32 } 1939 // CHECK2-NEXT: cleanup 1940 // CHECK2-NEXT: [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 0 1941 // CHECK2-NEXT: store ptr [[TMP8]], ptr [[EXN_SLOT]], align 8 1942 // CHECK2-NEXT: [[TMP9:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 1 1943 // CHECK2-NEXT: store i32 [[TMP9]], ptr [[EHSELECTOR_SLOT]], align 4 1944 // CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT7]], align 8 1945 // CHECK2-NEXT: [[ARRAYDESTROY_ISEMPTY14:%.*]] = icmp eq ptr [[ARRAYINIT_ELEMENT6]], [[TMP10]] 1946 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY14]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15:%.*]] 1947 // CHECK2: arraydestroy.body15: 1948 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi ptr [ [[TMP10]], [[LPAD8]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] 1949 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST16]], i64 -1 1950 // CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] 1951 // CHECK2-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT17]], [[ARRAYINIT_ELEMENT6]] 1952 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_BODY15]] 1953 // CHECK2: arraydestroy.done19: 1954 // CHECK2-NEXT: br label [[EHCLEANUP]] 1955 // CHECK2: ehcleanup: 1956 // CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8 1957 // CHECK2-NEXT: [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP1]], i64 0, i64 0 1958 // CHECK2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP11]], i64 0, i64 0 1959 // CHECK2-NEXT: [[ARRAYDESTROY_ISEMPTY20:%.*]] = icmp eq ptr [[PAD_ARRAYBEGIN]], [[PAD_ARRAYEND]] 1960 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY20]], label [[ARRAYDESTROY_DONE25:%.*]], label [[ARRAYDESTROY_BODY21:%.*]] 1961 // CHECK2: arraydestroy.body21: 1962 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST22:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT23:%.*]], [[ARRAYDESTROY_BODY21]] ] 1963 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT23]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST22]], i64 -1 1964 // CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT23]]) #[[ATTR3]] 1965 // CHECK2-NEXT: [[ARRAYDESTROY_DONE24:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT23]], [[PAD_ARRAYBEGIN]] 1966 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE24]], label [[ARRAYDESTROY_DONE25]], label [[ARRAYDESTROY_BODY21]] 1967 // CHECK2: arraydestroy.done25: 1968 // CHECK2-NEXT: br label [[EH_RESUME:%.*]] 1969 // CHECK2: eh.resume: 1970 // CHECK2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 1971 // CHECK2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 1972 // CHECK2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 1973 // CHECK2-NEXT: [[LPAD_VAL26:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 1974 // CHECK2-NEXT: resume { ptr, i32 } [[LPAD_VAL26]] 1975 // 1976 // 1977 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..4 1978 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1979 // CHECK2-NEXT: entry: 1980 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1981 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1982 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1983 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 6 1984 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1985 // CHECK2: arraydestroy.body: 1986 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1987 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1988 // CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 1989 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]] 1990 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1991 // CHECK2: arraydestroy.done1: 1992 // CHECK2-NEXT: ret void 1993 // 1994 // 1995 // CHECK2-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_..5 1996 // CHECK2-SAME: () #[[ATTR0]] { 1997 // CHECK2-NEXT: entry: 1998 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 1999 // CHECK2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @arr_x, ptr @.__kmpc_global_ctor_..3, ptr null, ptr @.__kmpc_global_dtor_..4) 2000 // CHECK2-NEXT: ret void 2001 // 2002 // 2003 // CHECK2-LABEL: define {{[^@]+}}@main 2004 // CHECK2-SAME: () #[[ATTR4:[0-9]+]] personality ptr @__gxx_personality_v0 { 2005 // CHECK2-NEXT: entry: 2006 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2007 // CHECK2-NEXT: [[RES:%.*]] = alloca i32, align 4 2008 // CHECK2-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 2009 // CHECK2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 2010 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 2011 // CHECK2-NEXT: store i32 0, ptr [[RETVAL]], align 4 2012 // CHECK2-NEXT: [[TMP1:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8 2013 // CHECK2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP1]], 0 2014 // CHECK2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]] 2015 // CHECK2: init.check: 2016 // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]] 2017 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 2018 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] 2019 // CHECK2: init: 2020 // CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 2021 // CHECK2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZZ4mainE2sm, ptr @.__kmpc_global_ctor_..6, ptr null, ptr @.__kmpc_global_dtor_..7) 2022 // CHECK2-NEXT: [[TMP4:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.) 2023 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP4]], i32 0, i32 0 2024 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 2025 // CHECK2-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP5]]) 2026 // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] 2027 // CHECK2: invoke.cont: 2028 // CHECK2-NEXT: [[TMP6:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]] 2029 // CHECK2-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]] 2030 // CHECK2-NEXT: br label [[INIT_END]] 2031 // CHECK2: init.end: 2032 // CHECK2-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.) 2033 // CHECK2-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP7]], i32 0, i32 0 2034 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4 2035 // CHECK2-NEXT: store i32 [[TMP8]], ptr [[RES]], align 4 2036 // CHECK2-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZZ4mainE2sm, i64 24, ptr @_ZZ4mainE2sm.cache.) 2037 // CHECK2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[TMP9]], i32 0, i32 0 2038 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[A2]], align 8 2039 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4 2040 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP10]] 2041 // CHECK2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4 2042 // CHECK2-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.) 2043 // CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP12]], i32 0, i32 0 2044 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[A3]], align 4 2045 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4 2046 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 2047 // CHECK2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 2048 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZL3gs2, align 8 2049 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4 2050 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 2051 // CHECK2-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4 2052 // CHECK2-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.) 2053 // CHECK2-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP17]], i32 0, i32 0 2054 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[A6]], align 4 2055 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4 2056 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]] 2057 // CHECK2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4 2058 // CHECK2-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.) 2059 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], i64 0, i64 1 2060 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 2061 // CHECK2-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0 2062 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[A9]], align 4 2063 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4 2064 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP21]] 2065 // CHECK2-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4 2066 // CHECK2-NEXT: [[TMP23:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.) 2067 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4 2068 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4 2069 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP25]], [[TMP24]] 2070 // CHECK2-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4 2071 // CHECK2-NEXT: [[TMP26:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.) 2072 // CHECK2-NEXT: [[TMP27:%.*]] = load float, ptr [[TMP26]], align 4 2073 // CHECK2-NEXT: [[CONV:%.*]] = fptosi float [[TMP27]] to i32 2074 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4 2075 // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[CONV]] 2076 // CHECK2-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4 2077 // CHECK2-NEXT: [[TMP29:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.) 2078 // CHECK2-NEXT: [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP29]], i32 0, i32 0 2079 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[A13]], align 4 2080 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[RES]], align 4 2081 // CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP31]], [[TMP30]] 2082 // CHECK2-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4 2083 // CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[RES]], align 4 2084 // CHECK2-NEXT: ret i32 [[TMP32]] 2085 // CHECK2: lpad: 2086 // CHECK2-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 } 2087 // CHECK2-NEXT: cleanup 2088 // CHECK2-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0 2089 // CHECK2-NEXT: store ptr [[TMP34]], ptr [[EXN_SLOT]], align 8 2090 // CHECK2-NEXT: [[TMP35:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 1 2091 // CHECK2-NEXT: store i32 [[TMP35]], ptr [[EHSELECTOR_SLOT]], align 4 2092 // CHECK2-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]] 2093 // CHECK2-NEXT: br label [[EH_RESUME:%.*]] 2094 // CHECK2: eh.resume: 2095 // CHECK2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 2096 // CHECK2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 2097 // CHECK2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 2098 // CHECK2-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 2099 // CHECK2-NEXT: resume { ptr, i32 } [[LPAD_VAL15]] 2100 // 2101 // 2102 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..6 2103 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2104 // CHECK2-NEXT: entry: 2105 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2106 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 2107 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2108 // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 2109 // CHECK2-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.) 2110 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0 2111 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4 2112 // CHECK2-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) [[TMP2]], i32 noundef [[TMP4]]) 2113 // CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8 2114 // CHECK2-NEXT: ret ptr [[TMP5]] 2115 // 2116 // 2117 // CHECK2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei 2118 // CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2119 // CHECK2-NEXT: entry: 2120 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2121 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2122 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2123 // CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2124 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2125 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2126 // CHECK2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]) 2127 // CHECK2-NEXT: ret void 2128 // 2129 // 2130 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..7 2131 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2132 // CHECK2-NEXT: entry: 2133 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2134 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2135 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 2136 // CHECK2-NEXT: call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[TMP1]]) #[[ATTR3]] 2137 // CHECK2-NEXT: ret void 2138 // 2139 // 2140 // CHECK2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev 2141 // CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 2142 // CHECK2-NEXT: entry: 2143 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2144 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2145 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2146 // CHECK2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] 2147 // CHECK2-NEXT: ret void 2148 // 2149 // 2150 // CHECK2-LABEL: define {{[^@]+}}@_Z6foobarv 2151 // CHECK2-SAME: () #[[ATTR2]] { 2152 // CHECK2-NEXT: entry: 2153 // CHECK2-NEXT: [[RES:%.*]] = alloca i32, align 4 2154 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 2155 // CHECK2-NEXT: [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.) 2156 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP1]], i32 0, i32 0 2157 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 2158 // CHECK2-NEXT: store i32 [[TMP2]], ptr [[RES]], align 4 2159 // CHECK2-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.) 2160 // CHECK2-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0 2161 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[A1]], align 4 2162 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[RES]], align 4 2163 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 2164 // CHECK2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4 2165 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr @_ZL3gs2, align 8 2166 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[RES]], align 4 2167 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] 2168 // CHECK2-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4 2169 // CHECK2-NEXT: [[TMP8:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.) 2170 // CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP8]], i32 0, i32 0 2171 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[A3]], align 4 2172 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4 2173 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 2174 // CHECK2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 2175 // CHECK2-NEXT: [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.) 2176 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], i64 0, i64 1 2177 // CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 2178 // CHECK2-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0 2179 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[A6]], align 4 2180 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4 2181 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP13]], [[TMP12]] 2182 // CHECK2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4 2183 // CHECK2-NEXT: [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.) 2184 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 2185 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4 2186 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 2187 // CHECK2-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4 2188 // CHECK2-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.) 2189 // CHECK2-NEXT: [[TMP18:%.*]] = load float, ptr [[TMP17]], align 4 2190 // CHECK2-NEXT: [[CONV:%.*]] = fptosi float [[TMP18]] to i32 2191 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4 2192 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], [[CONV]] 2193 // CHECK2-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4 2194 // CHECK2-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.) 2195 // CHECK2-NEXT: [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP20]], i32 0, i32 0 2196 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[A10]], align 4 2197 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4 2198 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]] 2199 // CHECK2-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4 2200 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[RES]], align 4 2201 // CHECK2-NEXT: ret i32 [[TMP23]] 2202 // 2203 // 2204 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.8 2205 // CHECK2-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) { 2206 // CHECK2-NEXT: entry: 2207 // CHECK2-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8 2208 // CHECK2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 2209 // CHECK2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]] 2210 // CHECK2: init.check: 2211 // CHECK2-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8 2212 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 2213 // CHECK2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZN2STI2S4E2stE, ptr @.__kmpc_global_ctor_..9, ptr null, ptr @.__kmpc_global_dtor_..10) 2214 // CHECK2-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23) 2215 // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]] 2216 // CHECK2-NEXT: br label [[INIT_END]] 2217 // CHECK2: init.end: 2218 // CHECK2-NEXT: ret void 2219 // 2220 // 2221 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..9 2222 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2223 // CHECK2-NEXT: entry: 2224 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2225 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2226 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 2227 // CHECK2-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]], i32 noundef 23) 2228 // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 2229 // CHECK2-NEXT: ret ptr [[TMP2]] 2230 // 2231 // 2232 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S4C1Ei 2233 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2234 // CHECK2-NEXT: entry: 2235 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2236 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2237 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2238 // CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2239 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2240 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2241 // CHECK2-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]) 2242 // CHECK2-NEXT: ret void 2243 // 2244 // 2245 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..10 2246 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2247 // CHECK2-NEXT: entry: 2248 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2249 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2250 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 2251 // CHECK2-NEXT: call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]]) #[[ATTR3]] 2252 // CHECK2-NEXT: ret void 2253 // 2254 // 2255 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S4D1Ev 2256 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 2257 // CHECK2-NEXT: entry: 2258 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2259 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2260 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2261 // CHECK2-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] 2262 // CHECK2-NEXT: ret void 2263 // 2264 // 2265 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S1C2Ei 2266 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 2267 // CHECK2-NEXT: entry: 2268 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2269 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2270 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2271 // CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2272 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2273 // CHECK2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 2274 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2275 // CHECK2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4 2276 // CHECK2-NEXT: ret void 2277 // 2278 // 2279 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S1D2Ev 2280 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 2281 // CHECK2-NEXT: entry: 2282 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2283 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2284 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2285 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 2286 // CHECK2-NEXT: store i32 0, ptr [[A]], align 4 2287 // CHECK2-NEXT: ret void 2288 // 2289 // 2290 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S2C2Ei 2291 // CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 2292 // CHECK2-NEXT: entry: 2293 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2294 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2295 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2296 // CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2297 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2298 // CHECK2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0 2299 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2300 // CHECK2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8 2301 // CHECK2-NEXT: ret void 2302 // 2303 // 2304 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S2D2Ev 2305 // CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 2306 // CHECK2-NEXT: entry: 2307 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2308 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2309 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2310 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0 2311 // CHECK2-NEXT: store i32 0, ptr [[A]], align 8 2312 // CHECK2-NEXT: ret void 2313 // 2314 // 2315 // CHECK2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei 2316 // CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 2317 // CHECK2-NEXT: entry: 2318 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2319 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2320 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2321 // CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2322 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2323 // CHECK2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0 2324 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2325 // CHECK2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8 2326 // CHECK2-NEXT: ret void 2327 // 2328 // 2329 // CHECK2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev 2330 // CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 2331 // CHECK2-NEXT: entry: 2332 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2333 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2334 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2335 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0 2336 // CHECK2-NEXT: store i32 0, ptr [[A]], align 8 2337 // CHECK2-NEXT: ret void 2338 // 2339 // 2340 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S4C2Ei 2341 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 2342 // CHECK2-NEXT: entry: 2343 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2344 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2345 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2346 // CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2347 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2348 // CHECK2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0 2349 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2350 // CHECK2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4 2351 // CHECK2-NEXT: ret void 2352 // 2353 // 2354 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S4D2Ev 2355 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 2356 // CHECK2-NEXT: entry: 2357 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2358 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2359 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2360 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0 2361 // CHECK2-NEXT: store i32 0, ptr [[A]], align 4 2362 // CHECK2-NEXT: ret void 2363 // 2364 // 2365 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp 2366 // CHECK2-SAME: () #[[ATTR0]] { 2367 // CHECK2-NEXT: entry: 2368 // CHECK2-NEXT: call void @__cxx_global_var_init() 2369 // CHECK2-NEXT: call void @.__omp_threadprivate_init_.() 2370 // CHECK2-NEXT: call void @__cxx_global_var_init.1() 2371 // CHECK2-NEXT: call void @__cxx_global_var_init.2() 2372 // CHECK2-NEXT: call void @.__omp_threadprivate_init_..5() 2373 // CHECK2-NEXT: ret void 2374 // 2375 // 2376 // SIMD1-LABEL: define {{[^@]+}}@__cxx_global_var_init 2377 // SIMD1-SAME: () #[[ATTR0:[0-9]+]] { 2378 // SIMD1-NEXT: entry: 2379 // SIMD1-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5) 2380 // SIMD1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]] 2381 // SIMD1-NEXT: ret void 2382 // 2383 // 2384 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S1C1Ei 2385 // SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2386 // SIMD1-NEXT: entry: 2387 // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2388 // SIMD1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2389 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2390 // SIMD1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2391 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2392 // SIMD1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2393 // SIMD1-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 2394 // SIMD1-NEXT: ret void 2395 // 2396 // 2397 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S1D1Ev 2398 // SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { 2399 // SIMD1-NEXT: entry: 2400 // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2401 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2402 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2403 // SIMD1-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] 2404 // SIMD1-NEXT: ret void 2405 // 2406 // 2407 // SIMD1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2408 // SIMD1-SAME: () #[[ATTR0]] { 2409 // SIMD1-NEXT: entry: 2410 // SIMD1-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27) 2411 // SIMD1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]] 2412 // SIMD1-NEXT: ret void 2413 // 2414 // 2415 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S2C1Ei 2416 // SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2417 // SIMD1-NEXT: entry: 2418 // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2419 // SIMD1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2420 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2421 // SIMD1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2422 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2423 // SIMD1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2424 // SIMD1-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]) 2425 // SIMD1-NEXT: ret void 2426 // 2427 // 2428 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S2D1Ev 2429 // SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 2430 // SIMD1-NEXT: entry: 2431 // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2432 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2433 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2434 // SIMD1-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]] 2435 // SIMD1-NEXT: ret void 2436 // 2437 // 2438 // SIMD1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2439 // SIMD1-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 { 2440 // SIMD1-NEXT: entry: 2441 // SIMD1-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 2442 // SIMD1-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 2443 // SIMD1-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 2444 // SIMD1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 2445 // SIMD1-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 2446 // SIMD1-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8 2447 // SIMD1-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8 2448 // SIMD1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) 2449 // SIMD1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] 2450 // SIMD1: invoke.cont: 2451 // SIMD1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8 2452 // SIMD1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) 2453 // SIMD1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]] 2454 // SIMD1: invoke.cont2: 2455 // SIMD1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8 2456 // SIMD1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) 2457 // SIMD1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] 2458 // SIMD1: invoke.cont3: 2459 // SIMD1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8 2460 // SIMD1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 2461 // SIMD1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) 2462 // SIMD1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]] 2463 // SIMD1: invoke.cont7: 2464 // SIMD1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 2465 // SIMD1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) 2466 // SIMD1-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]] 2467 // SIMD1: invoke.cont8: 2468 // SIMD1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 2469 // SIMD1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) 2470 // SIMD1-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]] 2471 // SIMD1: invoke.cont9: 2472 // SIMD1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]] 2473 // SIMD1-NEXT: ret void 2474 // SIMD1: lpad: 2475 // SIMD1-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } 2476 // SIMD1-NEXT: cleanup 2477 // SIMD1-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0 2478 // SIMD1-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8 2479 // SIMD1-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1 2480 // SIMD1-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4 2481 // SIMD1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8 2482 // SIMD1-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]] 2483 // SIMD1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]] 2484 // SIMD1: arraydestroy.body: 2485 // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2486 // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2487 // SIMD1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 2488 // SIMD1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x 2489 // SIMD1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]] 2490 // SIMD1: arraydestroy.done4: 2491 // SIMD1-NEXT: br label [[EHCLEANUP:%.*]] 2492 // SIMD1: lpad6: 2493 // SIMD1-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } 2494 // SIMD1-NEXT: cleanup 2495 // SIMD1-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0 2496 // SIMD1-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8 2497 // SIMD1-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1 2498 // SIMD1-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4 2499 // SIMD1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8 2500 // SIMD1-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]] 2501 // SIMD1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]] 2502 // SIMD1: arraydestroy.body11: 2503 // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ] 2504 // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1 2505 // SIMD1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] 2506 // SIMD1-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1) 2507 // SIMD1-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]] 2508 // SIMD1: arraydestroy.done15: 2509 // SIMD1-NEXT: br label [[EHCLEANUP]] 2510 // SIMD1: ehcleanup: 2511 // SIMD1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8 2512 // SIMD1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0 2513 // SIMD1-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]] 2514 // SIMD1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]] 2515 // SIMD1: arraydestroy.body17: 2516 // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] 2517 // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 2518 // SIMD1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] 2519 // SIMD1-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x 2520 // SIMD1-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] 2521 // SIMD1: arraydestroy.done21: 2522 // SIMD1-NEXT: br label [[EH_RESUME:%.*]] 2523 // SIMD1: eh.resume: 2524 // SIMD1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 2525 // SIMD1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 2526 // SIMD1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 2527 // SIMD1-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 2528 // SIMD1-NEXT: resume { ptr, i32 } [[LPAD_VAL22]] 2529 // 2530 // 2531 // SIMD1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2532 // SIMD1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2533 // SIMD1-NEXT: entry: 2534 // SIMD1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2535 // SIMD1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2536 // SIMD1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2537 // SIMD1: arraydestroy.body: 2538 // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2539 // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2540 // SIMD1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 2541 // SIMD1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x 2542 // SIMD1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2543 // SIMD1: arraydestroy.done1: 2544 // SIMD1-NEXT: ret void 2545 // 2546 // 2547 // SIMD1-LABEL: define {{[^@]+}}@main 2548 // SIMD1-SAME: () #[[ATTR4:[0-9]+]] personality ptr @__gxx_personality_v0 { 2549 // SIMD1-NEXT: entry: 2550 // SIMD1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2551 // SIMD1-NEXT: [[RES:%.*]] = alloca i32, align 4 2552 // SIMD1-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 2553 // SIMD1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 2554 // SIMD1-NEXT: store i32 0, ptr [[RETVAL]], align 4 2555 // SIMD1-NEXT: [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8 2556 // SIMD1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 2557 // SIMD1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] 2558 // SIMD1: init.check: 2559 // SIMD1-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]] 2560 // SIMD1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 2561 // SIMD1-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] 2562 // SIMD1: init: 2563 // SIMD1-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZL3gs1, align 4 2564 // SIMD1-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]]) 2565 // SIMD1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] 2566 // SIMD1: invoke.cont: 2567 // SIMD1-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]] 2568 // SIMD1-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]] 2569 // SIMD1-NEXT: br label [[INIT_END]] 2570 // SIMD1: init.end: 2571 // SIMD1-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZN6Static1sE, align 4 2572 // SIMD1-NEXT: store i32 [[TMP4]], ptr [[RES]], align 4 2573 // SIMD1-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE2sm, align 8 2574 // SIMD1-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4 2575 // SIMD1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 2576 // SIMD1-NEXT: store i32 [[ADD]], ptr [[RES]], align 4 2577 // SIMD1-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZL3gs1, align 4 2578 // SIMD1-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4 2579 // SIMD1-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] 2580 // SIMD1-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4 2581 // SIMD1-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZL3gs2, align 8 2582 // SIMD1-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4 2583 // SIMD1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 2584 // SIMD1-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4 2585 // SIMD1-NEXT: [[TMP11:%.*]] = load i32, ptr @gs3, align 4 2586 // SIMD1-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4 2587 // SIMD1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 2588 // SIMD1-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4 2589 // SIMD1-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4 2590 // SIMD1-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4 2591 // SIMD1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 2592 // SIMD1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 2593 // SIMD1-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4 2594 // SIMD1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4 2595 // SIMD1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 2596 // SIMD1-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4 2597 // SIMD1-NEXT: [[TMP17:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4 2598 // SIMD1-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32 2599 // SIMD1-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4 2600 // SIMD1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]] 2601 // SIMD1-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4 2602 // SIMD1-NEXT: [[TMP19:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4 2603 // SIMD1-NEXT: [[TMP20:%.*]] = load i32, ptr [[RES]], align 4 2604 // SIMD1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]] 2605 // SIMD1-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4 2606 // SIMD1-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4 2607 // SIMD1-NEXT: ret i32 [[TMP21]] 2608 // SIMD1: lpad: 2609 // SIMD1-NEXT: [[TMP22:%.*]] = landingpad { ptr, i32 } 2610 // SIMD1-NEXT: cleanup 2611 // SIMD1-NEXT: [[TMP23:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 0 2612 // SIMD1-NEXT: store ptr [[TMP23]], ptr [[EXN_SLOT]], align 8 2613 // SIMD1-NEXT: [[TMP24:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 1 2614 // SIMD1-NEXT: store i32 [[TMP24]], ptr [[EHSELECTOR_SLOT]], align 4 2615 // SIMD1-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]] 2616 // SIMD1-NEXT: br label [[EH_RESUME:%.*]] 2617 // SIMD1: eh.resume: 2618 // SIMD1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 2619 // SIMD1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 2620 // SIMD1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 2621 // SIMD1-NEXT: [[LPAD_VAL8:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 2622 // SIMD1-NEXT: resume { ptr, i32 } [[LPAD_VAL8]] 2623 // 2624 // 2625 // SIMD1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei 2626 // SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2627 // SIMD1-NEXT: entry: 2628 // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2629 // SIMD1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2630 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2631 // SIMD1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2632 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2633 // SIMD1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2634 // SIMD1-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]) 2635 // SIMD1-NEXT: ret void 2636 // 2637 // 2638 // SIMD1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev 2639 // SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 2640 // SIMD1-NEXT: entry: 2641 // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2642 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2643 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2644 // SIMD1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] 2645 // SIMD1-NEXT: ret void 2646 // 2647 // 2648 // SIMD1-LABEL: define {{[^@]+}}@_Z6foobarv 2649 // SIMD1-SAME: () #[[ATTR2]] { 2650 // SIMD1-NEXT: entry: 2651 // SIMD1-NEXT: [[RES:%.*]] = alloca i32, align 4 2652 // SIMD1-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZN6Static1sE, align 4 2653 // SIMD1-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4 2654 // SIMD1-NEXT: [[TMP1:%.*]] = load i32, ptr @_ZL3gs1, align 4 2655 // SIMD1-NEXT: [[TMP2:%.*]] = load i32, ptr [[RES]], align 4 2656 // SIMD1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] 2657 // SIMD1-NEXT: store i32 [[ADD]], ptr [[RES]], align 4 2658 // SIMD1-NEXT: [[TMP3:%.*]] = load i32, ptr @_ZL3gs2, align 8 2659 // SIMD1-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4 2660 // SIMD1-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]] 2661 // SIMD1-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4 2662 // SIMD1-NEXT: [[TMP5:%.*]] = load i32, ptr @gs3, align 4 2663 // SIMD1-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4 2664 // SIMD1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 2665 // SIMD1-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4 2666 // SIMD1-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4 2667 // SIMD1-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4 2668 // SIMD1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] 2669 // SIMD1-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4 2670 // SIMD1-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4 2671 // SIMD1-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4 2672 // SIMD1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 2673 // SIMD1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 2674 // SIMD1-NEXT: [[TMP11:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4 2675 // SIMD1-NEXT: [[CONV:%.*]] = fptosi float [[TMP11]] to i32 2676 // SIMD1-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4 2677 // SIMD1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]] 2678 // SIMD1-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4 2679 // SIMD1-NEXT: [[TMP13:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4 2680 // SIMD1-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4 2681 // SIMD1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 2682 // SIMD1-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4 2683 // SIMD1-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4 2684 // SIMD1-NEXT: ret i32 [[TMP15]] 2685 // 2686 // 2687 // SIMD1-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 2688 // SIMD1-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) { 2689 // SIMD1-NEXT: entry: 2690 // SIMD1-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8 2691 // SIMD1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 2692 // SIMD1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]] 2693 // SIMD1: init.check: 2694 // SIMD1-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8 2695 // SIMD1-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23) 2696 // SIMD1-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]] 2697 // SIMD1-NEXT: br label [[INIT_END]] 2698 // SIMD1: init.end: 2699 // SIMD1-NEXT: ret void 2700 // 2701 // 2702 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S4C1Ei 2703 // SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2704 // SIMD1-NEXT: entry: 2705 // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2706 // SIMD1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2707 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2708 // SIMD1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2709 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2710 // SIMD1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2711 // SIMD1-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]) 2712 // SIMD1-NEXT: ret void 2713 // 2714 // 2715 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S4D1Ev 2716 // SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 2717 // SIMD1-NEXT: entry: 2718 // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2719 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2720 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2721 // SIMD1-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] 2722 // SIMD1-NEXT: ret void 2723 // 2724 // 2725 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S1C2Ei 2726 // SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 2727 // SIMD1-NEXT: entry: 2728 // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2729 // SIMD1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2730 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2731 // SIMD1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2732 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2733 // SIMD1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 2734 // SIMD1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2735 // SIMD1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4 2736 // SIMD1-NEXT: ret void 2737 // 2738 // 2739 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S1D2Ev 2740 // SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 2741 // SIMD1-NEXT: entry: 2742 // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2743 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2744 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2745 // SIMD1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 2746 // SIMD1-NEXT: store i32 0, ptr [[A]], align 4 2747 // SIMD1-NEXT: ret void 2748 // 2749 // 2750 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S2C2Ei 2751 // SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 2752 // SIMD1-NEXT: entry: 2753 // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2754 // SIMD1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2755 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2756 // SIMD1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2757 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2758 // SIMD1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0 2759 // SIMD1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2760 // SIMD1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8 2761 // SIMD1-NEXT: ret void 2762 // 2763 // 2764 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S2D2Ev 2765 // SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 2766 // SIMD1-NEXT: entry: 2767 // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2768 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2769 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2770 // SIMD1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0 2771 // SIMD1-NEXT: store i32 0, ptr [[A]], align 8 2772 // SIMD1-NEXT: ret void 2773 // 2774 // 2775 // SIMD1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei 2776 // SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 2777 // SIMD1-NEXT: entry: 2778 // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2779 // SIMD1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2780 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2781 // SIMD1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2782 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2783 // SIMD1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0 2784 // SIMD1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2785 // SIMD1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8 2786 // SIMD1-NEXT: ret void 2787 // 2788 // 2789 // SIMD1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev 2790 // SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 2791 // SIMD1-NEXT: entry: 2792 // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2793 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2794 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2795 // SIMD1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0 2796 // SIMD1-NEXT: store i32 0, ptr [[A]], align 8 2797 // SIMD1-NEXT: ret void 2798 // 2799 // 2800 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S4C2Ei 2801 // SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 2802 // SIMD1-NEXT: entry: 2803 // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2804 // SIMD1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2805 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2806 // SIMD1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2807 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2808 // SIMD1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0 2809 // SIMD1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2810 // SIMD1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4 2811 // SIMD1-NEXT: ret void 2812 // 2813 // 2814 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S4D2Ev 2815 // SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 2816 // SIMD1-NEXT: entry: 2817 // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2818 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2819 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2820 // SIMD1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0 2821 // SIMD1-NEXT: store i32 0, ptr [[A]], align 4 2822 // SIMD1-NEXT: ret void 2823 // 2824 // 2825 // SIMD1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp 2826 // SIMD1-SAME: () #[[ATTR0]] { 2827 // SIMD1-NEXT: entry: 2828 // SIMD1-NEXT: call void @__cxx_global_var_init() 2829 // SIMD1-NEXT: call void @__cxx_global_var_init.1() 2830 // SIMD1-NEXT: call void @__cxx_global_var_init.2() 2831 // SIMD1-NEXT: ret void 2832 // 2833 // 2834 // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_var_init 2835 // SIMD2-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG115:![0-9]+]] { 2836 // SIMD2-NEXT: entry: 2837 // SIMD2-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG118:![0-9]+]] 2838 // SIMD2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG120:![0-9]+]] 2839 // SIMD2-NEXT: ret void, !dbg [[DBG121:![0-9]+]] 2840 // 2841 // 2842 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S1C1Ei 2843 // SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG122:![0-9]+]] { 2844 // SIMD2-NEXT: entry: 2845 // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2846 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2847 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2848 // SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META123:![0-9]+]], !DIExpression(), [[META125:![0-9]+]]) 2849 // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2850 // SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META126:![0-9]+]], !DIExpression(), [[META127:![0-9]+]]) 2851 // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2852 // SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG128:![0-9]+]] 2853 // SIMD2-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG128]] 2854 // SIMD2-NEXT: ret void, !dbg [[DBG129:![0-9]+]] 2855 // 2856 // 2857 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S1D1Ev 2858 // SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG130:![0-9]+]] { 2859 // SIMD2-NEXT: entry: 2860 // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2861 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2862 // SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META131:![0-9]+]], !DIExpression(), [[META132:![0-9]+]]) 2863 // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2864 // SIMD2-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG133:![0-9]+]] 2865 // SIMD2-NEXT: ret void, !dbg [[DBG134:![0-9]+]] 2866 // 2867 // 2868 // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2869 // SIMD2-SAME: () #[[ATTR0]] !dbg [[DBG135:![0-9]+]] { 2870 // SIMD2-NEXT: entry: 2871 // SIMD2-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG136:![0-9]+]] 2872 // SIMD2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG138:![0-9]+]] 2873 // SIMD2-NEXT: ret void, !dbg [[DBG139:![0-9]+]] 2874 // 2875 // 2876 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2C1Ei 2877 // SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG140:![0-9]+]] { 2878 // SIMD2-NEXT: entry: 2879 // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2880 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2881 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2882 // SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META141:![0-9]+]], !DIExpression(), [[META143:![0-9]+]]) 2883 // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2884 // SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META144:![0-9]+]], !DIExpression(), [[META145:![0-9]+]]) 2885 // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2886 // SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG146:![0-9]+]] 2887 // SIMD2-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG146]] 2888 // SIMD2-NEXT: ret void, !dbg [[DBG147:![0-9]+]] 2889 // 2890 // 2891 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2D1Ev 2892 // SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG148:![0-9]+]] { 2893 // SIMD2-NEXT: entry: 2894 // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2895 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2896 // SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META149:![0-9]+]], !DIExpression(), [[META150:![0-9]+]]) 2897 // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2898 // SIMD2-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG151:![0-9]+]] 2899 // SIMD2-NEXT: ret void, !dbg [[DBG152:![0-9]+]] 2900 // 2901 // 2902 // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2903 // SIMD2-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG153:![0-9]+]] { 2904 // SIMD2-NEXT: entry: 2905 // SIMD2-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 2906 // SIMD2-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 2907 // SIMD2-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 2908 // SIMD2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 2909 // SIMD2-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 2910 // SIMD2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154:![0-9]+]] 2911 // SIMD2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156:![0-9]+]] 2912 // SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) 2913 // SIMD2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG157:![0-9]+]] 2914 // SIMD2: invoke.cont: 2915 // SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] 2916 // SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) 2917 // SIMD2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG158:![0-9]+]] 2918 // SIMD2: invoke.cont2: 2919 // SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] 2920 // SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) 2921 // SIMD2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG159:![0-9]+]] 2922 // SIMD2: invoke.cont3: 2923 // SIMD2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154]] 2924 // SIMD2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160:![0-9]+]] 2925 // SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) 2926 // SIMD2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG161:![0-9]+]] 2927 // SIMD2: invoke.cont7: 2928 // SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] 2929 // SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) 2930 // SIMD2-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG162:![0-9]+]] 2931 // SIMD2: invoke.cont8: 2932 // SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] 2933 // SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) 2934 // SIMD2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG163:![0-9]+]] 2935 // SIMD2: invoke.cont9: 2936 // SIMD2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG164:![0-9]+]] 2937 // SIMD2-NEXT: ret void, !dbg [[DBG164]] 2938 // SIMD2: lpad: 2939 // SIMD2-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } 2940 // SIMD2-NEXT: cleanup, !dbg [[DBG165:![0-9]+]] 2941 // SIMD2-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG165]] 2942 // SIMD2-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG165]] 2943 // SIMD2-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG165]] 2944 // SIMD2-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG165]] 2945 // SIMD2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] 2946 // SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG156]] 2947 // SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG156]] 2948 // SIMD2: arraydestroy.body: 2949 // SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG156]] 2950 // SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG156]] 2951 // SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG156]] 2952 // SIMD2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG156]] 2953 // SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG156]] 2954 // SIMD2: arraydestroy.done4: 2955 // SIMD2-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG156]] 2956 // SIMD2: lpad6: 2957 // SIMD2-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } 2958 // SIMD2-NEXT: cleanup, !dbg [[DBG165]] 2959 // SIMD2-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG165]] 2960 // SIMD2-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG165]] 2961 // SIMD2-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG165]] 2962 // SIMD2-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG165]] 2963 // SIMD2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] 2964 // SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG160]] 2965 // SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG160]] 2966 // SIMD2: arraydestroy.body11: 2967 // SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG160]] 2968 // SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG160]] 2969 // SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG160]] 2970 // SIMD2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG160]] 2971 // SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG160]] 2972 // SIMD2: arraydestroy.done15: 2973 // SIMD2-NEXT: br label [[EHCLEANUP]], !dbg [[DBG160]] 2974 // SIMD2: ehcleanup: 2975 // SIMD2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154]] 2976 // SIMD2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG154]] 2977 // SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG154]] 2978 // SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG154]] 2979 // SIMD2: arraydestroy.body17: 2980 // SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG154]] 2981 // SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG154]] 2982 // SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG154]] 2983 // SIMD2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG154]] 2984 // SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG154]] 2985 // SIMD2: arraydestroy.done21: 2986 // SIMD2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG154]] 2987 // SIMD2: eh.resume: 2988 // SIMD2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG154]] 2989 // SIMD2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG154]] 2990 // SIMD2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG154]] 2991 // SIMD2-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG154]] 2992 // SIMD2-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG154]] 2993 // 2994 // 2995 // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2996 // SIMD2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG166:![0-9]+]] { 2997 // SIMD2-NEXT: entry: 2998 // SIMD2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2999 // SIMD2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 3000 // SIMD2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META170:![0-9]+]], !DIExpression(), [[META171:![0-9]+]]) 3001 // SIMD2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META171]] 3002 // SIMD2: arraydestroy.body: 3003 // SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META171]] 3004 // SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META171]] 3005 // SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META171]] 3006 // SIMD2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[META171]] 3007 // SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META171]] 3008 // SIMD2: arraydestroy.done1: 3009 // SIMD2-NEXT: ret void, !dbg [[META171]] 3010 // 3011 // 3012 // SIMD2-LABEL: define {{[^@]+}}@main 3013 // SIMD2-SAME: () #[[ATTR4:[0-9]+]] personality ptr @__gxx_personality_v0 !dbg [[DBG52:![0-9]+]] { 3014 // SIMD2-NEXT: entry: 3015 // SIMD2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3016 // SIMD2-NEXT: [[RES:%.*]] = alloca i32, align 4 3017 // SIMD2-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 3018 // SIMD2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 3019 // SIMD2-NEXT: store i32 0, ptr [[RETVAL]], align 4 3020 // SIMD2-NEXT: #dbg_declare(ptr [[RES]], [[META172:![0-9]+]], !DIExpression(), [[META173:![0-9]+]]) 3021 // SIMD2-NEXT: [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG174:![0-9]+]] 3022 // SIMD2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG174]] 3023 // SIMD2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG174]], !prof [[PROF175:![0-9]+]] 3024 // SIMD2: init.check: 3025 // SIMD2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] 3026 // SIMD2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG174]] 3027 // SIMD2-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG174]] 3028 // SIMD2: init: 3029 // SIMD2-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG176:![0-9]+]] 3030 // SIMD2-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]]) 3031 // SIMD2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG177:![0-9]+]] 3032 // SIMD2: invoke.cont: 3033 // SIMD2-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG174]] 3034 // SIMD2-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] 3035 // SIMD2-NEXT: br label [[INIT_END]], !dbg [[DBG174]] 3036 // SIMD2: init.end: 3037 // SIMD2-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG178:![0-9]+]] 3038 // SIMD2-NEXT: store i32 [[TMP4]], ptr [[RES]], align 4, !dbg [[DBG179:![0-9]+]] 3039 // SIMD2-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE2sm, align 8, !dbg [[DBG180:![0-9]+]] 3040 // SIMD2-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG181:![0-9]+]] 3041 // SIMD2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG181]] 3042 // SIMD2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG181]] 3043 // SIMD2-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG182:![0-9]+]] 3044 // SIMD2-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG183:![0-9]+]] 3045 // SIMD2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG183]] 3046 // SIMD2-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG183]] 3047 // SIMD2-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG184:![0-9]+]] 3048 // SIMD2-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG185:![0-9]+]] 3049 // SIMD2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG185]] 3050 // SIMD2-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG185]] 3051 // SIMD2-NEXT: [[TMP11:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG186:![0-9]+]] 3052 // SIMD2-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG187:![0-9]+]] 3053 // SIMD2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG187]] 3054 // SIMD2-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG187]] 3055 // SIMD2-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4, !dbg [[DBG188:![0-9]+]] 3056 // SIMD2-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG189:![0-9]+]] 3057 // SIMD2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG189]] 3058 // SIMD2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG189]] 3059 // SIMD2-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG190:![0-9]+]] 3060 // SIMD2-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG191:![0-9]+]] 3061 // SIMD2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG191]] 3062 // SIMD2-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG191]] 3063 // SIMD2-NEXT: [[TMP17:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG192:![0-9]+]] 3064 // SIMD2-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG192]] 3065 // SIMD2-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG193:![0-9]+]] 3066 // SIMD2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG193]] 3067 // SIMD2-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG193]] 3068 // SIMD2-NEXT: [[TMP19:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG194:![0-9]+]] 3069 // SIMD2-NEXT: [[TMP20:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG195:![0-9]+]] 3070 // SIMD2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]], !dbg [[DBG195]] 3071 // SIMD2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG195]] 3072 // SIMD2-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG196:![0-9]+]] 3073 // SIMD2-NEXT: ret i32 [[TMP21]], !dbg [[DBG197:![0-9]+]] 3074 // SIMD2: lpad: 3075 // SIMD2-NEXT: [[TMP22:%.*]] = landingpad { ptr, i32 } 3076 // SIMD2-NEXT: cleanup, !dbg [[DBG198:![0-9]+]] 3077 // SIMD2-NEXT: [[TMP23:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 0, !dbg [[DBG198]] 3078 // SIMD2-NEXT: store ptr [[TMP23]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG198]] 3079 // SIMD2-NEXT: [[TMP24:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 1, !dbg [[DBG198]] 3080 // SIMD2-NEXT: store i32 [[TMP24]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG198]] 3081 // SIMD2-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] 3082 // SIMD2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG174]] 3083 // SIMD2: eh.resume: 3084 // SIMD2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG174]] 3085 // SIMD2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG174]] 3086 // SIMD2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG174]] 3087 // SIMD2-NEXT: [[LPAD_VAL8:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG174]] 3088 // SIMD2-NEXT: resume { ptr, i32 } [[LPAD_VAL8]], !dbg [[DBG174]] 3089 // 3090 // 3091 // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei 3092 // SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG199:![0-9]+]] { 3093 // SIMD2-NEXT: entry: 3094 // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3095 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3096 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3097 // SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META200:![0-9]+]], !DIExpression(), [[META202:![0-9]+]]) 3098 // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3099 // SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META203:![0-9]+]], !DIExpression(), [[META204:![0-9]+]]) 3100 // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3101 // SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG205:![0-9]+]] 3102 // SIMD2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG205]] 3103 // SIMD2-NEXT: ret void, !dbg [[DBG206:![0-9]+]] 3104 // 3105 // 3106 // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev 3107 // SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG207:![0-9]+]] { 3108 // SIMD2-NEXT: entry: 3109 // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3110 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3111 // SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META208:![0-9]+]], !DIExpression(), [[META209:![0-9]+]]) 3112 // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3113 // SIMD2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG210:![0-9]+]] 3114 // SIMD2-NEXT: ret void, !dbg [[DBG211:![0-9]+]] 3115 // 3116 // 3117 // SIMD2-LABEL: define {{[^@]+}}@_Z6foobarv 3118 // SIMD2-SAME: () #[[ATTR2]] !dbg [[DBG212:![0-9]+]] { 3119 // SIMD2-NEXT: entry: 3120 // SIMD2-NEXT: [[RES:%.*]] = alloca i32, align 4 3121 // SIMD2-NEXT: #dbg_declare(ptr [[RES]], [[META213:![0-9]+]], !DIExpression(), [[META214:![0-9]+]]) 3122 // SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG215:![0-9]+]] 3123 // SIMD2-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4, !dbg [[DBG216:![0-9]+]] 3124 // SIMD2-NEXT: [[TMP1:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG217:![0-9]+]] 3125 // SIMD2-NEXT: [[TMP2:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG218:![0-9]+]] 3126 // SIMD2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]], !dbg [[DBG218]] 3127 // SIMD2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG218]] 3128 // SIMD2-NEXT: [[TMP3:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG219:![0-9]+]] 3129 // SIMD2-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG220:![0-9]+]] 3130 // SIMD2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG220]] 3131 // SIMD2-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG220]] 3132 // SIMD2-NEXT: [[TMP5:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG221:![0-9]+]] 3133 // SIMD2-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG222:![0-9]+]] 3134 // SIMD2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG222]] 3135 // SIMD2-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG222]] 3136 // SIMD2-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4, !dbg [[DBG223:![0-9]+]] 3137 // SIMD2-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG224:![0-9]+]] 3138 // SIMD2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG224]] 3139 // SIMD2-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG224]] 3140 // SIMD2-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG225:![0-9]+]] 3141 // SIMD2-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG226:![0-9]+]] 3142 // SIMD2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG226]] 3143 // SIMD2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG226]] 3144 // SIMD2-NEXT: [[TMP11:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG227:![0-9]+]] 3145 // SIMD2-NEXT: [[CONV:%.*]] = fptosi float [[TMP11]] to i32, !dbg [[DBG227]] 3146 // SIMD2-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG228:![0-9]+]] 3147 // SIMD2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]], !dbg [[DBG228]] 3148 // SIMD2-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG228]] 3149 // SIMD2-NEXT: [[TMP13:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG229:![0-9]+]] 3150 // SIMD2-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG230:![0-9]+]] 3151 // SIMD2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG230]] 3152 // SIMD2-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG230]] 3153 // SIMD2-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]] 3154 // SIMD2-NEXT: ret i32 [[TMP15]], !dbg [[DBG232:![0-9]+]] 3155 // 3156 // 3157 // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 3158 // SIMD2-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG233:![0-9]+]] { 3159 // SIMD2-NEXT: entry: 3160 // SIMD2-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG234:![0-9]+]] 3161 // SIMD2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG234]] 3162 // SIMD2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG234]] 3163 // SIMD2: init.check: 3164 // SIMD2-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG234]] 3165 // SIMD2-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG235:![0-9]+]] 3166 // SIMD2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG234]] 3167 // SIMD2-NEXT: br label [[INIT_END]], !dbg [[DBG234]] 3168 // SIMD2: init.end: 3169 // SIMD2-NEXT: ret void, !dbg [[DBG237:![0-9]+]] 3170 // 3171 // 3172 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4C1Ei 3173 // SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG238:![0-9]+]] { 3174 // SIMD2-NEXT: entry: 3175 // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3176 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3177 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3178 // SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META239:![0-9]+]], !DIExpression(), [[META241:![0-9]+]]) 3179 // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3180 // SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META242:![0-9]+]], !DIExpression(), [[META243:![0-9]+]]) 3181 // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3182 // SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG244:![0-9]+]] 3183 // SIMD2-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG244]] 3184 // SIMD2-NEXT: ret void, !dbg [[DBG245:![0-9]+]] 3185 // 3186 // 3187 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4D1Ev 3188 // SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG246:![0-9]+]] { 3189 // SIMD2-NEXT: entry: 3190 // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3191 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3192 // SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META247:![0-9]+]], !DIExpression(), [[META248:![0-9]+]]) 3193 // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3194 // SIMD2-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG249:![0-9]+]] 3195 // SIMD2-NEXT: ret void, !dbg [[DBG250:![0-9]+]] 3196 // 3197 // 3198 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S1C2Ei 3199 // SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG251:![0-9]+]] { 3200 // SIMD2-NEXT: entry: 3201 // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3202 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3203 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3204 // SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META252:![0-9]+]], !DIExpression(), [[META253:![0-9]+]]) 3205 // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3206 // SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META254:![0-9]+]], !DIExpression(), [[META255:![0-9]+]]) 3207 // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3208 // SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG256:![0-9]+]] 3209 // SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG257:![0-9]+]] 3210 // SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG256]] 3211 // SIMD2-NEXT: ret void, !dbg [[DBG258:![0-9]+]] 3212 // 3213 // 3214 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S1D2Ev 3215 // SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG259:![0-9]+]] { 3216 // SIMD2-NEXT: entry: 3217 // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3218 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3219 // SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META260:![0-9]+]], !DIExpression(), [[META261:![0-9]+]]) 3220 // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3221 // SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG262:![0-9]+]] 3222 // SIMD2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG264:![0-9]+]] 3223 // SIMD2-NEXT: ret void, !dbg [[DBG265:![0-9]+]] 3224 // 3225 // 3226 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2C2Ei 3227 // SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG266:![0-9]+]] { 3228 // SIMD2-NEXT: entry: 3229 // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3230 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3231 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3232 // SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META267:![0-9]+]], !DIExpression(), [[META268:![0-9]+]]) 3233 // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3234 // SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META269:![0-9]+]], !DIExpression(), [[META270:![0-9]+]]) 3235 // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3236 // SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG271:![0-9]+]] 3237 // SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG272:![0-9]+]] 3238 // SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG271]] 3239 // SIMD2-NEXT: ret void, !dbg [[DBG273:![0-9]+]] 3240 // 3241 // 3242 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2D2Ev 3243 // SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG274:![0-9]+]] { 3244 // SIMD2-NEXT: entry: 3245 // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3246 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3247 // SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META275:![0-9]+]], !DIExpression(), [[META276:![0-9]+]]) 3248 // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3249 // SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG277:![0-9]+]] 3250 // SIMD2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG279:![0-9]+]] 3251 // SIMD2-NEXT: ret void, !dbg [[DBG280:![0-9]+]] 3252 // 3253 // 3254 // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei 3255 // SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG281:![0-9]+]] { 3256 // SIMD2-NEXT: entry: 3257 // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3258 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3259 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3260 // SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META282:![0-9]+]], !DIExpression(), [[META283:![0-9]+]]) 3261 // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3262 // SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META284:![0-9]+]], !DIExpression(), [[META285:![0-9]+]]) 3263 // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3264 // SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG286:![0-9]+]] 3265 // SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG287:![0-9]+]] 3266 // SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG286]] 3267 // SIMD2-NEXT: ret void, !dbg [[DBG288:![0-9]+]] 3268 // 3269 // 3270 // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev 3271 // SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG289:![0-9]+]] { 3272 // SIMD2-NEXT: entry: 3273 // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3274 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3275 // SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META290:![0-9]+]], !DIExpression(), [[META291:![0-9]+]]) 3276 // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3277 // SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG292:![0-9]+]] 3278 // SIMD2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG294:![0-9]+]] 3279 // SIMD2-NEXT: ret void, !dbg [[DBG295:![0-9]+]] 3280 // 3281 // 3282 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4C2Ei 3283 // SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG296:![0-9]+]] { 3284 // SIMD2-NEXT: entry: 3285 // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3286 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3287 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3288 // SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META297:![0-9]+]], !DIExpression(), [[META298:![0-9]+]]) 3289 // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3290 // SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META299:![0-9]+]], !DIExpression(), [[META300:![0-9]+]]) 3291 // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3292 // SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG301:![0-9]+]] 3293 // SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG302:![0-9]+]] 3294 // SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG301]] 3295 // SIMD2-NEXT: ret void, !dbg [[DBG303:![0-9]+]] 3296 // 3297 // 3298 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4D2Ev 3299 // SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG304:![0-9]+]] { 3300 // SIMD2-NEXT: entry: 3301 // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3302 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3303 // SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META305:![0-9]+]], !DIExpression(), [[META306:![0-9]+]]) 3304 // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3305 // SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG307:![0-9]+]] 3306 // SIMD2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG309:![0-9]+]] 3307 // SIMD2-NEXT: ret void, !dbg [[DBG310:![0-9]+]] 3308 // 3309 // 3310 // SIMD2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp 3311 // SIMD2-SAME: () #[[ATTR0]] !dbg [[DBG311:![0-9]+]] { 3312 // SIMD2-NEXT: entry: 3313 // SIMD2-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG313:![0-9]+]] 3314 // SIMD2-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG313]] 3315 // SIMD2-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG313]] 3316 // SIMD2-NEXT: ret void 3317 // 3318 // 3319 // CHECK-TLS1-LABEL: define {{[^@]+}}@__cxx_global_var_init 3320 // CHECK-TLS1-SAME: () #[[ATTR0:[0-9]+]] { 3321 // CHECK-TLS1-NEXT: entry: 3322 // CHECK-TLS1-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5) 3323 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]] 3324 // CHECK-TLS1-NEXT: ret void 3325 // 3326 // 3327 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S1C1Ei 3328 // CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3329 // CHECK-TLS1-NEXT: entry: 3330 // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3331 // CHECK-TLS1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3332 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3333 // CHECK-TLS1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3334 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3335 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3336 // CHECK-TLS1-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 3337 // CHECK-TLS1-NEXT: ret void 3338 // 3339 // 3340 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S1D1Ev 3341 // CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { 3342 // CHECK-TLS1-NEXT: entry: 3343 // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3344 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3345 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3346 // CHECK-TLS1-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] 3347 // CHECK-TLS1-NEXT: ret void 3348 // 3349 // 3350 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S1C2Ei 3351 // CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 3352 // CHECK-TLS1-NEXT: entry: 3353 // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3354 // CHECK-TLS1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3355 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3356 // CHECK-TLS1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3357 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3358 // CHECK-TLS1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 3359 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3360 // CHECK-TLS1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4 3361 // CHECK-TLS1-NEXT: ret void 3362 // 3363 // 3364 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S1D2Ev 3365 // CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 3366 // CHECK-TLS1-NEXT: entry: 3367 // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3368 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3369 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3370 // CHECK-TLS1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 3371 // CHECK-TLS1-NEXT: store i32 0, ptr [[A]], align 4 3372 // CHECK-TLS1-NEXT: ret void 3373 // 3374 // 3375 // CHECK-TLS1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 3376 // CHECK-TLS1-SAME: () #[[ATTR0]] { 3377 // CHECK-TLS1-NEXT: entry: 3378 // CHECK-TLS1-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27) 3379 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]] 3380 // CHECK-TLS1-NEXT: ret void 3381 // 3382 // 3383 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S2C1Ei 3384 // CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3385 // CHECK-TLS1-NEXT: entry: 3386 // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3387 // CHECK-TLS1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3388 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3389 // CHECK-TLS1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3390 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3391 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3392 // CHECK-TLS1-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]) 3393 // CHECK-TLS1-NEXT: ret void 3394 // 3395 // 3396 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S2D1Ev 3397 // CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 3398 // CHECK-TLS1-NEXT: entry: 3399 // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3400 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3401 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3402 // CHECK-TLS1-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]] 3403 // CHECK-TLS1-NEXT: ret void 3404 // 3405 // 3406 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S2C2Ei 3407 // CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 3408 // CHECK-TLS1-NEXT: entry: 3409 // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3410 // CHECK-TLS1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3411 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3412 // CHECK-TLS1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3413 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3414 // CHECK-TLS1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0 3415 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3416 // CHECK-TLS1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8 3417 // CHECK-TLS1-NEXT: ret void 3418 // 3419 // 3420 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S2D2Ev 3421 // CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 3422 // CHECK-TLS1-NEXT: entry: 3423 // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3424 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3425 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3426 // CHECK-TLS1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0 3427 // CHECK-TLS1-NEXT: store i32 0, ptr [[A]], align 8 3428 // CHECK-TLS1-NEXT: ret void 3429 // 3430 // 3431 // CHECK-TLS1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 3432 // CHECK-TLS1-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 { 3433 // CHECK-TLS1-NEXT: entry: 3434 // CHECK-TLS1-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 3435 // CHECK-TLS1-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 3436 // CHECK-TLS1-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 3437 // CHECK-TLS1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 3438 // CHECK-TLS1-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 3439 // CHECK-TLS1-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8 3440 // CHECK-TLS1-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8 3441 // CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) 3442 // CHECK-TLS1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] 3443 // CHECK-TLS1: invoke.cont: 3444 // CHECK-TLS1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8 3445 // CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) 3446 // CHECK-TLS1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]] 3447 // CHECK-TLS1: invoke.cont2: 3448 // CHECK-TLS1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8 3449 // CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) 3450 // CHECK-TLS1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] 3451 // CHECK-TLS1: invoke.cont3: 3452 // CHECK-TLS1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8 3453 // CHECK-TLS1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 3454 // CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) 3455 // CHECK-TLS1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]] 3456 // CHECK-TLS1: invoke.cont7: 3457 // CHECK-TLS1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 3458 // CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) 3459 // CHECK-TLS1-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]] 3460 // CHECK-TLS1: invoke.cont8: 3461 // CHECK-TLS1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 3462 // CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) 3463 // CHECK-TLS1-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]] 3464 // CHECK-TLS1: invoke.cont9: 3465 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]] 3466 // CHECK-TLS1-NEXT: ret void 3467 // CHECK-TLS1: lpad: 3468 // CHECK-TLS1-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } 3469 // CHECK-TLS1-NEXT: cleanup 3470 // CHECK-TLS1-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0 3471 // CHECK-TLS1-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8 3472 // CHECK-TLS1-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1 3473 // CHECK-TLS1-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4 3474 // CHECK-TLS1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8 3475 // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]] 3476 // CHECK-TLS1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]] 3477 // CHECK-TLS1: arraydestroy.body: 3478 // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3479 // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3480 // CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 3481 // CHECK-TLS1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x 3482 // CHECK-TLS1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]] 3483 // CHECK-TLS1: arraydestroy.done4: 3484 // CHECK-TLS1-NEXT: br label [[EHCLEANUP:%.*]] 3485 // CHECK-TLS1: lpad6: 3486 // CHECK-TLS1-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } 3487 // CHECK-TLS1-NEXT: cleanup 3488 // CHECK-TLS1-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0 3489 // CHECK-TLS1-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8 3490 // CHECK-TLS1-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1 3491 // CHECK-TLS1-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4 3492 // CHECK-TLS1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8 3493 // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]] 3494 // CHECK-TLS1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]] 3495 // CHECK-TLS1: arraydestroy.body11: 3496 // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ] 3497 // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1 3498 // CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] 3499 // CHECK-TLS1-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1) 3500 // CHECK-TLS1-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]] 3501 // CHECK-TLS1: arraydestroy.done15: 3502 // CHECK-TLS1-NEXT: br label [[EHCLEANUP]] 3503 // CHECK-TLS1: ehcleanup: 3504 // CHECK-TLS1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8 3505 // CHECK-TLS1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0 3506 // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]] 3507 // CHECK-TLS1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]] 3508 // CHECK-TLS1: arraydestroy.body17: 3509 // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] 3510 // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 3511 // CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] 3512 // CHECK-TLS1-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x 3513 // CHECK-TLS1-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] 3514 // CHECK-TLS1: arraydestroy.done21: 3515 // CHECK-TLS1-NEXT: br label [[EH_RESUME:%.*]] 3516 // CHECK-TLS1: eh.resume: 3517 // CHECK-TLS1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 3518 // CHECK-TLS1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 3519 // CHECK-TLS1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 3520 // CHECK-TLS1-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 3521 // CHECK-TLS1-NEXT: resume { ptr, i32 } [[LPAD_VAL22]] 3522 // 3523 // 3524 // CHECK-TLS1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 3525 // CHECK-TLS1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 3526 // CHECK-TLS1-NEXT: entry: 3527 // CHECK-TLS1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 3528 // CHECK-TLS1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 3529 // CHECK-TLS1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3530 // CHECK-TLS1: arraydestroy.body: 3531 // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3532 // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3533 // CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 3534 // CHECK-TLS1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x 3535 // CHECK-TLS1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3536 // CHECK-TLS1: arraydestroy.done1: 3537 // CHECK-TLS1-NEXT: ret void 3538 // 3539 // 3540 // CHECK-TLS1-LABEL: define {{[^@]+}}@main 3541 // CHECK-TLS1-SAME: () #[[ATTR4:[0-9]+]] { 3542 // CHECK-TLS1-NEXT: entry: 3543 // CHECK-TLS1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3544 // CHECK-TLS1-NEXT: [[RES:%.*]] = alloca i32, align 4 3545 // CHECK-TLS1-NEXT: store i32 0, ptr [[RETVAL]], align 4 3546 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVZ4mainE2sm, align 1 3547 // CHECK-TLS1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 3548 // CHECK-TLS1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]] 3549 // CHECK-TLS1: init.check: 3550 // CHECK-TLS1-NEXT: [[TMP1:%.*]] = call ptr @_ZTWL3gs1() 3551 // CHECK-TLS1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP1]], i32 0, i32 0 3552 // CHECK-TLS1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 3553 // CHECK-TLS1-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]]) 3554 // CHECK-TLS1-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]] 3555 // CHECK-TLS1-NEXT: store i8 1, ptr @_ZGVZ4mainE2sm, align 1 3556 // CHECK-TLS1-NEXT: br label [[INIT_END]] 3557 // CHECK-TLS1: init.end: 3558 // CHECK-TLS1-NEXT: [[TMP4:%.*]] = call ptr @_ZTWN6Static1sE() 3559 // CHECK-TLS1-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP4]], i32 0, i32 0 3560 // CHECK-TLS1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A1]], align 4 3561 // CHECK-TLS1-NEXT: store i32 [[TMP5]], ptr [[RES]], align 4 3562 // CHECK-TLS1-NEXT: [[TMP6:%.*]] = call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @_ZZ4mainE2sm) 3563 // CHECK-TLS1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[TMP6]], i32 0, i32 0 3564 // CHECK-TLS1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A2]], align 8 3565 // CHECK-TLS1-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4 3566 // CHECK-TLS1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] 3567 // CHECK-TLS1-NEXT: store i32 [[ADD]], ptr [[RES]], align 4 3568 // CHECK-TLS1-NEXT: [[TMP9:%.*]] = call ptr @_ZTWL3gs1() 3569 // CHECK-TLS1-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP9]], i32 0, i32 0 3570 // CHECK-TLS1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A3]], align 4 3571 // CHECK-TLS1-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4 3572 // CHECK-TLS1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP10]] 3573 // CHECK-TLS1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 3574 // CHECK-TLS1-NEXT: [[TMP12:%.*]] = load i32, ptr @_ZL3gs2, align 8 3575 // CHECK-TLS1-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4 3576 // CHECK-TLS1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], [[TMP12]] 3577 // CHECK-TLS1-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4 3578 // CHECK-TLS1-NEXT: [[TMP14:%.*]] = call ptr @_ZTW3gs3() 3579 // CHECK-TLS1-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP14]], i32 0, i32 0 3580 // CHECK-TLS1-NEXT: [[TMP15:%.*]] = load i32, ptr [[A6]], align 4 3581 // CHECK-TLS1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4 3582 // CHECK-TLS1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 3583 // CHECK-TLS1-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4 3584 // CHECK-TLS1-NEXT: [[TMP17:%.*]] = call ptr @_ZTW5arr_x() 3585 // CHECK-TLS1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], i64 0, i64 1 3586 // CHECK-TLS1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 3587 // CHECK-TLS1-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0 3588 // CHECK-TLS1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A9]], align 4 3589 // CHECK-TLS1-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4 3590 // CHECK-TLS1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], [[TMP18]] 3591 // CHECK-TLS1-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4 3592 // CHECK-TLS1-NEXT: [[TMP20:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE) 3593 // CHECK-TLS1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 3594 // CHECK-TLS1-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4 3595 // CHECK-TLS1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]] 3596 // CHECK-TLS1-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4 3597 // CHECK-TLS1-NEXT: [[TMP23:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE) 3598 // CHECK-TLS1-NEXT: [[TMP24:%.*]] = load float, ptr [[TMP23]], align 4 3599 // CHECK-TLS1-NEXT: [[CONV:%.*]] = fptosi float [[TMP24]] to i32 3600 // CHECK-TLS1-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4 3601 // CHECK-TLS1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP25]], [[CONV]] 3602 // CHECK-TLS1-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4 3603 // CHECK-TLS1-NEXT: [[TMP26:%.*]] = call ptr @_ZTWN2STI2S4E2stE() 3604 // CHECK-TLS1-NEXT: [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP26]], i32 0, i32 0 3605 // CHECK-TLS1-NEXT: [[TMP27:%.*]] = load i32, ptr [[A13]], align 4 3606 // CHECK-TLS1-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4 3607 // CHECK-TLS1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], [[TMP27]] 3608 // CHECK-TLS1-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4 3609 // CHECK-TLS1-NEXT: [[TMP29:%.*]] = load i32, ptr [[RES]], align 4 3610 // CHECK-TLS1-NEXT: ret i32 [[TMP29]] 3611 // 3612 // 3613 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZTWL3gs1 3614 // CHECK-TLS1-SAME: () #[[ATTR5:[0-9]+]] { 3615 // CHECK-TLS1-NEXT: call void @_ZTHL3gs1() 3616 // CHECK-TLS1-NEXT: [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZL3gs1) 3617 // CHECK-TLS1-NEXT: ret ptr [[TMP1]] 3618 // 3619 // 3620 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei 3621 // CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 3622 // CHECK-TLS1-NEXT: entry: 3623 // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3624 // CHECK-TLS1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3625 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3626 // CHECK-TLS1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3627 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3628 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3629 // CHECK-TLS1-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]) 3630 // CHECK-TLS1-NEXT: ret void 3631 // 3632 // 3633 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev 3634 // CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 3635 // CHECK-TLS1-NEXT: entry: 3636 // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3637 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3638 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3639 // CHECK-TLS1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] 3640 // CHECK-TLS1-NEXT: ret void 3641 // 3642 // 3643 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZTWN6Static1sE 3644 // CHECK-TLS1-SAME: () #[[ATTR5]] comdat { 3645 // CHECK-TLS1-NEXT: [[TMP1:%.*]] = icmp ne ptr @_ZTHN6Static1sE, null 3646 // CHECK-TLS1-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP3:%.*]] 3647 // CHECK-TLS1: 2: 3648 // CHECK-TLS1-NEXT: call void @_ZTHN6Static1sE() 3649 // CHECK-TLS1-NEXT: br label [[TMP3]] 3650 // CHECK-TLS1: 3: 3651 // CHECK-TLS1-NEXT: [[TMP4:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN6Static1sE) 3652 // CHECK-TLS1-NEXT: ret ptr [[TMP4]] 3653 // 3654 // 3655 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZTW3gs3 3656 // CHECK-TLS1-SAME: () #[[ATTR5]] comdat { 3657 // CHECK-TLS1-NEXT: [[TMP1:%.*]] = icmp ne ptr @_ZTH3gs3, null 3658 // CHECK-TLS1-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP3:%.*]] 3659 // CHECK-TLS1: 2: 3660 // CHECK-TLS1-NEXT: call void @_ZTH3gs3() 3661 // CHECK-TLS1-NEXT: br label [[TMP3]] 3662 // CHECK-TLS1: 3: 3663 // CHECK-TLS1-NEXT: [[TMP4:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @gs3) 3664 // CHECK-TLS1-NEXT: ret ptr [[TMP4]] 3665 // 3666 // 3667 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZTW5arr_x 3668 // CHECK-TLS1-SAME: () #[[ATTR5]] comdat { 3669 // CHECK-TLS1-NEXT: call void @_ZTH5arr_x() 3670 // CHECK-TLS1-NEXT: [[TMP1:%.*]] = call align 16 ptr @llvm.threadlocal.address.p0(ptr align 16 @arr_x) 3671 // CHECK-TLS1-NEXT: ret ptr [[TMP1]] 3672 // 3673 // 3674 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZTWN2STI2S4E2stE 3675 // CHECK-TLS1-SAME: () #[[ATTR5]] comdat { 3676 // CHECK-TLS1-NEXT: call void @_ZTHN2STI2S4E2stE() 3677 // CHECK-TLS1-NEXT: [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STI2S4E2stE) 3678 // CHECK-TLS1-NEXT: ret ptr [[TMP1]] 3679 // 3680 // 3681 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei 3682 // CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 3683 // CHECK-TLS1-NEXT: entry: 3684 // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3685 // CHECK-TLS1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3686 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3687 // CHECK-TLS1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3688 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3689 // CHECK-TLS1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0 3690 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3691 // CHECK-TLS1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8 3692 // CHECK-TLS1-NEXT: ret void 3693 // 3694 // 3695 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev 3696 // CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 3697 // CHECK-TLS1-NEXT: entry: 3698 // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3699 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3700 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3701 // CHECK-TLS1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0 3702 // CHECK-TLS1-NEXT: store i32 0, ptr [[A]], align 8 3703 // CHECK-TLS1-NEXT: ret void 3704 // 3705 // 3706 // CHECK-TLS1-LABEL: define {{[^@]+}}@_Z6foobarv 3707 // CHECK-TLS1-SAME: () #[[ATTR1]] { 3708 // CHECK-TLS1-NEXT: entry: 3709 // CHECK-TLS1-NEXT: [[RES:%.*]] = alloca i32, align 4 3710 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = call ptr @_ZTWN6Static1sE() 3711 // CHECK-TLS1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP0]], i32 0, i32 0 3712 // CHECK-TLS1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 3713 // CHECK-TLS1-NEXT: store i32 [[TMP1]], ptr [[RES]], align 4 3714 // CHECK-TLS1-NEXT: [[TMP2:%.*]] = call ptr @_ZTWL3gs1() 3715 // CHECK-TLS1-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0 3716 // CHECK-TLS1-NEXT: [[TMP3:%.*]] = load i32, ptr [[A1]], align 4 3717 // CHECK-TLS1-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4 3718 // CHECK-TLS1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP3]] 3719 // CHECK-TLS1-NEXT: store i32 [[ADD]], ptr [[RES]], align 4 3720 // CHECK-TLS1-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZL3gs2, align 8 3721 // CHECK-TLS1-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4 3722 // CHECK-TLS1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 3723 // CHECK-TLS1-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4 3724 // CHECK-TLS1-NEXT: [[TMP7:%.*]] = call ptr @_ZTW3gs3() 3725 // CHECK-TLS1-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP7]], i32 0, i32 0 3726 // CHECK-TLS1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A3]], align 4 3727 // CHECK-TLS1-NEXT: [[TMP9:%.*]] = load i32, ptr [[RES]], align 4 3728 // CHECK-TLS1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] 3729 // CHECK-TLS1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 3730 // CHECK-TLS1-NEXT: [[TMP10:%.*]] = call ptr @_ZTW5arr_x() 3731 // CHECK-TLS1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], i64 0, i64 1 3732 // CHECK-TLS1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 3733 // CHECK-TLS1-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0 3734 // CHECK-TLS1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A6]], align 4 3735 // CHECK-TLS1-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4 3736 // CHECK-TLS1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 3737 // CHECK-TLS1-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4 3738 // CHECK-TLS1-NEXT: [[TMP13:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE) 3739 // CHECK-TLS1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 3740 // CHECK-TLS1-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4 3741 // CHECK-TLS1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], [[TMP14]] 3742 // CHECK-TLS1-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4 3743 // CHECK-TLS1-NEXT: [[TMP16:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE) 3744 // CHECK-TLS1-NEXT: [[TMP17:%.*]] = load float, ptr [[TMP16]], align 4 3745 // CHECK-TLS1-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32 3746 // CHECK-TLS1-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4 3747 // CHECK-TLS1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[CONV]] 3748 // CHECK-TLS1-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4 3749 // CHECK-TLS1-NEXT: [[TMP19:%.*]] = call ptr @_ZTWN2STI2S4E2stE() 3750 // CHECK-TLS1-NEXT: [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP19]], i32 0, i32 0 3751 // CHECK-TLS1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A10]], align 4 3752 // CHECK-TLS1-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4 3753 // CHECK-TLS1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] 3754 // CHECK-TLS1-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4 3755 // CHECK-TLS1-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4 3756 // CHECK-TLS1-NEXT: ret i32 [[TMP22]] 3757 // 3758 // 3759 // CHECK-TLS1-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 3760 // CHECK-TLS1-SAME: () #[[ATTR0]] { 3761 // CHECK-TLS1-NEXT: entry: 3762 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8 3763 // CHECK-TLS1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 3764 // CHECK-TLS1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]] 3765 // CHECK-TLS1: init.check: 3766 // CHECK-TLS1-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8 3767 // CHECK-TLS1-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23) 3768 // CHECK-TLS1-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]] 3769 // CHECK-TLS1-NEXT: br label [[INIT_END]] 3770 // CHECK-TLS1: init.end: 3771 // CHECK-TLS1-NEXT: ret void 3772 // 3773 // 3774 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S4C1Ei 3775 // CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3776 // CHECK-TLS1-NEXT: entry: 3777 // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3778 // CHECK-TLS1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3779 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3780 // CHECK-TLS1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3781 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3782 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3783 // CHECK-TLS1-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]) 3784 // CHECK-TLS1-NEXT: ret void 3785 // 3786 // 3787 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S4D1Ev 3788 // CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 3789 // CHECK-TLS1-NEXT: entry: 3790 // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3791 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3792 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3793 // CHECK-TLS1-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] 3794 // CHECK-TLS1-NEXT: ret void 3795 // 3796 // 3797 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S4C2Ei 3798 // CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 3799 // CHECK-TLS1-NEXT: entry: 3800 // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3801 // CHECK-TLS1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3802 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3803 // CHECK-TLS1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3804 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3805 // CHECK-TLS1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0 3806 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3807 // CHECK-TLS1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4 3808 // CHECK-TLS1-NEXT: ret void 3809 // 3810 // 3811 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S4D2Ev 3812 // CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 3813 // CHECK-TLS1-NEXT: entry: 3814 // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3815 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3816 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3817 // CHECK-TLS1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0 3818 // CHECK-TLS1-NEXT: store i32 0, ptr [[A]], align 4 3819 // CHECK-TLS1-NEXT: ret void 3820 // 3821 // 3822 // CHECK-TLS1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp 3823 // CHECK-TLS1-SAME: () #[[ATTR0]] { 3824 // CHECK-TLS1-NEXT: entry: 3825 // CHECK-TLS1-NEXT: call void @__cxx_global_var_init.1() 3826 // CHECK-TLS1-NEXT: ret void 3827 // 3828 // 3829 // CHECK-TLS1-LABEL: define {{[^@]+}}@__tls_init 3830 // CHECK-TLS1-SAME: () #[[ATTR0]] { 3831 // CHECK-TLS1-NEXT: entry: 3832 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 1 3833 // CHECK-TLS1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 3834 // CHECK-TLS1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !prof [[PROF3]] 3835 // CHECK-TLS1: init: 3836 // CHECK-TLS1-NEXT: store i8 1, ptr @__tls_guard, align 1 3837 // CHECK-TLS1-NEXT: call void @__cxx_global_var_init() 3838 // CHECK-TLS1-NEXT: call void @__cxx_global_var_init.2() 3839 // CHECK-TLS1-NEXT: br label [[EXIT]] 3840 // CHECK-TLS1: exit: 3841 // CHECK-TLS1-NEXT: ret void 3842 // 3843 // 3844 // CHECK-TLS2-LABEL: define {{[^@]+}}@main 3845 // CHECK-TLS2-SAME: () #[[ATTR0:[0-9]+]] { 3846 // CHECK-TLS2-NEXT: entry: 3847 // CHECK-TLS2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3848 // CHECK-TLS2-NEXT: [[RES:%.*]] = alloca i32, align 4 3849 // CHECK-TLS2-NEXT: store i32 0, ptr [[RETVAL]], align 4 3850 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVZ4mainE2sm, align 1 3851 // CHECK-TLS2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 3852 // CHECK-TLS2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]] 3853 // CHECK-TLS2: init.check: 3854 // CHECK-TLS2-NEXT: [[TMP1:%.*]] = call ptr @_ZTWL3gs1() 3855 // CHECK-TLS2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP1]], i32 0, i32 0 3856 // CHECK-TLS2-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 3857 // CHECK-TLS2-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]]) 3858 // CHECK-TLS2-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR4:[0-9]+]] 3859 // CHECK-TLS2-NEXT: store i8 1, ptr @_ZGVZ4mainE2sm, align 1 3860 // CHECK-TLS2-NEXT: br label [[INIT_END]] 3861 // CHECK-TLS2: init.end: 3862 // CHECK-TLS2-NEXT: [[TMP4:%.*]] = call ptr @_ZTWN6Static1sE() 3863 // CHECK-TLS2-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP4]], i32 0, i32 0 3864 // CHECK-TLS2-NEXT: [[TMP5:%.*]] = load i32, ptr [[A1]], align 4 3865 // CHECK-TLS2-NEXT: store i32 [[TMP5]], ptr [[RES]], align 4 3866 // CHECK-TLS2-NEXT: [[TMP6:%.*]] = call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @_ZZ4mainE2sm) 3867 // CHECK-TLS2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[TMP6]], i32 0, i32 0 3868 // CHECK-TLS2-NEXT: [[TMP7:%.*]] = load i32, ptr [[A2]], align 8 3869 // CHECK-TLS2-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4 3870 // CHECK-TLS2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] 3871 // CHECK-TLS2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4 3872 // CHECK-TLS2-NEXT: [[TMP9:%.*]] = call ptr @_ZTWL3gs1() 3873 // CHECK-TLS2-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP9]], i32 0, i32 0 3874 // CHECK-TLS2-NEXT: [[TMP10:%.*]] = load i32, ptr [[A3]], align 4 3875 // CHECK-TLS2-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4 3876 // CHECK-TLS2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP10]] 3877 // CHECK-TLS2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 3878 // CHECK-TLS2-NEXT: [[TMP12:%.*]] = load i32, ptr @_ZL3gs2, align 8 3879 // CHECK-TLS2-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4 3880 // CHECK-TLS2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], [[TMP12]] 3881 // CHECK-TLS2-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4 3882 // CHECK-TLS2-NEXT: [[TMP14:%.*]] = call ptr @_ZTW3gs3() 3883 // CHECK-TLS2-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP14]], i32 0, i32 0 3884 // CHECK-TLS2-NEXT: [[TMP15:%.*]] = load i32, ptr [[A6]], align 4 3885 // CHECK-TLS2-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4 3886 // CHECK-TLS2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 3887 // CHECK-TLS2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4 3888 // CHECK-TLS2-NEXT: [[TMP17:%.*]] = call ptr @_ZTW5arr_x() 3889 // CHECK-TLS2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], i64 0, i64 1 3890 // CHECK-TLS2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 3891 // CHECK-TLS2-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0 3892 // CHECK-TLS2-NEXT: [[TMP18:%.*]] = load i32, ptr [[A9]], align 4 3893 // CHECK-TLS2-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4 3894 // CHECK-TLS2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], [[TMP18]] 3895 // CHECK-TLS2-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4 3896 // CHECK-TLS2-NEXT: [[TMP20:%.*]] = call ptr @_ZTWN2STIiE2stE() 3897 // CHECK-TLS2-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 3898 // CHECK-TLS2-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4 3899 // CHECK-TLS2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]] 3900 // CHECK-TLS2-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4 3901 // CHECK-TLS2-NEXT: [[TMP23:%.*]] = call ptr @_ZTWN2STIfE2stE() 3902 // CHECK-TLS2-NEXT: [[TMP24:%.*]] = load float, ptr [[TMP23]], align 4 3903 // CHECK-TLS2-NEXT: [[CONV:%.*]] = fptosi float [[TMP24]] to i32 3904 // CHECK-TLS2-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4 3905 // CHECK-TLS2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP25]], [[CONV]] 3906 // CHECK-TLS2-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4 3907 // CHECK-TLS2-NEXT: [[TMP26:%.*]] = call ptr @_ZTWN2STI2S4E2stE() 3908 // CHECK-TLS2-NEXT: [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP26]], i32 0, i32 0 3909 // CHECK-TLS2-NEXT: [[TMP27:%.*]] = load i32, ptr [[A13]], align 4 3910 // CHECK-TLS2-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4 3911 // CHECK-TLS2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], [[TMP27]] 3912 // CHECK-TLS2-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4 3913 // CHECK-TLS2-NEXT: [[TMP29:%.*]] = load i32, ptr [[RES]], align 4 3914 // CHECK-TLS2-NEXT: ret i32 [[TMP29]] 3915 // 3916 // 3917 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZTWL3gs1 3918 // CHECK-TLS2-SAME: () #[[ATTR1:[0-9]+]] { 3919 // CHECK-TLS2-NEXT: call void @_ZTHL3gs1() 3920 // CHECK-TLS2-NEXT: [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZL3gs1) 3921 // CHECK-TLS2-NEXT: ret ptr [[TMP1]] 3922 // 3923 // 3924 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei 3925 // CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { 3926 // CHECK-TLS2-NEXT: entry: 3927 // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3928 // CHECK-TLS2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3929 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3930 // CHECK-TLS2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3931 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3932 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3933 // CHECK-TLS2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]) 3934 // CHECK-TLS2-NEXT: ret void 3935 // 3936 // 3937 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev 3938 // CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 { 3939 // CHECK-TLS2-NEXT: entry: 3940 // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3941 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3942 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3943 // CHECK-TLS2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]] 3944 // CHECK-TLS2-NEXT: ret void 3945 // 3946 // 3947 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZTWN6Static1sE 3948 // CHECK-TLS2-SAME: () #[[ATTR1]] comdat { 3949 // CHECK-TLS2-NEXT: [[TMP1:%.*]] = icmp ne ptr @_ZTHN6Static1sE, null 3950 // CHECK-TLS2-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP3:%.*]] 3951 // CHECK-TLS2: 2: 3952 // CHECK-TLS2-NEXT: call void @_ZTHN6Static1sE() 3953 // CHECK-TLS2-NEXT: br label [[TMP3]] 3954 // CHECK-TLS2: 3: 3955 // CHECK-TLS2-NEXT: [[TMP4:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN6Static1sE) 3956 // CHECK-TLS2-NEXT: ret ptr [[TMP4]] 3957 // 3958 // 3959 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZTW3gs3 3960 // CHECK-TLS2-SAME: () #[[ATTR1]] comdat { 3961 // CHECK-TLS2-NEXT: [[TMP1:%.*]] = icmp ne ptr @_ZTH3gs3, null 3962 // CHECK-TLS2-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP3:%.*]] 3963 // CHECK-TLS2: 2: 3964 // CHECK-TLS2-NEXT: call void @_ZTH3gs3() 3965 // CHECK-TLS2-NEXT: br label [[TMP3]] 3966 // CHECK-TLS2: 3: 3967 // CHECK-TLS2-NEXT: [[TMP4:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @gs3) 3968 // CHECK-TLS2-NEXT: ret ptr [[TMP4]] 3969 // 3970 // 3971 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZTW5arr_x 3972 // CHECK-TLS2-SAME: () #[[ATTR1]] comdat { 3973 // CHECK-TLS2-NEXT: call void @_ZTH5arr_x() 3974 // CHECK-TLS2-NEXT: [[TMP1:%.*]] = call align 16 ptr @llvm.threadlocal.address.p0(ptr align 16 @arr_x) 3975 // CHECK-TLS2-NEXT: ret ptr [[TMP1]] 3976 // 3977 // 3978 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZTWN2STIiE2stE 3979 // CHECK-TLS2-SAME: () #[[ATTR1]] comdat { 3980 // CHECK-TLS2-NEXT: [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE) 3981 // CHECK-TLS2-NEXT: ret ptr [[TMP1]] 3982 // 3983 // 3984 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZTWN2STIfE2stE 3985 // CHECK-TLS2-SAME: () #[[ATTR1]] comdat { 3986 // CHECK-TLS2-NEXT: [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE) 3987 // CHECK-TLS2-NEXT: ret ptr [[TMP1]] 3988 // 3989 // 3990 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZTWN2STI2S4E2stE 3991 // CHECK-TLS2-SAME: () #[[ATTR1]] comdat { 3992 // CHECK-TLS2-NEXT: call void @_ZTHN2STI2S4E2stE() 3993 // CHECK-TLS2-NEXT: [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STI2S4E2stE) 3994 // CHECK-TLS2-NEXT: ret ptr [[TMP1]] 3995 // 3996 // 3997 // CHECK-TLS2-LABEL: define {{[^@]+}}@_Z6foobarv 3998 // CHECK-TLS2-SAME: () #[[ATTR2]] { 3999 // CHECK-TLS2-NEXT: entry: 4000 // CHECK-TLS2-NEXT: [[RES:%.*]] = alloca i32, align 4 4001 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = call ptr @_ZTWN6Static1sE() 4002 // CHECK-TLS2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP0]], i32 0, i32 0 4003 // CHECK-TLS2-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 4004 // CHECK-TLS2-NEXT: store i32 [[TMP1]], ptr [[RES]], align 4 4005 // CHECK-TLS2-NEXT: [[TMP2:%.*]] = call ptr @_ZTWL3gs1() 4006 // CHECK-TLS2-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0 4007 // CHECK-TLS2-NEXT: [[TMP3:%.*]] = load i32, ptr [[A1]], align 4 4008 // CHECK-TLS2-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4 4009 // CHECK-TLS2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP3]] 4010 // CHECK-TLS2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4 4011 // CHECK-TLS2-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZL3gs2, align 8 4012 // CHECK-TLS2-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4 4013 // CHECK-TLS2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 4014 // CHECK-TLS2-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4 4015 // CHECK-TLS2-NEXT: [[TMP7:%.*]] = call ptr @_ZTW3gs3() 4016 // CHECK-TLS2-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP7]], i32 0, i32 0 4017 // CHECK-TLS2-NEXT: [[TMP8:%.*]] = load i32, ptr [[A3]], align 4 4018 // CHECK-TLS2-NEXT: [[TMP9:%.*]] = load i32, ptr [[RES]], align 4 4019 // CHECK-TLS2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] 4020 // CHECK-TLS2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 4021 // CHECK-TLS2-NEXT: [[TMP10:%.*]] = call ptr @_ZTW5arr_x() 4022 // CHECK-TLS2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], i64 0, i64 1 4023 // CHECK-TLS2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 4024 // CHECK-TLS2-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0 4025 // CHECK-TLS2-NEXT: [[TMP11:%.*]] = load i32, ptr [[A6]], align 4 4026 // CHECK-TLS2-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4 4027 // CHECK-TLS2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 4028 // CHECK-TLS2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4 4029 // CHECK-TLS2-NEXT: [[TMP13:%.*]] = call ptr @_ZTWN2STIiE2stE() 4030 // CHECK-TLS2-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 4031 // CHECK-TLS2-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4 4032 // CHECK-TLS2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], [[TMP14]] 4033 // CHECK-TLS2-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4 4034 // CHECK-TLS2-NEXT: [[TMP16:%.*]] = call ptr @_ZTWN2STIfE2stE() 4035 // CHECK-TLS2-NEXT: [[TMP17:%.*]] = load float, ptr [[TMP16]], align 4 4036 // CHECK-TLS2-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32 4037 // CHECK-TLS2-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4 4038 // CHECK-TLS2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[CONV]] 4039 // CHECK-TLS2-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4 4040 // CHECK-TLS2-NEXT: [[TMP19:%.*]] = call ptr @_ZTWN2STI2S4E2stE() 4041 // CHECK-TLS2-NEXT: [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP19]], i32 0, i32 0 4042 // CHECK-TLS2-NEXT: [[TMP20:%.*]] = load i32, ptr [[A10]], align 4 4043 // CHECK-TLS2-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4 4044 // CHECK-TLS2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] 4045 // CHECK-TLS2-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4 4046 // CHECK-TLS2-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4 4047 // CHECK-TLS2-NEXT: ret i32 [[TMP22]] 4048 // 4049 // 4050 // CHECK-TLS2-LABEL: define {{[^@]+}}@__cxx_global_var_init 4051 // CHECK-TLS2-SAME: () #[[ATTR6:[0-9]+]] { 4052 // CHECK-TLS2-NEXT: entry: 4053 // CHECK-TLS2-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5) 4054 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR4]] 4055 // CHECK-TLS2-NEXT: ret void 4056 // 4057 // 4058 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S1C1Ei 4059 // CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 4060 // CHECK-TLS2-NEXT: entry: 4061 // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4062 // CHECK-TLS2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4063 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4064 // CHECK-TLS2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4065 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4066 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4067 // CHECK-TLS2-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 4068 // CHECK-TLS2-NEXT: ret void 4069 // 4070 // 4071 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S1D1Ev 4072 // CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { 4073 // CHECK-TLS2-NEXT: entry: 4074 // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4075 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4076 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4077 // CHECK-TLS2-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 4078 // CHECK-TLS2-NEXT: ret void 4079 // 4080 // 4081 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S1C2Ei 4082 // CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { 4083 // CHECK-TLS2-NEXT: entry: 4084 // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4085 // CHECK-TLS2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4086 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4087 // CHECK-TLS2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4088 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4089 // CHECK-TLS2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 4090 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4091 // CHECK-TLS2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4 4092 // CHECK-TLS2-NEXT: ret void 4093 // 4094 // 4095 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S1D2Ev 4096 // CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { 4097 // CHECK-TLS2-NEXT: entry: 4098 // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4099 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4100 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4101 // CHECK-TLS2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 4102 // CHECK-TLS2-NEXT: store i32 0, ptr [[A]], align 4 4103 // CHECK-TLS2-NEXT: ret void 4104 // 4105 // 4106 // CHECK-TLS2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 4107 // CHECK-TLS2-SAME: () #[[ATTR6]] { 4108 // CHECK-TLS2-NEXT: entry: 4109 // CHECK-TLS2-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27) 4110 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR4]] 4111 // CHECK-TLS2-NEXT: ret void 4112 // 4113 // 4114 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S2C1Ei 4115 // CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 4116 // CHECK-TLS2-NEXT: entry: 4117 // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4118 // CHECK-TLS2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4119 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4120 // CHECK-TLS2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4121 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4122 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4123 // CHECK-TLS2-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]) 4124 // CHECK-TLS2-NEXT: ret void 4125 // 4126 // 4127 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S2D1Ev 4128 // CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { 4129 // CHECK-TLS2-NEXT: entry: 4130 // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4131 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4132 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4133 // CHECK-TLS2-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR4]] 4134 // CHECK-TLS2-NEXT: ret void 4135 // 4136 // 4137 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S2C2Ei 4138 // CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { 4139 // CHECK-TLS2-NEXT: entry: 4140 // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4141 // CHECK-TLS2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4142 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4143 // CHECK-TLS2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4144 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4145 // CHECK-TLS2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0 4146 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4147 // CHECK-TLS2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8 4148 // CHECK-TLS2-NEXT: ret void 4149 // 4150 // 4151 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S2D2Ev 4152 // CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { 4153 // CHECK-TLS2-NEXT: entry: 4154 // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4155 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4156 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4157 // CHECK-TLS2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0 4158 // CHECK-TLS2-NEXT: store i32 0, ptr [[A]], align 8 4159 // CHECK-TLS2-NEXT: ret void 4160 // 4161 // 4162 // CHECK-TLS2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 4163 // CHECK-TLS2-SAME: () #[[ATTR6]] personality ptr @__gxx_personality_v0 { 4164 // CHECK-TLS2-NEXT: entry: 4165 // CHECK-TLS2-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 4166 // CHECK-TLS2-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 4167 // CHECK-TLS2-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 4168 // CHECK-TLS2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 4169 // CHECK-TLS2-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 4170 // CHECK-TLS2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8 4171 // CHECK-TLS2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8 4172 // CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) 4173 // CHECK-TLS2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] 4174 // CHECK-TLS2: invoke.cont: 4175 // CHECK-TLS2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8 4176 // CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) 4177 // CHECK-TLS2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]] 4178 // CHECK-TLS2: invoke.cont2: 4179 // CHECK-TLS2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8 4180 // CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) 4181 // CHECK-TLS2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] 4182 // CHECK-TLS2: invoke.cont3: 4183 // CHECK-TLS2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8 4184 // CHECK-TLS2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 4185 // CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) 4186 // CHECK-TLS2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]] 4187 // CHECK-TLS2: invoke.cont7: 4188 // CHECK-TLS2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 4189 // CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) 4190 // CHECK-TLS2-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]] 4191 // CHECK-TLS2: invoke.cont8: 4192 // CHECK-TLS2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 4193 // CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) 4194 // CHECK-TLS2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]] 4195 // CHECK-TLS2: invoke.cont9: 4196 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR4]] 4197 // CHECK-TLS2-NEXT: ret void 4198 // CHECK-TLS2: lpad: 4199 // CHECK-TLS2-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } 4200 // CHECK-TLS2-NEXT: cleanup 4201 // CHECK-TLS2-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0 4202 // CHECK-TLS2-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8 4203 // CHECK-TLS2-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1 4204 // CHECK-TLS2-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4 4205 // CHECK-TLS2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8 4206 // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]] 4207 // CHECK-TLS2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]] 4208 // CHECK-TLS2: arraydestroy.body: 4209 // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4210 // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4211 // CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 4212 // CHECK-TLS2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x 4213 // CHECK-TLS2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]] 4214 // CHECK-TLS2: arraydestroy.done4: 4215 // CHECK-TLS2-NEXT: br label [[EHCLEANUP:%.*]] 4216 // CHECK-TLS2: lpad6: 4217 // CHECK-TLS2-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } 4218 // CHECK-TLS2-NEXT: cleanup 4219 // CHECK-TLS2-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0 4220 // CHECK-TLS2-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8 4221 // CHECK-TLS2-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1 4222 // CHECK-TLS2-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4 4223 // CHECK-TLS2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8 4224 // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]] 4225 // CHECK-TLS2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]] 4226 // CHECK-TLS2: arraydestroy.body11: 4227 // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ] 4228 // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1 4229 // CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR4]] 4230 // CHECK-TLS2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1) 4231 // CHECK-TLS2-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]] 4232 // CHECK-TLS2: arraydestroy.done15: 4233 // CHECK-TLS2-NEXT: br label [[EHCLEANUP]] 4234 // CHECK-TLS2: ehcleanup: 4235 // CHECK-TLS2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8 4236 // CHECK-TLS2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0 4237 // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]] 4238 // CHECK-TLS2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]] 4239 // CHECK-TLS2: arraydestroy.body17: 4240 // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] 4241 // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 4242 // CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] 4243 // CHECK-TLS2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x 4244 // CHECK-TLS2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] 4245 // CHECK-TLS2: arraydestroy.done21: 4246 // CHECK-TLS2-NEXT: br label [[EH_RESUME:%.*]] 4247 // CHECK-TLS2: eh.resume: 4248 // CHECK-TLS2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 4249 // CHECK-TLS2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 4250 // CHECK-TLS2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 4251 // CHECK-TLS2-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 4252 // CHECK-TLS2-NEXT: resume { ptr, i32 } [[LPAD_VAL22]] 4253 // 4254 // 4255 // CHECK-TLS2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 4256 // CHECK-TLS2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR6]] { 4257 // CHECK-TLS2-NEXT: entry: 4258 // CHECK-TLS2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 4259 // CHECK-TLS2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 4260 // CHECK-TLS2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4261 // CHECK-TLS2: arraydestroy.body: 4262 // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4263 // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4264 // CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 4265 // CHECK-TLS2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x 4266 // CHECK-TLS2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 4267 // CHECK-TLS2: arraydestroy.done1: 4268 // CHECK-TLS2-NEXT: ret void 4269 // 4270 // 4271 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei 4272 // CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] align 2 { 4273 // CHECK-TLS2-NEXT: entry: 4274 // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4275 // CHECK-TLS2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4276 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4277 // CHECK-TLS2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4278 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4279 // CHECK-TLS2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0 4280 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4281 // CHECK-TLS2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8 4282 // CHECK-TLS2-NEXT: ret void 4283 // 4284 // 4285 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev 4286 // CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 { 4287 // CHECK-TLS2-NEXT: entry: 4288 // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4289 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4290 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4291 // CHECK-TLS2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0 4292 // CHECK-TLS2-NEXT: store i32 0, ptr [[A]], align 8 4293 // CHECK-TLS2-NEXT: ret void 4294 // 4295 // 4296 // CHECK-TLS2-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 4297 // CHECK-TLS2-SAME: () #[[ATTR6]] { 4298 // CHECK-TLS2-NEXT: entry: 4299 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8 4300 // CHECK-TLS2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 4301 // CHECK-TLS2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]] 4302 // CHECK-TLS2: init.check: 4303 // CHECK-TLS2-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8 4304 // CHECK-TLS2-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23) 4305 // CHECK-TLS2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR4]] 4306 // CHECK-TLS2-NEXT: br label [[INIT_END]] 4307 // CHECK-TLS2: init.end: 4308 // CHECK-TLS2-NEXT: ret void 4309 // 4310 // 4311 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S4C1Ei 4312 // CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 4313 // CHECK-TLS2-NEXT: entry: 4314 // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4315 // CHECK-TLS2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4316 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4317 // CHECK-TLS2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4318 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4319 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4320 // CHECK-TLS2-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]) 4321 // CHECK-TLS2-NEXT: ret void 4322 // 4323 // 4324 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S4D1Ev 4325 // CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { 4326 // CHECK-TLS2-NEXT: entry: 4327 // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4328 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4329 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4330 // CHECK-TLS2-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] 4331 // CHECK-TLS2-NEXT: ret void 4332 // 4333 // 4334 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S4C2Ei 4335 // CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { 4336 // CHECK-TLS2-NEXT: entry: 4337 // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4338 // CHECK-TLS2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4339 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4340 // CHECK-TLS2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4341 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4342 // CHECK-TLS2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0 4343 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4344 // CHECK-TLS2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4 4345 // CHECK-TLS2-NEXT: ret void 4346 // 4347 // 4348 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S4D2Ev 4349 // CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { 4350 // CHECK-TLS2-NEXT: entry: 4351 // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4352 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4353 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4354 // CHECK-TLS2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0 4355 // CHECK-TLS2-NEXT: store i32 0, ptr [[A]], align 4 4356 // CHECK-TLS2-NEXT: ret void 4357 // 4358 // 4359 // CHECK-TLS2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp 4360 // CHECK-TLS2-SAME: () #[[ATTR6]] { 4361 // CHECK-TLS2-NEXT: entry: 4362 // CHECK-TLS2-NEXT: call void @__cxx_global_var_init.1() 4363 // CHECK-TLS2-NEXT: ret void 4364 // 4365 // 4366 // CHECK-TLS2-LABEL: define {{[^@]+}}@__tls_init 4367 // CHECK-TLS2-SAME: () #[[ATTR6]] { 4368 // CHECK-TLS2-NEXT: entry: 4369 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 1 4370 // CHECK-TLS2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 4371 // CHECK-TLS2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !prof [[PROF3]] 4372 // CHECK-TLS2: init: 4373 // CHECK-TLS2-NEXT: store i8 1, ptr @__tls_guard, align 1 4374 // CHECK-TLS2-NEXT: call void @__cxx_global_var_init() 4375 // CHECK-TLS2-NEXT: call void @__cxx_global_var_init.2() 4376 // CHECK-TLS2-NEXT: br label [[EXIT]] 4377 // CHECK-TLS2: exit: 4378 // CHECK-TLS2-NEXT: ret void 4379 // 4380 // 4381 // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_var_init 4382 // CHECK-TLS3-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG116:![0-9]+]] { 4383 // CHECK-TLS3-NEXT: entry: 4384 // CHECK-TLS3-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG119:![0-9]+]] 4385 // CHECK-TLS3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG121:![0-9]+]] 4386 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG122:![0-9]+]] 4387 // 4388 // 4389 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S1C1Ei 4390 // CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG123:![0-9]+]] { 4391 // CHECK-TLS3-NEXT: entry: 4392 // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4393 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4394 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4395 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META124:![0-9]+]], !DIExpression(), [[META126:![0-9]+]]) 4396 // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4397 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META127:![0-9]+]], !DIExpression(), [[META128:![0-9]+]]) 4398 // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4399 // CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG129:![0-9]+]] 4400 // CHECK-TLS3-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG129]] 4401 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG130:![0-9]+]] 4402 // 4403 // 4404 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S1D1Ev 4405 // CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG131:![0-9]+]] { 4406 // CHECK-TLS3-NEXT: entry: 4407 // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4408 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4409 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META132:![0-9]+]], !DIExpression(), [[META133:![0-9]+]]) 4410 // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4411 // CHECK-TLS3-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG134:![0-9]+]] 4412 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG135:![0-9]+]] 4413 // 4414 // 4415 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S1C2Ei 4416 // CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG136:![0-9]+]] { 4417 // CHECK-TLS3-NEXT: entry: 4418 // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4419 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4420 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4421 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META137:![0-9]+]], !DIExpression(), [[META138:![0-9]+]]) 4422 // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4423 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META139:![0-9]+]], !DIExpression(), [[META140:![0-9]+]]) 4424 // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4425 // CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG141:![0-9]+]] 4426 // CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG142:![0-9]+]] 4427 // CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG141]] 4428 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG143:![0-9]+]] 4429 // 4430 // 4431 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S1D2Ev 4432 // CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG144:![0-9]+]] { 4433 // CHECK-TLS3-NEXT: entry: 4434 // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4435 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4436 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META145:![0-9]+]], !DIExpression(), [[META146:![0-9]+]]) 4437 // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4438 // CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG147:![0-9]+]] 4439 // CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG149:![0-9]+]] 4440 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG150:![0-9]+]] 4441 // 4442 // 4443 // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 4444 // CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG151:![0-9]+]] { 4445 // CHECK-TLS3-NEXT: entry: 4446 // CHECK-TLS3-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG152:![0-9]+]] 4447 // CHECK-TLS3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG154:![0-9]+]] 4448 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG155:![0-9]+]] 4449 // 4450 // 4451 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2C1Ei 4452 // CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG156:![0-9]+]] { 4453 // CHECK-TLS3-NEXT: entry: 4454 // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4455 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4456 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4457 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META157:![0-9]+]], !DIExpression(), [[META159:![0-9]+]]) 4458 // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4459 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META160:![0-9]+]], !DIExpression(), [[META161:![0-9]+]]) 4460 // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4461 // CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG162:![0-9]+]] 4462 // CHECK-TLS3-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG162]] 4463 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG163:![0-9]+]] 4464 // 4465 // 4466 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2D1Ev 4467 // CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG164:![0-9]+]] { 4468 // CHECK-TLS3-NEXT: entry: 4469 // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4470 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4471 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META165:![0-9]+]], !DIExpression(), [[META166:![0-9]+]]) 4472 // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4473 // CHECK-TLS3-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG167:![0-9]+]] 4474 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG168:![0-9]+]] 4475 // 4476 // 4477 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2C2Ei 4478 // CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG169:![0-9]+]] { 4479 // CHECK-TLS3-NEXT: entry: 4480 // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4481 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4482 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4483 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META170:![0-9]+]], !DIExpression(), [[META171:![0-9]+]]) 4484 // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4485 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META172:![0-9]+]], !DIExpression(), [[META173:![0-9]+]]) 4486 // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4487 // CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG174:![0-9]+]] 4488 // CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG175:![0-9]+]] 4489 // CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG174]] 4490 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG176:![0-9]+]] 4491 // 4492 // 4493 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2D2Ev 4494 // CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG177:![0-9]+]] { 4495 // CHECK-TLS3-NEXT: entry: 4496 // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4497 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4498 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META178:![0-9]+]], !DIExpression(), [[META179:![0-9]+]]) 4499 // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4500 // CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG180:![0-9]+]] 4501 // CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG182:![0-9]+]] 4502 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG183:![0-9]+]] 4503 // 4504 // 4505 // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 4506 // CHECK-TLS3-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG184:![0-9]+]] { 4507 // CHECK-TLS3-NEXT: entry: 4508 // CHECK-TLS3-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 4509 // CHECK-TLS3-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 4510 // CHECK-TLS3-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 4511 // CHECK-TLS3-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 4512 // CHECK-TLS3-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 4513 // CHECK-TLS3-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG185:![0-9]+]] 4514 // CHECK-TLS3-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG187:![0-9]+]] 4515 // CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) 4516 // CHECK-TLS3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG188:![0-9]+]] 4517 // CHECK-TLS3: invoke.cont: 4518 // CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG187]] 4519 // CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) 4520 // CHECK-TLS3-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG189:![0-9]+]] 4521 // CHECK-TLS3: invoke.cont2: 4522 // CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG187]] 4523 // CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) 4524 // CHECK-TLS3-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG190:![0-9]+]] 4525 // CHECK-TLS3: invoke.cont3: 4526 // CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG185]] 4527 // CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG191:![0-9]+]] 4528 // CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) 4529 // CHECK-TLS3-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG192:![0-9]+]] 4530 // CHECK-TLS3: invoke.cont7: 4531 // CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG191]] 4532 // CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) 4533 // CHECK-TLS3-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG193:![0-9]+]] 4534 // CHECK-TLS3: invoke.cont8: 4535 // CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG191]] 4536 // CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) 4537 // CHECK-TLS3-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG194:![0-9]+]] 4538 // CHECK-TLS3: invoke.cont9: 4539 // CHECK-TLS3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG195:![0-9]+]] 4540 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG195]] 4541 // CHECK-TLS3: lpad: 4542 // CHECK-TLS3-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } 4543 // CHECK-TLS3-NEXT: cleanup, !dbg [[DBG196:![0-9]+]] 4544 // CHECK-TLS3-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG196]] 4545 // CHECK-TLS3-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG196]] 4546 // CHECK-TLS3-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG196]] 4547 // CHECK-TLS3-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG196]] 4548 // CHECK-TLS3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG187]] 4549 // CHECK-TLS3-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG187]] 4550 // CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG187]] 4551 // CHECK-TLS3: arraydestroy.body: 4552 // CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG187]] 4553 // CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG187]] 4554 // CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG187]] 4555 // CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG187]] 4556 // CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG187]] 4557 // CHECK-TLS3: arraydestroy.done4: 4558 // CHECK-TLS3-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG187]] 4559 // CHECK-TLS3: lpad6: 4560 // CHECK-TLS3-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } 4561 // CHECK-TLS3-NEXT: cleanup, !dbg [[DBG196]] 4562 // CHECK-TLS3-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG196]] 4563 // CHECK-TLS3-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG196]] 4564 // CHECK-TLS3-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG196]] 4565 // CHECK-TLS3-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG196]] 4566 // CHECK-TLS3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG191]] 4567 // CHECK-TLS3-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG191]] 4568 // CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG191]] 4569 // CHECK-TLS3: arraydestroy.body11: 4570 // CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG191]] 4571 // CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG191]] 4572 // CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG191]] 4573 // CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG191]] 4574 // CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG191]] 4575 // CHECK-TLS3: arraydestroy.done15: 4576 // CHECK-TLS3-NEXT: br label [[EHCLEANUP]], !dbg [[DBG191]] 4577 // CHECK-TLS3: ehcleanup: 4578 // CHECK-TLS3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG185]] 4579 // CHECK-TLS3-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG185]] 4580 // CHECK-TLS3-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG185]] 4581 // CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG185]] 4582 // CHECK-TLS3: arraydestroy.body17: 4583 // CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG185]] 4584 // CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG185]] 4585 // CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG185]] 4586 // CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG185]] 4587 // CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG185]] 4588 // CHECK-TLS3: arraydestroy.done21: 4589 // CHECK-TLS3-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG185]] 4590 // CHECK-TLS3: eh.resume: 4591 // CHECK-TLS3-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG185]] 4592 // CHECK-TLS3-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG185]] 4593 // CHECK-TLS3-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG185]] 4594 // CHECK-TLS3-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG185]] 4595 // CHECK-TLS3-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG185]] 4596 // 4597 // 4598 // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 4599 // CHECK-TLS3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG197:![0-9]+]] { 4600 // CHECK-TLS3-NEXT: entry: 4601 // CHECK-TLS3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 4602 // CHECK-TLS3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 4603 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META201:![0-9]+]], !DIExpression(), [[META202:![0-9]+]]) 4604 // CHECK-TLS3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META202]] 4605 // CHECK-TLS3: arraydestroy.body: 4606 // CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META202]] 4607 // CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META202]] 4608 // CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META202]] 4609 // CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[META202]] 4610 // CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META202]] 4611 // CHECK-TLS3: arraydestroy.done1: 4612 // CHECK-TLS3-NEXT: ret void, !dbg [[META202]] 4613 // 4614 // 4615 // CHECK-TLS3-LABEL: define {{[^@]+}}@main 4616 // CHECK-TLS3-SAME: () #[[ATTR4:[0-9]+]] !dbg [[DBG52:![0-9]+]] { 4617 // CHECK-TLS3-NEXT: entry: 4618 // CHECK-TLS3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4619 // CHECK-TLS3-NEXT: [[RES:%.*]] = alloca i32, align 4 4620 // CHECK-TLS3-NEXT: store i32 0, ptr [[RETVAL]], align 4 4621 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[RES]], [[META203:![0-9]+]], !DIExpression(), [[META204:![0-9]+]]) 4622 // CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVZ4mainE2sm, align 1, !dbg [[DBG205:![0-9]+]] 4623 // CHECK-TLS3-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG205]] 4624 // CHECK-TLS3-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG205]], !prof [[PROF206:![0-9]+]] 4625 // CHECK-TLS3: init.check: 4626 // CHECK-TLS3-NEXT: [[TMP1:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG207:![0-9]+]] 4627 // CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG208:![0-9]+]] 4628 // CHECK-TLS3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG208]] 4629 // CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]]), !dbg [[DBG209:![0-9]+]] 4630 // CHECK-TLS3-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG205]] 4631 // CHECK-TLS3-NEXT: store i8 1, ptr @_ZGVZ4mainE2sm, align 1, !dbg [[DBG205]] 4632 // CHECK-TLS3-NEXT: br label [[INIT_END]], !dbg [[DBG205]] 4633 // CHECK-TLS3: init.end: 4634 // CHECK-TLS3-NEXT: [[TMP4:%.*]] = call ptr @_ZTWN6Static1sE(), !dbg [[DBG210:![0-9]+]] 4635 // CHECK-TLS3-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG211:![0-9]+]] 4636 // CHECK-TLS3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG211]] 4637 // CHECK-TLS3-NEXT: store i32 [[TMP5]], ptr [[RES]], align 4, !dbg [[DBG212:![0-9]+]] 4638 // CHECK-TLS3-NEXT: [[TMP6:%.*]] = call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @_ZZ4mainE2sm), !dbg [[DBG213:![0-9]+]] 4639 // CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[TMP6]], i32 0, i32 0, !dbg [[DBG214:![0-9]+]] 4640 // CHECK-TLS3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG214]] 4641 // CHECK-TLS3-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG215:![0-9]+]] 4642 // CHECK-TLS3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG215]] 4643 // CHECK-TLS3-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG215]] 4644 // CHECK-TLS3-NEXT: [[TMP9:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG216:![0-9]+]] 4645 // CHECK-TLS3-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG217:![0-9]+]] 4646 // CHECK-TLS3-NEXT: [[TMP10:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG217]] 4647 // CHECK-TLS3-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG218:![0-9]+]] 4648 // CHECK-TLS3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG218]] 4649 // CHECK-TLS3-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG218]] 4650 // CHECK-TLS3-NEXT: [[TMP12:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG219:![0-9]+]] 4651 // CHECK-TLS3-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG220:![0-9]+]] 4652 // CHECK-TLS3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG220]] 4653 // CHECK-TLS3-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG220]] 4654 // CHECK-TLS3-NEXT: [[TMP14:%.*]] = call ptr @_ZTW3gs3(), !dbg [[DBG221:![0-9]+]] 4655 // CHECK-TLS3-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP14]], i32 0, i32 0, !dbg [[DBG222:![0-9]+]] 4656 // CHECK-TLS3-NEXT: [[TMP15:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG222]] 4657 // CHECK-TLS3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG223:![0-9]+]] 4658 // CHECK-TLS3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG223]] 4659 // CHECK-TLS3-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG223]] 4660 // CHECK-TLS3-NEXT: [[TMP17:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG224:![0-9]+]] 4661 // CHECK-TLS3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], i64 0, i64 1, !dbg [[DBG224]] 4662 // CHECK-TLS3-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG224]] 4663 // CHECK-TLS3-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG225:![0-9]+]] 4664 // CHECK-TLS3-NEXT: [[TMP18:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG225]] 4665 // CHECK-TLS3-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG226:![0-9]+]] 4666 // CHECK-TLS3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG226]] 4667 // CHECK-TLS3-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG226]] 4668 // CHECK-TLS3-NEXT: [[TMP20:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE), !dbg [[DBG227:![0-9]+]] 4669 // CHECK-TLS3-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4, !dbg [[DBG227]] 4670 // CHECK-TLS3-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG228:![0-9]+]] 4671 // CHECK-TLS3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG228]] 4672 // CHECK-TLS3-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG228]] 4673 // CHECK-TLS3-NEXT: [[TMP23:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE), !dbg [[DBG229:![0-9]+]] 4674 // CHECK-TLS3-NEXT: [[TMP24:%.*]] = load float, ptr [[TMP23]], align 4, !dbg [[DBG229]] 4675 // CHECK-TLS3-NEXT: [[CONV:%.*]] = fptosi float [[TMP24]] to i32, !dbg [[DBG229]] 4676 // CHECK-TLS3-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG230:![0-9]+]] 4677 // CHECK-TLS3-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP25]], [[CONV]], !dbg [[DBG230]] 4678 // CHECK-TLS3-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG230]] 4679 // CHECK-TLS3-NEXT: [[TMP26:%.*]] = call ptr @_ZTWN2STI2S4E2stE(), !dbg [[DBG231:![0-9]+]] 4680 // CHECK-TLS3-NEXT: [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP26]], i32 0, i32 0, !dbg [[DBG232:![0-9]+]] 4681 // CHECK-TLS3-NEXT: [[TMP27:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG232]] 4682 // CHECK-TLS3-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG233:![0-9]+]] 4683 // CHECK-TLS3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], [[TMP27]], !dbg [[DBG233]] 4684 // CHECK-TLS3-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG233]] 4685 // CHECK-TLS3-NEXT: [[TMP29:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG234:![0-9]+]] 4686 // CHECK-TLS3-NEXT: ret i32 [[TMP29]], !dbg [[DBG235:![0-9]+]] 4687 // 4688 // 4689 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZTWL3gs1 4690 // CHECK-TLS3-SAME: () #[[ATTR5:[0-9]+]] { 4691 // CHECK-TLS3-NEXT: call void @_ZTHL3gs1() 4692 // CHECK-TLS3-NEXT: [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZL3gs1) 4693 // CHECK-TLS3-NEXT: ret ptr [[TMP1]] 4694 // 4695 // 4696 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei 4697 // CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG236:![0-9]+]] { 4698 // CHECK-TLS3-NEXT: entry: 4699 // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4700 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4701 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4702 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META237:![0-9]+]], !DIExpression(), [[META239:![0-9]+]]) 4703 // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4704 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META240:![0-9]+]], !DIExpression(), [[META241:![0-9]+]]) 4705 // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4706 // CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG242:![0-9]+]] 4707 // CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG242]] 4708 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG243:![0-9]+]] 4709 // 4710 // 4711 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev 4712 // CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG244:![0-9]+]] { 4713 // CHECK-TLS3-NEXT: entry: 4714 // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4715 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4716 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META245:![0-9]+]], !DIExpression(), [[META246:![0-9]+]]) 4717 // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4718 // CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG247:![0-9]+]] 4719 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG248:![0-9]+]] 4720 // 4721 // 4722 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZTWN6Static1sE 4723 // CHECK-TLS3-SAME: () #[[ATTR5]] comdat { 4724 // CHECK-TLS3-NEXT: [[TMP1:%.*]] = icmp ne ptr @_ZTHN6Static1sE, null 4725 // CHECK-TLS3-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP3:%.*]] 4726 // CHECK-TLS3: 2: 4727 // CHECK-TLS3-NEXT: call void @_ZTHN6Static1sE() 4728 // CHECK-TLS3-NEXT: br label [[TMP3]] 4729 // CHECK-TLS3: 3: 4730 // CHECK-TLS3-NEXT: [[TMP4:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN6Static1sE) 4731 // CHECK-TLS3-NEXT: ret ptr [[TMP4]] 4732 // 4733 // 4734 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZTW3gs3 4735 // CHECK-TLS3-SAME: () #[[ATTR5]] comdat { 4736 // CHECK-TLS3-NEXT: [[TMP1:%.*]] = icmp ne ptr @_ZTH3gs3, null 4737 // CHECK-TLS3-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP3:%.*]] 4738 // CHECK-TLS3: 2: 4739 // CHECK-TLS3-NEXT: call void @_ZTH3gs3() 4740 // CHECK-TLS3-NEXT: br label [[TMP3]] 4741 // CHECK-TLS3: 3: 4742 // CHECK-TLS3-NEXT: [[TMP4:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @gs3) 4743 // CHECK-TLS3-NEXT: ret ptr [[TMP4]] 4744 // 4745 // 4746 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZTW5arr_x 4747 // CHECK-TLS3-SAME: () #[[ATTR5]] comdat { 4748 // CHECK-TLS3-NEXT: call void @_ZTH5arr_x() 4749 // CHECK-TLS3-NEXT: [[TMP1:%.*]] = call align 16 ptr @llvm.threadlocal.address.p0(ptr align 16 @arr_x) 4750 // CHECK-TLS3-NEXT: ret ptr [[TMP1]] 4751 // 4752 // 4753 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZTWN2STI2S4E2stE 4754 // CHECK-TLS3-SAME: () #[[ATTR5]] comdat { 4755 // CHECK-TLS3-NEXT: call void @_ZTHN2STI2S4E2stE() 4756 // CHECK-TLS3-NEXT: [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STI2S4E2stE) 4757 // CHECK-TLS3-NEXT: ret ptr [[TMP1]] 4758 // 4759 // 4760 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei 4761 // CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG249:![0-9]+]] { 4762 // CHECK-TLS3-NEXT: entry: 4763 // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4764 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4765 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4766 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META250:![0-9]+]], !DIExpression(), [[META251:![0-9]+]]) 4767 // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4768 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META252:![0-9]+]], !DIExpression(), [[META253:![0-9]+]]) 4769 // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4770 // CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG254:![0-9]+]] 4771 // CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG255:![0-9]+]] 4772 // CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG254]] 4773 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG256:![0-9]+]] 4774 // 4775 // 4776 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev 4777 // CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG257:![0-9]+]] { 4778 // CHECK-TLS3-NEXT: entry: 4779 // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4780 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4781 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META258:![0-9]+]], !DIExpression(), [[META259:![0-9]+]]) 4782 // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4783 // CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG260:![0-9]+]] 4784 // CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG262:![0-9]+]] 4785 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG263:![0-9]+]] 4786 // 4787 // 4788 // CHECK-TLS3-LABEL: define {{[^@]+}}@_Z6foobarv 4789 // CHECK-TLS3-SAME: () #[[ATTR1]] !dbg [[DBG264:![0-9]+]] { 4790 // CHECK-TLS3-NEXT: entry: 4791 // CHECK-TLS3-NEXT: [[RES:%.*]] = alloca i32, align 4 4792 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[RES]], [[META265:![0-9]+]], !DIExpression(), [[META266:![0-9]+]]) 4793 // CHECK-TLS3-NEXT: [[TMP0:%.*]] = call ptr @_ZTWN6Static1sE(), !dbg [[DBG267:![0-9]+]] 4794 // CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG268:![0-9]+]] 4795 // CHECK-TLS3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG268]] 4796 // CHECK-TLS3-NEXT: store i32 [[TMP1]], ptr [[RES]], align 4, !dbg [[DBG269:![0-9]+]] 4797 // CHECK-TLS3-NEXT: [[TMP2:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG270:![0-9]+]] 4798 // CHECK-TLS3-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0, !dbg [[DBG271:![0-9]+]] 4799 // CHECK-TLS3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG271]] 4800 // CHECK-TLS3-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG272:![0-9]+]] 4801 // CHECK-TLS3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG272]] 4802 // CHECK-TLS3-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG272]] 4803 // CHECK-TLS3-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG273:![0-9]+]] 4804 // CHECK-TLS3-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG274:![0-9]+]] 4805 // CHECK-TLS3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG274]] 4806 // CHECK-TLS3-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG274]] 4807 // CHECK-TLS3-NEXT: [[TMP7:%.*]] = call ptr @_ZTW3gs3(), !dbg [[DBG275:![0-9]+]] 4808 // CHECK-TLS3-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG276:![0-9]+]] 4809 // CHECK-TLS3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG276]] 4810 // CHECK-TLS3-NEXT: [[TMP9:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG277:![0-9]+]] 4811 // CHECK-TLS3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]], !dbg [[DBG277]] 4812 // CHECK-TLS3-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG277]] 4813 // CHECK-TLS3-NEXT: [[TMP10:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG278:![0-9]+]] 4814 // CHECK-TLS3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], i64 0, i64 1, !dbg [[DBG278]] 4815 // CHECK-TLS3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG278]] 4816 // CHECK-TLS3-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG279:![0-9]+]] 4817 // CHECK-TLS3-NEXT: [[TMP11:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG279]] 4818 // CHECK-TLS3-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG280:![0-9]+]] 4819 // CHECK-TLS3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG280]] 4820 // CHECK-TLS3-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG280]] 4821 // CHECK-TLS3-NEXT: [[TMP13:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE), !dbg [[DBG281:![0-9]+]] 4822 // CHECK-TLS3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG281]] 4823 // CHECK-TLS3-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG282:![0-9]+]] 4824 // CHECK-TLS3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], [[TMP14]], !dbg [[DBG282]] 4825 // CHECK-TLS3-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG282]] 4826 // CHECK-TLS3-NEXT: [[TMP16:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE), !dbg [[DBG283:![0-9]+]] 4827 // CHECK-TLS3-NEXT: [[TMP17:%.*]] = load float, ptr [[TMP16]], align 4, !dbg [[DBG283]] 4828 // CHECK-TLS3-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG283]] 4829 // CHECK-TLS3-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG284:![0-9]+]] 4830 // CHECK-TLS3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG284]] 4831 // CHECK-TLS3-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG284]] 4832 // CHECK-TLS3-NEXT: [[TMP19:%.*]] = call ptr @_ZTWN2STI2S4E2stE(), !dbg [[DBG285:![0-9]+]] 4833 // CHECK-TLS3-NEXT: [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP19]], i32 0, i32 0, !dbg [[DBG286:![0-9]+]] 4834 // CHECK-TLS3-NEXT: [[TMP20:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG286]] 4835 // CHECK-TLS3-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG287:![0-9]+]] 4836 // CHECK-TLS3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], [[TMP20]], !dbg [[DBG287]] 4837 // CHECK-TLS3-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG287]] 4838 // CHECK-TLS3-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG288:![0-9]+]] 4839 // CHECK-TLS3-NEXT: ret i32 [[TMP22]], !dbg [[DBG289:![0-9]+]] 4840 // 4841 // 4842 // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 4843 // CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG290:![0-9]+]] { 4844 // CHECK-TLS3-NEXT: entry: 4845 // CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG291:![0-9]+]] 4846 // CHECK-TLS3-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG291]] 4847 // CHECK-TLS3-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG291]] 4848 // CHECK-TLS3: init.check: 4849 // CHECK-TLS3-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG291]] 4850 // CHECK-TLS3-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG292:![0-9]+]] 4851 // CHECK-TLS3-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG291]] 4852 // CHECK-TLS3-NEXT: br label [[INIT_END]], !dbg [[DBG291]] 4853 // CHECK-TLS3: init.end: 4854 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG294:![0-9]+]] 4855 // 4856 // 4857 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4C1Ei 4858 // CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG295:![0-9]+]] { 4859 // CHECK-TLS3-NEXT: entry: 4860 // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4861 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4862 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4863 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META296:![0-9]+]], !DIExpression(), [[META298:![0-9]+]]) 4864 // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4865 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META299:![0-9]+]], !DIExpression(), [[META300:![0-9]+]]) 4866 // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4867 // CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG301:![0-9]+]] 4868 // CHECK-TLS3-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG301]] 4869 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG302:![0-9]+]] 4870 // 4871 // 4872 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4D1Ev 4873 // CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG303:![0-9]+]] { 4874 // CHECK-TLS3-NEXT: entry: 4875 // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4876 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4877 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META304:![0-9]+]], !DIExpression(), [[META305:![0-9]+]]) 4878 // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4879 // CHECK-TLS3-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG306:![0-9]+]] 4880 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG307:![0-9]+]] 4881 // 4882 // 4883 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4C2Ei 4884 // CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG308:![0-9]+]] { 4885 // CHECK-TLS3-NEXT: entry: 4886 // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4887 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4888 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4889 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META309:![0-9]+]], !DIExpression(), [[META310:![0-9]+]]) 4890 // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4891 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META311:![0-9]+]], !DIExpression(), [[META312:![0-9]+]]) 4892 // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4893 // CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG313:![0-9]+]] 4894 // CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG314:![0-9]+]] 4895 // CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG313]] 4896 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG315:![0-9]+]] 4897 // 4898 // 4899 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4D2Ev 4900 // CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG316:![0-9]+]] { 4901 // CHECK-TLS3-NEXT: entry: 4902 // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4903 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4904 // CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META317:![0-9]+]], !DIExpression(), [[META318:![0-9]+]]) 4905 // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4906 // CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG319:![0-9]+]] 4907 // CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG321:![0-9]+]] 4908 // CHECK-TLS3-NEXT: ret void, !dbg [[DBG322:![0-9]+]] 4909 // 4910 // 4911 // CHECK-TLS3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp 4912 // CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG323:![0-9]+]] { 4913 // CHECK-TLS3-NEXT: entry: 4914 // CHECK-TLS3-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG325:![0-9]+]] 4915 // CHECK-TLS3-NEXT: ret void 4916 // 4917 // 4918 // CHECK-TLS3-LABEL: define {{[^@]+}}@__tls_init 4919 // CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG326:![0-9]+]] { 4920 // CHECK-TLS3-NEXT: entry: 4921 // CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 1, !dbg [[DBG327:![0-9]+]] 4922 // CHECK-TLS3-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG327]] 4923 // CHECK-TLS3-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !dbg [[DBG327]], !prof [[PROF206]] 4924 // CHECK-TLS3: init: 4925 // CHECK-TLS3-NEXT: store i8 1, ptr @__tls_guard, align 1, !dbg [[DBG327]] 4926 // CHECK-TLS3-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG327]] 4927 // CHECK-TLS3-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG327]] 4928 // CHECK-TLS3-NEXT: br label [[EXIT]], !dbg [[DBG327]] 4929 // CHECK-TLS3: exit: 4930 // CHECK-TLS3-NEXT: ret void 4931 // 4932 // 4933 // CHECK-TLS4-LABEL: define {{[^@]+}}@main 4934 // CHECK-TLS4-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG9:![0-9]+]] { 4935 // CHECK-TLS4-NEXT: entry: 4936 // CHECK-TLS4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4937 // CHECK-TLS4-NEXT: [[RES:%.*]] = alloca i32, align 4 4938 // CHECK-TLS4-NEXT: store i32 0, ptr [[RETVAL]], align 4 4939 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[RES]], [[META116:![0-9]+]], !DIExpression(), [[META117:![0-9]+]]) 4940 // CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVZ4mainE2sm, align 1, !dbg [[DBG118:![0-9]+]] 4941 // CHECK-TLS4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG118]] 4942 // CHECK-TLS4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG118]], !prof [[PROF119:![0-9]+]] 4943 // CHECK-TLS4: init.check: 4944 // CHECK-TLS4-NEXT: [[TMP1:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG120:![0-9]+]] 4945 // CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG121:![0-9]+]] 4946 // CHECK-TLS4-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG121]] 4947 // CHECK-TLS4-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]]), !dbg [[DBG122:![0-9]+]] 4948 // CHECK-TLS4-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR4:[0-9]+]], !dbg [[DBG118]] 4949 // CHECK-TLS4-NEXT: store i8 1, ptr @_ZGVZ4mainE2sm, align 1, !dbg [[DBG118]] 4950 // CHECK-TLS4-NEXT: br label [[INIT_END]], !dbg [[DBG118]] 4951 // CHECK-TLS4: init.end: 4952 // CHECK-TLS4-NEXT: [[TMP4:%.*]] = call ptr @_ZTWN6Static1sE(), !dbg [[DBG123:![0-9]+]] 4953 // CHECK-TLS4-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG124:![0-9]+]] 4954 // CHECK-TLS4-NEXT: [[TMP5:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG124]] 4955 // CHECK-TLS4-NEXT: store i32 [[TMP5]], ptr [[RES]], align 4, !dbg [[DBG125:![0-9]+]] 4956 // CHECK-TLS4-NEXT: [[TMP6:%.*]] = call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @_ZZ4mainE2sm), !dbg [[DBG126:![0-9]+]] 4957 // CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[TMP6]], i32 0, i32 0, !dbg [[DBG127:![0-9]+]] 4958 // CHECK-TLS4-NEXT: [[TMP7:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG127]] 4959 // CHECK-TLS4-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG128:![0-9]+]] 4960 // CHECK-TLS4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG128]] 4961 // CHECK-TLS4-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG128]] 4962 // CHECK-TLS4-NEXT: [[TMP9:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG129:![0-9]+]] 4963 // CHECK-TLS4-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG130:![0-9]+]] 4964 // CHECK-TLS4-NEXT: [[TMP10:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG130]] 4965 // CHECK-TLS4-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG131:![0-9]+]] 4966 // CHECK-TLS4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG131]] 4967 // CHECK-TLS4-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG131]] 4968 // CHECK-TLS4-NEXT: [[TMP12:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG132:![0-9]+]] 4969 // CHECK-TLS4-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG133:![0-9]+]] 4970 // CHECK-TLS4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG133]] 4971 // CHECK-TLS4-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG133]] 4972 // CHECK-TLS4-NEXT: [[TMP14:%.*]] = call ptr @_ZTW3gs3(), !dbg [[DBG134:![0-9]+]] 4973 // CHECK-TLS4-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP14]], i32 0, i32 0, !dbg [[DBG135:![0-9]+]] 4974 // CHECK-TLS4-NEXT: [[TMP15:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG135]] 4975 // CHECK-TLS4-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG136:![0-9]+]] 4976 // CHECK-TLS4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG136]] 4977 // CHECK-TLS4-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG136]] 4978 // CHECK-TLS4-NEXT: [[TMP17:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG137:![0-9]+]] 4979 // CHECK-TLS4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], i64 0, i64 1, !dbg [[DBG137]] 4980 // CHECK-TLS4-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG137]] 4981 // CHECK-TLS4-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG138:![0-9]+]] 4982 // CHECK-TLS4-NEXT: [[TMP18:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG138]] 4983 // CHECK-TLS4-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG139:![0-9]+]] 4984 // CHECK-TLS4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG139]] 4985 // CHECK-TLS4-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG139]] 4986 // CHECK-TLS4-NEXT: [[TMP20:%.*]] = call ptr @_ZTWN2STIiE2stE(), !dbg [[DBG140:![0-9]+]] 4987 // CHECK-TLS4-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4, !dbg [[DBG140]] 4988 // CHECK-TLS4-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG141:![0-9]+]] 4989 // CHECK-TLS4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG141]] 4990 // CHECK-TLS4-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG141]] 4991 // CHECK-TLS4-NEXT: [[TMP23:%.*]] = call ptr @_ZTWN2STIfE2stE(), !dbg [[DBG142:![0-9]+]] 4992 // CHECK-TLS4-NEXT: [[TMP24:%.*]] = load float, ptr [[TMP23]], align 4, !dbg [[DBG142]] 4993 // CHECK-TLS4-NEXT: [[CONV:%.*]] = fptosi float [[TMP24]] to i32, !dbg [[DBG142]] 4994 // CHECK-TLS4-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG143:![0-9]+]] 4995 // CHECK-TLS4-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP25]], [[CONV]], !dbg [[DBG143]] 4996 // CHECK-TLS4-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG143]] 4997 // CHECK-TLS4-NEXT: [[TMP26:%.*]] = call ptr @_ZTWN2STI2S4E2stE(), !dbg [[DBG144:![0-9]+]] 4998 // CHECK-TLS4-NEXT: [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP26]], i32 0, i32 0, !dbg [[DBG145:![0-9]+]] 4999 // CHECK-TLS4-NEXT: [[TMP27:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG145]] 5000 // CHECK-TLS4-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG146:![0-9]+]] 5001 // CHECK-TLS4-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], [[TMP27]], !dbg [[DBG146]] 5002 // CHECK-TLS4-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG146]] 5003 // CHECK-TLS4-NEXT: [[TMP29:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG147:![0-9]+]] 5004 // CHECK-TLS4-NEXT: ret i32 [[TMP29]], !dbg [[DBG148:![0-9]+]] 5005 // 5006 // 5007 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZTWL3gs1 5008 // CHECK-TLS4-SAME: () #[[ATTR1:[0-9]+]] { 5009 // CHECK-TLS4-NEXT: call void @_ZTHL3gs1() 5010 // CHECK-TLS4-NEXT: [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZL3gs1) 5011 // CHECK-TLS4-NEXT: ret ptr [[TMP1]] 5012 // 5013 // 5014 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei 5015 // CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 !dbg [[DBG149:![0-9]+]] { 5016 // CHECK-TLS4-NEXT: entry: 5017 // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5018 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5019 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5020 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META150:![0-9]+]], !DIExpression(), [[META152:![0-9]+]]) 5021 // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5022 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META153:![0-9]+]], !DIExpression(), [[META154:![0-9]+]]) 5023 // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5024 // CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG155:![0-9]+]] 5025 // CHECK-TLS4-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG155]] 5026 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG156:![0-9]+]] 5027 // 5028 // 5029 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev 5030 // CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 !dbg [[DBG157:![0-9]+]] { 5031 // CHECK-TLS4-NEXT: entry: 5032 // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5033 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5034 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META158:![0-9]+]], !DIExpression(), [[META159:![0-9]+]]) 5035 // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5036 // CHECK-TLS4-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]], !dbg [[DBG160:![0-9]+]] 5037 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG161:![0-9]+]] 5038 // 5039 // 5040 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZTWN6Static1sE 5041 // CHECK-TLS4-SAME: () #[[ATTR1]] comdat { 5042 // CHECK-TLS4-NEXT: [[TMP1:%.*]] = icmp ne ptr @_ZTHN6Static1sE, null 5043 // CHECK-TLS4-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP3:%.*]] 5044 // CHECK-TLS4: 2: 5045 // CHECK-TLS4-NEXT: call void @_ZTHN6Static1sE() 5046 // CHECK-TLS4-NEXT: br label [[TMP3]] 5047 // CHECK-TLS4: 3: 5048 // CHECK-TLS4-NEXT: [[TMP4:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN6Static1sE) 5049 // CHECK-TLS4-NEXT: ret ptr [[TMP4]] 5050 // 5051 // 5052 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZTW3gs3 5053 // CHECK-TLS4-SAME: () #[[ATTR1]] comdat { 5054 // CHECK-TLS4-NEXT: [[TMP1:%.*]] = icmp ne ptr @_ZTH3gs3, null 5055 // CHECK-TLS4-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP3:%.*]] 5056 // CHECK-TLS4: 2: 5057 // CHECK-TLS4-NEXT: call void @_ZTH3gs3() 5058 // CHECK-TLS4-NEXT: br label [[TMP3]] 5059 // CHECK-TLS4: 3: 5060 // CHECK-TLS4-NEXT: [[TMP4:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @gs3) 5061 // CHECK-TLS4-NEXT: ret ptr [[TMP4]] 5062 // 5063 // 5064 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZTW5arr_x 5065 // CHECK-TLS4-SAME: () #[[ATTR1]] comdat { 5066 // CHECK-TLS4-NEXT: call void @_ZTH5arr_x() 5067 // CHECK-TLS4-NEXT: [[TMP1:%.*]] = call align 16 ptr @llvm.threadlocal.address.p0(ptr align 16 @arr_x) 5068 // CHECK-TLS4-NEXT: ret ptr [[TMP1]] 5069 // 5070 // 5071 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZTWN2STIiE2stE 5072 // CHECK-TLS4-SAME: () #[[ATTR1]] comdat { 5073 // CHECK-TLS4-NEXT: [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE) 5074 // CHECK-TLS4-NEXT: ret ptr [[TMP1]] 5075 // 5076 // 5077 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZTWN2STIfE2stE 5078 // CHECK-TLS4-SAME: () #[[ATTR1]] comdat { 5079 // CHECK-TLS4-NEXT: [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE) 5080 // CHECK-TLS4-NEXT: ret ptr [[TMP1]] 5081 // 5082 // 5083 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZTWN2STI2S4E2stE 5084 // CHECK-TLS4-SAME: () #[[ATTR1]] comdat { 5085 // CHECK-TLS4-NEXT: call void @_ZTHN2STI2S4E2stE() 5086 // CHECK-TLS4-NEXT: [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STI2S4E2stE) 5087 // CHECK-TLS4-NEXT: ret ptr [[TMP1]] 5088 // 5089 // 5090 // CHECK-TLS4-LABEL: define {{[^@]+}}@_Z6foobarv 5091 // CHECK-TLS4-SAME: () #[[ATTR2]] !dbg [[DBG162:![0-9]+]] { 5092 // CHECK-TLS4-NEXT: entry: 5093 // CHECK-TLS4-NEXT: [[RES:%.*]] = alloca i32, align 4 5094 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[RES]], [[META163:![0-9]+]], !DIExpression(), [[META164:![0-9]+]]) 5095 // CHECK-TLS4-NEXT: [[TMP0:%.*]] = call ptr @_ZTWN6Static1sE(), !dbg [[DBG165:![0-9]+]] 5096 // CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG166:![0-9]+]] 5097 // CHECK-TLS4-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG166]] 5098 // CHECK-TLS4-NEXT: store i32 [[TMP1]], ptr [[RES]], align 4, !dbg [[DBG167:![0-9]+]] 5099 // CHECK-TLS4-NEXT: [[TMP2:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG168:![0-9]+]] 5100 // CHECK-TLS4-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0, !dbg [[DBG169:![0-9]+]] 5101 // CHECK-TLS4-NEXT: [[TMP3:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG169]] 5102 // CHECK-TLS4-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG170:![0-9]+]] 5103 // CHECK-TLS4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG170]] 5104 // CHECK-TLS4-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG170]] 5105 // CHECK-TLS4-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG171:![0-9]+]] 5106 // CHECK-TLS4-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG172:![0-9]+]] 5107 // CHECK-TLS4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG172]] 5108 // CHECK-TLS4-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG172]] 5109 // CHECK-TLS4-NEXT: [[TMP7:%.*]] = call ptr @_ZTW3gs3(), !dbg [[DBG173:![0-9]+]] 5110 // CHECK-TLS4-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG174:![0-9]+]] 5111 // CHECK-TLS4-NEXT: [[TMP8:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG174]] 5112 // CHECK-TLS4-NEXT: [[TMP9:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG175:![0-9]+]] 5113 // CHECK-TLS4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]], !dbg [[DBG175]] 5114 // CHECK-TLS4-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG175]] 5115 // CHECK-TLS4-NEXT: [[TMP10:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG176:![0-9]+]] 5116 // CHECK-TLS4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], i64 0, i64 1, !dbg [[DBG176]] 5117 // CHECK-TLS4-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG176]] 5118 // CHECK-TLS4-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG177:![0-9]+]] 5119 // CHECK-TLS4-NEXT: [[TMP11:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG177]] 5120 // CHECK-TLS4-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG178:![0-9]+]] 5121 // CHECK-TLS4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG178]] 5122 // CHECK-TLS4-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG178]] 5123 // CHECK-TLS4-NEXT: [[TMP13:%.*]] = call ptr @_ZTWN2STIiE2stE(), !dbg [[DBG179:![0-9]+]] 5124 // CHECK-TLS4-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG179]] 5125 // CHECK-TLS4-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG180:![0-9]+]] 5126 // CHECK-TLS4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], [[TMP14]], !dbg [[DBG180]] 5127 // CHECK-TLS4-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG180]] 5128 // CHECK-TLS4-NEXT: [[TMP16:%.*]] = call ptr @_ZTWN2STIfE2stE(), !dbg [[DBG181:![0-9]+]] 5129 // CHECK-TLS4-NEXT: [[TMP17:%.*]] = load float, ptr [[TMP16]], align 4, !dbg [[DBG181]] 5130 // CHECK-TLS4-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG181]] 5131 // CHECK-TLS4-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG182:![0-9]+]] 5132 // CHECK-TLS4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG182]] 5133 // CHECK-TLS4-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG182]] 5134 // CHECK-TLS4-NEXT: [[TMP19:%.*]] = call ptr @_ZTWN2STI2S4E2stE(), !dbg [[DBG183:![0-9]+]] 5135 // CHECK-TLS4-NEXT: [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP19]], i32 0, i32 0, !dbg [[DBG184:![0-9]+]] 5136 // CHECK-TLS4-NEXT: [[TMP20:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG184]] 5137 // CHECK-TLS4-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG185:![0-9]+]] 5138 // CHECK-TLS4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], [[TMP20]], !dbg [[DBG185]] 5139 // CHECK-TLS4-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG185]] 5140 // CHECK-TLS4-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG186:![0-9]+]] 5141 // CHECK-TLS4-NEXT: ret i32 [[TMP22]], !dbg [[DBG187:![0-9]+]] 5142 // 5143 // 5144 // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_var_init 5145 // CHECK-TLS4-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG188:![0-9]+]] { 5146 // CHECK-TLS4-NEXT: entry: 5147 // CHECK-TLS4-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG191:![0-9]+]] 5148 // CHECK-TLS4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG193:![0-9]+]] 5149 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG194:![0-9]+]] 5150 // 5151 // 5152 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1C1Ei 5153 // CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG195:![0-9]+]] { 5154 // CHECK-TLS4-NEXT: entry: 5155 // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5156 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5157 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5158 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META196:![0-9]+]], !DIExpression(), [[META198:![0-9]+]]) 5159 // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5160 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META199:![0-9]+]], !DIExpression(), [[META200:![0-9]+]]) 5161 // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5162 // CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG201:![0-9]+]] 5163 // CHECK-TLS4-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG201]] 5164 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG202:![0-9]+]] 5165 // 5166 // 5167 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1D1Ev 5168 // CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG203:![0-9]+]] { 5169 // CHECK-TLS4-NEXT: entry: 5170 // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5171 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5172 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META204:![0-9]+]], !DIExpression(), [[META205:![0-9]+]]) 5173 // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5174 // CHECK-TLS4-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]], !dbg [[DBG206:![0-9]+]] 5175 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG207:![0-9]+]] 5176 // 5177 // 5178 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1C2Ei 5179 // CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG208:![0-9]+]] { 5180 // CHECK-TLS4-NEXT: entry: 5181 // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5182 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5183 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5184 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META209:![0-9]+]], !DIExpression(), [[META210:![0-9]+]]) 5185 // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5186 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META211:![0-9]+]], !DIExpression(), [[META212:![0-9]+]]) 5187 // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5188 // CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG213:![0-9]+]] 5189 // CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG214:![0-9]+]] 5190 // CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG213]] 5191 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG215:![0-9]+]] 5192 // 5193 // 5194 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1D2Ev 5195 // CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG216:![0-9]+]] { 5196 // CHECK-TLS4-NEXT: entry: 5197 // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5198 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5199 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META217:![0-9]+]], !DIExpression(), [[META218:![0-9]+]]) 5200 // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5201 // CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG219:![0-9]+]] 5202 // CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG221:![0-9]+]] 5203 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG222:![0-9]+]] 5204 // 5205 // 5206 // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 5207 // CHECK-TLS4-SAME: () #[[ATTR6]] !dbg [[DBG223:![0-9]+]] { 5208 // CHECK-TLS4-NEXT: entry: 5209 // CHECK-TLS4-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG224:![0-9]+]] 5210 // CHECK-TLS4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG226:![0-9]+]] 5211 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG227:![0-9]+]] 5212 // 5213 // 5214 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2C1Ei 5215 // CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG228:![0-9]+]] { 5216 // CHECK-TLS4-NEXT: entry: 5217 // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5218 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5219 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5220 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META229:![0-9]+]], !DIExpression(), [[META231:![0-9]+]]) 5221 // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5222 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META232:![0-9]+]], !DIExpression(), [[META233:![0-9]+]]) 5223 // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5224 // CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG234:![0-9]+]] 5225 // CHECK-TLS4-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG234]] 5226 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG235:![0-9]+]] 5227 // 5228 // 5229 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2D1Ev 5230 // CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG236:![0-9]+]] { 5231 // CHECK-TLS4-NEXT: entry: 5232 // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5233 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5234 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META237:![0-9]+]], !DIExpression(), [[META238:![0-9]+]]) 5235 // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5236 // CHECK-TLS4-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR4]], !dbg [[DBG239:![0-9]+]] 5237 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG240:![0-9]+]] 5238 // 5239 // 5240 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2C2Ei 5241 // CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG241:![0-9]+]] { 5242 // CHECK-TLS4-NEXT: entry: 5243 // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5244 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5245 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5246 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META242:![0-9]+]], !DIExpression(), [[META243:![0-9]+]]) 5247 // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5248 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META244:![0-9]+]], !DIExpression(), [[META245:![0-9]+]]) 5249 // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5250 // CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG246:![0-9]+]] 5251 // CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG247:![0-9]+]] 5252 // CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG246]] 5253 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG248:![0-9]+]] 5254 // 5255 // 5256 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2D2Ev 5257 // CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG249:![0-9]+]] { 5258 // CHECK-TLS4-NEXT: entry: 5259 // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5260 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5261 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META250:![0-9]+]], !DIExpression(), [[META251:![0-9]+]]) 5262 // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5263 // CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG252:![0-9]+]] 5264 // CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG254:![0-9]+]] 5265 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG255:![0-9]+]] 5266 // 5267 // 5268 // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 5269 // CHECK-TLS4-SAME: () #[[ATTR6]] personality ptr @__gxx_personality_v0 !dbg [[DBG256:![0-9]+]] { 5270 // CHECK-TLS4-NEXT: entry: 5271 // CHECK-TLS4-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 5272 // CHECK-TLS4-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 5273 // CHECK-TLS4-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 5274 // CHECK-TLS4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 5275 // CHECK-TLS4-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 5276 // CHECK-TLS4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG257:![0-9]+]] 5277 // CHECK-TLS4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG259:![0-9]+]] 5278 // CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) 5279 // CHECK-TLS4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG260:![0-9]+]] 5280 // CHECK-TLS4: invoke.cont: 5281 // CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG259]] 5282 // CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) 5283 // CHECK-TLS4-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG261:![0-9]+]] 5284 // CHECK-TLS4: invoke.cont2: 5285 // CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG259]] 5286 // CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) 5287 // CHECK-TLS4-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG262:![0-9]+]] 5288 // CHECK-TLS4: invoke.cont3: 5289 // CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG257]] 5290 // CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG263:![0-9]+]] 5291 // CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) 5292 // CHECK-TLS4-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG264:![0-9]+]] 5293 // CHECK-TLS4: invoke.cont7: 5294 // CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG263]] 5295 // CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) 5296 // CHECK-TLS4-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG265:![0-9]+]] 5297 // CHECK-TLS4: invoke.cont8: 5298 // CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG263]] 5299 // CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) 5300 // CHECK-TLS4-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG266:![0-9]+]] 5301 // CHECK-TLS4: invoke.cont9: 5302 // CHECK-TLS4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG267:![0-9]+]] 5303 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG267]] 5304 // CHECK-TLS4: lpad: 5305 // CHECK-TLS4-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } 5306 // CHECK-TLS4-NEXT: cleanup, !dbg [[DBG268:![0-9]+]] 5307 // CHECK-TLS4-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG268]] 5308 // CHECK-TLS4-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG268]] 5309 // CHECK-TLS4-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG268]] 5310 // CHECK-TLS4-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG268]] 5311 // CHECK-TLS4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG259]] 5312 // CHECK-TLS4-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG259]] 5313 // CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG259]] 5314 // CHECK-TLS4: arraydestroy.body: 5315 // CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG259]] 5316 // CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG259]] 5317 // CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG259]] 5318 // CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG259]] 5319 // CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG259]] 5320 // CHECK-TLS4: arraydestroy.done4: 5321 // CHECK-TLS4-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG259]] 5322 // CHECK-TLS4: lpad6: 5323 // CHECK-TLS4-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } 5324 // CHECK-TLS4-NEXT: cleanup, !dbg [[DBG268]] 5325 // CHECK-TLS4-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG268]] 5326 // CHECK-TLS4-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG268]] 5327 // CHECK-TLS4-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG268]] 5328 // CHECK-TLS4-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG268]] 5329 // CHECK-TLS4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG263]] 5330 // CHECK-TLS4-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG263]] 5331 // CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG263]] 5332 // CHECK-TLS4: arraydestroy.body11: 5333 // CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG263]] 5334 // CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG263]] 5335 // CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR4]], !dbg [[DBG263]] 5336 // CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG263]] 5337 // CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG263]] 5338 // CHECK-TLS4: arraydestroy.done15: 5339 // CHECK-TLS4-NEXT: br label [[EHCLEANUP]], !dbg [[DBG263]] 5340 // CHECK-TLS4: ehcleanup: 5341 // CHECK-TLS4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG257]] 5342 // CHECK-TLS4-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG257]] 5343 // CHECK-TLS4-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG257]] 5344 // CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG257]] 5345 // CHECK-TLS4: arraydestroy.body17: 5346 // CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG257]] 5347 // CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG257]] 5348 // CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG257]] 5349 // CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG257]] 5350 // CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG257]] 5351 // CHECK-TLS4: arraydestroy.done21: 5352 // CHECK-TLS4-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG257]] 5353 // CHECK-TLS4: eh.resume: 5354 // CHECK-TLS4-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG257]] 5355 // CHECK-TLS4-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG257]] 5356 // CHECK-TLS4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG257]] 5357 // CHECK-TLS4-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG257]] 5358 // CHECK-TLS4-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG257]] 5359 // 5360 // 5361 // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 5362 // CHECK-TLS4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR6]] !dbg [[DBG269:![0-9]+]] { 5363 // CHECK-TLS4-NEXT: entry: 5364 // CHECK-TLS4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 5365 // CHECK-TLS4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 5366 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META273:![0-9]+]], !DIExpression(), [[META274:![0-9]+]]) 5367 // CHECK-TLS4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META274]] 5368 // CHECK-TLS4: arraydestroy.body: 5369 // CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META274]] 5370 // CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META274]] 5371 // CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[META274]] 5372 // CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[META274]] 5373 // CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META274]] 5374 // CHECK-TLS4: arraydestroy.done1: 5375 // CHECK-TLS4-NEXT: ret void, !dbg [[META274]] 5376 // 5377 // 5378 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei 5379 // CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG275:![0-9]+]] { 5380 // CHECK-TLS4-NEXT: entry: 5381 // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5382 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5383 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5384 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META276:![0-9]+]], !DIExpression(), [[META277:![0-9]+]]) 5385 // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5386 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META278:![0-9]+]], !DIExpression(), [[META279:![0-9]+]]) 5387 // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5388 // CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG280:![0-9]+]] 5389 // CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG281:![0-9]+]] 5390 // CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG280]] 5391 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG282:![0-9]+]] 5392 // 5393 // 5394 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev 5395 // CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG283:![0-9]+]] { 5396 // CHECK-TLS4-NEXT: entry: 5397 // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5398 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5399 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META284:![0-9]+]], !DIExpression(), [[META285:![0-9]+]]) 5400 // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5401 // CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG286:![0-9]+]] 5402 // CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG288:![0-9]+]] 5403 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG289:![0-9]+]] 5404 // 5405 // 5406 // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 5407 // CHECK-TLS4-SAME: () #[[ATTR6]] !dbg [[DBG290:![0-9]+]] { 5408 // CHECK-TLS4-NEXT: entry: 5409 // CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG291:![0-9]+]] 5410 // CHECK-TLS4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG291]] 5411 // CHECK-TLS4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG291]] 5412 // CHECK-TLS4: init.check: 5413 // CHECK-TLS4-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG291]] 5414 // CHECK-TLS4-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG292:![0-9]+]] 5415 // CHECK-TLS4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG291]] 5416 // CHECK-TLS4-NEXT: br label [[INIT_END]], !dbg [[DBG291]] 5417 // CHECK-TLS4: init.end: 5418 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG294:![0-9]+]] 5419 // 5420 // 5421 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4C1Ei 5422 // CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG295:![0-9]+]] { 5423 // CHECK-TLS4-NEXT: entry: 5424 // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5425 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5426 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5427 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META296:![0-9]+]], !DIExpression(), [[META298:![0-9]+]]) 5428 // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5429 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META299:![0-9]+]], !DIExpression(), [[META300:![0-9]+]]) 5430 // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5431 // CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG301:![0-9]+]] 5432 // CHECK-TLS4-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG301]] 5433 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG302:![0-9]+]] 5434 // 5435 // 5436 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4D1Ev 5437 // CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG303:![0-9]+]] { 5438 // CHECK-TLS4-NEXT: entry: 5439 // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5440 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5441 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META304:![0-9]+]], !DIExpression(), [[META305:![0-9]+]]) 5442 // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5443 // CHECK-TLS4-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]], !dbg [[DBG306:![0-9]+]] 5444 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG307:![0-9]+]] 5445 // 5446 // 5447 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4C2Ei 5448 // CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG308:![0-9]+]] { 5449 // CHECK-TLS4-NEXT: entry: 5450 // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5451 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5452 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5453 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META309:![0-9]+]], !DIExpression(), [[META310:![0-9]+]]) 5454 // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5455 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META311:![0-9]+]], !DIExpression(), [[META312:![0-9]+]]) 5456 // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5457 // CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG313:![0-9]+]] 5458 // CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG314:![0-9]+]] 5459 // CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG313]] 5460 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG315:![0-9]+]] 5461 // 5462 // 5463 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4D2Ev 5464 // CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG316:![0-9]+]] { 5465 // CHECK-TLS4-NEXT: entry: 5466 // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5467 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5468 // CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META317:![0-9]+]], !DIExpression(), [[META318:![0-9]+]]) 5469 // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5470 // CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG319:![0-9]+]] 5471 // CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG321:![0-9]+]] 5472 // CHECK-TLS4-NEXT: ret void, !dbg [[DBG322:![0-9]+]] 5473 // 5474 // 5475 // CHECK-TLS4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp 5476 // CHECK-TLS4-SAME: () #[[ATTR6]] !dbg [[DBG323:![0-9]+]] { 5477 // CHECK-TLS4-NEXT: entry: 5478 // CHECK-TLS4-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG325:![0-9]+]] 5479 // CHECK-TLS4-NEXT: ret void 5480 // 5481 // 5482 // CHECK-TLS4-LABEL: define {{[^@]+}}@__tls_init 5483 // CHECK-TLS4-SAME: () #[[ATTR6]] !dbg [[DBG326:![0-9]+]] { 5484 // CHECK-TLS4-NEXT: entry: 5485 // CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 1, !dbg [[DBG327:![0-9]+]] 5486 // CHECK-TLS4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG327]] 5487 // CHECK-TLS4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !dbg [[DBG327]], !prof [[PROF119]] 5488 // CHECK-TLS4: init: 5489 // CHECK-TLS4-NEXT: store i8 1, ptr @__tls_guard, align 1, !dbg [[DBG327]] 5490 // CHECK-TLS4-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG327]] 5491 // CHECK-TLS4-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG327]] 5492 // CHECK-TLS4-NEXT: br label [[EXIT]], !dbg [[DBG327]] 5493 // CHECK-TLS4: exit: 5494 // CHECK-TLS4-NEXT: ret void 5495 // 5496 // 5497 // SIMD3-LABEL: define {{[^@]+}}@__cxx_global_var_init 5498 // SIMD3-SAME: () #[[ATTR0:[0-9]+]] { 5499 // SIMD3-NEXT: entry: 5500 // SIMD3-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5) 5501 // SIMD3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]] 5502 // SIMD3-NEXT: ret void 5503 // 5504 // 5505 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S1C1Ei 5506 // SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 5507 // SIMD3-NEXT: entry: 5508 // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5509 // SIMD3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5510 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5511 // SIMD3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5512 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5513 // SIMD3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 5514 // SIMD3-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 5515 // SIMD3-NEXT: ret void 5516 // 5517 // 5518 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S1D1Ev 5519 // SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { 5520 // SIMD3-NEXT: entry: 5521 // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5522 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5523 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5524 // SIMD3-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] 5525 // SIMD3-NEXT: ret void 5526 // 5527 // 5528 // SIMD3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 5529 // SIMD3-SAME: () #[[ATTR0]] { 5530 // SIMD3-NEXT: entry: 5531 // SIMD3-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27) 5532 // SIMD3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]] 5533 // SIMD3-NEXT: ret void 5534 // 5535 // 5536 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S2C1Ei 5537 // SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5538 // SIMD3-NEXT: entry: 5539 // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5540 // SIMD3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5541 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5542 // SIMD3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5543 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5544 // SIMD3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 5545 // SIMD3-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]) 5546 // SIMD3-NEXT: ret void 5547 // 5548 // 5549 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S2D1Ev 5550 // SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 5551 // SIMD3-NEXT: entry: 5552 // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5553 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5554 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5555 // SIMD3-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]] 5556 // SIMD3-NEXT: ret void 5557 // 5558 // 5559 // SIMD3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 5560 // SIMD3-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 { 5561 // SIMD3-NEXT: entry: 5562 // SIMD3-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 5563 // SIMD3-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 5564 // SIMD3-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 5565 // SIMD3-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 5566 // SIMD3-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 5567 // SIMD3-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8 5568 // SIMD3-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8 5569 // SIMD3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) 5570 // SIMD3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] 5571 // SIMD3: invoke.cont: 5572 // SIMD3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8 5573 // SIMD3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) 5574 // SIMD3-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]] 5575 // SIMD3: invoke.cont2: 5576 // SIMD3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8 5577 // SIMD3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) 5578 // SIMD3-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] 5579 // SIMD3: invoke.cont3: 5580 // SIMD3-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8 5581 // SIMD3-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 5582 // SIMD3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) 5583 // SIMD3-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]] 5584 // SIMD3: invoke.cont7: 5585 // SIMD3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 5586 // SIMD3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) 5587 // SIMD3-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]] 5588 // SIMD3: invoke.cont8: 5589 // SIMD3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 5590 // SIMD3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) 5591 // SIMD3-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]] 5592 // SIMD3: invoke.cont9: 5593 // SIMD3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]] 5594 // SIMD3-NEXT: ret void 5595 // SIMD3: lpad: 5596 // SIMD3-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } 5597 // SIMD3-NEXT: cleanup 5598 // SIMD3-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0 5599 // SIMD3-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8 5600 // SIMD3-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1 5601 // SIMD3-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4 5602 // SIMD3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8 5603 // SIMD3-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]] 5604 // SIMD3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]] 5605 // SIMD3: arraydestroy.body: 5606 // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 5607 // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 5608 // SIMD3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 5609 // SIMD3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x 5610 // SIMD3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]] 5611 // SIMD3: arraydestroy.done4: 5612 // SIMD3-NEXT: br label [[EHCLEANUP:%.*]] 5613 // SIMD3: lpad6: 5614 // SIMD3-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } 5615 // SIMD3-NEXT: cleanup 5616 // SIMD3-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0 5617 // SIMD3-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8 5618 // SIMD3-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1 5619 // SIMD3-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4 5620 // SIMD3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8 5621 // SIMD3-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]] 5622 // SIMD3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]] 5623 // SIMD3: arraydestroy.body11: 5624 // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ] 5625 // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1 5626 // SIMD3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] 5627 // SIMD3-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1) 5628 // SIMD3-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]] 5629 // SIMD3: arraydestroy.done15: 5630 // SIMD3-NEXT: br label [[EHCLEANUP]] 5631 // SIMD3: ehcleanup: 5632 // SIMD3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8 5633 // SIMD3-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0 5634 // SIMD3-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]] 5635 // SIMD3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]] 5636 // SIMD3: arraydestroy.body17: 5637 // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] 5638 // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 5639 // SIMD3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] 5640 // SIMD3-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x 5641 // SIMD3-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] 5642 // SIMD3: arraydestroy.done21: 5643 // SIMD3-NEXT: br label [[EH_RESUME:%.*]] 5644 // SIMD3: eh.resume: 5645 // SIMD3-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 5646 // SIMD3-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 5647 // SIMD3-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 5648 // SIMD3-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 5649 // SIMD3-NEXT: resume { ptr, i32 } [[LPAD_VAL22]] 5650 // 5651 // 5652 // SIMD3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 5653 // SIMD3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 5654 // SIMD3-NEXT: entry: 5655 // SIMD3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 5656 // SIMD3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 5657 // SIMD3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 5658 // SIMD3: arraydestroy.body: 5659 // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 5660 // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 5661 // SIMD3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 5662 // SIMD3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x 5663 // SIMD3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 5664 // SIMD3: arraydestroy.done1: 5665 // SIMD3-NEXT: ret void 5666 // 5667 // 5668 // SIMD3-LABEL: define {{[^@]+}}@main 5669 // SIMD3-SAME: () #[[ATTR4:[0-9]+]] personality ptr @__gxx_personality_v0 { 5670 // SIMD3-NEXT: entry: 5671 // SIMD3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 5672 // SIMD3-NEXT: [[RES:%.*]] = alloca i32, align 4 5673 // SIMD3-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 5674 // SIMD3-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 5675 // SIMD3-NEXT: store i32 0, ptr [[RETVAL]], align 4 5676 // SIMD3-NEXT: [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8 5677 // SIMD3-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 5678 // SIMD3-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] 5679 // SIMD3: init.check: 5680 // SIMD3-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]] 5681 // SIMD3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 5682 // SIMD3-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] 5683 // SIMD3: init: 5684 // SIMD3-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZL3gs1, align 4 5685 // SIMD3-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]]) 5686 // SIMD3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] 5687 // SIMD3: invoke.cont: 5688 // SIMD3-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]] 5689 // SIMD3-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]] 5690 // SIMD3-NEXT: br label [[INIT_END]] 5691 // SIMD3: init.end: 5692 // SIMD3-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZN6Static1sE, align 4 5693 // SIMD3-NEXT: store i32 [[TMP4]], ptr [[RES]], align 4 5694 // SIMD3-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE2sm, align 8 5695 // SIMD3-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4 5696 // SIMD3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 5697 // SIMD3-NEXT: store i32 [[ADD]], ptr [[RES]], align 4 5698 // SIMD3-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZL3gs1, align 4 5699 // SIMD3-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4 5700 // SIMD3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] 5701 // SIMD3-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4 5702 // SIMD3-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZL3gs2, align 8 5703 // SIMD3-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4 5704 // SIMD3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 5705 // SIMD3-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4 5706 // SIMD3-NEXT: [[TMP11:%.*]] = load i32, ptr @gs3, align 4 5707 // SIMD3-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4 5708 // SIMD3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 5709 // SIMD3-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4 5710 // SIMD3-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4 5711 // SIMD3-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4 5712 // SIMD3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 5713 // SIMD3-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 5714 // SIMD3-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4 5715 // SIMD3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4 5716 // SIMD3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 5717 // SIMD3-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4 5718 // SIMD3-NEXT: [[TMP17:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4 5719 // SIMD3-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32 5720 // SIMD3-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4 5721 // SIMD3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]] 5722 // SIMD3-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4 5723 // SIMD3-NEXT: [[TMP19:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4 5724 // SIMD3-NEXT: [[TMP20:%.*]] = load i32, ptr [[RES]], align 4 5725 // SIMD3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]] 5726 // SIMD3-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4 5727 // SIMD3-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4 5728 // SIMD3-NEXT: ret i32 [[TMP21]] 5729 // SIMD3: lpad: 5730 // SIMD3-NEXT: [[TMP22:%.*]] = landingpad { ptr, i32 } 5731 // SIMD3-NEXT: cleanup 5732 // SIMD3-NEXT: [[TMP23:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 0 5733 // SIMD3-NEXT: store ptr [[TMP23]], ptr [[EXN_SLOT]], align 8 5734 // SIMD3-NEXT: [[TMP24:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 1 5735 // SIMD3-NEXT: store i32 [[TMP24]], ptr [[EHSELECTOR_SLOT]], align 4 5736 // SIMD3-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]] 5737 // SIMD3-NEXT: br label [[EH_RESUME:%.*]] 5738 // SIMD3: eh.resume: 5739 // SIMD3-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 5740 // SIMD3-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 5741 // SIMD3-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 5742 // SIMD3-NEXT: [[LPAD_VAL8:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 5743 // SIMD3-NEXT: resume { ptr, i32 } [[LPAD_VAL8]] 5744 // 5745 // 5746 // SIMD3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei 5747 // SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 5748 // SIMD3-NEXT: entry: 5749 // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5750 // SIMD3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5751 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5752 // SIMD3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5753 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5754 // SIMD3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 5755 // SIMD3-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]) 5756 // SIMD3-NEXT: ret void 5757 // 5758 // 5759 // SIMD3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev 5760 // SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 5761 // SIMD3-NEXT: entry: 5762 // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5763 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5764 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5765 // SIMD3-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] 5766 // SIMD3-NEXT: ret void 5767 // 5768 // 5769 // SIMD3-LABEL: define {{[^@]+}}@_Z6foobarv 5770 // SIMD3-SAME: () #[[ATTR2]] { 5771 // SIMD3-NEXT: entry: 5772 // SIMD3-NEXT: [[RES:%.*]] = alloca i32, align 4 5773 // SIMD3-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZN6Static1sE, align 4 5774 // SIMD3-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4 5775 // SIMD3-NEXT: [[TMP1:%.*]] = load i32, ptr @_ZL3gs1, align 4 5776 // SIMD3-NEXT: [[TMP2:%.*]] = load i32, ptr [[RES]], align 4 5777 // SIMD3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] 5778 // SIMD3-NEXT: store i32 [[ADD]], ptr [[RES]], align 4 5779 // SIMD3-NEXT: [[TMP3:%.*]] = load i32, ptr @_ZL3gs2, align 8 5780 // SIMD3-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4 5781 // SIMD3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]] 5782 // SIMD3-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4 5783 // SIMD3-NEXT: [[TMP5:%.*]] = load i32, ptr @gs3, align 4 5784 // SIMD3-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4 5785 // SIMD3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 5786 // SIMD3-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4 5787 // SIMD3-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4 5788 // SIMD3-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4 5789 // SIMD3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] 5790 // SIMD3-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4 5791 // SIMD3-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4 5792 // SIMD3-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4 5793 // SIMD3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 5794 // SIMD3-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 5795 // SIMD3-NEXT: [[TMP11:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4 5796 // SIMD3-NEXT: [[CONV:%.*]] = fptosi float [[TMP11]] to i32 5797 // SIMD3-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4 5798 // SIMD3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]] 5799 // SIMD3-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4 5800 // SIMD3-NEXT: [[TMP13:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4 5801 // SIMD3-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4 5802 // SIMD3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 5803 // SIMD3-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4 5804 // SIMD3-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4 5805 // SIMD3-NEXT: ret i32 [[TMP15]] 5806 // 5807 // 5808 // SIMD3-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 5809 // SIMD3-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) { 5810 // SIMD3-NEXT: entry: 5811 // SIMD3-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8 5812 // SIMD3-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 5813 // SIMD3-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]] 5814 // SIMD3: init.check: 5815 // SIMD3-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8 5816 // SIMD3-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23) 5817 // SIMD3-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]] 5818 // SIMD3-NEXT: br label [[INIT_END]] 5819 // SIMD3: init.end: 5820 // SIMD3-NEXT: ret void 5821 // 5822 // 5823 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S4C1Ei 5824 // SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5825 // SIMD3-NEXT: entry: 5826 // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5827 // SIMD3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5828 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5829 // SIMD3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5830 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5831 // SIMD3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 5832 // SIMD3-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]) 5833 // SIMD3-NEXT: ret void 5834 // 5835 // 5836 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S4D1Ev 5837 // SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 5838 // SIMD3-NEXT: entry: 5839 // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5840 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5841 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5842 // SIMD3-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] 5843 // SIMD3-NEXT: ret void 5844 // 5845 // 5846 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S1C2Ei 5847 // SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 5848 // SIMD3-NEXT: entry: 5849 // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5850 // SIMD3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5851 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5852 // SIMD3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5853 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5854 // SIMD3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 5855 // SIMD3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 5856 // SIMD3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4 5857 // SIMD3-NEXT: ret void 5858 // 5859 // 5860 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S1D2Ev 5861 // SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 5862 // SIMD3-NEXT: entry: 5863 // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5864 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5865 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5866 // SIMD3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 5867 // SIMD3-NEXT: store i32 0, ptr [[A]], align 4 5868 // SIMD3-NEXT: ret void 5869 // 5870 // 5871 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S2C2Ei 5872 // SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 5873 // SIMD3-NEXT: entry: 5874 // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5875 // SIMD3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5876 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5877 // SIMD3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5878 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5879 // SIMD3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0 5880 // SIMD3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 5881 // SIMD3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8 5882 // SIMD3-NEXT: ret void 5883 // 5884 // 5885 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S2D2Ev 5886 // SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 5887 // SIMD3-NEXT: entry: 5888 // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5889 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5890 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5891 // SIMD3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0 5892 // SIMD3-NEXT: store i32 0, ptr [[A]], align 8 5893 // SIMD3-NEXT: ret void 5894 // 5895 // 5896 // SIMD3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei 5897 // SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 5898 // SIMD3-NEXT: entry: 5899 // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5900 // SIMD3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5901 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5902 // SIMD3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5903 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5904 // SIMD3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0 5905 // SIMD3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 5906 // SIMD3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8 5907 // SIMD3-NEXT: ret void 5908 // 5909 // 5910 // SIMD3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev 5911 // SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 5912 // SIMD3-NEXT: entry: 5913 // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5914 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5915 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5916 // SIMD3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0 5917 // SIMD3-NEXT: store i32 0, ptr [[A]], align 8 5918 // SIMD3-NEXT: ret void 5919 // 5920 // 5921 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S4C2Ei 5922 // SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 5923 // SIMD3-NEXT: entry: 5924 // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5925 // SIMD3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5926 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5927 // SIMD3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5928 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5929 // SIMD3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0 5930 // SIMD3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 5931 // SIMD3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4 5932 // SIMD3-NEXT: ret void 5933 // 5934 // 5935 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S4D2Ev 5936 // SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 5937 // SIMD3-NEXT: entry: 5938 // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5939 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5940 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5941 // SIMD3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0 5942 // SIMD3-NEXT: store i32 0, ptr [[A]], align 4 5943 // SIMD3-NEXT: ret void 5944 // 5945 // 5946 // SIMD3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp 5947 // SIMD3-SAME: () #[[ATTR0]] { 5948 // SIMD3-NEXT: entry: 5949 // SIMD3-NEXT: call void @__cxx_global_var_init() 5950 // SIMD3-NEXT: call void @__cxx_global_var_init.1() 5951 // SIMD3-NEXT: call void @__cxx_global_var_init.2() 5952 // SIMD3-NEXT: ret void 5953 // 5954 // 5955 // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_var_init 5956 // SIMD4-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG115:![0-9]+]] { 5957 // SIMD4-NEXT: entry: 5958 // SIMD4-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG118:![0-9]+]] 5959 // SIMD4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG120:![0-9]+]] 5960 // SIMD4-NEXT: ret void, !dbg [[DBG121:![0-9]+]] 5961 // 5962 // 5963 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S1C1Ei 5964 // SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG122:![0-9]+]] { 5965 // SIMD4-NEXT: entry: 5966 // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5967 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5968 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5969 // SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META123:![0-9]+]], !DIExpression(), [[META125:![0-9]+]]) 5970 // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5971 // SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META126:![0-9]+]], !DIExpression(), [[META127:![0-9]+]]) 5972 // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5973 // SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG128:![0-9]+]] 5974 // SIMD4-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG128]] 5975 // SIMD4-NEXT: ret void, !dbg [[DBG129:![0-9]+]] 5976 // 5977 // 5978 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S1D1Ev 5979 // SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG130:![0-9]+]] { 5980 // SIMD4-NEXT: entry: 5981 // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 5982 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 5983 // SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META131:![0-9]+]], !DIExpression(), [[META132:![0-9]+]]) 5984 // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 5985 // SIMD4-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG133:![0-9]+]] 5986 // SIMD4-NEXT: ret void, !dbg [[DBG134:![0-9]+]] 5987 // 5988 // 5989 // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 5990 // SIMD4-SAME: () #[[ATTR0]] !dbg [[DBG135:![0-9]+]] { 5991 // SIMD4-NEXT: entry: 5992 // SIMD4-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG136:![0-9]+]] 5993 // SIMD4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG138:![0-9]+]] 5994 // SIMD4-NEXT: ret void, !dbg [[DBG139:![0-9]+]] 5995 // 5996 // 5997 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2C1Ei 5998 // SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG140:![0-9]+]] { 5999 // SIMD4-NEXT: entry: 6000 // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6001 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6002 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6003 // SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META141:![0-9]+]], !DIExpression(), [[META143:![0-9]+]]) 6004 // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6005 // SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META144:![0-9]+]], !DIExpression(), [[META145:![0-9]+]]) 6006 // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6007 // SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG146:![0-9]+]] 6008 // SIMD4-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG146]] 6009 // SIMD4-NEXT: ret void, !dbg [[DBG147:![0-9]+]] 6010 // 6011 // 6012 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2D1Ev 6013 // SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG148:![0-9]+]] { 6014 // SIMD4-NEXT: entry: 6015 // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6016 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6017 // SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META149:![0-9]+]], !DIExpression(), [[META150:![0-9]+]]) 6018 // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6019 // SIMD4-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG151:![0-9]+]] 6020 // SIMD4-NEXT: ret void, !dbg [[DBG152:![0-9]+]] 6021 // 6022 // 6023 // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 6024 // SIMD4-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG153:![0-9]+]] { 6025 // SIMD4-NEXT: entry: 6026 // SIMD4-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 6027 // SIMD4-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 6028 // SIMD4-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 6029 // SIMD4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 6030 // SIMD4-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 6031 // SIMD4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154:![0-9]+]] 6032 // SIMD4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156:![0-9]+]] 6033 // SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) 6034 // SIMD4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG157:![0-9]+]] 6035 // SIMD4: invoke.cont: 6036 // SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] 6037 // SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) 6038 // SIMD4-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG158:![0-9]+]] 6039 // SIMD4: invoke.cont2: 6040 // SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] 6041 // SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) 6042 // SIMD4-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG159:![0-9]+]] 6043 // SIMD4: invoke.cont3: 6044 // SIMD4-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154]] 6045 // SIMD4-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160:![0-9]+]] 6046 // SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) 6047 // SIMD4-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG161:![0-9]+]] 6048 // SIMD4: invoke.cont7: 6049 // SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] 6050 // SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) 6051 // SIMD4-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG162:![0-9]+]] 6052 // SIMD4: invoke.cont8: 6053 // SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] 6054 // SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) 6055 // SIMD4-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG163:![0-9]+]] 6056 // SIMD4: invoke.cont9: 6057 // SIMD4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG164:![0-9]+]] 6058 // SIMD4-NEXT: ret void, !dbg [[DBG164]] 6059 // SIMD4: lpad: 6060 // SIMD4-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } 6061 // SIMD4-NEXT: cleanup, !dbg [[DBG165:![0-9]+]] 6062 // SIMD4-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG165]] 6063 // SIMD4-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG165]] 6064 // SIMD4-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG165]] 6065 // SIMD4-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG165]] 6066 // SIMD4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] 6067 // SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG156]] 6068 // SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG156]] 6069 // SIMD4: arraydestroy.body: 6070 // SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG156]] 6071 // SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG156]] 6072 // SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG156]] 6073 // SIMD4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG156]] 6074 // SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG156]] 6075 // SIMD4: arraydestroy.done4: 6076 // SIMD4-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG156]] 6077 // SIMD4: lpad6: 6078 // SIMD4-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } 6079 // SIMD4-NEXT: cleanup, !dbg [[DBG165]] 6080 // SIMD4-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG165]] 6081 // SIMD4-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG165]] 6082 // SIMD4-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG165]] 6083 // SIMD4-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG165]] 6084 // SIMD4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] 6085 // SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG160]] 6086 // SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG160]] 6087 // SIMD4: arraydestroy.body11: 6088 // SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG160]] 6089 // SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG160]] 6090 // SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG160]] 6091 // SIMD4-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG160]] 6092 // SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG160]] 6093 // SIMD4: arraydestroy.done15: 6094 // SIMD4-NEXT: br label [[EHCLEANUP]], !dbg [[DBG160]] 6095 // SIMD4: ehcleanup: 6096 // SIMD4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154]] 6097 // SIMD4-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG154]] 6098 // SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG154]] 6099 // SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG154]] 6100 // SIMD4: arraydestroy.body17: 6101 // SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG154]] 6102 // SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG154]] 6103 // SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG154]] 6104 // SIMD4-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG154]] 6105 // SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG154]] 6106 // SIMD4: arraydestroy.done21: 6107 // SIMD4-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG154]] 6108 // SIMD4: eh.resume: 6109 // SIMD4-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG154]] 6110 // SIMD4-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG154]] 6111 // SIMD4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG154]] 6112 // SIMD4-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG154]] 6113 // SIMD4-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG154]] 6114 // 6115 // 6116 // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 6117 // SIMD4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG166:![0-9]+]] { 6118 // SIMD4-NEXT: entry: 6119 // SIMD4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 6120 // SIMD4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 6121 // SIMD4-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META170:![0-9]+]], !DIExpression(), [[META171:![0-9]+]]) 6122 // SIMD4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META171]] 6123 // SIMD4: arraydestroy.body: 6124 // SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META171]] 6125 // SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META171]] 6126 // SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META171]] 6127 // SIMD4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[META171]] 6128 // SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META171]] 6129 // SIMD4: arraydestroy.done1: 6130 // SIMD4-NEXT: ret void, !dbg [[META171]] 6131 // 6132 // 6133 // SIMD4-LABEL: define {{[^@]+}}@main 6134 // SIMD4-SAME: () #[[ATTR4:[0-9]+]] personality ptr @__gxx_personality_v0 !dbg [[DBG52:![0-9]+]] { 6135 // SIMD4-NEXT: entry: 6136 // SIMD4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 6137 // SIMD4-NEXT: [[RES:%.*]] = alloca i32, align 4 6138 // SIMD4-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 6139 // SIMD4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 6140 // SIMD4-NEXT: store i32 0, ptr [[RETVAL]], align 4 6141 // SIMD4-NEXT: #dbg_declare(ptr [[RES]], [[META172:![0-9]+]], !DIExpression(), [[META173:![0-9]+]]) 6142 // SIMD4-NEXT: [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG174:![0-9]+]] 6143 // SIMD4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG174]] 6144 // SIMD4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG174]], !prof [[PROF175:![0-9]+]] 6145 // SIMD4: init.check: 6146 // SIMD4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] 6147 // SIMD4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG174]] 6148 // SIMD4-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG174]] 6149 // SIMD4: init: 6150 // SIMD4-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG176:![0-9]+]] 6151 // SIMD4-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]]) 6152 // SIMD4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG177:![0-9]+]] 6153 // SIMD4: invoke.cont: 6154 // SIMD4-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG174]] 6155 // SIMD4-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] 6156 // SIMD4-NEXT: br label [[INIT_END]], !dbg [[DBG174]] 6157 // SIMD4: init.end: 6158 // SIMD4-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG178:![0-9]+]] 6159 // SIMD4-NEXT: store i32 [[TMP4]], ptr [[RES]], align 4, !dbg [[DBG179:![0-9]+]] 6160 // SIMD4-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE2sm, align 8, !dbg [[DBG180:![0-9]+]] 6161 // SIMD4-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG181:![0-9]+]] 6162 // SIMD4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG181]] 6163 // SIMD4-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG181]] 6164 // SIMD4-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG182:![0-9]+]] 6165 // SIMD4-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG183:![0-9]+]] 6166 // SIMD4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG183]] 6167 // SIMD4-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG183]] 6168 // SIMD4-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG184:![0-9]+]] 6169 // SIMD4-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG185:![0-9]+]] 6170 // SIMD4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG185]] 6171 // SIMD4-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG185]] 6172 // SIMD4-NEXT: [[TMP11:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG186:![0-9]+]] 6173 // SIMD4-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG187:![0-9]+]] 6174 // SIMD4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG187]] 6175 // SIMD4-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG187]] 6176 // SIMD4-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4, !dbg [[DBG188:![0-9]+]] 6177 // SIMD4-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG189:![0-9]+]] 6178 // SIMD4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG189]] 6179 // SIMD4-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG189]] 6180 // SIMD4-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG190:![0-9]+]] 6181 // SIMD4-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG191:![0-9]+]] 6182 // SIMD4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG191]] 6183 // SIMD4-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG191]] 6184 // SIMD4-NEXT: [[TMP17:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG192:![0-9]+]] 6185 // SIMD4-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG192]] 6186 // SIMD4-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG193:![0-9]+]] 6187 // SIMD4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG193]] 6188 // SIMD4-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG193]] 6189 // SIMD4-NEXT: [[TMP19:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG194:![0-9]+]] 6190 // SIMD4-NEXT: [[TMP20:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG195:![0-9]+]] 6191 // SIMD4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]], !dbg [[DBG195]] 6192 // SIMD4-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG195]] 6193 // SIMD4-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG196:![0-9]+]] 6194 // SIMD4-NEXT: ret i32 [[TMP21]], !dbg [[DBG197:![0-9]+]] 6195 // SIMD4: lpad: 6196 // SIMD4-NEXT: [[TMP22:%.*]] = landingpad { ptr, i32 } 6197 // SIMD4-NEXT: cleanup, !dbg [[DBG198:![0-9]+]] 6198 // SIMD4-NEXT: [[TMP23:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 0, !dbg [[DBG198]] 6199 // SIMD4-NEXT: store ptr [[TMP23]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG198]] 6200 // SIMD4-NEXT: [[TMP24:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 1, !dbg [[DBG198]] 6201 // SIMD4-NEXT: store i32 [[TMP24]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG198]] 6202 // SIMD4-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] 6203 // SIMD4-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG174]] 6204 // SIMD4: eh.resume: 6205 // SIMD4-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG174]] 6206 // SIMD4-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG174]] 6207 // SIMD4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG174]] 6208 // SIMD4-NEXT: [[LPAD_VAL8:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG174]] 6209 // SIMD4-NEXT: resume { ptr, i32 } [[LPAD_VAL8]], !dbg [[DBG174]] 6210 // 6211 // 6212 // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei 6213 // SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG199:![0-9]+]] { 6214 // SIMD4-NEXT: entry: 6215 // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6216 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6217 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6218 // SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META200:![0-9]+]], !DIExpression(), [[META202:![0-9]+]]) 6219 // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6220 // SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META203:![0-9]+]], !DIExpression(), [[META204:![0-9]+]]) 6221 // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6222 // SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG205:![0-9]+]] 6223 // SIMD4-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG205]] 6224 // SIMD4-NEXT: ret void, !dbg [[DBG206:![0-9]+]] 6225 // 6226 // 6227 // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev 6228 // SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG207:![0-9]+]] { 6229 // SIMD4-NEXT: entry: 6230 // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6231 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6232 // SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META208:![0-9]+]], !DIExpression(), [[META209:![0-9]+]]) 6233 // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6234 // SIMD4-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG210:![0-9]+]] 6235 // SIMD4-NEXT: ret void, !dbg [[DBG211:![0-9]+]] 6236 // 6237 // 6238 // SIMD4-LABEL: define {{[^@]+}}@_Z6foobarv 6239 // SIMD4-SAME: () #[[ATTR2]] !dbg [[DBG212:![0-9]+]] { 6240 // SIMD4-NEXT: entry: 6241 // SIMD4-NEXT: [[RES:%.*]] = alloca i32, align 4 6242 // SIMD4-NEXT: #dbg_declare(ptr [[RES]], [[META213:![0-9]+]], !DIExpression(), [[META214:![0-9]+]]) 6243 // SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG215:![0-9]+]] 6244 // SIMD4-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4, !dbg [[DBG216:![0-9]+]] 6245 // SIMD4-NEXT: [[TMP1:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG217:![0-9]+]] 6246 // SIMD4-NEXT: [[TMP2:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG218:![0-9]+]] 6247 // SIMD4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]], !dbg [[DBG218]] 6248 // SIMD4-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG218]] 6249 // SIMD4-NEXT: [[TMP3:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG219:![0-9]+]] 6250 // SIMD4-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG220:![0-9]+]] 6251 // SIMD4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG220]] 6252 // SIMD4-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG220]] 6253 // SIMD4-NEXT: [[TMP5:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG221:![0-9]+]] 6254 // SIMD4-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG222:![0-9]+]] 6255 // SIMD4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG222]] 6256 // SIMD4-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG222]] 6257 // SIMD4-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4, !dbg [[DBG223:![0-9]+]] 6258 // SIMD4-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG224:![0-9]+]] 6259 // SIMD4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG224]] 6260 // SIMD4-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG224]] 6261 // SIMD4-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG225:![0-9]+]] 6262 // SIMD4-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG226:![0-9]+]] 6263 // SIMD4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG226]] 6264 // SIMD4-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG226]] 6265 // SIMD4-NEXT: [[TMP11:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG227:![0-9]+]] 6266 // SIMD4-NEXT: [[CONV:%.*]] = fptosi float [[TMP11]] to i32, !dbg [[DBG227]] 6267 // SIMD4-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG228:![0-9]+]] 6268 // SIMD4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]], !dbg [[DBG228]] 6269 // SIMD4-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG228]] 6270 // SIMD4-NEXT: [[TMP13:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG229:![0-9]+]] 6271 // SIMD4-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG230:![0-9]+]] 6272 // SIMD4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG230]] 6273 // SIMD4-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG230]] 6274 // SIMD4-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]] 6275 // SIMD4-NEXT: ret i32 [[TMP15]], !dbg [[DBG232:![0-9]+]] 6276 // 6277 // 6278 // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 6279 // SIMD4-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG233:![0-9]+]] { 6280 // SIMD4-NEXT: entry: 6281 // SIMD4-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG234:![0-9]+]] 6282 // SIMD4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG234]] 6283 // SIMD4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG234]] 6284 // SIMD4: init.check: 6285 // SIMD4-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG234]] 6286 // SIMD4-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG235:![0-9]+]] 6287 // SIMD4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG234]] 6288 // SIMD4-NEXT: br label [[INIT_END]], !dbg [[DBG234]] 6289 // SIMD4: init.end: 6290 // SIMD4-NEXT: ret void, !dbg [[DBG237:![0-9]+]] 6291 // 6292 // 6293 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4C1Ei 6294 // SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG238:![0-9]+]] { 6295 // SIMD4-NEXT: entry: 6296 // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6297 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6298 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6299 // SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META239:![0-9]+]], !DIExpression(), [[META241:![0-9]+]]) 6300 // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6301 // SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META242:![0-9]+]], !DIExpression(), [[META243:![0-9]+]]) 6302 // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6303 // SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG244:![0-9]+]] 6304 // SIMD4-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG244]] 6305 // SIMD4-NEXT: ret void, !dbg [[DBG245:![0-9]+]] 6306 // 6307 // 6308 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4D1Ev 6309 // SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG246:![0-9]+]] { 6310 // SIMD4-NEXT: entry: 6311 // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6312 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6313 // SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META247:![0-9]+]], !DIExpression(), [[META248:![0-9]+]]) 6314 // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6315 // SIMD4-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG249:![0-9]+]] 6316 // SIMD4-NEXT: ret void, !dbg [[DBG250:![0-9]+]] 6317 // 6318 // 6319 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S1C2Ei 6320 // SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG251:![0-9]+]] { 6321 // SIMD4-NEXT: entry: 6322 // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6323 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6324 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6325 // SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META252:![0-9]+]], !DIExpression(), [[META253:![0-9]+]]) 6326 // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6327 // SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META254:![0-9]+]], !DIExpression(), [[META255:![0-9]+]]) 6328 // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6329 // SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG256:![0-9]+]] 6330 // SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG257:![0-9]+]] 6331 // SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG256]] 6332 // SIMD4-NEXT: ret void, !dbg [[DBG258:![0-9]+]] 6333 // 6334 // 6335 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S1D2Ev 6336 // SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG259:![0-9]+]] { 6337 // SIMD4-NEXT: entry: 6338 // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6339 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6340 // SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META260:![0-9]+]], !DIExpression(), [[META261:![0-9]+]]) 6341 // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6342 // SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG262:![0-9]+]] 6343 // SIMD4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG264:![0-9]+]] 6344 // SIMD4-NEXT: ret void, !dbg [[DBG265:![0-9]+]] 6345 // 6346 // 6347 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2C2Ei 6348 // SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG266:![0-9]+]] { 6349 // SIMD4-NEXT: entry: 6350 // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6351 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6352 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6353 // SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META267:![0-9]+]], !DIExpression(), [[META268:![0-9]+]]) 6354 // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6355 // SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META269:![0-9]+]], !DIExpression(), [[META270:![0-9]+]]) 6356 // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6357 // SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG271:![0-9]+]] 6358 // SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG272:![0-9]+]] 6359 // SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG271]] 6360 // SIMD4-NEXT: ret void, !dbg [[DBG273:![0-9]+]] 6361 // 6362 // 6363 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2D2Ev 6364 // SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG274:![0-9]+]] { 6365 // SIMD4-NEXT: entry: 6366 // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6367 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6368 // SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META275:![0-9]+]], !DIExpression(), [[META276:![0-9]+]]) 6369 // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6370 // SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG277:![0-9]+]] 6371 // SIMD4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG279:![0-9]+]] 6372 // SIMD4-NEXT: ret void, !dbg [[DBG280:![0-9]+]] 6373 // 6374 // 6375 // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei 6376 // SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG281:![0-9]+]] { 6377 // SIMD4-NEXT: entry: 6378 // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6379 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6380 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6381 // SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META282:![0-9]+]], !DIExpression(), [[META283:![0-9]+]]) 6382 // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6383 // SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META284:![0-9]+]], !DIExpression(), [[META285:![0-9]+]]) 6384 // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6385 // SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG286:![0-9]+]] 6386 // SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG287:![0-9]+]] 6387 // SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG286]] 6388 // SIMD4-NEXT: ret void, !dbg [[DBG288:![0-9]+]] 6389 // 6390 // 6391 // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev 6392 // SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG289:![0-9]+]] { 6393 // SIMD4-NEXT: entry: 6394 // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6395 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6396 // SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META290:![0-9]+]], !DIExpression(), [[META291:![0-9]+]]) 6397 // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6398 // SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG292:![0-9]+]] 6399 // SIMD4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG294:![0-9]+]] 6400 // SIMD4-NEXT: ret void, !dbg [[DBG295:![0-9]+]] 6401 // 6402 // 6403 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4C2Ei 6404 // SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG296:![0-9]+]] { 6405 // SIMD4-NEXT: entry: 6406 // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6407 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6408 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6409 // SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META297:![0-9]+]], !DIExpression(), [[META298:![0-9]+]]) 6410 // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6411 // SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META299:![0-9]+]], !DIExpression(), [[META300:![0-9]+]]) 6412 // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6413 // SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG301:![0-9]+]] 6414 // SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG302:![0-9]+]] 6415 // SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG301]] 6416 // SIMD4-NEXT: ret void, !dbg [[DBG303:![0-9]+]] 6417 // 6418 // 6419 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4D2Ev 6420 // SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG304:![0-9]+]] { 6421 // SIMD4-NEXT: entry: 6422 // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6423 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6424 // SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META305:![0-9]+]], !DIExpression(), [[META306:![0-9]+]]) 6425 // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6426 // SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG307:![0-9]+]] 6427 // SIMD4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG309:![0-9]+]] 6428 // SIMD4-NEXT: ret void, !dbg [[DBG310:![0-9]+]] 6429 // 6430 // 6431 // SIMD4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp 6432 // SIMD4-SAME: () #[[ATTR0]] !dbg [[DBG311:![0-9]+]] { 6433 // SIMD4-NEXT: entry: 6434 // SIMD4-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG313:![0-9]+]] 6435 // SIMD4-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG313]] 6436 // SIMD4-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG313]] 6437 // SIMD4-NEXT: ret void 6438 // 6439 // 6440 // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_. 6441 // DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG116:![0-9]+]] { 6442 // DEBUG1-NEXT: entry: 6443 // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 6444 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 6445 // DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META118:![0-9]+]], !DIExpression(), [[META120:![0-9]+]]) 6446 // DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG121:![0-9]+]] 6447 // DEBUG1-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 5), !dbg [[DBG122:![0-9]+]] 6448 // DEBUG1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG121]] 6449 // DEBUG1-NEXT: ret ptr [[TMP2]], !dbg [[DBG121]] 6450 // 6451 // 6452 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S1C1Ei 6453 // DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG123:![0-9]+]] { 6454 // DEBUG1-NEXT: entry: 6455 // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6456 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6457 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6458 // DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META124:![0-9]+]], !DIExpression(), [[META126:![0-9]+]]) 6459 // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6460 // DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META127:![0-9]+]], !DIExpression(), [[META128:![0-9]+]]) 6461 // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6462 // DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG129:![0-9]+]] 6463 // DEBUG1-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG129]] 6464 // DEBUG1-NEXT: ret void, !dbg [[DBG130:![0-9]+]] 6465 // 6466 // 6467 // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_. 6468 // DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG131:![0-9]+]] { 6469 // DEBUG1-NEXT: entry: 6470 // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 6471 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 6472 // DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META132:![0-9]+]], !DIExpression(), [[META133:![0-9]+]]) 6473 // DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META133]] 6474 // DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR3:[0-9]+]], !dbg [[META133]] 6475 // DEBUG1-NEXT: ret void, !dbg [[DBG134:![0-9]+]] 6476 // 6477 // 6478 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S1D1Ev 6479 // DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG135:![0-9]+]] { 6480 // DEBUG1-NEXT: entry: 6481 // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6482 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6483 // DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META136:![0-9]+]], !DIExpression(), [[META137:![0-9]+]]) 6484 // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6485 // DEBUG1-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG138:![0-9]+]] 6486 // DEBUG1-NEXT: ret void, !dbg [[DBG139:![0-9]+]] 6487 // 6488 // 6489 // DEBUG1-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_. 6490 // DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG140:![0-9]+]] { 6491 // DEBUG1-NEXT: entry: 6492 // DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]), !dbg [[DBG141:![0-9]+]] 6493 // DEBUG1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZL3gs1, ptr @.__kmpc_global_ctor_., ptr null, ptr @.__kmpc_global_dtor_.), !dbg [[DBG141]] 6494 // DEBUG1-NEXT: ret void, !dbg [[DBG141]] 6495 // 6496 // 6497 // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..1 6498 // DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG142:![0-9]+]] { 6499 // DEBUG1-NEXT: entry: 6500 // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 6501 // DEBUG1-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 6502 // DEBUG1-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 6503 // DEBUG1-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 6504 // DEBUG1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 6505 // DEBUG1-NEXT: [[ARRAYINIT_ENDOFINIT7:%.*]] = alloca ptr, align 8 6506 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 6507 // DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META143:![0-9]+]], !DIExpression(), [[META144:![0-9]+]]) 6508 // DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG145:![0-9]+]] 6509 // DEBUG1-NEXT: store ptr [[TMP1]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG146:![0-9]+]] 6510 // DEBUG1-NEXT: store ptr [[TMP1]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG147:![0-9]+]] 6511 // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 1) 6512 // DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG148:![0-9]+]] 6513 // DEBUG1: invoke.cont: 6514 // DEBUG1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 1, !dbg [[DBG147]] 6515 // DEBUG1-NEXT: store ptr [[ARRAYINIT_ELEMENT]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG147]] 6516 // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 6517 // DEBUG1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG149:![0-9]+]] 6518 // DEBUG1: invoke.cont2: 6519 // DEBUG1-NEXT: [[ARRAYINIT_ELEMENT3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP1]], i64 2, !dbg [[DBG147]] 6520 // DEBUG1-NEXT: store ptr [[ARRAYINIT_ELEMENT3]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG147]] 6521 // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT3]], i32 noundef 3) 6522 // DEBUG1-NEXT: to label [[INVOKE_CONT4:%.*]] unwind label [[LPAD]], !dbg [[DBG150:![0-9]+]] 6523 // DEBUG1: invoke.cont4: 6524 // DEBUG1-NEXT: [[ARRAYINIT_ELEMENT6:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP1]], i64 1, !dbg [[DBG146]] 6525 // DEBUG1-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG146]] 6526 // DEBUG1-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG151:![0-9]+]] 6527 // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT6]], i32 noundef 4) 6528 // DEBUG1-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD8:%.*]], !dbg [[DBG152:![0-9]+]] 6529 // DEBUG1: invoke.cont9: 6530 // DEBUG1-NEXT: [[ARRAYINIT_ELEMENT10:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT6]], i64 1, !dbg [[DBG151]] 6531 // DEBUG1-NEXT: store ptr [[ARRAYINIT_ELEMENT10]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG151]] 6532 // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT10]], i32 noundef 5) 6533 // DEBUG1-NEXT: to label [[INVOKE_CONT11:%.*]] unwind label [[LPAD8]], !dbg [[DBG153:![0-9]+]] 6534 // DEBUG1: invoke.cont11: 6535 // DEBUG1-NEXT: [[ARRAYINIT_ELEMENT12:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT6]], i64 2, !dbg [[DBG151]] 6536 // DEBUG1-NEXT: store ptr [[ARRAYINIT_ELEMENT12]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG151]] 6537 // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT12]], i32 noundef 6) 6538 // DEBUG1-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[LPAD8]], !dbg [[DBG154:![0-9]+]] 6539 // DEBUG1: invoke.cont13: 6540 // DEBUG1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG145]] 6541 // DEBUG1-NEXT: ret ptr [[TMP2]], !dbg [[DBG145]] 6542 // DEBUG1: lpad: 6543 // DEBUG1-NEXT: [[TMP3:%.*]] = landingpad { ptr, i32 } 6544 // DEBUG1-NEXT: cleanup, !dbg [[META144]] 6545 // DEBUG1-NEXT: [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 0, !dbg [[META144]] 6546 // DEBUG1-NEXT: store ptr [[TMP4]], ptr [[EXN_SLOT]], align 8, !dbg [[META144]] 6547 // DEBUG1-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 1, !dbg [[META144]] 6548 // DEBUG1-NEXT: store i32 [[TMP5]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[META144]] 6549 // DEBUG1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG147]] 6550 // DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP6]], !dbg [[DBG147]] 6551 // DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG147]] 6552 // DEBUG1: arraydestroy.body: 6553 // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG147]] 6554 // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG147]] 6555 // DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG147]] 6556 // DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]], !dbg [[DBG147]] 6557 // DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG147]] 6558 // DEBUG1: arraydestroy.done5: 6559 // DEBUG1-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG147]] 6560 // DEBUG1: lpad8: 6561 // DEBUG1-NEXT: [[TMP7:%.*]] = landingpad { ptr, i32 } 6562 // DEBUG1-NEXT: cleanup, !dbg [[META144]] 6563 // DEBUG1-NEXT: [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 0, !dbg [[META144]] 6564 // DEBUG1-NEXT: store ptr [[TMP8]], ptr [[EXN_SLOT]], align 8, !dbg [[META144]] 6565 // DEBUG1-NEXT: [[TMP9:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 1, !dbg [[META144]] 6566 // DEBUG1-NEXT: store i32 [[TMP9]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[META144]] 6567 // DEBUG1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG151]] 6568 // DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY14:%.*]] = icmp eq ptr [[ARRAYINIT_ELEMENT6]], [[TMP10]], !dbg [[DBG151]] 6569 // DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY14]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15:%.*]], !dbg [[DBG151]] 6570 // DEBUG1: arraydestroy.body15: 6571 // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi ptr [ [[TMP10]], [[LPAD8]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ], !dbg [[DBG151]] 6572 // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST16]], i64 -1, !dbg [[DBG151]] 6573 // DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]], !dbg [[DBG151]] 6574 // DEBUG1-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT17]], [[ARRAYINIT_ELEMENT6]], !dbg [[DBG151]] 6575 // DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_BODY15]], !dbg [[DBG151]] 6576 // DEBUG1: arraydestroy.done19: 6577 // DEBUG1-NEXT: br label [[EHCLEANUP]], !dbg [[DBG151]] 6578 // DEBUG1: ehcleanup: 6579 // DEBUG1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG146]] 6580 // DEBUG1-NEXT: [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP1]], i64 0, i64 0, !dbg [[DBG146]] 6581 // DEBUG1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP11]], i64 0, i64 0, !dbg [[DBG146]] 6582 // DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY20:%.*]] = icmp eq ptr [[PAD_ARRAYBEGIN]], [[PAD_ARRAYEND]], !dbg [[DBG146]] 6583 // DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY20]], label [[ARRAYDESTROY_DONE25:%.*]], label [[ARRAYDESTROY_BODY21:%.*]], !dbg [[DBG146]] 6584 // DEBUG1: arraydestroy.body21: 6585 // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST22:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT23:%.*]], [[ARRAYDESTROY_BODY21]] ], !dbg [[DBG146]] 6586 // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT23]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST22]], i64 -1, !dbg [[DBG146]] 6587 // DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT23]]) #[[ATTR3]], !dbg [[DBG146]] 6588 // DEBUG1-NEXT: [[ARRAYDESTROY_DONE24:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT23]], [[PAD_ARRAYBEGIN]], !dbg [[DBG146]] 6589 // DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE24]], label [[ARRAYDESTROY_DONE25]], label [[ARRAYDESTROY_BODY21]], !dbg [[DBG146]] 6590 // DEBUG1: arraydestroy.done25: 6591 // DEBUG1-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG146]] 6592 // DEBUG1: eh.resume: 6593 // DEBUG1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG146]] 6594 // DEBUG1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG146]] 6595 // DEBUG1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG146]] 6596 // DEBUG1-NEXT: [[LPAD_VAL26:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG146]] 6597 // DEBUG1-NEXT: resume { ptr, i32 } [[LPAD_VAL26]], !dbg [[DBG146]] 6598 // 6599 // 6600 // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..2 6601 // DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG155:![0-9]+]] { 6602 // DEBUG1-NEXT: entry: 6603 // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 6604 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 6605 // DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META156:![0-9]+]], !DIExpression(), [[META157:![0-9]+]]) 6606 // DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META157]] 6607 // DEBUG1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 6, !dbg [[META157]] 6608 // DEBUG1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META157]] 6609 // DEBUG1: arraydestroy.body: 6610 // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META157]] 6611 // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META157]] 6612 // DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META157]] 6613 // DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]], !dbg [[META157]] 6614 // DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META157]] 6615 // DEBUG1: arraydestroy.done1: 6616 // DEBUG1-NEXT: ret void, !dbg [[DBG158:![0-9]+]] 6617 // 6618 // 6619 // DEBUG1-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_..3 6620 // DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG159:![0-9]+]] { 6621 // DEBUG1-NEXT: entry: 6622 // DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]), !dbg [[DBG160:![0-9]+]] 6623 // DEBUG1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB3]], ptr @arr_x, ptr @.__kmpc_global_ctor_..1, ptr null, ptr @.__kmpc_global_dtor_..2), !dbg [[DBG160]] 6624 // DEBUG1-NEXT: ret void, !dbg [[DBG160]] 6625 // 6626 // 6627 // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_var_init 6628 // DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG161:![0-9]+]] { 6629 // DEBUG1-NEXT: entry: 6630 // DEBUG1-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG164:![0-9]+]] 6631 // DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG166:![0-9]+]] 6632 // DEBUG1-NEXT: ret void, !dbg [[DBG167:![0-9]+]] 6633 // 6634 // 6635 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S1C2Ei 6636 // DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG168:![0-9]+]] { 6637 // DEBUG1-NEXT: entry: 6638 // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6639 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6640 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6641 // DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META169:![0-9]+]], !DIExpression(), [[META170:![0-9]+]]) 6642 // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6643 // DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META171:![0-9]+]], !DIExpression(), [[META172:![0-9]+]]) 6644 // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6645 // DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG173:![0-9]+]] 6646 // DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG174:![0-9]+]] 6647 // DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG173]] 6648 // DEBUG1-NEXT: ret void, !dbg [[DBG175:![0-9]+]] 6649 // 6650 // 6651 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S1D2Ev 6652 // DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG176:![0-9]+]] { 6653 // DEBUG1-NEXT: entry: 6654 // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6655 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6656 // DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META177:![0-9]+]], !DIExpression(), [[META178:![0-9]+]]) 6657 // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6658 // DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG179:![0-9]+]] 6659 // DEBUG1-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG181:![0-9]+]] 6660 // DEBUG1-NEXT: ret void, !dbg [[DBG182:![0-9]+]] 6661 // 6662 // 6663 // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_var_init.4 6664 // DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG183:![0-9]+]] { 6665 // DEBUG1-NEXT: entry: 6666 // DEBUG1-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG184:![0-9]+]] 6667 // DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG186:![0-9]+]] 6668 // DEBUG1-NEXT: ret void, !dbg [[DBG187:![0-9]+]] 6669 // 6670 // 6671 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2C1Ei 6672 // DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG188:![0-9]+]] { 6673 // DEBUG1-NEXT: entry: 6674 // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6675 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6676 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6677 // DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META189:![0-9]+]], !DIExpression(), [[META191:![0-9]+]]) 6678 // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6679 // DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META192:![0-9]+]], !DIExpression(), [[META193:![0-9]+]]) 6680 // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6681 // DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG194:![0-9]+]] 6682 // DEBUG1-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG194]] 6683 // DEBUG1-NEXT: ret void, !dbg [[DBG195:![0-9]+]] 6684 // 6685 // 6686 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2D1Ev 6687 // DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG196:![0-9]+]] { 6688 // DEBUG1-NEXT: entry: 6689 // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6690 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6691 // DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META197:![0-9]+]], !DIExpression(), [[META198:![0-9]+]]) 6692 // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6693 // DEBUG1-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG199:![0-9]+]] 6694 // DEBUG1-NEXT: ret void, !dbg [[DBG200:![0-9]+]] 6695 // 6696 // 6697 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2C2Ei 6698 // DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG201:![0-9]+]] { 6699 // DEBUG1-NEXT: entry: 6700 // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6701 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6702 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6703 // DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META202:![0-9]+]], !DIExpression(), [[META203:![0-9]+]]) 6704 // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6705 // DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META204:![0-9]+]], !DIExpression(), [[META205:![0-9]+]]) 6706 // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6707 // DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG206:![0-9]+]] 6708 // DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG207:![0-9]+]] 6709 // DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG206]] 6710 // DEBUG1-NEXT: ret void, !dbg [[DBG208:![0-9]+]] 6711 // 6712 // 6713 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2D2Ev 6714 // DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG209:![0-9]+]] { 6715 // DEBUG1-NEXT: entry: 6716 // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6717 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6718 // DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META210:![0-9]+]], !DIExpression(), [[META211:![0-9]+]]) 6719 // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6720 // DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG212:![0-9]+]] 6721 // DEBUG1-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG214:![0-9]+]] 6722 // DEBUG1-NEXT: ret void, !dbg [[DBG215:![0-9]+]] 6723 // 6724 // 6725 // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_var_init.5 6726 // DEBUG1-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG216:![0-9]+]] { 6727 // DEBUG1-NEXT: entry: 6728 // DEBUG1-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 6729 // DEBUG1-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 6730 // DEBUG1-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 6731 // DEBUG1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 6732 // DEBUG1-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 6733 // DEBUG1-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG217:![0-9]+]] 6734 // DEBUG1-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG219:![0-9]+]] 6735 // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) 6736 // DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG220:![0-9]+]] 6737 // DEBUG1: invoke.cont: 6738 // DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG219]] 6739 // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) 6740 // DEBUG1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG221:![0-9]+]] 6741 // DEBUG1: invoke.cont2: 6742 // DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG219]] 6743 // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) 6744 // DEBUG1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG222:![0-9]+]] 6745 // DEBUG1: invoke.cont3: 6746 // DEBUG1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG217]] 6747 // DEBUG1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG223:![0-9]+]] 6748 // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) 6749 // DEBUG1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG224:![0-9]+]] 6750 // DEBUG1: invoke.cont7: 6751 // DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG223]] 6752 // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) 6753 // DEBUG1-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG225:![0-9]+]] 6754 // DEBUG1: invoke.cont8: 6755 // DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG223]] 6756 // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) 6757 // DEBUG1-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG226:![0-9]+]] 6758 // DEBUG1: invoke.cont9: 6759 // DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG227:![0-9]+]] 6760 // DEBUG1-NEXT: ret void, !dbg [[DBG227]] 6761 // DEBUG1: lpad: 6762 // DEBUG1-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } 6763 // DEBUG1-NEXT: cleanup, !dbg [[DBG228:![0-9]+]] 6764 // DEBUG1-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG228]] 6765 // DEBUG1-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG228]] 6766 // DEBUG1-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG228]] 6767 // DEBUG1-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG228]] 6768 // DEBUG1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG219]] 6769 // DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG219]] 6770 // DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG219]] 6771 // DEBUG1: arraydestroy.body: 6772 // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG219]] 6773 // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG219]] 6774 // DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG219]] 6775 // DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG219]] 6776 // DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG219]] 6777 // DEBUG1: arraydestroy.done4: 6778 // DEBUG1-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG219]] 6779 // DEBUG1: lpad6: 6780 // DEBUG1-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } 6781 // DEBUG1-NEXT: cleanup, !dbg [[DBG228]] 6782 // DEBUG1-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG228]] 6783 // DEBUG1-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG228]] 6784 // DEBUG1-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG228]] 6785 // DEBUG1-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG228]] 6786 // DEBUG1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG223]] 6787 // DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG223]] 6788 // DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG223]] 6789 // DEBUG1: arraydestroy.body11: 6790 // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG223]] 6791 // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG223]] 6792 // DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG223]] 6793 // DEBUG1-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG223]] 6794 // DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG223]] 6795 // DEBUG1: arraydestroy.done15: 6796 // DEBUG1-NEXT: br label [[EHCLEANUP]], !dbg [[DBG223]] 6797 // DEBUG1: ehcleanup: 6798 // DEBUG1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG217]] 6799 // DEBUG1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG217]] 6800 // DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG217]] 6801 // DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG217]] 6802 // DEBUG1: arraydestroy.body17: 6803 // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG217]] 6804 // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG217]] 6805 // DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG217]] 6806 // DEBUG1-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG217]] 6807 // DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG217]] 6808 // DEBUG1: arraydestroy.done21: 6809 // DEBUG1-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG217]] 6810 // DEBUG1: eh.resume: 6811 // DEBUG1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG217]] 6812 // DEBUG1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG217]] 6813 // DEBUG1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG217]] 6814 // DEBUG1-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG217]] 6815 // DEBUG1-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG217]] 6816 // 6817 // 6818 // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 6819 // DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG229:![0-9]+]] { 6820 // DEBUG1-NEXT: entry: 6821 // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 6822 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 6823 // DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META232:![0-9]+]], !DIExpression(), [[META233:![0-9]+]]) 6824 // DEBUG1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META233]] 6825 // DEBUG1: arraydestroy.body: 6826 // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META233]] 6827 // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META233]] 6828 // DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META233]] 6829 // DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[META233]] 6830 // DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META233]] 6831 // DEBUG1: arraydestroy.done1: 6832 // DEBUG1-NEXT: ret void, !dbg [[META233]] 6833 // 6834 // 6835 // DEBUG1-LABEL: define {{[^@]+}}@main 6836 // DEBUG1-SAME: () #[[ATTR4:[0-9]+]] personality ptr @__gxx_personality_v0 !dbg [[DBG52:![0-9]+]] { 6837 // DEBUG1-NEXT: entry: 6838 // DEBUG1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 6839 // DEBUG1-NEXT: [[RES:%.*]] = alloca i32, align 4 6840 // DEBUG1-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 6841 // DEBUG1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 6842 // DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9:[0-9]+]]), !dbg [[DBG234:![0-9]+]] 6843 // DEBUG1-NEXT: store i32 0, ptr [[RETVAL]], align 4 6844 // DEBUG1-NEXT: #dbg_declare(ptr [[RES]], [[META235:![0-9]+]], !DIExpression(), [[META236:![0-9]+]]) 6845 // DEBUG1-NEXT: [[TMP1:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG237:![0-9]+]] 6846 // DEBUG1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP1]], 0, !dbg [[DBG237]] 6847 // DEBUG1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG237]], !prof [[PROF238:![0-9]+]] 6848 // DEBUG1: init.check: 6849 // DEBUG1-NEXT: [[TMP2:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG237]] 6850 // DEBUG1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0, !dbg [[DBG237]] 6851 // DEBUG1-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG237]] 6852 // DEBUG1: init: 6853 // DEBUG1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]]), !dbg [[DBG237]] 6854 // DEBUG1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB7]], ptr @_ZZ4mainE2sm, ptr @.__kmpc_global_ctor_..6, ptr null, ptr @.__kmpc_global_dtor_..7), !dbg [[DBG237]] 6855 // DEBUG1-NEXT: [[TMP4:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB9]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG234]] 6856 // DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG239:![0-9]+]] 6857 // DEBUG1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG239]] 6858 // DEBUG1-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP5]]) 6859 // DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG240:![0-9]+]] 6860 // DEBUG1: invoke.cont: 6861 // DEBUG1-NEXT: [[TMP6:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG237]] 6862 // DEBUG1-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG237]] 6863 // DEBUG1-NEXT: br label [[INIT_END]], !dbg [[DBG237]] 6864 // DEBUG1: init.end: 6865 // DEBUG1-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB11:[0-9]+]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG241:![0-9]+]] 6866 // DEBUG1-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG242:![0-9]+]] 6867 // DEBUG1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG242]] 6868 // DEBUG1-NEXT: store i32 [[TMP8]], ptr [[RES]], align 4, !dbg [[DBG243:![0-9]+]] 6869 // DEBUG1-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB13:[0-9]+]], i32 [[TMP0]], ptr @_ZZ4mainE2sm, i64 24, ptr @_ZZ4mainE2sm.cache.), !dbg [[DBG244:![0-9]+]] 6870 // DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG245:![0-9]+]] 6871 // DEBUG1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG245]] 6872 // DEBUG1-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG246:![0-9]+]] 6873 // DEBUG1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG246]] 6874 // DEBUG1-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG246]] 6875 // DEBUG1-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB15:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG247:![0-9]+]] 6876 // DEBUG1-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP12]], i32 0, i32 0, !dbg [[DBG248:![0-9]+]] 6877 // DEBUG1-NEXT: [[TMP13:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG248]] 6878 // DEBUG1-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG249:![0-9]+]] 6879 // DEBUG1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG249]] 6880 // DEBUG1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG249]] 6881 // DEBUG1-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG250:![0-9]+]] 6882 // DEBUG1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG251:![0-9]+]] 6883 // DEBUG1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG251]] 6884 // DEBUG1-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG251]] 6885 // DEBUG1-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB17:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG252:![0-9]+]] 6886 // DEBUG1-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP17]], i32 0, i32 0, !dbg [[DBG253:![0-9]+]] 6887 // DEBUG1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG253]] 6888 // DEBUG1-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG254:![0-9]+]] 6889 // DEBUG1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG254]] 6890 // DEBUG1-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG254]] 6891 // DEBUG1-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB19:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG255:![0-9]+]] 6892 // DEBUG1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], i64 0, i64 1, !dbg [[DBG255]] 6893 // DEBUG1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG255]] 6894 // DEBUG1-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG256:![0-9]+]] 6895 // DEBUG1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG256]] 6896 // DEBUG1-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG257:![0-9]+]] 6897 // DEBUG1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG257]] 6898 // DEBUG1-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG257]] 6899 // DEBUG1-NEXT: [[TMP23:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB21:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG258:![0-9]+]] 6900 // DEBUG1-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4, !dbg [[DBG258]] 6901 // DEBUG1-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG259:![0-9]+]] 6902 // DEBUG1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP25]], [[TMP24]], !dbg [[DBG259]] 6903 // DEBUG1-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG259]] 6904 // DEBUG1-NEXT: [[TMP26:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB23:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG260:![0-9]+]] 6905 // DEBUG1-NEXT: [[TMP27:%.*]] = load float, ptr [[TMP26]], align 4, !dbg [[DBG260]] 6906 // DEBUG1-NEXT: [[CONV:%.*]] = fptosi float [[TMP27]] to i32, !dbg [[DBG260]] 6907 // DEBUG1-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG261:![0-9]+]] 6908 // DEBUG1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[CONV]], !dbg [[DBG261]] 6909 // DEBUG1-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG261]] 6910 // DEBUG1-NEXT: [[TMP29:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB25:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG262:![0-9]+]] 6911 // DEBUG1-NEXT: [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP29]], i32 0, i32 0, !dbg [[DBG263:![0-9]+]] 6912 // DEBUG1-NEXT: [[TMP30:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG263]] 6913 // DEBUG1-NEXT: [[TMP31:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG264:![0-9]+]] 6914 // DEBUG1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP31]], [[TMP30]], !dbg [[DBG264]] 6915 // DEBUG1-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG264]] 6916 // DEBUG1-NEXT: [[TMP32:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG265:![0-9]+]] 6917 // DEBUG1-NEXT: ret i32 [[TMP32]], !dbg [[DBG266:![0-9]+]] 6918 // DEBUG1: lpad: 6919 // DEBUG1-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 } 6920 // DEBUG1-NEXT: cleanup, !dbg [[DBG267:![0-9]+]] 6921 // DEBUG1-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0, !dbg [[DBG267]] 6922 // DEBUG1-NEXT: store ptr [[TMP34]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG267]] 6923 // DEBUG1-NEXT: [[TMP35:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 1, !dbg [[DBG267]] 6924 // DEBUG1-NEXT: store i32 [[TMP35]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG267]] 6925 // DEBUG1-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG237]] 6926 // DEBUG1-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG237]] 6927 // DEBUG1: eh.resume: 6928 // DEBUG1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG237]] 6929 // DEBUG1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG237]] 6930 // DEBUG1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG237]] 6931 // DEBUG1-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG237]] 6932 // DEBUG1-NEXT: resume { ptr, i32 } [[LPAD_VAL15]], !dbg [[DBG237]] 6933 // 6934 // 6935 // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..6 6936 // DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG268:![0-9]+]] { 6937 // DEBUG1-NEXT: entry: 6938 // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 6939 // DEBUG1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB5:[0-9]+]]), !dbg [[DBG269:![0-9]+]] 6940 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 6941 // DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META270:![0-9]+]], !DIExpression(), [[META271:![0-9]+]]) 6942 // DEBUG1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG272:![0-9]+]] 6943 // DEBUG1-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB5]], i32 [[TMP1]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG269]] 6944 // DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG273:![0-9]+]] 6945 // DEBUG1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG273]] 6946 // DEBUG1-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) [[TMP2]], i32 noundef [[TMP4]]), !dbg [[DBG274:![0-9]+]] 6947 // DEBUG1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG272]] 6948 // DEBUG1-NEXT: ret ptr [[TMP5]], !dbg [[DBG272]] 6949 // 6950 // 6951 // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei 6952 // DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG275:![0-9]+]] { 6953 // DEBUG1-NEXT: entry: 6954 // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6955 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6956 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6957 // DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META276:![0-9]+]], !DIExpression(), [[META278:![0-9]+]]) 6958 // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6959 // DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META279:![0-9]+]], !DIExpression(), [[META280:![0-9]+]]) 6960 // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6961 // DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG281:![0-9]+]] 6962 // DEBUG1-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG281]] 6963 // DEBUG1-NEXT: ret void, !dbg [[DBG282:![0-9]+]] 6964 // 6965 // 6966 // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..7 6967 // DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG283:![0-9]+]] { 6968 // DEBUG1-NEXT: entry: 6969 // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 6970 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 6971 // DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META284:![0-9]+]], !DIExpression(), [[META285:![0-9]+]]) 6972 // DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META285]] 6973 // DEBUG1-NEXT: call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[TMP1]]) #[[ATTR3]], !dbg [[META285]] 6974 // DEBUG1-NEXT: ret void, !dbg [[DBG286:![0-9]+]] 6975 // 6976 // 6977 // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev 6978 // DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG287:![0-9]+]] { 6979 // DEBUG1-NEXT: entry: 6980 // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6981 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6982 // DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META288:![0-9]+]], !DIExpression(), [[META289:![0-9]+]]) 6983 // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6984 // DEBUG1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG290:![0-9]+]] 6985 // DEBUG1-NEXT: ret void, !dbg [[DBG291:![0-9]+]] 6986 // 6987 // 6988 // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei 6989 // DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG292:![0-9]+]] { 6990 // DEBUG1-NEXT: entry: 6991 // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 6992 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6993 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 6994 // DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META293:![0-9]+]], !DIExpression(), [[META294:![0-9]+]]) 6995 // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6996 // DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META295:![0-9]+]], !DIExpression(), [[META296:![0-9]+]]) 6997 // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 6998 // DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG297:![0-9]+]] 6999 // DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG298:![0-9]+]] 7000 // DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG297]] 7001 // DEBUG1-NEXT: ret void, !dbg [[DBG299:![0-9]+]] 7002 // 7003 // 7004 // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev 7005 // DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG300:![0-9]+]] { 7006 // DEBUG1-NEXT: entry: 7007 // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7008 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7009 // DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META301:![0-9]+]], !DIExpression(), [[META302:![0-9]+]]) 7010 // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7011 // DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG303:![0-9]+]] 7012 // DEBUG1-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG305:![0-9]+]] 7013 // DEBUG1-NEXT: ret void, !dbg [[DBG306:![0-9]+]] 7014 // 7015 // 7016 // DEBUG1-LABEL: define {{[^@]+}}@_Z6foobarv 7017 // DEBUG1-SAME: () #[[ATTR2]] !dbg [[DBG307:![0-9]+]] { 7018 // DEBUG1-NEXT: entry: 7019 // DEBUG1-NEXT: [[RES:%.*]] = alloca i32, align 4 7020 // DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB27:[0-9]+]]), !dbg [[DBG308:![0-9]+]] 7021 // DEBUG1-NEXT: #dbg_declare(ptr [[RES]], [[META309:![0-9]+]], !DIExpression(), [[META310:![0-9]+]]) 7022 // DEBUG1-NEXT: [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB27]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG308]] 7023 // DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG311:![0-9]+]] 7024 // DEBUG1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG311]] 7025 // DEBUG1-NEXT: store i32 [[TMP2]], ptr [[RES]], align 4, !dbg [[DBG312:![0-9]+]] 7026 // DEBUG1-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB29:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG313:![0-9]+]] 7027 // DEBUG1-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG314:![0-9]+]] 7028 // DEBUG1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG314]] 7029 // DEBUG1-NEXT: [[TMP5:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG315:![0-9]+]] 7030 // DEBUG1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]], !dbg [[DBG315]] 7031 // DEBUG1-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG315]] 7032 // DEBUG1-NEXT: [[TMP6:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG316:![0-9]+]] 7033 // DEBUG1-NEXT: [[TMP7:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG317:![0-9]+]] 7034 // DEBUG1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], [[TMP6]], !dbg [[DBG317]] 7035 // DEBUG1-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG317]] 7036 // DEBUG1-NEXT: [[TMP8:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB31:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG318:![0-9]+]] 7037 // DEBUG1-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP8]], i32 0, i32 0, !dbg [[DBG319:![0-9]+]] 7038 // DEBUG1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG319]] 7039 // DEBUG1-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG320:![0-9]+]] 7040 // DEBUG1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG320]] 7041 // DEBUG1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG320]] 7042 // DEBUG1-NEXT: [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB33:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG321:![0-9]+]] 7043 // DEBUG1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], i64 0, i64 1, !dbg [[DBG321]] 7044 // DEBUG1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG321]] 7045 // DEBUG1-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG322:![0-9]+]] 7046 // DEBUG1-NEXT: [[TMP12:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG322]] 7047 // DEBUG1-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG323:![0-9]+]] 7048 // DEBUG1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG323]] 7049 // DEBUG1-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG323]] 7050 // DEBUG1-NEXT: [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB35:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG324:![0-9]+]] 7051 // DEBUG1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4, !dbg [[DBG324]] 7052 // DEBUG1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG325:![0-9]+]] 7053 // DEBUG1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG325]] 7054 // DEBUG1-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG325]] 7055 // DEBUG1-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB37:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG326:![0-9]+]] 7056 // DEBUG1-NEXT: [[TMP18:%.*]] = load float, ptr [[TMP17]], align 4, !dbg [[DBG326]] 7057 // DEBUG1-NEXT: [[CONV:%.*]] = fptosi float [[TMP18]] to i32, !dbg [[DBG326]] 7058 // DEBUG1-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG327:![0-9]+]] 7059 // DEBUG1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], [[CONV]], !dbg [[DBG327]] 7060 // DEBUG1-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG327]] 7061 // DEBUG1-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB39:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG328:![0-9]+]] 7062 // DEBUG1-NEXT: [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP20]], i32 0, i32 0, !dbg [[DBG329:![0-9]+]] 7063 // DEBUG1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG329]] 7064 // DEBUG1-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG330:![0-9]+]] 7065 // DEBUG1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG330]] 7066 // DEBUG1-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG330]] 7067 // DEBUG1-NEXT: [[TMP23:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG331:![0-9]+]] 7068 // DEBUG1-NEXT: ret i32 [[TMP23]], !dbg [[DBG332:![0-9]+]] 7069 // 7070 // 7071 // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_var_init.8 7072 // DEBUG1-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG333:![0-9]+]] { 7073 // DEBUG1-NEXT: entry: 7074 // DEBUG1-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG334:![0-9]+]] 7075 // DEBUG1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG334]] 7076 // DEBUG1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG334]] 7077 // DEBUG1: init.check: 7078 // DEBUG1-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG334]] 7079 // DEBUG1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB41:[0-9]+]]), !dbg [[DBG334]] 7080 // DEBUG1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB41]], ptr @_ZN2STI2S4E2stE, ptr @.__kmpc_global_ctor_..9, ptr null, ptr @.__kmpc_global_dtor_..10), !dbg [[DBG334]] 7081 // DEBUG1-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG335:![0-9]+]] 7082 // DEBUG1-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG334]] 7083 // DEBUG1-NEXT: br label [[INIT_END]], !dbg [[DBG334]] 7084 // DEBUG1: init.end: 7085 // DEBUG1-NEXT: ret void, !dbg [[DBG337:![0-9]+]] 7086 // 7087 // 7088 // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..9 7089 // DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG338:![0-9]+]] { 7090 // DEBUG1-NEXT: entry: 7091 // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 7092 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 7093 // DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META339:![0-9]+]], !DIExpression(), [[META340:![0-9]+]]) 7094 // DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG341:![0-9]+]] 7095 // DEBUG1-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]], i32 noundef 23), !dbg [[DBG342:![0-9]+]] 7096 // DEBUG1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG341]] 7097 // DEBUG1-NEXT: ret ptr [[TMP2]], !dbg [[DBG341]] 7098 // 7099 // 7100 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4C1Ei 7101 // DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG343:![0-9]+]] { 7102 // DEBUG1-NEXT: entry: 7103 // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7104 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7105 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7106 // DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META344:![0-9]+]], !DIExpression(), [[META346:![0-9]+]]) 7107 // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 7108 // DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META347:![0-9]+]], !DIExpression(), [[META348:![0-9]+]]) 7109 // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7110 // DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG349:![0-9]+]] 7111 // DEBUG1-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG349]] 7112 // DEBUG1-NEXT: ret void, !dbg [[DBG350:![0-9]+]] 7113 // 7114 // 7115 // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..10 7116 // DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG351:![0-9]+]] { 7117 // DEBUG1-NEXT: entry: 7118 // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 7119 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 7120 // DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META352:![0-9]+]], !DIExpression(), [[META353:![0-9]+]]) 7121 // DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META353]] 7122 // DEBUG1-NEXT: call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]]) #[[ATTR3]], !dbg [[META353]] 7123 // DEBUG1-NEXT: ret void, !dbg [[DBG354:![0-9]+]] 7124 // 7125 // 7126 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4D1Ev 7127 // DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG355:![0-9]+]] { 7128 // DEBUG1-NEXT: entry: 7129 // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7130 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7131 // DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META356:![0-9]+]], !DIExpression(), [[META357:![0-9]+]]) 7132 // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7133 // DEBUG1-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG358:![0-9]+]] 7134 // DEBUG1-NEXT: ret void, !dbg [[DBG359:![0-9]+]] 7135 // 7136 // 7137 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4C2Ei 7138 // DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG360:![0-9]+]] { 7139 // DEBUG1-NEXT: entry: 7140 // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7141 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7142 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7143 // DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META361:![0-9]+]], !DIExpression(), [[META362:![0-9]+]]) 7144 // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 7145 // DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META363:![0-9]+]], !DIExpression(), [[META364:![0-9]+]]) 7146 // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7147 // DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG365:![0-9]+]] 7148 // DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG366:![0-9]+]] 7149 // DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG365]] 7150 // DEBUG1-NEXT: ret void, !dbg [[DBG367:![0-9]+]] 7151 // 7152 // 7153 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4D2Ev 7154 // DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG368:![0-9]+]] { 7155 // DEBUG1-NEXT: entry: 7156 // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7157 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7158 // DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META369:![0-9]+]], !DIExpression(), [[META370:![0-9]+]]) 7159 // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7160 // DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG371:![0-9]+]] 7161 // DEBUG1-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG373:![0-9]+]] 7162 // DEBUG1-NEXT: ret void, !dbg [[DBG374:![0-9]+]] 7163 // 7164 // 7165 // DEBUG1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp 7166 // DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG375:![0-9]+]] { 7167 // DEBUG1-NEXT: entry: 7168 // DEBUG1-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG376:![0-9]+]] 7169 // DEBUG1-NEXT: call void @.__omp_threadprivate_init_.(), !dbg [[DBG376]] 7170 // DEBUG1-NEXT: call void @__cxx_global_var_init.4(), !dbg [[DBG376]] 7171 // DEBUG1-NEXT: call void @__cxx_global_var_init.5(), !dbg [[DBG376]] 7172 // DEBUG1-NEXT: call void @.__omp_threadprivate_init_..3(), !dbg [[DBG376]] 7173 // DEBUG1-NEXT: ret void 7174 // 7175 // 7176 // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_var_init 7177 // DEBUG2-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG116:![0-9]+]] { 7178 // DEBUG2-NEXT: entry: 7179 // DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]), !dbg [[DBG119:![0-9]+]] 7180 // DEBUG2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZL3gs1, ptr @.__kmpc_global_ctor_., ptr null, ptr @.__kmpc_global_dtor_.), !dbg [[DBG119]] 7181 // DEBUG2-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG120:![0-9]+]] 7182 // DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG119]] 7183 // DEBUG2-NEXT: ret void, !dbg [[DBG122:![0-9]+]] 7184 // 7185 // 7186 // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_. 7187 // DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG123:![0-9]+]] { 7188 // DEBUG2-NEXT: entry: 7189 // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 7190 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 7191 // DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META125:![0-9]+]], !DIExpression(), [[META127:![0-9]+]]) 7192 // DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG128:![0-9]+]] 7193 // DEBUG2-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 5), !dbg [[DBG129:![0-9]+]] 7194 // DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG128]] 7195 // DEBUG2-NEXT: ret ptr [[TMP2]], !dbg [[DBG128]] 7196 // 7197 // 7198 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1C1Ei 7199 // DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG130:![0-9]+]] { 7200 // DEBUG2-NEXT: entry: 7201 // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7202 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7203 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7204 // DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META131:![0-9]+]], !DIExpression(), [[META133:![0-9]+]]) 7205 // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 7206 // DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META134:![0-9]+]], !DIExpression(), [[META135:![0-9]+]]) 7207 // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7208 // DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG136:![0-9]+]] 7209 // DEBUG2-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG136]] 7210 // DEBUG2-NEXT: ret void, !dbg [[DBG137:![0-9]+]] 7211 // 7212 // 7213 // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_. 7214 // DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG138:![0-9]+]] { 7215 // DEBUG2-NEXT: entry: 7216 // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 7217 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 7218 // DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META139:![0-9]+]], !DIExpression(), [[META140:![0-9]+]]) 7219 // DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META140]] 7220 // DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR3]], !dbg [[META140]] 7221 // DEBUG2-NEXT: ret void, !dbg [[DBG141:![0-9]+]] 7222 // 7223 // 7224 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1D1Ev 7225 // DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG142:![0-9]+]] { 7226 // DEBUG2-NEXT: entry: 7227 // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7228 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7229 // DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META143:![0-9]+]], !DIExpression(), [[META144:![0-9]+]]) 7230 // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7231 // DEBUG2-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG145:![0-9]+]] 7232 // DEBUG2-NEXT: ret void, !dbg [[DBG146:![0-9]+]] 7233 // 7234 // 7235 // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 7236 // DEBUG2-SAME: () #[[ATTR0]] !dbg [[DBG147:![0-9]+]] { 7237 // DEBUG2-NEXT: entry: 7238 // DEBUG2-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG148:![0-9]+]] 7239 // DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG150:![0-9]+]] 7240 // DEBUG2-NEXT: ret void, !dbg [[DBG151:![0-9]+]] 7241 // 7242 // 7243 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2C1Ei 7244 // DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG152:![0-9]+]] { 7245 // DEBUG2-NEXT: entry: 7246 // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7247 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7248 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7249 // DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META153:![0-9]+]], !DIExpression(), [[META155:![0-9]+]]) 7250 // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 7251 // DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META156:![0-9]+]], !DIExpression(), [[META157:![0-9]+]]) 7252 // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7253 // DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG158:![0-9]+]] 7254 // DEBUG2-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG158]] 7255 // DEBUG2-NEXT: ret void, !dbg [[DBG159:![0-9]+]] 7256 // 7257 // 7258 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2D1Ev 7259 // DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG160:![0-9]+]] { 7260 // DEBUG2-NEXT: entry: 7261 // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7262 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7263 // DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META161:![0-9]+]], !DIExpression(), [[META162:![0-9]+]]) 7264 // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7265 // DEBUG2-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG163:![0-9]+]] 7266 // DEBUG2-NEXT: ret void, !dbg [[DBG164:![0-9]+]] 7267 // 7268 // 7269 // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 7270 // DEBUG2-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG165:![0-9]+]] { 7271 // DEBUG2-NEXT: entry: 7272 // DEBUG2-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 7273 // DEBUG2-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 7274 // DEBUG2-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 7275 // DEBUG2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 7276 // DEBUG2-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 7277 // DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]), !dbg [[DBG166:![0-9]+]] 7278 // DEBUG2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB3]], ptr @arr_x, ptr @.__kmpc_global_ctor_..3, ptr null, ptr @.__kmpc_global_dtor_..4), !dbg [[DBG166]] 7279 // DEBUG2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG167:![0-9]+]] 7280 // DEBUG2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG169:![0-9]+]] 7281 // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) 7282 // DEBUG2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG170:![0-9]+]] 7283 // DEBUG2: invoke.cont: 7284 // DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG169]] 7285 // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) 7286 // DEBUG2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG171:![0-9]+]] 7287 // DEBUG2: invoke.cont2: 7288 // DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG169]] 7289 // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) 7290 // DEBUG2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG172:![0-9]+]] 7291 // DEBUG2: invoke.cont3: 7292 // DEBUG2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG167]] 7293 // DEBUG2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG173:![0-9]+]] 7294 // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) 7295 // DEBUG2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG174:![0-9]+]] 7296 // DEBUG2: invoke.cont7: 7297 // DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG173]] 7298 // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) 7299 // DEBUG2-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG175:![0-9]+]] 7300 // DEBUG2: invoke.cont8: 7301 // DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG173]] 7302 // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) 7303 // DEBUG2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG176:![0-9]+]] 7304 // DEBUG2: invoke.cont9: 7305 // DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG166]] 7306 // DEBUG2-NEXT: ret void, !dbg [[DBG166]] 7307 // DEBUG2: lpad: 7308 // DEBUG2-NEXT: [[TMP2:%.*]] = landingpad { ptr, i32 } 7309 // DEBUG2-NEXT: cleanup, !dbg [[DBG177:![0-9]+]] 7310 // DEBUG2-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0, !dbg [[DBG177]] 7311 // DEBUG2-NEXT: store ptr [[TMP3]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG177]] 7312 // DEBUG2-NEXT: [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 1, !dbg [[DBG177]] 7313 // DEBUG2-NEXT: store i32 [[TMP4]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG177]] 7314 // DEBUG2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG169]] 7315 // DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP5]], !dbg [[DBG169]] 7316 // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG169]] 7317 // DEBUG2: arraydestroy.body: 7318 // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG169]] 7319 // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG169]] 7320 // DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG169]] 7321 // DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG169]] 7322 // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG169]] 7323 // DEBUG2: arraydestroy.done4: 7324 // DEBUG2-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG169]] 7325 // DEBUG2: lpad6: 7326 // DEBUG2-NEXT: [[TMP6:%.*]] = landingpad { ptr, i32 } 7327 // DEBUG2-NEXT: cleanup, !dbg [[DBG177]] 7328 // DEBUG2-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP6]], 0, !dbg [[DBG177]] 7329 // DEBUG2-NEXT: store ptr [[TMP7]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG177]] 7330 // DEBUG2-NEXT: [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP6]], 1, !dbg [[DBG177]] 7331 // DEBUG2-NEXT: store i32 [[TMP8]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG177]] 7332 // DEBUG2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG173]] 7333 // DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP9]], !dbg [[DBG173]] 7334 // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG173]] 7335 // DEBUG2: arraydestroy.body11: 7336 // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP9]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG173]] 7337 // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG173]] 7338 // DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG173]] 7339 // DEBUG2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG173]] 7340 // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG173]] 7341 // DEBUG2: arraydestroy.done15: 7342 // DEBUG2-NEXT: br label [[EHCLEANUP]], !dbg [[DBG173]] 7343 // DEBUG2: ehcleanup: 7344 // DEBUG2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG167]] 7345 // DEBUG2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP10]], i64 0, i64 0, !dbg [[DBG167]] 7346 // DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG167]] 7347 // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG167]] 7348 // DEBUG2: arraydestroy.body17: 7349 // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG167]] 7350 // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG167]] 7351 // DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG167]] 7352 // DEBUG2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG167]] 7353 // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG167]] 7354 // DEBUG2: arraydestroy.done21: 7355 // DEBUG2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG167]] 7356 // DEBUG2: eh.resume: 7357 // DEBUG2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG167]] 7358 // DEBUG2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG167]] 7359 // DEBUG2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG167]] 7360 // DEBUG2-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG167]] 7361 // DEBUG2-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG167]] 7362 // 7363 // 7364 // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..3 7365 // DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG178:![0-9]+]] { 7366 // DEBUG2-NEXT: entry: 7367 // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 7368 // DEBUG2-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 7369 // DEBUG2-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 7370 // DEBUG2-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 7371 // DEBUG2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 7372 // DEBUG2-NEXT: [[ARRAYINIT_ENDOFINIT7:%.*]] = alloca ptr, align 8 7373 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 7374 // DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META179:![0-9]+]], !DIExpression(), [[META180:![0-9]+]]) 7375 // DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG181:![0-9]+]] 7376 // DEBUG2-NEXT: store ptr [[TMP1]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG182:![0-9]+]] 7377 // DEBUG2-NEXT: store ptr [[TMP1]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG183:![0-9]+]] 7378 // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 1) 7379 // DEBUG2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG184:![0-9]+]] 7380 // DEBUG2: invoke.cont: 7381 // DEBUG2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 1, !dbg [[DBG183]] 7382 // DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG183]] 7383 // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 7384 // DEBUG2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG185:![0-9]+]] 7385 // DEBUG2: invoke.cont2: 7386 // DEBUG2-NEXT: [[ARRAYINIT_ELEMENT3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP1]], i64 2, !dbg [[DBG183]] 7387 // DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT3]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG183]] 7388 // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT3]], i32 noundef 3) 7389 // DEBUG2-NEXT: to label [[INVOKE_CONT4:%.*]] unwind label [[LPAD]], !dbg [[DBG186:![0-9]+]] 7390 // DEBUG2: invoke.cont4: 7391 // DEBUG2-NEXT: [[ARRAYINIT_ELEMENT6:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP1]], i64 1, !dbg [[DBG182]] 7392 // DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG182]] 7393 // DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG187:![0-9]+]] 7394 // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT6]], i32 noundef 4) 7395 // DEBUG2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD8:%.*]], !dbg [[DBG188:![0-9]+]] 7396 // DEBUG2: invoke.cont9: 7397 // DEBUG2-NEXT: [[ARRAYINIT_ELEMENT10:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT6]], i64 1, !dbg [[DBG187]] 7398 // DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT10]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG187]] 7399 // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT10]], i32 noundef 5) 7400 // DEBUG2-NEXT: to label [[INVOKE_CONT11:%.*]] unwind label [[LPAD8]], !dbg [[DBG189:![0-9]+]] 7401 // DEBUG2: invoke.cont11: 7402 // DEBUG2-NEXT: [[ARRAYINIT_ELEMENT12:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT6]], i64 2, !dbg [[DBG187]] 7403 // DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT12]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG187]] 7404 // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT12]], i32 noundef 6) 7405 // DEBUG2-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[LPAD8]], !dbg [[DBG190:![0-9]+]] 7406 // DEBUG2: invoke.cont13: 7407 // DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG181]] 7408 // DEBUG2-NEXT: ret ptr [[TMP2]], !dbg [[DBG181]] 7409 // DEBUG2: lpad: 7410 // DEBUG2-NEXT: [[TMP3:%.*]] = landingpad { ptr, i32 } 7411 // DEBUG2-NEXT: cleanup, !dbg [[META180]] 7412 // DEBUG2-NEXT: [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 0, !dbg [[META180]] 7413 // DEBUG2-NEXT: store ptr [[TMP4]], ptr [[EXN_SLOT]], align 8, !dbg [[META180]] 7414 // DEBUG2-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 1, !dbg [[META180]] 7415 // DEBUG2-NEXT: store i32 [[TMP5]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[META180]] 7416 // DEBUG2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG183]] 7417 // DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP6]], !dbg [[DBG183]] 7418 // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG183]] 7419 // DEBUG2: arraydestroy.body: 7420 // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG183]] 7421 // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG183]] 7422 // DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG183]] 7423 // DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]], !dbg [[DBG183]] 7424 // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG183]] 7425 // DEBUG2: arraydestroy.done5: 7426 // DEBUG2-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG183]] 7427 // DEBUG2: lpad8: 7428 // DEBUG2-NEXT: [[TMP7:%.*]] = landingpad { ptr, i32 } 7429 // DEBUG2-NEXT: cleanup, !dbg [[META180]] 7430 // DEBUG2-NEXT: [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 0, !dbg [[META180]] 7431 // DEBUG2-NEXT: store ptr [[TMP8]], ptr [[EXN_SLOT]], align 8, !dbg [[META180]] 7432 // DEBUG2-NEXT: [[TMP9:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 1, !dbg [[META180]] 7433 // DEBUG2-NEXT: store i32 [[TMP9]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[META180]] 7434 // DEBUG2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG187]] 7435 // DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY14:%.*]] = icmp eq ptr [[ARRAYINIT_ELEMENT6]], [[TMP10]], !dbg [[DBG187]] 7436 // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY14]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15:%.*]], !dbg [[DBG187]] 7437 // DEBUG2: arraydestroy.body15: 7438 // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi ptr [ [[TMP10]], [[LPAD8]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ], !dbg [[DBG187]] 7439 // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST16]], i64 -1, !dbg [[DBG187]] 7440 // DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]], !dbg [[DBG187]] 7441 // DEBUG2-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT17]], [[ARRAYINIT_ELEMENT6]], !dbg [[DBG187]] 7442 // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_BODY15]], !dbg [[DBG187]] 7443 // DEBUG2: arraydestroy.done19: 7444 // DEBUG2-NEXT: br label [[EHCLEANUP]], !dbg [[DBG187]] 7445 // DEBUG2: ehcleanup: 7446 // DEBUG2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG182]] 7447 // DEBUG2-NEXT: [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP1]], i64 0, i64 0, !dbg [[DBG182]] 7448 // DEBUG2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP11]], i64 0, i64 0, !dbg [[DBG182]] 7449 // DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY20:%.*]] = icmp eq ptr [[PAD_ARRAYBEGIN]], [[PAD_ARRAYEND]], !dbg [[DBG182]] 7450 // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY20]], label [[ARRAYDESTROY_DONE25:%.*]], label [[ARRAYDESTROY_BODY21:%.*]], !dbg [[DBG182]] 7451 // DEBUG2: arraydestroy.body21: 7452 // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST22:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT23:%.*]], [[ARRAYDESTROY_BODY21]] ], !dbg [[DBG182]] 7453 // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT23]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST22]], i64 -1, !dbg [[DBG182]] 7454 // DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT23]]) #[[ATTR3]], !dbg [[DBG182]] 7455 // DEBUG2-NEXT: [[ARRAYDESTROY_DONE24:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT23]], [[PAD_ARRAYBEGIN]], !dbg [[DBG182]] 7456 // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE24]], label [[ARRAYDESTROY_DONE25]], label [[ARRAYDESTROY_BODY21]], !dbg [[DBG182]] 7457 // DEBUG2: arraydestroy.done25: 7458 // DEBUG2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG182]] 7459 // DEBUG2: eh.resume: 7460 // DEBUG2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG182]] 7461 // DEBUG2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG182]] 7462 // DEBUG2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG182]] 7463 // DEBUG2-NEXT: [[LPAD_VAL26:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG182]] 7464 // DEBUG2-NEXT: resume { ptr, i32 } [[LPAD_VAL26]], !dbg [[DBG182]] 7465 // 7466 // 7467 // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..4 7468 // DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG191:![0-9]+]] { 7469 // DEBUG2-NEXT: entry: 7470 // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 7471 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 7472 // DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META192:![0-9]+]], !DIExpression(), [[META193:![0-9]+]]) 7473 // DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META193]] 7474 // DEBUG2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 6, !dbg [[META193]] 7475 // DEBUG2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META193]] 7476 // DEBUG2: arraydestroy.body: 7477 // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META193]] 7478 // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META193]] 7479 // DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META193]] 7480 // DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]], !dbg [[META193]] 7481 // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META193]] 7482 // DEBUG2: arraydestroy.done1: 7483 // DEBUG2-NEXT: ret void, !dbg [[DBG194:![0-9]+]] 7484 // 7485 // 7486 // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 7487 // DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG195:![0-9]+]] { 7488 // DEBUG2-NEXT: entry: 7489 // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 7490 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 7491 // DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META198:![0-9]+]], !DIExpression(), [[META199:![0-9]+]]) 7492 // DEBUG2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META199]] 7493 // DEBUG2: arraydestroy.body: 7494 // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META199]] 7495 // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META199]] 7496 // DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META199]] 7497 // DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[META199]] 7498 // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META199]] 7499 // DEBUG2: arraydestroy.done1: 7500 // DEBUG2-NEXT: ret void, !dbg [[META199]] 7501 // 7502 // 7503 // DEBUG2-LABEL: define {{[^@]+}}@main 7504 // DEBUG2-SAME: () #[[ATTR4:[0-9]+]] personality ptr @__gxx_personality_v0 !dbg [[DBG52:![0-9]+]] { 7505 // DEBUG2-NEXT: entry: 7506 // DEBUG2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 7507 // DEBUG2-NEXT: [[RES:%.*]] = alloca i32, align 4 7508 // DEBUG2-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 7509 // DEBUG2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 7510 // DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9:[0-9]+]]), !dbg [[DBG200:![0-9]+]] 7511 // DEBUG2-NEXT: store i32 0, ptr [[RETVAL]], align 4 7512 // DEBUG2-NEXT: #dbg_declare(ptr [[RES]], [[META201:![0-9]+]], !DIExpression(), [[META202:![0-9]+]]) 7513 // DEBUG2-NEXT: [[TMP1:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG203:![0-9]+]] 7514 // DEBUG2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP1]], 0, !dbg [[DBG203]] 7515 // DEBUG2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG203]], !prof [[PROF204:![0-9]+]] 7516 // DEBUG2: init.check: 7517 // DEBUG2-NEXT: [[TMP2:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG203]] 7518 // DEBUG2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0, !dbg [[DBG203]] 7519 // DEBUG2-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG203]] 7520 // DEBUG2: init: 7521 // DEBUG2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]]), !dbg [[DBG203]] 7522 // DEBUG2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB7]], ptr @_ZZ4mainE2sm, ptr @.__kmpc_global_ctor_..5, ptr null, ptr @.__kmpc_global_dtor_..6), !dbg [[DBG203]] 7523 // DEBUG2-NEXT: [[TMP4:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB9]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG200]] 7524 // DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG205:![0-9]+]] 7525 // DEBUG2-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG205]] 7526 // DEBUG2-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP5]]) 7527 // DEBUG2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG206:![0-9]+]] 7528 // DEBUG2: invoke.cont: 7529 // DEBUG2-NEXT: [[TMP6:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG203]] 7530 // DEBUG2-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG203]] 7531 // DEBUG2-NEXT: br label [[INIT_END]], !dbg [[DBG203]] 7532 // DEBUG2: init.end: 7533 // DEBUG2-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB11:[0-9]+]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG207:![0-9]+]] 7534 // DEBUG2-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG208:![0-9]+]] 7535 // DEBUG2-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG208]] 7536 // DEBUG2-NEXT: store i32 [[TMP8]], ptr [[RES]], align 4, !dbg [[DBG209:![0-9]+]] 7537 // DEBUG2-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB13:[0-9]+]], i32 [[TMP0]], ptr @_ZZ4mainE2sm, i64 24, ptr @_ZZ4mainE2sm.cache.), !dbg [[DBG210:![0-9]+]] 7538 // DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG211:![0-9]+]] 7539 // DEBUG2-NEXT: [[TMP10:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG211]] 7540 // DEBUG2-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG212:![0-9]+]] 7541 // DEBUG2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG212]] 7542 // DEBUG2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG212]] 7543 // DEBUG2-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB15:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG213:![0-9]+]] 7544 // DEBUG2-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP12]], i32 0, i32 0, !dbg [[DBG214:![0-9]+]] 7545 // DEBUG2-NEXT: [[TMP13:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG214]] 7546 // DEBUG2-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG215:![0-9]+]] 7547 // DEBUG2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG215]] 7548 // DEBUG2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG215]] 7549 // DEBUG2-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG216:![0-9]+]] 7550 // DEBUG2-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG217:![0-9]+]] 7551 // DEBUG2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG217]] 7552 // DEBUG2-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG217]] 7553 // DEBUG2-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB17:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG218:![0-9]+]] 7554 // DEBUG2-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP17]], i32 0, i32 0, !dbg [[DBG219:![0-9]+]] 7555 // DEBUG2-NEXT: [[TMP18:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG219]] 7556 // DEBUG2-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG220:![0-9]+]] 7557 // DEBUG2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG220]] 7558 // DEBUG2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG220]] 7559 // DEBUG2-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB19:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG221:![0-9]+]] 7560 // DEBUG2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], i64 0, i64 1, !dbg [[DBG221]] 7561 // DEBUG2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG221]] 7562 // DEBUG2-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG222:![0-9]+]] 7563 // DEBUG2-NEXT: [[TMP21:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG222]] 7564 // DEBUG2-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG223:![0-9]+]] 7565 // DEBUG2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG223]] 7566 // DEBUG2-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG223]] 7567 // DEBUG2-NEXT: [[TMP23:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB21:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG224:![0-9]+]] 7568 // DEBUG2-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4, !dbg [[DBG224]] 7569 // DEBUG2-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG225:![0-9]+]] 7570 // DEBUG2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP25]], [[TMP24]], !dbg [[DBG225]] 7571 // DEBUG2-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG225]] 7572 // DEBUG2-NEXT: [[TMP26:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB23:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG226:![0-9]+]] 7573 // DEBUG2-NEXT: [[TMP27:%.*]] = load float, ptr [[TMP26]], align 4, !dbg [[DBG226]] 7574 // DEBUG2-NEXT: [[CONV:%.*]] = fptosi float [[TMP27]] to i32, !dbg [[DBG226]] 7575 // DEBUG2-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG227:![0-9]+]] 7576 // DEBUG2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[CONV]], !dbg [[DBG227]] 7577 // DEBUG2-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG227]] 7578 // DEBUG2-NEXT: [[TMP29:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB25:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG228:![0-9]+]] 7579 // DEBUG2-NEXT: [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP29]], i32 0, i32 0, !dbg [[DBG229:![0-9]+]] 7580 // DEBUG2-NEXT: [[TMP30:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG229]] 7581 // DEBUG2-NEXT: [[TMP31:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG230:![0-9]+]] 7582 // DEBUG2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP31]], [[TMP30]], !dbg [[DBG230]] 7583 // DEBUG2-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG230]] 7584 // DEBUG2-NEXT: [[TMP32:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]] 7585 // DEBUG2-NEXT: ret i32 [[TMP32]], !dbg [[DBG232:![0-9]+]] 7586 // DEBUG2: lpad: 7587 // DEBUG2-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 } 7588 // DEBUG2-NEXT: cleanup, !dbg [[DBG233:![0-9]+]] 7589 // DEBUG2-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0, !dbg [[DBG233]] 7590 // DEBUG2-NEXT: store ptr [[TMP34]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG233]] 7591 // DEBUG2-NEXT: [[TMP35:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 1, !dbg [[DBG233]] 7592 // DEBUG2-NEXT: store i32 [[TMP35]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG233]] 7593 // DEBUG2-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG203]] 7594 // DEBUG2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG203]] 7595 // DEBUG2: eh.resume: 7596 // DEBUG2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG203]] 7597 // DEBUG2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG203]] 7598 // DEBUG2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG203]] 7599 // DEBUG2-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG203]] 7600 // DEBUG2-NEXT: resume { ptr, i32 } [[LPAD_VAL15]], !dbg [[DBG203]] 7601 // 7602 // 7603 // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..5 7604 // DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG234:![0-9]+]] { 7605 // DEBUG2-NEXT: entry: 7606 // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 7607 // DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB5:[0-9]+]]), !dbg [[DBG235:![0-9]+]] 7608 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 7609 // DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META236:![0-9]+]], !DIExpression(), [[META237:![0-9]+]]) 7610 // DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG238:![0-9]+]] 7611 // DEBUG2-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB5]], i32 [[TMP1]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG235]] 7612 // DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG239:![0-9]+]] 7613 // DEBUG2-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG239]] 7614 // DEBUG2-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) [[TMP2]], i32 noundef [[TMP4]]), !dbg [[DBG240:![0-9]+]] 7615 // DEBUG2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG238]] 7616 // DEBUG2-NEXT: ret ptr [[TMP5]], !dbg [[DBG238]] 7617 // 7618 // 7619 // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei 7620 // DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG241:![0-9]+]] { 7621 // DEBUG2-NEXT: entry: 7622 // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7623 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7624 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7625 // DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META242:![0-9]+]], !DIExpression(), [[META244:![0-9]+]]) 7626 // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 7627 // DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META245:![0-9]+]], !DIExpression(), [[META246:![0-9]+]]) 7628 // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7629 // DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG247:![0-9]+]] 7630 // DEBUG2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG247]] 7631 // DEBUG2-NEXT: ret void, !dbg [[DBG248:![0-9]+]] 7632 // 7633 // 7634 // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..6 7635 // DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG249:![0-9]+]] { 7636 // DEBUG2-NEXT: entry: 7637 // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 7638 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 7639 // DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META250:![0-9]+]], !DIExpression(), [[META251:![0-9]+]]) 7640 // DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META251]] 7641 // DEBUG2-NEXT: call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[TMP1]]) #[[ATTR3]], !dbg [[META251]] 7642 // DEBUG2-NEXT: ret void, !dbg [[DBG252:![0-9]+]] 7643 // 7644 // 7645 // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev 7646 // DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG253:![0-9]+]] { 7647 // DEBUG2-NEXT: entry: 7648 // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7649 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7650 // DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META254:![0-9]+]], !DIExpression(), [[META255:![0-9]+]]) 7651 // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7652 // DEBUG2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG256:![0-9]+]] 7653 // DEBUG2-NEXT: ret void, !dbg [[DBG257:![0-9]+]] 7654 // 7655 // 7656 // DEBUG2-LABEL: define {{[^@]+}}@_Z6foobarv 7657 // DEBUG2-SAME: () #[[ATTR2]] !dbg [[DBG258:![0-9]+]] { 7658 // DEBUG2-NEXT: entry: 7659 // DEBUG2-NEXT: [[RES:%.*]] = alloca i32, align 4 7660 // DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB27:[0-9]+]]), !dbg [[DBG259:![0-9]+]] 7661 // DEBUG2-NEXT: #dbg_declare(ptr [[RES]], [[META260:![0-9]+]], !DIExpression(), [[META261:![0-9]+]]) 7662 // DEBUG2-NEXT: [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB27]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG259]] 7663 // DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG262:![0-9]+]] 7664 // DEBUG2-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG262]] 7665 // DEBUG2-NEXT: store i32 [[TMP2]], ptr [[RES]], align 4, !dbg [[DBG263:![0-9]+]] 7666 // DEBUG2-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB29:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG264:![0-9]+]] 7667 // DEBUG2-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG265:![0-9]+]] 7668 // DEBUG2-NEXT: [[TMP4:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG265]] 7669 // DEBUG2-NEXT: [[TMP5:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG266:![0-9]+]] 7670 // DEBUG2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]], !dbg [[DBG266]] 7671 // DEBUG2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG266]] 7672 // DEBUG2-NEXT: [[TMP6:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG267:![0-9]+]] 7673 // DEBUG2-NEXT: [[TMP7:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG268:![0-9]+]] 7674 // DEBUG2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], [[TMP6]], !dbg [[DBG268]] 7675 // DEBUG2-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG268]] 7676 // DEBUG2-NEXT: [[TMP8:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB31:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG269:![0-9]+]] 7677 // DEBUG2-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP8]], i32 0, i32 0, !dbg [[DBG270:![0-9]+]] 7678 // DEBUG2-NEXT: [[TMP9:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG270]] 7679 // DEBUG2-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG271:![0-9]+]] 7680 // DEBUG2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG271]] 7681 // DEBUG2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG271]] 7682 // DEBUG2-NEXT: [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB33:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG272:![0-9]+]] 7683 // DEBUG2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], i64 0, i64 1, !dbg [[DBG272]] 7684 // DEBUG2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG272]] 7685 // DEBUG2-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG273:![0-9]+]] 7686 // DEBUG2-NEXT: [[TMP12:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG273]] 7687 // DEBUG2-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG274:![0-9]+]] 7688 // DEBUG2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG274]] 7689 // DEBUG2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG274]] 7690 // DEBUG2-NEXT: [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB35:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG275:![0-9]+]] 7691 // DEBUG2-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4, !dbg [[DBG275]] 7692 // DEBUG2-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG276:![0-9]+]] 7693 // DEBUG2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG276]] 7694 // DEBUG2-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG276]] 7695 // DEBUG2-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB37:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG277:![0-9]+]] 7696 // DEBUG2-NEXT: [[TMP18:%.*]] = load float, ptr [[TMP17]], align 4, !dbg [[DBG277]] 7697 // DEBUG2-NEXT: [[CONV:%.*]] = fptosi float [[TMP18]] to i32, !dbg [[DBG277]] 7698 // DEBUG2-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG278:![0-9]+]] 7699 // DEBUG2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], [[CONV]], !dbg [[DBG278]] 7700 // DEBUG2-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG278]] 7701 // DEBUG2-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB39:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG279:![0-9]+]] 7702 // DEBUG2-NEXT: [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP20]], i32 0, i32 0, !dbg [[DBG280:![0-9]+]] 7703 // DEBUG2-NEXT: [[TMP21:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG280]] 7704 // DEBUG2-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG281:![0-9]+]] 7705 // DEBUG2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG281]] 7706 // DEBUG2-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG281]] 7707 // DEBUG2-NEXT: [[TMP23:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG282:![0-9]+]] 7708 // DEBUG2-NEXT: ret i32 [[TMP23]], !dbg [[DBG283:![0-9]+]] 7709 // 7710 // 7711 // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_var_init.7 7712 // DEBUG2-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG284:![0-9]+]] { 7713 // DEBUG2-NEXT: entry: 7714 // DEBUG2-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG285:![0-9]+]] 7715 // DEBUG2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG285]] 7716 // DEBUG2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG285]] 7717 // DEBUG2: init.check: 7718 // DEBUG2-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG285]] 7719 // DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB41:[0-9]+]]), !dbg [[DBG285]] 7720 // DEBUG2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB41]], ptr @_ZN2STI2S4E2stE, ptr @.__kmpc_global_ctor_..8, ptr null, ptr @.__kmpc_global_dtor_..9), !dbg [[DBG285]] 7721 // DEBUG2-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG286:![0-9]+]] 7722 // DEBUG2-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG285]] 7723 // DEBUG2-NEXT: br label [[INIT_END]], !dbg [[DBG285]] 7724 // DEBUG2: init.end: 7725 // DEBUG2-NEXT: ret void, !dbg [[DBG288:![0-9]+]] 7726 // 7727 // 7728 // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..8 7729 // DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG289:![0-9]+]] { 7730 // DEBUG2-NEXT: entry: 7731 // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 7732 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 7733 // DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META290:![0-9]+]], !DIExpression(), [[META291:![0-9]+]]) 7734 // DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG292:![0-9]+]] 7735 // DEBUG2-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]], i32 noundef 23), !dbg [[DBG293:![0-9]+]] 7736 // DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG292]] 7737 // DEBUG2-NEXT: ret ptr [[TMP2]], !dbg [[DBG292]] 7738 // 7739 // 7740 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4C1Ei 7741 // DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG294:![0-9]+]] { 7742 // DEBUG2-NEXT: entry: 7743 // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7744 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7745 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7746 // DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META295:![0-9]+]], !DIExpression(), [[META297:![0-9]+]]) 7747 // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 7748 // DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META298:![0-9]+]], !DIExpression(), [[META299:![0-9]+]]) 7749 // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7750 // DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG300:![0-9]+]] 7751 // DEBUG2-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG300]] 7752 // DEBUG2-NEXT: ret void, !dbg [[DBG301:![0-9]+]] 7753 // 7754 // 7755 // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..9 7756 // DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG302:![0-9]+]] { 7757 // DEBUG2-NEXT: entry: 7758 // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 7759 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 7760 // DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META303:![0-9]+]], !DIExpression(), [[META304:![0-9]+]]) 7761 // DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META304]] 7762 // DEBUG2-NEXT: call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]]) #[[ATTR3]], !dbg [[META304]] 7763 // DEBUG2-NEXT: ret void, !dbg [[DBG305:![0-9]+]] 7764 // 7765 // 7766 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4D1Ev 7767 // DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG306:![0-9]+]] { 7768 // DEBUG2-NEXT: entry: 7769 // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7770 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7771 // DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META307:![0-9]+]], !DIExpression(), [[META308:![0-9]+]]) 7772 // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7773 // DEBUG2-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG309:![0-9]+]] 7774 // DEBUG2-NEXT: ret void, !dbg [[DBG310:![0-9]+]] 7775 // 7776 // 7777 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1C2Ei 7778 // DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG311:![0-9]+]] { 7779 // DEBUG2-NEXT: entry: 7780 // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7781 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7782 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7783 // DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META312:![0-9]+]], !DIExpression(), [[META313:![0-9]+]]) 7784 // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 7785 // DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META314:![0-9]+]], !DIExpression(), [[META315:![0-9]+]]) 7786 // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7787 // DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG316:![0-9]+]] 7788 // DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG317:![0-9]+]] 7789 // DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG316]] 7790 // DEBUG2-NEXT: ret void, !dbg [[DBG318:![0-9]+]] 7791 // 7792 // 7793 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1D2Ev 7794 // DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG319:![0-9]+]] { 7795 // DEBUG2-NEXT: entry: 7796 // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7797 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7798 // DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META320:![0-9]+]], !DIExpression(), [[META321:![0-9]+]]) 7799 // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7800 // DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG322:![0-9]+]] 7801 // DEBUG2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG324:![0-9]+]] 7802 // DEBUG2-NEXT: ret void, !dbg [[DBG325:![0-9]+]] 7803 // 7804 // 7805 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2C2Ei 7806 // DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG326:![0-9]+]] { 7807 // DEBUG2-NEXT: entry: 7808 // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7809 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7810 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7811 // DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META327:![0-9]+]], !DIExpression(), [[META328:![0-9]+]]) 7812 // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 7813 // DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META329:![0-9]+]], !DIExpression(), [[META330:![0-9]+]]) 7814 // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7815 // DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG331:![0-9]+]] 7816 // DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG332:![0-9]+]] 7817 // DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG331]] 7818 // DEBUG2-NEXT: ret void, !dbg [[DBG333:![0-9]+]] 7819 // 7820 // 7821 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2D2Ev 7822 // DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG334:![0-9]+]] { 7823 // DEBUG2-NEXT: entry: 7824 // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7825 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7826 // DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META335:![0-9]+]], !DIExpression(), [[META336:![0-9]+]]) 7827 // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7828 // DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG337:![0-9]+]] 7829 // DEBUG2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG339:![0-9]+]] 7830 // DEBUG2-NEXT: ret void, !dbg [[DBG340:![0-9]+]] 7831 // 7832 // 7833 // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei 7834 // DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG341:![0-9]+]] { 7835 // DEBUG2-NEXT: entry: 7836 // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7837 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7838 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7839 // DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META342:![0-9]+]], !DIExpression(), [[META343:![0-9]+]]) 7840 // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 7841 // DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META344:![0-9]+]], !DIExpression(), [[META345:![0-9]+]]) 7842 // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7843 // DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG346:![0-9]+]] 7844 // DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG347:![0-9]+]] 7845 // DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG346]] 7846 // DEBUG2-NEXT: ret void, !dbg [[DBG348:![0-9]+]] 7847 // 7848 // 7849 // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev 7850 // DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG349:![0-9]+]] { 7851 // DEBUG2-NEXT: entry: 7852 // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7853 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7854 // DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META350:![0-9]+]], !DIExpression(), [[META351:![0-9]+]]) 7855 // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7856 // DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG352:![0-9]+]] 7857 // DEBUG2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG354:![0-9]+]] 7858 // DEBUG2-NEXT: ret void, !dbg [[DBG355:![0-9]+]] 7859 // 7860 // 7861 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4C2Ei 7862 // DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG356:![0-9]+]] { 7863 // DEBUG2-NEXT: entry: 7864 // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7865 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7866 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7867 // DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META357:![0-9]+]], !DIExpression(), [[META358:![0-9]+]]) 7868 // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 7869 // DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META359:![0-9]+]], !DIExpression(), [[META360:![0-9]+]]) 7870 // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7871 // DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG361:![0-9]+]] 7872 // DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG362:![0-9]+]] 7873 // DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG361]] 7874 // DEBUG2-NEXT: ret void, !dbg [[DBG363:![0-9]+]] 7875 // 7876 // 7877 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4D2Ev 7878 // DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG364:![0-9]+]] { 7879 // DEBUG2-NEXT: entry: 7880 // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7881 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7882 // DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META365:![0-9]+]], !DIExpression(), [[META366:![0-9]+]]) 7883 // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7884 // DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG367:![0-9]+]] 7885 // DEBUG2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG369:![0-9]+]] 7886 // DEBUG2-NEXT: ret void, !dbg [[DBG370:![0-9]+]] 7887 // 7888 // 7889 // DEBUG2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp 7890 // DEBUG2-SAME: () #[[ATTR0]] !dbg [[DBG371:![0-9]+]] { 7891 // DEBUG2-NEXT: entry: 7892 // DEBUG2-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG372:![0-9]+]] 7893 // DEBUG2-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG372]] 7894 // DEBUG2-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG372]] 7895 // DEBUG2-NEXT: ret void 7896 // 7897