1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target 57 #pragma omp teams loop private(t_var, vec, s_arr, var) 58 for (int i = 0; i < 2; ++i) { 59 vec[i] = t_var; 60 s_arr[i] = var; 61 } 62 return T(); 63 } 64 65 S<float> test; 66 int t_var = 333; 67 int vec[] = {1, 2}; 68 S<float> s_arr[] = {1, 2}; 69 S<float> var(3); 70 71 int main() { 72 static int sivar; 73 #ifdef LAMBDA 74 [&]() { 75 #pragma omp target 76 #pragma omp teams loop private(g, g1, sivar) 77 for (int i = 0; i < 2; ++i) { 78 79 // Skip global, bound tid and loop vars 80 81 g = 1; 82 g1 = 1; 83 sivar = 2; 84 85 // Skip global, bound tid and loop vars 86 [&]() { 87 g = 2; 88 g1 = 2; 89 sivar = 4; 90 91 }(); 92 } 93 }(); 94 return 0; 95 #else 96 #pragma omp target 97 #pragma omp teams loop private(t_var, vec, s_arr, var, sivar) 98 for (int i = 0; i < 2; ++i) { 99 vec[i] = t_var; 100 s_arr[i] = var; 101 sivar += i; 102 } 103 return tmain<int>(); 104 #endif 105 } 106 107 108 109 // Skip global, bound tid and loop vars 110 111 // private(s_arr) 112 113 // private(var) 114 115 116 // Skip global, bound tid and loop vars 117 118 // private(s_arr) 119 120 // private(var) 121 122 123 124 125 // Skip global, bound tid and loop vars 126 127 // private(s_arr) 128 129 130 // private(var) 131 132 133 // Skip global, bound tid and loop vars 134 // prev lb and ub 135 // iter variables 136 137 // private(s_arr) 138 139 140 // private(var) 141 142 143 144 #endif 145 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 146 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 147 // CHECK1-NEXT: entry: 148 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 149 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 150 // CHECK1-NEXT: ret void 151 // 152 // 153 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 154 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 155 // CHECK1-NEXT: entry: 156 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 157 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 158 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 159 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 160 // CHECK1-NEXT: ret void 161 // 162 // 163 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 164 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 165 // CHECK1-NEXT: entry: 166 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 167 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 168 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 169 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 170 // CHECK1-NEXT: ret void 171 // 172 // 173 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 174 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 175 // CHECK1-NEXT: entry: 176 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 177 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 178 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 179 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 180 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 181 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 182 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 183 // CHECK1-NEXT: ret void 184 // 185 // 186 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 187 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 188 // CHECK1-NEXT: entry: 189 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 190 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 191 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 192 // CHECK1-NEXT: ret void 193 // 194 // 195 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 196 // CHECK1-SAME: () #[[ATTR0]] { 197 // CHECK1-NEXT: entry: 198 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 199 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 200 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 201 // CHECK1-NEXT: ret void 202 // 203 // 204 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 205 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 206 // CHECK1-NEXT: entry: 207 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 208 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 209 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 210 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 211 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 212 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 213 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 214 // CHECK1-NEXT: ret void 215 // 216 // 217 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 218 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 219 // CHECK1-NEXT: entry: 220 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 221 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 222 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 223 // CHECK1: arraydestroy.body: 224 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 225 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 226 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 227 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 228 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 229 // CHECK1: arraydestroy.done1: 230 // CHECK1-NEXT: ret void 231 // 232 // 233 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 234 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 235 // CHECK1-NEXT: entry: 236 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 237 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 238 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 239 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 240 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 241 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 242 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 243 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 244 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 245 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 246 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 247 // CHECK1-NEXT: ret void 248 // 249 // 250 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 251 // CHECK1-SAME: () #[[ATTR0]] { 252 // CHECK1-NEXT: entry: 253 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 254 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 255 // CHECK1-NEXT: ret void 256 // 257 // 258 // CHECK1-LABEL: define {{[^@]+}}@main 259 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 260 // CHECK1-NEXT: entry: 261 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 262 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 263 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 264 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 265 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 266 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 267 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 268 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 269 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 270 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 271 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 272 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 273 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 274 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 275 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 276 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 277 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 278 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 279 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 280 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 281 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 282 // CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8 283 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 284 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 285 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 286 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 287 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 288 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 289 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 290 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 291 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, ptr [[KERNEL_ARGS]]) 292 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 293 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 294 // CHECK1: omp_offload.failed: 295 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96() #[[ATTR2]] 296 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 297 // CHECK1: omp_offload.cont: 298 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 299 // CHECK1-NEXT: ret i32 [[CALL]] 300 // 301 // 302 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 303 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 304 // CHECK1-NEXT: entry: 305 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined) 306 // CHECK1-NEXT: ret void 307 // 308 // 309 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined 310 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 311 // CHECK1-NEXT: entry: 312 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 313 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 314 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 315 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 316 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 317 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 318 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 319 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 320 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 321 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 322 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 323 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 324 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 325 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 326 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 327 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 328 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 329 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 330 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 331 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 332 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 333 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 334 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 335 // CHECK1: arrayctor.loop: 336 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 337 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 338 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 339 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 340 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 341 // CHECK1: arrayctor.cont: 342 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 343 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 344 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 345 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 346 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 347 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 348 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 349 // CHECK1: cond.true: 350 // CHECK1-NEXT: br label [[COND_END:%.*]] 351 // CHECK1: cond.false: 352 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 353 // CHECK1-NEXT: br label [[COND_END]] 354 // CHECK1: cond.end: 355 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 356 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 357 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 358 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 359 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 360 // CHECK1: omp.inner.for.cond: 361 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 362 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 363 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 364 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 365 // CHECK1: omp.inner.for.cond.cleanup: 366 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 367 // CHECK1: omp.inner.for.body: 368 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 369 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 370 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 371 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 372 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 373 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 374 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 375 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 376 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 377 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 378 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 379 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] 380 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) 381 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 382 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 383 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 384 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[SIVAR]], align 4 385 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 386 // CHECK1: omp.body.continue: 387 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 388 // CHECK1: omp.inner.for.inc: 389 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 390 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 391 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 392 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 393 // CHECK1: omp.inner.for.end: 394 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 395 // CHECK1: omp.loop.exit: 396 // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 397 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 398 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) 399 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 400 // CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 401 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2 402 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 403 // CHECK1: arraydestroy.body: 404 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 405 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 406 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 407 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 408 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 409 // CHECK1: arraydestroy.done7: 410 // CHECK1-NEXT: ret void 411 // 412 // 413 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 414 // CHECK1-SAME: () #[[ATTR1]] comdat { 415 // CHECK1-NEXT: entry: 416 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 417 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 418 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 419 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 420 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 421 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 422 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 423 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 424 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 425 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 426 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 427 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 428 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 429 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 430 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 431 // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 432 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 433 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 434 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 435 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 436 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 437 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 438 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 439 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 440 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 441 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 442 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 443 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 444 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 445 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 446 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 447 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 448 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 449 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 450 // CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8 451 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 452 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 453 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 454 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 455 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 456 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 457 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 458 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 459 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 460 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 461 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 462 // CHECK1: omp_offload.failed: 463 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 464 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 465 // CHECK1: omp_offload.cont: 466 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 467 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 468 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 469 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 470 // CHECK1: arraydestroy.body: 471 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 472 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 473 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 474 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 475 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 476 // CHECK1: arraydestroy.done2: 477 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 478 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 479 // CHECK1-NEXT: ret i32 [[TMP16]] 480 // 481 // 482 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 483 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 484 // CHECK1-NEXT: entry: 485 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 486 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 487 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 488 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 489 // CHECK1-NEXT: ret void 490 // 491 // 492 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 493 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 494 // CHECK1-NEXT: entry: 495 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 496 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 497 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 498 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 499 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 500 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 501 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 502 // CHECK1-NEXT: ret void 503 // 504 // 505 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 506 // CHECK1-SAME: () #[[ATTR4]] { 507 // CHECK1-NEXT: entry: 508 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined) 509 // CHECK1-NEXT: ret void 510 // 511 // 512 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 513 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 514 // CHECK1-NEXT: entry: 515 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 516 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 517 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 518 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 519 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 520 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 521 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 522 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 523 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 524 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 525 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 526 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 527 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 528 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 529 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 530 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 531 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 532 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 533 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 534 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 535 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 536 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 537 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 538 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 539 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 540 // CHECK1: arrayctor.loop: 541 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 542 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 543 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 544 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 545 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 546 // CHECK1: arrayctor.cont: 547 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 548 // CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 8 549 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 550 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 551 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 552 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 553 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 554 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 555 // CHECK1: cond.true: 556 // CHECK1-NEXT: br label [[COND_END:%.*]] 557 // CHECK1: cond.false: 558 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 559 // CHECK1-NEXT: br label [[COND_END]] 560 // CHECK1: cond.end: 561 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 562 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 563 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 564 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 565 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 566 // CHECK1: omp.inner.for.cond: 567 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 568 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 569 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 570 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 571 // CHECK1: omp.inner.for.cond.cleanup: 572 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 573 // CHECK1: omp.inner.for.body: 574 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 575 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 576 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 577 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 578 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 579 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 580 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 581 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 582 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 583 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 584 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 585 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 586 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] 587 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) 588 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 589 // CHECK1: omp.body.continue: 590 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 591 // CHECK1: omp.inner.for.inc: 592 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 593 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 594 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 595 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 596 // CHECK1: omp.inner.for.end: 597 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 598 // CHECK1: omp.loop.exit: 599 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 600 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 601 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 602 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 603 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 604 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 605 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 606 // CHECK1: arraydestroy.body: 607 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 608 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 609 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 610 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 611 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 612 // CHECK1: arraydestroy.done8: 613 // CHECK1-NEXT: ret void 614 // 615 // 616 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 617 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 618 // CHECK1-NEXT: entry: 619 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 620 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 621 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 622 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 623 // CHECK1-NEXT: ret void 624 // 625 // 626 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 627 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 628 // CHECK1-NEXT: entry: 629 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 630 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 631 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 632 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 633 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 634 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 635 // CHECK1-NEXT: ret void 636 // 637 // 638 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 639 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 640 // CHECK1-NEXT: entry: 641 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 642 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 643 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 644 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 645 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 646 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 647 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 648 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 649 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 650 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 651 // CHECK1-NEXT: ret void 652 // 653 // 654 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 655 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 656 // CHECK1-NEXT: entry: 657 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 658 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 659 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 660 // CHECK1-NEXT: ret void 661 // 662 // 663 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_generic_loop_private_codegen.cpp 664 // CHECK1-SAME: () #[[ATTR0]] { 665 // CHECK1-NEXT: entry: 666 // CHECK1-NEXT: call void @__cxx_global_var_init() 667 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 668 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 669 // CHECK1-NEXT: ret void 670 // 671 // 672 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 673 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 674 // CHECK3-NEXT: entry: 675 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 676 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 677 // CHECK3-NEXT: ret void 678 // 679 // 680 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 681 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 682 // CHECK3-NEXT: entry: 683 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 684 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 685 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 686 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 687 // CHECK3-NEXT: ret void 688 // 689 // 690 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 691 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 692 // CHECK3-NEXT: entry: 693 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 694 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 695 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 696 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 697 // CHECK3-NEXT: ret void 698 // 699 // 700 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 701 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 702 // CHECK3-NEXT: entry: 703 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 704 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 705 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 706 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 707 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 708 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 709 // CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4 710 // CHECK3-NEXT: ret void 711 // 712 // 713 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 714 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 715 // CHECK3-NEXT: entry: 716 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 717 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 718 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 719 // CHECK3-NEXT: ret void 720 // 721 // 722 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 723 // CHECK3-SAME: () #[[ATTR0]] { 724 // CHECK3-NEXT: entry: 725 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 726 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 727 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 728 // CHECK3-NEXT: ret void 729 // 730 // 731 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 732 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 733 // CHECK3-NEXT: entry: 734 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 735 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 736 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 737 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 738 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 739 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 740 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 741 // CHECK3-NEXT: ret void 742 // 743 // 744 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 745 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 746 // CHECK3-NEXT: entry: 747 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 748 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 749 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 750 // CHECK3: arraydestroy.body: 751 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 752 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 753 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 754 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 755 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 756 // CHECK3: arraydestroy.done1: 757 // CHECK3-NEXT: ret void 758 // 759 // 760 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 761 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 762 // CHECK3-NEXT: entry: 763 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 764 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 765 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 766 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 767 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 768 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 769 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 770 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 771 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 772 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 773 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 774 // CHECK3-NEXT: ret void 775 // 776 // 777 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 778 // CHECK3-SAME: () #[[ATTR0]] { 779 // CHECK3-NEXT: entry: 780 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 781 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 782 // CHECK3-NEXT: ret void 783 // 784 // 785 // CHECK3-LABEL: define {{[^@]+}}@main 786 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 787 // CHECK3-NEXT: entry: 788 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 789 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 790 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 791 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 792 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 793 // CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4 794 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 795 // CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4 796 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 797 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 798 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 799 // CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4 800 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 801 // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 802 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 803 // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 804 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 805 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 806 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 807 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 808 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 809 // CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8 810 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 811 // CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8 812 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 813 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 814 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 815 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 816 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 817 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 818 // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, ptr [[KERNEL_ARGS]]) 819 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 820 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 821 // CHECK3: omp_offload.failed: 822 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96() #[[ATTR2]] 823 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 824 // CHECK3: omp_offload.cont: 825 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 826 // CHECK3-NEXT: ret i32 [[CALL]] 827 // 828 // 829 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 830 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 831 // CHECK3-NEXT: entry: 832 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined) 833 // CHECK3-NEXT: ret void 834 // 835 // 836 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined 837 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 838 // CHECK3-NEXT: entry: 839 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 840 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 841 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 842 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 843 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 844 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 845 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 846 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 847 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 848 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 849 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 850 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 851 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 852 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 853 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 854 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 855 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 856 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 857 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 858 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 859 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 860 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 861 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 862 // CHECK3: arrayctor.loop: 863 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 864 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 865 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 866 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 867 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 868 // CHECK3: arrayctor.cont: 869 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 870 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 871 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 872 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 873 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 874 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 875 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 876 // CHECK3: cond.true: 877 // CHECK3-NEXT: br label [[COND_END:%.*]] 878 // CHECK3: cond.false: 879 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 880 // CHECK3-NEXT: br label [[COND_END]] 881 // CHECK3: cond.end: 882 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 883 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 884 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 885 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 886 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 887 // CHECK3: omp.inner.for.cond: 888 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 889 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 890 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 891 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 892 // CHECK3: omp.inner.for.cond.cleanup: 893 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 894 // CHECK3: omp.inner.for.body: 895 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 896 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 897 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 898 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 899 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 900 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 901 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] 902 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 903 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 904 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] 905 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) 906 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 907 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 908 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 909 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4 910 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 911 // CHECK3: omp.body.continue: 912 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 913 // CHECK3: omp.inner.for.inc: 914 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 915 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 916 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 917 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 918 // CHECK3: omp.inner.for.end: 919 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 920 // CHECK3: omp.loop.exit: 921 // CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 922 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 923 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) 924 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 925 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 926 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 927 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 928 // CHECK3: arraydestroy.body: 929 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 930 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 931 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 932 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 933 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 934 // CHECK3: arraydestroy.done6: 935 // CHECK3-NEXT: ret void 936 // 937 // 938 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 939 // CHECK3-SAME: () #[[ATTR1]] comdat { 940 // CHECK3-NEXT: entry: 941 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 942 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 943 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 944 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 945 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 946 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 947 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 948 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 949 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 950 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 951 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 952 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 953 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 954 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 955 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 956 // CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 957 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 958 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 959 // CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4 960 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 961 // CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4 962 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 963 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 964 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 965 // CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4 966 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 967 // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 968 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 969 // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 970 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 971 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 972 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 973 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 974 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 975 // CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8 976 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 977 // CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8 978 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 979 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 980 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 981 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 982 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 983 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 984 // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 985 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 986 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 987 // CHECK3: omp_offload.failed: 988 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 989 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 990 // CHECK3: omp_offload.cont: 991 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 992 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 993 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 994 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 995 // CHECK3: arraydestroy.body: 996 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 997 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 998 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 999 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1000 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1001 // CHECK3: arraydestroy.done2: 1002 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1003 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 1004 // CHECK3-NEXT: ret i32 [[TMP16]] 1005 // 1006 // 1007 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1008 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1009 // CHECK3-NEXT: entry: 1010 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1011 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1012 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1013 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1014 // CHECK3-NEXT: ret void 1015 // 1016 // 1017 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1018 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1019 // CHECK3-NEXT: entry: 1020 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1021 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1022 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1023 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1024 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1025 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1026 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1027 // CHECK3-NEXT: ret void 1028 // 1029 // 1030 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1031 // CHECK3-SAME: () #[[ATTR4]] { 1032 // CHECK3-NEXT: entry: 1033 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined) 1034 // CHECK3-NEXT: ret void 1035 // 1036 // 1037 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 1038 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1039 // CHECK3-NEXT: entry: 1040 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1041 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1042 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1043 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1044 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 1045 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1046 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1047 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1048 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1049 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1050 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1051 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1052 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1053 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 1054 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1055 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1056 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1057 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 1058 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1059 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1060 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1061 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1062 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1063 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1064 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1065 // CHECK3: arrayctor.loop: 1066 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1067 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1068 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 1069 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1070 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1071 // CHECK3: arrayctor.cont: 1072 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1073 // CHECK3-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 4 1074 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1075 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1076 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1077 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1078 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1079 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1080 // CHECK3: cond.true: 1081 // CHECK3-NEXT: br label [[COND_END:%.*]] 1082 // CHECK3: cond.false: 1083 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1084 // CHECK3-NEXT: br label [[COND_END]] 1085 // CHECK3: cond.end: 1086 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1087 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1088 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1089 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1090 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1091 // CHECK3: omp.inner.for.cond: 1092 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1093 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1094 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1095 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1096 // CHECK3: omp.inner.for.cond.cleanup: 1097 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1098 // CHECK3: omp.inner.for.body: 1099 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1100 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1101 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1102 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1103 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 1104 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 1105 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] 1106 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 1107 // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 1108 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 1109 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] 1110 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) 1111 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1112 // CHECK3: omp.body.continue: 1113 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1114 // CHECK3: omp.inner.for.inc: 1115 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1116 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1 1117 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 1118 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1119 // CHECK3: omp.inner.for.end: 1120 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1121 // CHECK3: omp.loop.exit: 1122 // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1123 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 1124 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 1125 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1126 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1127 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 1128 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1129 // CHECK3: arraydestroy.body: 1130 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1131 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1132 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1133 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 1134 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1135 // CHECK3: arraydestroy.done7: 1136 // CHECK3-NEXT: ret void 1137 // 1138 // 1139 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1140 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1141 // CHECK3-NEXT: entry: 1142 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1143 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1144 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1145 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1146 // CHECK3-NEXT: ret void 1147 // 1148 // 1149 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1150 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1151 // CHECK3-NEXT: entry: 1152 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1153 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1154 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1155 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1156 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1157 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1158 // CHECK3-NEXT: ret void 1159 // 1160 // 1161 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1162 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1163 // CHECK3-NEXT: entry: 1164 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1165 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1166 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1167 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1168 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1169 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1170 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1171 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1172 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1173 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1174 // CHECK3-NEXT: ret void 1175 // 1176 // 1177 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1178 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1179 // CHECK3-NEXT: entry: 1180 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1181 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1182 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1183 // CHECK3-NEXT: ret void 1184 // 1185 // 1186 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_generic_loop_private_codegen.cpp 1187 // CHECK3-SAME: () #[[ATTR0]] { 1188 // CHECK3-NEXT: entry: 1189 // CHECK3-NEXT: call void @__cxx_global_var_init() 1190 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1191 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1192 // CHECK3-NEXT: ret void 1193 // 1194 // 1195 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 1196 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 1197 // CHECK9-NEXT: entry: 1198 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 1199 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 1200 // CHECK9-NEXT: ret void 1201 // 1202 // 1203 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1204 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 1205 // CHECK9-NEXT: entry: 1206 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1207 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1208 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1209 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1210 // CHECK9-NEXT: ret void 1211 // 1212 // 1213 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1214 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1215 // CHECK9-NEXT: entry: 1216 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1217 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1218 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1219 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1220 // CHECK9-NEXT: ret void 1221 // 1222 // 1223 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1224 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1225 // CHECK9-NEXT: entry: 1226 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1227 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1228 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1229 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1230 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1231 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1232 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 1233 // CHECK9-NEXT: ret void 1234 // 1235 // 1236 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1237 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1238 // CHECK9-NEXT: entry: 1239 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1240 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1241 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1242 // CHECK9-NEXT: ret void 1243 // 1244 // 1245 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1246 // CHECK9-SAME: () #[[ATTR0]] { 1247 // CHECK9-NEXT: entry: 1248 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 1249 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 1250 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 1251 // CHECK9-NEXT: ret void 1252 // 1253 // 1254 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1255 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1256 // CHECK9-NEXT: entry: 1257 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1258 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1259 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1260 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1261 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1262 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1263 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1264 // CHECK9-NEXT: ret void 1265 // 1266 // 1267 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1268 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1269 // CHECK9-NEXT: entry: 1270 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1271 // CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1272 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1273 // CHECK9: arraydestroy.body: 1274 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1275 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1276 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1277 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1278 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1279 // CHECK9: arraydestroy.done1: 1280 // CHECK9-NEXT: ret void 1281 // 1282 // 1283 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1284 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1285 // CHECK9-NEXT: entry: 1286 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1287 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1288 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1289 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1290 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1291 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1292 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1293 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1294 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1295 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1296 // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 1297 // CHECK9-NEXT: ret void 1298 // 1299 // 1300 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1301 // CHECK9-SAME: () #[[ATTR0]] { 1302 // CHECK9-NEXT: entry: 1303 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1304 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1305 // CHECK9-NEXT: ret void 1306 // 1307 // 1308 // CHECK9-LABEL: define {{[^@]+}}@main 1309 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 1310 // CHECK9-NEXT: entry: 1311 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1312 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1313 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 1314 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 1315 // CHECK9-NEXT: ret i32 0 1316 // 1317 // 1318 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 1319 // CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR4:[0-9]+]] { 1320 // CHECK9-NEXT: entry: 1321 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 1322 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1323 // CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 1324 // CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 1325 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined) 1326 // CHECK9-NEXT: ret void 1327 // 1328 // 1329 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined 1330 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1331 // CHECK9-NEXT: entry: 1332 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1333 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1334 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1335 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1336 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1337 // CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1338 // CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1339 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1340 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1341 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 1342 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 1343 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 1344 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1345 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1346 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1347 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1348 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1349 // CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 8 1350 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1351 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1352 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1353 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1354 // CHECK9-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 8 1355 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1356 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1357 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1358 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1359 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1360 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1361 // CHECK9: cond.true: 1362 // CHECK9-NEXT: br label [[COND_END:%.*]] 1363 // CHECK9: cond.false: 1364 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1365 // CHECK9-NEXT: br label [[COND_END]] 1366 // CHECK9: cond.end: 1367 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1368 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1369 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1370 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1371 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1372 // CHECK9: omp.inner.for.cond: 1373 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1374 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1375 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1376 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1377 // CHECK9: omp.inner.for.body: 1378 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1379 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1380 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1381 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1382 // CHECK9-NEXT: store i32 1, ptr [[G]], align 4 1383 // CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 1384 // CHECK9-NEXT: store volatile i32 1, ptr [[TMP8]], align 4 1385 // CHECK9-NEXT: store i32 2, ptr [[SIVAR]], align 4 1386 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 1387 // CHECK9-NEXT: store ptr [[G]], ptr [[TMP9]], align 8 1388 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 1389 // CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8 1390 // CHECK9-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8 1391 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 1392 // CHECK9-NEXT: store ptr [[SIVAR]], ptr [[TMP12]], align 8 1393 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 1394 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1395 // CHECK9: omp.body.continue: 1396 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1397 // CHECK9: omp.inner.for.inc: 1398 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1399 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 1400 // CHECK9-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 1401 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 1402 // CHECK9: omp.inner.for.end: 1403 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1404 // CHECK9: omp.loop.exit: 1405 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1406 // CHECK9-NEXT: ret void 1407 // 1408 // 1409 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_generic_loop_private_codegen.cpp 1410 // CHECK9-SAME: () #[[ATTR0]] { 1411 // CHECK9-NEXT: entry: 1412 // CHECK9-NEXT: call void @__cxx_global_var_init() 1413 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 1414 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 1415 // CHECK9-NEXT: ret void 1416 // 1417