1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target 57 #pragma omp teams distribute simd firstprivate(t_var, vec, s_arr, var) 58 for (int i = 0; i < 2; ++i) { 59 vec[i] = t_var; 60 s_arr[i] = var; 61 } 62 return T(); 63 } 64 65 S<float> test; 66 int t_var = 333; 67 int vec[] = {1, 2}; 68 S<float> s_arr[] = {1, 2}; 69 S<float> var(3); 70 71 int main() { 72 static int sivar; 73 #ifdef LAMBDA 74 [&]() { 75 #pragma omp target 76 #pragma omp teams distribute simd firstprivate(g, g1, sivar) 77 for (int i = 0; i < 2; ++i) { 78 79 // Skip global and bound tid vars 80 // skip loop vars 81 g = 1; 82 g1 = 1; 83 sivar = 2; 84 [&]() { 85 g = 2; 86 g1 = 2; 87 sivar = 4; 88 89 }(); 90 } 91 }(); 92 return 0; 93 #else 94 #pragma omp target 95 #pragma omp teams distribute simd firstprivate(t_var, vec, s_arr, var, sivar) 96 for (int i = 0; i < 2; ++i) { 97 vec[i] = t_var; 98 s_arr[i] = var; 99 sivar += i; 100 } 101 return tmain<int>(); 102 #endif 103 } 104 105 106 107 108 109 // Skip global and bound tid vars 110 // Skip temp vars for loop 111 112 // param copy 113 114 // T_VAR and SIVAR 115 116 // preparation vars 117 118 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 119 120 // firstprivate(s_arr) 121 122 // firstprivate(var) 123 124 125 126 127 128 129 // Skip global and bound tid vars 130 // Skip temp vars for loop 131 132 // param copy 133 134 135 // T_VAR and preparation variables 136 137 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 138 139 // firstprivate(s_arr) 140 141 // firstprivate(var) 142 143 144 #endif 145 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 146 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 147 // CHECK1-NEXT: entry: 148 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 149 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 150 // CHECK1-NEXT: ret void 151 // 152 // 153 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 154 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 155 // CHECK1-NEXT: entry: 156 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 157 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 158 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 159 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 160 // CHECK1-NEXT: ret void 161 // 162 // 163 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 164 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 165 // CHECK1-NEXT: entry: 166 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 167 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 168 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 169 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 170 // CHECK1-NEXT: ret void 171 // 172 // 173 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 174 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 175 // CHECK1-NEXT: entry: 176 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 177 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 178 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 179 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 180 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 181 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 182 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 183 // CHECK1-NEXT: ret void 184 // 185 // 186 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 187 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 188 // CHECK1-NEXT: entry: 189 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 190 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 191 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 192 // CHECK1-NEXT: ret void 193 // 194 // 195 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 196 // CHECK1-SAME: () #[[ATTR0]] { 197 // CHECK1-NEXT: entry: 198 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 199 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 200 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 201 // CHECK1-NEXT: ret void 202 // 203 // 204 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 205 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 206 // CHECK1-NEXT: entry: 207 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 208 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 209 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 210 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 211 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 212 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 213 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 214 // CHECK1-NEXT: ret void 215 // 216 // 217 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 218 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 219 // CHECK1-NEXT: entry: 220 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 221 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 222 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 223 // CHECK1: arraydestroy.body: 224 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 225 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 226 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 227 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 228 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 229 // CHECK1: arraydestroy.done1: 230 // CHECK1-NEXT: ret void 231 // 232 // 233 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 234 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 235 // CHECK1-NEXT: entry: 236 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 237 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 238 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 239 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 240 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 241 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 242 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 243 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 244 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 245 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 246 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 247 // CHECK1-NEXT: ret void 248 // 249 // 250 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 251 // CHECK1-SAME: () #[[ATTR0]] { 252 // CHECK1-NEXT: entry: 253 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 254 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 255 // CHECK1-NEXT: ret void 256 // 257 // 258 // CHECK1-LABEL: define {{[^@]+}}@main 259 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 260 // CHECK1-NEXT: entry: 261 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 262 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 263 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 264 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 265 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 266 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 267 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 268 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 269 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 270 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr @t_var, align 4 271 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 272 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 273 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 274 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 275 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 276 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 277 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP4]], align 8 278 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 279 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 280 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 281 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 282 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 283 // CHECK1-NEXT: store ptr @vec, ptr [[TMP7]], align 8 284 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 285 // CHECK1-NEXT: store ptr @vec, ptr [[TMP8]], align 8 286 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 287 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 288 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 289 // CHECK1-NEXT: store ptr @s_arr, ptr [[TMP10]], align 8 290 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 291 // CHECK1-NEXT: store ptr @s_arr, ptr [[TMP11]], align 8 292 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 293 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 294 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 295 // CHECK1-NEXT: store ptr @var, ptr [[TMP13]], align 8 296 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 297 // CHECK1-NEXT: store ptr @var, ptr [[TMP14]], align 8 298 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 299 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 300 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 301 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP16]], align 8 302 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 303 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP17]], align 8 304 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 305 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 306 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 307 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 308 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 309 // CHECK1-NEXT: store i32 3, ptr [[TMP21]], align 4 310 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 311 // CHECK1-NEXT: store i32 5, ptr [[TMP22]], align 4 312 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 313 // CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8 314 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 315 // CHECK1-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8 316 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 317 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 8 318 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 319 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 8 320 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 321 // CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8 322 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 323 // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8 324 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 325 // CHECK1-NEXT: store i64 2, ptr [[TMP29]], align 8 326 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 327 // CHECK1-NEXT: store i64 0, ptr [[TMP30]], align 8 328 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 329 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 330 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 331 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP32]], align 4 332 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 333 // CHECK1-NEXT: store i32 0, ptr [[TMP33]], align 4 334 // CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, ptr [[KERNEL_ARGS]]) 335 // CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 336 // CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 337 // CHECK1: omp_offload.failed: 338 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i64 [[TMP1]], ptr @vec, ptr @s_arr, ptr @var, i64 [[TMP3]]) #[[ATTR2]] 339 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 340 // CHECK1: omp_offload.cont: 341 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 342 // CHECK1-NEXT: ret i32 [[CALL]] 343 // 344 // 345 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 346 // CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 347 // CHECK1-NEXT: entry: 348 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 349 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 350 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 351 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 352 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 353 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 354 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 355 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 356 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 357 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 358 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 359 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 360 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 361 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 362 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 363 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 364 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 365 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 366 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 367 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 368 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 369 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]]) 370 // CHECK1-NEXT: ret void 371 // 372 // 373 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined 374 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 375 // CHECK1-NEXT: entry: 376 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 377 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 378 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 379 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 380 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 381 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 382 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 383 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 384 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 385 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 386 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 387 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 388 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 389 // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 390 // CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 391 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 392 // CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 393 // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 394 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 395 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 396 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 397 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 398 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 399 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 400 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 401 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 402 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 403 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 404 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 405 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 406 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 407 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 408 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 409 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) 410 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 411 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 412 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 413 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 414 // CHECK1: omp.arraycpy.body: 415 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 416 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 417 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 418 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 419 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 420 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 421 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 422 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 423 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 424 // CHECK1: omp.arraycpy.done3: 425 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 426 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 427 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 428 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 429 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 430 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 431 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 432 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 433 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 434 // CHECK1: cond.true: 435 // CHECK1-NEXT: br label [[COND_END:%.*]] 436 // CHECK1: cond.false: 437 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 438 // CHECK1-NEXT: br label [[COND_END]] 439 // CHECK1: cond.end: 440 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 441 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 442 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 443 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 444 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 445 // CHECK1: omp.inner.for.cond: 446 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] 447 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 448 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 449 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 450 // CHECK1: omp.inner.for.cond.cleanup: 451 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 452 // CHECK1: omp.inner.for.body: 453 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 454 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 455 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 456 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] 457 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP5]] 458 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] 459 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 460 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 [[IDXPROM]] 461 // CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] 462 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] 463 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 464 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]] 465 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR4]], i64 4, i1 false), !llvm.access.group [[ACC_GRP5]] 466 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] 467 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP5]] 468 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 469 // CHECK1-NEXT: store i32 [[ADD9]], ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP5]] 470 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 471 // CHECK1: omp.body.continue: 472 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 473 // CHECK1: omp.inner.for.inc: 474 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 475 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP17]], 1 476 // CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 477 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 478 // CHECK1: omp.inner.for.end: 479 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 480 // CHECK1: omp.loop.exit: 481 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 482 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 483 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) 484 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 485 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 486 // CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 487 // CHECK1: .omp.final.then: 488 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 489 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 490 // CHECK1: .omp.final.done: 491 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 492 // CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 493 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 494 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 495 // CHECK1: arraydestroy.body: 496 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 497 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 498 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 499 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 500 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 501 // CHECK1: arraydestroy.done12: 502 // CHECK1-NEXT: ret void 503 // 504 // 505 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev 506 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 507 // CHECK1-NEXT: entry: 508 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 509 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 510 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 511 // CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 512 // CHECK1-NEXT: ret void 513 // 514 // 515 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 516 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 517 // CHECK1-NEXT: entry: 518 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 519 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 520 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 521 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 522 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 523 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 524 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 525 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 526 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 527 // CHECK1-NEXT: ret void 528 // 529 // 530 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev 531 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 532 // CHECK1-NEXT: entry: 533 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 534 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 535 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 536 // CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 537 // CHECK1-NEXT: ret void 538 // 539 // 540 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 541 // CHECK1-SAME: () #[[ATTR1]] comdat { 542 // CHECK1-NEXT: entry: 543 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 544 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 545 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 546 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 547 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 548 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 549 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 550 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 551 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 552 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 553 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 554 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 555 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 556 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 557 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 558 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 559 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 560 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 561 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 562 // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 563 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 564 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 565 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 566 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 567 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 568 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 569 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 570 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 571 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 572 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP6]], align 8 573 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 574 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP7]], align 8 575 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 576 // CHECK1-NEXT: store ptr null, ptr [[TMP8]], align 8 577 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 578 // CHECK1-NEXT: store ptr [[VEC]], ptr [[TMP9]], align 8 579 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 580 // CHECK1-NEXT: store ptr [[VEC]], ptr [[TMP10]], align 8 581 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 582 // CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8 583 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 584 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 8 585 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 586 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 8 587 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 588 // CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8 589 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 590 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 8 591 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 592 // CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 8 593 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 594 // CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8 595 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 596 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 597 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 598 // CHECK1-NEXT: store i32 3, ptr [[TMP20]], align 4 599 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 600 // CHECK1-NEXT: store i32 4, ptr [[TMP21]], align 4 601 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 602 // CHECK1-NEXT: store ptr [[TMP18]], ptr [[TMP22]], align 8 603 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 604 // CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8 605 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 606 // CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP24]], align 8 607 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 608 // CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP25]], align 8 609 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 610 // CHECK1-NEXT: store ptr null, ptr [[TMP26]], align 8 611 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 612 // CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8 613 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 614 // CHECK1-NEXT: store i64 2, ptr [[TMP28]], align 8 615 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 616 // CHECK1-NEXT: store i64 0, ptr [[TMP29]], align 8 617 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 618 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4 619 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 620 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4 621 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 622 // CHECK1-NEXT: store i32 0, ptr [[TMP32]], align 4 623 // CHECK1-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 624 // CHECK1-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 625 // CHECK1-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 626 // CHECK1: omp_offload.failed: 627 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]] 628 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 629 // CHECK1: omp_offload.cont: 630 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 631 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 632 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 633 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 634 // CHECK1: arraydestroy.body: 635 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 636 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 637 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 638 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 639 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 640 // CHECK1: arraydestroy.done2: 641 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 642 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 643 // CHECK1-NEXT: ret i32 [[TMP36]] 644 // 645 // 646 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev 647 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 648 // CHECK1-NEXT: entry: 649 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 650 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 651 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 652 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 653 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 654 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 655 // CHECK1-NEXT: store i32 0, ptr [[B]], align 4 656 // CHECK1-NEXT: ret void 657 // 658 // 659 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 660 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 661 // CHECK1-NEXT: entry: 662 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 663 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 664 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 665 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 666 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 667 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 668 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 669 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 670 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 671 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 672 // CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 673 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 674 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 675 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 676 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 677 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 678 // CHECK1-NEXT: ret void 679 // 680 // 681 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev 682 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 683 // CHECK1-NEXT: entry: 684 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 685 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 686 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 687 // CHECK1-NEXT: ret void 688 // 689 // 690 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 691 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 692 // CHECK1-NEXT: entry: 693 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 694 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 695 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 696 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 697 // CHECK1-NEXT: ret void 698 // 699 // 700 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 701 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 702 // CHECK1-NEXT: entry: 703 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 704 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 705 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 706 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 707 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 708 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 709 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 710 // CHECK1-NEXT: ret void 711 // 712 // 713 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 714 // CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 715 // CHECK1-NEXT: entry: 716 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 717 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 718 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 719 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 720 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 721 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 722 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 723 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 724 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 725 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 726 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 727 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 728 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 729 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 730 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 731 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 732 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 733 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 734 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) 735 // CHECK1-NEXT: ret void 736 // 737 // 738 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 739 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 740 // CHECK1-NEXT: entry: 741 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 742 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 743 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 744 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 745 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 746 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 747 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 748 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 749 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 750 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 751 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 752 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 753 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 754 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 755 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 756 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 757 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 758 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 759 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 760 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 761 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 762 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 763 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 764 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 765 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 766 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 767 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 768 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 769 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 770 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 771 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 772 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 773 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 774 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 775 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) 776 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 777 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 778 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 779 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 780 // CHECK1: omp.arraycpy.body: 781 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 782 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 783 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 784 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 785 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 786 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 787 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 788 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 789 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 790 // CHECK1: omp.arraycpy.done4: 791 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 792 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 793 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) 794 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 795 // CHECK1-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8 796 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 797 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 798 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 799 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 800 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 801 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 802 // CHECK1: cond.true: 803 // CHECK1-NEXT: br label [[COND_END:%.*]] 804 // CHECK1: cond.false: 805 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 806 // CHECK1-NEXT: br label [[COND_END]] 807 // CHECK1: cond.end: 808 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 809 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 810 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 811 // CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 812 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 813 // CHECK1: omp.inner.for.cond: 814 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 815 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 816 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 817 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 818 // CHECK1: omp.inner.for.cond.cleanup: 819 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 820 // CHECK1: omp.inner.for.body: 821 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 822 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 823 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 824 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 825 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP11]] 826 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 827 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 828 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] 829 // CHECK1-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] 830 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP11]] 831 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 832 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP16]] to i64 833 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]] 834 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]] 835 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 836 // CHECK1: omp.body.continue: 837 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 838 // CHECK1: omp.inner.for.inc: 839 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 840 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 841 // CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 842 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 843 // CHECK1: omp.inner.for.end: 844 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 845 // CHECK1: omp.loop.exit: 846 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 847 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 848 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) 849 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 850 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 851 // CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 852 // CHECK1: .omp.final.then: 853 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 854 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 855 // CHECK1: .omp.final.done: 856 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 857 // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 858 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 859 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 860 // CHECK1: arraydestroy.body: 861 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 862 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 863 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 864 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 865 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 866 // CHECK1: arraydestroy.done13: 867 // CHECK1-NEXT: ret void 868 // 869 // 870 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 871 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 872 // CHECK1-NEXT: entry: 873 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 874 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 875 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 876 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 877 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 878 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 879 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 880 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 881 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 882 // CHECK1-NEXT: ret void 883 // 884 // 885 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 886 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 887 // CHECK1-NEXT: entry: 888 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 889 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 890 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 891 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 892 // CHECK1-NEXT: ret void 893 // 894 // 895 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 896 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 897 // CHECK1-NEXT: entry: 898 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 899 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 900 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 901 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 902 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 903 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 904 // CHECK1-NEXT: ret void 905 // 906 // 907 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 908 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 909 // CHECK1-NEXT: entry: 910 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 911 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 912 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 913 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 914 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 915 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 916 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 917 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 918 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 919 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 920 // CHECK1-NEXT: ret void 921 // 922 // 923 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 924 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 925 // CHECK1-NEXT: entry: 926 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 927 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 928 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 929 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 930 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 931 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 932 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 933 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 934 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 935 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 936 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 937 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 938 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 939 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 940 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 941 // CHECK1-NEXT: ret void 942 // 943 // 944 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 945 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 946 // CHECK1-NEXT: entry: 947 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 948 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 949 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 950 // CHECK1-NEXT: ret void 951 // 952 // 953 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp 954 // CHECK1-SAME: () #[[ATTR0]] { 955 // CHECK1-NEXT: entry: 956 // CHECK1-NEXT: call void @__cxx_global_var_init() 957 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 958 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 959 // CHECK1-NEXT: ret void 960 // 961 // 962 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 963 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 964 // CHECK3-NEXT: entry: 965 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 966 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 967 // CHECK3-NEXT: ret void 968 // 969 // 970 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 971 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 972 // CHECK3-NEXT: entry: 973 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 974 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 975 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 976 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 977 // CHECK3-NEXT: ret void 978 // 979 // 980 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 981 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 982 // CHECK3-NEXT: entry: 983 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 984 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 985 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 986 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 987 // CHECK3-NEXT: ret void 988 // 989 // 990 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 991 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 992 // CHECK3-NEXT: entry: 993 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 994 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 995 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 996 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 997 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 998 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 999 // CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4 1000 // CHECK3-NEXT: ret void 1001 // 1002 // 1003 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1004 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1005 // CHECK3-NEXT: entry: 1006 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1007 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1008 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1009 // CHECK3-NEXT: ret void 1010 // 1011 // 1012 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1013 // CHECK3-SAME: () #[[ATTR0]] { 1014 // CHECK3-NEXT: entry: 1015 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 1016 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 1017 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 1018 // CHECK3-NEXT: ret void 1019 // 1020 // 1021 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1022 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1023 // CHECK3-NEXT: entry: 1024 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1025 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1026 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1027 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1028 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1029 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1030 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1031 // CHECK3-NEXT: ret void 1032 // 1033 // 1034 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1035 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1036 // CHECK3-NEXT: entry: 1037 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 1038 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 1039 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1040 // CHECK3: arraydestroy.body: 1041 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1042 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1043 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1044 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1045 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1046 // CHECK3: arraydestroy.done1: 1047 // CHECK3-NEXT: ret void 1048 // 1049 // 1050 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1051 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1052 // CHECK3-NEXT: entry: 1053 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1054 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1055 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1056 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1057 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1058 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1059 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1060 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1061 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1062 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1063 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 1064 // CHECK3-NEXT: ret void 1065 // 1066 // 1067 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1068 // CHECK3-SAME: () #[[ATTR0]] { 1069 // CHECK3-NEXT: entry: 1070 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1071 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1072 // CHECK3-NEXT: ret void 1073 // 1074 // 1075 // CHECK3-LABEL: define {{[^@]+}}@main 1076 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1077 // CHECK3-NEXT: entry: 1078 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1079 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1080 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1081 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 1082 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 1083 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 1084 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1085 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1086 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1087 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr @t_var, align 4 1088 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 1089 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1090 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 1091 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 1092 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 1093 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1094 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP4]], align 4 1095 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1096 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 1097 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1098 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1099 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1100 // CHECK3-NEXT: store ptr @vec, ptr [[TMP7]], align 4 1101 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1102 // CHECK3-NEXT: store ptr @vec, ptr [[TMP8]], align 4 1103 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1104 // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 1105 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1106 // CHECK3-NEXT: store ptr @s_arr, ptr [[TMP10]], align 4 1107 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1108 // CHECK3-NEXT: store ptr @s_arr, ptr [[TMP11]], align 4 1109 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1110 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 1111 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1112 // CHECK3-NEXT: store ptr @var, ptr [[TMP13]], align 4 1113 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1114 // CHECK3-NEXT: store ptr @var, ptr [[TMP14]], align 4 1115 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1116 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 1117 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1118 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP16]], align 4 1119 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1120 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP17]], align 4 1121 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1122 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 1123 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1124 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1125 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1126 // CHECK3-NEXT: store i32 3, ptr [[TMP21]], align 4 1127 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1128 // CHECK3-NEXT: store i32 5, ptr [[TMP22]], align 4 1129 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1130 // CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4 1131 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1132 // CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4 1133 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1134 // CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 4 1135 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1136 // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 4 1137 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1138 // CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 4 1139 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1140 // CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 4 1141 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1142 // CHECK3-NEXT: store i64 2, ptr [[TMP29]], align 8 1143 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1144 // CHECK3-NEXT: store i64 0, ptr [[TMP30]], align 8 1145 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1146 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 1147 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1148 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP32]], align 4 1149 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1150 // CHECK3-NEXT: store i32 0, ptr [[TMP33]], align 4 1151 // CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, ptr [[KERNEL_ARGS]]) 1152 // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 1153 // CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1154 // CHECK3: omp_offload.failed: 1155 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i32 [[TMP1]], ptr @vec, ptr @s_arr, ptr @var, i32 [[TMP3]]) #[[ATTR2]] 1156 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1157 // CHECK3: omp_offload.cont: 1158 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1159 // CHECK3-NEXT: ret i32 [[CALL]] 1160 // 1161 // 1162 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 1163 // CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 1164 // CHECK3-NEXT: entry: 1165 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1166 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1167 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1168 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1169 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1170 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1171 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1172 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1173 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1174 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1175 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1176 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 1177 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1178 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1179 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1180 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1181 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 1182 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1183 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 1184 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 1185 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 1186 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]]) 1187 // CHECK3-NEXT: ret void 1188 // 1189 // 1190 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined 1191 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 1192 // CHECK3-NEXT: entry: 1193 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1194 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1195 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1196 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1197 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1198 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1199 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1200 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1201 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1202 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1203 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1204 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1205 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1206 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 1207 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 1208 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1209 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1210 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 1211 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1212 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1213 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1214 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1215 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1216 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1217 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1218 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 1219 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1220 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1221 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1222 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1223 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1224 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1225 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1226 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) 1227 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1228 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1229 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 1230 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1231 // CHECK3: omp.arraycpy.body: 1232 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1233 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1234 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1235 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 1236 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1237 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1238 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1239 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 1240 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 1241 // CHECK3: omp.arraycpy.done3: 1242 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 1243 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 1244 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 1245 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1246 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 1247 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1248 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1249 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 1250 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1251 // CHECK3: cond.true: 1252 // CHECK3-NEXT: br label [[COND_END:%.*]] 1253 // CHECK3: cond.false: 1254 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1255 // CHECK3-NEXT: br label [[COND_END]] 1256 // CHECK3: cond.end: 1257 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1258 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1259 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1260 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 1261 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1262 // CHECK3: omp.inner.for.cond: 1263 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 1264 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 1265 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1266 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1267 // CHECK3: omp.inner.for.cond.cleanup: 1268 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1269 // CHECK3: omp.inner.for.body: 1270 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1271 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 1272 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1273 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1274 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP6]] 1275 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1276 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP13]] 1277 // CHECK3-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] 1278 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1279 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP14]] 1280 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false), !llvm.access.group [[ACC_GRP6]] 1281 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1282 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP6]] 1283 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 1284 // CHECK3-NEXT: store i32 [[ADD8]], ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP6]] 1285 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1286 // CHECK3: omp.body.continue: 1287 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1288 // CHECK3: omp.inner.for.inc: 1289 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1290 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], 1 1291 // CHECK3-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1292 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1293 // CHECK3: omp.inner.for.end: 1294 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1295 // CHECK3: omp.loop.exit: 1296 // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1297 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 1298 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) 1299 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1300 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 1301 // CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1302 // CHECK3: .omp.final.then: 1303 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 1304 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1305 // CHECK3: .omp.final.done: 1306 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 1307 // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1308 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 1309 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1310 // CHECK3: arraydestroy.body: 1311 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1312 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1313 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1314 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 1315 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 1316 // CHECK3: arraydestroy.done11: 1317 // CHECK3-NEXT: ret void 1318 // 1319 // 1320 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev 1321 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1322 // CHECK3-NEXT: entry: 1323 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1324 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1325 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1326 // CHECK3-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 1327 // CHECK3-NEXT: ret void 1328 // 1329 // 1330 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 1331 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1332 // CHECK3-NEXT: entry: 1333 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1334 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1335 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1336 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1337 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1338 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1339 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1340 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1341 // CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 1342 // CHECK3-NEXT: ret void 1343 // 1344 // 1345 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev 1346 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1347 // CHECK3-NEXT: entry: 1348 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1349 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1350 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1351 // CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 1352 // CHECK3-NEXT: ret void 1353 // 1354 // 1355 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1356 // CHECK3-SAME: () #[[ATTR1]] comdat { 1357 // CHECK3-NEXT: entry: 1358 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1359 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1360 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1361 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1362 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1363 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 1364 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1365 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1366 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 1367 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 1368 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 1369 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1370 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1371 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1372 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 1373 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 1374 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 1375 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 1376 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1377 // CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 1378 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 1379 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 1380 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 1381 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 1382 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1383 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 1384 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 1385 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 1386 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1387 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP6]], align 4 1388 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1389 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP7]], align 4 1390 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1391 // CHECK3-NEXT: store ptr null, ptr [[TMP8]], align 4 1392 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1393 // CHECK3-NEXT: store ptr [[VEC]], ptr [[TMP9]], align 4 1394 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1395 // CHECK3-NEXT: store ptr [[VEC]], ptr [[TMP10]], align 4 1396 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1397 // CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4 1398 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1399 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 4 1400 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1401 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 4 1402 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1403 // CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4 1404 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1405 // CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 4 1406 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1407 // CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 4 1408 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1409 // CHECK3-NEXT: store ptr null, ptr [[TMP17]], align 4 1410 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1411 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1412 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1413 // CHECK3-NEXT: store i32 3, ptr [[TMP20]], align 4 1414 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1415 // CHECK3-NEXT: store i32 4, ptr [[TMP21]], align 4 1416 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1417 // CHECK3-NEXT: store ptr [[TMP18]], ptr [[TMP22]], align 4 1418 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1419 // CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4 1420 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1421 // CHECK3-NEXT: store ptr @.offload_sizes.3, ptr [[TMP24]], align 4 1422 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1423 // CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP25]], align 4 1424 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1425 // CHECK3-NEXT: store ptr null, ptr [[TMP26]], align 4 1426 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1427 // CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 4 1428 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1429 // CHECK3-NEXT: store i64 2, ptr [[TMP28]], align 8 1430 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1431 // CHECK3-NEXT: store i64 0, ptr [[TMP29]], align 8 1432 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1433 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4 1434 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1435 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4 1436 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1437 // CHECK3-NEXT: store i32 0, ptr [[TMP32]], align 4 1438 // CHECK3-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 1439 // CHECK3-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 1440 // CHECK3-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1441 // CHECK3: omp_offload.failed: 1442 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]] 1443 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1444 // CHECK3: omp_offload.cont: 1445 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1446 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1447 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1448 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1449 // CHECK3: arraydestroy.body: 1450 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1451 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1452 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1453 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1454 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1455 // CHECK3: arraydestroy.done2: 1456 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1457 // CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 1458 // CHECK3-NEXT: ret i32 [[TMP36]] 1459 // 1460 // 1461 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev 1462 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1463 // CHECK3-NEXT: entry: 1464 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1465 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1466 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1467 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 1468 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 1469 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 1470 // CHECK3-NEXT: store i32 0, ptr [[B]], align 4 1471 // CHECK3-NEXT: ret void 1472 // 1473 // 1474 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 1475 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1476 // CHECK3-NEXT: entry: 1477 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1478 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1479 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1480 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1481 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1482 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1483 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1484 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1485 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1486 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 1487 // CHECK3-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 1488 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 1489 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1490 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 1491 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 1492 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 1493 // CHECK3-NEXT: ret void 1494 // 1495 // 1496 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev 1497 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1498 // CHECK3-NEXT: entry: 1499 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1500 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1501 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1502 // CHECK3-NEXT: ret void 1503 // 1504 // 1505 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1506 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1507 // CHECK3-NEXT: entry: 1508 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1509 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1510 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1511 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1512 // CHECK3-NEXT: ret void 1513 // 1514 // 1515 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1516 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1517 // CHECK3-NEXT: entry: 1518 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1519 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1520 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1521 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1522 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1523 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1524 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1525 // CHECK3-NEXT: ret void 1526 // 1527 // 1528 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1529 // CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1530 // CHECK3-NEXT: entry: 1531 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1532 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1533 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1534 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1535 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1536 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1537 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1538 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1539 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1540 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1541 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1542 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1543 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1544 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 1545 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1546 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 1547 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1548 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 1549 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) 1550 // CHECK3-NEXT: ret void 1551 // 1552 // 1553 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 1554 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1555 // CHECK3-NEXT: entry: 1556 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1557 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1558 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1559 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1560 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1561 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1562 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1563 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1564 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1565 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1566 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1567 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1568 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1569 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 1570 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 1571 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1572 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1573 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1574 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 1575 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1576 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1577 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1578 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1579 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1580 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1581 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1582 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1583 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1584 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1585 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 1586 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1587 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1588 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1589 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1590 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) 1591 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 1592 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1593 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 1594 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1595 // CHECK3: omp.arraycpy.body: 1596 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1597 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1598 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1599 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 1600 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1601 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1602 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1603 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 1604 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1605 // CHECK3: omp.arraycpy.done4: 1606 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 1607 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1608 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) 1609 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 1610 // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 1611 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1612 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 1613 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1614 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1615 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 1616 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1617 // CHECK3: cond.true: 1618 // CHECK3-NEXT: br label [[COND_END:%.*]] 1619 // CHECK3: cond.false: 1620 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1621 // CHECK3-NEXT: br label [[COND_END]] 1622 // CHECK3: cond.end: 1623 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 1624 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1625 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1626 // CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 1627 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1628 // CHECK3: omp.inner.for.cond: 1629 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 1630 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] 1631 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 1632 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1633 // CHECK3: omp.inner.for.cond.cleanup: 1634 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1635 // CHECK3: omp.inner.for.body: 1636 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 1637 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 1638 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1639 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] 1640 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] 1641 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] 1642 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP14]] 1643 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] 1644 // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP12]] 1645 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] 1646 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP16]] 1647 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]] 1648 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1649 // CHECK3: omp.body.continue: 1650 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1651 // CHECK3: omp.inner.for.inc: 1652 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 1653 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP17]], 1 1654 // CHECK3-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 1655 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 1656 // CHECK3: omp.inner.for.end: 1657 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1658 // CHECK3: omp.loop.exit: 1659 // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1660 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 1661 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) 1662 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1663 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 1664 // CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1665 // CHECK3: .omp.final.then: 1666 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 1667 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1668 // CHECK3: .omp.final.done: 1669 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1670 // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 1671 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 1672 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1673 // CHECK3: arraydestroy.body: 1674 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1675 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1676 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1677 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 1678 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 1679 // CHECK3: arraydestroy.done12: 1680 // CHECK3-NEXT: ret void 1681 // 1682 // 1683 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1684 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1685 // CHECK3-NEXT: entry: 1686 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1687 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1688 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1689 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1690 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1691 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1692 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1693 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1694 // CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 1695 // CHECK3-NEXT: ret void 1696 // 1697 // 1698 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1699 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1700 // CHECK3-NEXT: entry: 1701 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1702 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1703 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1704 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1705 // CHECK3-NEXT: ret void 1706 // 1707 // 1708 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1709 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1710 // CHECK3-NEXT: entry: 1711 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1712 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1713 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1714 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1715 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1716 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1717 // CHECK3-NEXT: ret void 1718 // 1719 // 1720 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1721 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1722 // CHECK3-NEXT: entry: 1723 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1724 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1725 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1726 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1727 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1728 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1729 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1730 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1731 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1732 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1733 // CHECK3-NEXT: ret void 1734 // 1735 // 1736 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1737 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1738 // CHECK3-NEXT: entry: 1739 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1740 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1741 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1742 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1743 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1744 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1745 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1746 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1747 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1748 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 1749 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 1750 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 1751 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1752 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1753 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1754 // CHECK3-NEXT: ret void 1755 // 1756 // 1757 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1758 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1759 // CHECK3-NEXT: entry: 1760 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1761 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1762 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1763 // CHECK3-NEXT: ret void 1764 // 1765 // 1766 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp 1767 // CHECK3-SAME: () #[[ATTR0]] { 1768 // CHECK3-NEXT: entry: 1769 // CHECK3-NEXT: call void @__cxx_global_var_init() 1770 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1771 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1772 // CHECK3-NEXT: ret void 1773 // 1774 // 1775 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 1776 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 1777 // CHECK5-NEXT: entry: 1778 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 1779 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 1780 // CHECK5-NEXT: ret void 1781 // 1782 // 1783 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1784 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 1785 // CHECK5-NEXT: entry: 1786 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1787 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1788 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1789 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1790 // CHECK5-NEXT: ret void 1791 // 1792 // 1793 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1794 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1795 // CHECK5-NEXT: entry: 1796 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1797 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1798 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1799 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1800 // CHECK5-NEXT: ret void 1801 // 1802 // 1803 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1804 // CHECK5-SAME: () #[[ATTR0]] { 1805 // CHECK5-NEXT: entry: 1806 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 1807 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 1808 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 1809 // CHECK5-NEXT: ret void 1810 // 1811 // 1812 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1813 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1814 // CHECK5-NEXT: entry: 1815 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1816 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1817 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1818 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1819 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1820 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1821 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1822 // CHECK5-NEXT: ret void 1823 // 1824 // 1825 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1826 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1827 // CHECK5-NEXT: entry: 1828 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1829 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1830 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1831 // CHECK5: arraydestroy.body: 1832 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1833 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1834 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1835 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1836 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1837 // CHECK5: arraydestroy.done1: 1838 // CHECK5-NEXT: ret void 1839 // 1840 // 1841 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1842 // CHECK5-SAME: () #[[ATTR0]] { 1843 // CHECK5-NEXT: entry: 1844 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1845 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1846 // CHECK5-NEXT: ret void 1847 // 1848 // 1849 // CHECK5-LABEL: define {{[^@]+}}@main 1850 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 1851 // CHECK5-NEXT: entry: 1852 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1853 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1854 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1855 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1856 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1857 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1858 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 1859 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1860 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1861 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1862 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 1863 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1864 // CHECK5: omp.inner.for.cond: 1865 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 1866 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 1867 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1868 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1869 // CHECK5: omp.inner.for.body: 1870 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1871 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1872 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1873 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1874 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP2]] 1875 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1876 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 1877 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i64 0, i64 [[IDXPROM]] 1878 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] 1879 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1880 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 1881 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i64 0, i64 [[IDXPROM1]] 1882 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 @var, i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] 1883 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1884 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] 1885 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] 1886 // CHECK5-NEXT: store i32 [[ADD3]], ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] 1887 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1888 // CHECK5: omp.body.continue: 1889 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1890 // CHECK5: omp.inner.for.inc: 1891 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1892 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 1893 // CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1894 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1895 // CHECK5: omp.inner.for.end: 1896 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 1897 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 1898 // CHECK5-NEXT: ret i32 [[CALL]] 1899 // 1900 // 1901 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1902 // CHECK5-SAME: () #[[ATTR1]] comdat { 1903 // CHECK5-NEXT: entry: 1904 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1905 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1906 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1907 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1908 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1909 // CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 8 1910 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1911 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1912 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 1913 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1914 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1915 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1916 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1917 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1918 // CHECK5-NEXT: store i32 0, ptr [[T_VAR]], align 4 1919 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 1920 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 1921 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 1922 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 1923 // CHECK5-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 1924 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 1925 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 1926 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8 1927 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 1928 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 8 1929 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1930 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1931 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1932 // CHECK5-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 1933 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1934 // CHECK5: omp.inner.for.cond: 1935 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 1936 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 1937 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 1938 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1939 // CHECK5: omp.inner.for.body: 1940 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1941 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 1942 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1943 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1944 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP6]] 1945 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1946 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i64 1947 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 1948 // CHECK5-NEXT: store i32 [[TMP7]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] 1949 // CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8, !llvm.access.group [[ACC_GRP6]] 1950 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1951 // CHECK5-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP10]] to i64 1952 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] 1953 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP9]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] 1954 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1955 // CHECK5: omp.body.continue: 1956 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1957 // CHECK5: omp.inner.for.inc: 1958 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1959 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 1960 // CHECK5-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1961 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1962 // CHECK5: omp.inner.for.end: 1963 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 1964 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 1965 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1966 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 1967 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1968 // CHECK5: arraydestroy.body: 1969 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1970 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1971 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1972 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1973 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 1974 // CHECK5: arraydestroy.done6: 1975 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1976 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 4 1977 // CHECK5-NEXT: ret i32 [[TMP13]] 1978 // 1979 // 1980 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1981 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1982 // CHECK5-NEXT: entry: 1983 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1984 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1985 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1986 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1987 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1988 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1989 // CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4 1990 // CHECK5-NEXT: ret void 1991 // 1992 // 1993 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1994 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1995 // CHECK5-NEXT: entry: 1996 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1997 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1998 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1999 // CHECK5-NEXT: ret void 2000 // 2001 // 2002 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2003 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2004 // CHECK5-NEXT: entry: 2005 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2006 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2007 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2008 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2009 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2010 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2011 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2012 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2013 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2014 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2015 // CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4 2016 // CHECK5-NEXT: ret void 2017 // 2018 // 2019 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2020 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2021 // CHECK5-NEXT: entry: 2022 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2023 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2024 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2025 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2026 // CHECK5-NEXT: ret void 2027 // 2028 // 2029 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2030 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2031 // CHECK5-NEXT: entry: 2032 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2033 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2034 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2035 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2036 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2037 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2038 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 2039 // CHECK5-NEXT: ret void 2040 // 2041 // 2042 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2043 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2044 // CHECK5-NEXT: entry: 2045 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2046 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2047 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2048 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2049 // CHECK5-NEXT: ret void 2050 // 2051 // 2052 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2053 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2054 // CHECK5-NEXT: entry: 2055 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2056 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2057 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2058 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2059 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2060 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 2061 // CHECK5-NEXT: ret void 2062 // 2063 // 2064 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2065 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2066 // CHECK5-NEXT: entry: 2067 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2068 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2069 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2070 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2071 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2072 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2073 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2074 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2075 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2076 // CHECK5-NEXT: store i32 [[ADD]], ptr [[F]], align 4 2077 // CHECK5-NEXT: ret void 2078 // 2079 // 2080 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2081 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2082 // CHECK5-NEXT: entry: 2083 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2084 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2085 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2086 // CHECK5-NEXT: ret void 2087 // 2088 // 2089 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp 2090 // CHECK5-SAME: () #[[ATTR0]] { 2091 // CHECK5-NEXT: entry: 2092 // CHECK5-NEXT: call void @__cxx_global_var_init() 2093 // CHECK5-NEXT: call void @__cxx_global_var_init.1() 2094 // CHECK5-NEXT: call void @__cxx_global_var_init.2() 2095 // CHECK5-NEXT: ret void 2096 // 2097 // 2098 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init 2099 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 2100 // CHECK7-NEXT: entry: 2101 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 2102 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 2103 // CHECK7-NEXT: ret void 2104 // 2105 // 2106 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2107 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2108 // CHECK7-NEXT: entry: 2109 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2110 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2111 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2112 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2113 // CHECK7-NEXT: ret void 2114 // 2115 // 2116 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2117 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2118 // CHECK7-NEXT: entry: 2119 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2120 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2121 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2122 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2123 // CHECK7-NEXT: ret void 2124 // 2125 // 2126 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2127 // CHECK7-SAME: () #[[ATTR0]] { 2128 // CHECK7-NEXT: entry: 2129 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 2130 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 2131 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 2132 // CHECK7-NEXT: ret void 2133 // 2134 // 2135 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2136 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2137 // CHECK7-NEXT: entry: 2138 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2139 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2140 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2141 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2142 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2143 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2144 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2145 // CHECK7-NEXT: ret void 2146 // 2147 // 2148 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2149 // CHECK7-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2150 // CHECK7-NEXT: entry: 2151 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 2152 // CHECK7-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 2153 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2154 // CHECK7: arraydestroy.body: 2155 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2156 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2157 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2158 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 2159 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2160 // CHECK7: arraydestroy.done1: 2161 // CHECK7-NEXT: ret void 2162 // 2163 // 2164 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2165 // CHECK7-SAME: () #[[ATTR0]] { 2166 // CHECK7-NEXT: entry: 2167 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2168 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 2169 // CHECK7-NEXT: ret void 2170 // 2171 // 2172 // CHECK7-LABEL: define {{[^@]+}}@main 2173 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] { 2174 // CHECK7-NEXT: entry: 2175 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2176 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 2177 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2178 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2179 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2180 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2181 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 2182 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2183 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2184 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2185 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 2186 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2187 // CHECK7: omp.inner.for.cond: 2188 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 2189 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 2190 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 2191 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2192 // CHECK7: omp.inner.for.body: 2193 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 2194 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 2195 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2196 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 2197 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP3]] 2198 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 2199 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i32 0, i32 [[TMP5]] 2200 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] 2201 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 2202 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i32 0, i32 [[TMP6]] 2203 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 @var, i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] 2204 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 2205 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]] 2206 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] 2207 // CHECK7-NEXT: store i32 [[ADD2]], ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]] 2208 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2209 // CHECK7: omp.body.continue: 2210 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2211 // CHECK7: omp.inner.for.inc: 2212 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 2213 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 2214 // CHECK7-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 2215 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 2216 // CHECK7: omp.inner.for.end: 2217 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 2218 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 2219 // CHECK7-NEXT: ret i32 [[CALL]] 2220 // 2221 // 2222 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2223 // CHECK7-SAME: () #[[ATTR1]] comdat { 2224 // CHECK7-NEXT: entry: 2225 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2226 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2227 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2228 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2229 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2230 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 4 2231 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4 2232 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 2233 // CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 2234 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2235 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2236 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2237 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2238 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 2239 // CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 4 2240 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 2241 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 2242 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 2243 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 2244 // CHECK7-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 2245 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 2246 // CHECK7-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 2247 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 4 2248 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4 2249 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 4 2250 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2251 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2252 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2253 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 2254 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2255 // CHECK7: omp.inner.for.cond: 2256 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 2257 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]] 2258 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 2259 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2260 // CHECK7: omp.inner.for.body: 2261 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 2262 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 2263 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2264 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 2265 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP7]] 2266 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 2267 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP8]] 2268 // CHECK7-NEXT: store i32 [[TMP7]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] 2269 // CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 4, !llvm.access.group [[ACC_GRP7]] 2270 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 2271 // CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP10]] 2272 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[TMP9]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] 2273 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2274 // CHECK7: omp.body.continue: 2275 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2276 // CHECK7: omp.inner.for.inc: 2277 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 2278 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 2279 // CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 2280 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 2281 // CHECK7: omp.inner.for.end: 2282 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 2283 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 2284 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 2285 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 2286 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2287 // CHECK7: arraydestroy.body: 2288 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2289 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2290 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2291 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2292 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 2293 // CHECK7: arraydestroy.done5: 2294 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 2295 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 4 2296 // CHECK7-NEXT: ret i32 [[TMP13]] 2297 // 2298 // 2299 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2300 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2301 // CHECK7-NEXT: entry: 2302 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2303 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2304 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2305 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2306 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2307 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2308 // CHECK7-NEXT: store float [[CONV]], ptr [[F]], align 4 2309 // CHECK7-NEXT: ret void 2310 // 2311 // 2312 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2313 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2314 // CHECK7-NEXT: entry: 2315 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2316 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2317 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2318 // CHECK7-NEXT: ret void 2319 // 2320 // 2321 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2322 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2323 // CHECK7-NEXT: entry: 2324 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2325 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2326 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2327 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2328 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2329 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2330 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2331 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2332 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2333 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2334 // CHECK7-NEXT: store float [[ADD]], ptr [[F]], align 4 2335 // CHECK7-NEXT: ret void 2336 // 2337 // 2338 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2339 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2340 // CHECK7-NEXT: entry: 2341 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2342 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2343 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2344 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2345 // CHECK7-NEXT: ret void 2346 // 2347 // 2348 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2349 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2350 // CHECK7-NEXT: entry: 2351 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2352 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2353 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2354 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2355 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2356 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2357 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 2358 // CHECK7-NEXT: ret void 2359 // 2360 // 2361 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2362 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2363 // CHECK7-NEXT: entry: 2364 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2365 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2366 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2367 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2368 // CHECK7-NEXT: ret void 2369 // 2370 // 2371 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2372 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2373 // CHECK7-NEXT: entry: 2374 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2375 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2376 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2377 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2378 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2379 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 2380 // CHECK7-NEXT: ret void 2381 // 2382 // 2383 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2384 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2385 // CHECK7-NEXT: entry: 2386 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2387 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2388 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2389 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2390 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2391 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2392 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2393 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2394 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2395 // CHECK7-NEXT: store i32 [[ADD]], ptr [[F]], align 4 2396 // CHECK7-NEXT: ret void 2397 // 2398 // 2399 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2400 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2401 // CHECK7-NEXT: entry: 2402 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2403 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2404 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2405 // CHECK7-NEXT: ret void 2406 // 2407 // 2408 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp 2409 // CHECK7-SAME: () #[[ATTR0]] { 2410 // CHECK7-NEXT: entry: 2411 // CHECK7-NEXT: call void @__cxx_global_var_init() 2412 // CHECK7-NEXT: call void @__cxx_global_var_init.1() 2413 // CHECK7-NEXT: call void @__cxx_global_var_init.2() 2414 // CHECK7-NEXT: ret void 2415 // 2416 // 2417 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 2418 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 2419 // CHECK9-NEXT: entry: 2420 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 2421 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 2422 // CHECK9-NEXT: ret void 2423 // 2424 // 2425 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2426 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 2427 // CHECK9-NEXT: entry: 2428 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2429 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2430 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2431 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2432 // CHECK9-NEXT: ret void 2433 // 2434 // 2435 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2436 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2437 // CHECK9-NEXT: entry: 2438 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2439 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2440 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2441 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2442 // CHECK9-NEXT: ret void 2443 // 2444 // 2445 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2446 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2447 // CHECK9-NEXT: entry: 2448 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2449 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2450 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2451 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2452 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2453 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2454 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 2455 // CHECK9-NEXT: ret void 2456 // 2457 // 2458 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2459 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2460 // CHECK9-NEXT: entry: 2461 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2462 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2463 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2464 // CHECK9-NEXT: ret void 2465 // 2466 // 2467 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2468 // CHECK9-SAME: () #[[ATTR0]] { 2469 // CHECK9-NEXT: entry: 2470 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 2471 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 2472 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 2473 // CHECK9-NEXT: ret void 2474 // 2475 // 2476 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2477 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2478 // CHECK9-NEXT: entry: 2479 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2480 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2481 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2482 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2483 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2484 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2485 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2486 // CHECK9-NEXT: ret void 2487 // 2488 // 2489 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2490 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2491 // CHECK9-NEXT: entry: 2492 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2493 // CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2494 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2495 // CHECK9: arraydestroy.body: 2496 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2497 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2498 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2499 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 2500 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2501 // CHECK9: arraydestroy.done1: 2502 // CHECK9-NEXT: ret void 2503 // 2504 // 2505 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2506 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2507 // CHECK9-NEXT: entry: 2508 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2509 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2510 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2511 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2512 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2513 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2514 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2515 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2516 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2517 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2518 // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 2519 // CHECK9-NEXT: ret void 2520 // 2521 // 2522 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2523 // CHECK9-SAME: () #[[ATTR0]] { 2524 // CHECK9-NEXT: entry: 2525 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2526 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 2527 // CHECK9-NEXT: ret void 2528 // 2529 // 2530 // CHECK9-LABEL: define {{[^@]+}}@main 2531 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 2532 // CHECK9-NEXT: entry: 2533 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2534 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2535 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 2536 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2537 // CHECK9-NEXT: ret i32 0 2538 // 2539 // 2540 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 2541 // CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[SIVAR:%.*]], i64 noundef [[G1:%.*]]) #[[ATTR4:[0-9]+]] { 2542 // CHECK9-NEXT: entry: 2543 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 2544 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2545 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 2546 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 2547 // CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 2548 // CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 2549 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 2550 // CHECK9-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 2551 // CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 2552 // CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 2553 // CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 2554 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 4 2555 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4 2556 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8 2557 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 2558 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 4 2559 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[G1_CASTED]], align 4 2560 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 8 2561 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 2562 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 2563 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 2564 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined, i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) 2565 // CHECK9-NEXT: ret void 2566 // 2567 // 2568 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined 2569 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 2570 // CHECK9-NEXT: entry: 2571 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2572 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2573 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 2574 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 2575 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2576 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 2577 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2578 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2579 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2580 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2581 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2582 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2583 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 2584 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 2585 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2586 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2587 // CHECK9-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 2588 // CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 2589 // CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 2590 // CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 2591 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2592 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2593 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2594 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2595 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2596 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2597 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2598 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2599 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 2600 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2601 // CHECK9: cond.true: 2602 // CHECK9-NEXT: br label [[COND_END:%.*]] 2603 // CHECK9: cond.false: 2604 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2605 // CHECK9-NEXT: br label [[COND_END]] 2606 // CHECK9: cond.end: 2607 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2608 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2609 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2610 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2611 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2612 // CHECK9: omp.inner.for.cond: 2613 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]] 2614 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]] 2615 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2616 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2617 // CHECK9: omp.inner.for.body: 2618 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 2619 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2620 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2621 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] 2622 // CHECK9-NEXT: store i32 1, ptr [[G_ADDR]], align 4, !llvm.access.group [[ACC_GRP4]] 2623 // CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8, !llvm.access.group [[ACC_GRP4]] 2624 // CHECK9-NEXT: store volatile i32 1, ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP4]] 2625 // CHECK9-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP4]] 2626 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 2627 // CHECK9-NEXT: store ptr [[G_ADDR]], ptr [[TMP9]], align 8, !llvm.access.group [[ACC_GRP4]] 2628 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 2629 // CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP]], align 8, !llvm.access.group [[ACC_GRP4]] 2630 // CHECK9-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP4]] 2631 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 2632 // CHECK9-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP4]] 2633 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group [[ACC_GRP4]] 2634 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2635 // CHECK9: omp.body.continue: 2636 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2637 // CHECK9: omp.inner.for.inc: 2638 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 2639 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], 1 2640 // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 2641 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 2642 // CHECK9: omp.inner.for.end: 2643 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2644 // CHECK9: omp.loop.exit: 2645 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2646 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2647 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 2648 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2649 // CHECK9: .omp.final.then: 2650 // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 2651 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 2652 // CHECK9: .omp.final.done: 2653 // CHECK9-NEXT: ret void 2654 // 2655 // 2656 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp 2657 // CHECK9-SAME: () #[[ATTR0]] { 2658 // CHECK9-NEXT: entry: 2659 // CHECK9-NEXT: call void @__cxx_global_var_init() 2660 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 2661 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 2662 // CHECK9-NEXT: ret void 2663 // 2664 // 2665 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init 2666 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 2667 // CHECK11-NEXT: entry: 2668 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 2669 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 2670 // CHECK11-NEXT: ret void 2671 // 2672 // 2673 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2674 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 2675 // CHECK11-NEXT: entry: 2676 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2677 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2678 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2679 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2680 // CHECK11-NEXT: ret void 2681 // 2682 // 2683 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2684 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2685 // CHECK11-NEXT: entry: 2686 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2687 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2688 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2689 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2690 // CHECK11-NEXT: ret void 2691 // 2692 // 2693 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2694 // CHECK11-SAME: () #[[ATTR0]] { 2695 // CHECK11-NEXT: entry: 2696 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 2697 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 2698 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 2699 // CHECK11-NEXT: ret void 2700 // 2701 // 2702 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2703 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2704 // CHECK11-NEXT: entry: 2705 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2706 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2707 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2708 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2709 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2710 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2711 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2712 // CHECK11-NEXT: ret void 2713 // 2714 // 2715 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2716 // CHECK11-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2717 // CHECK11-NEXT: entry: 2718 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2719 // CHECK11-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2720 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2721 // CHECK11: arraydestroy.body: 2722 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2723 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2724 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2725 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 2726 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2727 // CHECK11: arraydestroy.done1: 2728 // CHECK11-NEXT: ret void 2729 // 2730 // 2731 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2732 // CHECK11-SAME: () #[[ATTR0]] { 2733 // CHECK11-NEXT: entry: 2734 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2735 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 2736 // CHECK11-NEXT: ret void 2737 // 2738 // 2739 // CHECK11-LABEL: define {{[^@]+}}@main 2740 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 2741 // CHECK11-NEXT: entry: 2742 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2743 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2744 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 2745 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2746 // CHECK11-NEXT: ret i32 0 2747 // 2748 // 2749 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2750 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2751 // CHECK11-NEXT: entry: 2752 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2753 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2754 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2755 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2756 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2757 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2758 // CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4 2759 // CHECK11-NEXT: ret void 2760 // 2761 // 2762 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2763 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2764 // CHECK11-NEXT: entry: 2765 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2766 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2767 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2768 // CHECK11-NEXT: ret void 2769 // 2770 // 2771 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2772 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2773 // CHECK11-NEXT: entry: 2774 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2775 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2776 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2777 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2778 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2779 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2780 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2781 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2782 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2783 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2784 // CHECK11-NEXT: store float [[ADD]], ptr [[F]], align 4 2785 // CHECK11-NEXT: ret void 2786 // 2787 // 2788 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp 2789 // CHECK11-SAME: () #[[ATTR0]] { 2790 // CHECK11-NEXT: entry: 2791 // CHECK11-NEXT: call void @__cxx_global_var_init() 2792 // CHECK11-NEXT: call void @__cxx_global_var_init.1() 2793 // CHECK11-NEXT: call void @__cxx_global_var_init.2() 2794 // CHECK11-NEXT: ret void 2795 // 2796