1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target 57 #pragma omp teams distribute private(t_var, vec, s_arr, var) 58 for (int i = 0; i < 2; ++i) { 59 vec[i] = t_var; 60 s_arr[i] = var; 61 } 62 return T(); 63 } 64 65 S<float> test; 66 int t_var = 333; 67 int vec[] = {1, 2}; 68 S<float> s_arr[] = {1, 2}; 69 S<float> var(3); 70 71 int main() { 72 static int sivar; 73 #ifdef LAMBDA 74 [&]() { 75 #pragma omp target 76 #pragma omp teams distribute private(g, g1, sivar) 77 for (int i = 0; i < 2; ++i) { 78 79 // Skip global, bound tid and loop vars 80 g = 1; 81 g1 = 1; 82 sivar = 2; 83 [&]() { 84 g = 2; 85 g1 = 2; 86 sivar = 4; 87 88 }(); 89 } 90 }(); 91 return 0; 92 #else 93 #pragma omp target 94 #pragma omp teams distribute private(t_var, vec, s_arr, var, sivar) 95 for (int i = 0; i < 2; ++i) { 96 vec[i] = t_var; 97 s_arr[i] = var; 98 sivar += i; 99 } 100 return tmain<int>(); 101 #endif 102 } 103 104 105 106 // Skip global, bound tid and loop vars 107 108 // private(s_arr) 109 110 // private(var) 111 112 113 114 115 116 // Skip global, bound tid and loop vars 117 118 // private(s_arr) 119 120 121 // private(var) 122 123 124 #endif 125 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 126 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 127 // CHECK1-NEXT: entry: 128 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 129 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 130 // CHECK1-NEXT: ret void 131 // 132 // 133 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 134 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 135 // CHECK1-NEXT: entry: 136 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 137 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 138 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 139 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 140 // CHECK1-NEXT: ret void 141 // 142 // 143 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 144 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 145 // CHECK1-NEXT: entry: 146 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 147 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 148 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 149 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 150 // CHECK1-NEXT: ret void 151 // 152 // 153 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 154 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 155 // CHECK1-NEXT: entry: 156 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 157 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 158 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 159 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 160 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 161 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 162 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 163 // CHECK1-NEXT: ret void 164 // 165 // 166 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 167 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 168 // CHECK1-NEXT: entry: 169 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 170 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 171 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 172 // CHECK1-NEXT: ret void 173 // 174 // 175 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 176 // CHECK1-SAME: () #[[ATTR0]] { 177 // CHECK1-NEXT: entry: 178 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 179 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 180 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 181 // CHECK1-NEXT: ret void 182 // 183 // 184 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 185 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 186 // CHECK1-NEXT: entry: 187 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 188 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 189 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 190 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 191 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 192 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 193 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 194 // CHECK1-NEXT: ret void 195 // 196 // 197 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 198 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 199 // CHECK1-NEXT: entry: 200 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 201 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 202 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 203 // CHECK1: arraydestroy.body: 204 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 205 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 206 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 207 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 208 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 209 // CHECK1: arraydestroy.done1: 210 // CHECK1-NEXT: ret void 211 // 212 // 213 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 214 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 215 // CHECK1-NEXT: entry: 216 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 217 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 218 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 219 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 220 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 221 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 222 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 223 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 224 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 225 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 226 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 227 // CHECK1-NEXT: ret void 228 // 229 // 230 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 231 // CHECK1-SAME: () #[[ATTR0]] { 232 // CHECK1-NEXT: entry: 233 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 234 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 235 // CHECK1-NEXT: ret void 236 // 237 // 238 // CHECK1-LABEL: define {{[^@]+}}@main 239 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 240 // CHECK1-NEXT: entry: 241 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 242 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 243 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 244 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 245 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 246 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 247 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 248 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 249 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 250 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 251 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 252 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 253 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 254 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 255 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 256 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 257 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 258 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 259 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 260 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 261 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 262 // CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8 263 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 264 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 265 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 266 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 267 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 268 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 269 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 270 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 271 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, ptr [[KERNEL_ARGS]]) 272 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 273 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 274 // CHECK1: omp_offload.failed: 275 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR2]] 276 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 277 // CHECK1: omp_offload.cont: 278 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 279 // CHECK1-NEXT: ret i32 [[CALL]] 280 // 281 // 282 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93 283 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 284 // CHECK1-NEXT: entry: 285 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.omp_outlined) 286 // CHECK1-NEXT: ret void 287 // 288 // 289 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.omp_outlined 290 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 291 // CHECK1-NEXT: entry: 292 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 293 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 294 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 295 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 296 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 297 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 298 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 299 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 300 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 301 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 302 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 303 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 304 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 305 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 306 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 307 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 308 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 309 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 310 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 311 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 312 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 313 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 314 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 315 // CHECK1: arrayctor.loop: 316 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 317 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 318 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 319 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 320 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 321 // CHECK1: arrayctor.cont: 322 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 323 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 324 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 325 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 326 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 327 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 328 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 329 // CHECK1: cond.true: 330 // CHECK1-NEXT: br label [[COND_END:%.*]] 331 // CHECK1: cond.false: 332 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 333 // CHECK1-NEXT: br label [[COND_END]] 334 // CHECK1: cond.end: 335 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 336 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 337 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 338 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 339 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 340 // CHECK1: omp.inner.for.cond: 341 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 342 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 343 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 344 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 345 // CHECK1: omp.inner.for.cond.cleanup: 346 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 347 // CHECK1: omp.inner.for.body: 348 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 349 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 350 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 351 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 352 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 353 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 354 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 355 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 356 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 357 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 358 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 359 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] 360 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) 361 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 362 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 363 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 364 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[SIVAR]], align 4 365 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 366 // CHECK1: omp.body.continue: 367 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 368 // CHECK1: omp.inner.for.inc: 369 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 370 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 371 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 372 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 373 // CHECK1: omp.inner.for.end: 374 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 375 // CHECK1: omp.loop.exit: 376 // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 377 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 378 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) 379 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 380 // CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 381 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2 382 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 383 // CHECK1: arraydestroy.body: 384 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 385 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 386 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 387 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 388 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 389 // CHECK1: arraydestroy.done7: 390 // CHECK1-NEXT: ret void 391 // 392 // 393 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 394 // CHECK1-SAME: () #[[ATTR1]] comdat { 395 // CHECK1-NEXT: entry: 396 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 397 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 398 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 399 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 400 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 401 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 402 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 403 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 404 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 405 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 406 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 407 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 408 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 409 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 410 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 411 // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 412 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 413 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 414 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 415 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 416 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 417 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 418 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 419 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 420 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 421 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 422 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 423 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 424 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 425 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 426 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 427 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 428 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 429 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 430 // CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8 431 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 432 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 433 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 434 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 435 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 436 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 437 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 438 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 439 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 440 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 441 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 442 // CHECK1: omp_offload.failed: 443 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 444 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 445 // CHECK1: omp_offload.cont: 446 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 447 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 448 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 449 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 450 // CHECK1: arraydestroy.body: 451 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 452 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 453 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 454 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 455 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 456 // CHECK1: arraydestroy.done2: 457 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 458 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 459 // CHECK1-NEXT: ret i32 [[TMP16]] 460 // 461 // 462 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 463 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 464 // CHECK1-NEXT: entry: 465 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 466 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 467 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 468 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 469 // CHECK1-NEXT: ret void 470 // 471 // 472 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 473 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 474 // CHECK1-NEXT: entry: 475 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 476 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 477 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 478 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 479 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 480 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 481 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 482 // CHECK1-NEXT: ret void 483 // 484 // 485 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 486 // CHECK1-SAME: () #[[ATTR4]] { 487 // CHECK1-NEXT: entry: 488 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined) 489 // CHECK1-NEXT: ret void 490 // 491 // 492 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 493 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 494 // CHECK1-NEXT: entry: 495 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 496 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 497 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 498 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 499 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 500 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 501 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 502 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 503 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 504 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 505 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 506 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 507 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 508 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 509 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 510 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 511 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 512 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 513 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 514 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 515 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 516 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 517 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 518 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 519 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 520 // CHECK1: arrayctor.loop: 521 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 522 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 523 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 524 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 525 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 526 // CHECK1: arrayctor.cont: 527 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 528 // CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 8 529 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 530 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 531 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 532 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 533 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 534 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 535 // CHECK1: cond.true: 536 // CHECK1-NEXT: br label [[COND_END:%.*]] 537 // CHECK1: cond.false: 538 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 539 // CHECK1-NEXT: br label [[COND_END]] 540 // CHECK1: cond.end: 541 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 542 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 543 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 544 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 545 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 546 // CHECK1: omp.inner.for.cond: 547 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 548 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 549 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 550 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 551 // CHECK1: omp.inner.for.cond.cleanup: 552 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 553 // CHECK1: omp.inner.for.body: 554 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 555 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 556 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 557 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 558 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 559 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 560 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 561 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 562 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 563 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 564 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 565 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 566 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] 567 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) 568 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 569 // CHECK1: omp.body.continue: 570 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 571 // CHECK1: omp.inner.for.inc: 572 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 573 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 574 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 575 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 576 // CHECK1: omp.inner.for.end: 577 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 578 // CHECK1: omp.loop.exit: 579 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 580 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 581 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 582 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 583 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 584 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 585 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 586 // CHECK1: arraydestroy.body: 587 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 588 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 589 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 590 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 591 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 592 // CHECK1: arraydestroy.done8: 593 // CHECK1-NEXT: ret void 594 // 595 // 596 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 597 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 598 // CHECK1-NEXT: entry: 599 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 600 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 601 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 602 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 603 // CHECK1-NEXT: ret void 604 // 605 // 606 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 607 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 608 // CHECK1-NEXT: entry: 609 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 610 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 611 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 612 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 613 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 614 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 615 // CHECK1-NEXT: ret void 616 // 617 // 618 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 619 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 620 // CHECK1-NEXT: entry: 621 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 622 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 623 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 624 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 625 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 626 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 627 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 628 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 629 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 630 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 631 // CHECK1-NEXT: ret void 632 // 633 // 634 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 635 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 636 // CHECK1-NEXT: entry: 637 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 638 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 639 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 640 // CHECK1-NEXT: ret void 641 // 642 // 643 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp 644 // CHECK1-SAME: () #[[ATTR0]] { 645 // CHECK1-NEXT: entry: 646 // CHECK1-NEXT: call void @__cxx_global_var_init() 647 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 648 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 649 // CHECK1-NEXT: ret void 650 // 651 // 652 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 653 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 654 // CHECK3-NEXT: entry: 655 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 656 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 657 // CHECK3-NEXT: ret void 658 // 659 // 660 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 661 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 662 // CHECK3-NEXT: entry: 663 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 664 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 665 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 666 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 667 // CHECK3-NEXT: ret void 668 // 669 // 670 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 671 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 672 // CHECK3-NEXT: entry: 673 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 674 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 675 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 676 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 677 // CHECK3-NEXT: ret void 678 // 679 // 680 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 681 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 682 // CHECK3-NEXT: entry: 683 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 684 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 685 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 686 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 687 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 688 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 689 // CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4 690 // CHECK3-NEXT: ret void 691 // 692 // 693 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 694 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 695 // CHECK3-NEXT: entry: 696 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 697 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 698 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 699 // CHECK3-NEXT: ret void 700 // 701 // 702 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 703 // CHECK3-SAME: () #[[ATTR0]] { 704 // CHECK3-NEXT: entry: 705 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 706 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 707 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 708 // CHECK3-NEXT: ret void 709 // 710 // 711 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 712 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 713 // CHECK3-NEXT: entry: 714 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 715 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 716 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 717 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 718 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 719 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 720 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 721 // CHECK3-NEXT: ret void 722 // 723 // 724 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 725 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 726 // CHECK3-NEXT: entry: 727 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 728 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 729 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 730 // CHECK3: arraydestroy.body: 731 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 732 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 733 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 734 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 735 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 736 // CHECK3: arraydestroy.done1: 737 // CHECK3-NEXT: ret void 738 // 739 // 740 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 741 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 742 // CHECK3-NEXT: entry: 743 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 744 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 745 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 746 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 747 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 748 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 749 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 750 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 751 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 752 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 753 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 754 // CHECK3-NEXT: ret void 755 // 756 // 757 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 758 // CHECK3-SAME: () #[[ATTR0]] { 759 // CHECK3-NEXT: entry: 760 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 761 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 762 // CHECK3-NEXT: ret void 763 // 764 // 765 // CHECK3-LABEL: define {{[^@]+}}@main 766 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 767 // CHECK3-NEXT: entry: 768 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 769 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 770 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 771 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 772 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 773 // CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4 774 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 775 // CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4 776 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 777 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 778 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 779 // CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4 780 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 781 // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 782 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 783 // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 784 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 785 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 786 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 787 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 788 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 789 // CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8 790 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 791 // CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8 792 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 793 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 794 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 795 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 796 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 797 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 798 // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, ptr [[KERNEL_ARGS]]) 799 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 800 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 801 // CHECK3: omp_offload.failed: 802 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR2]] 803 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 804 // CHECK3: omp_offload.cont: 805 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 806 // CHECK3-NEXT: ret i32 [[CALL]] 807 // 808 // 809 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93 810 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 811 // CHECK3-NEXT: entry: 812 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.omp_outlined) 813 // CHECK3-NEXT: ret void 814 // 815 // 816 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.omp_outlined 817 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 818 // CHECK3-NEXT: entry: 819 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 820 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 821 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 822 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 823 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 824 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 825 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 826 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 827 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 828 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 829 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 830 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 831 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 832 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 833 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 834 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 835 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 836 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 837 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 838 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 839 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 840 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 841 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 842 // CHECK3: arrayctor.loop: 843 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 844 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 845 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 846 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 847 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 848 // CHECK3: arrayctor.cont: 849 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 850 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 851 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 852 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 853 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 854 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 855 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 856 // CHECK3: cond.true: 857 // CHECK3-NEXT: br label [[COND_END:%.*]] 858 // CHECK3: cond.false: 859 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 860 // CHECK3-NEXT: br label [[COND_END]] 861 // CHECK3: cond.end: 862 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 863 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 864 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 865 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 866 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 867 // CHECK3: omp.inner.for.cond: 868 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 869 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 870 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 871 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 872 // CHECK3: omp.inner.for.cond.cleanup: 873 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 874 // CHECK3: omp.inner.for.body: 875 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 876 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 877 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 878 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 879 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 880 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 881 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] 882 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 883 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 884 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] 885 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) 886 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 887 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 888 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 889 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4 890 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 891 // CHECK3: omp.body.continue: 892 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 893 // CHECK3: omp.inner.for.inc: 894 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 895 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 896 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 897 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 898 // CHECK3: omp.inner.for.end: 899 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 900 // CHECK3: omp.loop.exit: 901 // CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 902 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 903 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) 904 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 905 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 906 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 907 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 908 // CHECK3: arraydestroy.body: 909 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 910 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 911 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 912 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 913 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 914 // CHECK3: arraydestroy.done6: 915 // CHECK3-NEXT: ret void 916 // 917 // 918 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 919 // CHECK3-SAME: () #[[ATTR1]] comdat { 920 // CHECK3-NEXT: entry: 921 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 922 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 923 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 924 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 925 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 926 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 927 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 928 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 929 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 930 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 931 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 932 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 933 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 934 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 935 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 936 // CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 937 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 938 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 939 // CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4 940 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 941 // CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4 942 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 943 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 944 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 945 // CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4 946 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 947 // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 948 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 949 // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 950 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 951 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 952 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 953 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 954 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 955 // CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8 956 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 957 // CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8 958 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 959 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 960 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 961 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 962 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 963 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 964 // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 965 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 966 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 967 // CHECK3: omp_offload.failed: 968 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 969 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 970 // CHECK3: omp_offload.cont: 971 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 972 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 973 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 974 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 975 // CHECK3: arraydestroy.body: 976 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 977 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 978 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 979 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 980 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 981 // CHECK3: arraydestroy.done2: 982 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 983 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 984 // CHECK3-NEXT: ret i32 [[TMP16]] 985 // 986 // 987 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 988 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 989 // CHECK3-NEXT: entry: 990 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 991 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 992 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 993 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 994 // CHECK3-NEXT: ret void 995 // 996 // 997 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 998 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 999 // CHECK3-NEXT: entry: 1000 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1001 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1002 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1003 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1004 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1005 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1006 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1007 // CHECK3-NEXT: ret void 1008 // 1009 // 1010 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1011 // CHECK3-SAME: () #[[ATTR4]] { 1012 // CHECK3-NEXT: entry: 1013 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined) 1014 // CHECK3-NEXT: ret void 1015 // 1016 // 1017 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 1018 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1019 // CHECK3-NEXT: entry: 1020 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1021 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1022 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1023 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1024 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 1025 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1026 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1027 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1028 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1029 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1030 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1031 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1032 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1033 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 1034 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1035 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1036 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1037 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 1038 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1039 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1040 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1041 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1042 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1043 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1044 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1045 // CHECK3: arrayctor.loop: 1046 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1047 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1048 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 1049 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1050 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1051 // CHECK3: arrayctor.cont: 1052 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1053 // CHECK3-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 4 1054 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1055 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1056 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1057 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1058 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1059 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1060 // CHECK3: cond.true: 1061 // CHECK3-NEXT: br label [[COND_END:%.*]] 1062 // CHECK3: cond.false: 1063 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1064 // CHECK3-NEXT: br label [[COND_END]] 1065 // CHECK3: cond.end: 1066 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1067 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1068 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1069 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1070 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1071 // CHECK3: omp.inner.for.cond: 1072 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1073 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1074 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1075 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1076 // CHECK3: omp.inner.for.cond.cleanup: 1077 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1078 // CHECK3: omp.inner.for.body: 1079 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1080 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1081 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1082 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1083 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 1084 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 1085 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] 1086 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 1087 // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 1088 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 1089 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] 1090 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) 1091 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1092 // CHECK3: omp.body.continue: 1093 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1094 // CHECK3: omp.inner.for.inc: 1095 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1096 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1 1097 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 1098 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1099 // CHECK3: omp.inner.for.end: 1100 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1101 // CHECK3: omp.loop.exit: 1102 // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1103 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 1104 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 1105 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1106 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1107 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 1108 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1109 // CHECK3: arraydestroy.body: 1110 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1111 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1112 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1113 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 1114 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1115 // CHECK3: arraydestroy.done7: 1116 // CHECK3-NEXT: ret void 1117 // 1118 // 1119 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1120 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1121 // CHECK3-NEXT: entry: 1122 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1123 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1124 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1125 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1126 // CHECK3-NEXT: ret void 1127 // 1128 // 1129 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1130 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1131 // CHECK3-NEXT: entry: 1132 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1133 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1134 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1135 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1136 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1137 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1138 // CHECK3-NEXT: ret void 1139 // 1140 // 1141 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1142 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1143 // CHECK3-NEXT: entry: 1144 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1145 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1146 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1147 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1148 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1149 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1150 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1151 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1152 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1153 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1154 // CHECK3-NEXT: ret void 1155 // 1156 // 1157 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1158 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1159 // CHECK3-NEXT: entry: 1160 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1161 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1162 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1163 // CHECK3-NEXT: ret void 1164 // 1165 // 1166 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp 1167 // CHECK3-SAME: () #[[ATTR0]] { 1168 // CHECK3-NEXT: entry: 1169 // CHECK3-NEXT: call void @__cxx_global_var_init() 1170 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1171 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1172 // CHECK3-NEXT: ret void 1173 // 1174 // 1175 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 1176 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 1177 // CHECK9-NEXT: entry: 1178 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 1179 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 1180 // CHECK9-NEXT: ret void 1181 // 1182 // 1183 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1184 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 1185 // CHECK9-NEXT: entry: 1186 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1187 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1188 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1189 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1190 // CHECK9-NEXT: ret void 1191 // 1192 // 1193 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1194 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1195 // CHECK9-NEXT: entry: 1196 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1197 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1198 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1199 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1200 // CHECK9-NEXT: ret void 1201 // 1202 // 1203 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1204 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1205 // CHECK9-NEXT: entry: 1206 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1207 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1208 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1209 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1210 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1211 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1212 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 1213 // CHECK9-NEXT: ret void 1214 // 1215 // 1216 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1217 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1218 // CHECK9-NEXT: entry: 1219 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1220 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1221 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1222 // CHECK9-NEXT: ret void 1223 // 1224 // 1225 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1226 // CHECK9-SAME: () #[[ATTR0]] { 1227 // CHECK9-NEXT: entry: 1228 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 1229 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 1230 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 1231 // CHECK9-NEXT: ret void 1232 // 1233 // 1234 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1235 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1236 // CHECK9-NEXT: entry: 1237 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1238 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1239 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1240 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1241 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1242 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1243 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1244 // CHECK9-NEXT: ret void 1245 // 1246 // 1247 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1248 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1249 // CHECK9-NEXT: entry: 1250 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1251 // CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1252 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1253 // CHECK9: arraydestroy.body: 1254 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1255 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1256 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1257 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1258 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1259 // CHECK9: arraydestroy.done1: 1260 // CHECK9-NEXT: ret void 1261 // 1262 // 1263 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1264 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1265 // CHECK9-NEXT: entry: 1266 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1267 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1268 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1269 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1270 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1271 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1272 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1273 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1274 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1275 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1276 // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 1277 // CHECK9-NEXT: ret void 1278 // 1279 // 1280 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1281 // CHECK9-SAME: () #[[ATTR0]] { 1282 // CHECK9-NEXT: entry: 1283 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1284 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1285 // CHECK9-NEXT: ret void 1286 // 1287 // 1288 // CHECK9-LABEL: define {{[^@]+}}@main 1289 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 1290 // CHECK9-NEXT: entry: 1291 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1292 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1293 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 1294 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 1295 // CHECK9-NEXT: ret i32 0 1296 // 1297 // 1298 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 1299 // CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR4:[0-9]+]] { 1300 // CHECK9-NEXT: entry: 1301 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 1302 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1303 // CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 1304 // CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 1305 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined) 1306 // CHECK9-NEXT: ret void 1307 // 1308 // 1309 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined 1310 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1311 // CHECK9-NEXT: entry: 1312 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1313 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1314 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1315 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1316 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1317 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1318 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1319 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1320 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1321 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 1322 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 1323 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 1324 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1325 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1326 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1327 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1328 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1329 // CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 8 1330 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1331 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1332 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1333 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1334 // CHECK9-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 8 1335 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1336 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1337 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1338 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1339 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1340 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1341 // CHECK9: cond.true: 1342 // CHECK9-NEXT: br label [[COND_END:%.*]] 1343 // CHECK9: cond.false: 1344 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1345 // CHECK9-NEXT: br label [[COND_END]] 1346 // CHECK9: cond.end: 1347 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1348 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1349 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1350 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1351 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1352 // CHECK9: omp.inner.for.cond: 1353 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1354 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1355 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1356 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1357 // CHECK9: omp.inner.for.body: 1358 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1359 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1360 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1361 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1362 // CHECK9-NEXT: store i32 1, ptr [[G]], align 4 1363 // CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 1364 // CHECK9-NEXT: store volatile i32 1, ptr [[TMP8]], align 4 1365 // CHECK9-NEXT: store i32 2, ptr [[SIVAR]], align 4 1366 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 1367 // CHECK9-NEXT: store ptr [[G]], ptr [[TMP9]], align 8 1368 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 1369 // CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8 1370 // CHECK9-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8 1371 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 1372 // CHECK9-NEXT: store ptr [[SIVAR]], ptr [[TMP12]], align 8 1373 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 1374 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1375 // CHECK9: omp.body.continue: 1376 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1377 // CHECK9: omp.inner.for.inc: 1378 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1379 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 1380 // CHECK9-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 1381 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 1382 // CHECK9: omp.inner.for.end: 1383 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1384 // CHECK9: omp.loop.exit: 1385 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1386 // CHECK9-NEXT: ret void 1387 // 1388 // 1389 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp 1390 // CHECK9-SAME: () #[[ATTR0]] { 1391 // CHECK9-NEXT: entry: 1392 // CHECK9-NEXT: call void @__cxx_global_var_init() 1393 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 1394 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 1395 // CHECK9-NEXT: ret void 1396 // 1397