1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 template <typename T> 29 T tmain() { 30 T t_var = T(); 31 T vec[] = {1, 2}; 32 #pragma omp target 33 #pragma omp teams distribute parallel for simd reduction(+: t_var) 34 for (int i = 0; i < 2; ++i) { 35 t_var += (T) i; 36 } 37 return T(); 38 } 39 40 int main() { 41 static int sivar; 42 #ifdef LAMBDA 43 44 [&]() { 45 #pragma omp target 46 #pragma omp teams distribute parallel for simd reduction(+: sivar) 47 for (int i = 0; i < 2; ++i) { 48 49 // Skip global and bound tid vars 50 51 52 53 // Skip global and bound tid vars, and prev lb and ub vars 54 // skip loop vars 55 56 57 sivar += i; 58 59 [&]() { 60 61 sivar += 4; 62 63 }(); 64 } 65 }(); 66 return 0; 67 68 69 #else 70 #pragma omp target 71 #pragma omp teams distribute parallel for simd reduction(+: sivar) 72 for (int i = 0; i < 2; ++i) { 73 sivar += i; 74 } 75 return tmain<int>(); 76 #endif 77 } 78 79 80 81 82 // Skip global and bound tid vars 83 84 85 // Skip global and bound tid vars, and prev lb and ub 86 // skip loop vars 87 88 89 90 91 // Skip global and bound tid vars 92 93 94 // Skip global and bound tid vars, and prev lb and ub vars 95 // skip loop vars 96 97 98 99 #endif 100 // CHECK1-LABEL: define {{[^@]+}}@main 101 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 102 // CHECK1-NEXT: entry: 103 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 104 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 105 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 106 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 107 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 108 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 109 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 110 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 111 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 112 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[SIVAR_CASTED]], align 4 113 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 114 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 115 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8 116 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 117 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8 118 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 119 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 120 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 121 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 122 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 123 // CHECK1-NEXT: store i32 3, ptr [[TMP7]], align 4 124 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 125 // CHECK1-NEXT: store i32 1, ptr [[TMP8]], align 4 126 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 127 // CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8 128 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 129 // CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8 130 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 131 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP11]], align 8 132 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 133 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP12]], align 8 134 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 135 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8 136 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 137 // CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8 138 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 139 // CHECK1-NEXT: store i64 2, ptr [[TMP15]], align 8 140 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 141 // CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8 142 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 143 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 144 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 145 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 146 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 147 // CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4 148 // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.region_id, ptr [[KERNEL_ARGS]]) 149 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 150 // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 151 // CHECK1: omp_offload.failed: 152 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] 153 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 154 // CHECK1: omp_offload.cont: 155 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 156 // CHECK1-NEXT: ret i32 [[CALL]] 157 // 158 // 159 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70 160 // CHECK1-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 161 // CHECK1-NEXT: entry: 162 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 163 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 164 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined, ptr [[SIVAR_ADDR]]) 165 // CHECK1-NEXT: ret void 166 // 167 // 168 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined 169 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { 170 // CHECK1-NEXT: entry: 171 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 172 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 173 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 174 // CHECK1-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 175 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 176 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 177 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 178 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 179 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 180 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 181 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 182 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 183 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 184 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 185 // CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 186 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 187 // CHECK1-NEXT: store i32 0, ptr [[SIVAR1]], align 4 188 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 189 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 190 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 191 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 192 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 193 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 194 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 195 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 196 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 197 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 198 // CHECK1: cond.true: 199 // CHECK1-NEXT: br label [[COND_END:%.*]] 200 // CHECK1: cond.false: 201 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 202 // CHECK1-NEXT: br label [[COND_END]] 203 // CHECK1: cond.end: 204 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 205 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 206 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 207 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 208 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 209 // CHECK1: omp.inner.for.cond: 210 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] 211 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 212 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 213 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 214 // CHECK1: omp.inner.for.body: 215 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP5]] 216 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 217 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 218 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 219 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[SIVAR1]]), !llvm.access.group [[ACC_GRP5]] 220 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 221 // CHECK1: omp.inner.for.inc: 222 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 223 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP5]] 224 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 225 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 226 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 227 // CHECK1: omp.inner.for.end: 228 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 229 // CHECK1: omp.loop.exit: 230 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 231 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 232 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 233 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 234 // CHECK1: .omp.final.then: 235 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 236 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 237 // CHECK1: .omp.final.done: 238 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 239 // CHECK1-NEXT: store ptr [[SIVAR1]], ptr [[TMP16]], align 8 240 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 241 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 242 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 243 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 244 // CHECK1-NEXT: ] 245 // CHECK1: .omp.reduction.case1: 246 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 247 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR1]], align 4 248 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 249 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 250 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 251 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 252 // CHECK1: .omp.reduction.case2: 253 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR1]], align 4 254 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 255 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 256 // CHECK1: .omp.reduction.default: 257 // CHECK1-NEXT: ret void 258 // 259 // 260 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp_outlined 261 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { 262 // CHECK1-NEXT: entry: 263 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 264 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 265 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 266 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 267 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 268 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 269 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 270 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 271 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 272 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 273 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 274 // CHECK1-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 275 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 276 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 277 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 278 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 279 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 280 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 281 // CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 282 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 283 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 284 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 285 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 286 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 287 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 288 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 289 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 290 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 291 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 292 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 293 // CHECK1-NEXT: store i32 0, ptr [[SIVAR2]], align 4 294 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 295 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 296 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 297 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 298 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 299 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 300 // CHECK1: cond.true: 301 // CHECK1-NEXT: br label [[COND_END:%.*]] 302 // CHECK1: cond.false: 303 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 304 // CHECK1-NEXT: br label [[COND_END]] 305 // CHECK1: cond.end: 306 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 307 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 308 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 309 // CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 310 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 311 // CHECK1: omp.inner.for.cond: 312 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] 313 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 314 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 315 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 316 // CHECK1: omp.inner.for.body: 317 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 318 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 319 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 320 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 321 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 322 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR2]], align 4, !llvm.access.group [[ACC_GRP9]] 323 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 324 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[SIVAR2]], align 4, !llvm.access.group [[ACC_GRP9]] 325 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 326 // CHECK1: omp.body.continue: 327 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 328 // CHECK1: omp.inner.for.inc: 329 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 330 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 331 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 332 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 333 // CHECK1: omp.inner.for.end: 334 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 335 // CHECK1: omp.loop.exit: 336 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) 337 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 338 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 339 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 340 // CHECK1: .omp.final.then: 341 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 342 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 343 // CHECK1: .omp.final.done: 344 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 345 // CHECK1-NEXT: store ptr [[SIVAR2]], ptr [[TMP16]], align 8 346 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 347 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 348 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 349 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 350 // CHECK1-NEXT: ] 351 // CHECK1: .omp.reduction.case1: 352 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 353 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR2]], align 4 354 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 355 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[TMP0]], align 4 356 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) 357 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 358 // CHECK1: .omp.reduction.case2: 359 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR2]], align 4 360 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 361 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 362 // CHECK1: .omp.reduction.default: 363 // CHECK1-NEXT: ret void 364 // 365 // 366 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp_outlined.omp.reduction.reduction_func 367 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { 368 // CHECK1-NEXT: entry: 369 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 370 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 371 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 372 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 373 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 374 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 375 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 376 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 377 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 378 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 379 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 380 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 381 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 382 // CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 383 // CHECK1-NEXT: ret void 384 // 385 // 386 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp.reduction.reduction_func 387 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { 388 // CHECK1-NEXT: entry: 389 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 390 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 391 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 392 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 393 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 394 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 395 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 396 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 397 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 398 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 399 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 400 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 401 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 402 // CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 403 // CHECK1-NEXT: ret void 404 // 405 // 406 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 407 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] comdat { 408 // CHECK1-NEXT: entry: 409 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 410 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 411 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 412 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 413 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 414 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 415 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 416 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 417 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 418 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 419 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 420 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 421 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 422 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 423 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8 424 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 425 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8 426 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 427 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 428 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 429 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 430 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 431 // CHECK1-NEXT: store i32 3, ptr [[TMP7]], align 4 432 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 433 // CHECK1-NEXT: store i32 1, ptr [[TMP8]], align 4 434 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 435 // CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8 436 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 437 // CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8 438 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 439 // CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP11]], align 8 440 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 441 // CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP12]], align 8 442 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 443 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8 444 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 445 // CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8 446 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 447 // CHECK1-NEXT: store i64 2, ptr [[TMP15]], align 8 448 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 449 // CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8 450 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 451 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 452 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 453 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 454 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 455 // CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4 456 // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) 457 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 458 // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 459 // CHECK1: omp_offload.failed: 460 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i64 [[TMP1]]) #[[ATTR2]] 461 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 462 // CHECK1: omp_offload.cont: 463 // CHECK1-NEXT: ret i32 0 464 // 465 // 466 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 467 // CHECK1-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] { 468 // CHECK1-NEXT: entry: 469 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 470 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 471 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]]) 472 // CHECK1-NEXT: ret void 473 // 474 // 475 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined 476 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 477 // CHECK1-NEXT: entry: 478 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 479 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 480 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 481 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 482 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 483 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 484 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 485 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 486 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 487 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 488 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 489 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 490 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 491 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 492 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 493 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 494 // CHECK1-NEXT: store i32 0, ptr [[T_VAR1]], align 4 495 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 496 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 497 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 498 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 499 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 500 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 501 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 502 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 503 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 504 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 505 // CHECK1: cond.true: 506 // CHECK1-NEXT: br label [[COND_END:%.*]] 507 // CHECK1: cond.false: 508 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 509 // CHECK1-NEXT: br label [[COND_END]] 510 // CHECK1: cond.end: 511 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 512 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 513 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 514 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 515 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 516 // CHECK1: omp.inner.for.cond: 517 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]] 518 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]] 519 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 520 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 521 // CHECK1: omp.inner.for.body: 522 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP14]] 523 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 524 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]] 525 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 526 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[T_VAR1]]), !llvm.access.group [[ACC_GRP14]] 527 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 528 // CHECK1: omp.inner.for.inc: 529 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 530 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP14]] 531 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 532 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 533 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 534 // CHECK1: omp.inner.for.end: 535 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 536 // CHECK1: omp.loop.exit: 537 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 538 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 539 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 540 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 541 // CHECK1: .omp.final.then: 542 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 543 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 544 // CHECK1: .omp.final.done: 545 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 546 // CHECK1-NEXT: store ptr [[T_VAR1]], ptr [[TMP16]], align 8 547 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 548 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 549 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 550 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 551 // CHECK1-NEXT: ] 552 // CHECK1: .omp.reduction.case1: 553 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 554 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR1]], align 4 555 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 556 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 557 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 558 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 559 // CHECK1: .omp.reduction.case2: 560 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR1]], align 4 561 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 562 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 563 // CHECK1: .omp.reduction.default: 564 // CHECK1-NEXT: ret void 565 // 566 // 567 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined 568 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 569 // CHECK1-NEXT: entry: 570 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 571 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 572 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 573 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 574 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 575 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 576 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 577 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 578 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 579 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 580 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 581 // CHECK1-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 582 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 583 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 584 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 585 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 586 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 587 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 588 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 589 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 590 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 591 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 592 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 593 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 594 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 595 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 596 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 597 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 598 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 599 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 600 // CHECK1-NEXT: store i32 0, ptr [[T_VAR2]], align 4 601 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 602 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 603 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 604 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 605 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 606 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 607 // CHECK1: cond.true: 608 // CHECK1-NEXT: br label [[COND_END:%.*]] 609 // CHECK1: cond.false: 610 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 611 // CHECK1-NEXT: br label [[COND_END]] 612 // CHECK1: cond.end: 613 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 614 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 615 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 616 // CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 617 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 618 // CHECK1: omp.inner.for.cond: 619 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]] 620 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP17]] 621 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 622 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 623 // CHECK1: omp.inner.for.body: 624 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 625 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 626 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 627 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 628 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 629 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP17]] 630 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 631 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP17]] 632 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 633 // CHECK1: omp.body.continue: 634 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 635 // CHECK1: omp.inner.for.inc: 636 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 637 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 638 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 639 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 640 // CHECK1: omp.inner.for.end: 641 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 642 // CHECK1: omp.loop.exit: 643 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) 644 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 645 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 646 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 647 // CHECK1: .omp.final.then: 648 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 649 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 650 // CHECK1: .omp.final.done: 651 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 652 // CHECK1-NEXT: store ptr [[T_VAR2]], ptr [[TMP16]], align 8 653 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 654 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 655 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 656 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 657 // CHECK1-NEXT: ] 658 // CHECK1: .omp.reduction.case1: 659 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 660 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR2]], align 4 661 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 662 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[TMP0]], align 4 663 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) 664 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 665 // CHECK1: .omp.reduction.case2: 666 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR2]], align 4 667 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 668 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 669 // CHECK1: .omp.reduction.default: 670 // CHECK1-NEXT: ret void 671 // 672 // 673 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func 674 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { 675 // CHECK1-NEXT: entry: 676 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 677 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 678 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 679 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 680 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 681 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 682 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 683 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 684 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 685 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 686 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 687 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 688 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 689 // CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 690 // CHECK1-NEXT: ret void 691 // 692 // 693 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func 694 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { 695 // CHECK1-NEXT: entry: 696 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 697 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 698 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 699 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 700 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 701 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 702 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 703 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 704 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 705 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 706 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 707 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 708 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 709 // CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 710 // CHECK1-NEXT: ret void 711 // 712 // 713 // CHECK3-LABEL: define {{[^@]+}}@main 714 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 715 // CHECK3-NEXT: entry: 716 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 717 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 718 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 719 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 720 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 721 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 722 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 723 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 724 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 725 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[SIVAR_CASTED]], align 4 726 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 727 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 728 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4 729 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 730 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4 731 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 732 // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 733 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 734 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 735 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 736 // CHECK3-NEXT: store i32 3, ptr [[TMP7]], align 4 737 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 738 // CHECK3-NEXT: store i32 1, ptr [[TMP8]], align 4 739 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 740 // CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4 741 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 742 // CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4 743 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 744 // CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP11]], align 4 745 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 746 // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP12]], align 4 747 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 748 // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4 749 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 750 // CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4 751 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 752 // CHECK3-NEXT: store i64 2, ptr [[TMP15]], align 8 753 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 754 // CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8 755 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 756 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 757 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 758 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 759 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 760 // CHECK3-NEXT: store i32 0, ptr [[TMP19]], align 4 761 // CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.region_id, ptr [[KERNEL_ARGS]]) 762 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 763 // CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 764 // CHECK3: omp_offload.failed: 765 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] 766 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 767 // CHECK3: omp_offload.cont: 768 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 769 // CHECK3-NEXT: ret i32 [[CALL]] 770 // 771 // 772 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70 773 // CHECK3-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 774 // CHECK3-NEXT: entry: 775 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 776 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 777 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined, ptr [[SIVAR_ADDR]]) 778 // CHECK3-NEXT: ret void 779 // 780 // 781 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined 782 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { 783 // CHECK3-NEXT: entry: 784 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 785 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 786 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 4 787 // CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 788 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 789 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 790 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 791 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 792 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 793 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 794 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 795 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 796 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 797 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 798 // CHECK3-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 799 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4 800 // CHECK3-NEXT: store i32 0, ptr [[SIVAR1]], align 4 801 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 802 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 803 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 804 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 805 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 806 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 807 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 808 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 809 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 810 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 811 // CHECK3: cond.true: 812 // CHECK3-NEXT: br label [[COND_END:%.*]] 813 // CHECK3: cond.false: 814 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 815 // CHECK3-NEXT: br label [[COND_END]] 816 // CHECK3: cond.end: 817 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 818 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 819 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 820 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 821 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 822 // CHECK3: omp.inner.for.cond: 823 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 824 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 825 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 826 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 827 // CHECK3: omp.inner.for.body: 828 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP6]] 829 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 830 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp_outlined, i32 [[TMP8]], i32 [[TMP9]], ptr [[SIVAR1]]), !llvm.access.group [[ACC_GRP6]] 831 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 832 // CHECK3: omp.inner.for.inc: 833 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 834 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP6]] 835 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] 836 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 837 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 838 // CHECK3: omp.inner.for.end: 839 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 840 // CHECK3: omp.loop.exit: 841 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 842 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 843 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 844 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 845 // CHECK3: .omp.final.then: 846 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 847 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 848 // CHECK3: .omp.final.done: 849 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 850 // CHECK3-NEXT: store ptr [[SIVAR1]], ptr [[TMP14]], align 4 851 // CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 852 // CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 853 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 854 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 855 // CHECK3-NEXT: ] 856 // CHECK3: .omp.reduction.case1: 857 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 858 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR1]], align 4 859 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] 860 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 861 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 862 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 863 // CHECK3: .omp.reduction.case2: 864 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR1]], align 4 865 // CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 866 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 867 // CHECK3: .omp.reduction.default: 868 // CHECK3-NEXT: ret void 869 // 870 // 871 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp_outlined 872 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { 873 // CHECK3-NEXT: entry: 874 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 875 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 876 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 877 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 878 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 4 879 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 880 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 881 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 882 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 883 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 884 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 885 // CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 886 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 887 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 888 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 889 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 890 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 891 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 892 // CHECK3-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 893 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4 894 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 895 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 896 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 897 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 898 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4 899 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 900 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 901 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 902 // CHECK3-NEXT: store i32 0, ptr [[SIVAR1]], align 4 903 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 904 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 905 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 906 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 907 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 908 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 909 // CHECK3: cond.true: 910 // CHECK3-NEXT: br label [[COND_END:%.*]] 911 // CHECK3: cond.false: 912 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 913 // CHECK3-NEXT: br label [[COND_END]] 914 // CHECK3: cond.end: 915 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 916 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 917 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 918 // CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 919 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 920 // CHECK3: omp.inner.for.cond: 921 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 922 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 923 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 924 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 925 // CHECK3: omp.inner.for.body: 926 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 927 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 928 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 929 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 930 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 931 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP10]] 932 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 933 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP10]] 934 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 935 // CHECK3: omp.body.continue: 936 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 937 // CHECK3: omp.inner.for.inc: 938 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 939 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 940 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 941 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 942 // CHECK3: omp.inner.for.end: 943 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 944 // CHECK3: omp.loop.exit: 945 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) 946 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 947 // CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 948 // CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 949 // CHECK3: .omp.final.then: 950 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 951 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 952 // CHECK3: .omp.final.done: 953 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 954 // CHECK3-NEXT: store ptr [[SIVAR1]], ptr [[TMP16]], align 4 955 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 956 // CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 957 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 958 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 959 // CHECK3-NEXT: ] 960 // CHECK3: .omp.reduction.case1: 961 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 962 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR1]], align 4 963 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 964 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 965 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) 966 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 967 // CHECK3: .omp.reduction.case2: 968 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR1]], align 4 969 // CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 970 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 971 // CHECK3: .omp.reduction.default: 972 // CHECK3-NEXT: ret void 973 // 974 // 975 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp_outlined.omp.reduction.reduction_func 976 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { 977 // CHECK3-NEXT: entry: 978 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 979 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 980 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 981 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 982 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 4 983 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 984 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i32 0, i32 0 985 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 986 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i32 0, i32 0 987 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 988 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 989 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 990 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 991 // CHECK3-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 992 // CHECK3-NEXT: ret void 993 // 994 // 995 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp.reduction.reduction_func 996 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { 997 // CHECK3-NEXT: entry: 998 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 999 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 1000 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 1001 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 1002 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 4 1003 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 1004 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i32 0, i32 0 1005 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 1006 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i32 0, i32 0 1007 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 1008 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1009 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 1010 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 1011 // CHECK3-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 1012 // CHECK3-NEXT: ret void 1013 // 1014 // 1015 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1016 // CHECK3-SAME: () #[[ATTR5:[0-9]+]] comdat { 1017 // CHECK3-NEXT: entry: 1018 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1019 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1020 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1021 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 1022 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 1023 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 1024 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1025 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1026 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 1027 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 1028 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 1029 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 1030 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1031 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1032 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4 1033 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1034 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4 1035 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1036 // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 1037 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1038 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1039 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1040 // CHECK3-NEXT: store i32 3, ptr [[TMP7]], align 4 1041 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1042 // CHECK3-NEXT: store i32 1, ptr [[TMP8]], align 4 1043 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1044 // CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4 1045 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1046 // CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4 1047 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1048 // CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP11]], align 4 1049 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1050 // CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP12]], align 4 1051 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1052 // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4 1053 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1054 // CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4 1055 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1056 // CHECK3-NEXT: store i64 2, ptr [[TMP15]], align 8 1057 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1058 // CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8 1059 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1060 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 1061 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1062 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 1063 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1064 // CHECK3-NEXT: store i32 0, ptr [[TMP19]], align 4 1065 // CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) 1066 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 1067 // CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1068 // CHECK3: omp_offload.failed: 1069 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32 [[TMP1]]) #[[ATTR2]] 1070 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1071 // CHECK3: omp_offload.cont: 1072 // CHECK3-NEXT: ret i32 0 1073 // 1074 // 1075 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 1076 // CHECK3-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] { 1077 // CHECK3-NEXT: entry: 1078 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1079 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1080 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]]) 1081 // CHECK3-NEXT: ret void 1082 // 1083 // 1084 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined 1085 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 1086 // CHECK3-NEXT: entry: 1087 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1088 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1089 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 1090 // CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 1091 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1092 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1093 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1094 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1095 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1096 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1097 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1098 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 1099 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1100 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1101 // CHECK3-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1102 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 1103 // CHECK3-NEXT: store i32 0, ptr [[T_VAR1]], align 4 1104 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1105 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1106 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1107 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1108 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1109 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 1110 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1111 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1112 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 1113 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1114 // CHECK3: cond.true: 1115 // CHECK3-NEXT: br label [[COND_END:%.*]] 1116 // CHECK3: cond.false: 1117 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1118 // CHECK3-NEXT: br label [[COND_END]] 1119 // CHECK3: cond.end: 1120 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1121 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1122 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1123 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 1124 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1125 // CHECK3: omp.inner.for.cond: 1126 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] 1127 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 1128 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1129 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1130 // CHECK3: omp.inner.for.body: 1131 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]] 1132 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 1133 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined, i32 [[TMP8]], i32 [[TMP9]], ptr [[T_VAR1]]), !llvm.access.group [[ACC_GRP15]] 1134 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1135 // CHECK3: omp.inner.for.inc: 1136 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 1137 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]] 1138 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] 1139 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 1140 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 1141 // CHECK3: omp.inner.for.end: 1142 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1143 // CHECK3: omp.loop.exit: 1144 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 1145 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1146 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 1147 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1148 // CHECK3: .omp.final.then: 1149 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 1150 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1151 // CHECK3: .omp.final.done: 1152 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 1153 // CHECK3-NEXT: store ptr [[T_VAR1]], ptr [[TMP14]], align 4 1154 // CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 1155 // CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1156 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1157 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1158 // CHECK3-NEXT: ] 1159 // CHECK3: .omp.reduction.case1: 1160 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 1161 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR1]], align 4 1162 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] 1163 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 1164 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 1165 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1166 // CHECK3: .omp.reduction.case2: 1167 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR1]], align 4 1168 // CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 1169 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1170 // CHECK3: .omp.reduction.default: 1171 // CHECK3-NEXT: ret void 1172 // 1173 // 1174 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined 1175 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 1176 // CHECK3-NEXT: entry: 1177 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1178 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1179 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 1180 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 1181 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 1182 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1183 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1184 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1185 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1186 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1187 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1188 // CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 1189 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1190 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 1191 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1192 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1193 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1194 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1195 // CHECK3-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1196 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 1197 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1198 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1199 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1200 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1201 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4 1202 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 1203 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1204 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1205 // CHECK3-NEXT: store i32 0, ptr [[T_VAR1]], align 4 1206 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1207 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 1208 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1209 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1210 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 1211 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1212 // CHECK3: cond.true: 1213 // CHECK3-NEXT: br label [[COND_END:%.*]] 1214 // CHECK3: cond.false: 1215 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1216 // CHECK3-NEXT: br label [[COND_END]] 1217 // CHECK3: cond.end: 1218 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 1219 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1220 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1221 // CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 1222 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1223 // CHECK3: omp.inner.for.cond: 1224 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] 1225 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] 1226 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 1227 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1228 // CHECK3: omp.inner.for.body: 1229 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 1230 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 1231 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1232 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 1233 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 1234 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP18]] 1235 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 1236 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP18]] 1237 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1238 // CHECK3: omp.body.continue: 1239 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1240 // CHECK3: omp.inner.for.inc: 1241 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 1242 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 1243 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 1244 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 1245 // CHECK3: omp.inner.for.end: 1246 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1247 // CHECK3: omp.loop.exit: 1248 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) 1249 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1250 // CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 1251 // CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1252 // CHECK3: .omp.final.then: 1253 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 1254 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1255 // CHECK3: .omp.final.done: 1256 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 1257 // CHECK3-NEXT: store ptr [[T_VAR1]], ptr [[TMP16]], align 4 1258 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 1259 // CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1260 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1261 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1262 // CHECK3-NEXT: ] 1263 // CHECK3: .omp.reduction.case1: 1264 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 1265 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR1]], align 4 1266 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 1267 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 1268 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) 1269 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1270 // CHECK3: .omp.reduction.case2: 1271 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR1]], align 4 1272 // CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 1273 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1274 // CHECK3: .omp.reduction.default: 1275 // CHECK3-NEXT: ret void 1276 // 1277 // 1278 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func 1279 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { 1280 // CHECK3-NEXT: entry: 1281 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 1282 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 1283 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 1284 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 1285 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 4 1286 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 1287 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i32 0, i32 0 1288 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 1289 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i32 0, i32 0 1290 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 1291 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1292 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 1293 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 1294 // CHECK3-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 1295 // CHECK3-NEXT: ret void 1296 // 1297 // 1298 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func 1299 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { 1300 // CHECK3-NEXT: entry: 1301 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 1302 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 1303 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 1304 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 1305 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 4 1306 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 1307 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i32 0, i32 0 1308 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 1309 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i32 0, i32 0 1310 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 1311 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1312 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 1313 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 1314 // CHECK3-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 1315 // CHECK3-NEXT: ret void 1316 // 1317 // 1318 // CHECK5-LABEL: define {{[^@]+}}@main 1319 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 1320 // CHECK5-NEXT: entry: 1321 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1322 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1323 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1324 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1325 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1326 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1327 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1328 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 1329 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1330 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1331 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1332 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 1333 // CHECK5-NEXT: store i32 0, ptr [[SIVAR]], align 4 1334 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1335 // CHECK5: omp.inner.for.cond: 1336 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 1337 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 1338 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1339 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1340 // CHECK5: omp.inner.for.body: 1341 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1342 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1343 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1344 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1345 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1346 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] 1347 // CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 1348 // CHECK5-NEXT: store i32 [[ADD1]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] 1349 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1350 // CHECK5: omp.body.continue: 1351 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1352 // CHECK5: omp.inner.for.inc: 1353 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1354 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 1355 // CHECK5-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1356 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1357 // CHECK5: omp.inner.for.end: 1358 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 1359 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 1360 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4 1361 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 1362 // CHECK5-NEXT: store i32 [[ADD3]], ptr @_ZZ4mainE5sivar, align 4 1363 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 1364 // CHECK5-NEXT: ret i32 [[CALL]] 1365 // 1366 // 1367 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1368 // CHECK5-SAME: () #[[ATTR1:[0-9]+]] comdat { 1369 // CHECK5-NEXT: entry: 1370 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1371 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1372 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1373 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1374 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1375 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1376 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1377 // CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 1378 // CHECK5-NEXT: store i32 0, ptr [[T_VAR]], align 4 1379 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 1380 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1381 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1382 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1383 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 1384 // CHECK5-NEXT: store i32 0, ptr [[T_VAR1]], align 4 1385 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1386 // CHECK5: omp.inner.for.cond: 1387 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 1388 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 1389 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1390 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1391 // CHECK5: omp.inner.for.body: 1392 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1393 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1394 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1395 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1396 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1397 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP6]] 1398 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 1399 // CHECK5-NEXT: store i32 [[ADD2]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP6]] 1400 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1401 // CHECK5: omp.body.continue: 1402 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1403 // CHECK5: omp.inner.for.inc: 1404 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1405 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP6]], 1 1406 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1407 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1408 // CHECK5: omp.inner.for.end: 1409 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 1410 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4 1411 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR1]], align 4 1412 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 1413 // CHECK5-NEXT: store i32 [[ADD4]], ptr [[T_VAR]], align 4 1414 // CHECK5-NEXT: ret i32 0 1415 // 1416 // 1417 // CHECK7-LABEL: define {{[^@]+}}@main 1418 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 1419 // CHECK7-NEXT: entry: 1420 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1421 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 1422 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1423 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1424 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1425 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 1426 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1427 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 1428 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1429 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1430 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1431 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 1432 // CHECK7-NEXT: store i32 0, ptr [[SIVAR]], align 4 1433 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1434 // CHECK7: omp.inner.for.cond: 1435 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 1436 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 1437 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1438 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1439 // CHECK7: omp.inner.for.body: 1440 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 1441 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1442 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1443 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 1444 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 1445 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] 1446 // CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 1447 // CHECK7-NEXT: store i32 [[ADD1]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] 1448 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1449 // CHECK7: omp.body.continue: 1450 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1451 // CHECK7: omp.inner.for.inc: 1452 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 1453 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 1454 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 1455 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 1456 // CHECK7: omp.inner.for.end: 1457 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 1458 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 1459 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4 1460 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 1461 // CHECK7-NEXT: store i32 [[ADD3]], ptr @_ZZ4mainE5sivar, align 4 1462 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1463 // CHECK7-NEXT: ret i32 [[CALL]] 1464 // 1465 // 1466 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1467 // CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat { 1468 // CHECK7-NEXT: entry: 1469 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1470 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1471 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 1472 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1473 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1474 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1475 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 1476 // CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 1477 // CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 4 1478 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 1479 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1480 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1481 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1482 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 1483 // CHECK7-NEXT: store i32 0, ptr [[T_VAR1]], align 4 1484 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1485 // CHECK7: omp.inner.for.cond: 1486 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 1487 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]] 1488 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1489 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1490 // CHECK7: omp.inner.for.body: 1491 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 1492 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1493 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1494 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 1495 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 1496 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP7]] 1497 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 1498 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP7]] 1499 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1500 // CHECK7: omp.body.continue: 1501 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1502 // CHECK7: omp.inner.for.inc: 1503 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 1504 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP6]], 1 1505 // CHECK7-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 1506 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 1507 // CHECK7: omp.inner.for.end: 1508 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 1509 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4 1510 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR1]], align 4 1511 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 1512 // CHECK7-NEXT: store i32 [[ADD4]], ptr [[T_VAR]], align 4 1513 // CHECK7-NEXT: ret i32 0 1514 // 1515 // 1516 // CHECK9-LABEL: define {{[^@]+}}@main 1517 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 1518 // CHECK9-NEXT: entry: 1519 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1520 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1521 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 1522 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 1523 // CHECK9-NEXT: ret i32 0 1524 // 1525 // 1526 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 1527 // CHECK9-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 1528 // CHECK9-NEXT: entry: 1529 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 1530 // CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 1531 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined, ptr [[SIVAR_ADDR]]) 1532 // CHECK9-NEXT: ret void 1533 // 1534 // 1535 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined 1536 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { 1537 // CHECK9-NEXT: entry: 1538 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1539 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1540 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 1541 // CHECK9-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 1542 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1543 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1544 // CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1545 // CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1546 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1547 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1548 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1549 // CHECK9-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 1550 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1551 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1552 // CHECK9-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 1553 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 1554 // CHECK9-NEXT: store i32 0, ptr [[SIVAR1]], align 4 1555 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1556 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1557 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1558 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1559 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1560 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 1561 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1562 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1563 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 1564 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1565 // CHECK9: cond.true: 1566 // CHECK9-NEXT: br label [[COND_END:%.*]] 1567 // CHECK9: cond.false: 1568 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1569 // CHECK9-NEXT: br label [[COND_END]] 1570 // CHECK9: cond.end: 1571 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1572 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1573 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1574 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 1575 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1576 // CHECK9: omp.inner.for.cond: 1577 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]] 1578 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]] 1579 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1580 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1581 // CHECK9: omp.inner.for.body: 1582 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP4]] 1583 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 1584 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]] 1585 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 1586 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[SIVAR1]]), !llvm.access.group [[ACC_GRP4]] 1587 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1588 // CHECK9: omp.inner.for.inc: 1589 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 1590 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP4]] 1591 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 1592 // CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 1593 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 1594 // CHECK9: omp.inner.for.end: 1595 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1596 // CHECK9: omp.loop.exit: 1597 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 1598 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1599 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 1600 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1601 // CHECK9: .omp.final.then: 1602 // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 1603 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 1604 // CHECK9: .omp.final.done: 1605 // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 1606 // CHECK9-NEXT: store ptr [[SIVAR1]], ptr [[TMP16]], align 8 1607 // CHECK9-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 1608 // CHECK9-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1609 // CHECK9-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1610 // CHECK9-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1611 // CHECK9-NEXT: ] 1612 // CHECK9: .omp.reduction.case1: 1613 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 1614 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR1]], align 4 1615 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 1616 // CHECK9-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 1617 // CHECK9-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 1618 // CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1619 // CHECK9: .omp.reduction.case2: 1620 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR1]], align 4 1621 // CHECK9-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 1622 // CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1623 // CHECK9: .omp.reduction.default: 1624 // CHECK9-NEXT: ret void 1625 // 1626 // 1627 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined.omp_outlined 1628 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { 1629 // CHECK9-NEXT: entry: 1630 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1631 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1632 // CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1633 // CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1634 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 1635 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1636 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1637 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1638 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1639 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1640 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1641 // CHECK9-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 1642 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1643 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1644 // CHECK9-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 1645 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1646 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1647 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1648 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1649 // CHECK9-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 1650 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 1651 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1652 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1653 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1654 // CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 1655 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1656 // CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 1657 // CHECK9-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1658 // CHECK9-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 1659 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1660 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1661 // CHECK9-NEXT: store i32 0, ptr [[SIVAR2]], align 4 1662 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1663 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 1664 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1665 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1666 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 1667 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1668 // CHECK9: cond.true: 1669 // CHECK9-NEXT: br label [[COND_END:%.*]] 1670 // CHECK9: cond.false: 1671 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1672 // CHECK9-NEXT: br label [[COND_END]] 1673 // CHECK9: cond.end: 1674 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 1675 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1676 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1677 // CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 1678 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1679 // CHECK9: omp.inner.for.cond: 1680 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]] 1681 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]] 1682 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 1683 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1684 // CHECK9: omp.inner.for.body: 1685 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 1686 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 1687 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1688 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 1689 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 1690 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR2]], align 4, !llvm.access.group [[ACC_GRP8]] 1691 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 1692 // CHECK9-NEXT: store i32 [[ADD4]], ptr [[SIVAR2]], align 4, !llvm.access.group [[ACC_GRP8]] 1693 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 1694 // CHECK9-NEXT: store ptr [[SIVAR2]], ptr [[TMP13]], align 8, !llvm.access.group [[ACC_GRP8]] 1695 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group [[ACC_GRP8]] 1696 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1697 // CHECK9: omp.body.continue: 1698 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1699 // CHECK9: omp.inner.for.inc: 1700 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 1701 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 1702 // CHECK9-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 1703 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 1704 // CHECK9: omp.inner.for.end: 1705 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1706 // CHECK9: omp.loop.exit: 1707 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) 1708 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1709 // CHECK9-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 1710 // CHECK9-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1711 // CHECK9: .omp.final.then: 1712 // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 1713 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 1714 // CHECK9: .omp.final.done: 1715 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 1716 // CHECK9-NEXT: store ptr [[SIVAR2]], ptr [[TMP17]], align 8 1717 // CHECK9-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 1718 // CHECK9-NEXT: switch i32 [[TMP18]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1719 // CHECK9-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1720 // CHECK9-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1721 // CHECK9-NEXT: ] 1722 // CHECK9: .omp.reduction.case1: 1723 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP0]], align 4 1724 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR2]], align 4 1725 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] 1726 // CHECK9-NEXT: store i32 [[ADD6]], ptr [[TMP0]], align 4 1727 // CHECK9-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) 1728 // CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1729 // CHECK9: .omp.reduction.case2: 1730 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[SIVAR2]], align 4 1731 // CHECK9-NEXT: [[TMP22:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP21]] monotonic, align 4 1732 // CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1733 // CHECK9: .omp.reduction.default: 1734 // CHECK9-NEXT: ret void 1735 // 1736 // 1737 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined.omp_outlined.omp.reduction.reduction_func 1738 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { 1739 // CHECK9-NEXT: entry: 1740 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1741 // CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 1742 // CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1743 // CHECK9-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 1744 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1745 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 1746 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 1747 // CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 1748 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 1749 // CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 1750 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1751 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 1752 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 1753 // CHECK9-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 1754 // CHECK9-NEXT: ret void 1755 // 1756 // 1757 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined.omp.reduction.reduction_func 1758 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR4]] { 1759 // CHECK9-NEXT: entry: 1760 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1761 // CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 1762 // CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1763 // CHECK9-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 1764 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1765 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 1766 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 1767 // CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 1768 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 1769 // CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 1770 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1771 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 1772 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 1773 // CHECK9-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 1774 // CHECK9-NEXT: ret void 1775 // 1776 // 1777 // CHECK11-LABEL: define {{[^@]+}}@main 1778 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 1779 // CHECK11-NEXT: entry: 1780 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1781 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1782 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 1783 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 1784 // CHECK11-NEXT: ret i32 0 1785 // 1786