xref: /llvm-project/clang/test/OpenMP/teams_distribute_parallel_for_simd_proc_bind_codegen.cpp (revision 94473f4db6a6f5f12d7c4081455b5b596094eac5) 
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // add -fopenmp-targets
3 
4 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
6 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
7 
8 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
9 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
10 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
11 // expected-no-diagnostics
12 #ifndef HEADER
13 #define HEADER
14 
15 typedef __INTPTR_TYPE__ intptr_t;
16 
17 
18 void foo();
19 
20 struct S {
21   intptr_t a, b, c;
22   S(intptr_t a) : a(a) {}
23   operator char() { return a; }
24   ~S() {}
25 };
26 
27 template <typename T>
28 T tmain() {
29 #pragma omp target
30 #pragma omp teams distribute parallel for simd proc_bind(master)
31   for(int i = 0; i < 1000; i++) {}
32   return T();
33 }
34 
35 int main() {
36 #pragma omp target
37 #pragma omp teams distribute parallel for simd proc_bind(spread)
38   for(int i = 0; i < 1000; i++) {}
39 #pragma omp target
40 #pragma omp teams distribute parallel for simd proc_bind(close)
41   for(int i = 0; i < 1000; i++) {}
42   return tmain<int>();
43 }
44 
45 
46 
47 
48 
49 
50 
51 
52 
53 
54 #endif
55 // CHECK1-LABEL: define {{[^@]+}}@main
56 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
57 // CHECK1-NEXT:  entry:
58 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
59 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
60 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
61 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
62 // CHECK1-NEXT:    [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
63 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
64 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
65 // CHECK1-NEXT:    store i32 3, ptr [[TMP0]], align 4
66 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
67 // CHECK1-NEXT:    store i32 0, ptr [[TMP1]], align 4
68 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
69 // CHECK1-NEXT:    store ptr null, ptr [[TMP2]], align 8
70 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
71 // CHECK1-NEXT:    store ptr null, ptr [[TMP3]], align 8
72 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
73 // CHECK1-NEXT:    store ptr null, ptr [[TMP4]], align 8
74 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
75 // CHECK1-NEXT:    store ptr null, ptr [[TMP5]], align 8
76 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
77 // CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8
78 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
79 // CHECK1-NEXT:    store ptr null, ptr [[TMP7]], align 8
80 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
81 // CHECK1-NEXT:    store i64 1000, ptr [[TMP8]], align 8
82 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
83 // CHECK1-NEXT:    store i64 0, ptr [[TMP9]], align 8
84 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
85 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
86 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
87 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
88 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
89 // CHECK1-NEXT:    store i32 0, ptr [[TMP12]], align 4
90 // CHECK1-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l36.region_id, ptr [[KERNEL_ARGS]])
91 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
92 // CHECK1-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
93 // CHECK1:       omp_offload.failed:
94 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l36() #[[ATTR2:[0-9]+]]
95 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
96 // CHECK1:       omp_offload.cont:
97 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0
98 // CHECK1-NEXT:    store i32 3, ptr [[TMP15]], align 4
99 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1
100 // CHECK1-NEXT:    store i32 0, ptr [[TMP16]], align 4
101 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2
102 // CHECK1-NEXT:    store ptr null, ptr [[TMP17]], align 8
103 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3
104 // CHECK1-NEXT:    store ptr null, ptr [[TMP18]], align 8
105 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4
106 // CHECK1-NEXT:    store ptr null, ptr [[TMP19]], align 8
107 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5
108 // CHECK1-NEXT:    store ptr null, ptr [[TMP20]], align 8
109 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6
110 // CHECK1-NEXT:    store ptr null, ptr [[TMP21]], align 8
111 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7
112 // CHECK1-NEXT:    store ptr null, ptr [[TMP22]], align 8
113 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8
114 // CHECK1-NEXT:    store i64 1000, ptr [[TMP23]], align 8
115 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9
116 // CHECK1-NEXT:    store i64 0, ptr [[TMP24]], align 8
117 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10
118 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4
119 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11
120 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
121 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12
122 // CHECK1-NEXT:    store i32 0, ptr [[TMP27]], align 4
123 // CHECK1-NEXT:    [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l39.region_id, ptr [[KERNEL_ARGS2]])
124 // CHECK1-NEXT:    [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
125 // CHECK1-NEXT:    br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
126 // CHECK1:       omp_offload.failed3:
127 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l39() #[[ATTR2]]
128 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT4]]
129 // CHECK1:       omp_offload.cont4:
130 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
131 // CHECK1-NEXT:    ret i32 [[CALL]]
132 //
133 //
134 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l36
135 // CHECK1-SAME: () #[[ATTR1:[0-9]+]] {
136 // CHECK1-NEXT:  entry:
137 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l36.omp_outlined)
138 // CHECK1-NEXT:    ret void
139 //
140 //
141 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l36.omp_outlined
142 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
143 // CHECK1-NEXT:  entry:
144 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
145 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
146 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
147 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
148 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
149 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
150 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
151 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
152 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
153 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
154 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
155 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
156 // CHECK1-NEXT:    store i32 999, ptr [[DOTOMP_COMB_UB]], align 4
157 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
158 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
159 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
160 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
161 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
162 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
163 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 999
164 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
165 // CHECK1:       cond.true:
166 // CHECK1-NEXT:    br label [[COND_END:%.*]]
167 // CHECK1:       cond.false:
168 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
169 // CHECK1-NEXT:    br label [[COND_END]]
170 // CHECK1:       cond.end:
171 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
172 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
173 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
174 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
175 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
176 // CHECK1:       omp.inner.for.cond:
177 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
178 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
179 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
180 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
181 // CHECK1:       omp.inner.for.body:
182 // CHECK1-NEXT:    call void @__kmpc_push_proc_bind(ptr @[[GLOB3]], i32 [[TMP1]], i32 4), !llvm.access.group [[ACC_GRP6]]
183 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP6]]
184 // CHECK1-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
185 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
186 // CHECK1-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
187 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l36.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP6]]
188 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
189 // CHECK1:       omp.inner.for.inc:
190 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
191 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP6]]
192 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
193 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
194 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
195 // CHECK1:       omp.inner.for.end:
196 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
197 // CHECK1:       omp.loop.exit:
198 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
199 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
200 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
201 // CHECK1-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
202 // CHECK1:       .omp.final.then:
203 // CHECK1-NEXT:    store i32 1000, ptr [[I]], align 4
204 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
205 // CHECK1:       .omp.final.done:
206 // CHECK1-NEXT:    ret void
207 //
208 //
209 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l36.omp_outlined.omp_outlined
210 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] {
211 // CHECK1-NEXT:  entry:
212 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
213 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
214 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
215 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
216 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
217 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
218 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
219 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
220 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
221 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
222 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
223 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
224 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
225 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
226 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
227 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
228 // CHECK1-NEXT:    store i32 999, ptr [[DOTOMP_UB]], align 4
229 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
230 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
231 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
232 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
233 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
234 // CHECK1-NEXT:    store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
235 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
236 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
237 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
238 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
239 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
240 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
241 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 999
242 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
243 // CHECK1:       cond.true:
244 // CHECK1-NEXT:    br label [[COND_END:%.*]]
245 // CHECK1:       cond.false:
246 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
247 // CHECK1-NEXT:    br label [[COND_END]]
248 // CHECK1:       cond.end:
249 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
250 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
251 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
252 // CHECK1-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
253 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
254 // CHECK1:       omp.inner.for.cond:
255 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]
256 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]]
257 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
258 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
259 // CHECK1:       omp.inner.for.body:
260 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
261 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
262 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
263 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
264 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
265 // CHECK1:       omp.body.continue:
266 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
267 // CHECK1:       omp.inner.for.inc:
268 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
269 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
270 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
271 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
272 // CHECK1:       omp.inner.for.end:
273 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
274 // CHECK1:       omp.loop.exit:
275 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]])
276 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
277 // CHECK1-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
278 // CHECK1-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
279 // CHECK1:       .omp.final.then:
280 // CHECK1-NEXT:    store i32 1000, ptr [[I]], align 4
281 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
282 // CHECK1:       .omp.final.done:
283 // CHECK1-NEXT:    ret void
284 //
285 //
286 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l39
287 // CHECK1-SAME: () #[[ATTR1]] {
288 // CHECK1-NEXT:  entry:
289 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l39.omp_outlined)
290 // CHECK1-NEXT:    ret void
291 //
292 //
293 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l39.omp_outlined
294 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
295 // CHECK1-NEXT:  entry:
296 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
297 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
298 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
299 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
300 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
301 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
302 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
303 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
304 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
305 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
306 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
307 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
308 // CHECK1-NEXT:    store i32 999, ptr [[DOTOMP_COMB_UB]], align 4
309 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
310 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
311 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
312 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
313 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
314 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
315 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 999
316 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
317 // CHECK1:       cond.true:
318 // CHECK1-NEXT:    br label [[COND_END:%.*]]
319 // CHECK1:       cond.false:
320 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
321 // CHECK1-NEXT:    br label [[COND_END]]
322 // CHECK1:       cond.end:
323 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
324 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
325 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
326 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
327 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
328 // CHECK1:       omp.inner.for.cond:
329 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]]
330 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]]
331 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
332 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
333 // CHECK1:       omp.inner.for.body:
334 // CHECK1-NEXT:    call void @__kmpc_push_proc_bind(ptr @[[GLOB3]], i32 [[TMP1]], i32 3), !llvm.access.group [[ACC_GRP15]]
335 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]]
336 // CHECK1-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
337 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]]
338 // CHECK1-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
339 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l39.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP15]]
340 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
341 // CHECK1:       omp.inner.for.inc:
342 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]
343 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]]
344 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
345 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]
346 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
347 // CHECK1:       omp.inner.for.end:
348 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
349 // CHECK1:       omp.loop.exit:
350 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
351 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
352 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
353 // CHECK1-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
354 // CHECK1:       .omp.final.then:
355 // CHECK1-NEXT:    store i32 1000, ptr [[I]], align 4
356 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
357 // CHECK1:       .omp.final.done:
358 // CHECK1-NEXT:    ret void
359 //
360 //
361 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l39.omp_outlined.omp_outlined
362 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] {
363 // CHECK1-NEXT:  entry:
364 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
365 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
366 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
367 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
368 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
369 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
370 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
371 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
372 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
373 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
374 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
375 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
376 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
377 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
378 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
379 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
380 // CHECK1-NEXT:    store i32 999, ptr [[DOTOMP_UB]], align 4
381 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
382 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
383 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
384 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
385 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
386 // CHECK1-NEXT:    store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
387 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
388 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
389 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
390 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
391 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
392 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
393 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 999
394 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
395 // CHECK1:       cond.true:
396 // CHECK1-NEXT:    br label [[COND_END:%.*]]
397 // CHECK1:       cond.false:
398 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
399 // CHECK1-NEXT:    br label [[COND_END]]
400 // CHECK1:       cond.end:
401 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
402 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
403 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
404 // CHECK1-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
405 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
406 // CHECK1:       omp.inner.for.cond:
407 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]
408 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]
409 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
410 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
411 // CHECK1:       omp.inner.for.body:
412 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
413 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
414 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
415 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
416 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
417 // CHECK1:       omp.body.continue:
418 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
419 // CHECK1:       omp.inner.for.inc:
420 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
421 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
422 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
423 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
424 // CHECK1:       omp.inner.for.end:
425 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
426 // CHECK1:       omp.loop.exit:
427 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]])
428 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
429 // CHECK1-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
430 // CHECK1-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
431 // CHECK1:       .omp.final.then:
432 // CHECK1-NEXT:    store i32 1000, ptr [[I]], align 4
433 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
434 // CHECK1:       .omp.final.done:
435 // CHECK1-NEXT:    ret void
436 //
437 //
438 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
439 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] comdat {
440 // CHECK1-NEXT:  entry:
441 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
442 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
443 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
444 // CHECK1-NEXT:    store i32 3, ptr [[TMP0]], align 4
445 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
446 // CHECK1-NEXT:    store i32 0, ptr [[TMP1]], align 4
447 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
448 // CHECK1-NEXT:    store ptr null, ptr [[TMP2]], align 8
449 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
450 // CHECK1-NEXT:    store ptr null, ptr [[TMP3]], align 8
451 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
452 // CHECK1-NEXT:    store ptr null, ptr [[TMP4]], align 8
453 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
454 // CHECK1-NEXT:    store ptr null, ptr [[TMP5]], align 8
455 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
456 // CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8
457 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
458 // CHECK1-NEXT:    store ptr null, ptr [[TMP7]], align 8
459 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
460 // CHECK1-NEXT:    store i64 1000, ptr [[TMP8]], align 8
461 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
462 // CHECK1-NEXT:    store i64 0, ptr [[TMP9]], align 8
463 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
464 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
465 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
466 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
467 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
468 // CHECK1-NEXT:    store i32 0, ptr [[TMP12]], align 4
469 // CHECK1-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29.region_id, ptr [[KERNEL_ARGS]])
470 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
471 // CHECK1-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
472 // CHECK1:       omp_offload.failed:
473 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29() #[[ATTR2]]
474 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
475 // CHECK1:       omp_offload.cont:
476 // CHECK1-NEXT:    ret i32 0
477 //
478 //
479 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29
480 // CHECK1-SAME: () #[[ATTR1]] {
481 // CHECK1-NEXT:  entry:
482 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29.omp_outlined)
483 // CHECK1-NEXT:    ret void
484 //
485 //
486 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29.omp_outlined
487 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
488 // CHECK1-NEXT:  entry:
489 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
490 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
491 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
492 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
493 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
494 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
495 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
496 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
497 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
498 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
499 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
500 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
501 // CHECK1-NEXT:    store i32 999, ptr [[DOTOMP_COMB_UB]], align 4
502 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
503 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
504 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
505 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
506 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
507 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
508 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 999
509 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
510 // CHECK1:       cond.true:
511 // CHECK1-NEXT:    br label [[COND_END:%.*]]
512 // CHECK1:       cond.false:
513 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
514 // CHECK1-NEXT:    br label [[COND_END]]
515 // CHECK1:       cond.end:
516 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
517 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
518 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
519 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
520 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
521 // CHECK1:       omp.inner.for.cond:
522 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]]
523 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP21]]
524 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
525 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
526 // CHECK1:       omp.inner.for.body:
527 // CHECK1-NEXT:    call void @__kmpc_push_proc_bind(ptr @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group [[ACC_GRP21]]
528 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP21]]
529 // CHECK1-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
530 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP21]]
531 // CHECK1-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
532 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP21]]
533 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
534 // CHECK1:       omp.inner.for.inc:
535 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
536 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP21]]
537 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
538 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
539 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
540 // CHECK1:       omp.inner.for.end:
541 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
542 // CHECK1:       omp.loop.exit:
543 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
544 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
545 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
546 // CHECK1-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
547 // CHECK1:       .omp.final.then:
548 // CHECK1-NEXT:    store i32 1000, ptr [[I]], align 4
549 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
550 // CHECK1:       .omp.final.done:
551 // CHECK1-NEXT:    ret void
552 //
553 //
554 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29.omp_outlined.omp_outlined
555 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] {
556 // CHECK1-NEXT:  entry:
557 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
558 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
559 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
560 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
561 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
562 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
563 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
564 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
565 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
566 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
567 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
568 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
569 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
570 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
571 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
572 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
573 // CHECK1-NEXT:    store i32 999, ptr [[DOTOMP_UB]], align 4
574 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
575 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
576 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
577 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
578 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
579 // CHECK1-NEXT:    store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
580 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
581 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
582 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
583 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
584 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
585 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
586 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 999
587 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
588 // CHECK1:       cond.true:
589 // CHECK1-NEXT:    br label [[COND_END:%.*]]
590 // CHECK1:       cond.false:
591 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
592 // CHECK1-NEXT:    br label [[COND_END]]
593 // CHECK1:       cond.end:
594 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
595 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
596 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
597 // CHECK1-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
598 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
599 // CHECK1:       omp.inner.for.cond:
600 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]]
601 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]]
602 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
603 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
604 // CHECK1:       omp.inner.for.body:
605 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
606 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
607 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
608 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]]
609 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
610 // CHECK1:       omp.body.continue:
611 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
612 // CHECK1:       omp.inner.for.inc:
613 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
614 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
615 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
616 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
617 // CHECK1:       omp.inner.for.end:
618 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
619 // CHECK1:       omp.loop.exit:
620 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]])
621 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
622 // CHECK1-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
623 // CHECK1-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
624 // CHECK1:       .omp.final.then:
625 // CHECK1-NEXT:    store i32 1000, ptr [[I]], align 4
626 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
627 // CHECK1:       .omp.final.done:
628 // CHECK1-NEXT:    ret void
629 //
630 //
631 // CHECK3-LABEL: define {{[^@]+}}@main
632 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
633 // CHECK3-NEXT:  entry:
634 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
635 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
636 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
637 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
638 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
639 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
640 // CHECK3-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
641 // CHECK3-NEXT:    [[DOTOMP_LB3:%.*]] = alloca i32, align 4
642 // CHECK3-NEXT:    [[DOTOMP_UB4:%.*]] = alloca i32, align 4
643 // CHECK3-NEXT:    [[DOTOMP_IV5:%.*]] = alloca i32, align 4
644 // CHECK3-NEXT:    [[I6:%.*]] = alloca i32, align 4
645 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
646 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
647 // CHECK3-NEXT:    store i32 999, ptr [[DOTOMP_UB]], align 4
648 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
649 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
650 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
651 // CHECK3:       omp.inner.for.cond:
652 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
653 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]
654 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
655 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
656 // CHECK3:       omp.inner.for.body:
657 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
658 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
659 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
660 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
661 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
662 // CHECK3:       omp.body.continue:
663 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
664 // CHECK3:       omp.inner.for.inc:
665 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
666 // CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
667 // CHECK3-NEXT:    store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
668 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
669 // CHECK3:       omp.inner.for.end:
670 // CHECK3-NEXT:    store i32 1000, ptr [[I]], align 4
671 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB3]], align 4
672 // CHECK3-NEXT:    store i32 999, ptr [[DOTOMP_UB4]], align 4
673 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB3]], align 4
674 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV5]], align 4
675 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND7:%.*]]
676 // CHECK3:       omp.inner.for.cond7:
677 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
678 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB4]], align 4, !llvm.access.group [[ACC_GRP6]]
679 // CHECK3-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
680 // CHECK3-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]]
681 // CHECK3:       omp.inner.for.body9:
682 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP6]]
683 // CHECK3-NEXT:    [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1
684 // CHECK3-NEXT:    [[ADD11:%.*]] = add nsw i32 0, [[MUL10]]
685 // CHECK3-NEXT:    store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP6]]
686 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE12:%.*]]
687 // CHECK3:       omp.body.continue12:
688 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC13:%.*]]
689 // CHECK3:       omp.inner.for.inc13:
690 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP6]]
691 // CHECK3-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1
692 // CHECK3-NEXT:    store i32 [[ADD14]], ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP6]]
693 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP7:![0-9]+]]
694 // CHECK3:       omp.inner.for.end15:
695 // CHECK3-NEXT:    store i32 1000, ptr [[I6]], align 4
696 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
697 // CHECK3-NEXT:    ret i32 [[CALL]]
698 //
699 //
700 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
701 // CHECK3-SAME: () #[[ATTR1:[0-9]+]] comdat {
702 // CHECK3-NEXT:  entry:
703 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
704 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
705 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
706 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
707 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
708 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
709 // CHECK3-NEXT:    store i32 999, ptr [[DOTOMP_UB]], align 4
710 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
711 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
712 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
713 // CHECK3:       omp.inner.for.cond:
714 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]
715 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]
716 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
717 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
718 // CHECK3:       omp.inner.for.body:
719 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
720 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
721 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
722 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
723 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
724 // CHECK3:       omp.body.continue:
725 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
726 // CHECK3:       omp.inner.for.inc:
727 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
728 // CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
729 // CHECK3-NEXT:    store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
730 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
731 // CHECK3:       omp.inner.for.end:
732 // CHECK3-NEXT:    store i32 1000, ptr [[I]], align 4
733 // CHECK3-NEXT:    ret i32 0
734 //
735