1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target 57 #pragma omp teams distribute parallel for simd private(t_var, vec, s_arr, var) 58 for (int i = 0; i < 2; ++i) { 59 vec[i] = t_var; 60 s_arr[i] = var; 61 } 62 return T(); 63 } 64 65 S<float> test; 66 int t_var = 333; 67 int vec[] = {1, 2}; 68 S<float> s_arr[] = {1, 2}; 69 S<float> var(3); 70 71 int main() { 72 static int sivar; 73 #ifdef LAMBDA 74 [&]() { 75 #pragma omp target 76 #pragma omp teams distribute parallel for simd private(g, g1, sivar) 77 for (int i = 0; i < 2; ++i) { 78 79 // Skip global, bound tid and loop vars 80 81 g = 1; 82 g1 = 1; 83 sivar = 2; 84 85 // Skip global, bound tid and loop vars 86 [&]() { 87 g = 2; 88 g1 = 2; 89 sivar = 4; 90 91 }(); 92 } 93 }(); 94 return 0; 95 96 97 #else 98 #pragma omp target 99 #pragma omp teams distribute parallel for simd private(t_var, vec, s_arr, var, sivar) 100 for (int i = 0; i < 2; ++i) { 101 vec[i] = t_var; 102 s_arr[i] = var; 103 sivar += i; 104 } 105 return tmain<int>(); 106 #endif 107 } 108 109 110 111 // Skip global, bound tid and loop vars 112 113 // private(s_arr) 114 115 // private(var) 116 117 118 // Skip global, bound tid and loop vars 119 120 // private(s_arr) 121 122 // private(var) 123 124 125 126 127 // Skip global, bound tid and loop vars 128 129 // private(s_arr) 130 131 132 // private(var) 133 134 135 // Skip global, bound tid and loop vars 136 // prev lb and ub 137 // iter variables 138 139 // private(s_arr) 140 141 142 // private(var) 143 144 145 146 #endif 147 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 148 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 149 // CHECK1-NEXT: entry: 150 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 151 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 152 // CHECK1-NEXT: ret void 153 // 154 // 155 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 156 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 157 // CHECK1-NEXT: entry: 158 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 159 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 160 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 161 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 162 // CHECK1-NEXT: ret void 163 // 164 // 165 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 166 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 167 // CHECK1-NEXT: entry: 168 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 169 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 170 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 171 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 172 // CHECK1-NEXT: ret void 173 // 174 // 175 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 176 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 177 // CHECK1-NEXT: entry: 178 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 179 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 180 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 181 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 182 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 183 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 184 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 185 // CHECK1-NEXT: ret void 186 // 187 // 188 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 189 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 190 // CHECK1-NEXT: entry: 191 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 192 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 193 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 194 // CHECK1-NEXT: ret void 195 // 196 // 197 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 198 // CHECK1-SAME: () #[[ATTR0]] { 199 // CHECK1-NEXT: entry: 200 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 201 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 202 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 203 // CHECK1-NEXT: ret void 204 // 205 // 206 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 207 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 208 // CHECK1-NEXT: entry: 209 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 210 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 211 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 212 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 213 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 214 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 215 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 216 // CHECK1-NEXT: ret void 217 // 218 // 219 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 220 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 221 // CHECK1-NEXT: entry: 222 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 223 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 224 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 225 // CHECK1: arraydestroy.body: 226 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 227 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 228 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 229 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 230 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 231 // CHECK1: arraydestroy.done1: 232 // CHECK1-NEXT: ret void 233 // 234 // 235 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 236 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 237 // CHECK1-NEXT: entry: 238 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 239 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 240 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 241 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 242 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 243 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 244 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 245 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 246 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 247 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 248 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 249 // CHECK1-NEXT: ret void 250 // 251 // 252 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 253 // CHECK1-SAME: () #[[ATTR0]] { 254 // CHECK1-NEXT: entry: 255 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 256 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 257 // CHECK1-NEXT: ret void 258 // 259 // 260 // CHECK1-LABEL: define {{[^@]+}}@main 261 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 262 // CHECK1-NEXT: entry: 263 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 264 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 265 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 266 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 267 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 268 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 269 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 270 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 271 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 272 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 273 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 274 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 275 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 276 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 277 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 278 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 279 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 280 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 281 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 282 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 283 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 284 // CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8 285 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 286 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 287 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 288 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 289 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 290 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 291 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 292 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 293 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, ptr [[KERNEL_ARGS]]) 294 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 295 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 296 // CHECK1: omp_offload.failed: 297 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98() #[[ATTR2]] 298 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 299 // CHECK1: omp_offload.cont: 300 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 301 // CHECK1-NEXT: ret i32 [[CALL]] 302 // 303 // 304 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 305 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 306 // CHECK1-NEXT: entry: 307 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined) 308 // CHECK1-NEXT: ret void 309 // 310 // 311 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined 312 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 313 // CHECK1-NEXT: entry: 314 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 315 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 316 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 317 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 318 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 319 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 320 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 321 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 322 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 323 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 324 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 325 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 326 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 327 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 328 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 329 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 330 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 331 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 332 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 333 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 334 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 335 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 336 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 337 // CHECK1: arrayctor.loop: 338 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 339 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 340 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 341 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 342 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 343 // CHECK1: arrayctor.cont: 344 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 345 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 346 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 347 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 348 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 349 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 350 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 351 // CHECK1: cond.true: 352 // CHECK1-NEXT: br label [[COND_END:%.*]] 353 // CHECK1: cond.false: 354 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 355 // CHECK1-NEXT: br label [[COND_END]] 356 // CHECK1: cond.end: 357 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 358 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 359 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 360 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 361 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 362 // CHECK1: omp.inner.for.cond: 363 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] 364 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 365 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 366 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 367 // CHECK1: omp.inner.for.cond.cleanup: 368 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 369 // CHECK1: omp.inner.for.body: 370 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP5]] 371 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 372 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 373 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 374 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP5]] 375 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 376 // CHECK1: omp.inner.for.inc: 377 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 378 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP5]] 379 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 380 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 381 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 382 // CHECK1: omp.inner.for.end: 383 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 384 // CHECK1: omp.loop.exit: 385 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 386 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 387 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 388 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 389 // CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 390 // CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 391 // CHECK1: .omp.final.then: 392 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 393 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 394 // CHECK1: .omp.final.done: 395 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 396 // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 397 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2 398 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 399 // CHECK1: arraydestroy.body: 400 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 401 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 402 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 403 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 404 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 405 // CHECK1: arraydestroy.done3: 406 // CHECK1-NEXT: ret void 407 // 408 // 409 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined.omp_outlined 410 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 411 // CHECK1-NEXT: entry: 412 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 413 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 414 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 415 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 416 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 417 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 418 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 419 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 420 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 421 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 422 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 423 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 424 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 425 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 426 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 427 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 428 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 429 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 430 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 431 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 432 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 433 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 434 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 435 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 436 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 437 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 438 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 439 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 440 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 441 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 442 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 443 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 444 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 445 // CHECK1: arrayctor.loop: 446 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 447 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 448 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 449 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 450 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 451 // CHECK1: arrayctor.cont: 452 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 453 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 454 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 455 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 456 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 457 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 458 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 459 // CHECK1: cond.true: 460 // CHECK1-NEXT: br label [[COND_END:%.*]] 461 // CHECK1: cond.false: 462 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 463 // CHECK1-NEXT: br label [[COND_END]] 464 // CHECK1: cond.end: 465 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 466 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 467 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 468 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 469 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 470 // CHECK1: omp.inner.for.cond: 471 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] 472 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 473 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 474 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 475 // CHECK1: omp.inner.for.cond.cleanup: 476 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 477 // CHECK1: omp.inner.for.body: 478 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 479 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 480 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 481 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 482 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP9]] 483 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 484 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 485 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 486 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] 487 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 488 // CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 489 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] 490 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] 491 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 492 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP9]] 493 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 494 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP9]] 495 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 496 // CHECK1: omp.body.continue: 497 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 498 // CHECK1: omp.inner.for.inc: 499 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 500 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP15]], 1 501 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 502 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 503 // CHECK1: omp.inner.for.end: 504 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 505 // CHECK1: omp.loop.exit: 506 // CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 507 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 508 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) 509 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 510 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 511 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 512 // CHECK1: .omp.final.then: 513 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 514 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 515 // CHECK1: .omp.final.done: 516 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 517 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 518 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 519 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 520 // CHECK1: arraydestroy.body: 521 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 522 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 523 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 524 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 525 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 526 // CHECK1: arraydestroy.done8: 527 // CHECK1-NEXT: ret void 528 // 529 // 530 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 531 // CHECK1-SAME: () #[[ATTR1]] comdat { 532 // CHECK1-NEXT: entry: 533 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 534 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 535 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 536 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 537 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 538 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 539 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 540 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 541 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 542 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 543 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 544 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 545 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 546 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 547 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 548 // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 549 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 550 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 551 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 552 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 553 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 554 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 555 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 556 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 557 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 558 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 559 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 560 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 561 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 562 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 563 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 564 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 565 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 566 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 567 // CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8 568 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 569 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 570 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 571 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 572 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 573 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 574 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 575 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 576 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 577 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 578 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 579 // CHECK1: omp_offload.failed: 580 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 581 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 582 // CHECK1: omp_offload.cont: 583 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 584 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 585 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 586 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 587 // CHECK1: arraydestroy.body: 588 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 589 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 590 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 591 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 592 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 593 // CHECK1: arraydestroy.done2: 594 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 595 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 596 // CHECK1-NEXT: ret i32 [[TMP16]] 597 // 598 // 599 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 600 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 601 // CHECK1-NEXT: entry: 602 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 603 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 604 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 605 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 606 // CHECK1-NEXT: ret void 607 // 608 // 609 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 610 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 611 // CHECK1-NEXT: entry: 612 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 613 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 614 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 615 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 616 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 617 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 618 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 619 // CHECK1-NEXT: ret void 620 // 621 // 622 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 623 // CHECK1-SAME: () #[[ATTR4]] { 624 // CHECK1-NEXT: entry: 625 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined) 626 // CHECK1-NEXT: ret void 627 // 628 // 629 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 630 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 631 // CHECK1-NEXT: entry: 632 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 633 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 634 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 635 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 636 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 637 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 638 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 639 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 640 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 641 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 642 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 643 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 644 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 645 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 646 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 647 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 648 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 649 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 650 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 651 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 652 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 653 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 654 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 655 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 656 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 657 // CHECK1: arrayctor.loop: 658 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 659 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 660 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 661 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 662 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 663 // CHECK1: arrayctor.cont: 664 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 665 // CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 8 666 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 667 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 668 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 669 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 670 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 671 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 672 // CHECK1: cond.true: 673 // CHECK1-NEXT: br label [[COND_END:%.*]] 674 // CHECK1: cond.false: 675 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 676 // CHECK1-NEXT: br label [[COND_END]] 677 // CHECK1: cond.end: 678 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 679 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 680 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 681 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 682 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 683 // CHECK1: omp.inner.for.cond: 684 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]] 685 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]] 686 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 687 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 688 // CHECK1: omp.inner.for.cond.cleanup: 689 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 690 // CHECK1: omp.inner.for.body: 691 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP14]] 692 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 693 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]] 694 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 695 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP14]] 696 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 697 // CHECK1: omp.inner.for.inc: 698 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 699 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP14]] 700 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 701 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 702 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 703 // CHECK1: omp.inner.for.end: 704 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 705 // CHECK1: omp.loop.exit: 706 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 707 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 708 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 709 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 710 // CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 711 // CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 712 // CHECK1: .omp.final.then: 713 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 714 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 715 // CHECK1: .omp.final.done: 716 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 717 // CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 718 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2 719 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 720 // CHECK1: arraydestroy.body: 721 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 722 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 723 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 724 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 725 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 726 // CHECK1: arraydestroy.done5: 727 // CHECK1-NEXT: ret void 728 // 729 // 730 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined 731 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 732 // CHECK1-NEXT: entry: 733 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 734 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 735 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 736 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 737 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 738 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 739 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 740 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 741 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 742 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 743 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 744 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 745 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 746 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 747 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 748 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 749 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 750 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 751 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 752 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 753 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 754 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 755 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 756 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 757 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 758 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 759 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 760 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 761 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 762 // CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 763 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 764 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 765 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 766 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 767 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 768 // CHECK1: arrayctor.loop: 769 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 770 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 771 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 772 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 773 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 774 // CHECK1: arrayctor.cont: 775 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 776 // CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP3]], align 8 777 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 778 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 779 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 780 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 781 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 782 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 783 // CHECK1: cond.true: 784 // CHECK1-NEXT: br label [[COND_END:%.*]] 785 // CHECK1: cond.false: 786 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 787 // CHECK1-NEXT: br label [[COND_END]] 788 // CHECK1: cond.end: 789 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 790 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 791 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 792 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 793 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 794 // CHECK1: omp.inner.for.cond: 795 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]] 796 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP17]] 797 // CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 798 // CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 799 // CHECK1: omp.inner.for.cond.cleanup: 800 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 801 // CHECK1: omp.inner.for.body: 802 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 803 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 804 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 805 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 806 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP17]] 807 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 808 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 809 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 810 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]] 811 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !llvm.access.group [[ACC_GRP17]] 812 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 813 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 814 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] 815 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group [[ACC_GRP17]] 816 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 817 // CHECK1: omp.body.continue: 818 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 819 // CHECK1: omp.inner.for.inc: 820 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 821 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP14]], 1 822 // CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 823 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 824 // CHECK1: omp.inner.for.end: 825 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 826 // CHECK1: omp.loop.exit: 827 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 828 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 829 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) 830 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 831 // CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 832 // CHECK1-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 833 // CHECK1: .omp.final.then: 834 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 835 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 836 // CHECK1: .omp.final.done: 837 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 838 // CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 839 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 840 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 841 // CHECK1: arraydestroy.body: 842 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 843 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 844 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 845 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 846 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 847 // CHECK1: arraydestroy.done9: 848 // CHECK1-NEXT: ret void 849 // 850 // 851 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 852 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 853 // CHECK1-NEXT: entry: 854 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 855 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 856 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 857 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 858 // CHECK1-NEXT: ret void 859 // 860 // 861 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 862 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 863 // CHECK1-NEXT: entry: 864 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 865 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 866 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 867 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 868 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 869 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 870 // CHECK1-NEXT: ret void 871 // 872 // 873 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 874 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 875 // CHECK1-NEXT: entry: 876 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 877 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 878 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 879 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 880 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 881 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 882 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 883 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 884 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 885 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 886 // CHECK1-NEXT: ret void 887 // 888 // 889 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 890 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 891 // CHECK1-NEXT: entry: 892 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 893 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 894 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 895 // CHECK1-NEXT: ret void 896 // 897 // 898 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp 899 // CHECK1-SAME: () #[[ATTR0]] { 900 // CHECK1-NEXT: entry: 901 // CHECK1-NEXT: call void @__cxx_global_var_init() 902 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 903 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 904 // CHECK1-NEXT: ret void 905 // 906 // 907 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 908 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 909 // CHECK3-NEXT: entry: 910 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 911 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 912 // CHECK3-NEXT: ret void 913 // 914 // 915 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 916 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 917 // CHECK3-NEXT: entry: 918 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 919 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 920 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 921 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 922 // CHECK3-NEXT: ret void 923 // 924 // 925 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 926 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 927 // CHECK3-NEXT: entry: 928 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 929 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 930 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 931 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 932 // CHECK3-NEXT: ret void 933 // 934 // 935 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 936 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 937 // CHECK3-NEXT: entry: 938 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 939 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 940 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 941 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 942 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 943 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 944 // CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4 945 // CHECK3-NEXT: ret void 946 // 947 // 948 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 949 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 950 // CHECK3-NEXT: entry: 951 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 952 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 953 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 954 // CHECK3-NEXT: ret void 955 // 956 // 957 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 958 // CHECK3-SAME: () #[[ATTR0]] { 959 // CHECK3-NEXT: entry: 960 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 961 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 962 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 963 // CHECK3-NEXT: ret void 964 // 965 // 966 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 967 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 968 // CHECK3-NEXT: entry: 969 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 970 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 971 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 972 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 973 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 974 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 975 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 976 // CHECK3-NEXT: ret void 977 // 978 // 979 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 980 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 981 // CHECK3-NEXT: entry: 982 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 983 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 984 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 985 // CHECK3: arraydestroy.body: 986 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 987 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 988 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 989 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 990 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 991 // CHECK3: arraydestroy.done1: 992 // CHECK3-NEXT: ret void 993 // 994 // 995 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 996 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 997 // CHECK3-NEXT: entry: 998 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 999 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1000 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1001 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1002 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1003 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1004 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1005 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1006 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1007 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1008 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 1009 // CHECK3-NEXT: ret void 1010 // 1011 // 1012 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1013 // CHECK3-SAME: () #[[ATTR0]] { 1014 // CHECK3-NEXT: entry: 1015 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1016 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1017 // CHECK3-NEXT: ret void 1018 // 1019 // 1020 // CHECK3-LABEL: define {{[^@]+}}@main 1021 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1022 // CHECK3-NEXT: entry: 1023 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1024 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1025 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1026 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1027 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1028 // CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4 1029 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1030 // CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4 1031 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1032 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 1033 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1034 // CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4 1035 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1036 // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 1037 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1038 // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 1039 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1040 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1041 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1042 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 1043 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1044 // CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8 1045 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1046 // CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8 1047 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1048 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 1049 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1050 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 1051 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1052 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 1053 // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, ptr [[KERNEL_ARGS]]) 1054 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1055 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1056 // CHECK3: omp_offload.failed: 1057 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98() #[[ATTR2]] 1058 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1059 // CHECK3: omp_offload.cont: 1060 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1061 // CHECK3-NEXT: ret i32 [[CALL]] 1062 // 1063 // 1064 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 1065 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 1066 // CHECK3-NEXT: entry: 1067 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined) 1068 // CHECK3-NEXT: ret void 1069 // 1070 // 1071 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined 1072 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1073 // CHECK3-NEXT: entry: 1074 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1075 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1076 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1077 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1078 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1079 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1080 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1081 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1082 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1083 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1084 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1085 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1086 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1087 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1088 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1089 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1090 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1091 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1092 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1093 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1094 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1095 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1096 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1097 // CHECK3: arrayctor.loop: 1098 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1099 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1100 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 1101 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1102 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1103 // CHECK3: arrayctor.cont: 1104 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1105 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1106 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1107 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1108 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1109 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1110 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1111 // CHECK3: cond.true: 1112 // CHECK3-NEXT: br label [[COND_END:%.*]] 1113 // CHECK3: cond.false: 1114 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1115 // CHECK3-NEXT: br label [[COND_END]] 1116 // CHECK3: cond.end: 1117 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1118 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1119 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1120 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1121 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1122 // CHECK3: omp.inner.for.cond: 1123 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 1124 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 1125 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1126 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1127 // CHECK3: omp.inner.for.cond.cleanup: 1128 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1129 // CHECK3: omp.inner.for.body: 1130 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP6]] 1131 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 1132 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP6]] 1133 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1134 // CHECK3: omp.inner.for.inc: 1135 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1136 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP6]] 1137 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] 1138 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1139 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1140 // CHECK3: omp.inner.for.end: 1141 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1142 // CHECK3: omp.loop.exit: 1143 // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1144 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 1145 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) 1146 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1147 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1148 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1149 // CHECK3: .omp.final.then: 1150 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 1151 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1152 // CHECK3: .omp.final.done: 1153 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1154 // CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1155 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i32 2 1156 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1157 // CHECK3: arraydestroy.body: 1158 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1159 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1160 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1161 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 1162 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 1163 // CHECK3: arraydestroy.done3: 1164 // CHECK3-NEXT: ret void 1165 // 1166 // 1167 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined.omp_outlined 1168 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 1169 // CHECK3-NEXT: entry: 1170 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1171 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1172 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 1173 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 1174 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1175 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1176 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1177 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1178 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1179 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1180 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1181 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1182 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1183 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1184 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1185 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1186 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1187 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1188 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1189 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1190 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1191 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1192 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1193 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1194 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4 1195 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 1196 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1197 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1198 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1199 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1200 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1201 // CHECK3: arrayctor.loop: 1202 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1203 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1204 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 1205 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1206 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1207 // CHECK3: arrayctor.cont: 1208 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1209 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1210 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1211 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1212 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1213 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 1214 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1215 // CHECK3: cond.true: 1216 // CHECK3-NEXT: br label [[COND_END:%.*]] 1217 // CHECK3: cond.false: 1218 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1219 // CHECK3-NEXT: br label [[COND_END]] 1220 // CHECK3: cond.end: 1221 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1222 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1223 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1224 // CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1225 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1226 // CHECK3: omp.inner.for.cond: 1227 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 1228 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 1229 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1230 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1231 // CHECK3: omp.inner.for.cond.cleanup: 1232 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1233 // CHECK3: omp.inner.for.body: 1234 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 1235 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1236 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1237 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 1238 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP10]] 1239 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 1240 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] 1241 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] 1242 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 1243 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]] 1244 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] 1245 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 1246 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP10]] 1247 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 1248 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP10]] 1249 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1250 // CHECK3: omp.body.continue: 1251 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1252 // CHECK3: omp.inner.for.inc: 1253 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 1254 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 1255 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 1256 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 1257 // CHECK3: omp.inner.for.end: 1258 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1259 // CHECK3: omp.loop.exit: 1260 // CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1261 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 1262 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) 1263 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1264 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 1265 // CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1266 // CHECK3: .omp.final.then: 1267 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 1268 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1269 // CHECK3: .omp.final.done: 1270 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1271 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1272 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 1273 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1274 // CHECK3: arraydestroy.body: 1275 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1276 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1277 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1278 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 1279 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 1280 // CHECK3: arraydestroy.done6: 1281 // CHECK3-NEXT: ret void 1282 // 1283 // 1284 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1285 // CHECK3-SAME: () #[[ATTR1]] comdat { 1286 // CHECK3-NEXT: entry: 1287 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1288 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1289 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1290 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1291 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1292 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 1293 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1294 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 1295 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1296 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1297 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 1298 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 1299 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 1300 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 1301 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1302 // CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 1303 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 1304 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1305 // CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4 1306 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1307 // CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4 1308 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1309 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 1310 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1311 // CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4 1312 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1313 // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 1314 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1315 // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 1316 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1317 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1318 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1319 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 1320 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1321 // CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8 1322 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1323 // CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8 1324 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1325 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 1326 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1327 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 1328 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1329 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 1330 // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 1331 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1332 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1333 // CHECK3: omp_offload.failed: 1334 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 1335 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1336 // CHECK3: omp_offload.cont: 1337 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1338 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1339 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1340 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1341 // CHECK3: arraydestroy.body: 1342 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1343 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1344 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1345 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1346 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1347 // CHECK3: arraydestroy.done2: 1348 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1349 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 1350 // CHECK3-NEXT: ret i32 [[TMP16]] 1351 // 1352 // 1353 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1354 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1355 // CHECK3-NEXT: entry: 1356 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1357 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1358 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1359 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1360 // CHECK3-NEXT: ret void 1361 // 1362 // 1363 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1364 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1365 // CHECK3-NEXT: entry: 1366 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1367 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1368 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1369 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1370 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1371 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1372 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1373 // CHECK3-NEXT: ret void 1374 // 1375 // 1376 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1377 // CHECK3-SAME: () #[[ATTR4]] { 1378 // CHECK3-NEXT: entry: 1379 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined) 1380 // CHECK3-NEXT: ret void 1381 // 1382 // 1383 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 1384 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1385 // CHECK3-NEXT: entry: 1386 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1387 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1388 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1389 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1390 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 1391 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1392 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1393 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1394 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1395 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1396 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1397 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1398 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1399 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 1400 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1401 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1402 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1403 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 1404 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1405 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1406 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1407 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1408 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1409 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1410 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1411 // CHECK3: arrayctor.loop: 1412 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1413 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1414 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 1415 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1416 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1417 // CHECK3: arrayctor.cont: 1418 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1419 // CHECK3-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 4 1420 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1421 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1422 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1423 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1424 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1425 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1426 // CHECK3: cond.true: 1427 // CHECK3-NEXT: br label [[COND_END:%.*]] 1428 // CHECK3: cond.false: 1429 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1430 // CHECK3-NEXT: br label [[COND_END]] 1431 // CHECK3: cond.end: 1432 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1433 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1434 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1435 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1436 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1437 // CHECK3: omp.inner.for.cond: 1438 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] 1439 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 1440 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1441 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1442 // CHECK3: omp.inner.for.cond.cleanup: 1443 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1444 // CHECK3: omp.inner.for.body: 1445 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]] 1446 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 1447 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP15]] 1448 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1449 // CHECK3: omp.inner.for.inc: 1450 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 1451 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]] 1452 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] 1453 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 1454 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 1455 // CHECK3: omp.inner.for.end: 1456 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1457 // CHECK3: omp.loop.exit: 1458 // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1459 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 1460 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) 1461 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1462 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1463 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1464 // CHECK3: .omp.final.then: 1465 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 1466 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1467 // CHECK3: .omp.final.done: 1468 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1469 // CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1470 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2 1471 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1472 // CHECK3: arraydestroy.body: 1473 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1474 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1475 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1476 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 1477 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 1478 // CHECK3: arraydestroy.done5: 1479 // CHECK3-NEXT: ret void 1480 // 1481 // 1482 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined 1483 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 1484 // CHECK3-NEXT: entry: 1485 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1486 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1487 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 1488 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 1489 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1490 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1491 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 1492 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1493 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1494 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1495 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1496 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1497 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1498 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1499 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1500 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 1501 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1502 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1503 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1504 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1505 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1506 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 1507 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1508 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1509 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1510 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1511 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4 1512 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 1513 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1514 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1515 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1516 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1517 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1518 // CHECK3: arrayctor.loop: 1519 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1520 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1521 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 1522 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1523 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1524 // CHECK3: arrayctor.cont: 1525 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1526 // CHECK3-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 4 1527 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1528 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1529 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1530 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1531 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 1532 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1533 // CHECK3: cond.true: 1534 // CHECK3-NEXT: br label [[COND_END:%.*]] 1535 // CHECK3: cond.false: 1536 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1537 // CHECK3-NEXT: br label [[COND_END]] 1538 // CHECK3: cond.end: 1539 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1540 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1541 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1542 // CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1543 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1544 // CHECK3: omp.inner.for.cond: 1545 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] 1546 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] 1547 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1548 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1549 // CHECK3: omp.inner.for.cond.cleanup: 1550 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1551 // CHECK3: omp.inner.for.body: 1552 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 1553 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1554 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1555 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 1556 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP18]] 1557 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 1558 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] 1559 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] 1560 // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP18]] 1561 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 1562 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] 1563 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group [[ACC_GRP18]] 1564 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1565 // CHECK3: omp.body.continue: 1566 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1567 // CHECK3: omp.inner.for.inc: 1568 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 1569 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 1570 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 1571 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 1572 // CHECK3: omp.inner.for.end: 1573 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1574 // CHECK3: omp.loop.exit: 1575 // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1576 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 1577 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) 1578 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1579 // CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 1580 // CHECK3-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1581 // CHECK3: .omp.final.then: 1582 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 1583 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1584 // CHECK3: .omp.final.done: 1585 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1586 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1587 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 1588 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1589 // CHECK3: arraydestroy.body: 1590 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1591 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1592 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1593 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 1594 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1595 // CHECK3: arraydestroy.done7: 1596 // CHECK3-NEXT: ret void 1597 // 1598 // 1599 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1600 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1601 // CHECK3-NEXT: entry: 1602 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1603 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1604 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1605 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1606 // CHECK3-NEXT: ret void 1607 // 1608 // 1609 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1610 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1611 // CHECK3-NEXT: entry: 1612 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1613 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1614 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1615 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1616 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1617 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1618 // CHECK3-NEXT: ret void 1619 // 1620 // 1621 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1622 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1623 // CHECK3-NEXT: entry: 1624 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1625 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1626 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1627 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1628 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1629 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1630 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1631 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1632 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1633 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1634 // CHECK3-NEXT: ret void 1635 // 1636 // 1637 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1638 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1639 // CHECK3-NEXT: entry: 1640 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1641 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1642 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1643 // CHECK3-NEXT: ret void 1644 // 1645 // 1646 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp 1647 // CHECK3-SAME: () #[[ATTR0]] { 1648 // CHECK3-NEXT: entry: 1649 // CHECK3-NEXT: call void @__cxx_global_var_init() 1650 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1651 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1652 // CHECK3-NEXT: ret void 1653 // 1654 // 1655 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 1656 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 1657 // CHECK5-NEXT: entry: 1658 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 1659 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 1660 // CHECK5-NEXT: ret void 1661 // 1662 // 1663 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1664 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 1665 // CHECK5-NEXT: entry: 1666 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1667 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1668 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1669 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1670 // CHECK5-NEXT: ret void 1671 // 1672 // 1673 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1674 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1675 // CHECK5-NEXT: entry: 1676 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1677 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1678 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1679 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1680 // CHECK5-NEXT: ret void 1681 // 1682 // 1683 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1684 // CHECK5-SAME: () #[[ATTR0]] { 1685 // CHECK5-NEXT: entry: 1686 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 1687 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 1688 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 1689 // CHECK5-NEXT: ret void 1690 // 1691 // 1692 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1693 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1694 // CHECK5-NEXT: entry: 1695 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1696 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1697 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1698 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1699 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1700 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1701 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1702 // CHECK5-NEXT: ret void 1703 // 1704 // 1705 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1706 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1707 // CHECK5-NEXT: entry: 1708 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1709 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1710 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1711 // CHECK5: arraydestroy.body: 1712 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1713 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1714 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1715 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1716 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1717 // CHECK5: arraydestroy.done1: 1718 // CHECK5-NEXT: ret void 1719 // 1720 // 1721 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1722 // CHECK5-SAME: () #[[ATTR0]] { 1723 // CHECK5-NEXT: entry: 1724 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1725 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1726 // CHECK5-NEXT: ret void 1727 // 1728 // 1729 // CHECK5-LABEL: define {{[^@]+}}@main 1730 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 1731 // CHECK5-NEXT: entry: 1732 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1733 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1734 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1735 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1736 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1737 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1738 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1739 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1740 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1741 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1742 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1743 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 1744 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1745 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1746 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1747 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 1748 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1749 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 1750 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1751 // CHECK5: arrayctor.loop: 1752 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1753 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1754 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 1755 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1756 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1757 // CHECK5: arrayctor.cont: 1758 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1759 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1760 // CHECK5: omp.inner.for.cond: 1761 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 1762 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 1763 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1764 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1765 // CHECK5: omp.inner.for.cond.cleanup: 1766 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1767 // CHECK5: omp.inner.for.body: 1768 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1769 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1770 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1771 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1772 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]] 1773 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1774 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 1775 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 1776 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] 1777 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1778 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 1779 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM1]] 1780 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] 1781 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1782 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] 1783 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] 1784 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] 1785 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1786 // CHECK5: omp.body.continue: 1787 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1788 // CHECK5: omp.inner.for.inc: 1789 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1790 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 1791 // CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1792 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1793 // CHECK5: omp.inner.for.end: 1794 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 1795 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1796 // CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1797 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i64 2 1798 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1799 // CHECK5: arraydestroy.body: 1800 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1801 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1802 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1803 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 1804 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 1805 // CHECK5: arraydestroy.done6: 1806 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 1807 // CHECK5-NEXT: ret i32 [[CALL]] 1808 // 1809 // 1810 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1811 // CHECK5-SAME: () #[[ATTR1]] comdat { 1812 // CHECK5-NEXT: entry: 1813 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1814 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1815 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1816 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1817 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1818 // CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 8 1819 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1820 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1821 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1822 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1823 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1824 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 1825 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 1826 // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 1827 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 1828 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 1829 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1830 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1831 // CHECK5-NEXT: store i32 0, ptr [[T_VAR]], align 4 1832 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 1833 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 1834 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 1835 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 1836 // CHECK5-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 1837 // CHECK5-NEXT: store ptr undef, ptr [[_TMP1]], align 8 1838 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1839 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1840 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1841 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 1842 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 1843 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 1844 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1845 // CHECK5: arrayctor.loop: 1846 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1847 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1848 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 1849 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1850 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1851 // CHECK5: arrayctor.cont: 1852 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 1853 // CHECK5-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 8 1854 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1855 // CHECK5: omp.inner.for.cond: 1856 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 1857 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 1858 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1859 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1860 // CHECK5: omp.inner.for.cond.cleanup: 1861 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1862 // CHECK5: omp.inner.for.body: 1863 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1864 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1865 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1866 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1867 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP6]] 1868 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1869 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 1870 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] 1871 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] 1872 // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP6]] 1873 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1874 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 1875 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] 1876 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] 1877 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1878 // CHECK5: omp.body.continue: 1879 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1880 // CHECK5: omp.inner.for.inc: 1881 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1882 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1 1883 // CHECK5-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1884 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1885 // CHECK5: omp.inner.for.end: 1886 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 1887 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1888 // CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 1889 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 1890 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1891 // CHECK5: arraydestroy.body: 1892 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1893 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1894 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1895 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 1896 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 1897 // CHECK5: arraydestroy.done11: 1898 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 1899 // CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1900 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 1901 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] 1902 // CHECK5: arraydestroy.body13: 1903 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] 1904 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 1905 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] 1906 // CHECK5-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] 1907 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] 1908 // CHECK5: arraydestroy.done17: 1909 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1910 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 1911 // CHECK5-NEXT: ret i32 [[TMP11]] 1912 // 1913 // 1914 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1915 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1916 // CHECK5-NEXT: entry: 1917 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1918 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1919 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1920 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1921 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1922 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1923 // CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4 1924 // CHECK5-NEXT: ret void 1925 // 1926 // 1927 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1928 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1929 // CHECK5-NEXT: entry: 1930 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1931 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1932 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1933 // CHECK5-NEXT: ret void 1934 // 1935 // 1936 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1937 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1938 // CHECK5-NEXT: entry: 1939 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1940 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1941 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1942 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1943 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1944 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1945 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1946 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1947 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1948 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1949 // CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4 1950 // CHECK5-NEXT: ret void 1951 // 1952 // 1953 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1954 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1955 // CHECK5-NEXT: entry: 1956 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1957 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1958 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1959 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1960 // CHECK5-NEXT: ret void 1961 // 1962 // 1963 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1964 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1965 // CHECK5-NEXT: entry: 1966 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1967 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1968 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1969 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1970 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1971 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1972 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 1973 // CHECK5-NEXT: ret void 1974 // 1975 // 1976 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1977 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1978 // CHECK5-NEXT: entry: 1979 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1980 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1981 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1982 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1983 // CHECK5-NEXT: ret void 1984 // 1985 // 1986 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1987 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1988 // CHECK5-NEXT: entry: 1989 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1990 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1991 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1992 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1993 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1994 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1995 // CHECK5-NEXT: ret void 1996 // 1997 // 1998 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1999 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2000 // CHECK5-NEXT: entry: 2001 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2002 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2003 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2004 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2005 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2006 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2007 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2008 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2009 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2010 // CHECK5-NEXT: store i32 [[ADD]], ptr [[F]], align 4 2011 // CHECK5-NEXT: ret void 2012 // 2013 // 2014 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2015 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2016 // CHECK5-NEXT: entry: 2017 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2018 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2019 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2020 // CHECK5-NEXT: ret void 2021 // 2022 // 2023 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp 2024 // CHECK5-SAME: () #[[ATTR0]] { 2025 // CHECK5-NEXT: entry: 2026 // CHECK5-NEXT: call void @__cxx_global_var_init() 2027 // CHECK5-NEXT: call void @__cxx_global_var_init.1() 2028 // CHECK5-NEXT: call void @__cxx_global_var_init.2() 2029 // CHECK5-NEXT: ret void 2030 // 2031 // 2032 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init 2033 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 2034 // CHECK7-NEXT: entry: 2035 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 2036 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 2037 // CHECK7-NEXT: ret void 2038 // 2039 // 2040 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2041 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2042 // CHECK7-NEXT: entry: 2043 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2044 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2045 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2046 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2047 // CHECK7-NEXT: ret void 2048 // 2049 // 2050 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2051 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2052 // CHECK7-NEXT: entry: 2053 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2054 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2055 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2056 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2057 // CHECK7-NEXT: ret void 2058 // 2059 // 2060 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2061 // CHECK7-SAME: () #[[ATTR0]] { 2062 // CHECK7-NEXT: entry: 2063 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 2064 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 2065 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 2066 // CHECK7-NEXT: ret void 2067 // 2068 // 2069 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2070 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2071 // CHECK7-NEXT: entry: 2072 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2073 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2074 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2075 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2076 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2077 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2078 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2079 // CHECK7-NEXT: ret void 2080 // 2081 // 2082 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2083 // CHECK7-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2084 // CHECK7-NEXT: entry: 2085 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 2086 // CHECK7-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 2087 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2088 // CHECK7: arraydestroy.body: 2089 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2090 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2091 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2092 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 2093 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2094 // CHECK7: arraydestroy.done1: 2095 // CHECK7-NEXT: ret void 2096 // 2097 // 2098 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2099 // CHECK7-SAME: () #[[ATTR0]] { 2100 // CHECK7-NEXT: entry: 2101 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2102 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 2103 // CHECK7-NEXT: ret void 2104 // 2105 // 2106 // CHECK7-LABEL: define {{[^@]+}}@main 2107 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] { 2108 // CHECK7-NEXT: entry: 2109 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2110 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 2111 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2112 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2113 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2114 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2115 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2116 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 2117 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2118 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 2119 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2120 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 2121 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2122 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2123 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2124 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 2125 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 2126 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 2127 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2128 // CHECK7: arrayctor.loop: 2129 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2130 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2131 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 2132 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2133 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2134 // CHECK7: arrayctor.cont: 2135 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 2136 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2137 // CHECK7: omp.inner.for.cond: 2138 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 2139 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 2140 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 2141 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2142 // CHECK7: omp.inner.for.cond.cleanup: 2143 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2144 // CHECK7: omp.inner.for.body: 2145 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 2146 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 2147 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2148 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 2149 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP3]] 2150 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 2151 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP5]] 2152 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] 2153 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 2154 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP6]] 2155 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] 2156 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 2157 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] 2158 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] 2159 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] 2160 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2161 // CHECK7: omp.body.continue: 2162 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2163 // CHECK7: omp.inner.for.inc: 2164 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 2165 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 2166 // CHECK7-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 2167 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 2168 // CHECK7: omp.inner.for.end: 2169 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 2170 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 2171 // CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 2172 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i32 2 2173 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2174 // CHECK7: arraydestroy.body: 2175 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2176 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2177 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2178 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 2179 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 2180 // CHECK7: arraydestroy.done5: 2181 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 2182 // CHECK7-NEXT: ret i32 [[CALL]] 2183 // 2184 // 2185 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2186 // CHECK7-SAME: () #[[ATTR1]] comdat { 2187 // CHECK7-NEXT: entry: 2188 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2189 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2190 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2191 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2192 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2193 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 4 2194 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 2195 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 2196 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2197 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2198 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2199 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 2200 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 2201 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 2202 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 2203 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 2204 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2205 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 2206 // CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 4 2207 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 2208 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 2209 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 2210 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 2211 // CHECK7-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 2212 // CHECK7-NEXT: store ptr undef, ptr [[_TMP1]], align 4 2213 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2214 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2215 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2216 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 2217 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 2218 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 2219 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2220 // CHECK7: arrayctor.loop: 2221 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2222 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2223 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 2224 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2225 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2226 // CHECK7: arrayctor.cont: 2227 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 2228 // CHECK7-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 2229 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2230 // CHECK7: omp.inner.for.cond: 2231 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 2232 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]] 2233 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 2234 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2235 // CHECK7: omp.inner.for.cond.cleanup: 2236 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2237 // CHECK7: omp.inner.for.body: 2238 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 2239 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 2240 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2241 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 2242 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP7]] 2243 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 2244 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP5]] 2245 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] 2246 // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP7]] 2247 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 2248 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] 2249 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] 2250 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2251 // CHECK7: omp.body.continue: 2252 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2253 // CHECK7: omp.inner.for.inc: 2254 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 2255 // CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 2256 // CHECK7-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 2257 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 2258 // CHECK7: omp.inner.for.end: 2259 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 2260 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 2261 // CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 2262 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 2263 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2264 // CHECK7: arraydestroy.body: 2265 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2266 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2267 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2268 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] 2269 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] 2270 // CHECK7: arraydestroy.done10: 2271 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 2272 // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 2273 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 2274 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]] 2275 // CHECK7: arraydestroy.body12: 2276 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] 2277 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 2278 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] 2279 // CHECK7-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] 2280 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] 2281 // CHECK7: arraydestroy.done16: 2282 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 2283 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 2284 // CHECK7-NEXT: ret i32 [[TMP11]] 2285 // 2286 // 2287 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2288 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2289 // CHECK7-NEXT: entry: 2290 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2291 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2292 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2293 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2294 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2295 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2296 // CHECK7-NEXT: store float [[CONV]], ptr [[F]], align 4 2297 // CHECK7-NEXT: ret void 2298 // 2299 // 2300 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2301 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2302 // CHECK7-NEXT: entry: 2303 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2304 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2305 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2306 // CHECK7-NEXT: ret void 2307 // 2308 // 2309 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2310 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2311 // CHECK7-NEXT: entry: 2312 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2313 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2314 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2315 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2316 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2317 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2318 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2319 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2320 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2321 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2322 // CHECK7-NEXT: store float [[ADD]], ptr [[F]], align 4 2323 // CHECK7-NEXT: ret void 2324 // 2325 // 2326 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2327 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2328 // CHECK7-NEXT: entry: 2329 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2330 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2331 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2332 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2333 // CHECK7-NEXT: ret void 2334 // 2335 // 2336 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2337 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2338 // CHECK7-NEXT: entry: 2339 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2340 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2341 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2342 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2343 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2344 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2345 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 2346 // CHECK7-NEXT: ret void 2347 // 2348 // 2349 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2350 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2351 // CHECK7-NEXT: entry: 2352 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2353 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2354 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2355 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2356 // CHECK7-NEXT: ret void 2357 // 2358 // 2359 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2360 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2361 // CHECK7-NEXT: entry: 2362 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2363 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2364 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2365 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2366 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2367 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 2368 // CHECK7-NEXT: ret void 2369 // 2370 // 2371 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2372 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2373 // CHECK7-NEXT: entry: 2374 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2375 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2376 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2377 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2378 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2379 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2380 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2381 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2382 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2383 // CHECK7-NEXT: store i32 [[ADD]], ptr [[F]], align 4 2384 // CHECK7-NEXT: ret void 2385 // 2386 // 2387 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2388 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2389 // CHECK7-NEXT: entry: 2390 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2391 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2392 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2393 // CHECK7-NEXT: ret void 2394 // 2395 // 2396 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp 2397 // CHECK7-SAME: () #[[ATTR0]] { 2398 // CHECK7-NEXT: entry: 2399 // CHECK7-NEXT: call void @__cxx_global_var_init() 2400 // CHECK7-NEXT: call void @__cxx_global_var_init.1() 2401 // CHECK7-NEXT: call void @__cxx_global_var_init.2() 2402 // CHECK7-NEXT: ret void 2403 // 2404 // 2405 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 2406 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 2407 // CHECK9-NEXT: entry: 2408 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 2409 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 2410 // CHECK9-NEXT: ret void 2411 // 2412 // 2413 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2414 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 2415 // CHECK9-NEXT: entry: 2416 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2417 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2418 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2419 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2420 // CHECK9-NEXT: ret void 2421 // 2422 // 2423 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2424 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2425 // CHECK9-NEXT: entry: 2426 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2427 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2428 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2429 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2430 // CHECK9-NEXT: ret void 2431 // 2432 // 2433 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2434 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2435 // CHECK9-NEXT: entry: 2436 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2437 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2438 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2439 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2440 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2441 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2442 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 2443 // CHECK9-NEXT: ret void 2444 // 2445 // 2446 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2447 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2448 // CHECK9-NEXT: entry: 2449 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2450 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2451 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2452 // CHECK9-NEXT: ret void 2453 // 2454 // 2455 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2456 // CHECK9-SAME: () #[[ATTR0]] { 2457 // CHECK9-NEXT: entry: 2458 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 2459 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 2460 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 2461 // CHECK9-NEXT: ret void 2462 // 2463 // 2464 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2465 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2466 // CHECK9-NEXT: entry: 2467 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2468 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2469 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2470 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2471 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2472 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2473 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2474 // CHECK9-NEXT: ret void 2475 // 2476 // 2477 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2478 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2479 // CHECK9-NEXT: entry: 2480 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2481 // CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2482 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2483 // CHECK9: arraydestroy.body: 2484 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2485 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2486 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2487 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 2488 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2489 // CHECK9: arraydestroy.done1: 2490 // CHECK9-NEXT: ret void 2491 // 2492 // 2493 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2494 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2495 // CHECK9-NEXT: entry: 2496 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2497 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2498 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2499 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2500 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2501 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2502 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2503 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2504 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2505 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2506 // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 2507 // CHECK9-NEXT: ret void 2508 // 2509 // 2510 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2511 // CHECK9-SAME: () #[[ATTR0]] { 2512 // CHECK9-NEXT: entry: 2513 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2514 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 2515 // CHECK9-NEXT: ret void 2516 // 2517 // 2518 // CHECK9-LABEL: define {{[^@]+}}@main 2519 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 2520 // CHECK9-NEXT: entry: 2521 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2522 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2523 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 2524 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2525 // CHECK9-NEXT: ret i32 0 2526 // 2527 // 2528 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 2529 // CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR4:[0-9]+]] { 2530 // CHECK9-NEXT: entry: 2531 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 2532 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 2533 // CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 2534 // CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 2535 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined) 2536 // CHECK9-NEXT: ret void 2537 // 2538 // 2539 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined 2540 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 2541 // CHECK9-NEXT: entry: 2542 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2543 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2544 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2545 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 2546 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 2547 // CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2548 // CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2549 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2550 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2551 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 2552 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 2553 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 2554 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 2555 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 2556 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2557 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2558 // CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 8 2559 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 2560 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 2561 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2562 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2563 // CHECK9-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 8 2564 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2565 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2566 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2567 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2568 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 2569 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2570 // CHECK9: cond.true: 2571 // CHECK9-NEXT: br label [[COND_END:%.*]] 2572 // CHECK9: cond.false: 2573 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2574 // CHECK9-NEXT: br label [[COND_END]] 2575 // CHECK9: cond.end: 2576 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2577 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2578 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2579 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2580 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2581 // CHECK9: omp.inner.for.cond: 2582 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]] 2583 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]] 2584 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2585 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2586 // CHECK9: omp.inner.for.body: 2587 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP4]] 2588 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 2589 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]] 2590 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 2591 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP4]] 2592 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2593 // CHECK9: omp.inner.for.inc: 2594 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 2595 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP4]] 2596 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 2597 // CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 2598 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 2599 // CHECK9: omp.inner.for.end: 2600 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2601 // CHECK9: omp.loop.exit: 2602 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2603 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2604 // CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 2605 // CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2606 // CHECK9: .omp.final.then: 2607 // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 2608 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 2609 // CHECK9: .omp.final.done: 2610 // CHECK9-NEXT: ret void 2611 // 2612 // 2613 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined.omp_outlined 2614 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 2615 // CHECK9-NEXT: entry: 2616 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2617 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2618 // CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 2619 // CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 2620 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2621 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 2622 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 2623 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2624 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2625 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2626 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2627 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 2628 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 2629 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 2630 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 2631 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 2632 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 2633 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2634 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2635 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2636 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2637 // CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 8 2638 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2639 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2640 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2641 // CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 2642 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2643 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 2644 // CHECK9-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 2645 // CHECK9-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 2646 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2647 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2648 // CHECK9-NEXT: store ptr [[G1]], ptr [[_TMP3]], align 8 2649 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2650 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 2651 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2652 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2653 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 2654 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2655 // CHECK9: cond.true: 2656 // CHECK9-NEXT: br label [[COND_END:%.*]] 2657 // CHECK9: cond.false: 2658 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2659 // CHECK9-NEXT: br label [[COND_END]] 2660 // CHECK9: cond.end: 2661 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2662 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2663 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2664 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 2665 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2666 // CHECK9: omp.inner.for.cond: 2667 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]] 2668 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]] 2669 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2670 // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2671 // CHECK9: omp.inner.for.body: 2672 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 2673 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 2674 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2675 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 2676 // CHECK9-NEXT: store i32 1, ptr [[G]], align 4, !llvm.access.group [[ACC_GRP8]] 2677 // CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !llvm.access.group [[ACC_GRP8]] 2678 // CHECK9-NEXT: store volatile i32 1, ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP8]] 2679 // CHECK9-NEXT: store i32 2, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP8]] 2680 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 2681 // CHECK9-NEXT: store ptr [[G]], ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP8]] 2682 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 2683 // CHECK9-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8, !llvm.access.group [[ACC_GRP8]] 2684 // CHECK9-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP8]] 2685 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 2686 // CHECK9-NEXT: store ptr [[SIVAR]], ptr [[TMP14]], align 8, !llvm.access.group [[ACC_GRP8]] 2687 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group [[ACC_GRP8]] 2688 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2689 // CHECK9: omp.body.continue: 2690 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2691 // CHECK9: omp.inner.for.inc: 2692 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 2693 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 2694 // CHECK9-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 2695 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 2696 // CHECK9: omp.inner.for.end: 2697 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2698 // CHECK9: omp.loop.exit: 2699 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 2700 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2701 // CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 2702 // CHECK9-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2703 // CHECK9: .omp.final.then: 2704 // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 2705 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 2706 // CHECK9: .omp.final.done: 2707 // CHECK9-NEXT: ret void 2708 // 2709 // 2710 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp 2711 // CHECK9-SAME: () #[[ATTR0]] { 2712 // CHECK9-NEXT: entry: 2713 // CHECK9-NEXT: call void @__cxx_global_var_init() 2714 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 2715 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 2716 // CHECK9-NEXT: ret void 2717 // 2718 // 2719 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init 2720 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 2721 // CHECK11-NEXT: entry: 2722 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 2723 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 2724 // CHECK11-NEXT: ret void 2725 // 2726 // 2727 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2728 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 2729 // CHECK11-NEXT: entry: 2730 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2731 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2732 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2733 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2734 // CHECK11-NEXT: ret void 2735 // 2736 // 2737 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2738 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2739 // CHECK11-NEXT: entry: 2740 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2741 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2742 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2743 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2744 // CHECK11-NEXT: ret void 2745 // 2746 // 2747 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2748 // CHECK11-SAME: () #[[ATTR0]] { 2749 // CHECK11-NEXT: entry: 2750 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 2751 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 2752 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 2753 // CHECK11-NEXT: ret void 2754 // 2755 // 2756 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2757 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2758 // CHECK11-NEXT: entry: 2759 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2760 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2761 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2762 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2763 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2764 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2765 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2766 // CHECK11-NEXT: ret void 2767 // 2768 // 2769 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2770 // CHECK11-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2771 // CHECK11-NEXT: entry: 2772 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2773 // CHECK11-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2774 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2775 // CHECK11: arraydestroy.body: 2776 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2777 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2778 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2779 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 2780 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2781 // CHECK11: arraydestroy.done1: 2782 // CHECK11-NEXT: ret void 2783 // 2784 // 2785 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2786 // CHECK11-SAME: () #[[ATTR0]] { 2787 // CHECK11-NEXT: entry: 2788 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2789 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 2790 // CHECK11-NEXT: ret void 2791 // 2792 // 2793 // CHECK11-LABEL: define {{[^@]+}}@main 2794 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 2795 // CHECK11-NEXT: entry: 2796 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2797 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2798 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 2799 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2800 // CHECK11-NEXT: ret i32 0 2801 // 2802 // 2803 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2804 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2805 // CHECK11-NEXT: entry: 2806 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2807 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2808 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2809 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2810 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2811 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2812 // CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4 2813 // CHECK11-NEXT: ret void 2814 // 2815 // 2816 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2817 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2818 // CHECK11-NEXT: entry: 2819 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2820 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2821 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2822 // CHECK11-NEXT: ret void 2823 // 2824 // 2825 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2826 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2827 // CHECK11-NEXT: entry: 2828 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2829 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2830 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2831 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2832 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2833 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2834 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2835 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2836 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2837 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2838 // CHECK11-NEXT: store float [[ADD]], ptr [[F]], align 4 2839 // CHECK11-NEXT: ret void 2840 // 2841 // 2842 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp 2843 // CHECK11-SAME: () #[[ATTR0]] { 2844 // CHECK11-NEXT: entry: 2845 // CHECK11-NEXT: call void @__cxx_global_var_init() 2846 // CHECK11-NEXT: call void @__cxx_global_var_init.1() 2847 // CHECK11-NEXT: call void @__cxx_global_var_init.2() 2848 // CHECK11-NEXT: ret void 2849 // 2850