1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s 4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 5 6 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 9 10 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK5 11 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s 12 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 13 14 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s 16 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 17 18 // expected-no-diagnostics 19 #ifndef HEADER 20 #define HEADER 21 22 typedef __INTPTR_TYPE__ intptr_t; 23 24 25 void foo(); 26 27 struct S { 28 intptr_t a, b, c; 29 S(intptr_t a) : a(a) {} 30 operator char() { return a; } 31 ~S() {} 32 }; 33 34 template <typename T, int C> 35 int tmain() { 36 #pragma omp target 37 #pragma omp teams distribute parallel for simd num_threads(C) 38 for (int i = 0; i < 100; i++) 39 foo(); 40 #pragma omp target 41 #pragma omp teams distribute parallel for simd num_threads(T(23)) 42 for (int i = 0; i < 100; i++) 43 foo(); 44 return 0; 45 } 46 47 int main() { 48 S s(0); 49 char a = s; 50 #pragma omp target 51 #pragma omp teams distribute parallel for simd num_threads(2) 52 for (int i = 0; i < 100; i++) { 53 foo(); 54 } 55 #pragma omp target 56 57 #pragma omp teams distribute parallel for simd num_threads(a) 58 for (int i = 0; i < 100; i++) { 59 foo(); 60 } 61 return a + tmain<char, 5>() + tmain<S, 1>(); 62 } 63 64 // tmain 5 65 66 // tmain 1 67 68 69 70 71 72 73 74 75 76 77 #endif 78 // CHECK1-LABEL: define {{[^@]+}}@main 79 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__gxx_personality_v0 { 80 // CHECK1-NEXT: entry: 81 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 82 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 83 // CHECK1-NEXT: [[A:%.*]] = alloca i8, align 1 84 // CHECK1-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 85 // CHECK1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 86 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 87 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 88 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 89 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 90 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 91 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 92 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 93 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 94 // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 95 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 96 // CHECK1-NEXT: call void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[S]], i64 noundef 0) 97 // CHECK1-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) 98 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] 99 // CHECK1: invoke.cont: 100 // CHECK1-NEXT: store i8 [[CALL]], ptr [[A]], align 1 101 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 102 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 103 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 104 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 105 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 106 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 107 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 108 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 109 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 110 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 111 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 112 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 113 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 114 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 115 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 116 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 117 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 118 // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 119 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 120 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 121 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 122 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 123 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 124 // CHECK1-NEXT: store [3 x i32] [i32 2, i32 0, i32 0], ptr [[TMP11]], align 4 125 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 126 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 127 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 2, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.region_id, ptr [[KERNEL_ARGS]]) 128 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 129 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 130 // CHECK1: omp_offload.failed: 131 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50() #[[ATTR4:[0-9]+]] 132 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 133 // CHECK1: lpad: 134 // CHECK1-NEXT: [[TMP15:%.*]] = landingpad { ptr, i32 } 135 // CHECK1-NEXT: cleanup 136 // CHECK1-NEXT: [[TMP16:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 0 137 // CHECK1-NEXT: store ptr [[TMP16]], ptr [[EXN_SLOT]], align 8 138 // CHECK1-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 1 139 // CHECK1-NEXT: store i32 [[TMP17]], ptr [[EHSELECTOR_SLOT]], align 4 140 // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR4]] 141 // CHECK1-NEXT: br label [[EH_RESUME:%.*]] 142 // CHECK1: omp_offload.cont: 143 // CHECK1-NEXT: [[TMP18:%.*]] = load i8, ptr [[A]], align 1 144 // CHECK1-NEXT: store i8 [[TMP18]], ptr [[A_CASTED]], align 1 145 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[A_CASTED]], align 8 146 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 147 // CHECK1-NEXT: store i64 [[TMP19]], ptr [[TMP20]], align 8 148 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 149 // CHECK1-NEXT: store i64 [[TMP19]], ptr [[TMP21]], align 8 150 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 151 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 152 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 153 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 154 // CHECK1-NEXT: [[TMP25:%.*]] = load i8, ptr [[A]], align 1 155 // CHECK1-NEXT: store i8 [[TMP25]], ptr [[DOTCAPTURE_EXPR_]], align 1 156 // CHECK1-NEXT: [[TMP26:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 157 // CHECK1-NEXT: [[TMP27:%.*]] = zext i8 [[TMP26]] to i32 158 // CHECK1-NEXT: [[TMP28:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP27]], 0 159 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 160 // CHECK1-NEXT: store i32 3, ptr [[TMP29]], align 4 161 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 162 // CHECK1-NEXT: store i32 1, ptr [[TMP30]], align 4 163 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 164 // CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP31]], align 8 165 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3 166 // CHECK1-NEXT: store ptr [[TMP24]], ptr [[TMP32]], align 8 167 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4 168 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP33]], align 8 169 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5 170 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP34]], align 8 171 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6 172 // CHECK1-NEXT: store ptr null, ptr [[TMP35]], align 8 173 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 174 // CHECK1-NEXT: store ptr null, ptr [[TMP36]], align 8 175 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 176 // CHECK1-NEXT: store i64 100, ptr [[TMP37]], align 8 177 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9 178 // CHECK1-NEXT: store i64 0, ptr [[TMP38]], align 8 179 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10 180 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 4 181 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11 182 // CHECK1-NEXT: store [3 x i32] [[TMP28]], ptr [[TMP40]], align 4 183 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12 184 // CHECK1-NEXT: store i32 0, ptr [[TMP41]], align 4 185 // CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 [[TMP27]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.region_id, ptr [[KERNEL_ARGS2]]) 186 // CHECK1-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 187 // CHECK1-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 188 // CHECK1: omp_offload.failed3: 189 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55(i64 [[TMP19]]) #[[ATTR4]] 190 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] 191 // CHECK1: omp_offload.cont4: 192 // CHECK1-NEXT: [[TMP44:%.*]] = load i8, ptr [[A]], align 1 193 // CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP44]] to i32 194 // CHECK1-NEXT: [[CALL6:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() 195 // CHECK1-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] 196 // CHECK1: invoke.cont5: 197 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL6]] 198 // CHECK1-NEXT: [[CALL8:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() 199 // CHECK1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] 200 // CHECK1: invoke.cont7: 201 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] 202 // CHECK1-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 203 // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR4]] 204 // CHECK1-NEXT: [[TMP45:%.*]] = load i32, ptr [[RETVAL]], align 4 205 // CHECK1-NEXT: ret i32 [[TMP45]] 206 // CHECK1: eh.resume: 207 // CHECK1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 208 // CHECK1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 209 // CHECK1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 210 // CHECK1-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 211 // CHECK1-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] 212 // 213 // 214 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC1El 215 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 216 // CHECK1-NEXT: entry: 217 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 218 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 219 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 220 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 221 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 222 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 223 // CHECK1-NEXT: call void @_ZN1SC2El(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]]) 224 // CHECK1-NEXT: ret void 225 // 226 // 227 // CHECK1-LABEL: define {{[^@]+}}@_ZN1ScvcEv 228 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat { 229 // CHECK1-NEXT: entry: 230 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 231 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 232 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 233 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 234 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 235 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 236 // CHECK1-NEXT: ret i8 [[CONV]] 237 // 238 // 239 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50 240 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 241 // CHECK1-NEXT: entry: 242 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined) 243 // CHECK1-NEXT: ret void 244 // 245 // 246 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined 247 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 248 // CHECK1-NEXT: entry: 249 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 250 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 251 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 252 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 253 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 254 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 255 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 256 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 257 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 258 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 259 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 260 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 261 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 262 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 263 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 264 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 265 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 266 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 267 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 268 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 269 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 270 // CHECK1: cond.true: 271 // CHECK1-NEXT: br label [[COND_END:%.*]] 272 // CHECK1: cond.false: 273 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 274 // CHECK1-NEXT: br label [[COND_END]] 275 // CHECK1: cond.end: 276 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 277 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 278 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 279 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 280 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 281 // CHECK1: omp.inner.for.cond: 282 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] 283 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 284 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 285 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 286 // CHECK1: omp.inner.for.body: 287 // CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group [[ACC_GRP9]] 288 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP9]] 289 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 290 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 291 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 292 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP9]] 293 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 294 // CHECK1: omp.inner.for.inc: 295 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 296 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP9]] 297 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 298 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 299 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 300 // CHECK1: omp.inner.for.end: 301 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 302 // CHECK1: omp.loop.exit: 303 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 304 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 305 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 306 // CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 307 // CHECK1: .omp.final.then: 308 // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 309 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 310 // CHECK1: .omp.final.done: 311 // CHECK1-NEXT: ret void 312 // 313 // 314 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined.omp_outlined 315 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 316 // CHECK1-NEXT: entry: 317 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 318 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 319 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 320 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 321 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 322 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 323 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 324 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 325 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 326 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 327 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 328 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 329 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 330 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 331 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 332 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 333 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 334 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 335 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 336 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 337 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 338 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 339 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 340 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 341 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 342 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 343 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 344 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 345 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 346 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 347 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 348 // CHECK1: cond.true: 349 // CHECK1-NEXT: br label [[COND_END:%.*]] 350 // CHECK1: cond.false: 351 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 352 // CHECK1-NEXT: br label [[COND_END]] 353 // CHECK1: cond.end: 354 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 355 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 356 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 357 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 358 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 359 // CHECK1: omp.inner.for.cond: 360 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] 361 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] 362 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 363 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 364 // CHECK1: omp.inner.for.body: 365 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] 366 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 367 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 368 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] 369 // CHECK1-NEXT: invoke void @_Z3foov() 370 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP13]] 371 // CHECK1: invoke.cont: 372 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 373 // CHECK1: omp.body.continue: 374 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 375 // CHECK1: omp.inner.for.inc: 376 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] 377 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 378 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] 379 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 380 // CHECK1: omp.inner.for.end: 381 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 382 // CHECK1: omp.loop.exit: 383 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 384 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 385 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 386 // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 387 // CHECK1: .omp.final.then: 388 // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 389 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 390 // CHECK1: .omp.final.done: 391 // CHECK1-NEXT: ret void 392 // CHECK1: terminate.lpad: 393 // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } 394 // CHECK1-NEXT: catch ptr null 395 // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 396 // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7:[0-9]+]], !llvm.access.group [[ACC_GRP13]] 397 // CHECK1-NEXT: unreachable 398 // 399 // 400 // CHECK1-LABEL: define {{[^@]+}}@__clang_call_terminate 401 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat { 402 // CHECK1-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR4]] 403 // CHECK1-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] 404 // CHECK1-NEXT: unreachable 405 // 406 // 407 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 408 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { 409 // CHECK1-NEXT: entry: 410 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 411 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 412 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 413 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 414 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, ptr [[A_ADDR]], align 1 415 // CHECK1-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 1 416 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 417 // CHECK1-NEXT: store i8 [[TMP1]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 418 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 419 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined, i64 [[TMP2]]) 420 // CHECK1-NEXT: ret void 421 // 422 // 423 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined 424 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 425 // CHECK1-NEXT: entry: 426 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 427 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 428 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 429 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 430 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 431 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 432 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 433 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 434 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 435 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 436 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 437 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 438 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 439 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 440 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 441 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 442 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 443 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 444 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 445 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 446 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 447 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 448 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 449 // CHECK1: cond.true: 450 // CHECK1-NEXT: br label [[COND_END:%.*]] 451 // CHECK1: cond.false: 452 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 453 // CHECK1-NEXT: br label [[COND_END]] 454 // CHECK1: cond.end: 455 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 456 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 457 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 458 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 459 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 460 // CHECK1: omp.inner.for.cond: 461 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] 462 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]] 463 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 464 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 465 // CHECK1: omp.inner.for.body: 466 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !llvm.access.group [[ACC_GRP18]] 467 // CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 468 // CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP18]] 469 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP18]] 470 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 471 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]] 472 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 473 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined.omp_outlined, i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group [[ACC_GRP18]] 474 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 475 // CHECK1: omp.inner.for.inc: 476 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 477 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP18]] 478 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 479 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 480 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 481 // CHECK1: omp.inner.for.end: 482 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 483 // CHECK1: omp.loop.exit: 484 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 485 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 486 // CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 487 // CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 488 // CHECK1: .omp.final.then: 489 // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 490 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 491 // CHECK1: .omp.final.done: 492 // CHECK1-NEXT: ret void 493 // 494 // 495 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined.omp_outlined 496 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 497 // CHECK1-NEXT: entry: 498 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 499 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 500 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 501 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 502 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 503 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 504 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 505 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 506 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 507 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 508 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 509 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 510 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 511 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 512 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 513 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 514 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 515 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 516 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 517 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 518 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 519 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 520 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 521 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 522 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 523 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 524 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 525 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 526 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 527 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 528 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 529 // CHECK1: cond.true: 530 // CHECK1-NEXT: br label [[COND_END:%.*]] 531 // CHECK1: cond.false: 532 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 533 // CHECK1-NEXT: br label [[COND_END]] 534 // CHECK1: cond.end: 535 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 536 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 537 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 538 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 539 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 540 // CHECK1: omp.inner.for.cond: 541 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] 542 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] 543 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 544 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 545 // CHECK1: omp.inner.for.body: 546 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 547 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 548 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 549 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] 550 // CHECK1-NEXT: invoke void @_Z3foov() 551 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP21]] 552 // CHECK1: invoke.cont: 553 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 554 // CHECK1: omp.body.continue: 555 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 556 // CHECK1: omp.inner.for.inc: 557 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 558 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 559 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 560 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 561 // CHECK1: omp.inner.for.end: 562 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 563 // CHECK1: omp.loop.exit: 564 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 565 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 566 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 567 // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 568 // CHECK1: .omp.final.then: 569 // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 570 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 571 // CHECK1: .omp.final.done: 572 // CHECK1-NEXT: ret void 573 // CHECK1: terminate.lpad: 574 // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } 575 // CHECK1-NEXT: catch ptr null 576 // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 577 // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP21]] 578 // CHECK1-NEXT: unreachable 579 // 580 // 581 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv 582 // CHECK1-SAME: () #[[ATTR2]] comdat { 583 // CHECK1-NEXT: entry: 584 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 585 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 586 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 587 // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 588 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 589 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 590 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 591 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 592 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 593 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 594 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 595 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 596 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 597 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 598 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 599 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 600 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 601 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 602 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 603 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 604 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 605 // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 606 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 607 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 608 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 609 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 610 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 611 // CHECK1-NEXT: store [3 x i32] [i32 5, i32 0, i32 0], ptr [[TMP11]], align 4 612 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 613 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 614 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 5, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.region_id, ptr [[KERNEL_ARGS]]) 615 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 616 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 617 // CHECK1: omp_offload.failed: 618 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36() #[[ATTR4]] 619 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 620 // CHECK1: omp_offload.cont: 621 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 622 // CHECK1-NEXT: store i32 3, ptr [[TMP15]], align 4 623 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 624 // CHECK1-NEXT: store i32 0, ptr [[TMP16]], align 4 625 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 626 // CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8 627 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3 628 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 629 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4 630 // CHECK1-NEXT: store ptr null, ptr [[TMP19]], align 8 631 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5 632 // CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8 633 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6 634 // CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8 635 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 636 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 637 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 638 // CHECK1-NEXT: store i64 100, ptr [[TMP23]], align 8 639 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9 640 // CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 8 641 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10 642 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4 643 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11 644 // CHECK1-NEXT: store [3 x i32] [i32 23, i32 0, i32 0], ptr [[TMP26]], align 4 645 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12 646 // CHECK1-NEXT: store i32 0, ptr [[TMP27]], align 4 647 // CHECK1-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 23, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.region_id, ptr [[KERNEL_ARGS2]]) 648 // CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 649 // CHECK1-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 650 // CHECK1: omp_offload.failed3: 651 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40() #[[ATTR4]] 652 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] 653 // CHECK1: omp_offload.cont4: 654 // CHECK1-NEXT: ret i32 0 655 // 656 // 657 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv 658 // CHECK1-SAME: () #[[ATTR2]] comdat personality ptr @__gxx_personality_v0 { 659 // CHECK1-NEXT: entry: 660 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 661 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 662 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 663 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 664 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 665 // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 666 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 667 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 668 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 669 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 670 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 671 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 672 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 673 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 674 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 675 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 676 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 677 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 678 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 679 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 680 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 681 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 682 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 683 // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 684 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 685 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 686 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 687 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 688 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 689 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4 690 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 691 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 692 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.region_id, ptr [[KERNEL_ARGS]]) 693 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 694 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 695 // CHECK1: omp_offload.failed: 696 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR4]] 697 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 698 // CHECK1: omp_offload.cont: 699 // CHECK1-NEXT: invoke void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) 700 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 701 // CHECK1: invoke.cont: 702 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 703 // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] 704 // CHECK1-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 705 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 706 // CHECK1-NEXT: [[TMP16:%.*]] = zext i8 [[TMP15]] to i32 707 // CHECK1-NEXT: [[TMP17:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP16]], 0 708 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 709 // CHECK1-NEXT: store i32 3, ptr [[TMP18]], align 4 710 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 711 // CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4 712 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 713 // CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8 714 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3 715 // CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8 716 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4 717 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 718 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5 719 // CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8 720 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6 721 // CHECK1-NEXT: store ptr null, ptr [[TMP24]], align 8 722 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 723 // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 724 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 725 // CHECK1-NEXT: store i64 100, ptr [[TMP26]], align 8 726 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9 727 // CHECK1-NEXT: store i64 0, ptr [[TMP27]], align 8 728 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10 729 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 730 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11 731 // CHECK1-NEXT: store [3 x i32] [[TMP17]], ptr [[TMP29]], align 4 732 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12 733 // CHECK1-NEXT: store i32 0, ptr [[TMP30]], align 4 734 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 [[TMP16]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.region_id, ptr [[KERNEL_ARGS2]]) 735 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 736 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 737 // CHECK1: omp_offload.failed3: 738 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40() #[[ATTR4]] 739 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] 740 // CHECK1: omp_offload.cont4: 741 // CHECK1-NEXT: ret i32 0 742 // CHECK1: terminate.lpad: 743 // CHECK1-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 } 744 // CHECK1-NEXT: catch ptr null 745 // CHECK1-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0 746 // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP34]]) #[[ATTR7]] 747 // CHECK1-NEXT: unreachable 748 // 749 // 750 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev 751 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 752 // CHECK1-NEXT: entry: 753 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 754 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 755 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 756 // CHECK1-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]] 757 // CHECK1-NEXT: ret void 758 // 759 // 760 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2El 761 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat { 762 // CHECK1-NEXT: entry: 763 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 764 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 765 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 766 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 767 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 768 // CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 769 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 770 // CHECK1-NEXT: store i64 [[TMP0]], ptr [[A2]], align 8 771 // CHECK1-NEXT: ret void 772 // 773 // 774 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev 775 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 776 // CHECK1-NEXT: entry: 777 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 778 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 779 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 780 // CHECK1-NEXT: ret void 781 // 782 // 783 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36 784 // CHECK1-SAME: () #[[ATTR3]] { 785 // CHECK1-NEXT: entry: 786 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined) 787 // CHECK1-NEXT: ret void 788 // 789 // 790 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined 791 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 792 // CHECK1-NEXT: entry: 793 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 794 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 795 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 796 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 797 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 798 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 799 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 800 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 801 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 802 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 803 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 804 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 805 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 806 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 807 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 808 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 809 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 810 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 811 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 812 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 813 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 814 // CHECK1: cond.true: 815 // CHECK1-NEXT: br label [[COND_END:%.*]] 816 // CHECK1: cond.false: 817 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 818 // CHECK1-NEXT: br label [[COND_END]] 819 // CHECK1: cond.end: 820 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 821 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 822 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 823 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 824 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 825 // CHECK1: omp.inner.for.cond: 826 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] 827 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] 828 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 829 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 830 // CHECK1: omp.inner.for.body: 831 // CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group [[ACC_GRP24]] 832 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP24]] 833 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 834 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] 835 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 836 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP24]] 837 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 838 // CHECK1: omp.inner.for.inc: 839 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 840 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP24]] 841 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 842 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 843 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 844 // CHECK1: omp.inner.for.end: 845 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 846 // CHECK1: omp.loop.exit: 847 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 848 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 849 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 850 // CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 851 // CHECK1: .omp.final.then: 852 // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 853 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 854 // CHECK1: .omp.final.done: 855 // CHECK1-NEXT: ret void 856 // 857 // 858 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined.omp_outlined 859 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 860 // CHECK1-NEXT: entry: 861 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 862 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 863 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 864 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 865 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 866 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 867 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 868 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 869 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 870 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 871 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 872 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 873 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 874 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 875 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 876 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 877 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 878 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 879 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 880 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 881 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 882 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 883 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 884 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 885 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 886 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 887 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 888 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 889 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 890 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 891 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 892 // CHECK1: cond.true: 893 // CHECK1-NEXT: br label [[COND_END:%.*]] 894 // CHECK1: cond.false: 895 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 896 // CHECK1-NEXT: br label [[COND_END]] 897 // CHECK1: cond.end: 898 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 899 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 900 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 901 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 902 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 903 // CHECK1: omp.inner.for.cond: 904 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] 905 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] 906 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 907 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 908 // CHECK1: omp.inner.for.body: 909 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 910 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 911 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 912 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] 913 // CHECK1-NEXT: invoke void @_Z3foov() 914 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP27]] 915 // CHECK1: invoke.cont: 916 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 917 // CHECK1: omp.body.continue: 918 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 919 // CHECK1: omp.inner.for.inc: 920 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 921 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 922 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 923 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 924 // CHECK1: omp.inner.for.end: 925 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 926 // CHECK1: omp.loop.exit: 927 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 928 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 929 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 930 // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 931 // CHECK1: .omp.final.then: 932 // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 933 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 934 // CHECK1: .omp.final.done: 935 // CHECK1-NEXT: ret void 936 // CHECK1: terminate.lpad: 937 // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } 938 // CHECK1-NEXT: catch ptr null 939 // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 940 // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP27]] 941 // CHECK1-NEXT: unreachable 942 // 943 // 944 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40 945 // CHECK1-SAME: () #[[ATTR3]] { 946 // CHECK1-NEXT: entry: 947 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined) 948 // CHECK1-NEXT: ret void 949 // 950 // 951 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined 952 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 953 // CHECK1-NEXT: entry: 954 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 955 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 956 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 957 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 958 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 959 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 960 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 961 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 962 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 963 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 964 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 965 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 966 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 967 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 968 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 969 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 970 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 971 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 972 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 973 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 974 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 975 // CHECK1: cond.true: 976 // CHECK1-NEXT: br label [[COND_END:%.*]] 977 // CHECK1: cond.false: 978 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 979 // CHECK1-NEXT: br label [[COND_END]] 980 // CHECK1: cond.end: 981 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 982 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 983 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 984 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 985 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 986 // CHECK1: omp.inner.for.cond: 987 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]] 988 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] 989 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 990 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 991 // CHECK1: omp.inner.for.body: 992 // CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group [[ACC_GRP30]] 993 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP30]] 994 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 995 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] 996 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 997 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP30]] 998 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 999 // CHECK1: omp.inner.for.inc: 1000 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] 1001 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP30]] 1002 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 1003 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] 1004 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 1005 // CHECK1: omp.inner.for.end: 1006 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1007 // CHECK1: omp.loop.exit: 1008 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1009 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1010 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1011 // CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1012 // CHECK1: .omp.final.then: 1013 // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 1014 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1015 // CHECK1: .omp.final.done: 1016 // CHECK1-NEXT: ret void 1017 // 1018 // 1019 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined.omp_outlined 1020 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 1021 // CHECK1-NEXT: entry: 1022 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1023 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1024 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1025 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1026 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1027 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1028 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1029 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1030 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1031 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1032 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1033 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1034 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1035 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1036 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1037 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1038 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 1039 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1040 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 1041 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1042 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 1043 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1044 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 1045 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1046 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1047 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1048 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1049 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1050 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1051 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 1052 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1053 // CHECK1: cond.true: 1054 // CHECK1-NEXT: br label [[COND_END:%.*]] 1055 // CHECK1: cond.false: 1056 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1057 // CHECK1-NEXT: br label [[COND_END]] 1058 // CHECK1: cond.end: 1059 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1060 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1061 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1062 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1063 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1064 // CHECK1: omp.inner.for.cond: 1065 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] 1066 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] 1067 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1068 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1069 // CHECK1: omp.inner.for.body: 1070 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 1071 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1072 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1073 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] 1074 // CHECK1-NEXT: invoke void @_Z3foov() 1075 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP33]] 1076 // CHECK1: invoke.cont: 1077 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1078 // CHECK1: omp.body.continue: 1079 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1080 // CHECK1: omp.inner.for.inc: 1081 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 1082 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 1083 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 1084 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 1085 // CHECK1: omp.inner.for.end: 1086 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1087 // CHECK1: omp.loop.exit: 1088 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 1089 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1090 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 1091 // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1092 // CHECK1: .omp.final.then: 1093 // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 1094 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1095 // CHECK1: .omp.final.done: 1096 // CHECK1-NEXT: ret void 1097 // CHECK1: terminate.lpad: 1098 // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } 1099 // CHECK1-NEXT: catch ptr null 1100 // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 1101 // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP33]] 1102 // CHECK1-NEXT: unreachable 1103 // 1104 // 1105 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36 1106 // CHECK1-SAME: () #[[ATTR3]] { 1107 // CHECK1-NEXT: entry: 1108 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined) 1109 // CHECK1-NEXT: ret void 1110 // 1111 // 1112 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined 1113 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 1114 // CHECK1-NEXT: entry: 1115 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1116 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1117 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1118 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1119 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1120 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1121 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1122 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1123 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1124 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1125 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1126 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1127 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 1128 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1129 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1130 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1131 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1132 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1133 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1134 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 1135 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1136 // CHECK1: cond.true: 1137 // CHECK1-NEXT: br label [[COND_END:%.*]] 1138 // CHECK1: cond.false: 1139 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1140 // CHECK1-NEXT: br label [[COND_END]] 1141 // CHECK1: cond.end: 1142 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1143 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1144 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1145 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1146 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1147 // CHECK1: omp.inner.for.cond: 1148 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] 1149 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] 1150 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1151 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1152 // CHECK1: omp.inner.for.body: 1153 // CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group [[ACC_GRP36]] 1154 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP36]] 1155 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 1156 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] 1157 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 1158 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP36]] 1159 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1160 // CHECK1: omp.inner.for.inc: 1161 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 1162 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP36]] 1163 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 1164 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 1165 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] 1166 // CHECK1: omp.inner.for.end: 1167 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1168 // CHECK1: omp.loop.exit: 1169 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1170 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1171 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1172 // CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1173 // CHECK1: .omp.final.then: 1174 // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 1175 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1176 // CHECK1: .omp.final.done: 1177 // CHECK1-NEXT: ret void 1178 // 1179 // 1180 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined.omp_outlined 1181 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 1182 // CHECK1-NEXT: entry: 1183 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1184 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1185 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1186 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1187 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1188 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1189 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1190 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1191 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1192 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1193 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1194 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1195 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1196 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1197 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1198 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1199 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 1200 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1201 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 1202 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1203 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 1204 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1205 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 1206 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1207 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1208 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1209 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1210 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1211 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1212 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 1213 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1214 // CHECK1: cond.true: 1215 // CHECK1-NEXT: br label [[COND_END:%.*]] 1216 // CHECK1: cond.false: 1217 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1218 // CHECK1-NEXT: br label [[COND_END]] 1219 // CHECK1: cond.end: 1220 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1221 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1222 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1223 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1224 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1225 // CHECK1: omp.inner.for.cond: 1226 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]] 1227 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]] 1228 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1229 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1230 // CHECK1: omp.inner.for.body: 1231 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] 1232 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1233 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1234 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] 1235 // CHECK1-NEXT: invoke void @_Z3foov() 1236 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP39]] 1237 // CHECK1: invoke.cont: 1238 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1239 // CHECK1: omp.body.continue: 1240 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1241 // CHECK1: omp.inner.for.inc: 1242 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] 1243 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 1244 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] 1245 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] 1246 // CHECK1: omp.inner.for.end: 1247 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1248 // CHECK1: omp.loop.exit: 1249 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 1250 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1251 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 1252 // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1253 // CHECK1: .omp.final.then: 1254 // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 1255 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1256 // CHECK1: .omp.final.done: 1257 // CHECK1-NEXT: ret void 1258 // CHECK1: terminate.lpad: 1259 // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } 1260 // CHECK1-NEXT: catch ptr null 1261 // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 1262 // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP39]] 1263 // CHECK1-NEXT: unreachable 1264 // 1265 // 1266 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40 1267 // CHECK1-SAME: () #[[ATTR3]] personality ptr @__gxx_personality_v0 { 1268 // CHECK1-NEXT: entry: 1269 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1270 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 1271 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1272 // CHECK1-NEXT: invoke void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) 1273 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 1274 // CHECK1: invoke.cont: 1275 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 1276 // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] 1277 // CHECK1-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 1278 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 1279 // CHECK1-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 1280 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 1281 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined, i64 [[TMP1]]) 1282 // CHECK1-NEXT: ret void 1283 // CHECK1: terminate.lpad: 1284 // CHECK1-NEXT: [[TMP2:%.*]] = landingpad { ptr, i32 } 1285 // CHECK1-NEXT: catch ptr null 1286 // CHECK1-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0 1287 // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP3]]) #[[ATTR7]] 1288 // CHECK1-NEXT: unreachable 1289 // 1290 // 1291 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined 1292 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 1293 // CHECK1-NEXT: entry: 1294 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1295 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1296 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1297 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1298 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1299 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1300 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1301 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1302 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1303 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1304 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1305 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1306 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 1307 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1308 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 1309 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1310 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1311 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1312 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1313 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1314 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1315 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 1316 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1317 // CHECK1: cond.true: 1318 // CHECK1-NEXT: br label [[COND_END:%.*]] 1319 // CHECK1: cond.false: 1320 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1321 // CHECK1-NEXT: br label [[COND_END]] 1322 // CHECK1: cond.end: 1323 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1324 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1325 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1326 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1327 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1328 // CHECK1: omp.inner.for.cond: 1329 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42:![0-9]+]] 1330 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] 1331 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1332 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1333 // CHECK1: omp.inner.for.body: 1334 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !llvm.access.group [[ACC_GRP42]] 1335 // CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 1336 // CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP42]] 1337 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP42]] 1338 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 1339 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] 1340 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 1341 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined.omp_outlined, i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group [[ACC_GRP42]] 1342 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1343 // CHECK1: omp.inner.for.inc: 1344 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] 1345 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP42]] 1346 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 1347 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] 1348 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] 1349 // CHECK1: omp.inner.for.end: 1350 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1351 // CHECK1: omp.loop.exit: 1352 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1353 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1354 // CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 1355 // CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1356 // CHECK1: .omp.final.then: 1357 // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 1358 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1359 // CHECK1: .omp.final.done: 1360 // CHECK1-NEXT: ret void 1361 // 1362 // 1363 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined.omp_outlined 1364 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 1365 // CHECK1-NEXT: entry: 1366 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1367 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1368 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1369 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1370 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1371 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1372 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1373 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1374 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1375 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1376 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1377 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1378 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1379 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1380 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1381 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1382 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 1383 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1384 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 1385 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1386 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 1387 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1388 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 1389 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1390 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1391 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1392 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1393 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1394 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1395 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 1396 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1397 // CHECK1: cond.true: 1398 // CHECK1-NEXT: br label [[COND_END:%.*]] 1399 // CHECK1: cond.false: 1400 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1401 // CHECK1-NEXT: br label [[COND_END]] 1402 // CHECK1: cond.end: 1403 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1404 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1405 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1406 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1407 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1408 // CHECK1: omp.inner.for.cond: 1409 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]] 1410 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]] 1411 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1412 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1413 // CHECK1: omp.inner.for.body: 1414 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] 1415 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1416 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1417 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] 1418 // CHECK1-NEXT: invoke void @_Z3foov() 1419 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP45]] 1420 // CHECK1: invoke.cont: 1421 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1422 // CHECK1: omp.body.continue: 1423 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1424 // CHECK1: omp.inner.for.inc: 1425 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] 1426 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 1427 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] 1428 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] 1429 // CHECK1: omp.inner.for.end: 1430 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1431 // CHECK1: omp.loop.exit: 1432 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 1433 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1434 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 1435 // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1436 // CHECK1: .omp.final.then: 1437 // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 1438 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1439 // CHECK1: .omp.final.done: 1440 // CHECK1-NEXT: ret void 1441 // CHECK1: terminate.lpad: 1442 // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } 1443 // CHECK1-NEXT: catch ptr null 1444 // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 1445 // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP45]] 1446 // CHECK1-NEXT: unreachable 1447 // 1448 // 1449 // CHECK3-LABEL: define {{[^@]+}}@main 1450 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__gxx_personality_v0 { 1451 // CHECK3-NEXT: entry: 1452 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1453 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 1454 // CHECK3-NEXT: [[A:%.*]] = alloca i8, align 1 1455 // CHECK3-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 1456 // CHECK3-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 1457 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1458 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1459 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1460 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1461 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1462 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1463 // CHECK3-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 1464 // CHECK3-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 1465 // CHECK3-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 1466 // CHECK3-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 1467 // CHECK3-NEXT: [[I7:%.*]] = alloca i32, align 4 1468 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1469 // CHECK3-NEXT: call void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[S]], i64 noundef 0) 1470 // CHECK3-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) 1471 // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] 1472 // CHECK3: invoke.cont: 1473 // CHECK3-NEXT: store i8 [[CALL]], ptr [[A]], align 1 1474 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1475 // CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 1476 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1477 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 1478 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1479 // CHECK3: omp.inner.for.cond: 1480 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 1481 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 1482 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1483 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1484 // CHECK3: omp.inner.for.body: 1485 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1486 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1487 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1488 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1489 // CHECK3-NEXT: invoke void @_Z3foov() 1490 // CHECK3-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP2]] 1491 // CHECK3: invoke.cont1: 1492 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1493 // CHECK3: omp.body.continue: 1494 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1495 // CHECK3: omp.inner.for.inc: 1496 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1497 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1 1498 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1499 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1500 // CHECK3: lpad: 1501 // CHECK3-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } 1502 // CHECK3-NEXT: cleanup 1503 // CHECK3-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0 1504 // CHECK3-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8 1505 // CHECK3-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1 1506 // CHECK3-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4 1507 // CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5:[0-9]+]] 1508 // CHECK3-NEXT: br label [[EH_RESUME:%.*]] 1509 // CHECK3: omp.inner.for.end: 1510 // CHECK3-NEXT: store i32 100, ptr [[I]], align 4 1511 // CHECK3-NEXT: [[TMP8:%.*]] = load i8, ptr [[A]], align 1 1512 // CHECK3-NEXT: store i8 [[TMP8]], ptr [[DOTCAPTURE_EXPR_]], align 1 1513 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 4 1514 // CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB5]], align 4 1515 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 4 1516 // CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV6]], align 4 1517 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]] 1518 // CHECK3: omp.inner.for.cond8: 1519 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 1520 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP6]] 1521 // CHECK3-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 1522 // CHECK3-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END17:%.*]] 1523 // CHECK3: omp.inner.for.body10: 1524 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 1525 // CHECK3-NEXT: [[MUL11:%.*]] = mul nsw i32 [[TMP12]], 1 1526 // CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL11]] 1527 // CHECK3-NEXT: store i32 [[ADD12]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP6]] 1528 // CHECK3-NEXT: invoke void @_Z3foov() 1529 // CHECK3-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[TERMINATE_LPAD]], !llvm.access.group [[ACC_GRP6]] 1530 // CHECK3: invoke.cont13: 1531 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]] 1532 // CHECK3: omp.body.continue14: 1533 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC15:%.*]] 1534 // CHECK3: omp.inner.for.inc15: 1535 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 1536 // CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP13]], 1 1537 // CHECK3-NEXT: store i32 [[ADD16]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 1538 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP7:![0-9]+]] 1539 // CHECK3: omp.inner.for.end17: 1540 // CHECK3-NEXT: store i32 100, ptr [[I7]], align 4 1541 // CHECK3-NEXT: [[TMP14:%.*]] = load i8, ptr [[A]], align 1 1542 // CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP14]] to i32 1543 // CHECK3-NEXT: [[CALL19:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() 1544 // CHECK3-NEXT: to label [[INVOKE_CONT18:%.*]] unwind label [[LPAD]] 1545 // CHECK3: invoke.cont18: 1546 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV]], [[CALL19]] 1547 // CHECK3-NEXT: [[CALL22:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() 1548 // CHECK3-NEXT: to label [[INVOKE_CONT21:%.*]] unwind label [[LPAD]] 1549 // CHECK3: invoke.cont21: 1550 // CHECK3-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD20]], [[CALL22]] 1551 // CHECK3-NEXT: store i32 [[ADD23]], ptr [[RETVAL]], align 4 1552 // CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5]] 1553 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[RETVAL]], align 4 1554 // CHECK3-NEXT: ret i32 [[TMP15]] 1555 // CHECK3: eh.resume: 1556 // CHECK3-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 1557 // CHECK3-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 1558 // CHECK3-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 1559 // CHECK3-NEXT: [[LPAD_VAL24:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 1560 // CHECK3-NEXT: resume { ptr, i32 } [[LPAD_VAL24]] 1561 // CHECK3: terminate.lpad: 1562 // CHECK3-NEXT: [[TMP16:%.*]] = landingpad { ptr, i32 } 1563 // CHECK3-NEXT: catch ptr null 1564 // CHECK3-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP16]], 0 1565 // CHECK3-NEXT: call void @__clang_call_terminate(ptr [[TMP17]]) #[[ATTR6:[0-9]+]], !llvm.access.group [[ACC_GRP2]] 1566 // CHECK3-NEXT: unreachable 1567 // 1568 // 1569 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1El 1570 // CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 1571 // CHECK3-NEXT: entry: 1572 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1573 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1574 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1575 // CHECK3-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1576 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1577 // CHECK3-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 1578 // CHECK3-NEXT: call void @_ZN1SC2El(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]]) 1579 // CHECK3-NEXT: ret void 1580 // 1581 // 1582 // CHECK3-LABEL: define {{[^@]+}}@_ZN1ScvcEv 1583 // CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat { 1584 // CHECK3-NEXT: entry: 1585 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1586 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1587 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1588 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1589 // CHECK3-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 1590 // CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 1591 // CHECK3-NEXT: ret i8 [[CONV]] 1592 // 1593 // 1594 // CHECK3-LABEL: define {{[^@]+}}@__clang_call_terminate 1595 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { 1596 // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR5]] 1597 // CHECK3-NEXT: call void @_ZSt9terminatev() #[[ATTR6]] 1598 // CHECK3-NEXT: unreachable 1599 // 1600 // 1601 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv 1602 // CHECK3-SAME: () #[[ATTR2]] comdat personality ptr @__gxx_personality_v0 { 1603 // CHECK3-NEXT: entry: 1604 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1605 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1606 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1607 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1608 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1609 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 1610 // CHECK3-NEXT: [[DOTOMP_LB3:%.*]] = alloca i32, align 4 1611 // CHECK3-NEXT: [[DOTOMP_UB4:%.*]] = alloca i32, align 4 1612 // CHECK3-NEXT: [[DOTOMP_IV5:%.*]] = alloca i32, align 4 1613 // CHECK3-NEXT: [[I6:%.*]] = alloca i32, align 4 1614 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1615 // CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 1616 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1617 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 1618 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1619 // CHECK3: omp.inner.for.cond: 1620 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] 1621 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 1622 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1623 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1624 // CHECK3: omp.inner.for.body: 1625 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 1626 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1627 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1628 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 1629 // CHECK3-NEXT: invoke void @_Z3foov() 1630 // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP9]] 1631 // CHECK3: invoke.cont: 1632 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1633 // CHECK3: omp.body.continue: 1634 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1635 // CHECK3: omp.inner.for.inc: 1636 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 1637 // CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 1638 // CHECK3-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 1639 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 1640 // CHECK3: omp.inner.for.end: 1641 // CHECK3-NEXT: store i32 100, ptr [[I]], align 4 1642 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB3]], align 4 1643 // CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB4]], align 4 1644 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB3]], align 4 1645 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV5]], align 4 1646 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] 1647 // CHECK3: omp.inner.for.cond7: 1648 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 1649 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB4]], align 4, !llvm.access.group [[ACC_GRP12]] 1650 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1651 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END16:%.*]] 1652 // CHECK3: omp.inner.for.body9: 1653 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP12]] 1654 // CHECK3-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 1655 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] 1656 // CHECK3-NEXT: store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP12]] 1657 // CHECK3-NEXT: invoke void @_Z3foov() 1658 // CHECK3-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[TERMINATE_LPAD]], !llvm.access.group [[ACC_GRP12]] 1659 // CHECK3: invoke.cont12: 1660 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE13:%.*]] 1661 // CHECK3: omp.body.continue13: 1662 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC14:%.*]] 1663 // CHECK3: omp.inner.for.inc14: 1664 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP12]] 1665 // CHECK3-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP9]], 1 1666 // CHECK3-NEXT: store i32 [[ADD15]], ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP12]] 1667 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP13:![0-9]+]] 1668 // CHECK3: omp.inner.for.end16: 1669 // CHECK3-NEXT: store i32 100, ptr [[I6]], align 4 1670 // CHECK3-NEXT: ret i32 0 1671 // CHECK3: terminate.lpad: 1672 // CHECK3-NEXT: [[TMP10:%.*]] = landingpad { ptr, i32 } 1673 // CHECK3-NEXT: catch ptr null 1674 // CHECK3-NEXT: [[TMP11:%.*]] = extractvalue { ptr, i32 } [[TMP10]], 0 1675 // CHECK3-NEXT: call void @__clang_call_terminate(ptr [[TMP11]]) #[[ATTR6]], !llvm.access.group [[ACC_GRP9]] 1676 // CHECK3-NEXT: unreachable 1677 // 1678 // 1679 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv 1680 // CHECK3-SAME: () #[[ATTR2]] comdat personality ptr @__gxx_personality_v0 { 1681 // CHECK3-NEXT: entry: 1682 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1683 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1684 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1685 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1686 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1687 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1688 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 1689 // CHECK3-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 1690 // CHECK3-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 1691 // CHECK3-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 1692 // CHECK3-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 1693 // CHECK3-NEXT: [[I7:%.*]] = alloca i32, align 4 1694 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1695 // CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 1696 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1697 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 1698 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1699 // CHECK3: omp.inner.for.cond: 1700 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] 1701 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 1702 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1703 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1704 // CHECK3: omp.inner.for.body: 1705 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 1706 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1707 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1708 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] 1709 // CHECK3-NEXT: invoke void @_Z3foov() 1710 // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP15]] 1711 // CHECK3: invoke.cont: 1712 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1713 // CHECK3: omp.body.continue: 1714 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1715 // CHECK3: omp.inner.for.inc: 1716 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 1717 // CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 1718 // CHECK3-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 1719 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 1720 // CHECK3: omp.inner.for.end: 1721 // CHECK3-NEXT: store i32 100, ptr [[I]], align 4 1722 // CHECK3-NEXT: invoke void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) 1723 // CHECK3-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]] 1724 // CHECK3: invoke.cont2: 1725 // CHECK3-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 1726 // CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR5]] 1727 // CHECK3-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 1728 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 4 1729 // CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB5]], align 4 1730 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 4 1731 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV6]], align 4 1732 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]] 1733 // CHECK3: omp.inner.for.cond8: 1734 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] 1735 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP18]] 1736 // CHECK3-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1737 // CHECK3-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END17:%.*]] 1738 // CHECK3: omp.inner.for.body10: 1739 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP18]] 1740 // CHECK3-NEXT: [[MUL11:%.*]] = mul nsw i32 [[TMP8]], 1 1741 // CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL11]] 1742 // CHECK3-NEXT: store i32 [[ADD12]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP18]] 1743 // CHECK3-NEXT: invoke void @_Z3foov() 1744 // CHECK3-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[TERMINATE_LPAD]], !llvm.access.group [[ACC_GRP18]] 1745 // CHECK3: invoke.cont13: 1746 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]] 1747 // CHECK3: omp.body.continue14: 1748 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC15:%.*]] 1749 // CHECK3: omp.inner.for.inc15: 1750 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP18]] 1751 // CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP9]], 1 1752 // CHECK3-NEXT: store i32 [[ADD16]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP18]] 1753 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP19:![0-9]+]] 1754 // CHECK3: omp.inner.for.end17: 1755 // CHECK3-NEXT: store i32 100, ptr [[I7]], align 4 1756 // CHECK3-NEXT: ret i32 0 1757 // CHECK3: terminate.lpad: 1758 // CHECK3-NEXT: [[TMP10:%.*]] = landingpad { ptr, i32 } 1759 // CHECK3-NEXT: catch ptr null 1760 // CHECK3-NEXT: [[TMP11:%.*]] = extractvalue { ptr, i32 } [[TMP10]], 0 1761 // CHECK3-NEXT: call void @__clang_call_terminate(ptr [[TMP11]]) #[[ATTR6]], !llvm.access.group [[ACC_GRP15]] 1762 // CHECK3-NEXT: unreachable 1763 // 1764 // 1765 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev 1766 // CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 1767 // CHECK3-NEXT: entry: 1768 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1769 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1770 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1771 // CHECK3-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR5]] 1772 // CHECK3-NEXT: ret void 1773 // 1774 // 1775 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2El 1776 // CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat { 1777 // CHECK3-NEXT: entry: 1778 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1779 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1780 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1781 // CHECK3-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1782 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1783 // CHECK3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1784 // CHECK3-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 1785 // CHECK3-NEXT: store i64 [[TMP0]], ptr [[A2]], align 8 1786 // CHECK3-NEXT: ret void 1787 // 1788 // 1789 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev 1790 // CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 1791 // CHECK3-NEXT: entry: 1792 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1793 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1794 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1795 // CHECK3-NEXT: ret void 1796 // 1797 // 1798 // CHECK5-LABEL: define {{[^@]+}}@main 1799 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__gxx_personality_v0 { 1800 // CHECK5-NEXT: entry: 1801 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1802 // CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 1803 // CHECK5-NEXT: [[A:%.*]] = alloca i8, align 1 1804 // CHECK5-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 1805 // CHECK5-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 1806 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1807 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1808 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1809 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 1810 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 1811 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 1812 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1813 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1814 // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 1815 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 1816 // CHECK5-NEXT: call void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[S]], i64 noundef 0) 1817 // CHECK5-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) 1818 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] 1819 // CHECK5: invoke.cont: 1820 // CHECK5-NEXT: store i8 [[CALL]], ptr [[A]], align 1 1821 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1822 // CHECK5-NEXT: store i32 3, ptr [[TMP0]], align 4 1823 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1824 // CHECK5-NEXT: store i32 0, ptr [[TMP1]], align 4 1825 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1826 // CHECK5-NEXT: store ptr null, ptr [[TMP2]], align 8 1827 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1828 // CHECK5-NEXT: store ptr null, ptr [[TMP3]], align 8 1829 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1830 // CHECK5-NEXT: store ptr null, ptr [[TMP4]], align 8 1831 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1832 // CHECK5-NEXT: store ptr null, ptr [[TMP5]], align 8 1833 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1834 // CHECK5-NEXT: store ptr null, ptr [[TMP6]], align 8 1835 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1836 // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 1837 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1838 // CHECK5-NEXT: store i64 100, ptr [[TMP8]], align 8 1839 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1840 // CHECK5-NEXT: store i64 0, ptr [[TMP9]], align 8 1841 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1842 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 1843 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1844 // CHECK5-NEXT: store [3 x i32] [i32 2, i32 0, i32 0], ptr [[TMP11]], align 4 1845 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1846 // CHECK5-NEXT: store i32 0, ptr [[TMP12]], align 4 1847 // CHECK5-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 2, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.region_id, ptr [[KERNEL_ARGS]]) 1848 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1849 // CHECK5-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1850 // CHECK5: omp_offload.failed: 1851 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50() #[[ATTR4:[0-9]+]] 1852 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 1853 // CHECK5: lpad: 1854 // CHECK5-NEXT: [[TMP15:%.*]] = landingpad { ptr, i32 } 1855 // CHECK5-NEXT: cleanup 1856 // CHECK5-NEXT: [[TMP16:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 0 1857 // CHECK5-NEXT: store ptr [[TMP16]], ptr [[EXN_SLOT]], align 8 1858 // CHECK5-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 1 1859 // CHECK5-NEXT: store i32 [[TMP17]], ptr [[EHSELECTOR_SLOT]], align 4 1860 // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR4]] 1861 // CHECK5-NEXT: br label [[EH_RESUME:%.*]] 1862 // CHECK5: omp_offload.cont: 1863 // CHECK5-NEXT: [[TMP18:%.*]] = load i8, ptr [[A]], align 1 1864 // CHECK5-NEXT: store i8 [[TMP18]], ptr [[A_CASTED]], align 1 1865 // CHECK5-NEXT: [[TMP19:%.*]] = load i64, ptr [[A_CASTED]], align 8 1866 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1867 // CHECK5-NEXT: store i64 [[TMP19]], ptr [[TMP20]], align 8 1868 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1869 // CHECK5-NEXT: store i64 [[TMP19]], ptr [[TMP21]], align 8 1870 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1871 // CHECK5-NEXT: store ptr null, ptr [[TMP22]], align 8 1872 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1873 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1874 // CHECK5-NEXT: [[TMP25:%.*]] = load i8, ptr [[A]], align 1 1875 // CHECK5-NEXT: store i8 [[TMP25]], ptr [[DOTCAPTURE_EXPR_]], align 1 1876 // CHECK5-NEXT: [[TMP26:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 1877 // CHECK5-NEXT: [[TMP27:%.*]] = zext i8 [[TMP26]] to i32 1878 // CHECK5-NEXT: [[TMP28:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP27]], 0 1879 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 1880 // CHECK5-NEXT: store i32 3, ptr [[TMP29]], align 4 1881 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 1882 // CHECK5-NEXT: store i32 1, ptr [[TMP30]], align 4 1883 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 1884 // CHECK5-NEXT: store ptr [[TMP23]], ptr [[TMP31]], align 8 1885 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3 1886 // CHECK5-NEXT: store ptr [[TMP24]], ptr [[TMP32]], align 8 1887 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4 1888 // CHECK5-NEXT: store ptr @.offload_sizes, ptr [[TMP33]], align 8 1889 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5 1890 // CHECK5-NEXT: store ptr @.offload_maptypes, ptr [[TMP34]], align 8 1891 // CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6 1892 // CHECK5-NEXT: store ptr null, ptr [[TMP35]], align 8 1893 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 1894 // CHECK5-NEXT: store ptr null, ptr [[TMP36]], align 8 1895 // CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 1896 // CHECK5-NEXT: store i64 100, ptr [[TMP37]], align 8 1897 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9 1898 // CHECK5-NEXT: store i64 0, ptr [[TMP38]], align 8 1899 // CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10 1900 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 4 1901 // CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11 1902 // CHECK5-NEXT: store [3 x i32] [[TMP28]], ptr [[TMP40]], align 4 1903 // CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12 1904 // CHECK5-NEXT: store i32 0, ptr [[TMP41]], align 4 1905 // CHECK5-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 [[TMP27]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.region_id, ptr [[KERNEL_ARGS2]]) 1906 // CHECK5-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 1907 // CHECK5-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 1908 // CHECK5: omp_offload.failed3: 1909 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55(i64 [[TMP19]]) #[[ATTR4]] 1910 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]] 1911 // CHECK5: omp_offload.cont4: 1912 // CHECK5-NEXT: [[TMP44:%.*]] = load i8, ptr [[A]], align 1 1913 // CHECK5-NEXT: [[CONV:%.*]] = sext i8 [[TMP44]] to i32 1914 // CHECK5-NEXT: [[CALL6:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() 1915 // CHECK5-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] 1916 // CHECK5: invoke.cont5: 1917 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL6]] 1918 // CHECK5-NEXT: [[CALL8:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() 1919 // CHECK5-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] 1920 // CHECK5: invoke.cont7: 1921 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] 1922 // CHECK5-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 1923 // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR4]] 1924 // CHECK5-NEXT: [[TMP45:%.*]] = load i32, ptr [[RETVAL]], align 4 1925 // CHECK5-NEXT: ret i32 [[TMP45]] 1926 // CHECK5: eh.resume: 1927 // CHECK5-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 1928 // CHECK5-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 1929 // CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 1930 // CHECK5-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 1931 // CHECK5-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] 1932 // 1933 // 1934 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC1El 1935 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 1936 // CHECK5-NEXT: entry: 1937 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1938 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1939 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1940 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1941 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1942 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 1943 // CHECK5-NEXT: call void @_ZN1SC2El(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]]) 1944 // CHECK5-NEXT: ret void 1945 // 1946 // 1947 // CHECK5-LABEL: define {{[^@]+}}@_ZN1ScvcEv 1948 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat { 1949 // CHECK5-NEXT: entry: 1950 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1951 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1952 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1953 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1954 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 1955 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 1956 // CHECK5-NEXT: ret i8 [[CONV]] 1957 // 1958 // 1959 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50 1960 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 1961 // CHECK5-NEXT: entry: 1962 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined) 1963 // CHECK5-NEXT: ret void 1964 // 1965 // 1966 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined 1967 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 1968 // CHECK5-NEXT: entry: 1969 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1970 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1971 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1972 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1973 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1974 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1975 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1976 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1977 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1978 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1979 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1980 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1981 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 1982 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1983 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1984 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1985 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1986 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1987 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1988 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 1989 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1990 // CHECK5: cond.true: 1991 // CHECK5-NEXT: br label [[COND_END:%.*]] 1992 // CHECK5: cond.false: 1993 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1994 // CHECK5-NEXT: br label [[COND_END]] 1995 // CHECK5: cond.end: 1996 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1997 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1998 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1999 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2000 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2001 // CHECK5: omp.inner.for.cond: 2002 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] 2003 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 2004 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2005 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2006 // CHECK5: omp.inner.for.body: 2007 // CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group [[ACC_GRP9]] 2008 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP9]] 2009 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 2010 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 2011 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 2012 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP9]] 2013 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2014 // CHECK5: omp.inner.for.inc: 2015 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 2016 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP9]] 2017 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 2018 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 2019 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 2020 // CHECK5: omp.inner.for.end: 2021 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2022 // CHECK5: omp.loop.exit: 2023 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2024 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2025 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 2026 // CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2027 // CHECK5: .omp.final.then: 2028 // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 2029 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2030 // CHECK5: .omp.final.done: 2031 // CHECK5-NEXT: ret void 2032 // 2033 // 2034 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined.omp_outlined 2035 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 2036 // CHECK5-NEXT: entry: 2037 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2038 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2039 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 2040 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 2041 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2042 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2043 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2044 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2045 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2046 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2047 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2048 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2049 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2050 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2051 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2052 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2053 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 2054 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2055 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 2056 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2057 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 2058 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 2059 // CHECK5-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 2060 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2061 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2062 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2063 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 2064 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2065 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2066 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 2067 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2068 // CHECK5: cond.true: 2069 // CHECK5-NEXT: br label [[COND_END:%.*]] 2070 // CHECK5: cond.false: 2071 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2072 // CHECK5-NEXT: br label [[COND_END]] 2073 // CHECK5: cond.end: 2074 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2075 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2076 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2077 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 2078 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2079 // CHECK5: omp.inner.for.cond: 2080 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] 2081 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] 2082 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2083 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2084 // CHECK5: omp.inner.for.body: 2085 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] 2086 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 2087 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2088 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] 2089 // CHECK5-NEXT: invoke void @_Z3foov() 2090 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP13]] 2091 // CHECK5: invoke.cont: 2092 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2093 // CHECK5: omp.body.continue: 2094 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2095 // CHECK5: omp.inner.for.inc: 2096 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] 2097 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 2098 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] 2099 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 2100 // CHECK5: omp.inner.for.end: 2101 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2102 // CHECK5: omp.loop.exit: 2103 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 2104 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2105 // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 2106 // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2107 // CHECK5: .omp.final.then: 2108 // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 2109 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2110 // CHECK5: .omp.final.done: 2111 // CHECK5-NEXT: ret void 2112 // CHECK5: terminate.lpad: 2113 // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } 2114 // CHECK5-NEXT: catch ptr null 2115 // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 2116 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7:[0-9]+]], !llvm.access.group [[ACC_GRP13]] 2117 // CHECK5-NEXT: unreachable 2118 // 2119 // 2120 // CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate 2121 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat { 2122 // CHECK5-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR4]] 2123 // CHECK5-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] 2124 // CHECK5-NEXT: unreachable 2125 // 2126 // 2127 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 2128 // CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { 2129 // CHECK5-NEXT: entry: 2130 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2131 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2132 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 2133 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 2134 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, ptr [[A_ADDR]], align 1 2135 // CHECK5-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 1 2136 // CHECK5-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 2137 // CHECK5-NEXT: store i8 [[TMP1]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 2138 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 2139 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined, i64 [[TMP2]]) 2140 // CHECK5-NEXT: ret void 2141 // 2142 // 2143 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined 2144 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 2145 // CHECK5-NEXT: entry: 2146 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2147 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2148 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2149 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2150 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2151 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2152 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2153 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2154 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2155 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2156 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2157 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2158 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 2159 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 2160 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 2161 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2162 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2163 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2164 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2165 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2166 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2167 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 2168 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2169 // CHECK5: cond.true: 2170 // CHECK5-NEXT: br label [[COND_END:%.*]] 2171 // CHECK5: cond.false: 2172 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2173 // CHECK5-NEXT: br label [[COND_END]] 2174 // CHECK5: cond.end: 2175 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2176 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2177 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2178 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2179 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2180 // CHECK5: omp.inner.for.cond: 2181 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] 2182 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]] 2183 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2184 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2185 // CHECK5: omp.inner.for.body: 2186 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !llvm.access.group [[ACC_GRP18]] 2187 // CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 2188 // CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP18]] 2189 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP18]] 2190 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 2191 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]] 2192 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 2193 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined.omp_outlined, i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group [[ACC_GRP18]] 2194 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2195 // CHECK5: omp.inner.for.inc: 2196 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 2197 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP18]] 2198 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 2199 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 2200 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 2201 // CHECK5: omp.inner.for.end: 2202 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2203 // CHECK5: omp.loop.exit: 2204 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2205 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2206 // CHECK5-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 2207 // CHECK5-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2208 // CHECK5: .omp.final.then: 2209 // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 2210 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2211 // CHECK5: .omp.final.done: 2212 // CHECK5-NEXT: ret void 2213 // 2214 // 2215 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined.omp_outlined 2216 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 2217 // CHECK5-NEXT: entry: 2218 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2219 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2220 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 2221 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 2222 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2223 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2224 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2225 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2226 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2227 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2228 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2229 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2230 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2231 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2232 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2233 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2234 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 2235 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2236 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 2237 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2238 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 2239 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 2240 // CHECK5-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 2241 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2242 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2243 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2244 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 2245 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2246 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2247 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 2248 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2249 // CHECK5: cond.true: 2250 // CHECK5-NEXT: br label [[COND_END:%.*]] 2251 // CHECK5: cond.false: 2252 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2253 // CHECK5-NEXT: br label [[COND_END]] 2254 // CHECK5: cond.end: 2255 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2256 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2257 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2258 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 2259 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2260 // CHECK5: omp.inner.for.cond: 2261 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] 2262 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] 2263 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2264 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2265 // CHECK5: omp.inner.for.body: 2266 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 2267 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 2268 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2269 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] 2270 // CHECK5-NEXT: invoke void @_Z3foov() 2271 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP21]] 2272 // CHECK5: invoke.cont: 2273 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2274 // CHECK5: omp.body.continue: 2275 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2276 // CHECK5: omp.inner.for.inc: 2277 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 2278 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 2279 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 2280 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 2281 // CHECK5: omp.inner.for.end: 2282 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2283 // CHECK5: omp.loop.exit: 2284 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 2285 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2286 // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 2287 // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2288 // CHECK5: .omp.final.then: 2289 // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 2290 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2291 // CHECK5: .omp.final.done: 2292 // CHECK5-NEXT: ret void 2293 // CHECK5: terminate.lpad: 2294 // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } 2295 // CHECK5-NEXT: catch ptr null 2296 // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 2297 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP21]] 2298 // CHECK5-NEXT: unreachable 2299 // 2300 // 2301 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv 2302 // CHECK5-SAME: () #[[ATTR2]] comdat { 2303 // CHECK5-NEXT: entry: 2304 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2305 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2306 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2307 // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 2308 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2309 // CHECK5-NEXT: store i32 3, ptr [[TMP0]], align 4 2310 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2311 // CHECK5-NEXT: store i32 0, ptr [[TMP1]], align 4 2312 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2313 // CHECK5-NEXT: store ptr null, ptr [[TMP2]], align 8 2314 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2315 // CHECK5-NEXT: store ptr null, ptr [[TMP3]], align 8 2316 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2317 // CHECK5-NEXT: store ptr null, ptr [[TMP4]], align 8 2318 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2319 // CHECK5-NEXT: store ptr null, ptr [[TMP5]], align 8 2320 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 2321 // CHECK5-NEXT: store ptr null, ptr [[TMP6]], align 8 2322 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 2323 // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 2324 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 2325 // CHECK5-NEXT: store i64 100, ptr [[TMP8]], align 8 2326 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 2327 // CHECK5-NEXT: store i64 0, ptr [[TMP9]], align 8 2328 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 2329 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 2330 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 2331 // CHECK5-NEXT: store [3 x i32] [i32 5, i32 0, i32 0], ptr [[TMP11]], align 4 2332 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 2333 // CHECK5-NEXT: store i32 0, ptr [[TMP12]], align 4 2334 // CHECK5-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 5, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.region_id, ptr [[KERNEL_ARGS]]) 2335 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 2336 // CHECK5-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2337 // CHECK5: omp_offload.failed: 2338 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36() #[[ATTR4]] 2339 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 2340 // CHECK5: omp_offload.cont: 2341 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 2342 // CHECK5-NEXT: store i32 3, ptr [[TMP15]], align 4 2343 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 2344 // CHECK5-NEXT: store i32 0, ptr [[TMP16]], align 4 2345 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 2346 // CHECK5-NEXT: store ptr null, ptr [[TMP17]], align 8 2347 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3 2348 // CHECK5-NEXT: store ptr null, ptr [[TMP18]], align 8 2349 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4 2350 // CHECK5-NEXT: store ptr null, ptr [[TMP19]], align 8 2351 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5 2352 // CHECK5-NEXT: store ptr null, ptr [[TMP20]], align 8 2353 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6 2354 // CHECK5-NEXT: store ptr null, ptr [[TMP21]], align 8 2355 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 2356 // CHECK5-NEXT: store ptr null, ptr [[TMP22]], align 8 2357 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 2358 // CHECK5-NEXT: store i64 100, ptr [[TMP23]], align 8 2359 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9 2360 // CHECK5-NEXT: store i64 0, ptr [[TMP24]], align 8 2361 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10 2362 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4 2363 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11 2364 // CHECK5-NEXT: store [3 x i32] [i32 23, i32 0, i32 0], ptr [[TMP26]], align 4 2365 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12 2366 // CHECK5-NEXT: store i32 0, ptr [[TMP27]], align 4 2367 // CHECK5-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 23, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.region_id, ptr [[KERNEL_ARGS2]]) 2368 // CHECK5-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 2369 // CHECK5-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 2370 // CHECK5: omp_offload.failed3: 2371 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40() #[[ATTR4]] 2372 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]] 2373 // CHECK5: omp_offload.cont4: 2374 // CHECK5-NEXT: ret i32 0 2375 // 2376 // 2377 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv 2378 // CHECK5-SAME: () #[[ATTR2]] comdat personality ptr @__gxx_personality_v0 { 2379 // CHECK5-NEXT: entry: 2380 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2381 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2382 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2383 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 2384 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2385 // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 2386 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2387 // CHECK5-NEXT: store i32 3, ptr [[TMP0]], align 4 2388 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2389 // CHECK5-NEXT: store i32 0, ptr [[TMP1]], align 4 2390 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2391 // CHECK5-NEXT: store ptr null, ptr [[TMP2]], align 8 2392 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2393 // CHECK5-NEXT: store ptr null, ptr [[TMP3]], align 8 2394 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2395 // CHECK5-NEXT: store ptr null, ptr [[TMP4]], align 8 2396 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2397 // CHECK5-NEXT: store ptr null, ptr [[TMP5]], align 8 2398 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 2399 // CHECK5-NEXT: store ptr null, ptr [[TMP6]], align 8 2400 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 2401 // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 2402 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 2403 // CHECK5-NEXT: store i64 100, ptr [[TMP8]], align 8 2404 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 2405 // CHECK5-NEXT: store i64 0, ptr [[TMP9]], align 8 2406 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 2407 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 2408 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 2409 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4 2410 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 2411 // CHECK5-NEXT: store i32 0, ptr [[TMP12]], align 4 2412 // CHECK5-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.region_id, ptr [[KERNEL_ARGS]]) 2413 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 2414 // CHECK5-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2415 // CHECK5: omp_offload.failed: 2416 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR4]] 2417 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 2418 // CHECK5: omp_offload.cont: 2419 // CHECK5-NEXT: invoke void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) 2420 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 2421 // CHECK5: invoke.cont: 2422 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 2423 // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] 2424 // CHECK5-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 2425 // CHECK5-NEXT: [[TMP15:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 2426 // CHECK5-NEXT: [[TMP16:%.*]] = zext i8 [[TMP15]] to i32 2427 // CHECK5-NEXT: [[TMP17:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP16]], 0 2428 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 2429 // CHECK5-NEXT: store i32 3, ptr [[TMP18]], align 4 2430 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 2431 // CHECK5-NEXT: store i32 0, ptr [[TMP19]], align 4 2432 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 2433 // CHECK5-NEXT: store ptr null, ptr [[TMP20]], align 8 2434 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3 2435 // CHECK5-NEXT: store ptr null, ptr [[TMP21]], align 8 2436 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4 2437 // CHECK5-NEXT: store ptr null, ptr [[TMP22]], align 8 2438 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5 2439 // CHECK5-NEXT: store ptr null, ptr [[TMP23]], align 8 2440 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6 2441 // CHECK5-NEXT: store ptr null, ptr [[TMP24]], align 8 2442 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 2443 // CHECK5-NEXT: store ptr null, ptr [[TMP25]], align 8 2444 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 2445 // CHECK5-NEXT: store i64 100, ptr [[TMP26]], align 8 2446 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9 2447 // CHECK5-NEXT: store i64 0, ptr [[TMP27]], align 8 2448 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10 2449 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 2450 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11 2451 // CHECK5-NEXT: store [3 x i32] [[TMP17]], ptr [[TMP29]], align 4 2452 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12 2453 // CHECK5-NEXT: store i32 0, ptr [[TMP30]], align 4 2454 // CHECK5-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 [[TMP16]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.region_id, ptr [[KERNEL_ARGS2]]) 2455 // CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 2456 // CHECK5-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 2457 // CHECK5: omp_offload.failed3: 2458 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40() #[[ATTR4]] 2459 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]] 2460 // CHECK5: omp_offload.cont4: 2461 // CHECK5-NEXT: ret i32 0 2462 // CHECK5: terminate.lpad: 2463 // CHECK5-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 } 2464 // CHECK5-NEXT: catch ptr null 2465 // CHECK5-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0 2466 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP34]]) #[[ATTR7]] 2467 // CHECK5-NEXT: unreachable 2468 // 2469 // 2470 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev 2471 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 2472 // CHECK5-NEXT: entry: 2473 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2474 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2475 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2476 // CHECK5-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]] 2477 // CHECK5-NEXT: ret void 2478 // 2479 // 2480 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2El 2481 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat { 2482 // CHECK5-NEXT: entry: 2483 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2484 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2485 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2486 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 2487 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2488 // CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2489 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 2490 // CHECK5-NEXT: store i64 [[TMP0]], ptr [[A2]], align 8 2491 // CHECK5-NEXT: ret void 2492 // 2493 // 2494 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36 2495 // CHECK5-SAME: () #[[ATTR3]] { 2496 // CHECK5-NEXT: entry: 2497 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined) 2498 // CHECK5-NEXT: ret void 2499 // 2500 // 2501 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined 2502 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 2503 // CHECK5-NEXT: entry: 2504 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2505 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2506 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2507 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2508 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2509 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2510 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2511 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2512 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2513 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2514 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2515 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 2516 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 2517 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2518 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2519 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2520 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2521 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2522 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2523 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 2524 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2525 // CHECK5: cond.true: 2526 // CHECK5-NEXT: br label [[COND_END:%.*]] 2527 // CHECK5: cond.false: 2528 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2529 // CHECK5-NEXT: br label [[COND_END]] 2530 // CHECK5: cond.end: 2531 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2532 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2533 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2534 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2535 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2536 // CHECK5: omp.inner.for.cond: 2537 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] 2538 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] 2539 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2540 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2541 // CHECK5: omp.inner.for.body: 2542 // CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group [[ACC_GRP24]] 2543 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP24]] 2544 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 2545 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] 2546 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 2547 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP24]] 2548 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2549 // CHECK5: omp.inner.for.inc: 2550 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 2551 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP24]] 2552 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 2553 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 2554 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 2555 // CHECK5: omp.inner.for.end: 2556 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2557 // CHECK5: omp.loop.exit: 2558 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2559 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2560 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 2561 // CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2562 // CHECK5: .omp.final.then: 2563 // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 2564 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2565 // CHECK5: .omp.final.done: 2566 // CHECK5-NEXT: ret void 2567 // 2568 // 2569 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined.omp_outlined 2570 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 2571 // CHECK5-NEXT: entry: 2572 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2573 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2574 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 2575 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 2576 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2577 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2578 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2579 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2580 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2581 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2582 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2583 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2584 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2585 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2586 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2587 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2588 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 2589 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2590 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 2591 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2592 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 2593 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 2594 // CHECK5-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 2595 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2596 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2597 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2598 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 2599 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2600 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2601 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 2602 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2603 // CHECK5: cond.true: 2604 // CHECK5-NEXT: br label [[COND_END:%.*]] 2605 // CHECK5: cond.false: 2606 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2607 // CHECK5-NEXT: br label [[COND_END]] 2608 // CHECK5: cond.end: 2609 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2610 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2611 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2612 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 2613 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2614 // CHECK5: omp.inner.for.cond: 2615 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] 2616 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] 2617 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2618 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2619 // CHECK5: omp.inner.for.body: 2620 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 2621 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 2622 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2623 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] 2624 // CHECK5-NEXT: invoke void @_Z3foov() 2625 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP27]] 2626 // CHECK5: invoke.cont: 2627 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2628 // CHECK5: omp.body.continue: 2629 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2630 // CHECK5: omp.inner.for.inc: 2631 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 2632 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 2633 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 2634 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 2635 // CHECK5: omp.inner.for.end: 2636 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2637 // CHECK5: omp.loop.exit: 2638 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 2639 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2640 // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 2641 // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2642 // CHECK5: .omp.final.then: 2643 // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 2644 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2645 // CHECK5: .omp.final.done: 2646 // CHECK5-NEXT: ret void 2647 // CHECK5: terminate.lpad: 2648 // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } 2649 // CHECK5-NEXT: catch ptr null 2650 // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 2651 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP27]] 2652 // CHECK5-NEXT: unreachable 2653 // 2654 // 2655 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40 2656 // CHECK5-SAME: () #[[ATTR3]] { 2657 // CHECK5-NEXT: entry: 2658 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined) 2659 // CHECK5-NEXT: ret void 2660 // 2661 // 2662 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined 2663 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 2664 // CHECK5-NEXT: entry: 2665 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2666 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2667 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2668 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2669 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2670 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2671 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2672 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2673 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2674 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2675 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2676 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 2677 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 2678 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2679 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2680 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2681 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2682 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2683 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2684 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 2685 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2686 // CHECK5: cond.true: 2687 // CHECK5-NEXT: br label [[COND_END:%.*]] 2688 // CHECK5: cond.false: 2689 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2690 // CHECK5-NEXT: br label [[COND_END]] 2691 // CHECK5: cond.end: 2692 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2693 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2694 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2695 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2696 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2697 // CHECK5: omp.inner.for.cond: 2698 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]] 2699 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] 2700 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2701 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2702 // CHECK5: omp.inner.for.body: 2703 // CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group [[ACC_GRP30]] 2704 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP30]] 2705 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 2706 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] 2707 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 2708 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP30]] 2709 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2710 // CHECK5: omp.inner.for.inc: 2711 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] 2712 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP30]] 2713 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 2714 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] 2715 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 2716 // CHECK5: omp.inner.for.end: 2717 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2718 // CHECK5: omp.loop.exit: 2719 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2720 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2721 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 2722 // CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2723 // CHECK5: .omp.final.then: 2724 // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 2725 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2726 // CHECK5: .omp.final.done: 2727 // CHECK5-NEXT: ret void 2728 // 2729 // 2730 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined.omp_outlined 2731 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 2732 // CHECK5-NEXT: entry: 2733 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2734 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2735 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 2736 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 2737 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2738 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2739 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2740 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2741 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2742 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2743 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2744 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2745 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2746 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2747 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2748 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2749 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 2750 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2751 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 2752 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2753 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 2754 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 2755 // CHECK5-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 2756 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2757 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2758 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2759 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 2760 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2761 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2762 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 2763 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2764 // CHECK5: cond.true: 2765 // CHECK5-NEXT: br label [[COND_END:%.*]] 2766 // CHECK5: cond.false: 2767 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2768 // CHECK5-NEXT: br label [[COND_END]] 2769 // CHECK5: cond.end: 2770 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2771 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2772 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2773 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 2774 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2775 // CHECK5: omp.inner.for.cond: 2776 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] 2777 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] 2778 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2779 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2780 // CHECK5: omp.inner.for.body: 2781 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 2782 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 2783 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2784 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] 2785 // CHECK5-NEXT: invoke void @_Z3foov() 2786 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP33]] 2787 // CHECK5: invoke.cont: 2788 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2789 // CHECK5: omp.body.continue: 2790 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2791 // CHECK5: omp.inner.for.inc: 2792 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 2793 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 2794 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 2795 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 2796 // CHECK5: omp.inner.for.end: 2797 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2798 // CHECK5: omp.loop.exit: 2799 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 2800 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2801 // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 2802 // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2803 // CHECK5: .omp.final.then: 2804 // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 2805 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2806 // CHECK5: .omp.final.done: 2807 // CHECK5-NEXT: ret void 2808 // CHECK5: terminate.lpad: 2809 // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } 2810 // CHECK5-NEXT: catch ptr null 2811 // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 2812 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP33]] 2813 // CHECK5-NEXT: unreachable 2814 // 2815 // 2816 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36 2817 // CHECK5-SAME: () #[[ATTR3]] { 2818 // CHECK5-NEXT: entry: 2819 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined) 2820 // CHECK5-NEXT: ret void 2821 // 2822 // 2823 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined 2824 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 2825 // CHECK5-NEXT: entry: 2826 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2827 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2828 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2829 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2830 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2831 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2832 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2833 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2834 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2835 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2836 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2837 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 2838 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 2839 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2840 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2841 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2842 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2843 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2844 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2845 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 2846 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2847 // CHECK5: cond.true: 2848 // CHECK5-NEXT: br label [[COND_END:%.*]] 2849 // CHECK5: cond.false: 2850 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2851 // CHECK5-NEXT: br label [[COND_END]] 2852 // CHECK5: cond.end: 2853 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2854 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2855 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2856 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2857 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2858 // CHECK5: omp.inner.for.cond: 2859 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] 2860 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] 2861 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2862 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2863 // CHECK5: omp.inner.for.body: 2864 // CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group [[ACC_GRP36]] 2865 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP36]] 2866 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 2867 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] 2868 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 2869 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP36]] 2870 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2871 // CHECK5: omp.inner.for.inc: 2872 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 2873 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP36]] 2874 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 2875 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 2876 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] 2877 // CHECK5: omp.inner.for.end: 2878 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2879 // CHECK5: omp.loop.exit: 2880 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2881 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2882 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 2883 // CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2884 // CHECK5: .omp.final.then: 2885 // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 2886 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2887 // CHECK5: .omp.final.done: 2888 // CHECK5-NEXT: ret void 2889 // 2890 // 2891 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined.omp_outlined 2892 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 2893 // CHECK5-NEXT: entry: 2894 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2895 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2896 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 2897 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 2898 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2899 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2900 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2901 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2902 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2903 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2904 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2905 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2906 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2907 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2908 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2909 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2910 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 2911 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2912 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 2913 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2914 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 2915 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 2916 // CHECK5-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 2917 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2918 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2919 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2920 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 2921 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2922 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2923 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 2924 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2925 // CHECK5: cond.true: 2926 // CHECK5-NEXT: br label [[COND_END:%.*]] 2927 // CHECK5: cond.false: 2928 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2929 // CHECK5-NEXT: br label [[COND_END]] 2930 // CHECK5: cond.end: 2931 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2932 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2933 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2934 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 2935 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2936 // CHECK5: omp.inner.for.cond: 2937 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]] 2938 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]] 2939 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2940 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2941 // CHECK5: omp.inner.for.body: 2942 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] 2943 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 2944 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2945 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] 2946 // CHECK5-NEXT: invoke void @_Z3foov() 2947 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP39]] 2948 // CHECK5: invoke.cont: 2949 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2950 // CHECK5: omp.body.continue: 2951 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2952 // CHECK5: omp.inner.for.inc: 2953 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] 2954 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 2955 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] 2956 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] 2957 // CHECK5: omp.inner.for.end: 2958 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2959 // CHECK5: omp.loop.exit: 2960 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 2961 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2962 // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 2963 // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2964 // CHECK5: .omp.final.then: 2965 // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 2966 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2967 // CHECK5: .omp.final.done: 2968 // CHECK5-NEXT: ret void 2969 // CHECK5: terminate.lpad: 2970 // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } 2971 // CHECK5-NEXT: catch ptr null 2972 // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 2973 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP39]] 2974 // CHECK5-NEXT: unreachable 2975 // 2976 // 2977 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40 2978 // CHECK5-SAME: () #[[ATTR3]] personality ptr @__gxx_personality_v0 { 2979 // CHECK5-NEXT: entry: 2980 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2981 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 2982 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 2983 // CHECK5-NEXT: invoke void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) 2984 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 2985 // CHECK5: invoke.cont: 2986 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 2987 // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] 2988 // CHECK5-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 2989 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 2990 // CHECK5-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 2991 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 2992 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined, i64 [[TMP1]]) 2993 // CHECK5-NEXT: ret void 2994 // CHECK5: terminate.lpad: 2995 // CHECK5-NEXT: [[TMP2:%.*]] = landingpad { ptr, i32 } 2996 // CHECK5-NEXT: catch ptr null 2997 // CHECK5-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0 2998 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP3]]) #[[ATTR7]] 2999 // CHECK5-NEXT: unreachable 3000 // 3001 // 3002 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined 3003 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 3004 // CHECK5-NEXT: entry: 3005 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3006 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3007 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3008 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3009 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 3010 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 3011 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 3012 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3013 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3014 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3015 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3016 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3017 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 3018 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 3019 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 3020 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3021 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3022 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3023 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 3024 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3025 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3026 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 3027 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3028 // CHECK5: cond.true: 3029 // CHECK5-NEXT: br label [[COND_END:%.*]] 3030 // CHECK5: cond.false: 3031 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3032 // CHECK5-NEXT: br label [[COND_END]] 3033 // CHECK5: cond.end: 3034 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3035 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 3036 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 3037 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 3038 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3039 // CHECK5: omp.inner.for.cond: 3040 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42:![0-9]+]] 3041 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] 3042 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3043 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3044 // CHECK5: omp.inner.for.body: 3045 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !llvm.access.group [[ACC_GRP42]] 3046 // CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 3047 // CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP42]] 3048 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP42]] 3049 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 3050 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] 3051 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 3052 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined.omp_outlined, i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group [[ACC_GRP42]] 3053 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3054 // CHECK5: omp.inner.for.inc: 3055 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] 3056 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP42]] 3057 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 3058 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] 3059 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] 3060 // CHECK5: omp.inner.for.end: 3061 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3062 // CHECK5: omp.loop.exit: 3063 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 3064 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3065 // CHECK5-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 3066 // CHECK5-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3067 // CHECK5: .omp.final.then: 3068 // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 3069 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 3070 // CHECK5: .omp.final.done: 3071 // CHECK5-NEXT: ret void 3072 // 3073 // 3074 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined.omp_outlined 3075 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 3076 // CHECK5-NEXT: entry: 3077 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3078 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3079 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 3080 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 3081 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3082 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 3083 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3084 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3085 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3086 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3087 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3088 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3089 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3090 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 3091 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 3092 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3093 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 3094 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 3095 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 3096 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 3097 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 3098 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 3099 // CHECK5-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 3100 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3101 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3102 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3103 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 3104 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3105 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3106 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 3107 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3108 // CHECK5: cond.true: 3109 // CHECK5-NEXT: br label [[COND_END:%.*]] 3110 // CHECK5: cond.false: 3111 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3112 // CHECK5-NEXT: br label [[COND_END]] 3113 // CHECK5: cond.end: 3114 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 3115 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3116 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3117 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 3118 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3119 // CHECK5: omp.inner.for.cond: 3120 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]] 3121 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]] 3122 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 3123 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3124 // CHECK5: omp.inner.for.body: 3125 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] 3126 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 3127 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3128 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] 3129 // CHECK5-NEXT: invoke void @_Z3foov() 3130 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP45]] 3131 // CHECK5: invoke.cont: 3132 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3133 // CHECK5: omp.body.continue: 3134 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3135 // CHECK5: omp.inner.for.inc: 3136 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] 3137 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 3138 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] 3139 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] 3140 // CHECK5: omp.inner.for.end: 3141 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3142 // CHECK5: omp.loop.exit: 3143 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 3144 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3145 // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 3146 // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3147 // CHECK5: .omp.final.then: 3148 // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 3149 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 3150 // CHECK5: .omp.final.done: 3151 // CHECK5-NEXT: ret void 3152 // CHECK5: terminate.lpad: 3153 // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } 3154 // CHECK5-NEXT: catch ptr null 3155 // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 3156 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP45]] 3157 // CHECK5-NEXT: unreachable 3158 // 3159 // 3160 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev 3161 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 3162 // CHECK5-NEXT: entry: 3163 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3164 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3165 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3166 // CHECK5-NEXT: ret void 3167 // 3168