1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // expected-no-diagnostics 3 #ifndef HEADER 4 #define HEADER 5 6 // Test host codegen. 7 // RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 8 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 9 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 10 // RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 11 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 13 14 // RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 15 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 16 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 17 // RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 18 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 19 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 20 #ifdef CK1 21 22 template <typename T, int X, long long Y> 23 struct SS{ 24 T a[X][Y]; 25 26 int foo(void) { 27 28 #pragma omp target 29 #pragma omp teams distribute parallel for simd collapse(2) 30 for(int i = 0; i < X; i++) { 31 for(int j = 0; j < Y; j++) { 32 a[i][j] = (T)0; 33 } 34 } 35 36 // discard loop variables not needed here 37 38 39 return a[0][0]; 40 } 41 }; 42 43 int teams_template_struct(void) { 44 SS<int, 123, 456> V; 45 return V.foo(); 46 47 } 48 49 // CK4: !{!"llvm.loop.vectorize.enable", i1 true} 50 51 #endif // CK1 52 53 // Test host codegen. 54 // RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 55 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 56 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 57 // RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 58 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 59 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 60 61 // RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 62 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 63 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 64 // RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 65 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 66 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 67 #ifdef CK2 68 69 template <typename T, int n, int m> 70 int tmain(T argc) { 71 T a[n][m]; 72 #pragma omp target 73 #pragma omp teams distribute parallel for simd collapse(2) 74 for(int i = 0; i < n; i++) { 75 for(int j = 0; j < m; j++) { 76 a[i][j] = (T)0; 77 } 78 } 79 return 0; 80 } 81 82 int main (int argc, char **argv) { 83 int n = 100; 84 int m = 2; 85 int a[n][m]; 86 #pragma omp target 87 #pragma omp teams distribute parallel for simd collapse(2) 88 for(int i = 0; i < n; i++) { 89 for(int j = 0; j < m; j++) { 90 a[i][j] = 0; 91 } 92 } 93 return tmain<int, 10, 2>(argc); 94 } 95 96 97 98 99 100 101 102 103 // discard loop variables not needed here 104 105 106 // CK4: !{!"llvm.loop.vectorize.enable", i1 true} 107 108 #endif // CK2 109 #endif // #ifndef HEADER 110 // CHECK1-LABEL: define {{[^@]+}}@_Z21teams_template_structv 111 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 112 // CHECK1-NEXT: entry: 113 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 114 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]]) 115 // CHECK1-NEXT: ret i32 [[CALL]] 116 // 117 // 118 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 119 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat { 120 // CHECK1-NEXT: entry: 121 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 122 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 123 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 124 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 125 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 126 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 127 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 128 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 129 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 130 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 131 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 132 // CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP0]], align 8 133 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 134 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP1]], align 8 135 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 136 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 137 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 138 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 139 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 140 // CHECK1-NEXT: store i32 3, ptr [[TMP5]], align 4 141 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 142 // CHECK1-NEXT: store i32 1, ptr [[TMP6]], align 4 143 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 144 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8 145 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 146 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8 147 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 148 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 8 149 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 150 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 8 151 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 152 // CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8 153 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 154 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 155 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 156 // CHECK1-NEXT: store i64 56088, ptr [[TMP13]], align 8 157 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 158 // CHECK1-NEXT: store i64 0, ptr [[TMP14]], align 8 159 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 160 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 161 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 162 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 163 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 164 // CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4 165 // CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, ptr [[KERNEL_ARGS]]) 166 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 167 // CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 168 // CHECK1: omp_offload.failed: 169 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(ptr [[THIS1]]) #[[ATTR2:[0-9]+]] 170 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 171 // CHECK1: omp_offload.cont: 172 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 173 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i64 0, i64 0 174 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 0 175 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 176 // CHECK1-NEXT: ret i32 [[TMP20]] 177 // 178 // 179 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 180 // CHECK1-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 181 // CHECK1-NEXT: entry: 182 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 183 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 184 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 185 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined, ptr [[TMP0]]) 186 // CHECK1-NEXT: ret void 187 // 188 // 189 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined 190 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR1]] { 191 // CHECK1-NEXT: entry: 192 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 193 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 194 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 195 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 196 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 197 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 198 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 199 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 200 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 201 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 202 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 203 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 204 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 205 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 206 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 207 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 208 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 209 // CHECK1-NEXT: store i32 56087, ptr [[DOTOMP_COMB_UB]], align 4 210 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 211 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 212 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 213 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 214 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 215 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 216 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 217 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 218 // CHECK1: cond.true: 219 // CHECK1-NEXT: br label [[COND_END:%.*]] 220 // CHECK1: cond.false: 221 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 222 // CHECK1-NEXT: br label [[COND_END]] 223 // CHECK1: cond.end: 224 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 225 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 226 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 227 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 228 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 229 // CHECK1: omp.inner.for.cond: 230 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]] 231 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]] 232 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 233 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 234 // CHECK1: omp.inner.for.body: 235 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP4]] 236 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 237 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]] 238 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 239 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[TMP0]]), !llvm.access.group [[ACC_GRP4]] 240 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 241 // CHECK1: omp.inner.for.inc: 242 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 243 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP4]] 244 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 245 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 246 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 247 // CHECK1: omp.inner.for.end: 248 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 249 // CHECK1: omp.loop.exit: 250 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 251 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 252 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 253 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 254 // CHECK1: .omp.final.then: 255 // CHECK1-NEXT: store i32 123, ptr [[I]], align 4 256 // CHECK1-NEXT: store i32 456, ptr [[J]], align 4 257 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 258 // CHECK1: .omp.final.done: 259 // CHECK1-NEXT: ret void 260 // 261 // 262 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined.omp_outlined 263 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR1]] { 264 // CHECK1-NEXT: entry: 265 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 266 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 267 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 268 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 269 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 270 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 271 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 272 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 273 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 274 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 275 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 276 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 277 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 278 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 279 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 280 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 281 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 282 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 283 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 284 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 285 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 286 // CHECK1-NEXT: store i32 56087, ptr [[DOTOMP_UB]], align 4 287 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 288 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 289 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 290 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 291 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 292 // CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 293 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 294 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 295 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 296 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 297 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 298 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 299 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 56087 300 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 301 // CHECK1: cond.true: 302 // CHECK1-NEXT: br label [[COND_END:%.*]] 303 // CHECK1: cond.false: 304 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 305 // CHECK1-NEXT: br label [[COND_END]] 306 // CHECK1: cond.end: 307 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 308 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 309 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 310 // CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 311 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 312 // CHECK1: omp.inner.for.cond: 313 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]] 314 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]] 315 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 316 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 317 // CHECK1: omp.inner.for.body: 318 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 319 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456 320 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 321 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 322 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 323 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 324 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 325 // CHECK1-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 456 326 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 456 327 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] 328 // CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 329 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] 330 // CHECK1-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP8]] 331 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 332 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 333 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 334 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] 335 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP8]] 336 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 337 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] 338 // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP8]] 339 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 340 // CHECK1: omp.body.continue: 341 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 342 // CHECK1: omp.inner.for.inc: 343 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 344 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 345 // CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 346 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 347 // CHECK1: omp.inner.for.end: 348 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 349 // CHECK1: omp.loop.exit: 350 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) 351 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 352 // CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 353 // CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 354 // CHECK1: .omp.final.then: 355 // CHECK1-NEXT: store i32 123, ptr [[I]], align 4 356 // CHECK1-NEXT: store i32 456, ptr [[J]], align 4 357 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 358 // CHECK1: .omp.final.done: 359 // CHECK1-NEXT: ret void 360 // 361 // 362 // CHECK3-LABEL: define {{[^@]+}}@_Z21teams_template_structv 363 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 364 // CHECK3-NEXT: entry: 365 // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 366 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]]) 367 // CHECK3-NEXT: ret i32 [[CALL]] 368 // 369 // 370 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 371 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 372 // CHECK3-NEXT: entry: 373 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 374 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 375 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 376 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 377 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 378 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 379 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 380 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 381 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 382 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 383 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 384 // CHECK3-NEXT: store ptr [[THIS1]], ptr [[TMP0]], align 4 385 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 386 // CHECK3-NEXT: store ptr [[A]], ptr [[TMP1]], align 4 387 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 388 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 389 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 390 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 391 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 392 // CHECK3-NEXT: store i32 3, ptr [[TMP5]], align 4 393 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 394 // CHECK3-NEXT: store i32 1, ptr [[TMP6]], align 4 395 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 396 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4 397 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 398 // CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4 399 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 400 // CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 4 401 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 402 // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 4 403 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 404 // CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4 405 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 406 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 407 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 408 // CHECK3-NEXT: store i64 56088, ptr [[TMP13]], align 8 409 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 410 // CHECK3-NEXT: store i64 0, ptr [[TMP14]], align 8 411 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 412 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 413 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 414 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 415 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 416 // CHECK3-NEXT: store i32 0, ptr [[TMP17]], align 4 417 // CHECK3-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, ptr [[KERNEL_ARGS]]) 418 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 419 // CHECK3-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 420 // CHECK3: omp_offload.failed: 421 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(ptr [[THIS1]]) #[[ATTR2:[0-9]+]] 422 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 423 // CHECK3: omp_offload.cont: 424 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 425 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i32 0, i32 0 426 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 0 427 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 428 // CHECK3-NEXT: ret i32 [[TMP20]] 429 // 430 // 431 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 432 // CHECK3-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 433 // CHECK3-NEXT: entry: 434 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 435 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 436 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 437 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined, ptr [[TMP0]]) 438 // CHECK3-NEXT: ret void 439 // 440 // 441 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined 442 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR1]] { 443 // CHECK3-NEXT: entry: 444 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 445 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 446 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 447 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 448 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 449 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 450 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 451 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 452 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 453 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 454 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 455 // CHECK3-NEXT: [[J:%.*]] = alloca i32, align 4 456 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 457 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 458 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 459 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 460 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 461 // CHECK3-NEXT: store i32 56087, ptr [[DOTOMP_COMB_UB]], align 4 462 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 463 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 464 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 465 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 466 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 467 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 468 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 469 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 470 // CHECK3: cond.true: 471 // CHECK3-NEXT: br label [[COND_END:%.*]] 472 // CHECK3: cond.false: 473 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 474 // CHECK3-NEXT: br label [[COND_END]] 475 // CHECK3: cond.end: 476 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 477 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 478 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 479 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 480 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 481 // CHECK3: omp.inner.for.cond: 482 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] 483 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 484 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 485 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 486 // CHECK3: omp.inner.for.body: 487 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP5]] 488 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 489 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined.omp_outlined, i32 [[TMP8]], i32 [[TMP9]], ptr [[TMP0]]), !llvm.access.group [[ACC_GRP5]] 490 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 491 // CHECK3: omp.inner.for.inc: 492 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 493 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP5]] 494 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] 495 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 496 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 497 // CHECK3: omp.inner.for.end: 498 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 499 // CHECK3: omp.loop.exit: 500 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 501 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 502 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 503 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 504 // CHECK3: .omp.final.then: 505 // CHECK3-NEXT: store i32 123, ptr [[I]], align 4 506 // CHECK3-NEXT: store i32 456, ptr [[J]], align 4 507 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 508 // CHECK3: .omp.final.done: 509 // CHECK3-NEXT: ret void 510 // 511 // 512 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined.omp_outlined 513 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR1]] { 514 // CHECK3-NEXT: entry: 515 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 516 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 517 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 518 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 519 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 520 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 521 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 522 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 523 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 524 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 525 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 526 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 527 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 528 // CHECK3-NEXT: [[J:%.*]] = alloca i32, align 4 529 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 530 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 531 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 532 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 533 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 534 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 535 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 536 // CHECK3-NEXT: store i32 56087, ptr [[DOTOMP_UB]], align 4 537 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 538 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 539 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4 540 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 541 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 542 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 543 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 544 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 545 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 546 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 547 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 56087 548 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 549 // CHECK3: cond.true: 550 // CHECK3-NEXT: br label [[COND_END:%.*]] 551 // CHECK3: cond.false: 552 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 553 // CHECK3-NEXT: br label [[COND_END]] 554 // CHECK3: cond.end: 555 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 556 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 557 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 558 // CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 559 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 560 // CHECK3: omp.inner.for.cond: 561 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] 562 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 563 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 564 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 565 // CHECK3: omp.inner.for.body: 566 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 567 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456 568 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 569 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 570 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 571 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 572 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 573 // CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 456 574 // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 575 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] 576 // CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 577 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 578 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP9]] 579 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 580 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 581 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP13]] 582 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP9]] 583 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP14]] 584 // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP9]] 585 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 586 // CHECK3: omp.body.continue: 587 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 588 // CHECK3: omp.inner.for.inc: 589 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 590 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 591 // CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 592 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 593 // CHECK3: omp.inner.for.end: 594 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 595 // CHECK3: omp.loop.exit: 596 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) 597 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 598 // CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 599 // CHECK3-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 600 // CHECK3: .omp.final.then: 601 // CHECK3-NEXT: store i32 123, ptr [[I]], align 4 602 // CHECK3-NEXT: store i32 456, ptr [[J]], align 4 603 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 604 // CHECK3: .omp.final.done: 605 // CHECK3-NEXT: ret void 606 // 607 // 608 // CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv 609 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 610 // CHECK5-NEXT: entry: 611 // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 612 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]]) 613 // CHECK5-NEXT: ret i32 [[CALL]] 614 // 615 // 616 // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 617 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat { 618 // CHECK5-NEXT: entry: 619 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 620 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 621 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 622 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 623 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 624 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 625 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 626 // CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 627 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 628 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 629 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 630 // CHECK5-NEXT: store i32 56087, ptr [[DOTOMP_UB]], align 4 631 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 632 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 633 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 634 // CHECK5: omp.inner.for.cond: 635 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 636 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 637 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 638 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 639 // CHECK5: omp.inner.for.body: 640 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 641 // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456 642 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 643 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 644 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 645 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 646 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 647 // CHECK5-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456 648 // CHECK5-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 649 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]] 650 // CHECK5-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 651 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 652 // CHECK5-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP2]] 653 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 654 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 655 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 656 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] 657 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP2]] 658 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 659 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 660 // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP2]] 661 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 662 // CHECK5: omp.body.continue: 663 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 664 // CHECK5: omp.inner.for.inc: 665 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 666 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1 667 // CHECK5-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 668 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 669 // CHECK5: omp.inner.for.end: 670 // CHECK5-NEXT: store i32 123, ptr [[I]], align 4 671 // CHECK5-NEXT: store i32 456, ptr [[J]], align 4 672 // CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 673 // CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A10]], i64 0, i64 0 674 // CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX11]], i64 0, i64 0 675 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX12]], align 4 676 // CHECK5-NEXT: ret i32 [[TMP9]] 677 // 678 // 679 // CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv 680 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 681 // CHECK7-NEXT: entry: 682 // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 683 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]]) 684 // CHECK7-NEXT: ret i32 [[CALL]] 685 // 686 // 687 // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 688 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 689 // CHECK7-NEXT: entry: 690 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 691 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 692 // CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 693 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 694 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 695 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 696 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 697 // CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 698 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 699 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 700 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 701 // CHECK7-NEXT: store i32 56087, ptr [[DOTOMP_UB]], align 4 702 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 703 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 704 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 705 // CHECK7: omp.inner.for.cond: 706 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 707 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 708 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 709 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 710 // CHECK7: omp.inner.for.body: 711 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 712 // CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456 713 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 714 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 715 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 716 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 717 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 718 // CHECK7-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456 719 // CHECK7-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 720 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]] 721 // CHECK7-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 722 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 723 // CHECK7-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP3]] 724 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 725 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 726 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP6]] 727 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP3]] 728 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP7]] 729 // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP3]] 730 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 731 // CHECK7: omp.body.continue: 732 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 733 // CHECK7: omp.inner.for.inc: 734 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 735 // CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 736 // CHECK7-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 737 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 738 // CHECK7: omp.inner.for.end: 739 // CHECK7-NEXT: store i32 123, ptr [[I]], align 4 740 // CHECK7-NEXT: store i32 456, ptr [[J]], align 4 741 // CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 742 // CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A9]], i32 0, i32 0 743 // CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX10]], i32 0, i32 0 744 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4 745 // CHECK7-NEXT: ret i32 [[TMP9]] 746 // 747 // 748 // CHECK9-LABEL: define {{[^@]+}}@main 749 // CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 750 // CHECK9-NEXT: entry: 751 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 752 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 753 // CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8 754 // CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 755 // CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4 756 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 757 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 758 // CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 759 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 760 // CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 761 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 762 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 763 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 764 // CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 765 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 766 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 767 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 768 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 769 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 770 // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 771 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 772 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 773 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 774 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4 775 // CHECK9-NEXT: store i32 2, ptr [[M]], align 4 776 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 777 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 778 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4 779 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 780 // CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0() 781 // CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 782 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 783 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 784 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 785 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 786 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 787 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4 788 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8 789 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[M]], align 4 790 // CHECK9-NEXT: store i32 [[TMP8]], ptr [[M_CASTED]], align 4 791 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[M_CASTED]], align 8 792 // CHECK9-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 793 // CHECK9-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 794 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 40, i1 false) 795 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 796 // CHECK9-NEXT: store i64 [[TMP7]], ptr [[TMP12]], align 8 797 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 798 // CHECK9-NEXT: store i64 [[TMP7]], ptr [[TMP13]], align 8 799 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 800 // CHECK9-NEXT: store ptr null, ptr [[TMP14]], align 8 801 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 802 // CHECK9-NEXT: store i64 [[TMP9]], ptr [[TMP15]], align 8 803 // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 804 // CHECK9-NEXT: store i64 [[TMP9]], ptr [[TMP16]], align 8 805 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 806 // CHECK9-NEXT: store ptr null, ptr [[TMP17]], align 8 807 // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 808 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[TMP18]], align 8 809 // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 810 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[TMP19]], align 8 811 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 812 // CHECK9-NEXT: store ptr null, ptr [[TMP20]], align 8 813 // CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 814 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[TMP21]], align 8 815 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 816 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[TMP22]], align 8 817 // CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 818 // CHECK9-NEXT: store ptr null, ptr [[TMP23]], align 8 819 // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 820 // CHECK9-NEXT: store ptr [[VLA]], ptr [[TMP24]], align 8 821 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 822 // CHECK9-NEXT: store ptr [[VLA]], ptr [[TMP25]], align 8 823 // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 824 // CHECK9-NEXT: store i64 [[TMP11]], ptr [[TMP26]], align 8 825 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 826 // CHECK9-NEXT: store ptr null, ptr [[TMP27]], align 8 827 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 828 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 829 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 830 // CHECK9-NEXT: [[TMP31:%.*]] = load i32, ptr [[N]], align 4 831 // CHECK9-NEXT: store i32 [[TMP31]], ptr [[DOTCAPTURE_EXPR_]], align 4 832 // CHECK9-NEXT: [[TMP32:%.*]] = load i32, ptr [[M]], align 4 833 // CHECK9-NEXT: store i32 [[TMP32]], ptr [[DOTCAPTURE_EXPR_2]], align 4 834 // CHECK9-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 835 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP33]], 0 836 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 837 // CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 838 // CHECK9-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 839 // CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP34]], 0 840 // CHECK9-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 841 // CHECK9-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 842 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 843 // CHECK9-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 844 // CHECK9-NEXT: store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8 845 // CHECK9-NEXT: [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8 846 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP35]], 1 847 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 848 // CHECK9-NEXT: store i32 3, ptr [[TMP36]], align 4 849 // CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 850 // CHECK9-NEXT: store i32 5, ptr [[TMP37]], align 4 851 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 852 // CHECK9-NEXT: store ptr [[TMP28]], ptr [[TMP38]], align 8 853 // CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 854 // CHECK9-NEXT: store ptr [[TMP29]], ptr [[TMP39]], align 8 855 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 856 // CHECK9-NEXT: store ptr [[TMP30]], ptr [[TMP40]], align 8 857 // CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 858 // CHECK9-NEXT: store ptr @.offload_maptypes, ptr [[TMP41]], align 8 859 // CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 860 // CHECK9-NEXT: store ptr null, ptr [[TMP42]], align 8 861 // CHECK9-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 862 // CHECK9-NEXT: store ptr null, ptr [[TMP43]], align 8 863 // CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 864 // CHECK9-NEXT: store i64 [[ADD]], ptr [[TMP44]], align 8 865 // CHECK9-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 866 // CHECK9-NEXT: store i64 0, ptr [[TMP45]], align 8 867 // CHECK9-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 868 // CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP46]], align 4 869 // CHECK9-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 870 // CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP47]], align 4 871 // CHECK9-NEXT: [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 872 // CHECK9-NEXT: store i32 0, ptr [[TMP48]], align 4 873 // CHECK9-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86.region_id, ptr [[KERNEL_ARGS]]) 874 // CHECK9-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 875 // CHECK9-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 876 // CHECK9: omp_offload.failed: 877 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] 878 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 879 // CHECK9: omp_offload.cont: 880 // CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 881 // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]]) 882 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 883 // CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 884 // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP52]]) 885 // CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4 886 // CHECK9-NEXT: ret i32 [[TMP53]] 887 // 888 // 889 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86 890 // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 891 // CHECK9-NEXT: entry: 892 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 893 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 894 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 895 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 896 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 897 // CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 898 // CHECK9-NEXT: store i64 [[M]], ptr [[M_ADDR]], align 8 899 // CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 900 // CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 901 // CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 902 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 903 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 904 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8 905 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86.omp_outlined, ptr [[N_ADDR]], ptr [[M_ADDR]], i64 [[TMP0]], i64 [[TMP1]], ptr [[TMP2]]) 906 // CHECK9-NEXT: ret void 907 // 908 // 909 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86.omp_outlined 910 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { 911 // CHECK9-NEXT: entry: 912 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 913 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 914 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 8 915 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca ptr, align 8 916 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 917 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 918 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 919 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 920 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 921 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 922 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 923 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 924 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 925 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 926 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 927 // CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 928 // CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 929 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 930 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 931 // CHECK9-NEXT: [[I11:%.*]] = alloca i32, align 4 932 // CHECK9-NEXT: [[J12:%.*]] = alloca i32, align 4 933 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 934 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 935 // CHECK9-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 8 936 // CHECK9-NEXT: store ptr [[M]], ptr [[M_ADDR]], align 8 937 // CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 938 // CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 939 // CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 940 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 8 941 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[M_ADDR]], align 8 942 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 943 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 944 // CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 8 945 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 946 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4 947 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP1]], align 4 948 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_4]], align 4 949 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 950 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 951 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 952 // CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 953 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 954 // CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 955 // CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 956 // CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 957 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] 958 // CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 959 // CHECK9-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8 960 // CHECK9-NEXT: store i32 0, ptr [[I]], align 4 961 // CHECK9-NEXT: store i32 0, ptr [[J]], align 4 962 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 963 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] 964 // CHECK9-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 965 // CHECK9: land.lhs.true: 966 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 967 // CHECK9-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] 968 // CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 969 // CHECK9: omp.precond.then: 970 // CHECK9-NEXT: store i64 0, ptr [[DOTOMP_COMB_LB]], align 8 971 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 972 // CHECK9-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_COMB_UB]], align 8 973 // CHECK9-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 974 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 975 // CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 976 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4 977 // CHECK9-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 978 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 979 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 980 // CHECK9-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] 981 // CHECK9-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 982 // CHECK9: cond.true: 983 // CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 984 // CHECK9-NEXT: br label [[COND_END:%.*]] 985 // CHECK9: cond.false: 986 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 987 // CHECK9-NEXT: br label [[COND_END]] 988 // CHECK9: cond.end: 989 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] 990 // CHECK9-NEXT: store i64 [[COND]], ptr [[DOTOMP_COMB_UB]], align 8 991 // CHECK9-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8 992 // CHECK9-NEXT: store i64 [[TMP18]], ptr [[DOTOMP_IV]], align 8 993 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 994 // CHECK9: omp.inner.for.cond: 995 // CHECK9-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5:![0-9]+]] 996 // CHECK9-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8, !llvm.access.group [[ACC_GRP5]] 997 // CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] 998 // CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 999 // CHECK9: omp.inner.for.body: 1000 // CHECK9-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8, !llvm.access.group [[ACC_GRP5]] 1001 // CHECK9-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8, !llvm.access.group [[ACC_GRP5]] 1002 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86.omp_outlined.omp_outlined, i64 [[TMP21]], i64 [[TMP22]], ptr [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]]), !llvm.access.group [[ACC_GRP5]] 1003 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1004 // CHECK9: omp.inner.for.inc: 1005 // CHECK9-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]] 1006 // CHECK9-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8, !llvm.access.group [[ACC_GRP5]] 1007 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP23]], [[TMP24]] 1008 // CHECK9-NEXT: store i64 [[ADD]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]] 1009 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 1010 // CHECK9: omp.inner.for.end: 1011 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1012 // CHECK9: omp.loop.exit: 1013 // CHECK9-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1014 // CHECK9-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 1015 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]]) 1016 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1017 // CHECK9-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 1018 // CHECK9-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1019 // CHECK9: .omp.final.then: 1020 // CHECK9-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1021 // CHECK9-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP29]], 0 1022 // CHECK9-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 1023 // CHECK9-NEXT: [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 1 1024 // CHECK9-NEXT: [[ADD18:%.*]] = add nsw i32 0, [[MUL17]] 1025 // CHECK9-NEXT: store i32 [[ADD18]], ptr [[I11]], align 4 1026 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 1027 // CHECK9-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP30]], 0 1028 // CHECK9-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1 1029 // CHECK9-NEXT: [[MUL21:%.*]] = mul nsw i32 [[DIV20]], 1 1030 // CHECK9-NEXT: [[ADD22:%.*]] = add nsw i32 0, [[MUL21]] 1031 // CHECK9-NEXT: store i32 [[ADD22]], ptr [[J12]], align 4 1032 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 1033 // CHECK9: .omp.final.done: 1034 // CHECK9-NEXT: br label [[OMP_PRECOND_END]] 1035 // CHECK9: omp.precond.end: 1036 // CHECK9-NEXT: ret void 1037 // 1038 // 1039 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86.omp_outlined.omp_outlined 1040 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { 1041 // CHECK9-NEXT: entry: 1042 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1043 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1044 // CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1045 // CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1046 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 8 1047 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca ptr, align 8 1048 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1049 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1050 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 1051 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1052 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1053 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 1054 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1055 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 1056 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 1057 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1058 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 1059 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1060 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1061 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1062 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1063 // CHECK9-NEXT: [[I11:%.*]] = alloca i32, align 4 1064 // CHECK9-NEXT: [[J12:%.*]] = alloca i32, align 4 1065 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1066 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1067 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1068 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1069 // CHECK9-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 8 1070 // CHECK9-NEXT: store ptr [[M]], ptr [[M_ADDR]], align 8 1071 // CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1072 // CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1073 // CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 1074 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 8 1075 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[M_ADDR]], align 8 1076 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1077 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1078 // CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 8 1079 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 1080 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4 1081 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP1]], align 4 1082 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_4]], align 4 1083 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1084 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 1085 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1086 // CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1087 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 1088 // CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 1089 // CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 1090 // CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 1091 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] 1092 // CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 1093 // CHECK9-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8 1094 // CHECK9-NEXT: store i32 0, ptr [[I]], align 4 1095 // CHECK9-NEXT: store i32 0, ptr [[J]], align 4 1096 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1097 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] 1098 // CHECK9-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 1099 // CHECK9: land.lhs.true: 1100 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 1101 // CHECK9-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] 1102 // CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 1103 // CHECK9: omp.precond.then: 1104 // CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 1105 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 1106 // CHECK9-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_UB]], align 8 1107 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1108 // CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1109 // CHECK9-NEXT: store i64 [[TMP12]], ptr [[DOTOMP_LB]], align 8 1110 // CHECK9-NEXT: store i64 [[TMP13]], ptr [[DOTOMP_UB]], align 8 1111 // CHECK9-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 1112 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1113 // CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1114 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 1115 // CHECK9-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB2:[0-9]+]], i32 [[TMP15]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 1116 // CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 1117 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 1118 // CHECK9-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP16]], [[TMP17]] 1119 // CHECK9-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1120 // CHECK9: cond.true: 1121 // CHECK9-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 1122 // CHECK9-NEXT: br label [[COND_END:%.*]] 1123 // CHECK9: cond.false: 1124 // CHECK9-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 1125 // CHECK9-NEXT: br label [[COND_END]] 1126 // CHECK9: cond.end: 1127 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ] 1128 // CHECK9-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 1129 // CHECK9-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 1130 // CHECK9-NEXT: store i64 [[TMP20]], ptr [[DOTOMP_IV]], align 8 1131 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1132 // CHECK9: omp.inner.for.cond: 1133 // CHECK9-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP9:![0-9]+]] 1134 // CHECK9-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP9]] 1135 // CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]] 1136 // CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1137 // CHECK9: omp.inner.for.body: 1138 // CHECK9-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP9]] 1139 // CHECK9-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP9]] 1140 // CHECK9-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP24]], 0 1141 // CHECK9-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 1142 // CHECK9-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] 1143 // CHECK9-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 1144 // CHECK9-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP23]], [[CONV18]] 1145 // CHECK9-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 1146 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] 1147 // CHECK9-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 1148 // CHECK9-NEXT: store i32 [[CONV21]], ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP9]] 1149 // CHECK9-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP9]] 1150 // CHECK9-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP9]] 1151 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP9]] 1152 // CHECK9-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP27]], 0 1153 // CHECK9-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 1154 // CHECK9-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] 1155 // CHECK9-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 1156 // CHECK9-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP26]], [[CONV25]] 1157 // CHECK9-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP9]] 1158 // CHECK9-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP28]], 0 1159 // CHECK9-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 1160 // CHECK9-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] 1161 // CHECK9-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 1162 // CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] 1163 // CHECK9-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP25]], [[MUL31]] 1164 // CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 1165 // CHECK9-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] 1166 // CHECK9-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 1167 // CHECK9-NEXT: store i32 [[CONV35]], ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP9]] 1168 // CHECK9-NEXT: [[TMP29:%.*]] = load i32, ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP9]] 1169 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP29]] to i64 1170 // CHECK9-NEXT: [[TMP30:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] 1171 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 [[TMP30]] 1172 // CHECK9-NEXT: [[TMP31:%.*]] = load i32, ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP9]] 1173 // CHECK9-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64 1174 // CHECK9-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 [[IDXPROM36]] 1175 // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX37]], align 4, !llvm.access.group [[ACC_GRP9]] 1176 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1177 // CHECK9: omp.body.continue: 1178 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1179 // CHECK9: omp.inner.for.inc: 1180 // CHECK9-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP9]] 1181 // CHECK9-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP32]], 1 1182 // CHECK9-NEXT: store i64 [[ADD38]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP9]] 1183 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 1184 // CHECK9: omp.inner.for.end: 1185 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1186 // CHECK9: omp.loop.exit: 1187 // CHECK9-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1188 // CHECK9-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP33]], align 4 1189 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP34]]) 1190 // CHECK9-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1191 // CHECK9-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0 1192 // CHECK9-NEXT: br i1 [[TMP36]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1193 // CHECK9: .omp.final.then: 1194 // CHECK9-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1195 // CHECK9-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP37]], 0 1196 // CHECK9-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1 1197 // CHECK9-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1 1198 // CHECK9-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]] 1199 // CHECK9-NEXT: store i32 [[ADD42]], ptr [[I11]], align 4 1200 // CHECK9-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 1201 // CHECK9-NEXT: [[SUB43:%.*]] = sub nsw i32 [[TMP38]], 0 1202 // CHECK9-NEXT: [[DIV44:%.*]] = sdiv i32 [[SUB43]], 1 1203 // CHECK9-NEXT: [[MUL45:%.*]] = mul nsw i32 [[DIV44]], 1 1204 // CHECK9-NEXT: [[ADD46:%.*]] = add nsw i32 0, [[MUL45]] 1205 // CHECK9-NEXT: store i32 [[ADD46]], ptr [[J12]], align 4 1206 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 1207 // CHECK9: .omp.final.done: 1208 // CHECK9-NEXT: br label [[OMP_PRECOND_END]] 1209 // CHECK9: omp.precond.end: 1210 // CHECK9-NEXT: ret void 1211 // 1212 // 1213 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 1214 // CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { 1215 // CHECK9-NEXT: entry: 1216 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1217 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 1218 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 1219 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 1220 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 1221 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1222 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1223 // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1224 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 1225 // CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1226 // CHECK9-NEXT: store ptr [[A]], ptr [[TMP0]], align 8 1227 // CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1228 // CHECK9-NEXT: store ptr [[A]], ptr [[TMP1]], align 8 1229 // CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1230 // CHECK9-NEXT: store ptr null, ptr [[TMP2]], align 8 1231 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1232 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1233 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1234 // CHECK9-NEXT: store i32 3, ptr [[TMP5]], align 4 1235 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1236 // CHECK9-NEXT: store i32 1, ptr [[TMP6]], align 4 1237 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1238 // CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8 1239 // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1240 // CHECK9-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8 1241 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1242 // CHECK9-NEXT: store ptr @.offload_sizes.1, ptr [[TMP9]], align 8 1243 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1244 // CHECK9-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP10]], align 8 1245 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1246 // CHECK9-NEXT: store ptr null, ptr [[TMP11]], align 8 1247 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1248 // CHECK9-NEXT: store ptr null, ptr [[TMP12]], align 8 1249 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1250 // CHECK9-NEXT: store i64 20, ptr [[TMP13]], align 8 1251 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1252 // CHECK9-NEXT: store i64 0, ptr [[TMP14]], align 8 1253 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1254 // CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 1255 // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1256 // CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 1257 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1258 // CHECK9-NEXT: store i32 0, ptr [[TMP17]], align 4 1259 // CHECK9-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l72.region_id, ptr [[KERNEL_ARGS]]) 1260 // CHECK9-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 1261 // CHECK9-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1262 // CHECK9: omp_offload.failed: 1263 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l72(ptr [[A]]) #[[ATTR3]] 1264 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 1265 // CHECK9: omp_offload.cont: 1266 // CHECK9-NEXT: ret i32 0 1267 // 1268 // 1269 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l72 1270 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1271 // CHECK9-NEXT: entry: 1272 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 1273 // CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 1274 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 1275 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l72.omp_outlined, ptr [[TMP0]]) 1276 // CHECK9-NEXT: ret void 1277 // 1278 // 1279 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l72.omp_outlined 1280 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1281 // CHECK9-NEXT: entry: 1282 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1283 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1284 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 1285 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1286 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1287 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1288 // CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1289 // CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1290 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1291 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1292 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1293 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 1294 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1295 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1296 // CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 1297 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 1298 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1299 // CHECK9-NEXT: store i32 19, ptr [[DOTOMP_COMB_UB]], align 4 1300 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1301 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1302 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1303 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 1304 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1305 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1306 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 1307 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1308 // CHECK9: cond.true: 1309 // CHECK9-NEXT: br label [[COND_END:%.*]] 1310 // CHECK9: cond.false: 1311 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1312 // CHECK9-NEXT: br label [[COND_END]] 1313 // CHECK9: cond.end: 1314 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1315 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1316 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1317 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 1318 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1319 // CHECK9: omp.inner.for.cond: 1320 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]] 1321 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]] 1322 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1323 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1324 // CHECK9: omp.inner.for.body: 1325 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP14]] 1326 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 1327 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]] 1328 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 1329 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l72.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[TMP0]]), !llvm.access.group [[ACC_GRP14]] 1330 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1331 // CHECK9: omp.inner.for.inc: 1332 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 1333 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP14]] 1334 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 1335 // CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 1336 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 1337 // CHECK9: omp.inner.for.end: 1338 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1339 // CHECK9: omp.loop.exit: 1340 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 1341 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1342 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 1343 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1344 // CHECK9: .omp.final.then: 1345 // CHECK9-NEXT: store i32 10, ptr [[I]], align 4 1346 // CHECK9-NEXT: store i32 2, ptr [[J]], align 4 1347 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 1348 // CHECK9: .omp.final.done: 1349 // CHECK9-NEXT: ret void 1350 // 1351 // 1352 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l72.omp_outlined.omp_outlined 1353 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1354 // CHECK9-NEXT: entry: 1355 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1356 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1357 // CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1358 // CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1359 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 1360 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1361 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1362 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1363 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1364 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1365 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1366 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1367 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1368 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 1369 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1370 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1371 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1372 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1373 // CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 1374 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 1375 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1376 // CHECK9-NEXT: store i32 19, ptr [[DOTOMP_UB]], align 4 1377 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1378 // CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 1379 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1380 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 1381 // CHECK9-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1382 // CHECK9-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 1383 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1384 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1385 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1386 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 1387 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1388 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1389 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 1390 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1391 // CHECK9: cond.true: 1392 // CHECK9-NEXT: br label [[COND_END:%.*]] 1393 // CHECK9: cond.false: 1394 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1395 // CHECK9-NEXT: br label [[COND_END]] 1396 // CHECK9: cond.end: 1397 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 1398 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1399 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1400 // CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 1401 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1402 // CHECK9: omp.inner.for.cond: 1403 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]] 1404 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP17]] 1405 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 1406 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1407 // CHECK9: omp.inner.for.body: 1408 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 1409 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 1410 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1411 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1412 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 1413 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 1414 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 1415 // CHECK9-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2 1416 // CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2 1417 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] 1418 // CHECK9-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 1419 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] 1420 // CHECK9-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP17]] 1421 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 1422 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 1423 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] 1424 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP17]] 1425 // CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 1426 // CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] 1427 // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP17]] 1428 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1429 // CHECK9: omp.body.continue: 1430 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1431 // CHECK9: omp.inner.for.inc: 1432 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 1433 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 1434 // CHECK9-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 1435 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 1436 // CHECK9: omp.inner.for.end: 1437 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1438 // CHECK9: omp.loop.exit: 1439 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) 1440 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1441 // CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 1442 // CHECK9-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1443 // CHECK9: .omp.final.then: 1444 // CHECK9-NEXT: store i32 10, ptr [[I]], align 4 1445 // CHECK9-NEXT: store i32 2, ptr [[J]], align 4 1446 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 1447 // CHECK9: .omp.final.done: 1448 // CHECK9-NEXT: ret void 1449 // 1450 // 1451 // CHECK11-LABEL: define {{[^@]+}}@main 1452 // CHECK11-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 1453 // CHECK11-NEXT: entry: 1454 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1455 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1456 // CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 4 1457 // CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 1458 // CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4 1459 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 1460 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1461 // CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1462 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 1463 // CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 1464 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 1465 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 1466 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 1467 // CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 1468 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1469 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1470 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1471 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1472 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 1473 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1474 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 1475 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 1476 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 1477 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4 1478 // CHECK11-NEXT: store i32 2, ptr [[M]], align 4 1479 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 1480 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4 1481 // CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0() 1482 // CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 1483 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 1484 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 1485 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 1486 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4 1487 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 1488 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 1489 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4 1490 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[M]], align 4 1491 // CHECK11-NEXT: store i32 [[TMP6]], ptr [[M_CASTED]], align 4 1492 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[M_CASTED]], align 4 1493 // CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 1494 // CHECK11-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 1495 // CHECK11-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 1496 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes, i32 40, i1 false) 1497 // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1498 // CHECK11-NEXT: store i32 [[TMP5]], ptr [[TMP11]], align 4 1499 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1500 // CHECK11-NEXT: store i32 [[TMP5]], ptr [[TMP12]], align 4 1501 // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1502 // CHECK11-NEXT: store ptr null, ptr [[TMP13]], align 4 1503 // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1504 // CHECK11-NEXT: store i32 [[TMP7]], ptr [[TMP14]], align 4 1505 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1506 // CHECK11-NEXT: store i32 [[TMP7]], ptr [[TMP15]], align 4 1507 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1508 // CHECK11-NEXT: store ptr null, ptr [[TMP16]], align 4 1509 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1510 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[TMP17]], align 4 1511 // CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1512 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[TMP18]], align 4 1513 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1514 // CHECK11-NEXT: store ptr null, ptr [[TMP19]], align 4 1515 // CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1516 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[TMP20]], align 4 1517 // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1518 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[TMP21]], align 4 1519 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1520 // CHECK11-NEXT: store ptr null, ptr [[TMP22]], align 4 1521 // CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1522 // CHECK11-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 4 1523 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1524 // CHECK11-NEXT: store ptr [[VLA]], ptr [[TMP24]], align 4 1525 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1526 // CHECK11-NEXT: store i64 [[TMP10]], ptr [[TMP25]], align 4 1527 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1528 // CHECK11-NEXT: store ptr null, ptr [[TMP26]], align 4 1529 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1530 // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1531 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1532 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, ptr [[N]], align 4 1533 // CHECK11-NEXT: store i32 [[TMP30]], ptr [[DOTCAPTURE_EXPR_]], align 4 1534 // CHECK11-NEXT: [[TMP31:%.*]] = load i32, ptr [[M]], align 4 1535 // CHECK11-NEXT: store i32 [[TMP31]], ptr [[DOTCAPTURE_EXPR_2]], align 4 1536 // CHECK11-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1537 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP32]], 0 1538 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1539 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1540 // CHECK11-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 1541 // CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP33]], 0 1542 // CHECK11-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 1543 // CHECK11-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 1544 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 1545 // CHECK11-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 1546 // CHECK11-NEXT: store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8 1547 // CHECK11-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8 1548 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP34]], 1 1549 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1550 // CHECK11-NEXT: store i32 3, ptr [[TMP35]], align 4 1551 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1552 // CHECK11-NEXT: store i32 5, ptr [[TMP36]], align 4 1553 // CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1554 // CHECK11-NEXT: store ptr [[TMP27]], ptr [[TMP37]], align 4 1555 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1556 // CHECK11-NEXT: store ptr [[TMP28]], ptr [[TMP38]], align 4 1557 // CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1558 // CHECK11-NEXT: store ptr [[TMP29]], ptr [[TMP39]], align 4 1559 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1560 // CHECK11-NEXT: store ptr @.offload_maptypes, ptr [[TMP40]], align 4 1561 // CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1562 // CHECK11-NEXT: store ptr null, ptr [[TMP41]], align 4 1563 // CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1564 // CHECK11-NEXT: store ptr null, ptr [[TMP42]], align 4 1565 // CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1566 // CHECK11-NEXT: store i64 [[ADD]], ptr [[TMP43]], align 8 1567 // CHECK11-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1568 // CHECK11-NEXT: store i64 0, ptr [[TMP44]], align 8 1569 // CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1570 // CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP45]], align 4 1571 // CHECK11-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1572 // CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP46]], align 4 1573 // CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1574 // CHECK11-NEXT: store i32 0, ptr [[TMP47]], align 4 1575 // CHECK11-NEXT: [[TMP48:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86.region_id, ptr [[KERNEL_ARGS]]) 1576 // CHECK11-NEXT: [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0 1577 // CHECK11-NEXT: br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1578 // CHECK11: omp_offload.failed: 1579 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] 1580 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 1581 // CHECK11: omp_offload.cont: 1582 // CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 1583 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]]) 1584 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 1585 // CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 1586 // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP51]]) 1587 // CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4 1588 // CHECK11-NEXT: ret i32 [[TMP52]] 1589 // 1590 // 1591 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86 1592 // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 1593 // CHECK11-NEXT: entry: 1594 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1595 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 1596 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 1597 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 1598 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 1599 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1600 // CHECK11-NEXT: store i32 [[M]], ptr [[M_ADDR]], align 4 1601 // CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 1602 // CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 1603 // CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 1604 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 1605 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 1606 // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4 1607 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86.omp_outlined, ptr [[N_ADDR]], ptr [[M_ADDR]], i32 [[TMP0]], i32 [[TMP1]], ptr [[TMP2]]) 1608 // CHECK11-NEXT: ret void 1609 // 1610 // 1611 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86.omp_outlined 1612 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { 1613 // CHECK11-NEXT: entry: 1614 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1615 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1616 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 4 1617 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca ptr, align 4 1618 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 1619 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 1620 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 1621 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1622 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1623 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 1624 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1625 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 1626 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 1627 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 1628 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 1629 // CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 1630 // CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 1631 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1632 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1633 // CHECK11-NEXT: [[I11:%.*]] = alloca i32, align 4 1634 // CHECK11-NEXT: [[J12:%.*]] = alloca i32, align 4 1635 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1636 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1637 // CHECK11-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 4 1638 // CHECK11-NEXT: store ptr [[M]], ptr [[M_ADDR]], align 4 1639 // CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 1640 // CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 1641 // CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 1642 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 4 1643 // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[M_ADDR]], align 4 1644 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 1645 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 1646 // CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 4 1647 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 1648 // CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4 1649 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP1]], align 4 1650 // CHECK11-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_4]], align 4 1651 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1652 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 1653 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1654 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1655 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 1656 // CHECK11-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 1657 // CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 1658 // CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 1659 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] 1660 // CHECK11-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 1661 // CHECK11-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8 1662 // CHECK11-NEXT: store i32 0, ptr [[I]], align 4 1663 // CHECK11-NEXT: store i32 0, ptr [[J]], align 4 1664 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1665 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] 1666 // CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 1667 // CHECK11: land.lhs.true: 1668 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 1669 // CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] 1670 // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 1671 // CHECK11: omp.precond.then: 1672 // CHECK11-NEXT: store i64 0, ptr [[DOTOMP_COMB_LB]], align 8 1673 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 1674 // CHECK11-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_COMB_UB]], align 8 1675 // CHECK11-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 1676 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1677 // CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1678 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4 1679 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 1680 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 1681 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 1682 // CHECK11-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] 1683 // CHECK11-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1684 // CHECK11: cond.true: 1685 // CHECK11-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 1686 // CHECK11-NEXT: br label [[COND_END:%.*]] 1687 // CHECK11: cond.false: 1688 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 1689 // CHECK11-NEXT: br label [[COND_END]] 1690 // CHECK11: cond.end: 1691 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] 1692 // CHECK11-NEXT: store i64 [[COND]], ptr [[DOTOMP_COMB_UB]], align 8 1693 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8 1694 // CHECK11-NEXT: store i64 [[TMP18]], ptr [[DOTOMP_IV]], align 8 1695 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1696 // CHECK11: omp.inner.for.cond: 1697 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6:![0-9]+]] 1698 // CHECK11-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8, !llvm.access.group [[ACC_GRP6]] 1699 // CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] 1700 // CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1701 // CHECK11: omp.inner.for.body: 1702 // CHECK11-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8, !llvm.access.group [[ACC_GRP6]] 1703 // CHECK11-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32 1704 // CHECK11-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8, !llvm.access.group [[ACC_GRP6]] 1705 // CHECK11-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32 1706 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86.omp_outlined.omp_outlined, i32 [[TMP22]], i32 [[TMP24]], ptr [[TMP0]], ptr [[TMP1]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]]), !llvm.access.group [[ACC_GRP6]] 1707 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1708 // CHECK11: omp.inner.for.inc: 1709 // CHECK11-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]] 1710 // CHECK11-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8, !llvm.access.group [[ACC_GRP6]] 1711 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]] 1712 // CHECK11-NEXT: store i64 [[ADD]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]] 1713 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1714 // CHECK11: omp.inner.for.end: 1715 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1716 // CHECK11: omp.loop.exit: 1717 // CHECK11-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1718 // CHECK11-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4 1719 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP28]]) 1720 // CHECK11-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1721 // CHECK11-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 1722 // CHECK11-NEXT: br i1 [[TMP30]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1723 // CHECK11: .omp.final.then: 1724 // CHECK11-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1725 // CHECK11-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP31]], 0 1726 // CHECK11-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 1727 // CHECK11-NEXT: [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 1 1728 // CHECK11-NEXT: [[ADD18:%.*]] = add nsw i32 0, [[MUL17]] 1729 // CHECK11-NEXT: store i32 [[ADD18]], ptr [[I11]], align 4 1730 // CHECK11-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 1731 // CHECK11-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP32]], 0 1732 // CHECK11-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1 1733 // CHECK11-NEXT: [[MUL21:%.*]] = mul nsw i32 [[DIV20]], 1 1734 // CHECK11-NEXT: [[ADD22:%.*]] = add nsw i32 0, [[MUL21]] 1735 // CHECK11-NEXT: store i32 [[ADD22]], ptr [[J12]], align 4 1736 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] 1737 // CHECK11: .omp.final.done: 1738 // CHECK11-NEXT: br label [[OMP_PRECOND_END]] 1739 // CHECK11: omp.precond.end: 1740 // CHECK11-NEXT: ret void 1741 // 1742 // 1743 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86.omp_outlined.omp_outlined 1744 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { 1745 // CHECK11-NEXT: entry: 1746 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1747 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1748 // CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 1749 // CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 1750 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 4 1751 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca ptr, align 4 1752 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 1753 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 1754 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 1755 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1756 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1757 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 1758 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1759 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 1760 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 1761 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 1762 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 1763 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1764 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1765 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1766 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1767 // CHECK11-NEXT: [[I13:%.*]] = alloca i32, align 4 1768 // CHECK11-NEXT: [[J14:%.*]] = alloca i32, align 4 1769 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1770 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1771 // CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1772 // CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1773 // CHECK11-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 4 1774 // CHECK11-NEXT: store ptr [[M]], ptr [[M_ADDR]], align 4 1775 // CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 1776 // CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 1777 // CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 1778 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 4 1779 // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[M_ADDR]], align 4 1780 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 1781 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 1782 // CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 4 1783 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 1784 // CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4 1785 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP1]], align 4 1786 // CHECK11-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_4]], align 4 1787 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1788 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 1789 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1790 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1791 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 1792 // CHECK11-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 1793 // CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 1794 // CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 1795 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] 1796 // CHECK11-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 1797 // CHECK11-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8 1798 // CHECK11-NEXT: store i32 0, ptr [[I]], align 4 1799 // CHECK11-NEXT: store i32 0, ptr [[J]], align 4 1800 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1801 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] 1802 // CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 1803 // CHECK11: land.lhs.true: 1804 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 1805 // CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] 1806 // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 1807 // CHECK11: omp.precond.then: 1808 // CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 1809 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 1810 // CHECK11-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_UB]], align 8 1811 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1812 // CHECK11-NEXT: [[CONV11:%.*]] = zext i32 [[TMP12]] to i64 1813 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1814 // CHECK11-NEXT: [[CONV12:%.*]] = zext i32 [[TMP13]] to i64 1815 // CHECK11-NEXT: store i64 [[CONV11]], ptr [[DOTOMP_LB]], align 8 1816 // CHECK11-NEXT: store i64 [[CONV12]], ptr [[DOTOMP_UB]], align 8 1817 // CHECK11-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 1818 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1819 // CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1820 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 1821 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB2:[0-9]+]], i32 [[TMP15]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 1822 // CHECK11-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 1823 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 1824 // CHECK11-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP16]], [[TMP17]] 1825 // CHECK11-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1826 // CHECK11: cond.true: 1827 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 1828 // CHECK11-NEXT: br label [[COND_END:%.*]] 1829 // CHECK11: cond.false: 1830 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 1831 // CHECK11-NEXT: br label [[COND_END]] 1832 // CHECK11: cond.end: 1833 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ] 1834 // CHECK11-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 1835 // CHECK11-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 1836 // CHECK11-NEXT: store i64 [[TMP20]], ptr [[DOTOMP_IV]], align 8 1837 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1838 // CHECK11: omp.inner.for.cond: 1839 // CHECK11-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP10:![0-9]+]] 1840 // CHECK11-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP10]] 1841 // CHECK11-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]] 1842 // CHECK11-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1843 // CHECK11: omp.inner.for.body: 1844 // CHECK11-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP10]] 1845 // CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP10]] 1846 // CHECK11-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP24]], 0 1847 // CHECK11-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 1848 // CHECK11-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] 1849 // CHECK11-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 1850 // CHECK11-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP23]], [[CONV20]] 1851 // CHECK11-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 1852 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] 1853 // CHECK11-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 1854 // CHECK11-NEXT: store i32 [[CONV23]], ptr [[I13]], align 4, !llvm.access.group [[ACC_GRP10]] 1855 // CHECK11-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP10]] 1856 // CHECK11-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP10]] 1857 // CHECK11-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP10]] 1858 // CHECK11-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP27]], 0 1859 // CHECK11-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 1860 // CHECK11-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 1861 // CHECK11-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 1862 // CHECK11-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP26]], [[CONV27]] 1863 // CHECK11-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP10]] 1864 // CHECK11-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP28]], 0 1865 // CHECK11-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 1866 // CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] 1867 // CHECK11-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 1868 // CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] 1869 // CHECK11-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP25]], [[MUL33]] 1870 // CHECK11-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 1871 // CHECK11-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] 1872 // CHECK11-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 1873 // CHECK11-NEXT: store i32 [[CONV37]], ptr [[J14]], align 4, !llvm.access.group [[ACC_GRP10]] 1874 // CHECK11-NEXT: [[TMP29:%.*]] = load i32, ptr [[I13]], align 4, !llvm.access.group [[ACC_GRP10]] 1875 // CHECK11-NEXT: [[TMP30:%.*]] = mul nsw i32 [[TMP29]], [[TMP3]] 1876 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i32 [[TMP30]] 1877 // CHECK11-NEXT: [[TMP31:%.*]] = load i32, ptr [[J14]], align 4, !llvm.access.group [[ACC_GRP10]] 1878 // CHECK11-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i32 [[TMP31]] 1879 // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX38]], align 4, !llvm.access.group [[ACC_GRP10]] 1880 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1881 // CHECK11: omp.body.continue: 1882 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1883 // CHECK11: omp.inner.for.inc: 1884 // CHECK11-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP10]] 1885 // CHECK11-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP32]], 1 1886 // CHECK11-NEXT: store i64 [[ADD39]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP10]] 1887 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 1888 // CHECK11: omp.inner.for.end: 1889 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1890 // CHECK11: omp.loop.exit: 1891 // CHECK11-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1892 // CHECK11-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP33]], align 4 1893 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP34]]) 1894 // CHECK11-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1895 // CHECK11-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0 1896 // CHECK11-NEXT: br i1 [[TMP36]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1897 // CHECK11: .omp.final.then: 1898 // CHECK11-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1899 // CHECK11-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP37]], 0 1900 // CHECK11-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 1901 // CHECK11-NEXT: [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 1 1902 // CHECK11-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]] 1903 // CHECK11-NEXT: store i32 [[ADD43]], ptr [[I13]], align 4 1904 // CHECK11-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 1905 // CHECK11-NEXT: [[SUB44:%.*]] = sub nsw i32 [[TMP38]], 0 1906 // CHECK11-NEXT: [[DIV45:%.*]] = sdiv i32 [[SUB44]], 1 1907 // CHECK11-NEXT: [[MUL46:%.*]] = mul nsw i32 [[DIV45]], 1 1908 // CHECK11-NEXT: [[ADD47:%.*]] = add nsw i32 0, [[MUL46]] 1909 // CHECK11-NEXT: store i32 [[ADD47]], ptr [[J14]], align 4 1910 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] 1911 // CHECK11: .omp.final.done: 1912 // CHECK11-NEXT: br label [[OMP_PRECOND_END]] 1913 // CHECK11: omp.precond.end: 1914 // CHECK11-NEXT: ret void 1915 // 1916 // 1917 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 1918 // CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { 1919 // CHECK11-NEXT: entry: 1920 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1921 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 1922 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 1923 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 1924 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 1925 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1926 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1927 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1928 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 1929 // CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1930 // CHECK11-NEXT: store ptr [[A]], ptr [[TMP0]], align 4 1931 // CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1932 // CHECK11-NEXT: store ptr [[A]], ptr [[TMP1]], align 4 1933 // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1934 // CHECK11-NEXT: store ptr null, ptr [[TMP2]], align 4 1935 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1936 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1937 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1938 // CHECK11-NEXT: store i32 3, ptr [[TMP5]], align 4 1939 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1940 // CHECK11-NEXT: store i32 1, ptr [[TMP6]], align 4 1941 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1942 // CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4 1943 // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1944 // CHECK11-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4 1945 // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1946 // CHECK11-NEXT: store ptr @.offload_sizes.1, ptr [[TMP9]], align 4 1947 // CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1948 // CHECK11-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP10]], align 4 1949 // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1950 // CHECK11-NEXT: store ptr null, ptr [[TMP11]], align 4 1951 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1952 // CHECK11-NEXT: store ptr null, ptr [[TMP12]], align 4 1953 // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1954 // CHECK11-NEXT: store i64 20, ptr [[TMP13]], align 8 1955 // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1956 // CHECK11-NEXT: store i64 0, ptr [[TMP14]], align 8 1957 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1958 // CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 1959 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1960 // CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 1961 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1962 // CHECK11-NEXT: store i32 0, ptr [[TMP17]], align 4 1963 // CHECK11-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l72.region_id, ptr [[KERNEL_ARGS]]) 1964 // CHECK11-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 1965 // CHECK11-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1966 // CHECK11: omp_offload.failed: 1967 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l72(ptr [[A]]) #[[ATTR3]] 1968 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 1969 // CHECK11: omp_offload.cont: 1970 // CHECK11-NEXT: ret i32 0 1971 // 1972 // 1973 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l72 1974 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1975 // CHECK11-NEXT: entry: 1976 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 1977 // CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 1978 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 1979 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l72.omp_outlined, ptr [[TMP0]]) 1980 // CHECK11-NEXT: ret void 1981 // 1982 // 1983 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l72.omp_outlined 1984 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1985 // CHECK11-NEXT: entry: 1986 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1987 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1988 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 1989 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1990 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1991 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1992 // CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1993 // CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1994 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1995 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1996 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 1997 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 1998 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1999 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2000 // CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 2001 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 2002 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 2003 // CHECK11-NEXT: store i32 19, ptr [[DOTOMP_COMB_UB]], align 4 2004 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2005 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2006 // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2007 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 2008 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2009 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2010 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 2011 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2012 // CHECK11: cond.true: 2013 // CHECK11-NEXT: br label [[COND_END:%.*]] 2014 // CHECK11: cond.false: 2015 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2016 // CHECK11-NEXT: br label [[COND_END]] 2017 // CHECK11: cond.end: 2018 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 2019 // CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2020 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2021 // CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 2022 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2023 // CHECK11: omp.inner.for.cond: 2024 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] 2025 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 2026 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 2027 // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2028 // CHECK11: omp.inner.for.body: 2029 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]] 2030 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 2031 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l72.omp_outlined.omp_outlined, i32 [[TMP8]], i32 [[TMP9]], ptr [[TMP0]]), !llvm.access.group [[ACC_GRP15]] 2032 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2033 // CHECK11: omp.inner.for.inc: 2034 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 2035 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]] 2036 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] 2037 // CHECK11-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 2038 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 2039 // CHECK11: omp.inner.for.end: 2040 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2041 // CHECK11: omp.loop.exit: 2042 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 2043 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2044 // CHECK11-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 2045 // CHECK11-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2046 // CHECK11: .omp.final.then: 2047 // CHECK11-NEXT: store i32 10, ptr [[I]], align 4 2048 // CHECK11-NEXT: store i32 2, ptr [[J]], align 4 2049 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] 2050 // CHECK11: .omp.final.done: 2051 // CHECK11-NEXT: ret void 2052 // 2053 // 2054 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l72.omp_outlined.omp_outlined 2055 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 2056 // CHECK11-NEXT: entry: 2057 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2058 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2059 // CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 2060 // CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 2061 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 2062 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2063 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 2064 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2065 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2066 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2067 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2068 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2069 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 2070 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 2071 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2072 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2073 // CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 2074 // CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 2075 // CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 2076 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 2077 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2078 // CHECK11-NEXT: store i32 19, ptr [[DOTOMP_UB]], align 4 2079 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 2080 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 2081 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4 2082 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 2083 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2084 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2085 // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2086 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 2087 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2088 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2089 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 2090 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2091 // CHECK11: cond.true: 2092 // CHECK11-NEXT: br label [[COND_END:%.*]] 2093 // CHECK11: cond.false: 2094 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2095 // CHECK11-NEXT: br label [[COND_END]] 2096 // CHECK11: cond.end: 2097 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 2098 // CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2099 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2100 // CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 2101 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2102 // CHECK11: omp.inner.for.cond: 2103 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] 2104 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] 2105 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 2106 // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2107 // CHECK11: omp.inner.for.body: 2108 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 2109 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 2110 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 2111 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2112 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 2113 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 2114 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 2115 // CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2 2116 // CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 2117 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] 2118 // CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 2119 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 2120 // CHECK11-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP18]] 2121 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 2122 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP13]] 2123 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP18]] 2124 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP14]] 2125 // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP18]] 2126 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2127 // CHECK11: omp.body.continue: 2128 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2129 // CHECK11: omp.inner.for.inc: 2130 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 2131 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 2132 // CHECK11-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 2133 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 2134 // CHECK11: omp.inner.for.end: 2135 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2136 // CHECK11: omp.loop.exit: 2137 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) 2138 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2139 // CHECK11-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 2140 // CHECK11-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2141 // CHECK11: .omp.final.then: 2142 // CHECK11-NEXT: store i32 10, ptr [[I]], align 4 2143 // CHECK11-NEXT: store i32 2, ptr [[J]], align 4 2144 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] 2145 // CHECK11: .omp.final.done: 2146 // CHECK11-NEXT: ret void 2147 // 2148 // 2149 // CHECK13-LABEL: define {{[^@]+}}@main 2150 // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 2151 // CHECK13-NEXT: entry: 2152 // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2153 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2154 // CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8 2155 // CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 2156 // CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 2157 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 2158 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2159 // CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 2160 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 2161 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2162 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2163 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 2164 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 2165 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2166 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2167 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 2168 // CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 2169 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2170 // CHECK13-NEXT: [[I9:%.*]] = alloca i32, align 4 2171 // CHECK13-NEXT: [[J10:%.*]] = alloca i32, align 4 2172 // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 2173 // CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 2174 // CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 2175 // CHECK13-NEXT: store i32 100, ptr [[N]], align 4 2176 // CHECK13-NEXT: store i32 2, ptr [[M]], align 4 2177 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 2178 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 2179 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4 2180 // CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 2181 // CHECK13-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0() 2182 // CHECK13-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 2183 // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 2184 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 2185 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 2186 // CHECK13-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 2187 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 2188 // CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4 2189 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[M]], align 4 2190 // CHECK13-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_2]], align 4 2191 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 2192 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP8]], 0 2193 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 2194 // CHECK13-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 2195 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 2196 // CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP9]], 0 2197 // CHECK13-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 2198 // CHECK13-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 2199 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 2200 // CHECK13-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 2201 // CHECK13-NEXT: store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8 2202 // CHECK13-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 2203 // CHECK13-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8 2204 // CHECK13-NEXT: store i64 [[TMP10]], ptr [[DOTOMP_UB]], align 8 2205 // CHECK13-NEXT: store i32 0, ptr [[I]], align 4 2206 // CHECK13-NEXT: store i32 0, ptr [[J]], align 4 2207 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 2208 // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP11]] 2209 // CHECK13-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]] 2210 // CHECK13: land.lhs.true: 2211 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 2212 // CHECK13-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP12]] 2213 // CHECK13-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]] 2214 // CHECK13: simd.if.then: 2215 // CHECK13-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 2216 // CHECK13-NEXT: store i64 [[TMP13]], ptr [[DOTOMP_IV]], align 8 2217 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2218 // CHECK13: omp.inner.for.cond: 2219 // CHECK13-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2:![0-9]+]] 2220 // CHECK13-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]] 2221 // CHECK13-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP14]], [[TMP15]] 2222 // CHECK13-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2223 // CHECK13: omp.inner.for.body: 2224 // CHECK13-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]] 2225 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP2]] 2226 // CHECK13-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP17]], 0 2227 // CHECK13-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 2228 // CHECK13-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]] 2229 // CHECK13-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64 2230 // CHECK13-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP16]], [[CONV15]] 2231 // CHECK13-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1 2232 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]] 2233 // CHECK13-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32 2234 // CHECK13-NEXT: store i32 [[CONV18]], ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP2]] 2235 // CHECK13-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]] 2236 // CHECK13-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]] 2237 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP2]] 2238 // CHECK13-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP20]], 0 2239 // CHECK13-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1 2240 // CHECK13-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]] 2241 // CHECK13-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64 2242 // CHECK13-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP19]], [[CONV22]] 2243 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP2]] 2244 // CHECK13-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP21]], 0 2245 // CHECK13-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 2246 // CHECK13-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 2247 // CHECK13-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 2248 // CHECK13-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]] 2249 // CHECK13-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP18]], [[MUL28]] 2250 // CHECK13-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1 2251 // CHECK13-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]] 2252 // CHECK13-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32 2253 // CHECK13-NEXT: store i32 [[CONV32]], ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP2]] 2254 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP2]] 2255 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64 2256 // CHECK13-NEXT: [[TMP23:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] 2257 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 [[TMP23]] 2258 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP2]] 2259 // CHECK13-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP24]] to i64 2260 // CHECK13-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 [[IDXPROM33]] 2261 // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX34]], align 4, !llvm.access.group [[ACC_GRP2]] 2262 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2263 // CHECK13: omp.body.continue: 2264 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2265 // CHECK13: omp.inner.for.inc: 2266 // CHECK13-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]] 2267 // CHECK13-NEXT: [[ADD35:%.*]] = add nsw i64 [[TMP25]], 1 2268 // CHECK13-NEXT: store i64 [[ADD35]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]] 2269 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 2270 // CHECK13: omp.inner.for.end: 2271 // CHECK13-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 2272 // CHECK13-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP26]], 0 2273 // CHECK13-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 1 2274 // CHECK13-NEXT: [[MUL38:%.*]] = mul nsw i32 [[DIV37]], 1 2275 // CHECK13-NEXT: [[ADD39:%.*]] = add nsw i32 0, [[MUL38]] 2276 // CHECK13-NEXT: store i32 [[ADD39]], ptr [[I9]], align 4 2277 // CHECK13-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 2278 // CHECK13-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP27]], 0 2279 // CHECK13-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 2280 // CHECK13-NEXT: [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 1 2281 // CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]] 2282 // CHECK13-NEXT: store i32 [[ADD43]], ptr [[J10]], align 4 2283 // CHECK13-NEXT: br label [[SIMD_IF_END]] 2284 // CHECK13: simd.if.end: 2285 // CHECK13-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 2286 // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]]) 2287 // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 2288 // CHECK13-NEXT: [[TMP29:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 2289 // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP29]]) 2290 // CHECK13-NEXT: [[TMP30:%.*]] = load i32, ptr [[RETVAL]], align 4 2291 // CHECK13-NEXT: ret i32 [[TMP30]] 2292 // 2293 // 2294 // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 2295 // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { 2296 // CHECK13-NEXT: entry: 2297 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2298 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 2299 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 2300 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2301 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2302 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2303 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2304 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 2305 // CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 2306 // CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 2307 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2308 // CHECK13-NEXT: store i32 19, ptr [[DOTOMP_UB]], align 4 2309 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2310 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 2311 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2312 // CHECK13: omp.inner.for.cond: 2313 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 2314 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 2315 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 2316 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2317 // CHECK13: omp.inner.for.body: 2318 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 2319 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2 2320 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 2321 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2322 // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 2323 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 2324 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 2325 // CHECK13-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2 2326 // CHECK13-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2 2327 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]] 2328 // CHECK13-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 2329 // CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] 2330 // CHECK13-NEXT: store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP6]] 2331 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 2332 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 2333 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] 2334 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP6]] 2335 // CHECK13-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP7]] to i64 2336 // CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM6]] 2337 // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP6]] 2338 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2339 // CHECK13: omp.body.continue: 2340 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2341 // CHECK13: omp.inner.for.inc: 2342 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 2343 // CHECK13-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 2344 // CHECK13-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 2345 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 2346 // CHECK13: omp.inner.for.end: 2347 // CHECK13-NEXT: store i32 10, ptr [[I]], align 4 2348 // CHECK13-NEXT: store i32 2, ptr [[J]], align 4 2349 // CHECK13-NEXT: ret i32 0 2350 // 2351 // 2352 // CHECK15-LABEL: define {{[^@]+}}@main 2353 // CHECK15-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 2354 // CHECK15-NEXT: entry: 2355 // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2356 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2357 // CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 4 2358 // CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 2359 // CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 2360 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 2361 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2362 // CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2363 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 2364 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2365 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2366 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 2367 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 2368 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2369 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2370 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 2371 // CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 2372 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2373 // CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 2374 // CHECK15-NEXT: [[J10:%.*]] = alloca i32, align 4 2375 // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 2376 // CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 2377 // CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 2378 // CHECK15-NEXT: store i32 100, ptr [[N]], align 4 2379 // CHECK15-NEXT: store i32 2, ptr [[M]], align 4 2380 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 2381 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4 2382 // CHECK15-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0() 2383 // CHECK15-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 2384 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 2385 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 2386 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 2387 // CHECK15-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4 2388 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 2389 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 2390 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[M]], align 4 2391 // CHECK15-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_2]], align 4 2392 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 2393 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 2394 // CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 2395 // CHECK15-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 2396 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 2397 // CHECK15-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP7]], 0 2398 // CHECK15-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 2399 // CHECK15-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 2400 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 2401 // CHECK15-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 2402 // CHECK15-NEXT: store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8 2403 // CHECK15-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 2404 // CHECK15-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8 2405 // CHECK15-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_UB]], align 8 2406 // CHECK15-NEXT: store i32 0, ptr [[I]], align 4 2407 // CHECK15-NEXT: store i32 0, ptr [[J]], align 4 2408 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 2409 // CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] 2410 // CHECK15-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]] 2411 // CHECK15: land.lhs.true: 2412 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 2413 // CHECK15-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP10]] 2414 // CHECK15-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]] 2415 // CHECK15: simd.if.then: 2416 // CHECK15-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 2417 // CHECK15-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_IV]], align 8 2418 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2419 // CHECK15: omp.inner.for.cond: 2420 // CHECK15-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3:![0-9]+]] 2421 // CHECK15-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP3]] 2422 // CHECK15-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP12]], [[TMP13]] 2423 // CHECK15-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2424 // CHECK15: omp.inner.for.body: 2425 // CHECK15-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]] 2426 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]] 2427 // CHECK15-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP15]], 0 2428 // CHECK15-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 2429 // CHECK15-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]] 2430 // CHECK15-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64 2431 // CHECK15-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], [[CONV15]] 2432 // CHECK15-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1 2433 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]] 2434 // CHECK15-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32 2435 // CHECK15-NEXT: store i32 [[CONV18]], ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP3]] 2436 // CHECK15-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]] 2437 // CHECK15-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]] 2438 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]] 2439 // CHECK15-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP18]], 0 2440 // CHECK15-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1 2441 // CHECK15-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]] 2442 // CHECK15-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64 2443 // CHECK15-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP17]], [[CONV22]] 2444 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]] 2445 // CHECK15-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP19]], 0 2446 // CHECK15-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 2447 // CHECK15-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 2448 // CHECK15-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 2449 // CHECK15-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]] 2450 // CHECK15-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP16]], [[MUL28]] 2451 // CHECK15-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1 2452 // CHECK15-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]] 2453 // CHECK15-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32 2454 // CHECK15-NEXT: store i32 [[CONV32]], ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP3]] 2455 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP3]] 2456 // CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 [[TMP20]], [[TMP1]] 2457 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 [[TMP21]] 2458 // CHECK15-NEXT: [[TMP22:%.*]] = load i32, ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP3]] 2459 // CHECK15-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i32 [[TMP22]] 2460 // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX33]], align 4, !llvm.access.group [[ACC_GRP3]] 2461 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2462 // CHECK15: omp.body.continue: 2463 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2464 // CHECK15: omp.inner.for.inc: 2465 // CHECK15-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]] 2466 // CHECK15-NEXT: [[ADD34:%.*]] = add nsw i64 [[TMP23]], 1 2467 // CHECK15-NEXT: store i64 [[ADD34]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]] 2468 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 2469 // CHECK15: omp.inner.for.end: 2470 // CHECK15-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 2471 // CHECK15-NEXT: [[SUB35:%.*]] = sub nsw i32 [[TMP24]], 0 2472 // CHECK15-NEXT: [[DIV36:%.*]] = sdiv i32 [[SUB35]], 1 2473 // CHECK15-NEXT: [[MUL37:%.*]] = mul nsw i32 [[DIV36]], 1 2474 // CHECK15-NEXT: [[ADD38:%.*]] = add nsw i32 0, [[MUL37]] 2475 // CHECK15-NEXT: store i32 [[ADD38]], ptr [[I9]], align 4 2476 // CHECK15-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 2477 // CHECK15-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP25]], 0 2478 // CHECK15-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1 2479 // CHECK15-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1 2480 // CHECK15-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]] 2481 // CHECK15-NEXT: store i32 [[ADD42]], ptr [[J10]], align 4 2482 // CHECK15-NEXT: br label [[SIMD_IF_END]] 2483 // CHECK15: simd.if.end: 2484 // CHECK15-NEXT: [[TMP26:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 2485 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]]) 2486 // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 2487 // CHECK15-NEXT: [[TMP27:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 2488 // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP27]]) 2489 // CHECK15-NEXT: [[TMP28:%.*]] = load i32, ptr [[RETVAL]], align 4 2490 // CHECK15-NEXT: ret i32 [[TMP28]] 2491 // 2492 // 2493 // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 2494 // CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { 2495 // CHECK15-NEXT: entry: 2496 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2497 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 2498 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 2499 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2500 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2501 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2502 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2503 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 2504 // CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 2505 // CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 2506 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2507 // CHECK15-NEXT: store i32 19, ptr [[DOTOMP_UB]], align 4 2508 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2509 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 2510 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2511 // CHECK15: omp.inner.for.cond: 2512 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 2513 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]] 2514 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 2515 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2516 // CHECK15: omp.inner.for.body: 2517 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 2518 // CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2 2519 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 2520 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2521 // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 2522 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 2523 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 2524 // CHECK15-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2 2525 // CHECK15-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2 2526 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]] 2527 // CHECK15-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 2528 // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] 2529 // CHECK15-NEXT: store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP7]] 2530 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 2531 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], i32 0, i32 [[TMP6]] 2532 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP7]] 2533 // CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP7]] 2534 // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP7]] 2535 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2536 // CHECK15: omp.body.continue: 2537 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2538 // CHECK15: omp.inner.for.inc: 2539 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 2540 // CHECK15-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP8]], 1 2541 // CHECK15-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 2542 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 2543 // CHECK15: omp.inner.for.end: 2544 // CHECK15-NEXT: store i32 10, ptr [[I]], align 4 2545 // CHECK15-NEXT: store i32 2, ptr [[J]], align 4 2546 // CHECK15-NEXT: ret i32 0 2547 // 2548