1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target 57 #pragma omp teams distribute parallel for private(t_var, vec, s_arr, var) 58 for (int i = 0; i < 2; ++i) { 59 vec[i] = t_var; 60 s_arr[i] = var; 61 } 62 return T(); 63 } 64 65 S<float> test; 66 int t_var = 333; 67 int vec[] = {1, 2}; 68 S<float> s_arr[] = {1, 2}; 69 S<float> var(3); 70 71 int main() { 72 static int sivar; 73 #ifdef LAMBDA 74 [&]() { 75 #pragma omp target 76 #pragma omp teams distribute parallel for private(g, g1, sivar) 77 for (int i = 0; i < 2; ++i) { 78 79 // Skip global, bound tid and loop vars 80 81 g = 1; 82 g1 = 1; 83 sivar = 2; 84 85 // Skip global, bound tid and loop vars 86 [&]() { 87 g = 2; 88 g1 = 2; 89 sivar = 4; 90 91 }(); 92 } 93 }(); 94 return 0; 95 #else 96 #pragma omp target 97 #pragma omp teams distribute parallel for private(t_var, vec, s_arr, var, sivar) 98 for (int i = 0; i < 2; ++i) { 99 vec[i] = t_var; 100 s_arr[i] = var; 101 sivar += i; 102 } 103 return tmain<int>(); 104 #endif 105 } 106 107 108 109 // Skip global, bound tid and loop vars 110 111 // private(s_arr) 112 113 // private(var) 114 115 116 // Skip global, bound tid and loop vars 117 118 // private(s_arr) 119 120 // private(var) 121 122 123 124 125 // Skip global, bound tid and loop vars 126 127 // private(s_arr) 128 129 130 // private(var) 131 132 133 // Skip global, bound tid and loop vars 134 // prev lb and ub 135 // iter variables 136 137 // private(s_arr) 138 139 140 // private(var) 141 142 143 144 #endif 145 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 146 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 147 // CHECK1-NEXT: entry: 148 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 149 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 150 // CHECK1-NEXT: ret void 151 // 152 // 153 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 154 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 155 // CHECK1-NEXT: entry: 156 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 157 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 158 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 159 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 160 // CHECK1-NEXT: ret void 161 // 162 // 163 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 164 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 165 // CHECK1-NEXT: entry: 166 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 167 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 168 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 169 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 170 // CHECK1-NEXT: ret void 171 // 172 // 173 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 174 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 175 // CHECK1-NEXT: entry: 176 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 177 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 178 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 179 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 180 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 181 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 182 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 183 // CHECK1-NEXT: ret void 184 // 185 // 186 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 187 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 188 // CHECK1-NEXT: entry: 189 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 190 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 191 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 192 // CHECK1-NEXT: ret void 193 // 194 // 195 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 196 // CHECK1-SAME: () #[[ATTR0]] { 197 // CHECK1-NEXT: entry: 198 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 199 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 200 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 201 // CHECK1-NEXT: ret void 202 // 203 // 204 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 205 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 206 // CHECK1-NEXT: entry: 207 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 208 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 209 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 210 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 211 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 212 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 213 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 214 // CHECK1-NEXT: ret void 215 // 216 // 217 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 218 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 219 // CHECK1-NEXT: entry: 220 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 221 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 222 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 223 // CHECK1: arraydestroy.body: 224 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 225 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 226 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 227 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 228 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 229 // CHECK1: arraydestroy.done1: 230 // CHECK1-NEXT: ret void 231 // 232 // 233 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 234 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 235 // CHECK1-NEXT: entry: 236 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 237 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 238 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 239 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 240 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 241 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 242 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 243 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 244 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 245 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 246 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 247 // CHECK1-NEXT: ret void 248 // 249 // 250 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 251 // CHECK1-SAME: () #[[ATTR0]] { 252 // CHECK1-NEXT: entry: 253 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 254 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 255 // CHECK1-NEXT: ret void 256 // 257 // 258 // CHECK1-LABEL: define {{[^@]+}}@main 259 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 260 // CHECK1-NEXT: entry: 261 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 262 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 263 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 264 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 265 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 266 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 267 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 268 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 269 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 270 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 271 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 272 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 273 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 274 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 275 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 276 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 277 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 278 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 279 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 280 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 281 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 282 // CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8 283 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 284 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 285 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 286 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 287 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 288 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 289 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 290 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 291 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, ptr [[KERNEL_ARGS]]) 292 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 293 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 294 // CHECK1: omp_offload.failed: 295 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96() #[[ATTR2]] 296 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 297 // CHECK1: omp_offload.cont: 298 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 299 // CHECK1-NEXT: ret i32 [[CALL]] 300 // 301 // 302 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 303 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 304 // CHECK1-NEXT: entry: 305 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined) 306 // CHECK1-NEXT: ret void 307 // 308 // 309 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined 310 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 311 // CHECK1-NEXT: entry: 312 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 313 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 314 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 315 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 316 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 317 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 318 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 319 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 320 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 321 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 322 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 323 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 324 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 325 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 326 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 327 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 328 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 329 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 330 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 331 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 332 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 333 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 334 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 335 // CHECK1: arrayctor.loop: 336 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 337 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 338 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 339 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 340 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 341 // CHECK1: arrayctor.cont: 342 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 343 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 344 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 345 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 346 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 347 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 348 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 349 // CHECK1: cond.true: 350 // CHECK1-NEXT: br label [[COND_END:%.*]] 351 // CHECK1: cond.false: 352 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 353 // CHECK1-NEXT: br label [[COND_END]] 354 // CHECK1: cond.end: 355 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 356 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 357 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 358 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 359 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 360 // CHECK1: omp.inner.for.cond: 361 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 362 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 363 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 364 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 365 // CHECK1: omp.inner.for.cond.cleanup: 366 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 367 // CHECK1: omp.inner.for.body: 368 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 369 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 370 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 371 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 372 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) 373 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 374 // CHECK1: omp.inner.for.inc: 375 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 376 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 377 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 378 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 379 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 380 // CHECK1: omp.inner.for.end: 381 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 382 // CHECK1: omp.loop.exit: 383 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 384 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 385 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 386 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 387 // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 388 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2 389 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 390 // CHECK1: arraydestroy.body: 391 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 392 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 393 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 394 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 395 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 396 // CHECK1: arraydestroy.done3: 397 // CHECK1-NEXT: ret void 398 // 399 // 400 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined.omp_outlined 401 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 402 // CHECK1-NEXT: entry: 403 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 404 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 405 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 406 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 407 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 408 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 409 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 410 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 411 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 412 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 413 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 414 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 415 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 416 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 417 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 418 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 419 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 420 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 421 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 422 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 423 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 424 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 425 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 426 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 427 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 428 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 429 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 430 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 431 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 432 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 433 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 434 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 435 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 436 // CHECK1: arrayctor.loop: 437 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 438 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 439 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 440 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 441 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 442 // CHECK1: arrayctor.cont: 443 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 444 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 445 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 446 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 447 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 448 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 449 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 450 // CHECK1: cond.true: 451 // CHECK1-NEXT: br label [[COND_END:%.*]] 452 // CHECK1: cond.false: 453 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 454 // CHECK1-NEXT: br label [[COND_END]] 455 // CHECK1: cond.end: 456 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 457 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 458 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 459 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 460 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 461 // CHECK1: omp.inner.for.cond: 462 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 463 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 464 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 465 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 466 // CHECK1: omp.inner.for.cond.cleanup: 467 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 468 // CHECK1: omp.inner.for.body: 469 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 470 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 471 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 472 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 473 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 474 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 475 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 476 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 477 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 478 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 479 // CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 480 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] 481 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false) 482 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 483 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 484 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 485 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[SIVAR]], align 4 486 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 487 // CHECK1: omp.body.continue: 488 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 489 // CHECK1: omp.inner.for.inc: 490 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 491 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP15]], 1 492 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 493 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 494 // CHECK1: omp.inner.for.end: 495 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 496 // CHECK1: omp.loop.exit: 497 // CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 498 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 499 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) 500 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 501 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 502 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 503 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 504 // CHECK1: arraydestroy.body: 505 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 506 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 507 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 508 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 509 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 510 // CHECK1: arraydestroy.done8: 511 // CHECK1-NEXT: ret void 512 // 513 // 514 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 515 // CHECK1-SAME: () #[[ATTR1]] comdat { 516 // CHECK1-NEXT: entry: 517 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 518 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 519 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 520 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 521 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 522 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 523 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 524 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 525 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 526 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 527 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 528 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 529 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 530 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 531 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 532 // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 533 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 534 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 535 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 536 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 537 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 538 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 539 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 540 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 541 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 542 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 543 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 544 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 545 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 546 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 547 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 548 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 549 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 550 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 551 // CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8 552 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 553 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 554 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 555 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 556 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 557 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 558 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 559 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 560 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 561 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 562 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 563 // CHECK1: omp_offload.failed: 564 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 565 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 566 // CHECK1: omp_offload.cont: 567 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 568 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 569 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 570 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 571 // CHECK1: arraydestroy.body: 572 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 573 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 574 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 575 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 576 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 577 // CHECK1: arraydestroy.done2: 578 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 579 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 580 // CHECK1-NEXT: ret i32 [[TMP16]] 581 // 582 // 583 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 584 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 585 // CHECK1-NEXT: entry: 586 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 587 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 588 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 589 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 590 // CHECK1-NEXT: ret void 591 // 592 // 593 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 594 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 595 // CHECK1-NEXT: entry: 596 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 597 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 598 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 599 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 600 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 601 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 602 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 603 // CHECK1-NEXT: ret void 604 // 605 // 606 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 607 // CHECK1-SAME: () #[[ATTR4]] { 608 // CHECK1-NEXT: entry: 609 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined) 610 // CHECK1-NEXT: ret void 611 // 612 // 613 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 614 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 615 // CHECK1-NEXT: entry: 616 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 617 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 618 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 619 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 620 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 621 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 622 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 623 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 624 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 625 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 626 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 627 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 628 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 629 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 630 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 631 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 632 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 633 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 634 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 635 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 636 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 637 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 638 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 639 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 640 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 641 // CHECK1: arrayctor.loop: 642 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 643 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 644 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 645 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 646 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 647 // CHECK1: arrayctor.cont: 648 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 649 // CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 8 650 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 651 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 652 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 653 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 654 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 655 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 656 // CHECK1: cond.true: 657 // CHECK1-NEXT: br label [[COND_END:%.*]] 658 // CHECK1: cond.false: 659 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 660 // CHECK1-NEXT: br label [[COND_END]] 661 // CHECK1: cond.end: 662 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 663 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 664 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 665 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 666 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 667 // CHECK1: omp.inner.for.cond: 668 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 669 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 670 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 671 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 672 // CHECK1: omp.inner.for.cond.cleanup: 673 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 674 // CHECK1: omp.inner.for.body: 675 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 676 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 677 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 678 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 679 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) 680 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 681 // CHECK1: omp.inner.for.inc: 682 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 683 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 684 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 685 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 686 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 687 // CHECK1: omp.inner.for.end: 688 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 689 // CHECK1: omp.loop.exit: 690 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 691 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 692 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 693 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 694 // CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 695 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2 696 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 697 // CHECK1: arraydestroy.body: 698 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 699 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 700 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 701 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 702 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 703 // CHECK1: arraydestroy.done5: 704 // CHECK1-NEXT: ret void 705 // 706 // 707 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined 708 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 709 // CHECK1-NEXT: entry: 710 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 711 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 712 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 713 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 714 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 715 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 716 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 717 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 718 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 719 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 720 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 721 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 722 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 723 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 724 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 725 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 726 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 727 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 728 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 729 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 730 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 731 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 732 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 733 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 734 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 735 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 736 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 737 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 738 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 739 // CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 740 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 741 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 742 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 743 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 744 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 745 // CHECK1: arrayctor.loop: 746 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 747 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 748 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 749 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 750 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 751 // CHECK1: arrayctor.cont: 752 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 753 // CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP3]], align 8 754 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 755 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 756 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 757 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 758 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 759 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 760 // CHECK1: cond.true: 761 // CHECK1-NEXT: br label [[COND_END:%.*]] 762 // CHECK1: cond.false: 763 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 764 // CHECK1-NEXT: br label [[COND_END]] 765 // CHECK1: cond.end: 766 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 767 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 768 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 769 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 770 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 771 // CHECK1: omp.inner.for.cond: 772 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 773 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 774 // CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 775 // CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 776 // CHECK1: omp.inner.for.cond.cleanup: 777 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 778 // CHECK1: omp.inner.for.body: 779 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 780 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 781 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 782 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 783 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 784 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 785 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 786 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 787 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 788 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8 789 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 790 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 791 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] 792 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false) 793 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 794 // CHECK1: omp.body.continue: 795 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 796 // CHECK1: omp.inner.for.inc: 797 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 798 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP14]], 1 799 // CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4 800 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 801 // CHECK1: omp.inner.for.end: 802 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 803 // CHECK1: omp.loop.exit: 804 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 805 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 806 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) 807 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 808 // CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 809 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 810 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 811 // CHECK1: arraydestroy.body: 812 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 813 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 814 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 815 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 816 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 817 // CHECK1: arraydestroy.done9: 818 // CHECK1-NEXT: ret void 819 // 820 // 821 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 822 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 823 // CHECK1-NEXT: entry: 824 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 825 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 826 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 827 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 828 // CHECK1-NEXT: ret void 829 // 830 // 831 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 832 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 833 // CHECK1-NEXT: entry: 834 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 835 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 836 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 837 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 838 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 839 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 840 // CHECK1-NEXT: ret void 841 // 842 // 843 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 844 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 845 // CHECK1-NEXT: entry: 846 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 847 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 848 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 849 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 850 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 851 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 852 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 853 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 854 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 855 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 856 // CHECK1-NEXT: ret void 857 // 858 // 859 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 860 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 861 // CHECK1-NEXT: entry: 862 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 863 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 864 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 865 // CHECK1-NEXT: ret void 866 // 867 // 868 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp 869 // CHECK1-SAME: () #[[ATTR0]] { 870 // CHECK1-NEXT: entry: 871 // CHECK1-NEXT: call void @__cxx_global_var_init() 872 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 873 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 874 // CHECK1-NEXT: ret void 875 // 876 // 877 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 878 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 879 // CHECK3-NEXT: entry: 880 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 881 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 882 // CHECK3-NEXT: ret void 883 // 884 // 885 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 886 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 887 // CHECK3-NEXT: entry: 888 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 889 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 890 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 891 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 892 // CHECK3-NEXT: ret void 893 // 894 // 895 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 896 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 897 // CHECK3-NEXT: entry: 898 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 899 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 900 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 901 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 902 // CHECK3-NEXT: ret void 903 // 904 // 905 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 906 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 907 // CHECK3-NEXT: entry: 908 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 909 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 910 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 911 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 912 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 913 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 914 // CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4 915 // CHECK3-NEXT: ret void 916 // 917 // 918 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 919 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 920 // CHECK3-NEXT: entry: 921 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 922 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 923 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 924 // CHECK3-NEXT: ret void 925 // 926 // 927 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 928 // CHECK3-SAME: () #[[ATTR0]] { 929 // CHECK3-NEXT: entry: 930 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 931 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 932 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 933 // CHECK3-NEXT: ret void 934 // 935 // 936 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 937 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 938 // CHECK3-NEXT: entry: 939 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 940 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 941 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 942 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 943 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 944 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 945 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 946 // CHECK3-NEXT: ret void 947 // 948 // 949 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 950 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 951 // CHECK3-NEXT: entry: 952 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 953 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 954 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 955 // CHECK3: arraydestroy.body: 956 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 957 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 958 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 959 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 960 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 961 // CHECK3: arraydestroy.done1: 962 // CHECK3-NEXT: ret void 963 // 964 // 965 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 966 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 967 // CHECK3-NEXT: entry: 968 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 969 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 970 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 971 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 972 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 973 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 974 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 975 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 976 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 977 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 978 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 979 // CHECK3-NEXT: ret void 980 // 981 // 982 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 983 // CHECK3-SAME: () #[[ATTR0]] { 984 // CHECK3-NEXT: entry: 985 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 986 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 987 // CHECK3-NEXT: ret void 988 // 989 // 990 // CHECK3-LABEL: define {{[^@]+}}@main 991 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 992 // CHECK3-NEXT: entry: 993 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 994 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 995 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 996 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 997 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 998 // CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4 999 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1000 // CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4 1001 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1002 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 1003 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1004 // CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4 1005 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1006 // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 1007 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1008 // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 1009 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1010 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1011 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1012 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 1013 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1014 // CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8 1015 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1016 // CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8 1017 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1018 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 1019 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1020 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 1021 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1022 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 1023 // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, ptr [[KERNEL_ARGS]]) 1024 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1025 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1026 // CHECK3: omp_offload.failed: 1027 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96() #[[ATTR2]] 1028 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1029 // CHECK3: omp_offload.cont: 1030 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1031 // CHECK3-NEXT: ret i32 [[CALL]] 1032 // 1033 // 1034 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 1035 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 1036 // CHECK3-NEXT: entry: 1037 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined) 1038 // CHECK3-NEXT: ret void 1039 // 1040 // 1041 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined 1042 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1043 // CHECK3-NEXT: entry: 1044 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1045 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1046 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1047 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1048 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1049 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1050 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1051 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1052 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1053 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1054 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1055 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1056 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1057 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1058 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1059 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1060 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1061 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1062 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1063 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1064 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1065 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1066 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1067 // CHECK3: arrayctor.loop: 1068 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1069 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1070 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 1071 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1072 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1073 // CHECK3: arrayctor.cont: 1074 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1075 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1076 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1077 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1078 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1079 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1080 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1081 // CHECK3: cond.true: 1082 // CHECK3-NEXT: br label [[COND_END:%.*]] 1083 // CHECK3: cond.false: 1084 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1085 // CHECK3-NEXT: br label [[COND_END]] 1086 // CHECK3: cond.end: 1087 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1088 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1089 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1090 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1091 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1092 // CHECK3: omp.inner.for.cond: 1093 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1094 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1095 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1096 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1097 // CHECK3: omp.inner.for.cond.cleanup: 1098 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1099 // CHECK3: omp.inner.for.body: 1100 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1101 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1102 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]]) 1103 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1104 // CHECK3: omp.inner.for.inc: 1105 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1106 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1107 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] 1108 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 1109 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1110 // CHECK3: omp.inner.for.end: 1111 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1112 // CHECK3: omp.loop.exit: 1113 // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1114 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 1115 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) 1116 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1117 // CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1118 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i32 2 1119 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1120 // CHECK3: arraydestroy.body: 1121 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1122 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1123 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1124 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 1125 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 1126 // CHECK3: arraydestroy.done3: 1127 // CHECK3-NEXT: ret void 1128 // 1129 // 1130 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined.omp_outlined 1131 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 1132 // CHECK3-NEXT: entry: 1133 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1134 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1135 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 1136 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 1137 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1138 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1139 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1140 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1141 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1142 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1143 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1144 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1145 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1146 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1147 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1148 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1149 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1150 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1151 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1152 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1153 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1154 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1155 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1156 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1157 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4 1158 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 1159 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1160 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1161 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1162 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1163 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1164 // CHECK3: arrayctor.loop: 1165 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1166 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1167 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 1168 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1169 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1170 // CHECK3: arrayctor.cont: 1171 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1172 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1173 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1174 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1175 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1176 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 1177 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1178 // CHECK3: cond.true: 1179 // CHECK3-NEXT: br label [[COND_END:%.*]] 1180 // CHECK3: cond.false: 1181 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1182 // CHECK3-NEXT: br label [[COND_END]] 1183 // CHECK3: cond.end: 1184 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1185 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1186 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1187 // CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1188 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1189 // CHECK3: omp.inner.for.cond: 1190 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1191 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1192 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1193 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1194 // CHECK3: omp.inner.for.cond.cleanup: 1195 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1196 // CHECK3: omp.inner.for.body: 1197 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1198 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1199 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1200 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1201 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 1202 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 1203 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] 1204 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 1205 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 1206 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]] 1207 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) 1208 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 1209 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 1210 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 1211 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4 1212 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1213 // CHECK3: omp.body.continue: 1214 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1215 // CHECK3: omp.inner.for.inc: 1216 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1217 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 1218 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 1219 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1220 // CHECK3: omp.inner.for.end: 1221 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1222 // CHECK3: omp.loop.exit: 1223 // CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1224 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 1225 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) 1226 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1227 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1228 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 1229 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1230 // CHECK3: arraydestroy.body: 1231 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1232 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1233 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1234 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 1235 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 1236 // CHECK3: arraydestroy.done6: 1237 // CHECK3-NEXT: ret void 1238 // 1239 // 1240 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1241 // CHECK3-SAME: () #[[ATTR1]] comdat { 1242 // CHECK3-NEXT: entry: 1243 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1244 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1245 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1246 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1247 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1248 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 1249 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1250 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 1251 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1252 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1253 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 1254 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 1255 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 1256 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 1257 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1258 // CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 1259 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 1260 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1261 // CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4 1262 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1263 // CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4 1264 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1265 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 1266 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1267 // CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4 1268 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1269 // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 1270 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1271 // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 1272 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1273 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1274 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1275 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 1276 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1277 // CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8 1278 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1279 // CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8 1280 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1281 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 1282 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1283 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 1284 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1285 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 1286 // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 1287 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1288 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1289 // CHECK3: omp_offload.failed: 1290 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 1291 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1292 // CHECK3: omp_offload.cont: 1293 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1294 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1295 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1296 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1297 // CHECK3: arraydestroy.body: 1298 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1299 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1300 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1301 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1302 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1303 // CHECK3: arraydestroy.done2: 1304 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1305 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 1306 // CHECK3-NEXT: ret i32 [[TMP16]] 1307 // 1308 // 1309 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1310 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1311 // CHECK3-NEXT: entry: 1312 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1313 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1314 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1315 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1316 // CHECK3-NEXT: ret void 1317 // 1318 // 1319 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1320 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1321 // CHECK3-NEXT: entry: 1322 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1323 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1324 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1325 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1326 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1327 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1328 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1329 // CHECK3-NEXT: ret void 1330 // 1331 // 1332 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1333 // CHECK3-SAME: () #[[ATTR4]] { 1334 // CHECK3-NEXT: entry: 1335 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined) 1336 // CHECK3-NEXT: ret void 1337 // 1338 // 1339 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 1340 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1341 // CHECK3-NEXT: entry: 1342 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1343 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1344 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1345 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1346 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 1347 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1348 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1349 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1350 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1351 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1352 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1353 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1354 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1355 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 1356 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1357 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1358 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1359 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 1360 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1361 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1362 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1363 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1364 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1365 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1366 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1367 // CHECK3: arrayctor.loop: 1368 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1369 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1370 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 1371 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1372 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1373 // CHECK3: arrayctor.cont: 1374 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1375 // CHECK3-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 4 1376 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1377 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1378 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1379 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1380 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1381 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1382 // CHECK3: cond.true: 1383 // CHECK3-NEXT: br label [[COND_END:%.*]] 1384 // CHECK3: cond.false: 1385 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1386 // CHECK3-NEXT: br label [[COND_END]] 1387 // CHECK3: cond.end: 1388 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1389 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1390 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1391 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1392 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1393 // CHECK3: omp.inner.for.cond: 1394 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1395 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1396 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1397 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1398 // CHECK3: omp.inner.for.cond.cleanup: 1399 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1400 // CHECK3: omp.inner.for.body: 1401 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1402 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1403 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]]) 1404 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1405 // CHECK3: omp.inner.for.inc: 1406 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1407 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1408 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] 1409 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 1410 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1411 // CHECK3: omp.inner.for.end: 1412 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1413 // CHECK3: omp.loop.exit: 1414 // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1415 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 1416 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) 1417 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1418 // CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1419 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2 1420 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1421 // CHECK3: arraydestroy.body: 1422 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1423 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1424 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1425 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 1426 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 1427 // CHECK3: arraydestroy.done5: 1428 // CHECK3-NEXT: ret void 1429 // 1430 // 1431 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined 1432 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 1433 // CHECK3-NEXT: entry: 1434 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1435 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1436 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 1437 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 1438 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1439 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1440 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 1441 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1442 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1443 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1444 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1445 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1446 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1447 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1448 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1449 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 1450 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1451 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1452 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1453 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1454 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1455 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 1456 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1457 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1458 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1459 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1460 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4 1461 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 1462 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1463 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1464 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1465 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1466 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1467 // CHECK3: arrayctor.loop: 1468 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1469 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1470 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 1471 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1472 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1473 // CHECK3: arrayctor.cont: 1474 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1475 // CHECK3-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 4 1476 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1477 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1478 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1479 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1480 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 1481 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1482 // CHECK3: cond.true: 1483 // CHECK3-NEXT: br label [[COND_END:%.*]] 1484 // CHECK3: cond.false: 1485 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1486 // CHECK3-NEXT: br label [[COND_END]] 1487 // CHECK3: cond.end: 1488 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1489 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1490 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1491 // CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1492 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1493 // CHECK3: omp.inner.for.cond: 1494 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1495 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1496 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1497 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1498 // CHECK3: omp.inner.for.cond.cleanup: 1499 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1500 // CHECK3: omp.inner.for.body: 1501 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1502 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1503 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1504 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1505 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 1506 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 1507 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] 1508 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 1509 // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4 1510 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 1511 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] 1512 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false) 1513 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1514 // CHECK3: omp.body.continue: 1515 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1516 // CHECK3: omp.inner.for.inc: 1517 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1518 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 1519 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 1520 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1521 // CHECK3: omp.inner.for.end: 1522 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1523 // CHECK3: omp.loop.exit: 1524 // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1525 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 1526 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) 1527 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1528 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1529 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 1530 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1531 // CHECK3: arraydestroy.body: 1532 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1533 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1534 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1535 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 1536 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1537 // CHECK3: arraydestroy.done7: 1538 // CHECK3-NEXT: ret void 1539 // 1540 // 1541 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1542 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1543 // CHECK3-NEXT: entry: 1544 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1545 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1546 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1547 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1548 // CHECK3-NEXT: ret void 1549 // 1550 // 1551 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1552 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1553 // CHECK3-NEXT: entry: 1554 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1555 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1556 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1557 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1558 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1559 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1560 // CHECK3-NEXT: ret void 1561 // 1562 // 1563 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1564 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1565 // CHECK3-NEXT: entry: 1566 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1567 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1568 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1569 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1570 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1571 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1572 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1573 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1574 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1575 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1576 // CHECK3-NEXT: ret void 1577 // 1578 // 1579 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1580 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1581 // CHECK3-NEXT: entry: 1582 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1583 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1584 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1585 // CHECK3-NEXT: ret void 1586 // 1587 // 1588 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp 1589 // CHECK3-SAME: () #[[ATTR0]] { 1590 // CHECK3-NEXT: entry: 1591 // CHECK3-NEXT: call void @__cxx_global_var_init() 1592 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1593 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1594 // CHECK3-NEXT: ret void 1595 // 1596 // 1597 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 1598 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 1599 // CHECK9-NEXT: entry: 1600 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 1601 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 1602 // CHECK9-NEXT: ret void 1603 // 1604 // 1605 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1606 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 1607 // CHECK9-NEXT: entry: 1608 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1609 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1610 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1611 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1612 // CHECK9-NEXT: ret void 1613 // 1614 // 1615 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1616 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1617 // CHECK9-NEXT: entry: 1618 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1619 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1620 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1621 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1622 // CHECK9-NEXT: ret void 1623 // 1624 // 1625 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1626 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1627 // CHECK9-NEXT: entry: 1628 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1629 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1630 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1631 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1632 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1633 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1634 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 1635 // CHECK9-NEXT: ret void 1636 // 1637 // 1638 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1639 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1640 // CHECK9-NEXT: entry: 1641 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1642 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1643 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1644 // CHECK9-NEXT: ret void 1645 // 1646 // 1647 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1648 // CHECK9-SAME: () #[[ATTR0]] { 1649 // CHECK9-NEXT: entry: 1650 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 1651 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 1652 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 1653 // CHECK9-NEXT: ret void 1654 // 1655 // 1656 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1657 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1658 // CHECK9-NEXT: entry: 1659 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1660 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1661 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1662 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1663 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1664 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1665 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1666 // CHECK9-NEXT: ret void 1667 // 1668 // 1669 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1670 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1671 // CHECK9-NEXT: entry: 1672 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1673 // CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1674 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1675 // CHECK9: arraydestroy.body: 1676 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1677 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1678 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1679 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1680 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1681 // CHECK9: arraydestroy.done1: 1682 // CHECK9-NEXT: ret void 1683 // 1684 // 1685 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1686 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1687 // CHECK9-NEXT: entry: 1688 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1689 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1690 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1691 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1692 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1693 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1694 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1695 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1696 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1697 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1698 // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 1699 // CHECK9-NEXT: ret void 1700 // 1701 // 1702 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1703 // CHECK9-SAME: () #[[ATTR0]] { 1704 // CHECK9-NEXT: entry: 1705 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1706 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1707 // CHECK9-NEXT: ret void 1708 // 1709 // 1710 // CHECK9-LABEL: define {{[^@]+}}@main 1711 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 1712 // CHECK9-NEXT: entry: 1713 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1714 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1715 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 1716 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 1717 // CHECK9-NEXT: ret i32 0 1718 // 1719 // 1720 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 1721 // CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR4:[0-9]+]] { 1722 // CHECK9-NEXT: entry: 1723 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 1724 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1725 // CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 1726 // CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 1727 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined) 1728 // CHECK9-NEXT: ret void 1729 // 1730 // 1731 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined 1732 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1733 // CHECK9-NEXT: entry: 1734 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1735 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1736 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1737 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1738 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1739 // CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1740 // CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1741 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1742 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1743 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 1744 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 1745 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 1746 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1747 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1748 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1749 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1750 // CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 8 1751 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1752 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1753 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1754 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1755 // CHECK9-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 8 1756 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1757 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1758 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1759 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1760 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1761 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1762 // CHECK9: cond.true: 1763 // CHECK9-NEXT: br label [[COND_END:%.*]] 1764 // CHECK9: cond.false: 1765 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1766 // CHECK9-NEXT: br label [[COND_END]] 1767 // CHECK9: cond.end: 1768 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1769 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1770 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1771 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1772 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1773 // CHECK9: omp.inner.for.cond: 1774 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1775 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1776 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1777 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1778 // CHECK9: omp.inner.for.body: 1779 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1780 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 1781 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1782 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 1783 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) 1784 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1785 // CHECK9: omp.inner.for.inc: 1786 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1787 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1788 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 1789 // CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 1790 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 1791 // CHECK9: omp.inner.for.end: 1792 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1793 // CHECK9: omp.loop.exit: 1794 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1795 // CHECK9-NEXT: ret void 1796 // 1797 // 1798 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined.omp_outlined 1799 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 1800 // CHECK9-NEXT: entry: 1801 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1802 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1803 // CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1804 // CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1805 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1806 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1807 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1808 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1809 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1810 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1811 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1812 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 1813 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 1814 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 1815 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1816 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1817 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1818 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1819 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1820 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1821 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1822 // CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 8 1823 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1824 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1825 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1826 // CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 1827 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1828 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 1829 // CHECK9-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1830 // CHECK9-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 1831 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1832 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1833 // CHECK9-NEXT: store ptr [[G1]], ptr [[_TMP3]], align 8 1834 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1835 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1836 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1837 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1838 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 1839 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1840 // CHECK9: cond.true: 1841 // CHECK9-NEXT: br label [[COND_END:%.*]] 1842 // CHECK9: cond.false: 1843 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1844 // CHECK9-NEXT: br label [[COND_END]] 1845 // CHECK9: cond.end: 1846 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1847 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1848 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1849 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1850 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1851 // CHECK9: omp.inner.for.cond: 1852 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1853 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1854 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1855 // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1856 // CHECK9: omp.inner.for.body: 1857 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1858 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1859 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1860 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1861 // CHECK9-NEXT: store i32 1, ptr [[G]], align 4 1862 // CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8 1863 // CHECK9-NEXT: store volatile i32 1, ptr [[TMP10]], align 4 1864 // CHECK9-NEXT: store i32 2, ptr [[SIVAR]], align 4 1865 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 1866 // CHECK9-NEXT: store ptr [[G]], ptr [[TMP11]], align 8 1867 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 1868 // CHECK9-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8 1869 // CHECK9-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 1870 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 1871 // CHECK9-NEXT: store ptr [[SIVAR]], ptr [[TMP14]], align 8 1872 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 1873 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1874 // CHECK9: omp.body.continue: 1875 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1876 // CHECK9: omp.inner.for.inc: 1877 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1878 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 1879 // CHECK9-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 1880 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 1881 // CHECK9: omp.inner.for.end: 1882 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1883 // CHECK9: omp.loop.exit: 1884 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 1885 // CHECK9-NEXT: ret void 1886 // 1887 // 1888 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp 1889 // CHECK9-SAME: () #[[ATTR0]] { 1890 // CHECK9-NEXT: entry: 1891 // CHECK9-NEXT: call void @__cxx_global_var_init() 1892 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 1893 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 1894 // CHECK9-NEXT: ret void 1895 // 1896