1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s 4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 5 6 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 7 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 9 10 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK5 11 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s 12 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 13 14 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s 16 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 17 18 // expected-no-diagnostics 19 #ifndef HEADER 20 #define HEADER 21 22 typedef __INTPTR_TYPE__ intptr_t; 23 24 25 void foo(); 26 27 struct S { 28 intptr_t a, b, c; 29 S(intptr_t a) : a(a) {} 30 operator char() { return a; } 31 ~S() {} 32 }; 33 34 template <typename T, int C> 35 int tmain() { 36 #pragma omp target 37 #pragma omp teams distribute parallel for num_threads(C) 38 for (int i = 0; i < 100; i++) 39 foo(); 40 #pragma omp target 41 #pragma omp teams distribute parallel for num_threads(T(23)) 42 for (int i = 0; i < 100; i++) 43 foo(); 44 return 0; 45 } 46 47 int main() { 48 S s(0); 49 char a = s; 50 #pragma omp target 51 #pragma omp teams distribute parallel for num_threads(2) 52 for (int i = 0; i < 100; i++) { 53 foo(); 54 } 55 #pragma omp target 56 57 #pragma omp teams distribute parallel for num_threads(a) 58 for (int i = 0; i < 100; i++) { 59 foo(); 60 } 61 return a + tmain<char, 5>() + tmain<S, 1>(); 62 } 63 64 // tmain 5 65 66 // tmain 1 67 68 69 70 71 72 73 74 75 #endif 76 // CHECK1-LABEL: define {{[^@]+}}@main 77 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__gxx_personality_v0 { 78 // CHECK1-NEXT: entry: 79 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 80 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 81 // CHECK1-NEXT: [[A:%.*]] = alloca i8, align 1 82 // CHECK1-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 83 // CHECK1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 84 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 85 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 86 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 87 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 88 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 89 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 90 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 91 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 92 // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 93 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 94 // CHECK1-NEXT: call void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[S]], i64 noundef 0) 95 // CHECK1-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) 96 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] 97 // CHECK1: invoke.cont: 98 // CHECK1-NEXT: store i8 [[CALL]], ptr [[A]], align 1 99 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 100 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 101 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 102 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 103 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 104 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 105 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 106 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 107 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 108 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 109 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 110 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 111 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 112 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 113 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 114 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 115 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 116 // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 117 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 118 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 119 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 120 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 121 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 122 // CHECK1-NEXT: store [3 x i32] [i32 2, i32 0, i32 0], ptr [[TMP11]], align 4 123 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 124 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 125 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 2, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.region_id, ptr [[KERNEL_ARGS]]) 126 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 127 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 128 // CHECK1: omp_offload.failed: 129 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50() #[[ATTR4:[0-9]+]] 130 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 131 // CHECK1: lpad: 132 // CHECK1-NEXT: [[TMP15:%.*]] = landingpad { ptr, i32 } 133 // CHECK1-NEXT: cleanup 134 // CHECK1-NEXT: [[TMP16:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 0 135 // CHECK1-NEXT: store ptr [[TMP16]], ptr [[EXN_SLOT]], align 8 136 // CHECK1-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 1 137 // CHECK1-NEXT: store i32 [[TMP17]], ptr [[EHSELECTOR_SLOT]], align 4 138 // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR4]] 139 // CHECK1-NEXT: br label [[EH_RESUME:%.*]] 140 // CHECK1: omp_offload.cont: 141 // CHECK1-NEXT: [[TMP18:%.*]] = load i8, ptr [[A]], align 1 142 // CHECK1-NEXT: store i8 [[TMP18]], ptr [[A_CASTED]], align 1 143 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[A_CASTED]], align 8 144 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 145 // CHECK1-NEXT: store i64 [[TMP19]], ptr [[TMP20]], align 8 146 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 147 // CHECK1-NEXT: store i64 [[TMP19]], ptr [[TMP21]], align 8 148 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 149 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 150 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 151 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 152 // CHECK1-NEXT: [[TMP25:%.*]] = load i8, ptr [[A]], align 1 153 // CHECK1-NEXT: store i8 [[TMP25]], ptr [[DOTCAPTURE_EXPR_]], align 1 154 // CHECK1-NEXT: [[TMP26:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 155 // CHECK1-NEXT: [[TMP27:%.*]] = zext i8 [[TMP26]] to i32 156 // CHECK1-NEXT: [[TMP28:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP27]], 0 157 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 158 // CHECK1-NEXT: store i32 3, ptr [[TMP29]], align 4 159 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 160 // CHECK1-NEXT: store i32 1, ptr [[TMP30]], align 4 161 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 162 // CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP31]], align 8 163 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3 164 // CHECK1-NEXT: store ptr [[TMP24]], ptr [[TMP32]], align 8 165 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4 166 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP33]], align 8 167 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5 168 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP34]], align 8 169 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6 170 // CHECK1-NEXT: store ptr null, ptr [[TMP35]], align 8 171 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 172 // CHECK1-NEXT: store ptr null, ptr [[TMP36]], align 8 173 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 174 // CHECK1-NEXT: store i64 100, ptr [[TMP37]], align 8 175 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9 176 // CHECK1-NEXT: store i64 0, ptr [[TMP38]], align 8 177 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10 178 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 4 179 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11 180 // CHECK1-NEXT: store [3 x i32] [[TMP28]], ptr [[TMP40]], align 4 181 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12 182 // CHECK1-NEXT: store i32 0, ptr [[TMP41]], align 4 183 // CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 [[TMP27]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.region_id, ptr [[KERNEL_ARGS2]]) 184 // CHECK1-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 185 // CHECK1-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 186 // CHECK1: omp_offload.failed3: 187 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55(i64 [[TMP19]]) #[[ATTR4]] 188 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] 189 // CHECK1: omp_offload.cont4: 190 // CHECK1-NEXT: [[TMP44:%.*]] = load i8, ptr [[A]], align 1 191 // CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP44]] to i32 192 // CHECK1-NEXT: [[CALL6:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() 193 // CHECK1-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] 194 // CHECK1: invoke.cont5: 195 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL6]] 196 // CHECK1-NEXT: [[CALL8:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() 197 // CHECK1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] 198 // CHECK1: invoke.cont7: 199 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] 200 // CHECK1-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 201 // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR4]] 202 // CHECK1-NEXT: [[TMP45:%.*]] = load i32, ptr [[RETVAL]], align 4 203 // CHECK1-NEXT: ret i32 [[TMP45]] 204 // CHECK1: eh.resume: 205 // CHECK1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 206 // CHECK1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 207 // CHECK1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 208 // CHECK1-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 209 // CHECK1-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] 210 // 211 // 212 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC1El 213 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 214 // CHECK1-NEXT: entry: 215 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 216 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 217 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 218 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 219 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 220 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 221 // CHECK1-NEXT: call void @_ZN1SC2El(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]]) 222 // CHECK1-NEXT: ret void 223 // 224 // 225 // CHECK1-LABEL: define {{[^@]+}}@_ZN1ScvcEv 226 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat { 227 // CHECK1-NEXT: entry: 228 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 229 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 230 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 231 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 232 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 233 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 234 // CHECK1-NEXT: ret i8 [[CONV]] 235 // 236 // 237 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50 238 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 239 // CHECK1-NEXT: entry: 240 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined) 241 // CHECK1-NEXT: ret void 242 // 243 // 244 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined 245 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 246 // CHECK1-NEXT: entry: 247 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 248 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 249 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 250 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 251 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 252 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 253 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 254 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 255 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 256 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 257 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 258 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 259 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 260 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 261 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 262 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 263 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 264 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 265 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 266 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 267 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 268 // CHECK1: cond.true: 269 // CHECK1-NEXT: br label [[COND_END:%.*]] 270 // CHECK1: cond.false: 271 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 272 // CHECK1-NEXT: br label [[COND_END]] 273 // CHECK1: cond.end: 274 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 275 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 276 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 277 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 278 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 279 // CHECK1: omp.inner.for.cond: 280 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 281 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 282 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 283 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 284 // CHECK1: omp.inner.for.body: 285 // CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 2) 286 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 287 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 288 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 289 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 290 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) 291 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 292 // CHECK1: omp.inner.for.inc: 293 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 294 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 295 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 296 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 297 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 298 // CHECK1: omp.inner.for.end: 299 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 300 // CHECK1: omp.loop.exit: 301 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 302 // CHECK1-NEXT: ret void 303 // 304 // 305 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined.omp_outlined 306 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 307 // CHECK1-NEXT: entry: 308 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 309 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 310 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 311 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 312 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 313 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 314 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 315 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 316 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 317 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 318 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 319 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 320 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 321 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 322 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 323 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 324 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 325 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 326 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 327 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 328 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 329 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 330 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 331 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 332 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 333 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 334 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 335 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 336 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 337 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 338 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 339 // CHECK1: cond.true: 340 // CHECK1-NEXT: br label [[COND_END:%.*]] 341 // CHECK1: cond.false: 342 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 343 // CHECK1-NEXT: br label [[COND_END]] 344 // CHECK1: cond.end: 345 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 346 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 347 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 348 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 349 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 350 // CHECK1: omp.inner.for.cond: 351 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 352 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 353 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 354 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 355 // CHECK1: omp.inner.for.body: 356 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 357 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 358 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 359 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 360 // CHECK1-NEXT: invoke void @_Z3foov() 361 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 362 // CHECK1: invoke.cont: 363 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 364 // CHECK1: omp.body.continue: 365 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 366 // CHECK1: omp.inner.for.inc: 367 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 368 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 369 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 370 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 371 // CHECK1: omp.inner.for.end: 372 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 373 // CHECK1: omp.loop.exit: 374 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 375 // CHECK1-NEXT: ret void 376 // CHECK1: terminate.lpad: 377 // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } 378 // CHECK1-NEXT: catch ptr null 379 // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 380 // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR7:[0-9]+]] 381 // CHECK1-NEXT: unreachable 382 // 383 // 384 // CHECK1-LABEL: define {{[^@]+}}@__clang_call_terminate 385 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat { 386 // CHECK1-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR4]] 387 // CHECK1-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] 388 // CHECK1-NEXT: unreachable 389 // 390 // 391 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 392 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { 393 // CHECK1-NEXT: entry: 394 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 395 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 396 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 397 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 398 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, ptr [[A_ADDR]], align 1 399 // CHECK1-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 1 400 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 401 // CHECK1-NEXT: store i8 [[TMP1]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 402 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 403 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined, i64 [[TMP2]]) 404 // CHECK1-NEXT: ret void 405 // 406 // 407 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined 408 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 409 // CHECK1-NEXT: entry: 410 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 411 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 412 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 413 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 414 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 415 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 416 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 417 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 418 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 419 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 420 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 421 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 422 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 423 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 424 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 425 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 426 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 427 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 428 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 429 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 430 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 431 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 432 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 433 // CHECK1: cond.true: 434 // CHECK1-NEXT: br label [[COND_END:%.*]] 435 // CHECK1: cond.false: 436 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 437 // CHECK1-NEXT: br label [[COND_END]] 438 // CHECK1: cond.end: 439 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 440 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 441 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 442 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 443 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 444 // CHECK1: omp.inner.for.cond: 445 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 446 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 447 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 448 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 449 // CHECK1: omp.inner.for.body: 450 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 451 // CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 452 // CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) 453 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 454 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 455 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 456 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 457 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined.omp_outlined, i64 [[TMP10]], i64 [[TMP12]]) 458 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 459 // CHECK1: omp.inner.for.inc: 460 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 461 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 462 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 463 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 464 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 465 // CHECK1: omp.inner.for.end: 466 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 467 // CHECK1: omp.loop.exit: 468 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 469 // CHECK1-NEXT: ret void 470 // 471 // 472 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined.omp_outlined 473 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 474 // CHECK1-NEXT: entry: 475 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 476 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 477 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 478 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 479 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 480 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 481 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 482 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 483 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 484 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 485 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 486 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 487 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 488 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 489 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 490 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 491 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 492 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 493 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 494 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 495 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 496 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 497 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 498 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 499 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 500 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 501 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 502 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 503 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 504 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 505 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 506 // CHECK1: cond.true: 507 // CHECK1-NEXT: br label [[COND_END:%.*]] 508 // CHECK1: cond.false: 509 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 510 // CHECK1-NEXT: br label [[COND_END]] 511 // CHECK1: cond.end: 512 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 513 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 514 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 515 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 516 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 517 // CHECK1: omp.inner.for.cond: 518 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 519 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 520 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 521 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 522 // CHECK1: omp.inner.for.body: 523 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 524 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 525 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 526 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 527 // CHECK1-NEXT: invoke void @_Z3foov() 528 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 529 // CHECK1: invoke.cont: 530 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 531 // CHECK1: omp.body.continue: 532 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 533 // CHECK1: omp.inner.for.inc: 534 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 535 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 536 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 537 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 538 // CHECK1: omp.inner.for.end: 539 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 540 // CHECK1: omp.loop.exit: 541 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 542 // CHECK1-NEXT: ret void 543 // CHECK1: terminate.lpad: 544 // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } 545 // CHECK1-NEXT: catch ptr null 546 // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 547 // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR7]] 548 // CHECK1-NEXT: unreachable 549 // 550 // 551 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv 552 // CHECK1-SAME: () #[[ATTR2]] comdat { 553 // CHECK1-NEXT: entry: 554 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 555 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 556 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 557 // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 558 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 559 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 560 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 561 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 562 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 563 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 564 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 565 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 566 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 567 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 568 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 569 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 570 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 571 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 572 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 573 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 574 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 575 // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 576 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 577 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 578 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 579 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 580 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 581 // CHECK1-NEXT: store [3 x i32] [i32 5, i32 0, i32 0], ptr [[TMP11]], align 4 582 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 583 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 584 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 5, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.region_id, ptr [[KERNEL_ARGS]]) 585 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 586 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 587 // CHECK1: omp_offload.failed: 588 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36() #[[ATTR4]] 589 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 590 // CHECK1: omp_offload.cont: 591 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 592 // CHECK1-NEXT: store i32 3, ptr [[TMP15]], align 4 593 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 594 // CHECK1-NEXT: store i32 0, ptr [[TMP16]], align 4 595 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 596 // CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8 597 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3 598 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 599 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4 600 // CHECK1-NEXT: store ptr null, ptr [[TMP19]], align 8 601 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5 602 // CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8 603 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6 604 // CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8 605 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 606 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 607 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 608 // CHECK1-NEXT: store i64 100, ptr [[TMP23]], align 8 609 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9 610 // CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 8 611 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10 612 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4 613 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11 614 // CHECK1-NEXT: store [3 x i32] [i32 23, i32 0, i32 0], ptr [[TMP26]], align 4 615 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12 616 // CHECK1-NEXT: store i32 0, ptr [[TMP27]], align 4 617 // CHECK1-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 23, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.region_id, ptr [[KERNEL_ARGS2]]) 618 // CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 619 // CHECK1-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 620 // CHECK1: omp_offload.failed3: 621 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40() #[[ATTR4]] 622 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] 623 // CHECK1: omp_offload.cont4: 624 // CHECK1-NEXT: ret i32 0 625 // 626 // 627 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv 628 // CHECK1-SAME: () #[[ATTR2]] comdat personality ptr @__gxx_personality_v0 { 629 // CHECK1-NEXT: entry: 630 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 631 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 632 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 633 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 634 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 635 // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 636 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 637 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 638 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 639 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 640 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 641 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 642 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 643 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 644 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 645 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 646 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 647 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 648 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 649 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 650 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 651 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 652 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 653 // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 654 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 655 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 656 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 657 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 658 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 659 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4 660 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 661 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 662 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.region_id, ptr [[KERNEL_ARGS]]) 663 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 664 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 665 // CHECK1: omp_offload.failed: 666 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR4]] 667 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 668 // CHECK1: omp_offload.cont: 669 // CHECK1-NEXT: invoke void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) 670 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 671 // CHECK1: invoke.cont: 672 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 673 // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] 674 // CHECK1-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 675 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 676 // CHECK1-NEXT: [[TMP16:%.*]] = zext i8 [[TMP15]] to i32 677 // CHECK1-NEXT: [[TMP17:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP16]], 0 678 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 679 // CHECK1-NEXT: store i32 3, ptr [[TMP18]], align 4 680 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 681 // CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4 682 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 683 // CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8 684 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3 685 // CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8 686 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4 687 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 688 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5 689 // CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8 690 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6 691 // CHECK1-NEXT: store ptr null, ptr [[TMP24]], align 8 692 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 693 // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 694 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 695 // CHECK1-NEXT: store i64 100, ptr [[TMP26]], align 8 696 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9 697 // CHECK1-NEXT: store i64 0, ptr [[TMP27]], align 8 698 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10 699 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 700 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11 701 // CHECK1-NEXT: store [3 x i32] [[TMP17]], ptr [[TMP29]], align 4 702 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12 703 // CHECK1-NEXT: store i32 0, ptr [[TMP30]], align 4 704 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 [[TMP16]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.region_id, ptr [[KERNEL_ARGS2]]) 705 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 706 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 707 // CHECK1: omp_offload.failed3: 708 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40() #[[ATTR4]] 709 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] 710 // CHECK1: omp_offload.cont4: 711 // CHECK1-NEXT: ret i32 0 712 // CHECK1: terminate.lpad: 713 // CHECK1-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 } 714 // CHECK1-NEXT: catch ptr null 715 // CHECK1-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0 716 // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP34]]) #[[ATTR7]] 717 // CHECK1-NEXT: unreachable 718 // 719 // 720 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev 721 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 722 // CHECK1-NEXT: entry: 723 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 724 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 725 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 726 // CHECK1-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]] 727 // CHECK1-NEXT: ret void 728 // 729 // 730 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2El 731 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat { 732 // CHECK1-NEXT: entry: 733 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 734 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 735 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 736 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 737 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 738 // CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 739 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 740 // CHECK1-NEXT: store i64 [[TMP0]], ptr [[A2]], align 8 741 // CHECK1-NEXT: ret void 742 // 743 // 744 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev 745 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 746 // CHECK1-NEXT: entry: 747 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 748 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 749 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 750 // CHECK1-NEXT: ret void 751 // 752 // 753 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36 754 // CHECK1-SAME: () #[[ATTR3]] { 755 // CHECK1-NEXT: entry: 756 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined) 757 // CHECK1-NEXT: ret void 758 // 759 // 760 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined 761 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 762 // CHECK1-NEXT: entry: 763 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 764 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 765 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 766 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 767 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 768 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 769 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 770 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 771 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 772 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 773 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 774 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 775 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 776 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 777 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 778 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 779 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 780 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 781 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 782 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 783 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 784 // CHECK1: cond.true: 785 // CHECK1-NEXT: br label [[COND_END:%.*]] 786 // CHECK1: cond.false: 787 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 788 // CHECK1-NEXT: br label [[COND_END]] 789 // CHECK1: cond.end: 790 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 791 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 792 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 793 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 794 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 795 // CHECK1: omp.inner.for.cond: 796 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 797 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 798 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 799 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 800 // CHECK1: omp.inner.for.body: 801 // CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 5) 802 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 803 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 804 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 805 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 806 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) 807 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 808 // CHECK1: omp.inner.for.inc: 809 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 810 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 811 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 812 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 813 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 814 // CHECK1: omp.inner.for.end: 815 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 816 // CHECK1: omp.loop.exit: 817 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 818 // CHECK1-NEXT: ret void 819 // 820 // 821 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined.omp_outlined 822 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 823 // CHECK1-NEXT: entry: 824 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 825 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 826 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 827 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 828 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 829 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 830 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 831 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 832 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 833 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 834 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 835 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 836 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 837 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 838 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 839 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 840 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 841 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 842 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 843 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 844 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 845 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 846 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 847 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 848 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 849 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 850 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 851 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 852 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 853 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 854 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 855 // CHECK1: cond.true: 856 // CHECK1-NEXT: br label [[COND_END:%.*]] 857 // CHECK1: cond.false: 858 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 859 // CHECK1-NEXT: br label [[COND_END]] 860 // CHECK1: cond.end: 861 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 862 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 863 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 864 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 865 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 866 // CHECK1: omp.inner.for.cond: 867 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 868 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 869 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 870 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 871 // CHECK1: omp.inner.for.body: 872 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 873 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 874 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 875 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 876 // CHECK1-NEXT: invoke void @_Z3foov() 877 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 878 // CHECK1: invoke.cont: 879 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 880 // CHECK1: omp.body.continue: 881 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 882 // CHECK1: omp.inner.for.inc: 883 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 884 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 885 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 886 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 887 // CHECK1: omp.inner.for.end: 888 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 889 // CHECK1: omp.loop.exit: 890 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 891 // CHECK1-NEXT: ret void 892 // CHECK1: terminate.lpad: 893 // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } 894 // CHECK1-NEXT: catch ptr null 895 // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 896 // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR7]] 897 // CHECK1-NEXT: unreachable 898 // 899 // 900 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40 901 // CHECK1-SAME: () #[[ATTR3]] { 902 // CHECK1-NEXT: entry: 903 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined) 904 // CHECK1-NEXT: ret void 905 // 906 // 907 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined 908 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 909 // CHECK1-NEXT: entry: 910 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 911 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 912 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 913 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 914 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 915 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 916 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 917 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 918 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 919 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 920 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 921 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 922 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 923 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 924 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 925 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 926 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 927 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 928 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 929 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 930 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 931 // CHECK1: cond.true: 932 // CHECK1-NEXT: br label [[COND_END:%.*]] 933 // CHECK1: cond.false: 934 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 935 // CHECK1-NEXT: br label [[COND_END]] 936 // CHECK1: cond.end: 937 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 938 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 939 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 940 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 941 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 942 // CHECK1: omp.inner.for.cond: 943 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 944 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 945 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 946 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 947 // CHECK1: omp.inner.for.body: 948 // CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 23) 949 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 950 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 951 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 952 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 953 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) 954 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 955 // CHECK1: omp.inner.for.inc: 956 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 957 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 958 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 959 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 960 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 961 // CHECK1: omp.inner.for.end: 962 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 963 // CHECK1: omp.loop.exit: 964 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 965 // CHECK1-NEXT: ret void 966 // 967 // 968 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined.omp_outlined 969 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 970 // CHECK1-NEXT: entry: 971 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 972 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 973 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 974 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 975 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 976 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 977 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 978 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 979 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 980 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 981 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 982 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 983 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 984 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 985 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 986 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 987 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 988 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 989 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 990 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 991 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 992 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 993 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 994 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 995 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 996 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 997 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 998 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 999 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1000 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 1001 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1002 // CHECK1: cond.true: 1003 // CHECK1-NEXT: br label [[COND_END:%.*]] 1004 // CHECK1: cond.false: 1005 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1006 // CHECK1-NEXT: br label [[COND_END]] 1007 // CHECK1: cond.end: 1008 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1009 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1010 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1011 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1012 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1013 // CHECK1: omp.inner.for.cond: 1014 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1015 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1016 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1017 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1018 // CHECK1: omp.inner.for.body: 1019 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1020 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1021 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1022 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1023 // CHECK1-NEXT: invoke void @_Z3foov() 1024 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 1025 // CHECK1: invoke.cont: 1026 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1027 // CHECK1: omp.body.continue: 1028 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1029 // CHECK1: omp.inner.for.inc: 1030 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1031 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 1032 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 1033 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1034 // CHECK1: omp.inner.for.end: 1035 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1036 // CHECK1: omp.loop.exit: 1037 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 1038 // CHECK1-NEXT: ret void 1039 // CHECK1: terminate.lpad: 1040 // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } 1041 // CHECK1-NEXT: catch ptr null 1042 // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 1043 // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR7]] 1044 // CHECK1-NEXT: unreachable 1045 // 1046 // 1047 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36 1048 // CHECK1-SAME: () #[[ATTR3]] { 1049 // CHECK1-NEXT: entry: 1050 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined) 1051 // CHECK1-NEXT: ret void 1052 // 1053 // 1054 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined 1055 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 1056 // CHECK1-NEXT: entry: 1057 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1058 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1059 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1060 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1061 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1062 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1063 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1064 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1065 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1066 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1067 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1068 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1069 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 1070 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1071 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1072 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1073 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1074 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1075 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1076 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 1077 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1078 // CHECK1: cond.true: 1079 // CHECK1-NEXT: br label [[COND_END:%.*]] 1080 // CHECK1: cond.false: 1081 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1082 // CHECK1-NEXT: br label [[COND_END]] 1083 // CHECK1: cond.end: 1084 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1085 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1086 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1087 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1088 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1089 // CHECK1: omp.inner.for.cond: 1090 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1091 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1092 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1093 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1094 // CHECK1: omp.inner.for.body: 1095 // CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 1) 1096 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1097 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 1098 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1099 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 1100 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) 1101 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1102 // CHECK1: omp.inner.for.inc: 1103 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1104 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1105 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 1106 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 1107 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1108 // CHECK1: omp.inner.for.end: 1109 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1110 // CHECK1: omp.loop.exit: 1111 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1112 // CHECK1-NEXT: ret void 1113 // 1114 // 1115 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined.omp_outlined 1116 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 1117 // CHECK1-NEXT: entry: 1118 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1119 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1120 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1121 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1122 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1123 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1124 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1125 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1126 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1127 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1128 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1129 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1130 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1131 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1132 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1133 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1134 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 1135 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1136 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 1137 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1138 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 1139 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1140 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 1141 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1142 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1143 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1144 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1145 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1146 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1147 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 1148 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1149 // CHECK1: cond.true: 1150 // CHECK1-NEXT: br label [[COND_END:%.*]] 1151 // CHECK1: cond.false: 1152 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1153 // CHECK1-NEXT: br label [[COND_END]] 1154 // CHECK1: cond.end: 1155 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1156 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1157 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1158 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1159 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1160 // CHECK1: omp.inner.for.cond: 1161 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1162 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1163 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1164 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1165 // CHECK1: omp.inner.for.body: 1166 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1167 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1168 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1169 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1170 // CHECK1-NEXT: invoke void @_Z3foov() 1171 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 1172 // CHECK1: invoke.cont: 1173 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1174 // CHECK1: omp.body.continue: 1175 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1176 // CHECK1: omp.inner.for.inc: 1177 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1178 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 1179 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 1180 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1181 // CHECK1: omp.inner.for.end: 1182 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1183 // CHECK1: omp.loop.exit: 1184 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 1185 // CHECK1-NEXT: ret void 1186 // CHECK1: terminate.lpad: 1187 // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } 1188 // CHECK1-NEXT: catch ptr null 1189 // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 1190 // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR7]] 1191 // CHECK1-NEXT: unreachable 1192 // 1193 // 1194 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40 1195 // CHECK1-SAME: () #[[ATTR3]] personality ptr @__gxx_personality_v0 { 1196 // CHECK1-NEXT: entry: 1197 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1198 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 1199 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1200 // CHECK1-NEXT: invoke void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) 1201 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 1202 // CHECK1: invoke.cont: 1203 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 1204 // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] 1205 // CHECK1-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 1206 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 1207 // CHECK1-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 1208 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 1209 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined, i64 [[TMP1]]) 1210 // CHECK1-NEXT: ret void 1211 // CHECK1: terminate.lpad: 1212 // CHECK1-NEXT: [[TMP2:%.*]] = landingpad { ptr, i32 } 1213 // CHECK1-NEXT: catch ptr null 1214 // CHECK1-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0 1215 // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP3]]) #[[ATTR7]] 1216 // CHECK1-NEXT: unreachable 1217 // 1218 // 1219 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined 1220 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 1221 // CHECK1-NEXT: entry: 1222 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1223 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1224 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1225 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1226 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1227 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1228 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1229 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1230 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1231 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1232 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1233 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1234 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 1235 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1236 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 1237 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1238 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1239 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1240 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1241 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1242 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1243 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 1244 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1245 // CHECK1: cond.true: 1246 // CHECK1-NEXT: br label [[COND_END:%.*]] 1247 // CHECK1: cond.false: 1248 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1249 // CHECK1-NEXT: br label [[COND_END]] 1250 // CHECK1: cond.end: 1251 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1252 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1253 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1254 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1255 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1256 // CHECK1: omp.inner.for.cond: 1257 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1258 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1259 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1260 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1261 // CHECK1: omp.inner.for.body: 1262 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 1263 // CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 1264 // CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) 1265 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1266 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 1267 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1268 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 1269 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined.omp_outlined, i64 [[TMP10]], i64 [[TMP12]]) 1270 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1271 // CHECK1: omp.inner.for.inc: 1272 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1273 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1274 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 1275 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 1276 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1277 // CHECK1: omp.inner.for.end: 1278 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1279 // CHECK1: omp.loop.exit: 1280 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1281 // CHECK1-NEXT: ret void 1282 // 1283 // 1284 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined.omp_outlined 1285 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 1286 // CHECK1-NEXT: entry: 1287 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1288 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1289 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1290 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1291 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1292 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1293 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1294 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1295 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1296 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1297 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1298 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1299 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1300 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1301 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1302 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1303 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 1304 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1305 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 1306 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1307 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 1308 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1309 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 1310 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1311 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1312 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1313 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1314 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1315 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1316 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 1317 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1318 // CHECK1: cond.true: 1319 // CHECK1-NEXT: br label [[COND_END:%.*]] 1320 // CHECK1: cond.false: 1321 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1322 // CHECK1-NEXT: br label [[COND_END]] 1323 // CHECK1: cond.end: 1324 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1325 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1326 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1327 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1328 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1329 // CHECK1: omp.inner.for.cond: 1330 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1331 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1332 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1333 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1334 // CHECK1: omp.inner.for.body: 1335 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1336 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1337 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1338 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1339 // CHECK1-NEXT: invoke void @_Z3foov() 1340 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 1341 // CHECK1: invoke.cont: 1342 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1343 // CHECK1: omp.body.continue: 1344 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1345 // CHECK1: omp.inner.for.inc: 1346 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1347 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 1348 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 1349 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1350 // CHECK1: omp.inner.for.end: 1351 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1352 // CHECK1: omp.loop.exit: 1353 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 1354 // CHECK1-NEXT: ret void 1355 // CHECK1: terminate.lpad: 1356 // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } 1357 // CHECK1-NEXT: catch ptr null 1358 // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 1359 // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR7]] 1360 // CHECK1-NEXT: unreachable 1361 // 1362 // 1363 // CHECK5-LABEL: define {{[^@]+}}@main 1364 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__gxx_personality_v0 { 1365 // CHECK5-NEXT: entry: 1366 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1367 // CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 1368 // CHECK5-NEXT: [[A:%.*]] = alloca i8, align 1 1369 // CHECK5-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 1370 // CHECK5-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 1371 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1372 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1373 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1374 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 1375 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 1376 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 1377 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1378 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1379 // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 1380 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 1381 // CHECK5-NEXT: call void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[S]], i64 noundef 0) 1382 // CHECK5-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) 1383 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] 1384 // CHECK5: invoke.cont: 1385 // CHECK5-NEXT: store i8 [[CALL]], ptr [[A]], align 1 1386 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1387 // CHECK5-NEXT: store i32 3, ptr [[TMP0]], align 4 1388 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1389 // CHECK5-NEXT: store i32 0, ptr [[TMP1]], align 4 1390 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1391 // CHECK5-NEXT: store ptr null, ptr [[TMP2]], align 8 1392 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1393 // CHECK5-NEXT: store ptr null, ptr [[TMP3]], align 8 1394 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1395 // CHECK5-NEXT: store ptr null, ptr [[TMP4]], align 8 1396 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1397 // CHECK5-NEXT: store ptr null, ptr [[TMP5]], align 8 1398 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1399 // CHECK5-NEXT: store ptr null, ptr [[TMP6]], align 8 1400 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1401 // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 1402 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1403 // CHECK5-NEXT: store i64 100, ptr [[TMP8]], align 8 1404 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1405 // CHECK5-NEXT: store i64 0, ptr [[TMP9]], align 8 1406 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1407 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 1408 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1409 // CHECK5-NEXT: store [3 x i32] [i32 2, i32 0, i32 0], ptr [[TMP11]], align 4 1410 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1411 // CHECK5-NEXT: store i32 0, ptr [[TMP12]], align 4 1412 // CHECK5-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 2, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.region_id, ptr [[KERNEL_ARGS]]) 1413 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1414 // CHECK5-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1415 // CHECK5: omp_offload.failed: 1416 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50() #[[ATTR4:[0-9]+]] 1417 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 1418 // CHECK5: lpad: 1419 // CHECK5-NEXT: [[TMP15:%.*]] = landingpad { ptr, i32 } 1420 // CHECK5-NEXT: cleanup 1421 // CHECK5-NEXT: [[TMP16:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 0 1422 // CHECK5-NEXT: store ptr [[TMP16]], ptr [[EXN_SLOT]], align 8 1423 // CHECK5-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 1 1424 // CHECK5-NEXT: store i32 [[TMP17]], ptr [[EHSELECTOR_SLOT]], align 4 1425 // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR4]] 1426 // CHECK5-NEXT: br label [[EH_RESUME:%.*]] 1427 // CHECK5: omp_offload.cont: 1428 // CHECK5-NEXT: [[TMP18:%.*]] = load i8, ptr [[A]], align 1 1429 // CHECK5-NEXT: store i8 [[TMP18]], ptr [[A_CASTED]], align 1 1430 // CHECK5-NEXT: [[TMP19:%.*]] = load i64, ptr [[A_CASTED]], align 8 1431 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1432 // CHECK5-NEXT: store i64 [[TMP19]], ptr [[TMP20]], align 8 1433 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1434 // CHECK5-NEXT: store i64 [[TMP19]], ptr [[TMP21]], align 8 1435 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1436 // CHECK5-NEXT: store ptr null, ptr [[TMP22]], align 8 1437 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1438 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1439 // CHECK5-NEXT: [[TMP25:%.*]] = load i8, ptr [[A]], align 1 1440 // CHECK5-NEXT: store i8 [[TMP25]], ptr [[DOTCAPTURE_EXPR_]], align 1 1441 // CHECK5-NEXT: [[TMP26:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 1442 // CHECK5-NEXT: [[TMP27:%.*]] = zext i8 [[TMP26]] to i32 1443 // CHECK5-NEXT: [[TMP28:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP27]], 0 1444 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 1445 // CHECK5-NEXT: store i32 3, ptr [[TMP29]], align 4 1446 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 1447 // CHECK5-NEXT: store i32 1, ptr [[TMP30]], align 4 1448 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 1449 // CHECK5-NEXT: store ptr [[TMP23]], ptr [[TMP31]], align 8 1450 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3 1451 // CHECK5-NEXT: store ptr [[TMP24]], ptr [[TMP32]], align 8 1452 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4 1453 // CHECK5-NEXT: store ptr @.offload_sizes, ptr [[TMP33]], align 8 1454 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5 1455 // CHECK5-NEXT: store ptr @.offload_maptypes, ptr [[TMP34]], align 8 1456 // CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6 1457 // CHECK5-NEXT: store ptr null, ptr [[TMP35]], align 8 1458 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 1459 // CHECK5-NEXT: store ptr null, ptr [[TMP36]], align 8 1460 // CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 1461 // CHECK5-NEXT: store i64 100, ptr [[TMP37]], align 8 1462 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9 1463 // CHECK5-NEXT: store i64 0, ptr [[TMP38]], align 8 1464 // CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10 1465 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 4 1466 // CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11 1467 // CHECK5-NEXT: store [3 x i32] [[TMP28]], ptr [[TMP40]], align 4 1468 // CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12 1469 // CHECK5-NEXT: store i32 0, ptr [[TMP41]], align 4 1470 // CHECK5-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 [[TMP27]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.region_id, ptr [[KERNEL_ARGS2]]) 1471 // CHECK5-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 1472 // CHECK5-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 1473 // CHECK5: omp_offload.failed3: 1474 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55(i64 [[TMP19]]) #[[ATTR4]] 1475 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]] 1476 // CHECK5: omp_offload.cont4: 1477 // CHECK5-NEXT: [[TMP44:%.*]] = load i8, ptr [[A]], align 1 1478 // CHECK5-NEXT: [[CONV:%.*]] = sext i8 [[TMP44]] to i32 1479 // CHECK5-NEXT: [[CALL6:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() 1480 // CHECK5-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] 1481 // CHECK5: invoke.cont5: 1482 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL6]] 1483 // CHECK5-NEXT: [[CALL8:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() 1484 // CHECK5-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] 1485 // CHECK5: invoke.cont7: 1486 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] 1487 // CHECK5-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 1488 // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR4]] 1489 // CHECK5-NEXT: [[TMP45:%.*]] = load i32, ptr [[RETVAL]], align 4 1490 // CHECK5-NEXT: ret i32 [[TMP45]] 1491 // CHECK5: eh.resume: 1492 // CHECK5-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 1493 // CHECK5-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 1494 // CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 1495 // CHECK5-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 1496 // CHECK5-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] 1497 // 1498 // 1499 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC1El 1500 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 1501 // CHECK5-NEXT: entry: 1502 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1503 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1504 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1505 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1506 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1507 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 1508 // CHECK5-NEXT: call void @_ZN1SC2El(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]]) 1509 // CHECK5-NEXT: ret void 1510 // 1511 // 1512 // CHECK5-LABEL: define {{[^@]+}}@_ZN1ScvcEv 1513 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat { 1514 // CHECK5-NEXT: entry: 1515 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1516 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1517 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1518 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1519 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 1520 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 1521 // CHECK5-NEXT: ret i8 [[CONV]] 1522 // 1523 // 1524 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50 1525 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 1526 // CHECK5-NEXT: entry: 1527 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined) 1528 // CHECK5-NEXT: ret void 1529 // 1530 // 1531 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined 1532 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 1533 // CHECK5-NEXT: entry: 1534 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1535 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1536 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1537 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1538 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1539 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1540 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1541 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1542 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1543 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1544 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1545 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1546 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 1547 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1548 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1549 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1550 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1551 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1552 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1553 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 1554 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1555 // CHECK5: cond.true: 1556 // CHECK5-NEXT: br label [[COND_END:%.*]] 1557 // CHECK5: cond.false: 1558 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1559 // CHECK5-NEXT: br label [[COND_END]] 1560 // CHECK5: cond.end: 1561 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1562 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1563 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1564 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1565 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1566 // CHECK5: omp.inner.for.cond: 1567 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1568 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1569 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1570 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1571 // CHECK5: omp.inner.for.body: 1572 // CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 2) 1573 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1574 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 1575 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1576 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 1577 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) 1578 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1579 // CHECK5: omp.inner.for.inc: 1580 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1581 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1582 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 1583 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 1584 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] 1585 // CHECK5: omp.inner.for.end: 1586 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1587 // CHECK5: omp.loop.exit: 1588 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1589 // CHECK5-NEXT: ret void 1590 // 1591 // 1592 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined.omp_outlined 1593 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 1594 // CHECK5-NEXT: entry: 1595 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1596 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1597 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1598 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1599 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1600 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1601 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1602 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1603 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1604 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1605 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1606 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1607 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1608 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1609 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1610 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1611 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 1612 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1613 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 1614 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1615 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 1616 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1617 // CHECK5-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 1618 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1619 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1620 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1621 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1622 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1623 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1624 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 1625 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1626 // CHECK5: cond.true: 1627 // CHECK5-NEXT: br label [[COND_END:%.*]] 1628 // CHECK5: cond.false: 1629 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1630 // CHECK5-NEXT: br label [[COND_END]] 1631 // CHECK5: cond.end: 1632 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1633 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1634 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1635 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1636 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1637 // CHECK5: omp.inner.for.cond: 1638 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1639 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1640 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1641 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1642 // CHECK5: omp.inner.for.body: 1643 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1644 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1645 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1646 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1647 // CHECK5-NEXT: invoke void @_Z3foov() 1648 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 1649 // CHECK5: invoke.cont: 1650 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1651 // CHECK5: omp.body.continue: 1652 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1653 // CHECK5: omp.inner.for.inc: 1654 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1655 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 1656 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 1657 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] 1658 // CHECK5: omp.inner.for.end: 1659 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1660 // CHECK5: omp.loop.exit: 1661 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 1662 // CHECK5-NEXT: ret void 1663 // CHECK5: terminate.lpad: 1664 // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } 1665 // CHECK5-NEXT: catch ptr null 1666 // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 1667 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR7:[0-9]+]] 1668 // CHECK5-NEXT: unreachable 1669 // 1670 // 1671 // CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate 1672 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat { 1673 // CHECK5-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR4]] 1674 // CHECK5-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] 1675 // CHECK5-NEXT: unreachable 1676 // 1677 // 1678 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 1679 // CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { 1680 // CHECK5-NEXT: entry: 1681 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1682 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1683 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1684 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1685 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, ptr [[A_ADDR]], align 1 1686 // CHECK5-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 1 1687 // CHECK5-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 1688 // CHECK5-NEXT: store i8 [[TMP1]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 1689 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 1690 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined, i64 [[TMP2]]) 1691 // CHECK5-NEXT: ret void 1692 // 1693 // 1694 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined 1695 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 1696 // CHECK5-NEXT: entry: 1697 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1698 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1699 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1700 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1701 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1702 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1703 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1704 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1705 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1706 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1707 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1708 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1709 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 1710 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1711 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 1712 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1713 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1714 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1715 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1716 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1717 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1718 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 1719 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1720 // CHECK5: cond.true: 1721 // CHECK5-NEXT: br label [[COND_END:%.*]] 1722 // CHECK5: cond.false: 1723 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1724 // CHECK5-NEXT: br label [[COND_END]] 1725 // CHECK5: cond.end: 1726 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1727 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1728 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1729 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1730 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1731 // CHECK5: omp.inner.for.cond: 1732 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1733 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1734 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1735 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1736 // CHECK5: omp.inner.for.body: 1737 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 1738 // CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 1739 // CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) 1740 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1741 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 1742 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1743 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 1744 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined.omp_outlined, i64 [[TMP10]], i64 [[TMP12]]) 1745 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1746 // CHECK5: omp.inner.for.inc: 1747 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1748 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1749 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 1750 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 1751 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] 1752 // CHECK5: omp.inner.for.end: 1753 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1754 // CHECK5: omp.loop.exit: 1755 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1756 // CHECK5-NEXT: ret void 1757 // 1758 // 1759 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined.omp_outlined 1760 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 1761 // CHECK5-NEXT: entry: 1762 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1763 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1764 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1765 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1766 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1767 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1768 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1769 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1770 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1771 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1772 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1773 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1774 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1775 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1776 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1777 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1778 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 1779 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1780 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 1781 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1782 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 1783 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1784 // CHECK5-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 1785 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1786 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1787 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1788 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1789 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1790 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1791 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 1792 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1793 // CHECK5: cond.true: 1794 // CHECK5-NEXT: br label [[COND_END:%.*]] 1795 // CHECK5: cond.false: 1796 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1797 // CHECK5-NEXT: br label [[COND_END]] 1798 // CHECK5: cond.end: 1799 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1800 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1801 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1802 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1803 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1804 // CHECK5: omp.inner.for.cond: 1805 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1806 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1807 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1808 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1809 // CHECK5: omp.inner.for.body: 1810 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1811 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1812 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1813 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1814 // CHECK5-NEXT: invoke void @_Z3foov() 1815 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 1816 // CHECK5: invoke.cont: 1817 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1818 // CHECK5: omp.body.continue: 1819 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1820 // CHECK5: omp.inner.for.inc: 1821 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1822 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 1823 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 1824 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] 1825 // CHECK5: omp.inner.for.end: 1826 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1827 // CHECK5: omp.loop.exit: 1828 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 1829 // CHECK5-NEXT: ret void 1830 // CHECK5: terminate.lpad: 1831 // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } 1832 // CHECK5-NEXT: catch ptr null 1833 // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 1834 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR7]] 1835 // CHECK5-NEXT: unreachable 1836 // 1837 // 1838 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv 1839 // CHECK5-SAME: () #[[ATTR2]] comdat { 1840 // CHECK5-NEXT: entry: 1841 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1842 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1843 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1844 // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 1845 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1846 // CHECK5-NEXT: store i32 3, ptr [[TMP0]], align 4 1847 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1848 // CHECK5-NEXT: store i32 0, ptr [[TMP1]], align 4 1849 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1850 // CHECK5-NEXT: store ptr null, ptr [[TMP2]], align 8 1851 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1852 // CHECK5-NEXT: store ptr null, ptr [[TMP3]], align 8 1853 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1854 // CHECK5-NEXT: store ptr null, ptr [[TMP4]], align 8 1855 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1856 // CHECK5-NEXT: store ptr null, ptr [[TMP5]], align 8 1857 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1858 // CHECK5-NEXT: store ptr null, ptr [[TMP6]], align 8 1859 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1860 // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 1861 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1862 // CHECK5-NEXT: store i64 100, ptr [[TMP8]], align 8 1863 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1864 // CHECK5-NEXT: store i64 0, ptr [[TMP9]], align 8 1865 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1866 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 1867 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1868 // CHECK5-NEXT: store [3 x i32] [i32 5, i32 0, i32 0], ptr [[TMP11]], align 4 1869 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1870 // CHECK5-NEXT: store i32 0, ptr [[TMP12]], align 4 1871 // CHECK5-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 5, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.region_id, ptr [[KERNEL_ARGS]]) 1872 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1873 // CHECK5-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1874 // CHECK5: omp_offload.failed: 1875 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36() #[[ATTR4]] 1876 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 1877 // CHECK5: omp_offload.cont: 1878 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 1879 // CHECK5-NEXT: store i32 3, ptr [[TMP15]], align 4 1880 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 1881 // CHECK5-NEXT: store i32 0, ptr [[TMP16]], align 4 1882 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 1883 // CHECK5-NEXT: store ptr null, ptr [[TMP17]], align 8 1884 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3 1885 // CHECK5-NEXT: store ptr null, ptr [[TMP18]], align 8 1886 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4 1887 // CHECK5-NEXT: store ptr null, ptr [[TMP19]], align 8 1888 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5 1889 // CHECK5-NEXT: store ptr null, ptr [[TMP20]], align 8 1890 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6 1891 // CHECK5-NEXT: store ptr null, ptr [[TMP21]], align 8 1892 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 1893 // CHECK5-NEXT: store ptr null, ptr [[TMP22]], align 8 1894 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 1895 // CHECK5-NEXT: store i64 100, ptr [[TMP23]], align 8 1896 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9 1897 // CHECK5-NEXT: store i64 0, ptr [[TMP24]], align 8 1898 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10 1899 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4 1900 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11 1901 // CHECK5-NEXT: store [3 x i32] [i32 23, i32 0, i32 0], ptr [[TMP26]], align 4 1902 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12 1903 // CHECK5-NEXT: store i32 0, ptr [[TMP27]], align 4 1904 // CHECK5-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 23, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.region_id, ptr [[KERNEL_ARGS2]]) 1905 // CHECK5-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 1906 // CHECK5-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 1907 // CHECK5: omp_offload.failed3: 1908 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40() #[[ATTR4]] 1909 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]] 1910 // CHECK5: omp_offload.cont4: 1911 // CHECK5-NEXT: ret i32 0 1912 // 1913 // 1914 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv 1915 // CHECK5-SAME: () #[[ATTR2]] comdat personality ptr @__gxx_personality_v0 { 1916 // CHECK5-NEXT: entry: 1917 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1918 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1919 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1920 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 1921 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1922 // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 1923 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1924 // CHECK5-NEXT: store i32 3, ptr [[TMP0]], align 4 1925 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1926 // CHECK5-NEXT: store i32 0, ptr [[TMP1]], align 4 1927 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1928 // CHECK5-NEXT: store ptr null, ptr [[TMP2]], align 8 1929 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1930 // CHECK5-NEXT: store ptr null, ptr [[TMP3]], align 8 1931 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1932 // CHECK5-NEXT: store ptr null, ptr [[TMP4]], align 8 1933 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1934 // CHECK5-NEXT: store ptr null, ptr [[TMP5]], align 8 1935 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1936 // CHECK5-NEXT: store ptr null, ptr [[TMP6]], align 8 1937 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1938 // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 1939 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1940 // CHECK5-NEXT: store i64 100, ptr [[TMP8]], align 8 1941 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1942 // CHECK5-NEXT: store i64 0, ptr [[TMP9]], align 8 1943 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1944 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 1945 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1946 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4 1947 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1948 // CHECK5-NEXT: store i32 0, ptr [[TMP12]], align 4 1949 // CHECK5-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.region_id, ptr [[KERNEL_ARGS]]) 1950 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1951 // CHECK5-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1952 // CHECK5: omp_offload.failed: 1953 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR4]] 1954 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 1955 // CHECK5: omp_offload.cont: 1956 // CHECK5-NEXT: invoke void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) 1957 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 1958 // CHECK5: invoke.cont: 1959 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 1960 // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] 1961 // CHECK5-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 1962 // CHECK5-NEXT: [[TMP15:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 1963 // CHECK5-NEXT: [[TMP16:%.*]] = zext i8 [[TMP15]] to i32 1964 // CHECK5-NEXT: [[TMP17:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP16]], 0 1965 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 1966 // CHECK5-NEXT: store i32 3, ptr [[TMP18]], align 4 1967 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 1968 // CHECK5-NEXT: store i32 0, ptr [[TMP19]], align 4 1969 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 1970 // CHECK5-NEXT: store ptr null, ptr [[TMP20]], align 8 1971 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3 1972 // CHECK5-NEXT: store ptr null, ptr [[TMP21]], align 8 1973 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4 1974 // CHECK5-NEXT: store ptr null, ptr [[TMP22]], align 8 1975 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5 1976 // CHECK5-NEXT: store ptr null, ptr [[TMP23]], align 8 1977 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6 1978 // CHECK5-NEXT: store ptr null, ptr [[TMP24]], align 8 1979 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 1980 // CHECK5-NEXT: store ptr null, ptr [[TMP25]], align 8 1981 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 1982 // CHECK5-NEXT: store i64 100, ptr [[TMP26]], align 8 1983 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9 1984 // CHECK5-NEXT: store i64 0, ptr [[TMP27]], align 8 1985 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10 1986 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 1987 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11 1988 // CHECK5-NEXT: store [3 x i32] [[TMP17]], ptr [[TMP29]], align 4 1989 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12 1990 // CHECK5-NEXT: store i32 0, ptr [[TMP30]], align 4 1991 // CHECK5-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 [[TMP16]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.region_id, ptr [[KERNEL_ARGS2]]) 1992 // CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1993 // CHECK5-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 1994 // CHECK5: omp_offload.failed3: 1995 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40() #[[ATTR4]] 1996 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]] 1997 // CHECK5: omp_offload.cont4: 1998 // CHECK5-NEXT: ret i32 0 1999 // CHECK5: terminate.lpad: 2000 // CHECK5-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 } 2001 // CHECK5-NEXT: catch ptr null 2002 // CHECK5-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0 2003 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP34]]) #[[ATTR7]] 2004 // CHECK5-NEXT: unreachable 2005 // 2006 // 2007 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev 2008 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 2009 // CHECK5-NEXT: entry: 2010 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2011 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2012 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2013 // CHECK5-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]] 2014 // CHECK5-NEXT: ret void 2015 // 2016 // 2017 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2El 2018 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat { 2019 // CHECK5-NEXT: entry: 2020 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2021 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2022 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2023 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 2024 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2025 // CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2026 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 2027 // CHECK5-NEXT: store i64 [[TMP0]], ptr [[A2]], align 8 2028 // CHECK5-NEXT: ret void 2029 // 2030 // 2031 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36 2032 // CHECK5-SAME: () #[[ATTR3]] { 2033 // CHECK5-NEXT: entry: 2034 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined) 2035 // CHECK5-NEXT: ret void 2036 // 2037 // 2038 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined 2039 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 2040 // CHECK5-NEXT: entry: 2041 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2042 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2043 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2044 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2045 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2046 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2047 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2048 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2049 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2050 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2051 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2052 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 2053 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 2054 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2055 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2056 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2057 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2058 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2059 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2060 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 2061 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2062 // CHECK5: cond.true: 2063 // CHECK5-NEXT: br label [[COND_END:%.*]] 2064 // CHECK5: cond.false: 2065 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2066 // CHECK5-NEXT: br label [[COND_END]] 2067 // CHECK5: cond.end: 2068 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2069 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2070 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2071 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2072 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2073 // CHECK5: omp.inner.for.cond: 2074 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2075 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2076 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2077 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2078 // CHECK5: omp.inner.for.body: 2079 // CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 5) 2080 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2081 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 2082 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2083 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 2084 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) 2085 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2086 // CHECK5: omp.inner.for.inc: 2087 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2088 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2089 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 2090 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 2091 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] 2092 // CHECK5: omp.inner.for.end: 2093 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2094 // CHECK5: omp.loop.exit: 2095 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2096 // CHECK5-NEXT: ret void 2097 // 2098 // 2099 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined.omp_outlined 2100 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 2101 // CHECK5-NEXT: entry: 2102 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2103 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2104 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 2105 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 2106 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2107 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2108 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2109 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2110 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2111 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2112 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2113 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2114 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2115 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2116 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2117 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2118 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 2119 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2120 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 2121 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2122 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 2123 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 2124 // CHECK5-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 2125 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2126 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2127 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2128 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 2129 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2130 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2131 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 2132 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2133 // CHECK5: cond.true: 2134 // CHECK5-NEXT: br label [[COND_END:%.*]] 2135 // CHECK5: cond.false: 2136 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2137 // CHECK5-NEXT: br label [[COND_END]] 2138 // CHECK5: cond.end: 2139 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2140 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2141 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2142 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 2143 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2144 // CHECK5: omp.inner.for.cond: 2145 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2146 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2147 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2148 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2149 // CHECK5: omp.inner.for.body: 2150 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2151 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 2152 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2153 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 2154 // CHECK5-NEXT: invoke void @_Z3foov() 2155 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 2156 // CHECK5: invoke.cont: 2157 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2158 // CHECK5: omp.body.continue: 2159 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2160 // CHECK5: omp.inner.for.inc: 2161 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2162 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 2163 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 2164 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] 2165 // CHECK5: omp.inner.for.end: 2166 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2167 // CHECK5: omp.loop.exit: 2168 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 2169 // CHECK5-NEXT: ret void 2170 // CHECK5: terminate.lpad: 2171 // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } 2172 // CHECK5-NEXT: catch ptr null 2173 // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 2174 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR7]] 2175 // CHECK5-NEXT: unreachable 2176 // 2177 // 2178 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40 2179 // CHECK5-SAME: () #[[ATTR3]] { 2180 // CHECK5-NEXT: entry: 2181 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined) 2182 // CHECK5-NEXT: ret void 2183 // 2184 // 2185 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined 2186 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 2187 // CHECK5-NEXT: entry: 2188 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2189 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2190 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2191 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2192 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2193 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2194 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2195 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2196 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2197 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2198 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2199 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 2200 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 2201 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2202 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2203 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2204 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2205 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2206 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2207 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 2208 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2209 // CHECK5: cond.true: 2210 // CHECK5-NEXT: br label [[COND_END:%.*]] 2211 // CHECK5: cond.false: 2212 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2213 // CHECK5-NEXT: br label [[COND_END]] 2214 // CHECK5: cond.end: 2215 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2216 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2217 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2218 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2219 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2220 // CHECK5: omp.inner.for.cond: 2221 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2222 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2223 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2224 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2225 // CHECK5: omp.inner.for.body: 2226 // CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 23) 2227 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2228 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 2229 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2230 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 2231 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) 2232 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2233 // CHECK5: omp.inner.for.inc: 2234 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2235 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2236 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 2237 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 2238 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] 2239 // CHECK5: omp.inner.for.end: 2240 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2241 // CHECK5: omp.loop.exit: 2242 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2243 // CHECK5-NEXT: ret void 2244 // 2245 // 2246 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined.omp_outlined 2247 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 2248 // CHECK5-NEXT: entry: 2249 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2250 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2251 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 2252 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 2253 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2254 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2255 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2256 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2257 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2258 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2259 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2260 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2261 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2262 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2263 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2264 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2265 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 2266 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2267 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 2268 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2269 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 2270 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 2271 // CHECK5-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 2272 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2273 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2274 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2275 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 2276 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2277 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2278 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 2279 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2280 // CHECK5: cond.true: 2281 // CHECK5-NEXT: br label [[COND_END:%.*]] 2282 // CHECK5: cond.false: 2283 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2284 // CHECK5-NEXT: br label [[COND_END]] 2285 // CHECK5: cond.end: 2286 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2287 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2288 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2289 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 2290 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2291 // CHECK5: omp.inner.for.cond: 2292 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2293 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2294 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2295 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2296 // CHECK5: omp.inner.for.body: 2297 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2298 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 2299 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2300 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 2301 // CHECK5-NEXT: invoke void @_Z3foov() 2302 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 2303 // CHECK5: invoke.cont: 2304 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2305 // CHECK5: omp.body.continue: 2306 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2307 // CHECK5: omp.inner.for.inc: 2308 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2309 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 2310 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 2311 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] 2312 // CHECK5: omp.inner.for.end: 2313 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2314 // CHECK5: omp.loop.exit: 2315 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 2316 // CHECK5-NEXT: ret void 2317 // CHECK5: terminate.lpad: 2318 // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } 2319 // CHECK5-NEXT: catch ptr null 2320 // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 2321 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR7]] 2322 // CHECK5-NEXT: unreachable 2323 // 2324 // 2325 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36 2326 // CHECK5-SAME: () #[[ATTR3]] { 2327 // CHECK5-NEXT: entry: 2328 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined) 2329 // CHECK5-NEXT: ret void 2330 // 2331 // 2332 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined 2333 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 2334 // CHECK5-NEXT: entry: 2335 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2336 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2337 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2338 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2339 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2340 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2341 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2342 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2343 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2344 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2345 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2346 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 2347 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 2348 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2349 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2350 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2351 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2352 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2353 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2354 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 2355 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2356 // CHECK5: cond.true: 2357 // CHECK5-NEXT: br label [[COND_END:%.*]] 2358 // CHECK5: cond.false: 2359 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2360 // CHECK5-NEXT: br label [[COND_END]] 2361 // CHECK5: cond.end: 2362 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2363 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2364 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2365 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2366 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2367 // CHECK5: omp.inner.for.cond: 2368 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2369 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2370 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2371 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2372 // CHECK5: omp.inner.for.body: 2373 // CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 1) 2374 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2375 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 2376 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2377 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 2378 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) 2379 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2380 // CHECK5: omp.inner.for.inc: 2381 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2382 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2383 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 2384 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 2385 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] 2386 // CHECK5: omp.inner.for.end: 2387 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2388 // CHECK5: omp.loop.exit: 2389 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2390 // CHECK5-NEXT: ret void 2391 // 2392 // 2393 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined.omp_outlined 2394 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 2395 // CHECK5-NEXT: entry: 2396 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2397 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2398 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 2399 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 2400 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2401 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2402 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2403 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2404 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2405 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2406 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2407 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2408 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2409 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2410 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2411 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2412 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 2413 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2414 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 2415 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2416 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 2417 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 2418 // CHECK5-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 2419 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2420 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2421 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2422 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 2423 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2424 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2425 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 2426 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2427 // CHECK5: cond.true: 2428 // CHECK5-NEXT: br label [[COND_END:%.*]] 2429 // CHECK5: cond.false: 2430 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2431 // CHECK5-NEXT: br label [[COND_END]] 2432 // CHECK5: cond.end: 2433 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2434 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2435 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2436 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 2437 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2438 // CHECK5: omp.inner.for.cond: 2439 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2440 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2441 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2442 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2443 // CHECK5: omp.inner.for.body: 2444 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2445 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 2446 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2447 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 2448 // CHECK5-NEXT: invoke void @_Z3foov() 2449 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 2450 // CHECK5: invoke.cont: 2451 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2452 // CHECK5: omp.body.continue: 2453 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2454 // CHECK5: omp.inner.for.inc: 2455 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2456 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 2457 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 2458 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] 2459 // CHECK5: omp.inner.for.end: 2460 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2461 // CHECK5: omp.loop.exit: 2462 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 2463 // CHECK5-NEXT: ret void 2464 // CHECK5: terminate.lpad: 2465 // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } 2466 // CHECK5-NEXT: catch ptr null 2467 // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 2468 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR7]] 2469 // CHECK5-NEXT: unreachable 2470 // 2471 // 2472 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40 2473 // CHECK5-SAME: () #[[ATTR3]] personality ptr @__gxx_personality_v0 { 2474 // CHECK5-NEXT: entry: 2475 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2476 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 2477 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 2478 // CHECK5-NEXT: invoke void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) 2479 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 2480 // CHECK5: invoke.cont: 2481 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 2482 // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] 2483 // CHECK5-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 2484 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 2485 // CHECK5-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 2486 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 2487 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined, i64 [[TMP1]]) 2488 // CHECK5-NEXT: ret void 2489 // CHECK5: terminate.lpad: 2490 // CHECK5-NEXT: [[TMP2:%.*]] = landingpad { ptr, i32 } 2491 // CHECK5-NEXT: catch ptr null 2492 // CHECK5-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0 2493 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP3]]) #[[ATTR7]] 2494 // CHECK5-NEXT: unreachable 2495 // 2496 // 2497 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined 2498 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 2499 // CHECK5-NEXT: entry: 2500 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2501 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2502 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2503 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2504 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2505 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2506 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2507 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2508 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2509 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2510 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2511 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2512 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 2513 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 2514 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 2515 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2516 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2517 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2518 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2519 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2520 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2521 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 2522 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2523 // CHECK5: cond.true: 2524 // CHECK5-NEXT: br label [[COND_END:%.*]] 2525 // CHECK5: cond.false: 2526 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2527 // CHECK5-NEXT: br label [[COND_END]] 2528 // CHECK5: cond.end: 2529 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2530 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2531 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2532 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2533 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2534 // CHECK5: omp.inner.for.cond: 2535 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2536 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2537 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2538 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2539 // CHECK5: omp.inner.for.body: 2540 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 2541 // CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 2542 // CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) 2543 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2544 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 2545 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2546 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 2547 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined.omp_outlined, i64 [[TMP10]], i64 [[TMP12]]) 2548 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2549 // CHECK5: omp.inner.for.inc: 2550 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2551 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2552 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 2553 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 2554 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] 2555 // CHECK5: omp.inner.for.end: 2556 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2557 // CHECK5: omp.loop.exit: 2558 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2559 // CHECK5-NEXT: ret void 2560 // 2561 // 2562 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined.omp_outlined 2563 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { 2564 // CHECK5-NEXT: entry: 2565 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2566 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2567 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 2568 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 2569 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2570 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2571 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2572 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2573 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2574 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2575 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2576 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2577 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2578 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2579 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2580 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2581 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 2582 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2583 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 2584 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2585 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 2586 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 2587 // CHECK5-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 2588 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2589 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2590 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2591 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 2592 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2593 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2594 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 2595 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2596 // CHECK5: cond.true: 2597 // CHECK5-NEXT: br label [[COND_END:%.*]] 2598 // CHECK5: cond.false: 2599 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2600 // CHECK5-NEXT: br label [[COND_END]] 2601 // CHECK5: cond.end: 2602 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2603 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2604 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2605 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 2606 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2607 // CHECK5: omp.inner.for.cond: 2608 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2609 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2610 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2611 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2612 // CHECK5: omp.inner.for.body: 2613 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2614 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 2615 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2616 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 2617 // CHECK5-NEXT: invoke void @_Z3foov() 2618 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 2619 // CHECK5: invoke.cont: 2620 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2621 // CHECK5: omp.body.continue: 2622 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2623 // CHECK5: omp.inner.for.inc: 2624 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2625 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 2626 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 2627 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] 2628 // CHECK5: omp.inner.for.end: 2629 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2630 // CHECK5: omp.loop.exit: 2631 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 2632 // CHECK5-NEXT: ret void 2633 // CHECK5: terminate.lpad: 2634 // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } 2635 // CHECK5-NEXT: catch ptr null 2636 // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 2637 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR7]] 2638 // CHECK5-NEXT: unreachable 2639 // 2640 // 2641 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev 2642 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 2643 // CHECK5-NEXT: entry: 2644 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2645 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2646 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2647 // CHECK5-NEXT: ret void 2648 // 2649