1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s 4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 5 6 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 7 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 9 10 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 11 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s 12 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 13 14 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s 16 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 17 18 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 19 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s 20 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 21 22 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 23 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s 24 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 25 26 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 27 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s 28 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 29 30 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 31 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s 32 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 33 34 // expected-no-diagnostics 35 #ifndef HEADER 36 #define HEADER 37 38 void fn1(); 39 void fn2(); 40 void fn3(); 41 void fn4(); 42 void fn5(); 43 void fn6(); 44 45 int Arg; 46 47 void gtid_test() { 48 #pragma omp target 49 #pragma omp teams distribute parallel for 50 for(int i = 0 ; i < 100; i++) {} 51 52 #pragma omp target 53 #pragma omp teams distribute parallel for if (parallel: false) 54 for(int i = 0 ; i < 100; i++) { 55 gtid_test(); 56 } 57 } 58 59 60 template <typename T> 61 int tmain(T Arg) { 62 #pragma omp target 63 #pragma omp teams distribute parallel for if (true) 64 for(int i = 0 ; i < 100; i++) { 65 fn1(); 66 } 67 #pragma omp target 68 #pragma omp teams distribute parallel for if (false) 69 for(int i = 0 ; i < 100; i++) { 70 fn2(); 71 } 72 #pragma omp target 73 #pragma omp teams distribute parallel for if (parallel: Arg) 74 for(int i = 0 ; i < 100; i++) { 75 fn3(); 76 } 77 return 0; 78 } 79 80 int main() { 81 #pragma omp target 82 #pragma omp teams distribute parallel for if (true) 83 for(int i = 0 ; i < 100; i++) { 84 85 86 fn4(); 87 } 88 89 #pragma omp target 90 #pragma omp teams distribute parallel for if (false) 91 for(int i = 0 ; i < 100; i++) { 92 93 94 fn5(); 95 } 96 97 #pragma omp target 98 #pragma omp teams distribute parallel for if (Arg) 99 for(int i = 0 ; i < 100; i++) { 100 101 102 fn6(); 103 } 104 105 return tmain(Arg); 106 } 107 108 109 110 111 112 113 // call void [[T_OUTLINE_FUN_3:@.+]]( 114 115 #endif 116 // CHECK1-LABEL: define {{[^@]+}}@_Z9gtid_testv 117 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 118 // CHECK1-NEXT: entry: 119 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 120 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 121 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 122 // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 123 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 124 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 125 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 126 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 127 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 128 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 129 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 130 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 131 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 132 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 133 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 134 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 135 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 136 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 137 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 138 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 139 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 140 // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 141 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 142 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 143 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 144 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 145 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 146 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 147 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 148 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 149 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.region_id, ptr [[KERNEL_ARGS]]) 150 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 151 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 152 // CHECK1: omp_offload.failed: 153 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48() #[[ATTR2:[0-9]+]] 154 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 155 // CHECK1: omp_offload.cont: 156 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 157 // CHECK1-NEXT: store i32 3, ptr [[TMP15]], align 4 158 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 159 // CHECK1-NEXT: store i32 0, ptr [[TMP16]], align 4 160 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 161 // CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8 162 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3 163 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 164 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4 165 // CHECK1-NEXT: store ptr null, ptr [[TMP19]], align 8 166 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5 167 // CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8 168 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6 169 // CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8 170 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 171 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 172 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 173 // CHECK1-NEXT: store i64 100, ptr [[TMP23]], align 8 174 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9 175 // CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 8 176 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10 177 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4 178 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11 179 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4 180 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12 181 // CHECK1-NEXT: store i32 0, ptr [[TMP27]], align 4 182 // CHECK1-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.region_id, ptr [[KERNEL_ARGS2]]) 183 // CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 184 // CHECK1-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 185 // CHECK1: omp_offload.failed3: 186 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52() #[[ATTR2]] 187 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] 188 // CHECK1: omp_offload.cont4: 189 // CHECK1-NEXT: ret void 190 // 191 // 192 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48 193 // CHECK1-SAME: () #[[ATTR1:[0-9]+]] { 194 // CHECK1-NEXT: entry: 195 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.omp_outlined) 196 // CHECK1-NEXT: ret void 197 // 198 // 199 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.omp_outlined 200 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 201 // CHECK1-NEXT: entry: 202 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 203 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 204 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 205 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 206 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 207 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 208 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 209 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 210 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 211 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 212 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 213 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 214 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 215 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 216 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 217 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 218 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 219 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 220 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 221 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 222 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 223 // CHECK1: cond.true: 224 // CHECK1-NEXT: br label [[COND_END:%.*]] 225 // CHECK1: cond.false: 226 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 227 // CHECK1-NEXT: br label [[COND_END]] 228 // CHECK1: cond.end: 229 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 230 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 231 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 232 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 233 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 234 // CHECK1: omp.inner.for.cond: 235 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 236 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 237 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 238 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 239 // CHECK1: omp.inner.for.body: 240 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 241 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 242 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 243 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 244 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) 245 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 246 // CHECK1: omp.inner.for.inc: 247 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 248 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 249 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 250 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 251 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 252 // CHECK1: omp.inner.for.end: 253 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 254 // CHECK1: omp.loop.exit: 255 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 256 // CHECK1-NEXT: ret void 257 // 258 // 259 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l48.omp_outlined.omp_outlined 260 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { 261 // CHECK1-NEXT: entry: 262 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 263 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 264 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 265 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 266 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 267 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 268 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 269 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 270 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 271 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 272 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 273 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 274 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 275 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 276 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 277 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 278 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 279 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 280 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 281 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 282 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 283 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 284 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 285 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 286 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 287 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 288 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 289 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 290 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 291 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 292 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 293 // CHECK1: cond.true: 294 // CHECK1-NEXT: br label [[COND_END:%.*]] 295 // CHECK1: cond.false: 296 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 297 // CHECK1-NEXT: br label [[COND_END]] 298 // CHECK1: cond.end: 299 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 300 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 301 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 302 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 303 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 304 // CHECK1: omp.inner.for.cond: 305 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 306 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 307 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 308 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 309 // CHECK1: omp.inner.for.body: 310 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 311 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 312 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 313 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 314 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 315 // CHECK1: omp.body.continue: 316 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 317 // CHECK1: omp.inner.for.inc: 318 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 319 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 320 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 321 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 322 // CHECK1: omp.inner.for.end: 323 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 324 // CHECK1: omp.loop.exit: 325 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 326 // CHECK1-NEXT: ret void 327 // 328 // 329 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52 330 // CHECK1-SAME: () #[[ATTR1]] { 331 // CHECK1-NEXT: entry: 332 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.omp_outlined) 333 // CHECK1-NEXT: ret void 334 // 335 // 336 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.omp_outlined 337 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 338 // CHECK1-NEXT: entry: 339 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 340 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 341 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 342 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 343 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 344 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 345 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 346 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 347 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 348 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 349 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 350 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 351 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 352 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 353 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 354 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 355 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 356 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 357 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 358 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 359 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 360 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 361 // CHECK1: cond.true: 362 // CHECK1-NEXT: br label [[COND_END:%.*]] 363 // CHECK1: cond.false: 364 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 365 // CHECK1-NEXT: br label [[COND_END]] 366 // CHECK1: cond.end: 367 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 368 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 369 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 370 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 371 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 372 // CHECK1: omp.inner.for.cond: 373 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 374 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 375 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 376 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 377 // CHECK1: omp.inner.for.body: 378 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 379 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 380 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 381 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 382 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB3]], i32 [[TMP1]]) 383 // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 384 // CHECK1-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 385 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.omp_outlined.omp_outlined(ptr [[TMP11]], ptr [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] 386 // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB3]], i32 [[TMP1]]) 387 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 388 // CHECK1: omp.inner.for.inc: 389 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 390 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 391 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 392 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 393 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 394 // CHECK1: omp.inner.for.end: 395 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 396 // CHECK1: omp.loop.exit: 397 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 398 // CHECK1-NEXT: ret void 399 // 400 // 401 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.omp_outlined.omp_outlined 402 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { 403 // CHECK1-NEXT: entry: 404 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 405 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 406 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 407 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 408 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 409 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 410 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 411 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 412 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 413 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 414 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 415 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 416 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 417 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 418 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 419 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 420 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 421 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 422 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 423 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 424 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 425 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 426 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 427 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 428 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 429 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 430 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 431 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 432 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 433 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 434 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 435 // CHECK1: cond.true: 436 // CHECK1-NEXT: br label [[COND_END:%.*]] 437 // CHECK1: cond.false: 438 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 439 // CHECK1-NEXT: br label [[COND_END]] 440 // CHECK1: cond.end: 441 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 442 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 443 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 444 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 445 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 446 // CHECK1: omp.inner.for.cond: 447 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 448 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 449 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 450 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 451 // CHECK1: omp.inner.for.body: 452 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 453 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 454 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 455 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 456 // CHECK1-NEXT: call void @_Z9gtid_testv() 457 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 458 // CHECK1: omp.body.continue: 459 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 460 // CHECK1: omp.inner.for.inc: 461 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 462 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 463 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 464 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 465 // CHECK1: omp.inner.for.end: 466 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 467 // CHECK1: omp.loop.exit: 468 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 469 // CHECK1-NEXT: ret void 470 // 471 // 472 // CHECK1-LABEL: define {{[^@]+}}@main 473 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 474 // CHECK1-NEXT: entry: 475 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 476 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 477 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 478 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 479 // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 480 // CHECK1-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 481 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 482 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 483 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 484 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 485 // CHECK1-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 486 // CHECK1-NEXT: [[KERNEL_ARGS6:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 487 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 488 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 489 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 490 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 491 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 492 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 493 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 494 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 495 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 496 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 497 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 498 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 499 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 500 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 501 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 502 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 503 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 504 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 505 // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 506 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 507 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 508 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 509 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 510 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 511 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 512 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 513 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 514 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, ptr [[KERNEL_ARGS]]) 515 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 516 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 517 // CHECK1: omp_offload.failed: 518 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81() #[[ATTR2]] 519 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 520 // CHECK1: omp_offload.cont: 521 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 522 // CHECK1-NEXT: store i32 3, ptr [[TMP15]], align 4 523 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 524 // CHECK1-NEXT: store i32 0, ptr [[TMP16]], align 4 525 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 526 // CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8 527 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3 528 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 529 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4 530 // CHECK1-NEXT: store ptr null, ptr [[TMP19]], align 8 531 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5 532 // CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8 533 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6 534 // CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8 535 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 536 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 537 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 538 // CHECK1-NEXT: store i64 100, ptr [[TMP23]], align 8 539 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9 540 // CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 8 541 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10 542 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4 543 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11 544 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4 545 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12 546 // CHECK1-NEXT: store i32 0, ptr [[TMP27]], align 4 547 // CHECK1-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89.region_id, ptr [[KERNEL_ARGS2]]) 548 // CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 549 // CHECK1-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 550 // CHECK1: omp_offload.failed3: 551 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89() #[[ATTR2]] 552 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] 553 // CHECK1: omp_offload.cont4: 554 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr @Arg, align 4 555 // CHECK1-NEXT: store i32 [[TMP30]], ptr [[ARG_CASTED]], align 4 556 // CHECK1-NEXT: [[TMP31:%.*]] = load i64, ptr [[ARG_CASTED]], align 8 557 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 558 // CHECK1-NEXT: store i64 [[TMP31]], ptr [[TMP32]], align 8 559 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 560 // CHECK1-NEXT: store i64 [[TMP31]], ptr [[TMP33]], align 8 561 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 562 // CHECK1-NEXT: store ptr null, ptr [[TMP34]], align 8 563 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 564 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 565 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr @Arg, align 4 566 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP37]], 0 567 // CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8 568 // CHECK1-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1 569 // CHECK1-NEXT: [[TMP38:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 570 // CHECK1-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP38]] to i1 571 // CHECK1-NEXT: [[TMP39:%.*]] = select i1 [[LOADEDV]], i32 0, i32 1 572 // CHECK1-NEXT: [[TMP40:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP39]], 0 573 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 0 574 // CHECK1-NEXT: store i32 3, ptr [[TMP41]], align 4 575 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 1 576 // CHECK1-NEXT: store i32 1, ptr [[TMP42]], align 4 577 // CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 2 578 // CHECK1-NEXT: store ptr [[TMP35]], ptr [[TMP43]], align 8 579 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 3 580 // CHECK1-NEXT: store ptr [[TMP36]], ptr [[TMP44]], align 8 581 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 4 582 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP45]], align 8 583 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 5 584 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP46]], align 8 585 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 6 586 // CHECK1-NEXT: store ptr null, ptr [[TMP47]], align 8 587 // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 7 588 // CHECK1-NEXT: store ptr null, ptr [[TMP48]], align 8 589 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 8 590 // CHECK1-NEXT: store i64 100, ptr [[TMP49]], align 8 591 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 9 592 // CHECK1-NEXT: store i64 0, ptr [[TMP50]], align 8 593 // CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 10 594 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP51]], align 4 595 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 11 596 // CHECK1-NEXT: store [3 x i32] [[TMP40]], ptr [[TMP52]], align 4 597 // CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 12 598 // CHECK1-NEXT: store i32 0, ptr [[TMP53]], align 4 599 // CHECK1-NEXT: [[TMP54:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 [[TMP39]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97.region_id, ptr [[KERNEL_ARGS6]]) 600 // CHECK1-NEXT: [[TMP55:%.*]] = icmp ne i32 [[TMP54]], 0 601 // CHECK1-NEXT: br i1 [[TMP55]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 602 // CHECK1: omp_offload.failed7: 603 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97(i64 [[TMP31]]) #[[ATTR2]] 604 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT8]] 605 // CHECK1: omp_offload.cont8: 606 // CHECK1-NEXT: [[TMP56:%.*]] = load i32, ptr @Arg, align 4 607 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP56]]) 608 // CHECK1-NEXT: ret i32 [[CALL]] 609 // 610 // 611 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 612 // CHECK1-SAME: () #[[ATTR1]] { 613 // CHECK1-NEXT: entry: 614 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.omp_outlined) 615 // CHECK1-NEXT: ret void 616 // 617 // 618 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.omp_outlined 619 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 620 // CHECK1-NEXT: entry: 621 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 622 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 623 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 624 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 625 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 626 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 627 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 628 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 629 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 630 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 631 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 632 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 633 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 634 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 635 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 636 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 637 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 638 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 639 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 640 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 641 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 642 // CHECK1: cond.true: 643 // CHECK1-NEXT: br label [[COND_END:%.*]] 644 // CHECK1: cond.false: 645 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 646 // CHECK1-NEXT: br label [[COND_END]] 647 // CHECK1: cond.end: 648 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 649 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 650 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 651 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 652 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 653 // CHECK1: omp.inner.for.cond: 654 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 655 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 656 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 657 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 658 // CHECK1: omp.inner.for.body: 659 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 660 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 661 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 662 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 663 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) 664 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 665 // CHECK1: omp.inner.for.inc: 666 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 667 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 668 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 669 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 670 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 671 // CHECK1: omp.inner.for.end: 672 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 673 // CHECK1: omp.loop.exit: 674 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 675 // CHECK1-NEXT: ret void 676 // 677 // 678 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.omp_outlined.omp_outlined 679 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { 680 // CHECK1-NEXT: entry: 681 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 682 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 683 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 684 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 685 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 686 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 687 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 688 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 689 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 690 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 691 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 692 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 693 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 694 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 695 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 696 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 697 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 698 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 699 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 700 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 701 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 702 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 703 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 704 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 705 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 706 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 707 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 708 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 709 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 710 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 711 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 712 // CHECK1: cond.true: 713 // CHECK1-NEXT: br label [[COND_END:%.*]] 714 // CHECK1: cond.false: 715 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 716 // CHECK1-NEXT: br label [[COND_END]] 717 // CHECK1: cond.end: 718 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 719 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 720 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 721 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 722 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 723 // CHECK1: omp.inner.for.cond: 724 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 725 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 726 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 727 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 728 // CHECK1: omp.inner.for.body: 729 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 730 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 731 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 732 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 733 // CHECK1-NEXT: call void @_Z3fn4v() 734 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 735 // CHECK1: omp.body.continue: 736 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 737 // CHECK1: omp.inner.for.inc: 738 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 739 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 740 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 741 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 742 // CHECK1: omp.inner.for.end: 743 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 744 // CHECK1: omp.loop.exit: 745 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 746 // CHECK1-NEXT: ret void 747 // 748 // 749 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89 750 // CHECK1-SAME: () #[[ATTR1]] { 751 // CHECK1-NEXT: entry: 752 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89.omp_outlined) 753 // CHECK1-NEXT: ret void 754 // 755 // 756 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89.omp_outlined 757 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 758 // CHECK1-NEXT: entry: 759 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 760 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 761 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 762 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 763 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 764 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 765 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 766 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 767 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 768 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 769 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 770 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 771 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 772 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 773 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 774 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 775 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 776 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 777 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 778 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 779 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 780 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 781 // CHECK1: cond.true: 782 // CHECK1-NEXT: br label [[COND_END:%.*]] 783 // CHECK1: cond.false: 784 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 785 // CHECK1-NEXT: br label [[COND_END]] 786 // CHECK1: cond.end: 787 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 788 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 789 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 790 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 791 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 792 // CHECK1: omp.inner.for.cond: 793 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 794 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 795 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 796 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 797 // CHECK1: omp.inner.for.body: 798 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 799 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 800 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 801 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 802 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB3]], i32 [[TMP1]]) 803 // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 804 // CHECK1-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 805 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89.omp_outlined.omp_outlined(ptr [[TMP11]], ptr [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] 806 // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB3]], i32 [[TMP1]]) 807 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 808 // CHECK1: omp.inner.for.inc: 809 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 810 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 811 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 812 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 813 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 814 // CHECK1: omp.inner.for.end: 815 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 816 // CHECK1: omp.loop.exit: 817 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 818 // CHECK1-NEXT: ret void 819 // 820 // 821 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l89.omp_outlined.omp_outlined 822 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { 823 // CHECK1-NEXT: entry: 824 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 825 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 826 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 827 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 828 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 829 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 830 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 831 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 832 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 833 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 834 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 835 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 836 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 837 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 838 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 839 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 840 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 841 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 842 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 843 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 844 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 845 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 846 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 847 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 848 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 849 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 850 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 851 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 852 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 853 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 854 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 855 // CHECK1: cond.true: 856 // CHECK1-NEXT: br label [[COND_END:%.*]] 857 // CHECK1: cond.false: 858 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 859 // CHECK1-NEXT: br label [[COND_END]] 860 // CHECK1: cond.end: 861 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 862 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 863 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 864 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 865 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 866 // CHECK1: omp.inner.for.cond: 867 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 868 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 869 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 870 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 871 // CHECK1: omp.inner.for.body: 872 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 873 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 874 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 875 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 876 // CHECK1-NEXT: call void @_Z3fn5v() 877 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 878 // CHECK1: omp.body.continue: 879 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 880 // CHECK1: omp.inner.for.inc: 881 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 882 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 883 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 884 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 885 // CHECK1: omp.inner.for.end: 886 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 887 // CHECK1: omp.loop.exit: 888 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 889 // CHECK1-NEXT: ret void 890 // 891 // 892 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 893 // CHECK1-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { 894 // CHECK1-NEXT: entry: 895 // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 896 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 897 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 898 // CHECK1-NEXT: store i64 [[ARG]], ptr [[ARG_ADDR]], align 8 899 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARG_ADDR]], align 4 900 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 901 // CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8 902 // CHECK1-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1 903 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 904 // CHECK1-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP1]] to i1 905 // CHECK1-NEXT: [[STOREDV1:%.*]] = zext i1 [[LOADEDV]] to i8 906 // CHECK1-NEXT: store i8 [[STOREDV1]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 907 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 908 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97.omp_outlined, i64 [[TMP2]]) 909 // CHECK1-NEXT: ret void 910 // 911 // 912 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97.omp_outlined 913 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 914 // CHECK1-NEXT: entry: 915 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 916 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 917 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 918 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 919 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 920 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 921 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 922 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 923 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 924 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 925 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 926 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 927 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 928 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 929 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 930 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 931 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 932 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 933 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 934 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 935 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 936 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 937 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 938 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 939 // CHECK1: cond.true: 940 // CHECK1-NEXT: br label [[COND_END:%.*]] 941 // CHECK1: cond.false: 942 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 943 // CHECK1-NEXT: br label [[COND_END]] 944 // CHECK1: cond.end: 945 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 946 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 947 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 948 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 949 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 950 // CHECK1: omp.inner.for.cond: 951 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 952 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 953 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 954 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 955 // CHECK1: omp.inner.for.body: 956 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 957 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 958 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 959 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 960 // CHECK1-NEXT: [[TMP11:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 961 // CHECK1-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP11]] to i1 962 // CHECK1-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 963 // CHECK1: omp_if.then: 964 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) 965 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 966 // CHECK1: omp_if.else: 967 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB3]], i32 [[TMP1]]) 968 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 969 // CHECK1-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 970 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97.omp_outlined.omp_outlined(ptr [[TMP12]], ptr [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] 971 // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB3]], i32 [[TMP1]]) 972 // CHECK1-NEXT: br label [[OMP_IF_END]] 973 // CHECK1: omp_if.end: 974 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 975 // CHECK1: omp.inner.for.inc: 976 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 977 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 978 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 979 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 980 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 981 // CHECK1: omp.inner.for.end: 982 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 983 // CHECK1: omp.loop.exit: 984 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 985 // CHECK1-NEXT: ret void 986 // 987 // 988 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97.omp_outlined.omp_outlined 989 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { 990 // CHECK1-NEXT: entry: 991 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 992 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 993 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 994 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 995 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 996 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 997 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 998 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 999 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1000 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1001 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1002 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1003 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1004 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1005 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1006 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1007 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 1008 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1009 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 1010 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1011 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 1012 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1013 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 1014 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1015 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1016 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1017 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1018 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1019 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1020 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 1021 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1022 // CHECK1: cond.true: 1023 // CHECK1-NEXT: br label [[COND_END:%.*]] 1024 // CHECK1: cond.false: 1025 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1026 // CHECK1-NEXT: br label [[COND_END]] 1027 // CHECK1: cond.end: 1028 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1029 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1030 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1031 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1032 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1033 // CHECK1: omp.inner.for.cond: 1034 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1035 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1036 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1037 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1038 // CHECK1: omp.inner.for.body: 1039 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1040 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1041 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1042 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1043 // CHECK1-NEXT: call void @_Z3fn6v() 1044 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1045 // CHECK1: omp.body.continue: 1046 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1047 // CHECK1: omp.inner.for.inc: 1048 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1049 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 1050 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 1051 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1052 // CHECK1: omp.inner.for.end: 1053 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1054 // CHECK1: omp.loop.exit: 1055 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 1056 // CHECK1-NEXT: ret void 1057 // 1058 // 1059 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ 1060 // CHECK1-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { 1061 // CHECK1-NEXT: entry: 1062 // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 1063 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1064 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1065 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1066 // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 1067 // CHECK1-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 1068 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 1069 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 1070 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 1071 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1072 // CHECK1-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 1073 // CHECK1-NEXT: [[KERNEL_ARGS6:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 1074 // CHECK1-NEXT: store i32 [[ARG]], ptr [[ARG_ADDR]], align 4 1075 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1076 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 1077 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1078 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 1079 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1080 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 1081 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1082 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 1083 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1084 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 1085 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1086 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 1087 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1088 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 1089 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1090 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 1091 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1092 // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 1093 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1094 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 1095 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1096 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 1097 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1098 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 1099 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1100 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 1101 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62.region_id, ptr [[KERNEL_ARGS]]) 1102 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1103 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1104 // CHECK1: omp_offload.failed: 1105 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62() #[[ATTR2]] 1106 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1107 // CHECK1: omp_offload.cont: 1108 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 1109 // CHECK1-NEXT: store i32 3, ptr [[TMP15]], align 4 1110 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 1111 // CHECK1-NEXT: store i32 0, ptr [[TMP16]], align 4 1112 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 1113 // CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8 1114 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3 1115 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 1116 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4 1117 // CHECK1-NEXT: store ptr null, ptr [[TMP19]], align 8 1118 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5 1119 // CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8 1120 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6 1121 // CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8 1122 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 1123 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 1124 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 1125 // CHECK1-NEXT: store i64 100, ptr [[TMP23]], align 8 1126 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9 1127 // CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 8 1128 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10 1129 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4 1130 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11 1131 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4 1132 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12 1133 // CHECK1-NEXT: store i32 0, ptr [[TMP27]], align 4 1134 // CHECK1-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67.region_id, ptr [[KERNEL_ARGS2]]) 1135 // CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 1136 // CHECK1-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 1137 // CHECK1: omp_offload.failed3: 1138 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67() #[[ATTR2]] 1139 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] 1140 // CHECK1: omp_offload.cont4: 1141 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[ARG_ADDR]], align 4 1142 // CHECK1-NEXT: store i32 [[TMP30]], ptr [[ARG_CASTED]], align 4 1143 // CHECK1-NEXT: [[TMP31:%.*]] = load i64, ptr [[ARG_CASTED]], align 8 1144 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1145 // CHECK1-NEXT: store i64 [[TMP31]], ptr [[TMP32]], align 8 1146 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1147 // CHECK1-NEXT: store i64 [[TMP31]], ptr [[TMP33]], align 8 1148 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1149 // CHECK1-NEXT: store ptr null, ptr [[TMP34]], align 8 1150 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1151 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1152 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[ARG_ADDR]], align 4 1153 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP37]], 0 1154 // CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8 1155 // CHECK1-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1 1156 // CHECK1-NEXT: [[TMP38:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 1157 // CHECK1-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP38]] to i1 1158 // CHECK1-NEXT: [[TMP39:%.*]] = select i1 [[LOADEDV]], i32 0, i32 1 1159 // CHECK1-NEXT: [[TMP40:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP39]], 0 1160 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 0 1161 // CHECK1-NEXT: store i32 3, ptr [[TMP41]], align 4 1162 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 1 1163 // CHECK1-NEXT: store i32 1, ptr [[TMP42]], align 4 1164 // CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 2 1165 // CHECK1-NEXT: store ptr [[TMP35]], ptr [[TMP43]], align 8 1166 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 3 1167 // CHECK1-NEXT: store ptr [[TMP36]], ptr [[TMP44]], align 8 1168 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 4 1169 // CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP45]], align 8 1170 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 5 1171 // CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP46]], align 8 1172 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 6 1173 // CHECK1-NEXT: store ptr null, ptr [[TMP47]], align 8 1174 // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 7 1175 // CHECK1-NEXT: store ptr null, ptr [[TMP48]], align 8 1176 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 8 1177 // CHECK1-NEXT: store i64 100, ptr [[TMP49]], align 8 1178 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 9 1179 // CHECK1-NEXT: store i64 0, ptr [[TMP50]], align 8 1180 // CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 10 1181 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP51]], align 4 1182 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 11 1183 // CHECK1-NEXT: store [3 x i32] [[TMP40]], ptr [[TMP52]], align 4 1184 // CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 12 1185 // CHECK1-NEXT: store i32 0, ptr [[TMP53]], align 4 1186 // CHECK1-NEXT: [[TMP54:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 [[TMP39]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72.region_id, ptr [[KERNEL_ARGS6]]) 1187 // CHECK1-NEXT: [[TMP55:%.*]] = icmp ne i32 [[TMP54]], 0 1188 // CHECK1-NEXT: br i1 [[TMP55]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 1189 // CHECK1: omp_offload.failed7: 1190 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72(i64 [[TMP31]]) #[[ATTR2]] 1191 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT8]] 1192 // CHECK1: omp_offload.cont8: 1193 // CHECK1-NEXT: ret i32 0 1194 // 1195 // 1196 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62 1197 // CHECK1-SAME: () #[[ATTR1]] { 1198 // CHECK1-NEXT: entry: 1199 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62.omp_outlined) 1200 // CHECK1-NEXT: ret void 1201 // 1202 // 1203 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62.omp_outlined 1204 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 1205 // CHECK1-NEXT: entry: 1206 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1207 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1208 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1209 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1210 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1211 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1212 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1213 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1214 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1215 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1216 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1217 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1218 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 1219 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1220 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1221 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1222 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1223 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1224 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1225 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 1226 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1227 // CHECK1: cond.true: 1228 // CHECK1-NEXT: br label [[COND_END:%.*]] 1229 // CHECK1: cond.false: 1230 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1231 // CHECK1-NEXT: br label [[COND_END]] 1232 // CHECK1: cond.end: 1233 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1234 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1235 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1236 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1237 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1238 // CHECK1: omp.inner.for.cond: 1239 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1240 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1241 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1242 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1243 // CHECK1: omp.inner.for.body: 1244 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1245 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 1246 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1247 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 1248 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) 1249 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1250 // CHECK1: omp.inner.for.inc: 1251 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1252 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1253 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 1254 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 1255 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1256 // CHECK1: omp.inner.for.end: 1257 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1258 // CHECK1: omp.loop.exit: 1259 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1260 // CHECK1-NEXT: ret void 1261 // 1262 // 1263 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l62.omp_outlined.omp_outlined 1264 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { 1265 // CHECK1-NEXT: entry: 1266 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1267 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1268 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1269 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1270 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1271 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1272 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1273 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1274 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1275 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1276 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1277 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1278 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1279 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1280 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1281 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1282 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 1283 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1284 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 1285 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1286 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 1287 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1288 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 1289 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1290 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1291 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1292 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1293 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1294 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1295 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 1296 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1297 // CHECK1: cond.true: 1298 // CHECK1-NEXT: br label [[COND_END:%.*]] 1299 // CHECK1: cond.false: 1300 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1301 // CHECK1-NEXT: br label [[COND_END]] 1302 // CHECK1: cond.end: 1303 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1304 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1305 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1306 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1307 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1308 // CHECK1: omp.inner.for.cond: 1309 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1310 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1311 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1312 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1313 // CHECK1: omp.inner.for.body: 1314 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1315 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1316 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1317 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1318 // CHECK1-NEXT: call void @_Z3fn1v() 1319 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1320 // CHECK1: omp.body.continue: 1321 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1322 // CHECK1: omp.inner.for.inc: 1323 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1324 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 1325 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 1326 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1327 // CHECK1: omp.inner.for.end: 1328 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1329 // CHECK1: omp.loop.exit: 1330 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 1331 // CHECK1-NEXT: ret void 1332 // 1333 // 1334 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 1335 // CHECK1-SAME: () #[[ATTR1]] { 1336 // CHECK1-NEXT: entry: 1337 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67.omp_outlined) 1338 // CHECK1-NEXT: ret void 1339 // 1340 // 1341 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67.omp_outlined 1342 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 1343 // CHECK1-NEXT: entry: 1344 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1345 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1346 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1347 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1348 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1349 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1350 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1351 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1352 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1353 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 1354 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1355 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1356 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1357 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 1358 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1359 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1360 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1361 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1362 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1363 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1364 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 1365 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1366 // CHECK1: cond.true: 1367 // CHECK1-NEXT: br label [[COND_END:%.*]] 1368 // CHECK1: cond.false: 1369 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1370 // CHECK1-NEXT: br label [[COND_END]] 1371 // CHECK1: cond.end: 1372 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1373 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1374 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1375 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1376 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1377 // CHECK1: omp.inner.for.cond: 1378 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1379 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1380 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1381 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1382 // CHECK1: omp.inner.for.body: 1383 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1384 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 1385 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1386 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 1387 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB3]], i32 [[TMP1]]) 1388 // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1389 // CHECK1-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 1390 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67.omp_outlined.omp_outlined(ptr [[TMP11]], ptr [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] 1391 // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB3]], i32 [[TMP1]]) 1392 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1393 // CHECK1: omp.inner.for.inc: 1394 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1395 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1396 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 1397 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 1398 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1399 // CHECK1: omp.inner.for.end: 1400 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1401 // CHECK1: omp.loop.exit: 1402 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1403 // CHECK1-NEXT: ret void 1404 // 1405 // 1406 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67.omp_outlined.omp_outlined 1407 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { 1408 // CHECK1-NEXT: entry: 1409 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1410 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1411 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1412 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1413 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1414 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1415 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1416 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1417 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1418 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1419 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1420 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1421 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1422 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1423 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1424 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1425 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 1426 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1427 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 1428 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1429 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 1430 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1431 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 1432 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1433 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1434 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1435 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1436 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1437 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1438 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 1439 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1440 // CHECK1: cond.true: 1441 // CHECK1-NEXT: br label [[COND_END:%.*]] 1442 // CHECK1: cond.false: 1443 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1444 // CHECK1-NEXT: br label [[COND_END]] 1445 // CHECK1: cond.end: 1446 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1447 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1448 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1449 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1450 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1451 // CHECK1: omp.inner.for.cond: 1452 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1453 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1454 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1455 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1456 // CHECK1: omp.inner.for.body: 1457 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1458 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1459 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1460 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1461 // CHECK1-NEXT: call void @_Z3fn2v() 1462 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1463 // CHECK1: omp.body.continue: 1464 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1465 // CHECK1: omp.inner.for.inc: 1466 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1467 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 1468 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 1469 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1470 // CHECK1: omp.inner.for.end: 1471 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1472 // CHECK1: omp.loop.exit: 1473 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 1474 // CHECK1-NEXT: ret void 1475 // 1476 // 1477 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 1478 // CHECK1-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { 1479 // CHECK1-NEXT: entry: 1480 // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 1481 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1482 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1483 // CHECK1-NEXT: store i64 [[ARG]], ptr [[ARG_ADDR]], align 8 1484 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARG_ADDR]], align 4 1485 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 1486 // CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8 1487 // CHECK1-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1 1488 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 1489 // CHECK1-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP1]] to i1 1490 // CHECK1-NEXT: [[STOREDV1:%.*]] = zext i1 [[LOADEDV]] to i8 1491 // CHECK1-NEXT: store i8 [[STOREDV1]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 1492 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 1493 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72.omp_outlined, i64 [[TMP2]]) 1494 // CHECK1-NEXT: ret void 1495 // 1496 // 1497 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72.omp_outlined 1498 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 1499 // CHECK1-NEXT: entry: 1500 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1501 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1502 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1503 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1504 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1505 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1506 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1507 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1508 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1509 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1510 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 1511 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1512 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1513 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 1514 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1515 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 1516 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1517 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1518 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1519 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1520 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1521 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1522 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99 1523 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1524 // CHECK1: cond.true: 1525 // CHECK1-NEXT: br label [[COND_END:%.*]] 1526 // CHECK1: cond.false: 1527 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1528 // CHECK1-NEXT: br label [[COND_END]] 1529 // CHECK1: cond.end: 1530 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1531 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1532 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1533 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1534 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1535 // CHECK1: omp.inner.for.cond: 1536 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1537 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1538 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1539 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1540 // CHECK1: omp.inner.for.body: 1541 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1542 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 1543 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1544 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 1545 // CHECK1-NEXT: [[TMP11:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 1546 // CHECK1-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP11]] to i1 1547 // CHECK1-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1548 // CHECK1: omp_if.then: 1549 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) 1550 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1551 // CHECK1: omp_if.else: 1552 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB3]], i32 [[TMP1]]) 1553 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1554 // CHECK1-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 1555 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72.omp_outlined.omp_outlined(ptr [[TMP12]], ptr [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] 1556 // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB3]], i32 [[TMP1]]) 1557 // CHECK1-NEXT: br label [[OMP_IF_END]] 1558 // CHECK1: omp_if.end: 1559 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1560 // CHECK1: omp.inner.for.inc: 1561 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1562 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1563 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 1564 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 1565 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1566 // CHECK1: omp.inner.for.end: 1567 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1568 // CHECK1: omp.loop.exit: 1569 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1570 // CHECK1-NEXT: ret void 1571 // 1572 // 1573 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72.omp_outlined.omp_outlined 1574 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { 1575 // CHECK1-NEXT: entry: 1576 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1577 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1578 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1579 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1580 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1581 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1582 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1583 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1584 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1585 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1586 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1587 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1588 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1589 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1590 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1591 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1592 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 1593 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1594 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 1595 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1596 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 1597 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1598 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 1599 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1600 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1601 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1602 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1603 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1604 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1605 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 1606 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1607 // CHECK1: cond.true: 1608 // CHECK1-NEXT: br label [[COND_END:%.*]] 1609 // CHECK1: cond.false: 1610 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1611 // CHECK1-NEXT: br label [[COND_END]] 1612 // CHECK1: cond.end: 1613 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1614 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1615 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1616 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1617 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1618 // CHECK1: omp.inner.for.cond: 1619 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1620 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1621 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1622 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1623 // CHECK1: omp.inner.for.body: 1624 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1625 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1626 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1627 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1628 // CHECK1-NEXT: call void @_Z3fn3v() 1629 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1630 // CHECK1: omp.body.continue: 1631 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1632 // CHECK1: omp.inner.for.inc: 1633 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1634 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 1635 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 1636 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1637 // CHECK1: omp.inner.for.end: 1638 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1639 // CHECK1: omp.loop.exit: 1640 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 1641 // CHECK1-NEXT: ret void 1642 // 1643