1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target 57 #pragma omp teams distribute firstprivate(t_var, vec, s_arr, var) 58 for (int i = 0; i < 2; ++i) { 59 vec[i] = t_var; 60 s_arr[i] = var; 61 } 62 return T(); 63 } 64 65 S<float> test; 66 int t_var = 333; 67 int vec[] = {1, 2}; 68 S<float> s_arr[] = {1, 2}; 69 S<float> var(3); 70 71 int main() { 72 static int sivar; 73 #ifdef LAMBDA 74 [&]() { 75 #pragma omp target 76 #pragma omp teams distribute firstprivate(g, g1, sivar) 77 for (int i = 0; i < 2; ++i) { 78 79 // Skip global and bound tid vars 80 // skip loop vars 81 g = 1; 82 g1 = 1; 83 sivar = 2; 84 [&]() { 85 g = 2; 86 g1 = 2; 87 sivar = 4; 88 89 }(); 90 } 91 }(); 92 return 0; 93 #else 94 #pragma omp target 95 #pragma omp teams distribute firstprivate(t_var, vec, s_arr, var, sivar) 96 for (int i = 0; i < 2; ++i) { 97 vec[i] = t_var; 98 s_arr[i] = var; 99 sivar += i; 100 } 101 return tmain<int>(); 102 #endif 103 } 104 105 106 107 108 109 // Skip global and bound tid vars 110 // Skip temp vars for loop 111 112 // param copy 113 114 // T_VAR and SIVAR 115 116 // preparation vars 117 118 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 119 120 // firstprivate(s_arr) 121 122 // firstprivate(var) 123 124 125 126 127 128 129 // Skip global and bound tid vars 130 // Skip temp vars for loop 131 132 // param copy 133 134 135 // T_VAR and preparation variables 136 137 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 138 139 // firstprivate(s_arr) 140 141 // firstprivate(var) 142 143 144 #endif 145 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 146 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 147 // CHECK1-NEXT: entry: 148 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 149 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 150 // CHECK1-NEXT: ret void 151 // 152 // 153 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 154 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 155 // CHECK1-NEXT: entry: 156 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 157 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 158 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 159 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 160 // CHECK1-NEXT: ret void 161 // 162 // 163 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 164 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 165 // CHECK1-NEXT: entry: 166 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 167 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 168 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 169 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 170 // CHECK1-NEXT: ret void 171 // 172 // 173 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 174 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 175 // CHECK1-NEXT: entry: 176 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 177 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 178 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 179 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 180 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 181 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 182 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 183 // CHECK1-NEXT: ret void 184 // 185 // 186 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 187 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 188 // CHECK1-NEXT: entry: 189 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 190 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 191 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 192 // CHECK1-NEXT: ret void 193 // 194 // 195 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 196 // CHECK1-SAME: () #[[ATTR0]] { 197 // CHECK1-NEXT: entry: 198 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 199 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 200 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 201 // CHECK1-NEXT: ret void 202 // 203 // 204 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 205 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 206 // CHECK1-NEXT: entry: 207 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 208 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 209 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 210 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 211 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 212 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 213 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 214 // CHECK1-NEXT: ret void 215 // 216 // 217 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 218 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 219 // CHECK1-NEXT: entry: 220 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 221 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 222 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 223 // CHECK1: arraydestroy.body: 224 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 225 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 226 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 227 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 228 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 229 // CHECK1: arraydestroy.done1: 230 // CHECK1-NEXT: ret void 231 // 232 // 233 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 234 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 235 // CHECK1-NEXT: entry: 236 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 237 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 238 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 239 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 240 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 241 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 242 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 243 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 244 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 245 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 246 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 247 // CHECK1-NEXT: ret void 248 // 249 // 250 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 251 // CHECK1-SAME: () #[[ATTR0]] { 252 // CHECK1-NEXT: entry: 253 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 254 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 255 // CHECK1-NEXT: ret void 256 // 257 // 258 // CHECK1-LABEL: define {{[^@]+}}@main 259 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 260 // CHECK1-NEXT: entry: 261 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 262 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 263 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 264 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 265 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 266 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 267 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 268 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 269 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 270 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr @t_var, align 4 271 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 272 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 273 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 274 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 275 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 276 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 277 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP4]], align 8 278 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 279 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 280 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 281 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 282 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 283 // CHECK1-NEXT: store ptr @vec, ptr [[TMP7]], align 8 284 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 285 // CHECK1-NEXT: store ptr @vec, ptr [[TMP8]], align 8 286 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 287 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 288 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 289 // CHECK1-NEXT: store ptr @s_arr, ptr [[TMP10]], align 8 290 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 291 // CHECK1-NEXT: store ptr @s_arr, ptr [[TMP11]], align 8 292 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 293 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 294 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 295 // CHECK1-NEXT: store ptr @var, ptr [[TMP13]], align 8 296 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 297 // CHECK1-NEXT: store ptr @var, ptr [[TMP14]], align 8 298 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 299 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 300 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 301 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP16]], align 8 302 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 303 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP17]], align 8 304 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 305 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 306 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 307 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 308 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 309 // CHECK1-NEXT: store i32 3, ptr [[TMP21]], align 4 310 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 311 // CHECK1-NEXT: store i32 5, ptr [[TMP22]], align 4 312 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 313 // CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8 314 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 315 // CHECK1-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8 316 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 317 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 8 318 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 319 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 8 320 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 321 // CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8 322 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 323 // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8 324 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 325 // CHECK1-NEXT: store i64 2, ptr [[TMP29]], align 8 326 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 327 // CHECK1-NEXT: store i64 0, ptr [[TMP30]], align 8 328 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 329 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 330 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 331 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 332 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 333 // CHECK1-NEXT: store i32 0, ptr [[TMP33]], align 4 334 // CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, ptr [[KERNEL_ARGS]]) 335 // CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 336 // CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 337 // CHECK1: omp_offload.failed: 338 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i64 [[TMP1]], ptr @vec, ptr @s_arr, ptr @var, i64 [[TMP3]]) #[[ATTR2]] 339 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 340 // CHECK1: omp_offload.cont: 341 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 342 // CHECK1-NEXT: ret i32 [[CALL]] 343 // 344 // 345 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 346 // CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 347 // CHECK1-NEXT: entry: 348 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 349 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 350 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 351 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 352 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 353 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 354 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 355 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 356 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 357 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 358 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 359 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 360 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 361 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 362 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 363 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 364 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 365 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 366 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 367 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 368 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 369 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]]) 370 // CHECK1-NEXT: ret void 371 // 372 // 373 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined 374 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 375 // CHECK1-NEXT: entry: 376 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 377 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 378 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 379 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 380 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 381 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 382 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 383 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 384 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 385 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 386 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 387 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 388 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 389 // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 390 // CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 391 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 392 // CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 393 // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 394 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 395 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 396 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 397 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 398 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 399 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 400 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 401 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 402 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 403 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 404 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 405 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 406 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 407 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 408 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 409 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) 410 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 411 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 412 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 413 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 414 // CHECK1: omp.arraycpy.body: 415 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 416 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 417 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 418 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 419 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 420 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 421 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 422 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 423 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 424 // CHECK1: omp.arraycpy.done3: 425 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 426 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 427 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 428 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 429 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 430 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 431 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 432 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 433 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 434 // CHECK1: cond.true: 435 // CHECK1-NEXT: br label [[COND_END:%.*]] 436 // CHECK1: cond.false: 437 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 438 // CHECK1-NEXT: br label [[COND_END]] 439 // CHECK1: cond.end: 440 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 441 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 442 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 443 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 444 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 445 // CHECK1: omp.inner.for.cond: 446 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 447 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 448 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 449 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 450 // CHECK1: omp.inner.for.cond.cleanup: 451 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 452 // CHECK1: omp.inner.for.body: 453 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 454 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 455 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 456 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 457 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 458 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 459 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 460 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 [[IDXPROM]] 461 // CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 462 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 463 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 464 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]] 465 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR4]], i64 4, i1 false) 466 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 467 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 468 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 469 // CHECK1-NEXT: store i32 [[ADD9]], ptr [[SIVAR_ADDR]], align 4 470 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 471 // CHECK1: omp.body.continue: 472 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 473 // CHECK1: omp.inner.for.inc: 474 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 475 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP17]], 1 476 // CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4 477 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 478 // CHECK1: omp.inner.for.end: 479 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 480 // CHECK1: omp.loop.exit: 481 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 482 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 483 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) 484 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 485 // CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 486 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 487 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 488 // CHECK1: arraydestroy.body: 489 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 490 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 491 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 492 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 493 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 494 // CHECK1: arraydestroy.done12: 495 // CHECK1-NEXT: ret void 496 // 497 // 498 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev 499 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 500 // CHECK1-NEXT: entry: 501 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 502 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 503 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 504 // CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 505 // CHECK1-NEXT: ret void 506 // 507 // 508 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 509 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 510 // CHECK1-NEXT: entry: 511 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 512 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 513 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 514 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 515 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 516 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 517 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 518 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 519 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 520 // CHECK1-NEXT: ret void 521 // 522 // 523 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev 524 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 525 // CHECK1-NEXT: entry: 526 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 527 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 528 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 529 // CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 530 // CHECK1-NEXT: ret void 531 // 532 // 533 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 534 // CHECK1-SAME: () #[[ATTR1]] comdat { 535 // CHECK1-NEXT: entry: 536 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 537 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 538 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 539 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 540 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 541 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 542 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 543 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 544 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 545 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 546 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 547 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 548 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 549 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 550 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 551 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 552 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 553 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 554 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 555 // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 556 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 557 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 558 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 559 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 560 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 561 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 562 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 563 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 564 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 565 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP6]], align 8 566 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 567 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP7]], align 8 568 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 569 // CHECK1-NEXT: store ptr null, ptr [[TMP8]], align 8 570 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 571 // CHECK1-NEXT: store ptr [[VEC]], ptr [[TMP9]], align 8 572 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 573 // CHECK1-NEXT: store ptr [[VEC]], ptr [[TMP10]], align 8 574 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 575 // CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8 576 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 577 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 8 578 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 579 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 8 580 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 581 // CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8 582 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 583 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 8 584 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 585 // CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 8 586 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 587 // CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8 588 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 589 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 590 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 591 // CHECK1-NEXT: store i32 3, ptr [[TMP20]], align 4 592 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 593 // CHECK1-NEXT: store i32 4, ptr [[TMP21]], align 4 594 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 595 // CHECK1-NEXT: store ptr [[TMP18]], ptr [[TMP22]], align 8 596 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 597 // CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8 598 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 599 // CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP24]], align 8 600 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 601 // CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP25]], align 8 602 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 603 // CHECK1-NEXT: store ptr null, ptr [[TMP26]], align 8 604 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 605 // CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8 606 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 607 // CHECK1-NEXT: store i64 2, ptr [[TMP28]], align 8 608 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 609 // CHECK1-NEXT: store i64 0, ptr [[TMP29]], align 8 610 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 611 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4 612 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 613 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 614 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 615 // CHECK1-NEXT: store i32 0, ptr [[TMP32]], align 4 616 // CHECK1-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 617 // CHECK1-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 618 // CHECK1-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 619 // CHECK1: omp_offload.failed: 620 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]] 621 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 622 // CHECK1: omp_offload.cont: 623 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 624 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 625 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 626 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 627 // CHECK1: arraydestroy.body: 628 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 629 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 630 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 631 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 632 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 633 // CHECK1: arraydestroy.done2: 634 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 635 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 636 // CHECK1-NEXT: ret i32 [[TMP36]] 637 // 638 // 639 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev 640 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 641 // CHECK1-NEXT: entry: 642 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 643 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 644 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 645 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 646 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 647 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 648 // CHECK1-NEXT: store i32 0, ptr [[B]], align 4 649 // CHECK1-NEXT: ret void 650 // 651 // 652 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 653 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 654 // CHECK1-NEXT: entry: 655 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 656 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 657 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 658 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 659 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 660 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 661 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 662 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 663 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 664 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 665 // CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 666 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 667 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 668 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 669 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 670 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 671 // CHECK1-NEXT: ret void 672 // 673 // 674 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev 675 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 676 // CHECK1-NEXT: entry: 677 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 678 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 679 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 680 // CHECK1-NEXT: ret void 681 // 682 // 683 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 684 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 685 // CHECK1-NEXT: entry: 686 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 687 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 688 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 689 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 690 // CHECK1-NEXT: ret void 691 // 692 // 693 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 694 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 695 // CHECK1-NEXT: entry: 696 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 697 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 698 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 699 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 700 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 701 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 702 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 703 // CHECK1-NEXT: ret void 704 // 705 // 706 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 707 // CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 708 // CHECK1-NEXT: entry: 709 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 710 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 711 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 712 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 713 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 714 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 715 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 716 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 717 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 718 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 719 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 720 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 721 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 722 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 723 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 724 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 725 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 726 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 727 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) 728 // CHECK1-NEXT: ret void 729 // 730 // 731 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 732 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 733 // CHECK1-NEXT: entry: 734 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 735 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 736 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 737 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 738 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 739 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 740 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 741 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 742 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 743 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 744 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 745 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 746 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 747 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 748 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 749 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 750 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 751 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 752 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 753 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 754 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 755 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 756 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 757 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 758 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 759 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 760 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 761 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 762 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 763 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 764 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 765 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 766 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 767 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 768 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) 769 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 770 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 771 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 772 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 773 // CHECK1: omp.arraycpy.body: 774 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 775 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 776 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 777 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 778 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 779 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 780 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 781 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 782 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 783 // CHECK1: omp.arraycpy.done4: 784 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 785 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 786 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) 787 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 788 // CHECK1-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8 789 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 790 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 791 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 792 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 793 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 794 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 795 // CHECK1: cond.true: 796 // CHECK1-NEXT: br label [[COND_END:%.*]] 797 // CHECK1: cond.false: 798 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 799 // CHECK1-NEXT: br label [[COND_END]] 800 // CHECK1: cond.end: 801 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 802 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 803 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 804 // CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 805 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 806 // CHECK1: omp.inner.for.cond: 807 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 808 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 809 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 810 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 811 // CHECK1: omp.inner.for.cond.cleanup: 812 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 813 // CHECK1: omp.inner.for.body: 814 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 815 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 816 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 817 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 818 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 819 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 820 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 821 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] 822 // CHECK1-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 823 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8 824 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 825 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP16]] to i64 826 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]] 827 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP15]], i64 4, i1 false) 828 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 829 // CHECK1: omp.body.continue: 830 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 831 // CHECK1: omp.inner.for.inc: 832 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 833 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 834 // CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4 835 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 836 // CHECK1: omp.inner.for.end: 837 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 838 // CHECK1: omp.loop.exit: 839 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 840 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 841 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) 842 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 843 // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 844 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 845 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 846 // CHECK1: arraydestroy.body: 847 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 848 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 849 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 850 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 851 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 852 // CHECK1: arraydestroy.done13: 853 // CHECK1-NEXT: ret void 854 // 855 // 856 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 857 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 858 // CHECK1-NEXT: entry: 859 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 860 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 861 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 862 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 863 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 864 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 865 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 866 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 867 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 868 // CHECK1-NEXT: ret void 869 // 870 // 871 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 872 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 873 // CHECK1-NEXT: entry: 874 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 875 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 876 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 877 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 878 // CHECK1-NEXT: ret void 879 // 880 // 881 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 882 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 883 // CHECK1-NEXT: entry: 884 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 885 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 886 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 887 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 888 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 889 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 890 // CHECK1-NEXT: ret void 891 // 892 // 893 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 894 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 895 // CHECK1-NEXT: entry: 896 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 897 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 898 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 899 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 900 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 901 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 902 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 903 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 904 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 905 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 906 // CHECK1-NEXT: ret void 907 // 908 // 909 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 910 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 911 // CHECK1-NEXT: entry: 912 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 913 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 914 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 915 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 916 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 917 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 918 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 919 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 920 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 921 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 922 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 923 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 924 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 925 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 926 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 927 // CHECK1-NEXT: ret void 928 // 929 // 930 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 931 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 932 // CHECK1-NEXT: entry: 933 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 934 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 935 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 936 // CHECK1-NEXT: ret void 937 // 938 // 939 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp 940 // CHECK1-SAME: () #[[ATTR0]] { 941 // CHECK1-NEXT: entry: 942 // CHECK1-NEXT: call void @__cxx_global_var_init() 943 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 944 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 945 // CHECK1-NEXT: ret void 946 // 947 // 948 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 949 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 950 // CHECK3-NEXT: entry: 951 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 952 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 953 // CHECK3-NEXT: ret void 954 // 955 // 956 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 957 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 958 // CHECK3-NEXT: entry: 959 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 960 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 961 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 962 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 963 // CHECK3-NEXT: ret void 964 // 965 // 966 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 967 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 968 // CHECK3-NEXT: entry: 969 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 970 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 971 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 972 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 973 // CHECK3-NEXT: ret void 974 // 975 // 976 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 977 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 978 // CHECK3-NEXT: entry: 979 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 980 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 981 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 982 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 983 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 984 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 985 // CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4 986 // CHECK3-NEXT: ret void 987 // 988 // 989 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 990 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 991 // CHECK3-NEXT: entry: 992 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 993 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 994 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 995 // CHECK3-NEXT: ret void 996 // 997 // 998 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 999 // CHECK3-SAME: () #[[ATTR0]] { 1000 // CHECK3-NEXT: entry: 1001 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 1002 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 1003 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 1004 // CHECK3-NEXT: ret void 1005 // 1006 // 1007 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1008 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1009 // CHECK3-NEXT: entry: 1010 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1011 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1012 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1013 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1014 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1015 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1016 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1017 // CHECK3-NEXT: ret void 1018 // 1019 // 1020 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1021 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1022 // CHECK3-NEXT: entry: 1023 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 1024 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 1025 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1026 // CHECK3: arraydestroy.body: 1027 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1028 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1029 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1030 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1031 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1032 // CHECK3: arraydestroy.done1: 1033 // CHECK3-NEXT: ret void 1034 // 1035 // 1036 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1037 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1038 // CHECK3-NEXT: entry: 1039 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1040 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1041 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1042 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1043 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1044 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1045 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1046 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1047 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1048 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1049 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 1050 // CHECK3-NEXT: ret void 1051 // 1052 // 1053 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1054 // CHECK3-SAME: () #[[ATTR0]] { 1055 // CHECK3-NEXT: entry: 1056 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1057 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1058 // CHECK3-NEXT: ret void 1059 // 1060 // 1061 // CHECK3-LABEL: define {{[^@]+}}@main 1062 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1063 // CHECK3-NEXT: entry: 1064 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1065 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1066 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1067 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 1068 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 1069 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 1070 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1071 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1072 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1073 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr @t_var, align 4 1074 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 1075 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1076 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 1077 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 1078 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 1079 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1080 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP4]], align 4 1081 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1082 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 1083 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1084 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1085 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1086 // CHECK3-NEXT: store ptr @vec, ptr [[TMP7]], align 4 1087 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1088 // CHECK3-NEXT: store ptr @vec, ptr [[TMP8]], align 4 1089 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1090 // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 1091 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1092 // CHECK3-NEXT: store ptr @s_arr, ptr [[TMP10]], align 4 1093 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1094 // CHECK3-NEXT: store ptr @s_arr, ptr [[TMP11]], align 4 1095 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1096 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 1097 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1098 // CHECK3-NEXT: store ptr @var, ptr [[TMP13]], align 4 1099 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1100 // CHECK3-NEXT: store ptr @var, ptr [[TMP14]], align 4 1101 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1102 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 1103 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1104 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP16]], align 4 1105 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1106 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP17]], align 4 1107 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1108 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 1109 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1110 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1111 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1112 // CHECK3-NEXT: store i32 3, ptr [[TMP21]], align 4 1113 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1114 // CHECK3-NEXT: store i32 5, ptr [[TMP22]], align 4 1115 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1116 // CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4 1117 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1118 // CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4 1119 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1120 // CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 4 1121 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1122 // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 4 1123 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1124 // CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 4 1125 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1126 // CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 4 1127 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1128 // CHECK3-NEXT: store i64 2, ptr [[TMP29]], align 8 1129 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1130 // CHECK3-NEXT: store i64 0, ptr [[TMP30]], align 8 1131 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1132 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 1133 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1134 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 1135 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1136 // CHECK3-NEXT: store i32 0, ptr [[TMP33]], align 4 1137 // CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, ptr [[KERNEL_ARGS]]) 1138 // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 1139 // CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1140 // CHECK3: omp_offload.failed: 1141 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i32 [[TMP1]], ptr @vec, ptr @s_arr, ptr @var, i32 [[TMP3]]) #[[ATTR2]] 1142 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1143 // CHECK3: omp_offload.cont: 1144 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1145 // CHECK3-NEXT: ret i32 [[CALL]] 1146 // 1147 // 1148 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 1149 // CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 1150 // CHECK3-NEXT: entry: 1151 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1152 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1153 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1154 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1155 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1156 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1157 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1158 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1159 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1160 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1161 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1162 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 1163 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1164 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1165 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1166 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1167 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 1168 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1169 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 1170 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 1171 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 1172 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]]) 1173 // CHECK3-NEXT: ret void 1174 // 1175 // 1176 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined 1177 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 1178 // CHECK3-NEXT: entry: 1179 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1180 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1181 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1182 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1183 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1184 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1185 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1186 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1187 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1188 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1189 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1190 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1191 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1192 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 1193 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 1194 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1195 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1196 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 1197 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1198 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1199 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1200 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1201 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1202 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1203 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1204 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 1205 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1206 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1207 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1208 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1209 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1210 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1211 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1212 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) 1213 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1214 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1215 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 1216 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1217 // CHECK3: omp.arraycpy.body: 1218 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1219 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1220 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1221 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 1222 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1223 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1224 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1225 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 1226 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 1227 // CHECK3: omp.arraycpy.done3: 1228 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 1229 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 1230 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 1231 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1232 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 1233 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1234 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1235 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 1236 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1237 // CHECK3: cond.true: 1238 // CHECK3-NEXT: br label [[COND_END:%.*]] 1239 // CHECK3: cond.false: 1240 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1241 // CHECK3-NEXT: br label [[COND_END]] 1242 // CHECK3: cond.end: 1243 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1244 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1245 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1246 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 1247 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1248 // CHECK3: omp.inner.for.cond: 1249 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1250 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1251 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1252 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1253 // CHECK3: omp.inner.for.cond.cleanup: 1254 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1255 // CHECK3: omp.inner.for.body: 1256 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1257 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 1258 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1259 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1260 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1261 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 1262 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP13]] 1263 // CHECK3-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 1264 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 1265 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP14]] 1266 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false) 1267 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 1268 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 1269 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 1270 // CHECK3-NEXT: store i32 [[ADD8]], ptr [[SIVAR_ADDR]], align 4 1271 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1272 // CHECK3: omp.body.continue: 1273 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1274 // CHECK3: omp.inner.for.inc: 1275 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1276 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], 1 1277 // CHECK3-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4 1278 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1279 // CHECK3: omp.inner.for.end: 1280 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1281 // CHECK3: omp.loop.exit: 1282 // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1283 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 1284 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) 1285 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 1286 // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1287 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 1288 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1289 // CHECK3: arraydestroy.body: 1290 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1291 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1292 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1293 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 1294 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 1295 // CHECK3: arraydestroy.done11: 1296 // CHECK3-NEXT: ret void 1297 // 1298 // 1299 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev 1300 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1301 // CHECK3-NEXT: entry: 1302 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1303 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1304 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1305 // CHECK3-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 1306 // CHECK3-NEXT: ret void 1307 // 1308 // 1309 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 1310 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1311 // CHECK3-NEXT: entry: 1312 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1313 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1314 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1315 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1316 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1317 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1318 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1319 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1320 // CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 1321 // CHECK3-NEXT: ret void 1322 // 1323 // 1324 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev 1325 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1326 // CHECK3-NEXT: entry: 1327 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1328 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1329 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1330 // CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 1331 // CHECK3-NEXT: ret void 1332 // 1333 // 1334 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1335 // CHECK3-SAME: () #[[ATTR1]] comdat { 1336 // CHECK3-NEXT: entry: 1337 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1338 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1339 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1340 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1341 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1342 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 1343 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1344 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1345 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 1346 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 1347 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 1348 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1349 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1350 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1351 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 1352 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 1353 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 1354 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 1355 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1356 // CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 1357 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 1358 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 1359 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 1360 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 1361 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1362 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 1363 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 1364 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 1365 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1366 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP6]], align 4 1367 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1368 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP7]], align 4 1369 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1370 // CHECK3-NEXT: store ptr null, ptr [[TMP8]], align 4 1371 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1372 // CHECK3-NEXT: store ptr [[VEC]], ptr [[TMP9]], align 4 1373 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1374 // CHECK3-NEXT: store ptr [[VEC]], ptr [[TMP10]], align 4 1375 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1376 // CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4 1377 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1378 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 4 1379 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1380 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 4 1381 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1382 // CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4 1383 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1384 // CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 4 1385 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1386 // CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 4 1387 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1388 // CHECK3-NEXT: store ptr null, ptr [[TMP17]], align 4 1389 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1390 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1391 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1392 // CHECK3-NEXT: store i32 3, ptr [[TMP20]], align 4 1393 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1394 // CHECK3-NEXT: store i32 4, ptr [[TMP21]], align 4 1395 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1396 // CHECK3-NEXT: store ptr [[TMP18]], ptr [[TMP22]], align 4 1397 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1398 // CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4 1399 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1400 // CHECK3-NEXT: store ptr @.offload_sizes.3, ptr [[TMP24]], align 4 1401 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1402 // CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP25]], align 4 1403 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1404 // CHECK3-NEXT: store ptr null, ptr [[TMP26]], align 4 1405 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1406 // CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 4 1407 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1408 // CHECK3-NEXT: store i64 2, ptr [[TMP28]], align 8 1409 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1410 // CHECK3-NEXT: store i64 0, ptr [[TMP29]], align 8 1411 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1412 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4 1413 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1414 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 1415 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1416 // CHECK3-NEXT: store i32 0, ptr [[TMP32]], align 4 1417 // CHECK3-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 1418 // CHECK3-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 1419 // CHECK3-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1420 // CHECK3: omp_offload.failed: 1421 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]] 1422 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1423 // CHECK3: omp_offload.cont: 1424 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1425 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1426 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1427 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1428 // CHECK3: arraydestroy.body: 1429 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1430 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1431 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1432 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1433 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1434 // CHECK3: arraydestroy.done2: 1435 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1436 // CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 1437 // CHECK3-NEXT: ret i32 [[TMP36]] 1438 // 1439 // 1440 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev 1441 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1442 // CHECK3-NEXT: entry: 1443 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1444 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1445 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1446 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 1447 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 1448 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 1449 // CHECK3-NEXT: store i32 0, ptr [[B]], align 4 1450 // CHECK3-NEXT: ret void 1451 // 1452 // 1453 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 1454 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1455 // CHECK3-NEXT: entry: 1456 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1457 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1458 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1459 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1460 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1461 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1462 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1463 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1464 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1465 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 1466 // CHECK3-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 1467 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 1468 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1469 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 1470 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 1471 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 1472 // CHECK3-NEXT: ret void 1473 // 1474 // 1475 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev 1476 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1477 // CHECK3-NEXT: entry: 1478 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1479 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1480 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1481 // CHECK3-NEXT: ret void 1482 // 1483 // 1484 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1485 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1486 // CHECK3-NEXT: entry: 1487 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1488 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1489 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1490 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1491 // CHECK3-NEXT: ret void 1492 // 1493 // 1494 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1495 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1496 // CHECK3-NEXT: entry: 1497 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1498 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1499 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1500 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1501 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1502 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1503 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1504 // CHECK3-NEXT: ret void 1505 // 1506 // 1507 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1508 // CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1509 // CHECK3-NEXT: entry: 1510 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1511 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1512 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1513 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1514 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1515 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1516 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1517 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1518 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1519 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1520 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1521 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1522 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1523 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 1524 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1525 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 1526 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1527 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 1528 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) 1529 // CHECK3-NEXT: ret void 1530 // 1531 // 1532 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 1533 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1534 // CHECK3-NEXT: entry: 1535 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1536 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1537 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1538 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1539 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1540 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1541 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1542 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1543 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1544 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1545 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1546 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1547 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1548 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 1549 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 1550 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1551 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1552 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1553 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 1554 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1555 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1556 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1557 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1558 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1559 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1560 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1561 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1562 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1563 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1564 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 1565 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1566 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1567 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1568 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1569 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) 1570 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 1571 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1572 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 1573 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1574 // CHECK3: omp.arraycpy.body: 1575 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1576 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1577 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1578 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 1579 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1580 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1581 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1582 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 1583 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1584 // CHECK3: omp.arraycpy.done4: 1585 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 1586 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1587 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) 1588 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 1589 // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 1590 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1591 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 1592 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1593 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1594 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 1595 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1596 // CHECK3: cond.true: 1597 // CHECK3-NEXT: br label [[COND_END:%.*]] 1598 // CHECK3: cond.false: 1599 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1600 // CHECK3-NEXT: br label [[COND_END]] 1601 // CHECK3: cond.end: 1602 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 1603 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1604 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1605 // CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 1606 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1607 // CHECK3: omp.inner.for.cond: 1608 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1609 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1610 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 1611 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1612 // CHECK3: omp.inner.for.cond.cleanup: 1613 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1614 // CHECK3: omp.inner.for.body: 1615 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1616 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 1617 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1618 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1619 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1620 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 1621 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP14]] 1622 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 1623 // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 4 1624 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 1625 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP16]] 1626 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i32 4, i1 false) 1627 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1628 // CHECK3: omp.body.continue: 1629 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1630 // CHECK3: omp.inner.for.inc: 1631 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1632 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP17]], 1 1633 // CHECK3-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4 1634 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1635 // CHECK3: omp.inner.for.end: 1636 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1637 // CHECK3: omp.loop.exit: 1638 // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1639 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 1640 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) 1641 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1642 // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 1643 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 1644 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1645 // CHECK3: arraydestroy.body: 1646 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1647 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1648 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1649 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 1650 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 1651 // CHECK3: arraydestroy.done12: 1652 // CHECK3-NEXT: ret void 1653 // 1654 // 1655 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1656 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1657 // CHECK3-NEXT: entry: 1658 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1659 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1660 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1661 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1662 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1663 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1664 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1665 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1666 // CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 1667 // CHECK3-NEXT: ret void 1668 // 1669 // 1670 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1671 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1672 // CHECK3-NEXT: entry: 1673 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1674 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1675 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1676 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1677 // CHECK3-NEXT: ret void 1678 // 1679 // 1680 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1681 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1682 // CHECK3-NEXT: entry: 1683 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1684 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1685 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1686 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1687 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1688 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1689 // CHECK3-NEXT: ret void 1690 // 1691 // 1692 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1693 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1694 // CHECK3-NEXT: entry: 1695 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1696 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1697 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1698 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1699 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1700 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1701 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1702 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1703 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1704 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1705 // CHECK3-NEXT: ret void 1706 // 1707 // 1708 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1709 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1710 // CHECK3-NEXT: entry: 1711 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1712 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1713 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1714 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1715 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1716 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1717 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1718 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1719 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1720 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 1721 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 1722 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 1723 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1724 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1725 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1726 // CHECK3-NEXT: ret void 1727 // 1728 // 1729 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1730 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1731 // CHECK3-NEXT: entry: 1732 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1733 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1734 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1735 // CHECK3-NEXT: ret void 1736 // 1737 // 1738 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp 1739 // CHECK3-SAME: () #[[ATTR0]] { 1740 // CHECK3-NEXT: entry: 1741 // CHECK3-NEXT: call void @__cxx_global_var_init() 1742 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1743 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1744 // CHECK3-NEXT: ret void 1745 // 1746 // 1747 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 1748 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 1749 // CHECK9-NEXT: entry: 1750 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 1751 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 1752 // CHECK9-NEXT: ret void 1753 // 1754 // 1755 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1756 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 1757 // CHECK9-NEXT: entry: 1758 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1759 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1760 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1761 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1762 // CHECK9-NEXT: ret void 1763 // 1764 // 1765 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1766 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1767 // CHECK9-NEXT: entry: 1768 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1769 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1770 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1771 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1772 // CHECK9-NEXT: ret void 1773 // 1774 // 1775 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1776 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1777 // CHECK9-NEXT: entry: 1778 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1779 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1780 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1781 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1782 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1783 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1784 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 1785 // CHECK9-NEXT: ret void 1786 // 1787 // 1788 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1789 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1790 // CHECK9-NEXT: entry: 1791 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1792 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1793 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1794 // CHECK9-NEXT: ret void 1795 // 1796 // 1797 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1798 // CHECK9-SAME: () #[[ATTR0]] { 1799 // CHECK9-NEXT: entry: 1800 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 1801 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 1802 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 1803 // CHECK9-NEXT: ret void 1804 // 1805 // 1806 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1807 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1808 // CHECK9-NEXT: entry: 1809 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1810 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1811 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1812 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1813 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1814 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1815 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1816 // CHECK9-NEXT: ret void 1817 // 1818 // 1819 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1820 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1821 // CHECK9-NEXT: entry: 1822 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1823 // CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1824 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1825 // CHECK9: arraydestroy.body: 1826 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1827 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1828 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1829 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1830 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1831 // CHECK9: arraydestroy.done1: 1832 // CHECK9-NEXT: ret void 1833 // 1834 // 1835 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1836 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1837 // CHECK9-NEXT: entry: 1838 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1839 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1840 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1841 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1842 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1843 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1844 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1845 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1846 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1847 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1848 // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 1849 // CHECK9-NEXT: ret void 1850 // 1851 // 1852 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1853 // CHECK9-SAME: () #[[ATTR0]] { 1854 // CHECK9-NEXT: entry: 1855 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1856 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1857 // CHECK9-NEXT: ret void 1858 // 1859 // 1860 // CHECK9-LABEL: define {{[^@]+}}@main 1861 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 1862 // CHECK9-NEXT: entry: 1863 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1864 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1865 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 1866 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 1867 // CHECK9-NEXT: ret i32 0 1868 // 1869 // 1870 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 1871 // CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[SIVAR:%.*]], i64 noundef [[G1:%.*]]) #[[ATTR4:[0-9]+]] { 1872 // CHECK9-NEXT: entry: 1873 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 1874 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 1875 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 1876 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1877 // CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 1878 // CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 1879 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 1880 // CHECK9-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 1881 // CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 1882 // CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 1883 // CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 1884 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 4 1885 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4 1886 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8 1887 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 1888 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 4 1889 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[G1_CASTED]], align 4 1890 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 8 1891 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 1892 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 1893 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 1894 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined, i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) 1895 // CHECK9-NEXT: ret void 1896 // 1897 // 1898 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined 1899 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 1900 // CHECK9-NEXT: entry: 1901 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1902 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1903 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 1904 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 1905 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 1906 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1907 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1908 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1909 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1910 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1911 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1912 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1913 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1914 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1915 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1916 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1917 // CHECK9-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 1918 // CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 1919 // CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 1920 // CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 1921 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1922 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1923 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1924 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1925 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1926 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1927 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1928 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1929 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1930 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1931 // CHECK9: cond.true: 1932 // CHECK9-NEXT: br label [[COND_END:%.*]] 1933 // CHECK9: cond.false: 1934 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1935 // CHECK9-NEXT: br label [[COND_END]] 1936 // CHECK9: cond.end: 1937 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1938 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1939 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1940 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1941 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1942 // CHECK9: omp.inner.for.cond: 1943 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1944 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1945 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1946 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1947 // CHECK9: omp.inner.for.body: 1948 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1949 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1950 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1951 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1952 // CHECK9-NEXT: store i32 1, ptr [[G_ADDR]], align 4 1953 // CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8 1954 // CHECK9-NEXT: store volatile i32 1, ptr [[TMP8]], align 4 1955 // CHECK9-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 1956 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 1957 // CHECK9-NEXT: store ptr [[G_ADDR]], ptr [[TMP9]], align 8 1958 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 1959 // CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP]], align 8 1960 // CHECK9-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8 1961 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 1962 // CHECK9-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP12]], align 8 1963 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 1964 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1965 // CHECK9: omp.body.continue: 1966 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1967 // CHECK9: omp.inner.for.inc: 1968 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1969 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], 1 1970 // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 1971 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 1972 // CHECK9: omp.inner.for.end: 1973 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1974 // CHECK9: omp.loop.exit: 1975 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1976 // CHECK9-NEXT: ret void 1977 // 1978 // 1979 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp 1980 // CHECK9-SAME: () #[[ATTR0]] { 1981 // CHECK9-NEXT: entry: 1982 // CHECK9-NEXT: call void @__cxx_global_var_init() 1983 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 1984 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 1985 // CHECK9-NEXT: ret void 1986 // 1987