1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 12 13 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 17 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 23 24 // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region) 25 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 26 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 27 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 28 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 29 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 30 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 31 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 32 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 33 34 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 35 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 36 37 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 38 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 39 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 40 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 41 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 42 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 43 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 44 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 45 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 46 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 47 48 // expected-no-diagnostics 49 #ifndef HEADER 50 #define HEADER 51 52 struct St { 53 int a, b; 54 St() : a(0), b(0) {} 55 St(const St &st) : a(st.a + st.b), b(0) {} 56 ~St() {} 57 }; 58 59 volatile int g = 1212; 60 volatile int &g1 = g; 61 62 template <class T> 63 struct S { 64 T f; 65 S(T a) : f(a + g) {} 66 S() : f(g) {} 67 S(const S &s, St t = St()) : f(s.f + t.a) {} 68 operator T() { return T(); } 69 ~S() {} 70 }; 71 72 73 template <typename T> 74 T tmain() { 75 S<T> test; 76 T t_var = T(); 77 T vec[] = {1, 2}; 78 S<T> s_arr[] = {1, 2}; 79 S<T> &var = test; 80 #pragma omp target teams loop private(t_var, vec, s_arr, var) 81 for (int i = 0; i < 2; ++i) { 82 vec[i] = t_var; 83 s_arr[i] = var; 84 } 85 return T(); 86 } 87 88 // HCHECK-DAG: [[TEST:@.+]] ={{.*}} global [[S_FLOAT_TY]] zeroinitializer, 89 S<float> test; 90 // HCHECK-DAG: [[T_VAR:@.+]] ={{.+}} global i{{[0-9]+}} 333, 91 int t_var = 333; 92 // HCHECK-DAG: [[VEC:@.+]] ={{.+}} global [2 x i{{[0-9]+}}] [i{{[0-9]+}} 1, i{{[0-9]+}} 2], 93 int vec[] = {1, 2}; 94 // HCHECK-DAG: [[S_ARR:@.+]] ={{.+}} global [2 x [[S_FLOAT_TY]]] zeroinitializer, 95 S<float> s_arr[] = {1, 2}; 96 // HCHECK-DAG: [[VAR:@.+]] ={{.+}} global [[S_FLOAT_TY]] zeroinitializer, 97 S<float> var(3); 98 // HCHECK-DAG: [[SIVAR:@.+]] = internal global i{{[0-9]+}} 0, 99 100 int main() { 101 static int sivar; 102 #ifdef LAMBDA 103 [&]() { 104 #pragma omp target teams loop private(g, g1, sivar) 105 for (int i = 0; i < 2; ++i) { 106 107 // Skip global, bound tid and loop vars 108 109 g = 1; 110 g1 = 1; 111 sivar = 2; 112 113 // Skip global, bound tid and loop vars 114 [&]() { 115 g = 2; 116 g1 = 2; 117 sivar = 4; 118 119 }(); 120 } 121 }(); 122 return 0; 123 #else 124 #pragma omp target teams loop private(t_var, vec, s_arr, var, sivar) 125 for (int i = 0; i < 2; ++i) { 126 vec[i] = t_var; 127 s_arr[i] = var; 128 sivar += i; 129 } 130 return tmain<int>(); 131 #endif 132 } 133 134 // HCHECK: define {{.*}}i{{[0-9]+}} @main() 135 // HCHECK: call i32 @__tgt_target_teams_mapper(ptr @{{.+}}, i64 -1, ptr @{{[^,]+}}, i32 0, ptr null, ptr null, {{.+}} null, {{.+}} null, ptr null, ptr null, i32 0, i32 0) 136 // HCHECK: call void @[[OFFL1:.+]]() 137 // HCHECK: {{%.+}} = call{{.*}} i32 @[[TMAIN_INT:.+]]() 138 // HCHECK: ret 139 140 // HCHECK: define{{.*}} void @[[OFFL1]]() 141 142 // Skip global, bound tid and loop vars 143 144 // private(s_arr) 145 146 // private(var) 147 148 149 // Skip global, bound tid and loop vars 150 151 // private(s_arr) 152 153 // private(var) 154 155 156 // HCHECK: define{{.*}} i{{[0-9]+}} @[[TMAIN_INT]]() 157 // HCHECK: call i32 @__tgt_target_teams_mapper(ptr @{{.+}}, i64 -1, ptr @{{[^,]+}}, i32 0, 158 // HCHECK: call void @[[TOFFL1:.+]]() 159 // HCHECK: ret 160 161 // HCHECK: define {{.*}}void @[[TOFFL1]]() 162 163 // Skip global, bound tid and loop vars 164 165 // private(s_arr) 166 167 168 // private(var) 169 170 171 // Skip global, bound tid and loop vars 172 // prev lb and ub 173 // iter variables 174 175 // private(s_arr) 176 177 178 // private(var) 179 180 181 182 #endif 183 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 184 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 185 // CHECK1-NEXT: entry: 186 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 187 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 188 // CHECK1-NEXT: ret void 189 // 190 // 191 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 192 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 193 // CHECK1-NEXT: entry: 194 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 195 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 196 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 197 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 198 // CHECK1-NEXT: ret void 199 // 200 // 201 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 202 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 203 // CHECK1-NEXT: entry: 204 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 205 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 206 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 207 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 208 // CHECK1-NEXT: ret void 209 // 210 // 211 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 212 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 213 // CHECK1-NEXT: entry: 214 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 215 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 216 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 217 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 218 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 219 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 220 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 221 // CHECK1-NEXT: ret void 222 // 223 // 224 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 225 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 226 // CHECK1-NEXT: entry: 227 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 228 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 229 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 230 // CHECK1-NEXT: ret void 231 // 232 // 233 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 234 // CHECK1-SAME: () #[[ATTR0]] { 235 // CHECK1-NEXT: entry: 236 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 237 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 238 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 239 // CHECK1-NEXT: ret void 240 // 241 // 242 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 243 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 244 // CHECK1-NEXT: entry: 245 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 246 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 247 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 248 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 249 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 250 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 251 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 252 // CHECK1-NEXT: ret void 253 // 254 // 255 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 256 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 257 // CHECK1-NEXT: entry: 258 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 259 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 260 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 261 // CHECK1: arraydestroy.body: 262 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 263 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 264 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 265 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 266 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 267 // CHECK1: arraydestroy.done1: 268 // CHECK1-NEXT: ret void 269 // 270 // 271 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 272 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 273 // CHECK1-NEXT: entry: 274 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 275 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 276 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 277 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 278 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 279 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 280 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 281 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 282 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 283 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 284 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 285 // CHECK1-NEXT: ret void 286 // 287 // 288 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 289 // CHECK1-SAME: () #[[ATTR0]] { 290 // CHECK1-NEXT: entry: 291 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 292 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 293 // CHECK1-NEXT: ret void 294 // 295 // 296 // CHECK1-LABEL: define {{[^@]+}}@main 297 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 298 // CHECK1-NEXT: entry: 299 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 300 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 301 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 302 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 303 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 304 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 305 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 306 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 307 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 308 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 309 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 310 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 311 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 312 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 313 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 314 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 315 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 316 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 317 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 318 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 319 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 320 // CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8 321 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 322 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 323 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 324 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 325 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 326 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 327 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 328 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 329 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.region_id, ptr [[KERNEL_ARGS]]) 330 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 331 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 332 // CHECK1: omp_offload.failed: 333 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124() #[[ATTR2]] 334 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 335 // CHECK1: omp_offload.cont: 336 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 337 // CHECK1-NEXT: ret i32 [[CALL]] 338 // 339 // 340 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 341 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 342 // CHECK1-NEXT: entry: 343 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) 344 // CHECK1-NEXT: ret void 345 // 346 // 347 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined 348 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 349 // CHECK1-NEXT: entry: 350 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 351 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 352 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 353 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 354 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 355 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 356 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 357 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 358 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 359 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 360 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 361 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 362 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 363 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 364 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 365 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 366 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 367 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 368 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 369 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 370 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 371 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 372 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 373 // CHECK1: arrayctor.loop: 374 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 375 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 376 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 377 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 378 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 379 // CHECK1: arrayctor.cont: 380 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 381 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 382 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 383 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 384 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 385 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 386 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 387 // CHECK1: cond.true: 388 // CHECK1-NEXT: br label [[COND_END:%.*]] 389 // CHECK1: cond.false: 390 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 391 // CHECK1-NEXT: br label [[COND_END]] 392 // CHECK1: cond.end: 393 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 394 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 395 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 396 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 397 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 398 // CHECK1: omp.inner.for.cond: 399 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 400 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 401 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 402 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 403 // CHECK1: omp.inner.for.cond.cleanup: 404 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 405 // CHECK1: omp.inner.for.body: 406 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 407 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 408 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 409 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 410 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 411 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 412 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 413 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 414 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 415 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 416 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 417 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] 418 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) 419 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 420 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 421 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 422 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[SIVAR]], align 4 423 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 424 // CHECK1: omp.body.continue: 425 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 426 // CHECK1: omp.inner.for.inc: 427 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 428 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 429 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 430 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 431 // CHECK1: omp.inner.for.end: 432 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 433 // CHECK1: omp.loop.exit: 434 // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 435 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 436 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) 437 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 438 // CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 439 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2 440 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 441 // CHECK1: arraydestroy.body: 442 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 443 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 444 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 445 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 446 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 447 // CHECK1: arraydestroy.done7: 448 // CHECK1-NEXT: ret void 449 // 450 // 451 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 452 // CHECK1-SAME: () #[[ATTR1]] comdat { 453 // CHECK1-NEXT: entry: 454 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 455 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 456 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 457 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 458 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 459 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 460 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 461 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 462 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 463 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 464 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 465 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 466 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 467 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 468 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 469 // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 470 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 471 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 472 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 473 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 474 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 475 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 476 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 477 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 478 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 479 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 480 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 481 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 482 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 483 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 484 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 485 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 486 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 487 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 488 // CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8 489 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 490 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 491 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 492 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 493 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 494 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 495 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 496 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 497 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.region_id, ptr [[KERNEL_ARGS]]) 498 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 499 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 500 // CHECK1: omp_offload.failed: 501 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80() #[[ATTR2]] 502 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 503 // CHECK1: omp_offload.cont: 504 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 505 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 506 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 507 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 508 // CHECK1: arraydestroy.body: 509 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 510 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 511 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 512 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 513 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 514 // CHECK1: arraydestroy.done2: 515 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 516 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 517 // CHECK1-NEXT: ret i32 [[TMP16]] 518 // 519 // 520 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 521 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 522 // CHECK1-NEXT: entry: 523 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 524 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 525 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 526 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 527 // CHECK1-NEXT: ret void 528 // 529 // 530 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 531 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 532 // CHECK1-NEXT: entry: 533 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 534 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 535 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 536 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 537 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 538 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 539 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 540 // CHECK1-NEXT: ret void 541 // 542 // 543 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 544 // CHECK1-SAME: () #[[ATTR4]] { 545 // CHECK1-NEXT: entry: 546 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) 547 // CHECK1-NEXT: ret void 548 // 549 // 550 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined 551 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 552 // CHECK1-NEXT: entry: 553 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 554 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 555 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 556 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 557 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 558 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 559 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 560 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 561 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 562 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 563 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 564 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 565 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 566 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 567 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 568 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 569 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 570 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 571 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 572 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 573 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 574 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 575 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 576 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 577 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 578 // CHECK1: arrayctor.loop: 579 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 580 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 581 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 582 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 583 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 584 // CHECK1: arrayctor.cont: 585 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 586 // CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 8 587 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 588 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 589 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 590 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 591 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 592 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 593 // CHECK1: cond.true: 594 // CHECK1-NEXT: br label [[COND_END:%.*]] 595 // CHECK1: cond.false: 596 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 597 // CHECK1-NEXT: br label [[COND_END]] 598 // CHECK1: cond.end: 599 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 600 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 601 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 602 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 603 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 604 // CHECK1: omp.inner.for.cond: 605 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 606 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 607 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 608 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 609 // CHECK1: omp.inner.for.cond.cleanup: 610 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 611 // CHECK1: omp.inner.for.body: 612 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 613 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 614 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 615 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 616 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 617 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 618 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 619 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 620 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 621 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 622 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 623 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 624 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] 625 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) 626 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 627 // CHECK1: omp.body.continue: 628 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 629 // CHECK1: omp.inner.for.inc: 630 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 631 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 632 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 633 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 634 // CHECK1: omp.inner.for.end: 635 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 636 // CHECK1: omp.loop.exit: 637 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 638 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 639 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 640 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 641 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 642 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 643 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 644 // CHECK1: arraydestroy.body: 645 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 646 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 647 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 648 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 649 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 650 // CHECK1: arraydestroy.done8: 651 // CHECK1-NEXT: ret void 652 // 653 // 654 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 655 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 656 // CHECK1-NEXT: entry: 657 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 658 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 659 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 660 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 661 // CHECK1-NEXT: ret void 662 // 663 // 664 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 665 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 666 // CHECK1-NEXT: entry: 667 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 668 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 669 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 670 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 671 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 672 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 673 // CHECK1-NEXT: ret void 674 // 675 // 676 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 677 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 678 // CHECK1-NEXT: entry: 679 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 680 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 681 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 682 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 683 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 684 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 685 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 686 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 687 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 688 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 689 // CHECK1-NEXT: ret void 690 // 691 // 692 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 693 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 694 // CHECK1-NEXT: entry: 695 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 696 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 697 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 698 // CHECK1-NEXT: ret void 699 // 700 // 701 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_generic_loop_private_codegen.cpp 702 // CHECK1-SAME: () #[[ATTR0]] { 703 // CHECK1-NEXT: entry: 704 // CHECK1-NEXT: call void @__cxx_global_var_init() 705 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 706 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 707 // CHECK1-NEXT: ret void 708 // 709 // 710 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 711 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 712 // CHECK3-NEXT: entry: 713 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 714 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 715 // CHECK3-NEXT: ret void 716 // 717 // 718 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 719 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 720 // CHECK3-NEXT: entry: 721 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 722 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 723 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 724 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 725 // CHECK3-NEXT: ret void 726 // 727 // 728 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 729 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 730 // CHECK3-NEXT: entry: 731 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 732 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 733 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 734 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 735 // CHECK3-NEXT: ret void 736 // 737 // 738 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 739 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 740 // CHECK3-NEXT: entry: 741 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 742 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 743 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 744 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 745 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 746 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 747 // CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4 748 // CHECK3-NEXT: ret void 749 // 750 // 751 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 752 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 753 // CHECK3-NEXT: entry: 754 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 755 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 756 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 757 // CHECK3-NEXT: ret void 758 // 759 // 760 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 761 // CHECK3-SAME: () #[[ATTR0]] { 762 // CHECK3-NEXT: entry: 763 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 764 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 765 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 766 // CHECK3-NEXT: ret void 767 // 768 // 769 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 770 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 771 // CHECK3-NEXT: entry: 772 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 773 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 774 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 775 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 776 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 777 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 778 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 779 // CHECK3-NEXT: ret void 780 // 781 // 782 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 783 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 784 // CHECK3-NEXT: entry: 785 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 786 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 787 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 788 // CHECK3: arraydestroy.body: 789 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 790 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 791 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 792 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 793 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 794 // CHECK3: arraydestroy.done1: 795 // CHECK3-NEXT: ret void 796 // 797 // 798 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 799 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 800 // CHECK3-NEXT: entry: 801 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 802 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 803 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 804 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 805 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 806 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 807 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 808 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 809 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 810 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 811 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 812 // CHECK3-NEXT: ret void 813 // 814 // 815 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 816 // CHECK3-SAME: () #[[ATTR0]] { 817 // CHECK3-NEXT: entry: 818 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 819 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 820 // CHECK3-NEXT: ret void 821 // 822 // 823 // CHECK3-LABEL: define {{[^@]+}}@main 824 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 825 // CHECK3-NEXT: entry: 826 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 827 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 828 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 829 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 830 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 831 // CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4 832 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 833 // CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4 834 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 835 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 836 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 837 // CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4 838 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 839 // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 840 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 841 // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 842 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 843 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 844 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 845 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 846 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 847 // CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8 848 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 849 // CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8 850 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 851 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 852 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 853 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 854 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 855 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 856 // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.region_id, ptr [[KERNEL_ARGS]]) 857 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 858 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 859 // CHECK3: omp_offload.failed: 860 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124() #[[ATTR2]] 861 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 862 // CHECK3: omp_offload.cont: 863 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 864 // CHECK3-NEXT: ret i32 [[CALL]] 865 // 866 // 867 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 868 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 869 // CHECK3-NEXT: entry: 870 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) 871 // CHECK3-NEXT: ret void 872 // 873 // 874 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined 875 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 876 // CHECK3-NEXT: entry: 877 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 878 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 879 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 880 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 881 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 882 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 883 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 884 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 885 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 886 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 887 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 888 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 889 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 890 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 891 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 892 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 893 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 894 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 895 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 896 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 897 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 898 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 899 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 900 // CHECK3: arrayctor.loop: 901 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 902 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 903 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 904 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 905 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 906 // CHECK3: arrayctor.cont: 907 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 908 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 909 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 910 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 911 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 912 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 913 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 914 // CHECK3: cond.true: 915 // CHECK3-NEXT: br label [[COND_END:%.*]] 916 // CHECK3: cond.false: 917 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 918 // CHECK3-NEXT: br label [[COND_END]] 919 // CHECK3: cond.end: 920 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 921 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 922 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 923 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 924 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 925 // CHECK3: omp.inner.for.cond: 926 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 927 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 928 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 929 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 930 // CHECK3: omp.inner.for.cond.cleanup: 931 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 932 // CHECK3: omp.inner.for.body: 933 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 934 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 935 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 936 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 937 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 938 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 939 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] 940 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 941 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 942 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] 943 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) 944 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 945 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 946 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 947 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4 948 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 949 // CHECK3: omp.body.continue: 950 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 951 // CHECK3: omp.inner.for.inc: 952 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 953 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 954 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 955 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 956 // CHECK3: omp.inner.for.end: 957 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 958 // CHECK3: omp.loop.exit: 959 // CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 960 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 961 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) 962 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 963 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 964 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 965 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 966 // CHECK3: arraydestroy.body: 967 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 968 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 969 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 970 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 971 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 972 // CHECK3: arraydestroy.done6: 973 // CHECK3-NEXT: ret void 974 // 975 // 976 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 977 // CHECK3-SAME: () #[[ATTR1]] comdat { 978 // CHECK3-NEXT: entry: 979 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 980 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 981 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 982 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 983 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 984 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 985 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 986 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 987 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 988 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 989 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 990 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 991 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 992 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 993 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 994 // CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 995 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 996 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 997 // CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4 998 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 999 // CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4 1000 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1001 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 1002 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1003 // CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4 1004 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1005 // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 1006 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1007 // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 1008 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1009 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1010 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1011 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 1012 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1013 // CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8 1014 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1015 // CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8 1016 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1017 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 1018 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1019 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 1020 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1021 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 1022 // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.region_id, ptr [[KERNEL_ARGS]]) 1023 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1024 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1025 // CHECK3: omp_offload.failed: 1026 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80() #[[ATTR2]] 1027 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1028 // CHECK3: omp_offload.cont: 1029 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1030 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1031 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1032 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1033 // CHECK3: arraydestroy.body: 1034 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1035 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1036 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1037 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1038 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1039 // CHECK3: arraydestroy.done2: 1040 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1041 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 1042 // CHECK3-NEXT: ret i32 [[TMP16]] 1043 // 1044 // 1045 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1046 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1047 // CHECK3-NEXT: entry: 1048 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1049 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1050 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1051 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1052 // CHECK3-NEXT: ret void 1053 // 1054 // 1055 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1056 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1057 // CHECK3-NEXT: entry: 1058 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1059 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1060 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1061 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1062 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1063 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1064 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1065 // CHECK3-NEXT: ret void 1066 // 1067 // 1068 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 1069 // CHECK3-SAME: () #[[ATTR4]] { 1070 // CHECK3-NEXT: entry: 1071 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) 1072 // CHECK3-NEXT: ret void 1073 // 1074 // 1075 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined 1076 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1077 // CHECK3-NEXT: entry: 1078 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1079 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1080 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1081 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1082 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 1083 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1084 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1085 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1086 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1087 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1088 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1089 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1090 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1091 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 1092 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1093 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1094 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1095 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 1096 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1097 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1098 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1099 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1100 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1101 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1102 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1103 // CHECK3: arrayctor.loop: 1104 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1105 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1106 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 1107 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1108 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1109 // CHECK3: arrayctor.cont: 1110 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1111 // CHECK3-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 4 1112 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1113 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1114 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1115 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1116 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1117 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1118 // CHECK3: cond.true: 1119 // CHECK3-NEXT: br label [[COND_END:%.*]] 1120 // CHECK3: cond.false: 1121 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1122 // CHECK3-NEXT: br label [[COND_END]] 1123 // CHECK3: cond.end: 1124 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1125 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1126 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1127 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1128 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1129 // CHECK3: omp.inner.for.cond: 1130 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1131 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1132 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1133 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1134 // CHECK3: omp.inner.for.cond.cleanup: 1135 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1136 // CHECK3: omp.inner.for.body: 1137 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1138 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1139 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1140 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1141 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 1142 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 1143 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] 1144 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 1145 // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 1146 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 1147 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] 1148 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) 1149 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1150 // CHECK3: omp.body.continue: 1151 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1152 // CHECK3: omp.inner.for.inc: 1153 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1154 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1 1155 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 1156 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1157 // CHECK3: omp.inner.for.end: 1158 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1159 // CHECK3: omp.loop.exit: 1160 // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1161 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 1162 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 1163 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1164 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1165 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 1166 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1167 // CHECK3: arraydestroy.body: 1168 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1169 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1170 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1171 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 1172 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1173 // CHECK3: arraydestroy.done7: 1174 // CHECK3-NEXT: ret void 1175 // 1176 // 1177 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1178 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1179 // CHECK3-NEXT: entry: 1180 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1181 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1182 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1183 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1184 // CHECK3-NEXT: ret void 1185 // 1186 // 1187 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1188 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1189 // CHECK3-NEXT: entry: 1190 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1191 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1192 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1193 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1194 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1195 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1196 // CHECK3-NEXT: ret void 1197 // 1198 // 1199 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1200 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1201 // CHECK3-NEXT: entry: 1202 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1203 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1204 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1205 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1206 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1207 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1208 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1209 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1210 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1211 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1212 // CHECK3-NEXT: ret void 1213 // 1214 // 1215 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1216 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1217 // CHECK3-NEXT: entry: 1218 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1219 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1220 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1221 // CHECK3-NEXT: ret void 1222 // 1223 // 1224 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_generic_loop_private_codegen.cpp 1225 // CHECK3-SAME: () #[[ATTR0]] { 1226 // CHECK3-NEXT: entry: 1227 // CHECK3-NEXT: call void @__cxx_global_var_init() 1228 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1229 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1230 // CHECK3-NEXT: ret void 1231 // 1232 // 1233 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 1234 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 1235 // CHECK5-NEXT: entry: 1236 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 1237 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 1238 // CHECK5-NEXT: ret void 1239 // 1240 // 1241 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1242 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 1243 // CHECK5-NEXT: entry: 1244 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1245 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1246 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1247 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1248 // CHECK5-NEXT: ret void 1249 // 1250 // 1251 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1252 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1253 // CHECK5-NEXT: entry: 1254 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1255 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1256 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1257 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1258 // CHECK5-NEXT: ret void 1259 // 1260 // 1261 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1262 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1263 // CHECK5-NEXT: entry: 1264 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1265 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1266 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1267 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1268 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1269 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1270 // CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4 1271 // CHECK5-NEXT: ret void 1272 // 1273 // 1274 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1275 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1276 // CHECK5-NEXT: entry: 1277 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1278 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1279 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1280 // CHECK5-NEXT: ret void 1281 // 1282 // 1283 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1284 // CHECK5-SAME: () #[[ATTR0]] { 1285 // CHECK5-NEXT: entry: 1286 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 1287 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 1288 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 1289 // CHECK5-NEXT: ret void 1290 // 1291 // 1292 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1293 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1294 // CHECK5-NEXT: entry: 1295 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1296 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1297 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1298 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1299 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1300 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1301 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1302 // CHECK5-NEXT: ret void 1303 // 1304 // 1305 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1306 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1307 // CHECK5-NEXT: entry: 1308 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1309 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1310 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1311 // CHECK5: arraydestroy.body: 1312 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1313 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1314 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1315 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1316 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1317 // CHECK5: arraydestroy.done1: 1318 // CHECK5-NEXT: ret void 1319 // 1320 // 1321 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1322 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1323 // CHECK5-NEXT: entry: 1324 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1325 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1326 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1327 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1328 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1329 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1330 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1331 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1332 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1333 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1334 // CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4 1335 // CHECK5-NEXT: ret void 1336 // 1337 // 1338 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1339 // CHECK5-SAME: () #[[ATTR0]] { 1340 // CHECK5-NEXT: entry: 1341 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1342 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1343 // CHECK5-NEXT: ret void 1344 // 1345 // 1346 // CHECK5-LABEL: define {{[^@]+}}@main 1347 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 1348 // CHECK5-NEXT: entry: 1349 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1350 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1351 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 1352 // CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 1353 // CHECK5-NEXT: ret i32 0 1354 // 1355 // 1356 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 1357 // CHECK5-SAME: () #[[ATTR4:[0-9]+]] { 1358 // CHECK5-NEXT: entry: 1359 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined) 1360 // CHECK5-NEXT: ret void 1361 // 1362 // 1363 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined 1364 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1365 // CHECK5-NEXT: entry: 1366 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1367 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1368 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1369 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1370 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1371 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1372 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1373 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1374 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1375 // CHECK5-NEXT: [[G:%.*]] = alloca i32, align 4 1376 // CHECK5-NEXT: [[G1:%.*]] = alloca i32, align 4 1377 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 1378 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1379 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1380 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1381 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1382 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1383 // CHECK5-NEXT: store ptr undef, ptr [[_TMP1]], align 8 1384 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1385 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1386 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1387 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1388 // CHECK5-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 8 1389 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1390 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1391 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1392 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1393 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1394 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1395 // CHECK5: cond.true: 1396 // CHECK5-NEXT: br label [[COND_END:%.*]] 1397 // CHECK5: cond.false: 1398 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1399 // CHECK5-NEXT: br label [[COND_END]] 1400 // CHECK5: cond.end: 1401 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1402 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1403 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1404 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1405 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1406 // CHECK5: omp.inner.for.cond: 1407 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1408 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1409 // CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1410 // CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1411 // CHECK5: omp.inner.for.body: 1412 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1413 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1414 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1415 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1416 // CHECK5-NEXT: store i32 1, ptr [[G]], align 4 1417 // CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 1418 // CHECK5-NEXT: store volatile i32 1, ptr [[TMP8]], align 4 1419 // CHECK5-NEXT: store i32 2, ptr [[SIVAR]], align 4 1420 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 1421 // CHECK5-NEXT: store ptr [[G]], ptr [[TMP9]], align 8 1422 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 1423 // CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8 1424 // CHECK5-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8 1425 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 1426 // CHECK5-NEXT: store ptr [[SIVAR]], ptr [[TMP12]], align 8 1427 // CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 1428 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1429 // CHECK5: omp.body.continue: 1430 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1431 // CHECK5: omp.inner.for.inc: 1432 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1433 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 1434 // CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 1435 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] 1436 // CHECK5: omp.inner.for.end: 1437 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1438 // CHECK5: omp.loop.exit: 1439 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1440 // CHECK5-NEXT: ret void 1441 // 1442 // 1443 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_generic_loop_private_codegen.cpp 1444 // CHECK5-SAME: () #[[ATTR0]] { 1445 // CHECK5-NEXT: entry: 1446 // CHECK5-NEXT: call void @__cxx_global_var_init() 1447 // CHECK5-NEXT: call void @__cxx_global_var_init.1() 1448 // CHECK5-NEXT: call void @__cxx_global_var_init.2() 1449 // CHECK5-NEXT: ret void 1450 // 1451 // 1452 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 1453 // CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { 1454 // CHECK13-NEXT: entry: 1455 // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 1456 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 1457 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) 1458 // CHECK13-NEXT: ret void 1459 // 1460 // 1461 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined 1462 // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 1463 // CHECK13-NEXT: entry: 1464 // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1465 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1466 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1467 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 1468 // CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1469 // CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1470 // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1471 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1472 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1473 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1474 // CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1475 // CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1476 // CHECK13-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1477 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 1478 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1479 // CHECK13-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1480 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1481 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1482 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1483 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1484 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1485 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 1486 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1487 // CHECK13: arrayctor.loop: 1488 // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1489 // CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1490 // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 1491 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1492 // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1493 // CHECK13: arrayctor.cont: 1494 // CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1495 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1496 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1497 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1498 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1499 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1500 // CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1501 // CHECK13: cond.true: 1502 // CHECK13-NEXT: br label [[COND_END:%.*]] 1503 // CHECK13: cond.false: 1504 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1505 // CHECK13-NEXT: br label [[COND_END]] 1506 // CHECK13: cond.end: 1507 // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1508 // CHECK13-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1509 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1510 // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1511 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1512 // CHECK13: omp.inner.for.cond: 1513 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1514 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1515 // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1516 // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1517 // CHECK13: omp.inner.for.cond.cleanup: 1518 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1519 // CHECK13: omp.inner.for.body: 1520 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1521 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1522 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1523 // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1524 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 1525 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 1526 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 1527 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 1528 // CHECK13-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 1529 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 1530 // CHECK13-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 1531 // CHECK13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] 1532 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) 1533 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 1534 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 1535 // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 1536 // CHECK13-NEXT: store i32 [[ADD4]], ptr [[SIVAR]], align 4 1537 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1538 // CHECK13: omp.body.continue: 1539 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1540 // CHECK13: omp.inner.for.inc: 1541 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1542 // CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 1543 // CHECK13-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 1544 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] 1545 // CHECK13: omp.inner.for.end: 1546 // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1547 // CHECK13: omp.loop.exit: 1548 // CHECK13-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1549 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 1550 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) 1551 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2:[0-9]+]] 1552 // CHECK13-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1553 // CHECK13-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2 1554 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1555 // CHECK13: arraydestroy.body: 1556 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1557 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1558 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1559 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 1560 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1561 // CHECK13: arraydestroy.done7: 1562 // CHECK13-NEXT: ret void 1563 // 1564 // 1565 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1566 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 1567 // CHECK13-NEXT: entry: 1568 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1569 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1570 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1571 // CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1572 // CHECK13-NEXT: ret void 1573 // 1574 // 1575 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1576 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1577 // CHECK13-NEXT: entry: 1578 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1579 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1580 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1581 // CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1582 // CHECK13-NEXT: ret void 1583 // 1584 // 1585 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 1586 // CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { 1587 // CHECK13-NEXT: entry: 1588 // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 1589 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 1590 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) 1591 // CHECK13-NEXT: ret void 1592 // 1593 // 1594 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined 1595 // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 1596 // CHECK13-NEXT: entry: 1597 // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1598 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1599 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1600 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 1601 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1602 // CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1603 // CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1604 // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1605 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1606 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1607 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1608 // CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1609 // CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1610 // CHECK13-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 1611 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 1612 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1613 // CHECK13-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1614 // CHECK13-NEXT: store ptr undef, ptr [[_TMP1]], align 8 1615 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1616 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1617 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1618 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1619 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1620 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 1621 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1622 // CHECK13: arrayctor.loop: 1623 // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1624 // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1625 // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 1626 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1627 // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1628 // CHECK13: arrayctor.cont: 1629 // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1630 // CHECK13-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 8 1631 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1632 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1633 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1634 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1635 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1636 // CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1637 // CHECK13: cond.true: 1638 // CHECK13-NEXT: br label [[COND_END:%.*]] 1639 // CHECK13: cond.false: 1640 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1641 // CHECK13-NEXT: br label [[COND_END]] 1642 // CHECK13: cond.end: 1643 // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1644 // CHECK13-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1645 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1646 // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1647 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1648 // CHECK13: omp.inner.for.cond: 1649 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1650 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1651 // CHECK13-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1652 // CHECK13-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1653 // CHECK13: omp.inner.for.cond.cleanup: 1654 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1655 // CHECK13: omp.inner.for.body: 1656 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1657 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1658 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1659 // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1660 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 1661 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 1662 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 1663 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 1664 // CHECK13-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 1665 // CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 1666 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 1667 // CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 1668 // CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] 1669 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) 1670 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1671 // CHECK13: omp.body.continue: 1672 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1673 // CHECK13: omp.inner.for.inc: 1674 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1675 // CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 1676 // CHECK13-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 1677 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] 1678 // CHECK13: omp.inner.for.end: 1679 // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1680 // CHECK13: omp.loop.exit: 1681 // CHECK13-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1682 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 1683 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 1684 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1685 // CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1686 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 1687 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1688 // CHECK13: arraydestroy.body: 1689 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1690 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1691 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1692 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 1693 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 1694 // CHECK13: arraydestroy.done8: 1695 // CHECK13-NEXT: ret void 1696 // 1697 // 1698 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1699 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1700 // CHECK13-NEXT: entry: 1701 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1702 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1703 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1704 // CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1705 // CHECK13-NEXT: ret void 1706 // 1707 // 1708 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1709 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1710 // CHECK13-NEXT: entry: 1711 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1712 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1713 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1714 // CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1715 // CHECK13-NEXT: ret void 1716 // 1717 // 1718 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1719 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1720 // CHECK13-NEXT: entry: 1721 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1722 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1723 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1724 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1725 // CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1726 // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1727 // CHECK13-NEXT: store float [[CONV]], ptr [[F]], align 4 1728 // CHECK13-NEXT: ret void 1729 // 1730 // 1731 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1732 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1733 // CHECK13-NEXT: entry: 1734 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1735 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1736 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1737 // CHECK13-NEXT: ret void 1738 // 1739 // 1740 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1741 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1742 // CHECK13-NEXT: entry: 1743 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1744 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1745 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1746 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1747 // CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1748 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1749 // CHECK13-NEXT: ret void 1750 // 1751 // 1752 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1753 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1754 // CHECK13-NEXT: entry: 1755 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1756 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1757 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1758 // CHECK13-NEXT: ret void 1759 // 1760 // 1761 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 1762 // CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { 1763 // CHECK15-NEXT: entry: 1764 // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 1765 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 1766 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) 1767 // CHECK15-NEXT: ret void 1768 // 1769 // 1770 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined 1771 // CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 1772 // CHECK15-NEXT: entry: 1773 // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1774 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1775 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1776 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 1777 // CHECK15-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1778 // CHECK15-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1779 // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1780 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1781 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1782 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1783 // CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1784 // CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1785 // CHECK15-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1786 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 1787 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1788 // CHECK15-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1789 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1790 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1791 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1792 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1793 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1794 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1795 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1796 // CHECK15: arrayctor.loop: 1797 // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1798 // CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1799 // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 1800 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1801 // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1802 // CHECK15: arrayctor.cont: 1803 // CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1804 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1805 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1806 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1807 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1808 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1809 // CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1810 // CHECK15: cond.true: 1811 // CHECK15-NEXT: br label [[COND_END:%.*]] 1812 // CHECK15: cond.false: 1813 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1814 // CHECK15-NEXT: br label [[COND_END]] 1815 // CHECK15: cond.end: 1816 // CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1817 // CHECK15-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1818 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1819 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1820 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1821 // CHECK15: omp.inner.for.cond: 1822 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1823 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1824 // CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1825 // CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1826 // CHECK15: omp.inner.for.cond.cleanup: 1827 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1828 // CHECK15: omp.inner.for.body: 1829 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1830 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1831 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1832 // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1833 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 1834 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 1835 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] 1836 // CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 1837 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 1838 // CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] 1839 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) 1840 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 1841 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 1842 // CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 1843 // CHECK15-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4 1844 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1845 // CHECK15: omp.body.continue: 1846 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1847 // CHECK15: omp.inner.for.inc: 1848 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1849 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 1850 // CHECK15-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 1851 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] 1852 // CHECK15: omp.inner.for.end: 1853 // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1854 // CHECK15: omp.loop.exit: 1855 // CHECK15-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1856 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 1857 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) 1858 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2:[0-9]+]] 1859 // CHECK15-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1860 // CHECK15-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 1861 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1862 // CHECK15: arraydestroy.body: 1863 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1864 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1865 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1866 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 1867 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 1868 // CHECK15: arraydestroy.done6: 1869 // CHECK15-NEXT: ret void 1870 // 1871 // 1872 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1873 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1874 // CHECK15-NEXT: entry: 1875 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1876 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1877 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1878 // CHECK15-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1879 // CHECK15-NEXT: ret void 1880 // 1881 // 1882 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1883 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1884 // CHECK15-NEXT: entry: 1885 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1886 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1887 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1888 // CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1889 // CHECK15-NEXT: ret void 1890 // 1891 // 1892 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 1893 // CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { 1894 // CHECK15-NEXT: entry: 1895 // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 1896 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 1897 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) 1898 // CHECK15-NEXT: ret void 1899 // 1900 // 1901 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined 1902 // CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 1903 // CHECK15-NEXT: entry: 1904 // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1905 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1906 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1907 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 1908 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 1909 // CHECK15-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1910 // CHECK15-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1911 // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1912 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1913 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1914 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1915 // CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1916 // CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1917 // CHECK15-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 1918 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 1919 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1920 // CHECK15-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1921 // CHECK15-NEXT: store ptr undef, ptr [[_TMP1]], align 4 1922 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1923 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1924 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1925 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1926 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1927 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1928 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1929 // CHECK15: arrayctor.loop: 1930 // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1931 // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1932 // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 1933 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1934 // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1935 // CHECK15: arrayctor.cont: 1936 // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1937 // CHECK15-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 4 1938 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1939 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1940 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1941 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1942 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1943 // CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1944 // CHECK15: cond.true: 1945 // CHECK15-NEXT: br label [[COND_END:%.*]] 1946 // CHECK15: cond.false: 1947 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1948 // CHECK15-NEXT: br label [[COND_END]] 1949 // CHECK15: cond.end: 1950 // CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1951 // CHECK15-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1952 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1953 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1954 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1955 // CHECK15: omp.inner.for.cond: 1956 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1957 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1958 // CHECK15-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1959 // CHECK15-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1960 // CHECK15: omp.inner.for.cond.cleanup: 1961 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1962 // CHECK15: omp.inner.for.body: 1963 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1964 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1965 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1966 // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1967 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 1968 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 1969 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] 1970 // CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 1971 // CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 1972 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 1973 // CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] 1974 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) 1975 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1976 // CHECK15: omp.body.continue: 1977 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1978 // CHECK15: omp.inner.for.inc: 1979 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1980 // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1 1981 // CHECK15-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 1982 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] 1983 // CHECK15: omp.inner.for.end: 1984 // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1985 // CHECK15: omp.loop.exit: 1986 // CHECK15-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1987 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 1988 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 1989 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1990 // CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1991 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 1992 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1993 // CHECK15: arraydestroy.body: 1994 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1995 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1996 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1997 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 1998 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1999 // CHECK15: arraydestroy.done7: 2000 // CHECK15-NEXT: ret void 2001 // 2002 // 2003 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2004 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2005 // CHECK15-NEXT: entry: 2006 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2007 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2008 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2009 // CHECK15-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2010 // CHECK15-NEXT: ret void 2011 // 2012 // 2013 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2014 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2015 // CHECK15-NEXT: entry: 2016 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2017 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2018 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2019 // CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2020 // CHECK15-NEXT: ret void 2021 // 2022 // 2023 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2024 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2025 // CHECK15-NEXT: entry: 2026 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2027 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2028 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2029 // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2030 // CHECK15-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2031 // CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2032 // CHECK15-NEXT: store float [[CONV]], ptr [[F]], align 4 2033 // CHECK15-NEXT: ret void 2034 // 2035 // 2036 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2037 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2038 // CHECK15-NEXT: entry: 2039 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2040 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2041 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2042 // CHECK15-NEXT: ret void 2043 // 2044 // 2045 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2046 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2047 // CHECK15-NEXT: entry: 2048 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2049 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2050 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2051 // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2052 // CHECK15-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2053 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 2054 // CHECK15-NEXT: ret void 2055 // 2056 // 2057 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2058 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2059 // CHECK15-NEXT: entry: 2060 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2061 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2062 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2063 // CHECK15-NEXT: ret void 2064 // 2065 // 2066 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 2067 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { 2068 // CHECK17-NEXT: entry: 2069 // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 2070 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 2071 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined) 2072 // CHECK17-NEXT: ret void 2073 // 2074 // 2075 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined 2076 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2077 // CHECK17-NEXT: entry: 2078 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2079 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2080 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2081 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 2082 // CHECK17-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 2083 // CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2084 // CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2085 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2086 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2087 // CHECK17-NEXT: [[G:%.*]] = alloca i32, align 4 2088 // CHECK17-NEXT: [[G1:%.*]] = alloca i32, align 4 2089 // CHECK17-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 2090 // CHECK17-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 2091 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 2092 // CHECK17-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 2093 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2094 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2095 // CHECK17-NEXT: store ptr undef, ptr [[_TMP1]], align 8 2096 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 2097 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 2098 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2099 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2100 // CHECK17-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 8 2101 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2102 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2103 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2104 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2105 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 2106 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2107 // CHECK17: cond.true: 2108 // CHECK17-NEXT: br label [[COND_END:%.*]] 2109 // CHECK17: cond.false: 2110 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2111 // CHECK17-NEXT: br label [[COND_END]] 2112 // CHECK17: cond.end: 2113 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2114 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2115 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2116 // CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2117 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2118 // CHECK17: omp.inner.for.cond: 2119 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2120 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2121 // CHECK17-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2122 // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2123 // CHECK17: omp.inner.for.body: 2124 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2125 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2126 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2127 // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4 2128 // CHECK17-NEXT: store i32 1, ptr [[G]], align 4 2129 // CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 2130 // CHECK17-NEXT: store volatile i32 1, ptr [[TMP8]], align 4 2131 // CHECK17-NEXT: store i32 2, ptr [[SIVAR]], align 4 2132 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 2133 // CHECK17-NEXT: store ptr [[G]], ptr [[TMP9]], align 8 2134 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 2135 // CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8 2136 // CHECK17-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8 2137 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 2 2138 // CHECK17-NEXT: store ptr [[SIVAR]], ptr [[TMP12]], align 8 2139 // CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 2140 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2141 // CHECK17: omp.body.continue: 2142 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2143 // CHECK17: omp.inner.for.inc: 2144 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2145 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 2146 // CHECK17-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 2147 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 2148 // CHECK17: omp.inner.for.end: 2149 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2150 // CHECK17: omp.loop.exit: 2151 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2152 // CHECK17-NEXT: ret void 2153 // 2154