1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 template <typename T> 29 T tmain() { 30 T t_var = T(); 31 T vec[] = {1, 2}; 32 #pragma omp target teams distribute simd reduction(+: t_var) 33 for (int i = 0; i < 2; ++i) { 34 t_var += (T) i; 35 } 36 return T(); 37 } 38 39 int main() { 40 static int sivar; 41 #ifdef LAMBDA 42 43 [&]() { 44 #pragma omp target teams distribute simd reduction(+: sivar) 45 for (int i = 0; i < 2; ++i) { 46 47 // Skip global and bound tid vars 48 49 sivar += i; 50 51 [&]() { 52 53 sivar += 4; 54 55 }(); 56 } 57 }(); 58 return 0; 59 #else 60 #pragma omp target teams distribute simd reduction(+: sivar) 61 for (int i = 0; i < 2; ++i) { 62 sivar += i; 63 } 64 return tmain<int>(); 65 #endif 66 } 67 68 69 70 71 // Skip global and bound tid vars 72 73 74 75 76 77 // Skip global and bound tid vars 78 79 80 #endif 81 // CHECK1-LABEL: define {{[^@]+}}@main 82 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 83 // CHECK1-NEXT: entry: 84 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 85 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 86 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 87 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 88 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 89 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 90 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 91 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 92 // CHECK1-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP0]], align 8 93 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 94 // CHECK1-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP1]], align 8 95 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 96 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 97 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 98 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 99 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 100 // CHECK1-NEXT: store i32 3, ptr [[TMP5]], align 4 101 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 102 // CHECK1-NEXT: store i32 1, ptr [[TMP6]], align 4 103 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 104 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8 105 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 106 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8 107 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 108 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 8 109 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 110 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 8 111 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 112 // CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8 113 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 114 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 115 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 116 // CHECK1-NEXT: store i64 2, ptr [[TMP13]], align 8 117 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 118 // CHECK1-NEXT: store i64 0, ptr [[TMP14]], align 8 119 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 120 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 121 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 122 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 4 123 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 124 // CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4 125 // CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60.region_id, ptr [[KERNEL_ARGS]]) 126 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 127 // CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 128 // CHECK1: omp_offload.failed: 129 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60(ptr @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]] 130 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 131 // CHECK1: omp_offload.cont: 132 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 133 // CHECK1-NEXT: ret i32 [[CALL]] 134 // 135 // 136 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60 137 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 138 // CHECK1-NEXT: entry: 139 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 140 // CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 141 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 142 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60.omp_outlined, ptr [[TMP0]]) 143 // CHECK1-NEXT: ret void 144 // 145 // 146 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60.omp_outlined 147 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { 148 // CHECK1-NEXT: entry: 149 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 150 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 151 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 152 // CHECK1-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 153 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 154 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 155 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 156 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 157 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 158 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 159 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 160 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 161 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 162 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 163 // CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 164 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 165 // CHECK1-NEXT: store i32 0, ptr [[SIVAR1]], align 4 166 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 167 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 168 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 169 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 170 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 171 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 172 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 173 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 174 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 175 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 176 // CHECK1: cond.true: 177 // CHECK1-NEXT: br label [[COND_END:%.*]] 178 // CHECK1: cond.false: 179 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 180 // CHECK1-NEXT: br label [[COND_END]] 181 // CHECK1: cond.end: 182 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 183 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 184 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 185 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 186 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 187 // CHECK1: omp.inner.for.cond: 188 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] 189 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 190 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 191 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 192 // CHECK1: omp.inner.for.body: 193 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 194 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 195 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 196 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] 197 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] 198 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP5]] 199 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 200 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP5]] 201 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 202 // CHECK1: omp.body.continue: 203 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 204 // CHECK1: omp.inner.for.inc: 205 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 206 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 207 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 208 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 209 // CHECK1: omp.inner.for.end: 210 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 211 // CHECK1: omp.loop.exit: 212 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 213 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 214 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 215 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 216 // CHECK1: .omp.final.then: 217 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 218 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 219 // CHECK1: .omp.final.done: 220 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 221 // CHECK1-NEXT: store ptr [[SIVAR1]], ptr [[TMP14]], align 8 222 // CHECK1-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 223 // CHECK1-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 224 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 225 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 226 // CHECK1-NEXT: ] 227 // CHECK1: .omp.reduction.case1: 228 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 229 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR1]], align 4 230 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] 231 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 232 // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 233 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 234 // CHECK1: .omp.reduction.case2: 235 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR1]], align 4 236 // CHECK1-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 237 // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 238 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 239 // CHECK1: .omp.reduction.default: 240 // CHECK1-NEXT: ret void 241 // 242 // 243 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60.omp_outlined.omp.reduction.reduction_func 244 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { 245 // CHECK1-NEXT: entry: 246 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 247 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 248 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 249 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 250 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 251 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 252 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 253 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 254 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 255 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 256 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 257 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 258 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 259 // CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 260 // CHECK1-NEXT: ret void 261 // 262 // 263 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 264 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] comdat { 265 // CHECK1-NEXT: entry: 266 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 267 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 268 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 269 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 270 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 271 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 272 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 273 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 274 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 275 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 276 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[TMP0]], align 8 277 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 278 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[TMP1]], align 8 279 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 280 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 281 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 282 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 283 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 284 // CHECK1-NEXT: store i32 3, ptr [[TMP5]], align 4 285 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 286 // CHECK1-NEXT: store i32 1, ptr [[TMP6]], align 4 287 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 288 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8 289 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 290 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8 291 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 292 // CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP9]], align 8 293 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 294 // CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP10]], align 8 295 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 296 // CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8 297 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 298 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 299 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 300 // CHECK1-NEXT: store i64 2, ptr [[TMP13]], align 8 301 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 302 // CHECK1-NEXT: store i64 0, ptr [[TMP14]], align 8 303 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 304 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 305 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 306 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 4 307 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 308 // CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4 309 // CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) 310 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 311 // CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 312 // CHECK1: omp_offload.failed: 313 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(ptr [[T_VAR]]) #[[ATTR2]] 314 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 315 // CHECK1: omp_offload.cont: 316 // CHECK1-NEXT: ret i32 0 317 // 318 // 319 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 320 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 321 // CHECK1-NEXT: entry: 322 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 323 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 324 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 325 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[TMP0]]) 326 // CHECK1-NEXT: ret void 327 // 328 // 329 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined 330 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 331 // CHECK1-NEXT: entry: 332 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 333 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 334 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 335 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 336 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 337 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 338 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 339 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 340 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 341 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 342 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 343 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 344 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 345 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 346 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 347 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 348 // CHECK1-NEXT: store i32 0, ptr [[T_VAR1]], align 4 349 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 350 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 351 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 352 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 353 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 354 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 355 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 356 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 357 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 358 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 359 // CHECK1: cond.true: 360 // CHECK1-NEXT: br label [[COND_END:%.*]] 361 // CHECK1: cond.false: 362 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 363 // CHECK1-NEXT: br label [[COND_END]] 364 // CHECK1: cond.end: 365 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 366 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 367 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 368 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 369 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 370 // CHECK1: omp.inner.for.cond: 371 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 372 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 373 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 374 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 375 // CHECK1: omp.inner.for.body: 376 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 377 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 378 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 379 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 380 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 381 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP11]] 382 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 383 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP11]] 384 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 385 // CHECK1: omp.body.continue: 386 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 387 // CHECK1: omp.inner.for.inc: 388 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 389 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 390 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 391 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 392 // CHECK1: omp.inner.for.end: 393 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 394 // CHECK1: omp.loop.exit: 395 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 396 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 397 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 398 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 399 // CHECK1: .omp.final.then: 400 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 401 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 402 // CHECK1: .omp.final.done: 403 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 404 // CHECK1-NEXT: store ptr [[T_VAR1]], ptr [[TMP14]], align 8 405 // CHECK1-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 406 // CHECK1-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 407 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 408 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 409 // CHECK1-NEXT: ] 410 // CHECK1: .omp.reduction.case1: 411 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 412 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR1]], align 4 413 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] 414 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 415 // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 416 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 417 // CHECK1: .omp.reduction.case2: 418 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR1]], align 4 419 // CHECK1-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 420 // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 421 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 422 // CHECK1: .omp.reduction.default: 423 // CHECK1-NEXT: ret void 424 // 425 // 426 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func 427 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { 428 // CHECK1-NEXT: entry: 429 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 430 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 431 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 432 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 433 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 434 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 435 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 436 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 437 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 438 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 439 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 440 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 441 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 442 // CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 443 // CHECK1-NEXT: ret void 444 // 445 // 446 // CHECK3-LABEL: define {{[^@]+}}@main 447 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 448 // CHECK3-NEXT: entry: 449 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 450 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 451 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 452 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 453 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 454 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 455 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 456 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 457 // CHECK3-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP0]], align 4 458 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 459 // CHECK3-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP1]], align 4 460 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 461 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 462 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 463 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 464 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 465 // CHECK3-NEXT: store i32 3, ptr [[TMP5]], align 4 466 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 467 // CHECK3-NEXT: store i32 1, ptr [[TMP6]], align 4 468 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 469 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4 470 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 471 // CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4 472 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 473 // CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 4 474 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 475 // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 4 476 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 477 // CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4 478 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 479 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 480 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 481 // CHECK3-NEXT: store i64 2, ptr [[TMP13]], align 8 482 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 483 // CHECK3-NEXT: store i64 0, ptr [[TMP14]], align 8 484 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 485 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 486 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 487 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 4 488 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 489 // CHECK3-NEXT: store i32 0, ptr [[TMP17]], align 4 490 // CHECK3-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60.region_id, ptr [[KERNEL_ARGS]]) 491 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 492 // CHECK3-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 493 // CHECK3: omp_offload.failed: 494 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60(ptr @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]] 495 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 496 // CHECK3: omp_offload.cont: 497 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 498 // CHECK3-NEXT: ret i32 [[CALL]] 499 // 500 // 501 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60 502 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 503 // CHECK3-NEXT: entry: 504 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 4 505 // CHECK3-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 506 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4 507 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60.omp_outlined, ptr [[TMP0]]) 508 // CHECK3-NEXT: ret void 509 // 510 // 511 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60.omp_outlined 512 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { 513 // CHECK3-NEXT: entry: 514 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 515 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 516 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 4 517 // CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 518 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 519 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 520 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 521 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 522 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 523 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 524 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 525 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 526 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 527 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 528 // CHECK3-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 529 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4 530 // CHECK3-NEXT: store i32 0, ptr [[SIVAR1]], align 4 531 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 532 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 533 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 534 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 535 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 536 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 537 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 538 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 539 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 540 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 541 // CHECK3: cond.true: 542 // CHECK3-NEXT: br label [[COND_END:%.*]] 543 // CHECK3: cond.false: 544 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 545 // CHECK3-NEXT: br label [[COND_END]] 546 // CHECK3: cond.end: 547 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 548 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 549 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 550 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 551 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 552 // CHECK3: omp.inner.for.cond: 553 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 554 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 555 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 556 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 557 // CHECK3: omp.inner.for.body: 558 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 559 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 560 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 561 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 562 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 563 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP6]] 564 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 565 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP6]] 566 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 567 // CHECK3: omp.body.continue: 568 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 569 // CHECK3: omp.inner.for.inc: 570 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 571 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 572 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 573 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 574 // CHECK3: omp.inner.for.end: 575 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 576 // CHECK3: omp.loop.exit: 577 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 578 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 579 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 580 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 581 // CHECK3: .omp.final.then: 582 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 583 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 584 // CHECK3: .omp.final.done: 585 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 586 // CHECK3-NEXT: store ptr [[SIVAR1]], ptr [[TMP14]], align 4 587 // CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 588 // CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 589 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 590 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 591 // CHECK3-NEXT: ] 592 // CHECK3: .omp.reduction.case1: 593 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 594 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR1]], align 4 595 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] 596 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 597 // CHECK3-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 598 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 599 // CHECK3: .omp.reduction.case2: 600 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR1]], align 4 601 // CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 602 // CHECK3-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 603 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 604 // CHECK3: .omp.reduction.default: 605 // CHECK3-NEXT: ret void 606 // 607 // 608 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60.omp_outlined.omp.reduction.reduction_func 609 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { 610 // CHECK3-NEXT: entry: 611 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 612 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 613 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 614 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 615 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 4 616 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 617 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i32 0, i32 0 618 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 619 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i32 0, i32 0 620 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 621 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 622 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 623 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 624 // CHECK3-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 625 // CHECK3-NEXT: ret void 626 // 627 // 628 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 629 // CHECK3-SAME: () #[[ATTR5:[0-9]+]] comdat { 630 // CHECK3-NEXT: entry: 631 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 632 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 633 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 634 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 635 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 636 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 637 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 638 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 639 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 640 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 641 // CHECK3-NEXT: store ptr [[T_VAR]], ptr [[TMP0]], align 4 642 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 643 // CHECK3-NEXT: store ptr [[T_VAR]], ptr [[TMP1]], align 4 644 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 645 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 646 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 647 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 648 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 649 // CHECK3-NEXT: store i32 3, ptr [[TMP5]], align 4 650 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 651 // CHECK3-NEXT: store i32 1, ptr [[TMP6]], align 4 652 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 653 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4 654 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 655 // CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4 656 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 657 // CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP9]], align 4 658 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 659 // CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP10]], align 4 660 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 661 // CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4 662 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 663 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 664 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 665 // CHECK3-NEXT: store i64 2, ptr [[TMP13]], align 8 666 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 667 // CHECK3-NEXT: store i64 0, ptr [[TMP14]], align 8 668 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 669 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 670 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 671 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 4 672 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 673 // CHECK3-NEXT: store i32 0, ptr [[TMP17]], align 4 674 // CHECK3-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) 675 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 676 // CHECK3-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 677 // CHECK3: omp_offload.failed: 678 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(ptr [[T_VAR]]) #[[ATTR2]] 679 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 680 // CHECK3: omp_offload.cont: 681 // CHECK3-NEXT: ret i32 0 682 // 683 // 684 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 685 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 686 // CHECK3-NEXT: entry: 687 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 688 // CHECK3-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 689 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 690 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[TMP0]]) 691 // CHECK3-NEXT: ret void 692 // 693 // 694 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined 695 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 696 // CHECK3-NEXT: entry: 697 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 698 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 699 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 700 // CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 701 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 702 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 703 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 704 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 705 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 706 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 707 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 708 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 709 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 710 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 711 // CHECK3-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 712 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 713 // CHECK3-NEXT: store i32 0, ptr [[T_VAR1]], align 4 714 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 715 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 716 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 717 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 718 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 719 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 720 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 721 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 722 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 723 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 724 // CHECK3: cond.true: 725 // CHECK3-NEXT: br label [[COND_END:%.*]] 726 // CHECK3: cond.false: 727 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 728 // CHECK3-NEXT: br label [[COND_END]] 729 // CHECK3: cond.end: 730 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 731 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 732 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 733 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 734 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 735 // CHECK3: omp.inner.for.cond: 736 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 737 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] 738 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 739 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 740 // CHECK3: omp.inner.for.body: 741 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 742 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 743 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 744 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] 745 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] 746 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP12]] 747 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 748 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP12]] 749 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 750 // CHECK3: omp.body.continue: 751 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 752 // CHECK3: omp.inner.for.inc: 753 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 754 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 755 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 756 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 757 // CHECK3: omp.inner.for.end: 758 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 759 // CHECK3: omp.loop.exit: 760 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 761 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 762 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 763 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 764 // CHECK3: .omp.final.then: 765 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 766 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 767 // CHECK3: .omp.final.done: 768 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 769 // CHECK3-NEXT: store ptr [[T_VAR1]], ptr [[TMP14]], align 4 770 // CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2]], i32 [[TMP2]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 771 // CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 772 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 773 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 774 // CHECK3-NEXT: ] 775 // CHECK3: .omp.reduction.case1: 776 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 777 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR1]], align 4 778 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] 779 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 780 // CHECK3-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 781 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 782 // CHECK3: .omp.reduction.case2: 783 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR1]], align 4 784 // CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 785 // CHECK3-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 786 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 787 // CHECK3: .omp.reduction.default: 788 // CHECK3-NEXT: ret void 789 // 790 // 791 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func 792 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { 793 // CHECK3-NEXT: entry: 794 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 795 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 796 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 797 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 798 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 4 799 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 800 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i32 0, i32 0 801 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 802 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i32 0, i32 0 803 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 804 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 805 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 806 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 807 // CHECK3-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 808 // CHECK3-NEXT: ret void 809 // 810 // 811 // CHECK5-LABEL: define {{[^@]+}}@main 812 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 813 // CHECK5-NEXT: entry: 814 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 815 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 816 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 817 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 818 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 819 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 820 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 821 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 822 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 823 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 824 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 825 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 826 // CHECK5-NEXT: store i32 0, ptr [[SIVAR]], align 4 827 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 828 // CHECK5: omp.inner.for.cond: 829 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 830 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 831 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 832 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 833 // CHECK5: omp.inner.for.body: 834 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 835 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 836 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 837 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 838 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 839 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] 840 // CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 841 // CHECK5-NEXT: store i32 [[ADD1]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] 842 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 843 // CHECK5: omp.body.continue: 844 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 845 // CHECK5: omp.inner.for.inc: 846 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 847 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 848 // CHECK5-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 849 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 850 // CHECK5: omp.inner.for.end: 851 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 852 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 853 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4 854 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 855 // CHECK5-NEXT: store i32 [[ADD3]], ptr @_ZZ4mainE5sivar, align 4 856 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 857 // CHECK5-NEXT: ret i32 [[CALL]] 858 // 859 // 860 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 861 // CHECK5-SAME: () #[[ATTR1:[0-9]+]] comdat { 862 // CHECK5-NEXT: entry: 863 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 864 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 865 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 866 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 867 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 868 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 869 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 870 // CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 871 // CHECK5-NEXT: store i32 0, ptr [[T_VAR]], align 4 872 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 873 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 874 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 875 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 876 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 877 // CHECK5-NEXT: store i32 0, ptr [[T_VAR1]], align 4 878 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 879 // CHECK5: omp.inner.for.cond: 880 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 881 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 882 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 883 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 884 // CHECK5: omp.inner.for.body: 885 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 886 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 887 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 888 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 889 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 890 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP6]] 891 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 892 // CHECK5-NEXT: store i32 [[ADD2]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP6]] 893 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 894 // CHECK5: omp.body.continue: 895 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 896 // CHECK5: omp.inner.for.inc: 897 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 898 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP6]], 1 899 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 900 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 901 // CHECK5: omp.inner.for.end: 902 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 903 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4 904 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR1]], align 4 905 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 906 // CHECK5-NEXT: store i32 [[ADD4]], ptr [[T_VAR]], align 4 907 // CHECK5-NEXT: ret i32 0 908 // 909 // 910 // CHECK7-LABEL: define {{[^@]+}}@main 911 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 912 // CHECK7-NEXT: entry: 913 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 914 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 915 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 916 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 917 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 918 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 919 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 920 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 921 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 922 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 923 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 924 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 925 // CHECK7-NEXT: store i32 0, ptr [[SIVAR]], align 4 926 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 927 // CHECK7: omp.inner.for.cond: 928 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 929 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 930 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 931 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 932 // CHECK7: omp.inner.for.body: 933 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 934 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 935 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 936 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 937 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 938 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] 939 // CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 940 // CHECK7-NEXT: store i32 [[ADD1]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] 941 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 942 // CHECK7: omp.body.continue: 943 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 944 // CHECK7: omp.inner.for.inc: 945 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 946 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 947 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 948 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 949 // CHECK7: omp.inner.for.end: 950 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 951 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 952 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4 953 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 954 // CHECK7-NEXT: store i32 [[ADD3]], ptr @_ZZ4mainE5sivar, align 4 955 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 956 // CHECK7-NEXT: ret i32 [[CALL]] 957 // 958 // 959 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 960 // CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat { 961 // CHECK7-NEXT: entry: 962 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 963 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 964 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 965 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 966 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 967 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 968 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 969 // CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 970 // CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 4 971 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 972 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 973 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 974 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 975 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 976 // CHECK7-NEXT: store i32 0, ptr [[T_VAR1]], align 4 977 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 978 // CHECK7: omp.inner.for.cond: 979 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 980 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]] 981 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 982 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 983 // CHECK7: omp.inner.for.body: 984 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 985 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 986 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 987 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 988 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 989 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP7]] 990 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 991 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP7]] 992 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 993 // CHECK7: omp.body.continue: 994 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 995 // CHECK7: omp.inner.for.inc: 996 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 997 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP6]], 1 998 // CHECK7-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 999 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 1000 // CHECK7: omp.inner.for.end: 1001 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 1002 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4 1003 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR1]], align 4 1004 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 1005 // CHECK7-NEXT: store i32 [[ADD4]], ptr [[T_VAR]], align 4 1006 // CHECK7-NEXT: ret i32 0 1007 // 1008 // 1009 // CHECK9-LABEL: define {{[^@]+}}@main 1010 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 1011 // CHECK9-NEXT: entry: 1012 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1013 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1014 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 1015 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 1016 // CHECK9-NEXT: ret i32 0 1017 // 1018 // 1019 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44 1020 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 1021 // CHECK9-NEXT: entry: 1022 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 1023 // CHECK9-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 1024 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 1025 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44.omp_outlined, ptr [[TMP0]]) 1026 // CHECK9-NEXT: ret void 1027 // 1028 // 1029 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44.omp_outlined 1030 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { 1031 // CHECK9-NEXT: entry: 1032 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1033 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1034 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 1035 // CHECK9-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 1036 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1037 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1038 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1039 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1040 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1041 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1042 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1043 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1044 // CHECK9-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 1045 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1046 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1047 // CHECK9-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 1048 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 1049 // CHECK9-NEXT: store i32 0, ptr [[SIVAR1]], align 4 1050 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1051 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1052 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1053 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1054 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1055 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 1056 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1057 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1058 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 1059 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1060 // CHECK9: cond.true: 1061 // CHECK9-NEXT: br label [[COND_END:%.*]] 1062 // CHECK9: cond.false: 1063 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1064 // CHECK9-NEXT: br label [[COND_END]] 1065 // CHECK9: cond.end: 1066 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1067 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1068 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1069 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 1070 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1071 // CHECK9: omp.inner.for.cond: 1072 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]] 1073 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]] 1074 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1075 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1076 // CHECK9: omp.inner.for.body: 1077 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 1078 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 1079 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1080 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] 1081 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] 1082 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP4]] 1083 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 1084 // CHECK9-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP4]] 1085 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 1086 // CHECK9-NEXT: store ptr [[SIVAR1]], ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP4]] 1087 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group [[ACC_GRP4]] 1088 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1089 // CHECK9: omp.body.continue: 1090 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1091 // CHECK9: omp.inner.for.inc: 1092 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 1093 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 1094 // CHECK9-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 1095 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 1096 // CHECK9: omp.inner.for.end: 1097 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1098 // CHECK9: omp.loop.exit: 1099 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 1100 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1101 // CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1102 // CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1103 // CHECK9: .omp.final.then: 1104 // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 1105 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 1106 // CHECK9: .omp.final.done: 1107 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 1108 // CHECK9-NEXT: store ptr [[SIVAR1]], ptr [[TMP15]], align 8 1109 // CHECK9-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 1110 // CHECK9-NEXT: switch i32 [[TMP16]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1111 // CHECK9-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1112 // CHECK9-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1113 // CHECK9-NEXT: ] 1114 // CHECK9: .omp.reduction.case1: 1115 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP0]], align 4 1116 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR1]], align 4 1117 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] 1118 // CHECK9-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 1119 // CHECK9-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 1120 // CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1121 // CHECK9: .omp.reduction.case2: 1122 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR1]], align 4 1123 // CHECK9-NEXT: [[TMP20:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP19]] monotonic, align 4 1124 // CHECK9-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 1125 // CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1126 // CHECK9: .omp.reduction.default: 1127 // CHECK9-NEXT: ret void 1128 // 1129 // 1130 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44.omp_outlined.omp.reduction.reduction_func 1131 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { 1132 // CHECK9-NEXT: entry: 1133 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1134 // CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 1135 // CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1136 // CHECK9-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 1137 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1138 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 1139 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 1140 // CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 1141 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 1142 // CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 1143 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1144 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 1145 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 1146 // CHECK9-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 1147 // CHECK9-NEXT: ret void 1148 // 1149 // 1150 // CHECK11-LABEL: define {{[^@]+}}@main 1151 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 1152 // CHECK11-NEXT: entry: 1153 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1154 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1155 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 1156 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 1157 // CHECK11-NEXT: ret i32 0 1158 // 1159