1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target teams distribute simd firstprivate(t_var, vec, s_arr, var) 57 for (int i = 0; i < 2; ++i) { 58 vec[i] = t_var; 59 s_arr[i] = var; 60 } 61 return T(); 62 } 63 64 S<float> test; 65 int t_var = 333; 66 int vec[] = {1, 2}; 67 S<float> s_arr[] = {1, 2}; 68 S<float> var(3); 69 70 int main() { 71 static int sivar; 72 #ifdef LAMBDA 73 [&]() { 74 #pragma omp target teams distribute simd firstprivate(g, g1, sivar) 75 for (int i = 0; i < 2; ++i) { 76 77 // Skip global and bound tid vars 78 // skip loop vars 79 g = 1; 80 g1 = 1; 81 sivar = 2; 82 [&]() { 83 g = 2; 84 g1 = 2; 85 sivar = 4; 86 87 }(); 88 } 89 }(); 90 return 0; 91 #else 92 #pragma omp target teams distribute simd firstprivate(t_var, vec, s_arr, var, sivar) 93 for (int i = 0; i < 2; ++i) { 94 vec[i] = t_var; 95 s_arr[i] = var; 96 sivar += i; 97 } 98 return tmain<int>(); 99 #endif 100 } 101 102 103 104 105 106 // Skip global and bound tid vars 107 // Skip temp vars for loop 108 109 // param copy 110 111 // T_VAR and SIVAR 112 113 // preparation vars 114 115 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 116 117 // firstprivate(s_arr) 118 119 // firstprivate(var) 120 121 122 123 124 125 126 // Skip global and bound tid vars 127 // Skip temp vars for loop 128 129 // param copy 130 131 132 // T_VAR and preparation variables 133 134 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 135 136 // firstprivate(s_arr) 137 138 // firstprivate(var) 139 140 141 #endif 142 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 143 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 144 // CHECK1-NEXT: entry: 145 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 146 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 147 // CHECK1-NEXT: ret void 148 // 149 // 150 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 151 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 152 // CHECK1-NEXT: entry: 153 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 154 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 155 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 156 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 157 // CHECK1-NEXT: ret void 158 // 159 // 160 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 161 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 162 // CHECK1-NEXT: entry: 163 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 164 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 165 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 166 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 167 // CHECK1-NEXT: ret void 168 // 169 // 170 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 171 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 172 // CHECK1-NEXT: entry: 173 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 174 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 175 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 176 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 177 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 178 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 179 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 180 // CHECK1-NEXT: ret void 181 // 182 // 183 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 184 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 185 // CHECK1-NEXT: entry: 186 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 187 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 188 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 189 // CHECK1-NEXT: ret void 190 // 191 // 192 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 193 // CHECK1-SAME: () #[[ATTR0]] { 194 // CHECK1-NEXT: entry: 195 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 196 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 197 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 198 // CHECK1-NEXT: ret void 199 // 200 // 201 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 202 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 203 // CHECK1-NEXT: entry: 204 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 205 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 206 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 207 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 208 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 209 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 210 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 211 // CHECK1-NEXT: ret void 212 // 213 // 214 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 215 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 216 // CHECK1-NEXT: entry: 217 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 218 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 219 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 220 // CHECK1: arraydestroy.body: 221 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 222 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 223 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 224 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 225 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 226 // CHECK1: arraydestroy.done1: 227 // CHECK1-NEXT: ret void 228 // 229 // 230 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 231 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 232 // CHECK1-NEXT: entry: 233 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 234 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 235 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 236 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 237 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 238 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 239 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 240 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 241 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 242 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 243 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 244 // CHECK1-NEXT: ret void 245 // 246 // 247 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 248 // CHECK1-SAME: () #[[ATTR0]] { 249 // CHECK1-NEXT: entry: 250 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 251 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 252 // CHECK1-NEXT: ret void 253 // 254 // 255 // CHECK1-LABEL: define {{[^@]+}}@main 256 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 257 // CHECK1-NEXT: entry: 258 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 259 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 260 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 261 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 262 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 263 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 264 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 265 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 266 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 267 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr @t_var, align 4 268 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 269 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 270 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 271 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 272 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 273 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 274 // CHECK1-NEXT: store ptr @vec, ptr [[TMP4]], align 8 275 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 276 // CHECK1-NEXT: store ptr @vec, ptr [[TMP5]], align 8 277 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 278 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 279 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 280 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP7]], align 8 281 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 282 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP8]], align 8 283 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 284 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 285 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 286 // CHECK1-NEXT: store ptr @s_arr, ptr [[TMP10]], align 8 287 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 288 // CHECK1-NEXT: store ptr @s_arr, ptr [[TMP11]], align 8 289 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 290 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 291 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 292 // CHECK1-NEXT: store ptr @var, ptr [[TMP13]], align 8 293 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 294 // CHECK1-NEXT: store ptr @var, ptr [[TMP14]], align 8 295 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 296 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 297 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 298 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP16]], align 8 299 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 300 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP17]], align 8 301 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 302 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 303 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 304 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 305 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 306 // CHECK1-NEXT: store i32 3, ptr [[TMP21]], align 4 307 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 308 // CHECK1-NEXT: store i32 5, ptr [[TMP22]], align 4 309 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 310 // CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8 311 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 312 // CHECK1-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8 313 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 314 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 8 315 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 316 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 8 317 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 318 // CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8 319 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 320 // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8 321 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 322 // CHECK1-NEXT: store i64 2, ptr [[TMP29]], align 8 323 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 324 // CHECK1-NEXT: store i64 0, ptr [[TMP30]], align 8 325 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 326 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 327 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 328 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP32]], align 4 329 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 330 // CHECK1-NEXT: store i32 0, ptr [[TMP33]], align 4 331 // CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.region_id, ptr [[KERNEL_ARGS]]) 332 // CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 333 // CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 334 // CHECK1: omp_offload.failed: 335 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92(ptr @vec, i64 [[TMP1]], ptr @s_arr, ptr @var, i64 [[TMP3]]) #[[ATTR2]] 336 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 337 // CHECK1: omp_offload.cont: 338 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 339 // CHECK1-NEXT: ret i32 [[CALL]] 340 // 341 // 342 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 343 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 344 // CHECK1-NEXT: entry: 345 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 346 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 347 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 348 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 349 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 350 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 351 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 352 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 353 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 354 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 355 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 356 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 357 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 358 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 359 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 360 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 361 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 362 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 363 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 364 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 365 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 366 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]]) 367 // CHECK1-NEXT: ret void 368 // 369 // 370 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.omp_outlined 371 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 372 // CHECK1-NEXT: entry: 373 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 374 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 375 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 376 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 377 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 378 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 379 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 380 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 381 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 382 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 383 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 384 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 385 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 386 // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 387 // CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 388 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 389 // CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 390 // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 391 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 392 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 393 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 394 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 395 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 396 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 397 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 398 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 399 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 400 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 401 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 402 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 403 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 404 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 405 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 406 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) 407 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 408 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 409 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 410 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 411 // CHECK1: omp.arraycpy.body: 412 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 413 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 414 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 415 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 416 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 417 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 418 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 419 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 420 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 421 // CHECK1: omp.arraycpy.done3: 422 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 423 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 424 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 425 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 426 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 427 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 428 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 429 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 430 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 431 // CHECK1: cond.true: 432 // CHECK1-NEXT: br label [[COND_END:%.*]] 433 // CHECK1: cond.false: 434 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 435 // CHECK1-NEXT: br label [[COND_END]] 436 // CHECK1: cond.end: 437 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 438 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 439 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 440 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 441 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 442 // CHECK1: omp.inner.for.cond: 443 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] 444 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 445 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 446 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 447 // CHECK1: omp.inner.for.cond.cleanup: 448 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 449 // CHECK1: omp.inner.for.body: 450 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 451 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 452 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 453 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] 454 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP5]] 455 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] 456 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 457 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 [[IDXPROM]] 458 // CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] 459 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] 460 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 461 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]] 462 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR4]], i64 4, i1 false), !llvm.access.group [[ACC_GRP5]] 463 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] 464 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP5]] 465 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 466 // CHECK1-NEXT: store i32 [[ADD9]], ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP5]] 467 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 468 // CHECK1: omp.body.continue: 469 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 470 // CHECK1: omp.inner.for.inc: 471 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 472 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP17]], 1 473 // CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 474 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 475 // CHECK1: omp.inner.for.end: 476 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 477 // CHECK1: omp.loop.exit: 478 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 479 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 480 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) 481 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 482 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 483 // CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 484 // CHECK1: .omp.final.then: 485 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 486 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 487 // CHECK1: .omp.final.done: 488 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 489 // CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 490 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 491 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 492 // CHECK1: arraydestroy.body: 493 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 494 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 495 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 496 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 497 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 498 // CHECK1: arraydestroy.done12: 499 // CHECK1-NEXT: ret void 500 // 501 // 502 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev 503 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 504 // CHECK1-NEXT: entry: 505 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 506 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 507 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 508 // CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 509 // CHECK1-NEXT: ret void 510 // 511 // 512 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 513 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 514 // CHECK1-NEXT: entry: 515 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 516 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 517 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 518 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 519 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 520 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 521 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 522 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 523 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 524 // CHECK1-NEXT: ret void 525 // 526 // 527 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev 528 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 529 // CHECK1-NEXT: entry: 530 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 531 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 532 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 533 // CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 534 // CHECK1-NEXT: ret void 535 // 536 // 537 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 538 // CHECK1-SAME: () #[[ATTR1]] comdat { 539 // CHECK1-NEXT: entry: 540 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 541 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 542 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 543 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 544 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 545 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 546 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 547 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 548 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 549 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 550 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 551 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 552 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 553 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 554 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 555 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 556 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 557 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 558 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 559 // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 560 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 561 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 562 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 563 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 564 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 565 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 566 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 567 // CHECK1-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 8 568 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 569 // CHECK1-NEXT: store ptr [[VEC]], ptr [[TMP5]], align 8 570 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 571 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 572 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 573 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP7]], align 8 574 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 575 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP8]], align 8 576 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 577 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 578 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 579 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[TMP10]], align 8 580 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 581 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[TMP11]], align 8 582 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 583 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 584 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 585 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 8 586 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 587 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 8 588 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 589 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 590 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 591 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 592 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 593 // CHECK1-NEXT: store i32 3, ptr [[TMP18]], align 4 594 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 595 // CHECK1-NEXT: store i32 4, ptr [[TMP19]], align 4 596 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 597 // CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 8 598 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 599 // CHECK1-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 8 600 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 601 // CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP22]], align 8 602 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 603 // CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP23]], align 8 604 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 605 // CHECK1-NEXT: store ptr null, ptr [[TMP24]], align 8 606 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 607 // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 608 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 609 // CHECK1-NEXT: store i64 2, ptr [[TMP26]], align 8 610 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 611 // CHECK1-NEXT: store i64 0, ptr [[TMP27]], align 8 612 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 613 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 614 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 615 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4 616 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 617 // CHECK1-NEXT: store i32 0, ptr [[TMP30]], align 4 618 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 619 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 620 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 621 // CHECK1: omp_offload.failed: 622 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(ptr [[VEC]], i64 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]] 623 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 624 // CHECK1: omp_offload.cont: 625 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 626 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 627 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 628 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 629 // CHECK1: arraydestroy.body: 630 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 631 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 632 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 633 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 634 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 635 // CHECK1: arraydestroy.done2: 636 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 637 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 638 // CHECK1-NEXT: ret i32 [[TMP34]] 639 // 640 // 641 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev 642 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 643 // CHECK1-NEXT: entry: 644 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 645 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 646 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 647 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 648 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 649 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 650 // CHECK1-NEXT: store i32 0, ptr [[B]], align 4 651 // CHECK1-NEXT: ret void 652 // 653 // 654 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 655 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 656 // CHECK1-NEXT: entry: 657 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 658 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 659 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 660 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 661 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 662 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 663 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 664 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 665 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 666 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 667 // CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 668 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 669 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 670 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 671 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 672 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 673 // CHECK1-NEXT: ret void 674 // 675 // 676 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev 677 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 678 // CHECK1-NEXT: entry: 679 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 680 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 681 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 682 // CHECK1-NEXT: ret void 683 // 684 // 685 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 686 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 687 // CHECK1-NEXT: entry: 688 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 689 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 690 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 691 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 692 // CHECK1-NEXT: ret void 693 // 694 // 695 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 696 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 697 // CHECK1-NEXT: entry: 698 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 699 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 700 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 701 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 702 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 703 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 704 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 705 // CHECK1-NEXT: ret void 706 // 707 // 708 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 709 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 710 // CHECK1-NEXT: entry: 711 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 712 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 713 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 714 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 715 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 716 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 717 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 718 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 719 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 720 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 721 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 722 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 723 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 724 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 725 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 726 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 727 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 728 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 729 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) 730 // CHECK1-NEXT: ret void 731 // 732 // 733 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 734 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 735 // CHECK1-NEXT: entry: 736 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 737 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 738 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 739 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 740 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 741 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 742 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 743 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 744 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 745 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 746 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 747 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 748 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 749 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 750 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 751 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 752 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 753 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 754 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 755 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 756 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 757 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 758 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 759 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 760 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 761 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 762 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 763 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 764 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 765 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 766 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 767 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 768 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 769 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 770 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) 771 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 772 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 773 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 774 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 775 // CHECK1: omp.arraycpy.body: 776 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 777 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 778 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 779 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 780 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 781 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 782 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 783 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 784 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 785 // CHECK1: omp.arraycpy.done4: 786 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 787 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 788 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) 789 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 790 // CHECK1-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8 791 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 792 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 793 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 794 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 795 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 796 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 797 // CHECK1: cond.true: 798 // CHECK1-NEXT: br label [[COND_END:%.*]] 799 // CHECK1: cond.false: 800 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 801 // CHECK1-NEXT: br label [[COND_END]] 802 // CHECK1: cond.end: 803 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 804 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 805 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 806 // CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 807 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 808 // CHECK1: omp.inner.for.cond: 809 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 810 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 811 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 812 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 813 // CHECK1: omp.inner.for.cond.cleanup: 814 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 815 // CHECK1: omp.inner.for.body: 816 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 817 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 818 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 819 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 820 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP11]] 821 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 822 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 823 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] 824 // CHECK1-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] 825 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP11]] 826 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 827 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP16]] to i64 828 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]] 829 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]] 830 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 831 // CHECK1: omp.body.continue: 832 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 833 // CHECK1: omp.inner.for.inc: 834 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 835 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 836 // CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 837 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 838 // CHECK1: omp.inner.for.end: 839 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 840 // CHECK1: omp.loop.exit: 841 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 842 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 843 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) 844 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 845 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 846 // CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 847 // CHECK1: .omp.final.then: 848 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 849 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 850 // CHECK1: .omp.final.done: 851 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 852 // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 853 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 854 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 855 // CHECK1: arraydestroy.body: 856 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 857 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 858 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 859 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 860 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 861 // CHECK1: arraydestroy.done13: 862 // CHECK1-NEXT: ret void 863 // 864 // 865 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 866 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 867 // CHECK1-NEXT: entry: 868 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 869 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 870 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 871 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 872 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 873 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 874 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 875 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 876 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 877 // CHECK1-NEXT: ret void 878 // 879 // 880 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 881 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 882 // CHECK1-NEXT: entry: 883 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 884 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 885 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 886 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 887 // CHECK1-NEXT: ret void 888 // 889 // 890 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 891 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 892 // CHECK1-NEXT: entry: 893 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 894 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 895 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 896 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 897 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 898 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 899 // CHECK1-NEXT: ret void 900 // 901 // 902 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 903 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 904 // CHECK1-NEXT: entry: 905 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 906 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 907 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 908 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 909 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 910 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 911 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 912 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 913 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 914 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 915 // CHECK1-NEXT: ret void 916 // 917 // 918 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 919 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 920 // CHECK1-NEXT: entry: 921 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 922 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 923 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 924 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 925 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 926 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 927 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 928 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 929 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 930 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 931 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 932 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 933 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 934 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 935 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 936 // CHECK1-NEXT: ret void 937 // 938 // 939 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 940 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 941 // CHECK1-NEXT: entry: 942 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 943 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 944 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 945 // CHECK1-NEXT: ret void 946 // 947 // 948 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 949 // CHECK1-SAME: () #[[ATTR0]] { 950 // CHECK1-NEXT: entry: 951 // CHECK1-NEXT: call void @__cxx_global_var_init() 952 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 953 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 954 // CHECK1-NEXT: ret void 955 // 956 // 957 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 958 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 959 // CHECK3-NEXT: entry: 960 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 961 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 962 // CHECK3-NEXT: ret void 963 // 964 // 965 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 966 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 967 // CHECK3-NEXT: entry: 968 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 969 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 970 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 971 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 972 // CHECK3-NEXT: ret void 973 // 974 // 975 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 976 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 977 // CHECK3-NEXT: entry: 978 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 979 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 980 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 981 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 982 // CHECK3-NEXT: ret void 983 // 984 // 985 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 986 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 987 // CHECK3-NEXT: entry: 988 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 989 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 990 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 991 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 992 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 993 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 994 // CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4 995 // CHECK3-NEXT: ret void 996 // 997 // 998 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 999 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1000 // CHECK3-NEXT: entry: 1001 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1002 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1003 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1004 // CHECK3-NEXT: ret void 1005 // 1006 // 1007 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1008 // CHECK3-SAME: () #[[ATTR0]] { 1009 // CHECK3-NEXT: entry: 1010 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 1011 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 1012 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 1013 // CHECK3-NEXT: ret void 1014 // 1015 // 1016 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1017 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1018 // CHECK3-NEXT: entry: 1019 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1020 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1021 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1022 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1023 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1024 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1025 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1026 // CHECK3-NEXT: ret void 1027 // 1028 // 1029 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1030 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1031 // CHECK3-NEXT: entry: 1032 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 1033 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 1034 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1035 // CHECK3: arraydestroy.body: 1036 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1037 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1038 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1039 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1040 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1041 // CHECK3: arraydestroy.done1: 1042 // CHECK3-NEXT: ret void 1043 // 1044 // 1045 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1046 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1047 // CHECK3-NEXT: entry: 1048 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1049 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1050 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1051 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1052 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1053 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1054 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1055 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1056 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1057 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1058 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 1059 // CHECK3-NEXT: ret void 1060 // 1061 // 1062 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1063 // CHECK3-SAME: () #[[ATTR0]] { 1064 // CHECK3-NEXT: entry: 1065 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1066 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1067 // CHECK3-NEXT: ret void 1068 // 1069 // 1070 // CHECK3-LABEL: define {{[^@]+}}@main 1071 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1072 // CHECK3-NEXT: entry: 1073 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1074 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1075 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1076 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 1077 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 1078 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 1079 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1080 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1081 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1082 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr @t_var, align 4 1083 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 1084 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1085 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 1086 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 1087 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 1088 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1089 // CHECK3-NEXT: store ptr @vec, ptr [[TMP4]], align 4 1090 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1091 // CHECK3-NEXT: store ptr @vec, ptr [[TMP5]], align 4 1092 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1093 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1094 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1095 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 4 1096 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1097 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 4 1098 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1099 // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 1100 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1101 // CHECK3-NEXT: store ptr @s_arr, ptr [[TMP10]], align 4 1102 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1103 // CHECK3-NEXT: store ptr @s_arr, ptr [[TMP11]], align 4 1104 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1105 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 1106 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1107 // CHECK3-NEXT: store ptr @var, ptr [[TMP13]], align 4 1108 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1109 // CHECK3-NEXT: store ptr @var, ptr [[TMP14]], align 4 1110 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1111 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 1112 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1113 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP16]], align 4 1114 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1115 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP17]], align 4 1116 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1117 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 1118 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1119 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1120 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1121 // CHECK3-NEXT: store i32 3, ptr [[TMP21]], align 4 1122 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1123 // CHECK3-NEXT: store i32 5, ptr [[TMP22]], align 4 1124 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1125 // CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4 1126 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1127 // CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4 1128 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1129 // CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 4 1130 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1131 // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 4 1132 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1133 // CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 4 1134 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1135 // CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 4 1136 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1137 // CHECK3-NEXT: store i64 2, ptr [[TMP29]], align 8 1138 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1139 // CHECK3-NEXT: store i64 0, ptr [[TMP30]], align 8 1140 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1141 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 1142 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1143 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP32]], align 4 1144 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1145 // CHECK3-NEXT: store i32 0, ptr [[TMP33]], align 4 1146 // CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.region_id, ptr [[KERNEL_ARGS]]) 1147 // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 1148 // CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1149 // CHECK3: omp_offload.failed: 1150 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92(ptr @vec, i32 [[TMP1]], ptr @s_arr, ptr @var, i32 [[TMP3]]) #[[ATTR2]] 1151 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1152 // CHECK3: omp_offload.cont: 1153 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1154 // CHECK3-NEXT: ret i32 [[CALL]] 1155 // 1156 // 1157 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 1158 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 1159 // CHECK3-NEXT: entry: 1160 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1161 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1162 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1163 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1164 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1165 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1166 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1167 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1168 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1169 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1170 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1171 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 1172 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1173 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1174 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1175 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1176 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 1177 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1178 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 1179 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 1180 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 1181 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]]) 1182 // CHECK3-NEXT: ret void 1183 // 1184 // 1185 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.omp_outlined 1186 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 1187 // CHECK3-NEXT: entry: 1188 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1189 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1190 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1191 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1192 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1193 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1194 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1195 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1196 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1197 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1198 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1199 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1200 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1201 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 1202 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 1203 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1204 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1205 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 1206 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1207 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1208 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1209 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1210 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1211 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1212 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1213 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 1214 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1215 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1216 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1217 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1218 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1219 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1220 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1221 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) 1222 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1223 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1224 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 1225 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1226 // CHECK3: omp.arraycpy.body: 1227 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1228 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1229 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1230 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 1231 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1232 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1233 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1234 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 1235 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 1236 // CHECK3: omp.arraycpy.done3: 1237 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 1238 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 1239 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 1240 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1241 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 1242 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1243 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1244 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 1245 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1246 // CHECK3: cond.true: 1247 // CHECK3-NEXT: br label [[COND_END:%.*]] 1248 // CHECK3: cond.false: 1249 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1250 // CHECK3-NEXT: br label [[COND_END]] 1251 // CHECK3: cond.end: 1252 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1253 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1254 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1255 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 1256 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1257 // CHECK3: omp.inner.for.cond: 1258 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 1259 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 1260 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1261 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1262 // CHECK3: omp.inner.for.cond.cleanup: 1263 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1264 // CHECK3: omp.inner.for.body: 1265 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1266 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 1267 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1268 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1269 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP6]] 1270 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1271 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP13]] 1272 // CHECK3-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] 1273 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1274 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP14]] 1275 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false), !llvm.access.group [[ACC_GRP6]] 1276 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1277 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP6]] 1278 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 1279 // CHECK3-NEXT: store i32 [[ADD8]], ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP6]] 1280 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1281 // CHECK3: omp.body.continue: 1282 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1283 // CHECK3: omp.inner.for.inc: 1284 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1285 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], 1 1286 // CHECK3-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1287 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1288 // CHECK3: omp.inner.for.end: 1289 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1290 // CHECK3: omp.loop.exit: 1291 // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1292 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 1293 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) 1294 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1295 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 1296 // CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1297 // CHECK3: .omp.final.then: 1298 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 1299 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1300 // CHECK3: .omp.final.done: 1301 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 1302 // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1303 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 1304 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1305 // CHECK3: arraydestroy.body: 1306 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1307 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1308 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1309 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 1310 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 1311 // CHECK3: arraydestroy.done11: 1312 // CHECK3-NEXT: ret void 1313 // 1314 // 1315 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev 1316 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1317 // CHECK3-NEXT: entry: 1318 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1319 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1320 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1321 // CHECK3-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 1322 // CHECK3-NEXT: ret void 1323 // 1324 // 1325 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 1326 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1327 // CHECK3-NEXT: entry: 1328 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1329 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1330 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1331 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1332 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1333 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1334 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1335 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1336 // CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 1337 // CHECK3-NEXT: ret void 1338 // 1339 // 1340 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev 1341 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1342 // CHECK3-NEXT: entry: 1343 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1344 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1345 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1346 // CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 1347 // CHECK3-NEXT: ret void 1348 // 1349 // 1350 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1351 // CHECK3-SAME: () #[[ATTR1]] comdat { 1352 // CHECK3-NEXT: entry: 1353 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1354 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1355 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1356 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1357 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1358 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 1359 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1360 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1361 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 1362 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 1363 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 1364 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1365 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1366 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1367 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 1368 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 1369 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 1370 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 1371 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1372 // CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 1373 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 1374 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 1375 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 1376 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 1377 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1378 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 1379 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1380 // CHECK3-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 4 1381 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1382 // CHECK3-NEXT: store ptr [[VEC]], ptr [[TMP5]], align 4 1383 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1384 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1385 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1386 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP7]], align 4 1387 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1388 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP8]], align 4 1389 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1390 // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 1391 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1392 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[TMP10]], align 4 1393 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1394 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[TMP11]], align 4 1395 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1396 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 1397 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1398 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 4 1399 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1400 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 4 1401 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1402 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 1403 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1404 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1405 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1406 // CHECK3-NEXT: store i32 3, ptr [[TMP18]], align 4 1407 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1408 // CHECK3-NEXT: store i32 4, ptr [[TMP19]], align 4 1409 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1410 // CHECK3-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 4 1411 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1412 // CHECK3-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 4 1413 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1414 // CHECK3-NEXT: store ptr @.offload_sizes.3, ptr [[TMP22]], align 4 1415 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1416 // CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP23]], align 4 1417 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1418 // CHECK3-NEXT: store ptr null, ptr [[TMP24]], align 4 1419 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1420 // CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4 1421 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1422 // CHECK3-NEXT: store i64 2, ptr [[TMP26]], align 8 1423 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1424 // CHECK3-NEXT: store i64 0, ptr [[TMP27]], align 8 1425 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1426 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 1427 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1428 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4 1429 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1430 // CHECK3-NEXT: store i32 0, ptr [[TMP30]], align 4 1431 // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 1432 // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1433 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1434 // CHECK3: omp_offload.failed: 1435 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(ptr [[VEC]], i32 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]] 1436 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1437 // CHECK3: omp_offload.cont: 1438 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1439 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1440 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1441 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1442 // CHECK3: arraydestroy.body: 1443 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1444 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1445 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1446 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1447 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1448 // CHECK3: arraydestroy.done2: 1449 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1450 // CHECK3-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 1451 // CHECK3-NEXT: ret i32 [[TMP34]] 1452 // 1453 // 1454 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev 1455 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1456 // CHECK3-NEXT: entry: 1457 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1458 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1459 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1460 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 1461 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 1462 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 1463 // CHECK3-NEXT: store i32 0, ptr [[B]], align 4 1464 // CHECK3-NEXT: ret void 1465 // 1466 // 1467 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 1468 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1469 // CHECK3-NEXT: entry: 1470 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1471 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1472 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1473 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1474 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1475 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1476 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1477 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1478 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1479 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 1480 // CHECK3-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 1481 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 1482 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1483 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 1484 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 1485 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 1486 // CHECK3-NEXT: ret void 1487 // 1488 // 1489 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev 1490 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1491 // CHECK3-NEXT: entry: 1492 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1493 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1494 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1495 // CHECK3-NEXT: ret void 1496 // 1497 // 1498 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1499 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1500 // CHECK3-NEXT: entry: 1501 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1502 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1503 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1504 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1505 // CHECK3-NEXT: ret void 1506 // 1507 // 1508 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1509 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1510 // CHECK3-NEXT: entry: 1511 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1512 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1513 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1514 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1515 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1516 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1517 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1518 // CHECK3-NEXT: ret void 1519 // 1520 // 1521 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1522 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1523 // CHECK3-NEXT: entry: 1524 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1525 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1526 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1527 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1528 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1529 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1530 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1531 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1532 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1533 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1534 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1535 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1536 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1537 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 1538 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1539 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 1540 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1541 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 1542 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) 1543 // CHECK3-NEXT: ret void 1544 // 1545 // 1546 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 1547 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1548 // CHECK3-NEXT: entry: 1549 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1550 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1551 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1552 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1553 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1554 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1555 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1556 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1557 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1558 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1559 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1560 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1561 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1562 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 1563 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 1564 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1565 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1566 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1567 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 1568 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1569 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1570 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1571 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1572 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1573 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1574 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1575 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1576 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1577 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1578 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 1579 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1580 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1581 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1582 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1583 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) 1584 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 1585 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1586 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 1587 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1588 // CHECK3: omp.arraycpy.body: 1589 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1590 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1591 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1592 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 1593 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1594 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1595 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1596 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 1597 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1598 // CHECK3: omp.arraycpy.done4: 1599 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 1600 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1601 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) 1602 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 1603 // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 1604 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1605 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 1606 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1607 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1608 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 1609 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1610 // CHECK3: cond.true: 1611 // CHECK3-NEXT: br label [[COND_END:%.*]] 1612 // CHECK3: cond.false: 1613 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1614 // CHECK3-NEXT: br label [[COND_END]] 1615 // CHECK3: cond.end: 1616 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 1617 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1618 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1619 // CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 1620 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1621 // CHECK3: omp.inner.for.cond: 1622 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 1623 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] 1624 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 1625 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1626 // CHECK3: omp.inner.for.cond.cleanup: 1627 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1628 // CHECK3: omp.inner.for.body: 1629 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 1630 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 1631 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1632 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] 1633 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] 1634 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] 1635 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP14]] 1636 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] 1637 // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP12]] 1638 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] 1639 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP16]] 1640 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]] 1641 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1642 // CHECK3: omp.body.continue: 1643 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1644 // CHECK3: omp.inner.for.inc: 1645 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 1646 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP17]], 1 1647 // CHECK3-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 1648 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 1649 // CHECK3: omp.inner.for.end: 1650 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1651 // CHECK3: omp.loop.exit: 1652 // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1653 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 1654 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) 1655 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1656 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 1657 // CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1658 // CHECK3: .omp.final.then: 1659 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 1660 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1661 // CHECK3: .omp.final.done: 1662 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1663 // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 1664 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 1665 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1666 // CHECK3: arraydestroy.body: 1667 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1668 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1669 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1670 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 1671 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 1672 // CHECK3: arraydestroy.done12: 1673 // CHECK3-NEXT: ret void 1674 // 1675 // 1676 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1677 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1678 // CHECK3-NEXT: entry: 1679 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1680 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1681 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1682 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1683 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1684 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1685 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1686 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1687 // CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 1688 // CHECK3-NEXT: ret void 1689 // 1690 // 1691 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1692 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1693 // CHECK3-NEXT: entry: 1694 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1695 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1696 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1697 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1698 // CHECK3-NEXT: ret void 1699 // 1700 // 1701 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1702 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1703 // CHECK3-NEXT: entry: 1704 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1705 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1706 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1707 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1708 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1709 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1710 // CHECK3-NEXT: ret void 1711 // 1712 // 1713 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1714 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1715 // CHECK3-NEXT: entry: 1716 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1717 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1718 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1719 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1720 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1721 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1722 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1723 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1724 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1725 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1726 // CHECK3-NEXT: ret void 1727 // 1728 // 1729 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1730 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1731 // CHECK3-NEXT: entry: 1732 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1733 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1734 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1735 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1736 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1737 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1738 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1739 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1740 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1741 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 1742 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 1743 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 1744 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1745 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1746 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1747 // CHECK3-NEXT: ret void 1748 // 1749 // 1750 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1751 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1752 // CHECK3-NEXT: entry: 1753 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1754 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1755 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1756 // CHECK3-NEXT: ret void 1757 // 1758 // 1759 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 1760 // CHECK3-SAME: () #[[ATTR0]] { 1761 // CHECK3-NEXT: entry: 1762 // CHECK3-NEXT: call void @__cxx_global_var_init() 1763 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1764 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1765 // CHECK3-NEXT: ret void 1766 // 1767 // 1768 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 1769 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 1770 // CHECK5-NEXT: entry: 1771 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 1772 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 1773 // CHECK5-NEXT: ret void 1774 // 1775 // 1776 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1777 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 1778 // CHECK5-NEXT: entry: 1779 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1780 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1781 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1782 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1783 // CHECK5-NEXT: ret void 1784 // 1785 // 1786 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1787 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1788 // CHECK5-NEXT: entry: 1789 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1790 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1791 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1792 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1793 // CHECK5-NEXT: ret void 1794 // 1795 // 1796 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1797 // CHECK5-SAME: () #[[ATTR0]] { 1798 // CHECK5-NEXT: entry: 1799 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 1800 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 1801 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 1802 // CHECK5-NEXT: ret void 1803 // 1804 // 1805 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1806 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1807 // CHECK5-NEXT: entry: 1808 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1809 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1810 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1811 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1812 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1813 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1814 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1815 // CHECK5-NEXT: ret void 1816 // 1817 // 1818 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1819 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1820 // CHECK5-NEXT: entry: 1821 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1822 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1823 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1824 // CHECK5: arraydestroy.body: 1825 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1826 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1827 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1828 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1829 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1830 // CHECK5: arraydestroy.done1: 1831 // CHECK5-NEXT: ret void 1832 // 1833 // 1834 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1835 // CHECK5-SAME: () #[[ATTR0]] { 1836 // CHECK5-NEXT: entry: 1837 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1838 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1839 // CHECK5-NEXT: ret void 1840 // 1841 // 1842 // CHECK5-LABEL: define {{[^@]+}}@main 1843 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 1844 // CHECK5-NEXT: entry: 1845 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1846 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1847 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1848 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1849 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1850 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1851 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 1852 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1853 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1854 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1855 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 1856 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1857 // CHECK5: omp.inner.for.cond: 1858 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 1859 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 1860 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1861 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1862 // CHECK5: omp.inner.for.body: 1863 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1864 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1865 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1866 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1867 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP2]] 1868 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1869 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 1870 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i64 0, i64 [[IDXPROM]] 1871 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] 1872 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1873 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 1874 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i64 0, i64 [[IDXPROM1]] 1875 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 @var, i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] 1876 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1877 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] 1878 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] 1879 // CHECK5-NEXT: store i32 [[ADD3]], ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] 1880 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1881 // CHECK5: omp.body.continue: 1882 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1883 // CHECK5: omp.inner.for.inc: 1884 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1885 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 1886 // CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1887 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1888 // CHECK5: omp.inner.for.end: 1889 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 1890 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 1891 // CHECK5-NEXT: ret i32 [[CALL]] 1892 // 1893 // 1894 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1895 // CHECK5-SAME: () #[[ATTR1]] comdat { 1896 // CHECK5-NEXT: entry: 1897 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1898 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1899 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1900 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1901 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1902 // CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 8 1903 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1904 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1905 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1906 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1907 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1908 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1909 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1910 // CHECK5-NEXT: store i32 0, ptr [[T_VAR]], align 4 1911 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 1912 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 1913 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 1914 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 1915 // CHECK5-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 1916 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 1917 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 1918 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8 1919 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR]], align 8 1920 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1921 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1922 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1923 // CHECK5-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 1924 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1925 // CHECK5: omp.inner.for.cond: 1926 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 1927 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 1928 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 1929 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1930 // CHECK5: omp.inner.for.body: 1931 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1932 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 1933 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1934 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1935 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP6]] 1936 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1937 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i64 1938 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 1939 // CHECK5-NEXT: store i32 [[TMP7]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] 1940 // CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP]], align 8, !llvm.access.group [[ACC_GRP6]] 1941 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1942 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 1943 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] 1944 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[TMP9]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] 1945 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1946 // CHECK5: omp.body.continue: 1947 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1948 // CHECK5: omp.inner.for.inc: 1949 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1950 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 1951 // CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1952 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1953 // CHECK5: omp.inner.for.end: 1954 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 1955 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 1956 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1957 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 1958 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1959 // CHECK5: arraydestroy.body: 1960 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1961 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1962 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1963 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1964 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 1965 // CHECK5: arraydestroy.done5: 1966 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1967 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 4 1968 // CHECK5-NEXT: ret i32 [[TMP13]] 1969 // 1970 // 1971 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1972 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1973 // CHECK5-NEXT: entry: 1974 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1975 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1976 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1977 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1978 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1979 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1980 // CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4 1981 // CHECK5-NEXT: ret void 1982 // 1983 // 1984 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1985 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1986 // CHECK5-NEXT: entry: 1987 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1988 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1989 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1990 // CHECK5-NEXT: ret void 1991 // 1992 // 1993 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1994 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1995 // CHECK5-NEXT: entry: 1996 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1997 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1998 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1999 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2000 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2001 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2002 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2003 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2004 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2005 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2006 // CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4 2007 // CHECK5-NEXT: ret void 2008 // 2009 // 2010 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2011 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2012 // CHECK5-NEXT: entry: 2013 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2014 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2015 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2016 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2017 // CHECK5-NEXT: ret void 2018 // 2019 // 2020 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2021 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2022 // CHECK5-NEXT: entry: 2023 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2024 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2025 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2026 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2027 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2028 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2029 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 2030 // CHECK5-NEXT: ret void 2031 // 2032 // 2033 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2034 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2035 // CHECK5-NEXT: entry: 2036 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2037 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2038 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2039 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2040 // CHECK5-NEXT: ret void 2041 // 2042 // 2043 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2044 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2045 // CHECK5-NEXT: entry: 2046 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2047 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2048 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2049 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2050 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2051 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 2052 // CHECK5-NEXT: ret void 2053 // 2054 // 2055 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2056 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2057 // CHECK5-NEXT: entry: 2058 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2059 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2060 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2061 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2062 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2063 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2064 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2065 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2066 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2067 // CHECK5-NEXT: store i32 [[ADD]], ptr [[F]], align 4 2068 // CHECK5-NEXT: ret void 2069 // 2070 // 2071 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2072 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2073 // CHECK5-NEXT: entry: 2074 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2075 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2076 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2077 // CHECK5-NEXT: ret void 2078 // 2079 // 2080 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 2081 // CHECK5-SAME: () #[[ATTR0]] { 2082 // CHECK5-NEXT: entry: 2083 // CHECK5-NEXT: call void @__cxx_global_var_init() 2084 // CHECK5-NEXT: call void @__cxx_global_var_init.1() 2085 // CHECK5-NEXT: call void @__cxx_global_var_init.2() 2086 // CHECK5-NEXT: ret void 2087 // 2088 // 2089 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init 2090 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 2091 // CHECK7-NEXT: entry: 2092 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 2093 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 2094 // CHECK7-NEXT: ret void 2095 // 2096 // 2097 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2098 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2099 // CHECK7-NEXT: entry: 2100 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2101 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2102 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2103 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2104 // CHECK7-NEXT: ret void 2105 // 2106 // 2107 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2108 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2109 // CHECK7-NEXT: entry: 2110 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2111 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2112 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2113 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2114 // CHECK7-NEXT: ret void 2115 // 2116 // 2117 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2118 // CHECK7-SAME: () #[[ATTR0]] { 2119 // CHECK7-NEXT: entry: 2120 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 2121 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 2122 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 2123 // CHECK7-NEXT: ret void 2124 // 2125 // 2126 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2127 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2128 // CHECK7-NEXT: entry: 2129 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2130 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2131 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2132 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2133 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2134 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2135 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2136 // CHECK7-NEXT: ret void 2137 // 2138 // 2139 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2140 // CHECK7-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2141 // CHECK7-NEXT: entry: 2142 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 2143 // CHECK7-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 2144 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2145 // CHECK7: arraydestroy.body: 2146 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2147 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2148 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2149 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 2150 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2151 // CHECK7: arraydestroy.done1: 2152 // CHECK7-NEXT: ret void 2153 // 2154 // 2155 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2156 // CHECK7-SAME: () #[[ATTR0]] { 2157 // CHECK7-NEXT: entry: 2158 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2159 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 2160 // CHECK7-NEXT: ret void 2161 // 2162 // 2163 // CHECK7-LABEL: define {{[^@]+}}@main 2164 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] { 2165 // CHECK7-NEXT: entry: 2166 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2167 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 2168 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2169 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2170 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2171 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2172 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 2173 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2174 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2175 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2176 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 2177 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2178 // CHECK7: omp.inner.for.cond: 2179 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 2180 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 2181 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 2182 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2183 // CHECK7: omp.inner.for.body: 2184 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 2185 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 2186 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2187 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 2188 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP3]] 2189 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 2190 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i32 0, i32 [[TMP5]] 2191 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] 2192 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 2193 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i32 0, i32 [[TMP6]] 2194 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 @var, i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] 2195 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 2196 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]] 2197 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] 2198 // CHECK7-NEXT: store i32 [[ADD2]], ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]] 2199 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2200 // CHECK7: omp.body.continue: 2201 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2202 // CHECK7: omp.inner.for.inc: 2203 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 2204 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 2205 // CHECK7-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 2206 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 2207 // CHECK7: omp.inner.for.end: 2208 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 2209 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 2210 // CHECK7-NEXT: ret i32 [[CALL]] 2211 // 2212 // 2213 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2214 // CHECK7-SAME: () #[[ATTR1]] comdat { 2215 // CHECK7-NEXT: entry: 2216 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2217 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2218 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2219 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2220 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2221 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 4 2222 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4 2223 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2224 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2225 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2226 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2227 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2228 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 2229 // CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 4 2230 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 2231 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 2232 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 2233 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 2234 // CHECK7-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 2235 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 2236 // CHECK7-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 2237 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 4 2238 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR]], align 4 2239 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2240 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2241 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2242 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 2243 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2244 // CHECK7: omp.inner.for.cond: 2245 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 2246 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]] 2247 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 2248 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2249 // CHECK7: omp.inner.for.body: 2250 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 2251 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 2252 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2253 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 2254 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP7]] 2255 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 2256 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP8]] 2257 // CHECK7-NEXT: store i32 [[TMP7]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] 2258 // CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP]], align 4, !llvm.access.group [[ACC_GRP7]] 2259 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 2260 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP10]] 2261 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[TMP9]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] 2262 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2263 // CHECK7: omp.body.continue: 2264 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2265 // CHECK7: omp.inner.for.inc: 2266 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 2267 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 2268 // CHECK7-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 2269 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 2270 // CHECK7: omp.inner.for.end: 2271 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 2272 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 2273 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 2274 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 2275 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2276 // CHECK7: arraydestroy.body: 2277 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2278 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2279 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2280 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2281 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] 2282 // CHECK7: arraydestroy.done4: 2283 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 2284 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 4 2285 // CHECK7-NEXT: ret i32 [[TMP13]] 2286 // 2287 // 2288 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2289 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2290 // CHECK7-NEXT: entry: 2291 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2292 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2293 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2294 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2295 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2296 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2297 // CHECK7-NEXT: store float [[CONV]], ptr [[F]], align 4 2298 // CHECK7-NEXT: ret void 2299 // 2300 // 2301 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2302 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2303 // CHECK7-NEXT: entry: 2304 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2305 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2306 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2307 // CHECK7-NEXT: ret void 2308 // 2309 // 2310 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2311 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2312 // CHECK7-NEXT: entry: 2313 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2314 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2315 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2316 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2317 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2318 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2319 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2320 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2321 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2322 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2323 // CHECK7-NEXT: store float [[ADD]], ptr [[F]], align 4 2324 // CHECK7-NEXT: ret void 2325 // 2326 // 2327 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2328 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2329 // CHECK7-NEXT: entry: 2330 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2331 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2332 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2333 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2334 // CHECK7-NEXT: ret void 2335 // 2336 // 2337 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2338 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2339 // CHECK7-NEXT: entry: 2340 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2341 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2342 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2343 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2344 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2345 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2346 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 2347 // CHECK7-NEXT: ret void 2348 // 2349 // 2350 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2351 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2352 // CHECK7-NEXT: entry: 2353 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2354 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2355 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2356 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2357 // CHECK7-NEXT: ret void 2358 // 2359 // 2360 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2361 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2362 // CHECK7-NEXT: entry: 2363 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2364 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2365 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2366 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2367 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2368 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 2369 // CHECK7-NEXT: ret void 2370 // 2371 // 2372 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2373 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2374 // CHECK7-NEXT: entry: 2375 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2376 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2377 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2378 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2379 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2380 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2381 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2382 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2383 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2384 // CHECK7-NEXT: store i32 [[ADD]], ptr [[F]], align 4 2385 // CHECK7-NEXT: ret void 2386 // 2387 // 2388 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2389 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2390 // CHECK7-NEXT: entry: 2391 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2392 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2393 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2394 // CHECK7-NEXT: ret void 2395 // 2396 // 2397 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 2398 // CHECK7-SAME: () #[[ATTR0]] { 2399 // CHECK7-NEXT: entry: 2400 // CHECK7-NEXT: call void @__cxx_global_var_init() 2401 // CHECK7-NEXT: call void @__cxx_global_var_init.1() 2402 // CHECK7-NEXT: call void @__cxx_global_var_init.2() 2403 // CHECK7-NEXT: ret void 2404 // 2405 // 2406 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 2407 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 2408 // CHECK9-NEXT: entry: 2409 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 2410 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 2411 // CHECK9-NEXT: ret void 2412 // 2413 // 2414 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2415 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 2416 // CHECK9-NEXT: entry: 2417 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2418 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2419 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2420 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2421 // CHECK9-NEXT: ret void 2422 // 2423 // 2424 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2425 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2426 // CHECK9-NEXT: entry: 2427 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2428 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2429 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2430 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2431 // CHECK9-NEXT: ret void 2432 // 2433 // 2434 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2435 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2436 // CHECK9-NEXT: entry: 2437 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2438 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2439 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2440 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2441 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2442 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2443 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 2444 // CHECK9-NEXT: ret void 2445 // 2446 // 2447 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2448 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2449 // CHECK9-NEXT: entry: 2450 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2451 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2452 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2453 // CHECK9-NEXT: ret void 2454 // 2455 // 2456 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2457 // CHECK9-SAME: () #[[ATTR0]] { 2458 // CHECK9-NEXT: entry: 2459 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 2460 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 2461 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 2462 // CHECK9-NEXT: ret void 2463 // 2464 // 2465 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2466 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2467 // CHECK9-NEXT: entry: 2468 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2469 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2470 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2471 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2472 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2473 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2474 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2475 // CHECK9-NEXT: ret void 2476 // 2477 // 2478 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2479 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2480 // CHECK9-NEXT: entry: 2481 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2482 // CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2483 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2484 // CHECK9: arraydestroy.body: 2485 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2486 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2487 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2488 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 2489 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2490 // CHECK9: arraydestroy.done1: 2491 // CHECK9-NEXT: ret void 2492 // 2493 // 2494 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2495 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2496 // CHECK9-NEXT: entry: 2497 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2498 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2499 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2500 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2501 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2502 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2503 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2504 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2505 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2506 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2507 // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 2508 // CHECK9-NEXT: ret void 2509 // 2510 // 2511 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2512 // CHECK9-SAME: () #[[ATTR0]] { 2513 // CHECK9-NEXT: entry: 2514 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2515 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 2516 // CHECK9-NEXT: ret void 2517 // 2518 // 2519 // CHECK9-LABEL: define {{[^@]+}}@main 2520 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 2521 // CHECK9-NEXT: entry: 2522 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2523 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2524 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 2525 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2526 // CHECK9-NEXT: ret i32 0 2527 // 2528 // 2529 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 2530 // CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 2531 // CHECK9-NEXT: entry: 2532 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 2533 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 2534 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2535 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 2536 // CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 2537 // CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 2538 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 2539 // CHECK9-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 2540 // CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 2541 // CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 2542 // CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 2543 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 4 2544 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4 2545 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8 2546 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 2547 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 4 2548 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[G1_CASTED]], align 4 2549 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 8 2550 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 2551 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 2552 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 2553 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined, i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) 2554 // CHECK9-NEXT: ret void 2555 // 2556 // 2557 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined 2558 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 2559 // CHECK9-NEXT: entry: 2560 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2561 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2562 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 2563 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 2564 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2565 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 2566 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2567 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2568 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2569 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2570 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2571 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2572 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 2573 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 2574 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2575 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2576 // CHECK9-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 2577 // CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 2578 // CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 2579 // CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 2580 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2581 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2582 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2583 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2584 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2585 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2586 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2587 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2588 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 2589 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2590 // CHECK9: cond.true: 2591 // CHECK9-NEXT: br label [[COND_END:%.*]] 2592 // CHECK9: cond.false: 2593 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2594 // CHECK9-NEXT: br label [[COND_END]] 2595 // CHECK9: cond.end: 2596 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2597 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2598 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2599 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2600 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2601 // CHECK9: omp.inner.for.cond: 2602 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]] 2603 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]] 2604 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2605 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2606 // CHECK9: omp.inner.for.body: 2607 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 2608 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2609 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2610 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] 2611 // CHECK9-NEXT: store i32 1, ptr [[G_ADDR]], align 4, !llvm.access.group [[ACC_GRP4]] 2612 // CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8, !llvm.access.group [[ACC_GRP4]] 2613 // CHECK9-NEXT: store volatile i32 1, ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP4]] 2614 // CHECK9-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP4]] 2615 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 2616 // CHECK9-NEXT: store ptr [[G_ADDR]], ptr [[TMP9]], align 8, !llvm.access.group [[ACC_GRP4]] 2617 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 2618 // CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP]], align 8, !llvm.access.group [[ACC_GRP4]] 2619 // CHECK9-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP4]] 2620 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 2621 // CHECK9-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP4]] 2622 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group [[ACC_GRP4]] 2623 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2624 // CHECK9: omp.body.continue: 2625 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2626 // CHECK9: omp.inner.for.inc: 2627 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 2628 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], 1 2629 // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 2630 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 2631 // CHECK9: omp.inner.for.end: 2632 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2633 // CHECK9: omp.loop.exit: 2634 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2635 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2636 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 2637 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2638 // CHECK9: .omp.final.then: 2639 // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 2640 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 2641 // CHECK9: .omp.final.done: 2642 // CHECK9-NEXT: ret void 2643 // 2644 // 2645 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 2646 // CHECK9-SAME: () #[[ATTR0]] { 2647 // CHECK9-NEXT: entry: 2648 // CHECK9-NEXT: call void @__cxx_global_var_init() 2649 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 2650 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 2651 // CHECK9-NEXT: ret void 2652 // 2653 // 2654 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init 2655 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 2656 // CHECK11-NEXT: entry: 2657 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 2658 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 2659 // CHECK11-NEXT: ret void 2660 // 2661 // 2662 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2663 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 2664 // CHECK11-NEXT: entry: 2665 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2666 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2667 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2668 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2669 // CHECK11-NEXT: ret void 2670 // 2671 // 2672 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2673 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2674 // CHECK11-NEXT: entry: 2675 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2676 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2677 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2678 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2679 // CHECK11-NEXT: ret void 2680 // 2681 // 2682 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2683 // CHECK11-SAME: () #[[ATTR0]] { 2684 // CHECK11-NEXT: entry: 2685 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 2686 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 2687 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 2688 // CHECK11-NEXT: ret void 2689 // 2690 // 2691 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2692 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2693 // CHECK11-NEXT: entry: 2694 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2695 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2696 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2697 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2698 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2699 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2700 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2701 // CHECK11-NEXT: ret void 2702 // 2703 // 2704 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2705 // CHECK11-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2706 // CHECK11-NEXT: entry: 2707 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2708 // CHECK11-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2709 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2710 // CHECK11: arraydestroy.body: 2711 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2712 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2713 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2714 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 2715 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2716 // CHECK11: arraydestroy.done1: 2717 // CHECK11-NEXT: ret void 2718 // 2719 // 2720 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2721 // CHECK11-SAME: () #[[ATTR0]] { 2722 // CHECK11-NEXT: entry: 2723 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2724 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 2725 // CHECK11-NEXT: ret void 2726 // 2727 // 2728 // CHECK11-LABEL: define {{[^@]+}}@main 2729 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 2730 // CHECK11-NEXT: entry: 2731 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2732 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2733 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 2734 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2735 // CHECK11-NEXT: ret i32 0 2736 // 2737 // 2738 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2739 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2740 // CHECK11-NEXT: entry: 2741 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2742 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2743 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2744 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2745 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2746 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2747 // CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4 2748 // CHECK11-NEXT: ret void 2749 // 2750 // 2751 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2752 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2753 // CHECK11-NEXT: entry: 2754 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2755 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2756 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2757 // CHECK11-NEXT: ret void 2758 // 2759 // 2760 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2761 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2762 // CHECK11-NEXT: entry: 2763 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2764 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2765 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2766 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2767 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2768 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2769 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2770 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2771 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2772 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2773 // CHECK11-NEXT: store float [[ADD]], ptr [[F]], align 4 2774 // CHECK11-NEXT: ret void 2775 // 2776 // 2777 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 2778 // CHECK11-SAME: () #[[ATTR0]] { 2779 // CHECK11-NEXT: entry: 2780 // CHECK11-NEXT: call void @__cxx_global_var_init() 2781 // CHECK11-NEXT: call void @__cxx_global_var_init.1() 2782 // CHECK11-NEXT: call void @__cxx_global_var_init.2() 2783 // CHECK11-NEXT: ret void 2784 // 2785