1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 12 13 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 16 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 template <typename T> 29 T tmain() { 30 T t_var = T(); 31 T vec[] = {1, 2}; 32 #pragma omp target teams distribute parallel for simd reduction(+: t_var) 33 for (int i = 0; i < 2; ++i) { 34 t_var += (T) i; 35 } 36 return T(); 37 } 38 39 int main() { 40 static int sivar; 41 #ifdef LAMBDA 42 43 [&]() { 44 #pragma omp target teams distribute parallel for simd reduction(+: sivar) 45 for (int i = 0; i < 2; ++i) { 46 47 // Skip global and bound tid vars 48 49 50 51 // Skip global and bound tid vars, and prev lb and ub vars 52 // skip loop vars 53 54 55 sivar += i; 56 57 [&]() { 58 59 sivar += 4; 60 61 }(); 62 } 63 }(); 64 return 0; 65 #else 66 #pragma omp target teams distribute parallel for simd reduction(+: sivar) 67 for (int i = 0; i < 2; ++i) { 68 sivar += i; 69 } 70 return tmain<int>(); 71 #endif 72 } 73 74 75 76 77 // Skip global and bound tid vars 78 79 80 // Skip global and bound tid vars, and prev lb and ub 81 // skip loop vars 82 83 84 85 86 // Skip global and bound tid vars 87 88 89 // Skip global and bound tid vars, and prev lb and ub vars 90 // skip loop vars 91 92 #endif 93 // CHECK1-LABEL: define {{[^@]+}}@main 94 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 95 // CHECK1-NEXT: entry: 96 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 97 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 98 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 99 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 100 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 101 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 102 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 103 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 104 // CHECK1-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP0]], align 8 105 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 106 // CHECK1-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP1]], align 8 107 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 108 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 109 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 110 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 111 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 112 // CHECK1-NEXT: store i32 3, ptr [[TMP5]], align 4 113 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 114 // CHECK1-NEXT: store i32 1, ptr [[TMP6]], align 4 115 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 116 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8 117 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 118 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8 119 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 120 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 8 121 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 122 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 8 123 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 124 // CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8 125 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 126 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 127 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 128 // CHECK1-NEXT: store i64 2, ptr [[TMP13]], align 8 129 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 130 // CHECK1-NEXT: store i64 0, ptr [[TMP14]], align 8 131 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 132 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 133 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 134 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 135 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 136 // CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4 137 // CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.region_id, ptr [[KERNEL_ARGS]]) 138 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 139 // CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 140 // CHECK1: omp_offload.failed: 141 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66(ptr @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]] 142 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 143 // CHECK1: omp_offload.cont: 144 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 145 // CHECK1-NEXT: ret i32 [[CALL]] 146 // 147 // 148 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 149 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 150 // CHECK1-NEXT: entry: 151 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 152 // CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 153 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 154 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined, ptr [[TMP0]]) 155 // CHECK1-NEXT: ret void 156 // 157 // 158 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined 159 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { 160 // CHECK1-NEXT: entry: 161 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 162 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 163 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 164 // CHECK1-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 165 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 166 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 167 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 168 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 169 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 170 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 171 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 172 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 173 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 174 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 175 // CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 176 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 177 // CHECK1-NEXT: store i32 0, ptr [[SIVAR1]], align 4 178 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 179 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 180 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 181 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 182 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 183 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 184 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 185 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 186 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 187 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 188 // CHECK1: cond.true: 189 // CHECK1-NEXT: br label [[COND_END:%.*]] 190 // CHECK1: cond.false: 191 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 192 // CHECK1-NEXT: br label [[COND_END]] 193 // CHECK1: cond.end: 194 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 195 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 196 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 197 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 198 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 199 // CHECK1: omp.inner.for.cond: 200 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] 201 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 202 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 203 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 204 // CHECK1: omp.inner.for.body: 205 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP5]] 206 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 207 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 208 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 209 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[SIVAR1]]), !llvm.access.group [[ACC_GRP5]] 210 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 211 // CHECK1: omp.inner.for.inc: 212 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 213 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP5]] 214 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 215 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 216 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 217 // CHECK1: omp.inner.for.end: 218 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 219 // CHECK1: omp.loop.exit: 220 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 221 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 222 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 223 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 224 // CHECK1: .omp.final.then: 225 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 226 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 227 // CHECK1: .omp.final.done: 228 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 229 // CHECK1-NEXT: store ptr [[SIVAR1]], ptr [[TMP16]], align 8 230 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 231 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 232 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 233 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 234 // CHECK1-NEXT: ] 235 // CHECK1: .omp.reduction.case1: 236 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 237 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR1]], align 4 238 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 239 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 240 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 241 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 242 // CHECK1: .omp.reduction.case2: 243 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR1]], align 4 244 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 245 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 246 // CHECK1: .omp.reduction.default: 247 // CHECK1-NEXT: ret void 248 // 249 // 250 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp_outlined 251 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { 252 // CHECK1-NEXT: entry: 253 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 254 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 255 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 256 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 257 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 258 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 259 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 260 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 261 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 262 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 263 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 264 // CHECK1-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 265 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 266 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 267 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 268 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 269 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 270 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 271 // CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 272 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 273 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 274 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 275 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 276 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 277 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 278 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 279 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 280 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 281 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 282 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 283 // CHECK1-NEXT: store i32 0, ptr [[SIVAR2]], align 4 284 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 285 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 286 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 287 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 288 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 289 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 290 // CHECK1: cond.true: 291 // CHECK1-NEXT: br label [[COND_END:%.*]] 292 // CHECK1: cond.false: 293 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 294 // CHECK1-NEXT: br label [[COND_END]] 295 // CHECK1: cond.end: 296 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 297 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 298 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 299 // CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 300 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 301 // CHECK1: omp.inner.for.cond: 302 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] 303 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 304 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 305 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 306 // CHECK1: omp.inner.for.body: 307 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 308 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 309 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 310 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 311 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 312 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR2]], align 4, !llvm.access.group [[ACC_GRP9]] 313 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 314 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[SIVAR2]], align 4, !llvm.access.group [[ACC_GRP9]] 315 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 316 // CHECK1: omp.body.continue: 317 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 318 // CHECK1: omp.inner.for.inc: 319 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 320 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 321 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 322 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 323 // CHECK1: omp.inner.for.end: 324 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 325 // CHECK1: omp.loop.exit: 326 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) 327 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 328 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 329 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 330 // CHECK1: .omp.final.then: 331 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 332 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 333 // CHECK1: .omp.final.done: 334 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 335 // CHECK1-NEXT: store ptr [[SIVAR2]], ptr [[TMP16]], align 8 336 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 337 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 338 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 339 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 340 // CHECK1-NEXT: ] 341 // CHECK1: .omp.reduction.case1: 342 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 343 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR2]], align 4 344 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 345 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[TMP0]], align 4 346 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) 347 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 348 // CHECK1: .omp.reduction.case2: 349 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR2]], align 4 350 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 351 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 352 // CHECK1: .omp.reduction.default: 353 // CHECK1-NEXT: ret void 354 // 355 // 356 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp_outlined.omp.reduction.reduction_func 357 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { 358 // CHECK1-NEXT: entry: 359 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 360 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 361 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 362 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 363 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 364 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 365 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 366 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 367 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 368 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 369 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 370 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 371 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 372 // CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 373 // CHECK1-NEXT: ret void 374 // 375 // 376 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp.reduction.reduction_func 377 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { 378 // CHECK1-NEXT: entry: 379 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 380 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 381 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 382 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 383 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 384 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 385 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 386 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 387 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 388 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 389 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 390 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 391 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 392 // CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 393 // CHECK1-NEXT: ret void 394 // 395 // 396 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 397 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] comdat { 398 // CHECK1-NEXT: entry: 399 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 400 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 401 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 402 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 403 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 404 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 405 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 406 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 407 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 408 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 409 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[TMP0]], align 8 410 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 411 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[TMP1]], align 8 412 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 413 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 414 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 415 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 416 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 417 // CHECK1-NEXT: store i32 3, ptr [[TMP5]], align 4 418 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 419 // CHECK1-NEXT: store i32 1, ptr [[TMP6]], align 4 420 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 421 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8 422 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 423 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8 424 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 425 // CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP9]], align 8 426 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 427 // CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP10]], align 8 428 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 429 // CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8 430 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 431 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 432 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 433 // CHECK1-NEXT: store i64 2, ptr [[TMP13]], align 8 434 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 435 // CHECK1-NEXT: store i64 0, ptr [[TMP14]], align 8 436 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 437 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 438 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 439 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 440 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 441 // CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4 442 // CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) 443 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 444 // CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 445 // CHECK1: omp_offload.failed: 446 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(ptr [[T_VAR]]) #[[ATTR2]] 447 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 448 // CHECK1: omp_offload.cont: 449 // CHECK1-NEXT: ret i32 0 450 // 451 // 452 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 453 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 454 // CHECK1-NEXT: entry: 455 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 456 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 457 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 458 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[TMP0]]) 459 // CHECK1-NEXT: ret void 460 // 461 // 462 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined 463 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 464 // CHECK1-NEXT: entry: 465 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 466 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 467 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 468 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 469 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 470 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 471 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 472 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 473 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 474 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 475 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 476 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 477 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 478 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 479 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 480 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 481 // CHECK1-NEXT: store i32 0, ptr [[T_VAR1]], align 4 482 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 483 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 484 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 485 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 486 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 487 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 488 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 489 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 490 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 491 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 492 // CHECK1: cond.true: 493 // CHECK1-NEXT: br label [[COND_END:%.*]] 494 // CHECK1: cond.false: 495 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 496 // CHECK1-NEXT: br label [[COND_END]] 497 // CHECK1: cond.end: 498 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 499 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 500 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 501 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 502 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 503 // CHECK1: omp.inner.for.cond: 504 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]] 505 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]] 506 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 507 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 508 // CHECK1: omp.inner.for.body: 509 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP14]] 510 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 511 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]] 512 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 513 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[T_VAR1]]), !llvm.access.group [[ACC_GRP14]] 514 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 515 // CHECK1: omp.inner.for.inc: 516 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 517 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP14]] 518 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 519 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 520 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 521 // CHECK1: omp.inner.for.end: 522 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 523 // CHECK1: omp.loop.exit: 524 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 525 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 526 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 527 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 528 // CHECK1: .omp.final.then: 529 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 530 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 531 // CHECK1: .omp.final.done: 532 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 533 // CHECK1-NEXT: store ptr [[T_VAR1]], ptr [[TMP16]], align 8 534 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 535 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 536 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 537 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 538 // CHECK1-NEXT: ] 539 // CHECK1: .omp.reduction.case1: 540 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 541 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR1]], align 4 542 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 543 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 544 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 545 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 546 // CHECK1: .omp.reduction.case2: 547 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR1]], align 4 548 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 549 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 550 // CHECK1: .omp.reduction.default: 551 // CHECK1-NEXT: ret void 552 // 553 // 554 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined 555 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 556 // CHECK1-NEXT: entry: 557 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 558 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 559 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 560 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 561 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 562 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 563 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 564 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 565 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 566 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 567 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 568 // CHECK1-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 569 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 570 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 571 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 572 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 573 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 574 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 575 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 576 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 577 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 578 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 579 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 580 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 581 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 582 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 583 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 584 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 585 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 586 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 587 // CHECK1-NEXT: store i32 0, ptr [[T_VAR2]], align 4 588 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 589 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 590 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 591 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 592 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 593 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 594 // CHECK1: cond.true: 595 // CHECK1-NEXT: br label [[COND_END:%.*]] 596 // CHECK1: cond.false: 597 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 598 // CHECK1-NEXT: br label [[COND_END]] 599 // CHECK1: cond.end: 600 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 601 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 602 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 603 // CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 604 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 605 // CHECK1: omp.inner.for.cond: 606 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]] 607 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP17]] 608 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 609 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 610 // CHECK1: omp.inner.for.body: 611 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 612 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 613 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 614 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 615 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 616 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP17]] 617 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 618 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP17]] 619 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 620 // CHECK1: omp.body.continue: 621 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 622 // CHECK1: omp.inner.for.inc: 623 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 624 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 625 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 626 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 627 // CHECK1: omp.inner.for.end: 628 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 629 // CHECK1: omp.loop.exit: 630 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) 631 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 632 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 633 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 634 // CHECK1: .omp.final.then: 635 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 636 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 637 // CHECK1: .omp.final.done: 638 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 639 // CHECK1-NEXT: store ptr [[T_VAR2]], ptr [[TMP16]], align 8 640 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 641 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 642 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 643 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 644 // CHECK1-NEXT: ] 645 // CHECK1: .omp.reduction.case1: 646 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 647 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR2]], align 4 648 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 649 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[TMP0]], align 4 650 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) 651 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 652 // CHECK1: .omp.reduction.case2: 653 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR2]], align 4 654 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 655 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 656 // CHECK1: .omp.reduction.default: 657 // CHECK1-NEXT: ret void 658 // 659 // 660 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func 661 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { 662 // CHECK1-NEXT: entry: 663 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 664 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 665 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 666 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 667 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 668 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 669 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 670 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 671 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 672 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 673 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 674 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 675 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 676 // CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 677 // CHECK1-NEXT: ret void 678 // 679 // 680 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func 681 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { 682 // CHECK1-NEXT: entry: 683 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 684 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 685 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 686 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 687 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 688 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 689 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 690 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 691 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 692 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 693 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 694 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 695 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 696 // CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 697 // CHECK1-NEXT: ret void 698 // 699 // 700 // CHECK3-LABEL: define {{[^@]+}}@main 701 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 702 // CHECK3-NEXT: entry: 703 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 704 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 705 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 706 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 707 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 708 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 709 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 710 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 711 // CHECK3-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP0]], align 4 712 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 713 // CHECK3-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP1]], align 4 714 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 715 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 716 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 717 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 718 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 719 // CHECK3-NEXT: store i32 3, ptr [[TMP5]], align 4 720 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 721 // CHECK3-NEXT: store i32 1, ptr [[TMP6]], align 4 722 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 723 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4 724 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 725 // CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4 726 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 727 // CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 4 728 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 729 // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 4 730 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 731 // CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4 732 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 733 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 734 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 735 // CHECK3-NEXT: store i64 2, ptr [[TMP13]], align 8 736 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 737 // CHECK3-NEXT: store i64 0, ptr [[TMP14]], align 8 738 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 739 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 740 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 741 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 742 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 743 // CHECK3-NEXT: store i32 0, ptr [[TMP17]], align 4 744 // CHECK3-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.region_id, ptr [[KERNEL_ARGS]]) 745 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 746 // CHECK3-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 747 // CHECK3: omp_offload.failed: 748 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66(ptr @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]] 749 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 750 // CHECK3: omp_offload.cont: 751 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 752 // CHECK3-NEXT: ret i32 [[CALL]] 753 // 754 // 755 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 756 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 757 // CHECK3-NEXT: entry: 758 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 4 759 // CHECK3-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 760 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4 761 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined, ptr [[TMP0]]) 762 // CHECK3-NEXT: ret void 763 // 764 // 765 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined 766 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { 767 // CHECK3-NEXT: entry: 768 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 769 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 770 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 4 771 // CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 772 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 773 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 774 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 775 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 776 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 777 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 778 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 779 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 780 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 781 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 782 // CHECK3-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 783 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4 784 // CHECK3-NEXT: store i32 0, ptr [[SIVAR1]], align 4 785 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 786 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 787 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 788 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 789 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 790 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 791 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 792 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 793 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 794 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 795 // CHECK3: cond.true: 796 // CHECK3-NEXT: br label [[COND_END:%.*]] 797 // CHECK3: cond.false: 798 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 799 // CHECK3-NEXT: br label [[COND_END]] 800 // CHECK3: cond.end: 801 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 802 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 803 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 804 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 805 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 806 // CHECK3: omp.inner.for.cond: 807 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 808 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 809 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 810 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 811 // CHECK3: omp.inner.for.body: 812 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP6]] 813 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 814 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp_outlined, i32 [[TMP8]], i32 [[TMP9]], ptr [[SIVAR1]]), !llvm.access.group [[ACC_GRP6]] 815 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 816 // CHECK3: omp.inner.for.inc: 817 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 818 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP6]] 819 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] 820 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 821 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 822 // CHECK3: omp.inner.for.end: 823 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 824 // CHECK3: omp.loop.exit: 825 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 826 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 827 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 828 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 829 // CHECK3: .omp.final.then: 830 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 831 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 832 // CHECK3: .omp.final.done: 833 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 834 // CHECK3-NEXT: store ptr [[SIVAR1]], ptr [[TMP14]], align 4 835 // CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 836 // CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 837 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 838 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 839 // CHECK3-NEXT: ] 840 // CHECK3: .omp.reduction.case1: 841 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 842 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR1]], align 4 843 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] 844 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 845 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 846 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 847 // CHECK3: .omp.reduction.case2: 848 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR1]], align 4 849 // CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 850 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 851 // CHECK3: .omp.reduction.default: 852 // CHECK3-NEXT: ret void 853 // 854 // 855 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp_outlined 856 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { 857 // CHECK3-NEXT: entry: 858 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 859 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 860 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 861 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 862 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 4 863 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 864 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 865 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 866 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 867 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 868 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 869 // CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 870 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 871 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 872 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 873 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 874 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 875 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 876 // CHECK3-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 877 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4 878 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 879 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 880 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 881 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 882 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4 883 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 884 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 885 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 886 // CHECK3-NEXT: store i32 0, ptr [[SIVAR1]], align 4 887 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 888 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 889 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 890 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 891 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 892 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 893 // CHECK3: cond.true: 894 // CHECK3-NEXT: br label [[COND_END:%.*]] 895 // CHECK3: cond.false: 896 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 897 // CHECK3-NEXT: br label [[COND_END]] 898 // CHECK3: cond.end: 899 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 900 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 901 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 902 // CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 903 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 904 // CHECK3: omp.inner.for.cond: 905 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 906 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 907 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 908 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 909 // CHECK3: omp.inner.for.body: 910 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 911 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 912 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 913 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 914 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 915 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP10]] 916 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 917 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP10]] 918 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 919 // CHECK3: omp.body.continue: 920 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 921 // CHECK3: omp.inner.for.inc: 922 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 923 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 924 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 925 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 926 // CHECK3: omp.inner.for.end: 927 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 928 // CHECK3: omp.loop.exit: 929 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) 930 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 931 // CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 932 // CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 933 // CHECK3: .omp.final.then: 934 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 935 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 936 // CHECK3: .omp.final.done: 937 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 938 // CHECK3-NEXT: store ptr [[SIVAR1]], ptr [[TMP16]], align 4 939 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 940 // CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 941 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 942 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 943 // CHECK3-NEXT: ] 944 // CHECK3: .omp.reduction.case1: 945 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 946 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR1]], align 4 947 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 948 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 949 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) 950 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 951 // CHECK3: .omp.reduction.case2: 952 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR1]], align 4 953 // CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 954 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 955 // CHECK3: .omp.reduction.default: 956 // CHECK3-NEXT: ret void 957 // 958 // 959 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp_outlined.omp.reduction.reduction_func 960 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { 961 // CHECK3-NEXT: entry: 962 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 963 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 964 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 965 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 966 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 4 967 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 968 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i32 0, i32 0 969 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 970 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i32 0, i32 0 971 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 972 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 973 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 974 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 975 // CHECK3-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 976 // CHECK3-NEXT: ret void 977 // 978 // 979 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp.reduction.reduction_func 980 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { 981 // CHECK3-NEXT: entry: 982 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 983 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 984 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 985 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 986 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 4 987 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 988 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i32 0, i32 0 989 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 990 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i32 0, i32 0 991 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 992 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 993 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 994 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 995 // CHECK3-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 996 // CHECK3-NEXT: ret void 997 // 998 // 999 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1000 // CHECK3-SAME: () #[[ATTR5:[0-9]+]] comdat { 1001 // CHECK3-NEXT: entry: 1002 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1003 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1004 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 1005 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 1006 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 1007 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1008 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1009 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 1010 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 1011 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1012 // CHECK3-NEXT: store ptr [[T_VAR]], ptr [[TMP0]], align 4 1013 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1014 // CHECK3-NEXT: store ptr [[T_VAR]], ptr [[TMP1]], align 4 1015 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1016 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 1017 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1018 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1019 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1020 // CHECK3-NEXT: store i32 3, ptr [[TMP5]], align 4 1021 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1022 // CHECK3-NEXT: store i32 1, ptr [[TMP6]], align 4 1023 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1024 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4 1025 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1026 // CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4 1027 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1028 // CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP9]], align 4 1029 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1030 // CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP10]], align 4 1031 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1032 // CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4 1033 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1034 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 1035 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1036 // CHECK3-NEXT: store i64 2, ptr [[TMP13]], align 8 1037 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1038 // CHECK3-NEXT: store i64 0, ptr [[TMP14]], align 8 1039 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1040 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 1041 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1042 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 1043 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1044 // CHECK3-NEXT: store i32 0, ptr [[TMP17]], align 4 1045 // CHECK3-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) 1046 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 1047 // CHECK3-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1048 // CHECK3: omp_offload.failed: 1049 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(ptr [[T_VAR]]) #[[ATTR2]] 1050 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1051 // CHECK3: omp_offload.cont: 1052 // CHECK3-NEXT: ret i32 0 1053 // 1054 // 1055 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 1056 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 1057 // CHECK3-NEXT: entry: 1058 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 1059 // CHECK3-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1060 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 1061 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[TMP0]]) 1062 // CHECK3-NEXT: ret void 1063 // 1064 // 1065 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined 1066 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 1067 // CHECK3-NEXT: entry: 1068 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1069 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1070 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 1071 // CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 1072 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1073 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1074 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1075 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1076 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1077 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1078 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1079 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 1080 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1081 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1082 // CHECK3-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1083 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 1084 // CHECK3-NEXT: store i32 0, ptr [[T_VAR1]], align 4 1085 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1086 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1087 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1088 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1089 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1090 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 1091 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1092 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1093 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 1094 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1095 // CHECK3: cond.true: 1096 // CHECK3-NEXT: br label [[COND_END:%.*]] 1097 // CHECK3: cond.false: 1098 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1099 // CHECK3-NEXT: br label [[COND_END]] 1100 // CHECK3: cond.end: 1101 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1102 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1103 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1104 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 1105 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1106 // CHECK3: omp.inner.for.cond: 1107 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] 1108 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 1109 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1110 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1111 // CHECK3: omp.inner.for.body: 1112 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]] 1113 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 1114 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined, i32 [[TMP8]], i32 [[TMP9]], ptr [[T_VAR1]]), !llvm.access.group [[ACC_GRP15]] 1115 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1116 // CHECK3: omp.inner.for.inc: 1117 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 1118 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]] 1119 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] 1120 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 1121 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 1122 // CHECK3: omp.inner.for.end: 1123 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1124 // CHECK3: omp.loop.exit: 1125 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 1126 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1127 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 1128 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1129 // CHECK3: .omp.final.then: 1130 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 1131 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1132 // CHECK3: .omp.final.done: 1133 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 1134 // CHECK3-NEXT: store ptr [[T_VAR1]], ptr [[TMP14]], align 4 1135 // CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 1136 // CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1137 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1138 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1139 // CHECK3-NEXT: ] 1140 // CHECK3: .omp.reduction.case1: 1141 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 1142 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR1]], align 4 1143 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] 1144 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 1145 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 1146 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1147 // CHECK3: .omp.reduction.case2: 1148 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR1]], align 4 1149 // CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 1150 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1151 // CHECK3: .omp.reduction.default: 1152 // CHECK3-NEXT: ret void 1153 // 1154 // 1155 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined 1156 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 1157 // CHECK3-NEXT: entry: 1158 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1159 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1160 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 1161 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 1162 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 1163 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1164 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1165 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1166 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1167 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1168 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1169 // CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 1170 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1171 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 1172 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1173 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1174 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1175 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1176 // CHECK3-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1177 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 1178 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1179 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1180 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1181 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1182 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4 1183 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 1184 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1185 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1186 // CHECK3-NEXT: store i32 0, ptr [[T_VAR1]], align 4 1187 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1188 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 1189 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1190 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1191 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 1192 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1193 // CHECK3: cond.true: 1194 // CHECK3-NEXT: br label [[COND_END:%.*]] 1195 // CHECK3: cond.false: 1196 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1197 // CHECK3-NEXT: br label [[COND_END]] 1198 // CHECK3: cond.end: 1199 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 1200 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1201 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1202 // CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 1203 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1204 // CHECK3: omp.inner.for.cond: 1205 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] 1206 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] 1207 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 1208 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1209 // CHECK3: omp.inner.for.body: 1210 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 1211 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 1212 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1213 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 1214 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 1215 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP18]] 1216 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 1217 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP18]] 1218 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1219 // CHECK3: omp.body.continue: 1220 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1221 // CHECK3: omp.inner.for.inc: 1222 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 1223 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 1224 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 1225 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 1226 // CHECK3: omp.inner.for.end: 1227 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1228 // CHECK3: omp.loop.exit: 1229 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) 1230 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1231 // CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 1232 // CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1233 // CHECK3: .omp.final.then: 1234 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 1235 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1236 // CHECK3: .omp.final.done: 1237 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 1238 // CHECK3-NEXT: store ptr [[T_VAR1]], ptr [[TMP16]], align 4 1239 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 1240 // CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1241 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1242 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1243 // CHECK3-NEXT: ] 1244 // CHECK3: .omp.reduction.case1: 1245 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 1246 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR1]], align 4 1247 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 1248 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 1249 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) 1250 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1251 // CHECK3: .omp.reduction.case2: 1252 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR1]], align 4 1253 // CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 1254 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1255 // CHECK3: .omp.reduction.default: 1256 // CHECK3-NEXT: ret void 1257 // 1258 // 1259 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func 1260 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { 1261 // CHECK3-NEXT: entry: 1262 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 1263 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 1264 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 1265 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 1266 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 4 1267 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 1268 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i32 0, i32 0 1269 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 1270 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i32 0, i32 0 1271 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 1272 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1273 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 1274 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 1275 // CHECK3-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 1276 // CHECK3-NEXT: ret void 1277 // 1278 // 1279 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func 1280 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { 1281 // CHECK3-NEXT: entry: 1282 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 1283 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 1284 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 1285 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 1286 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 4 1287 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 1288 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i32 0, i32 0 1289 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 1290 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i32 0, i32 0 1291 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 1292 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1293 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 1294 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 1295 // CHECK3-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 1296 // CHECK3-NEXT: ret void 1297 // 1298 // 1299 // CHECK5-LABEL: define {{[^@]+}}@main 1300 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 1301 // CHECK5-NEXT: entry: 1302 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1303 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1304 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 1305 // CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 1306 // CHECK5-NEXT: ret i32 0 1307 // 1308 // 1309 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44 1310 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 1311 // CHECK5-NEXT: entry: 1312 // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 1313 // CHECK5-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 1314 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 1315 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44.omp_outlined, ptr [[TMP0]]) 1316 // CHECK5-NEXT: ret void 1317 // 1318 // 1319 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44.omp_outlined 1320 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { 1321 // CHECK5-NEXT: entry: 1322 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1323 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1324 // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 1325 // CHECK5-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 1326 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1327 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1328 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1329 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1330 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1331 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1332 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1333 // CHECK5-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 1334 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1335 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1336 // CHECK5-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 1337 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 1338 // CHECK5-NEXT: store i32 0, ptr [[SIVAR1]], align 4 1339 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1340 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1341 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1342 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1343 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1344 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 1345 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1346 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1347 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 1348 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1349 // CHECK5: cond.true: 1350 // CHECK5-NEXT: br label [[COND_END:%.*]] 1351 // CHECK5: cond.false: 1352 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1353 // CHECK5-NEXT: br label [[COND_END]] 1354 // CHECK5: cond.end: 1355 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1356 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1357 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1358 // CHECK5-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 1359 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1360 // CHECK5: omp.inner.for.cond: 1361 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]] 1362 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]] 1363 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1364 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1365 // CHECK5: omp.inner.for.body: 1366 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP4]] 1367 // CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 1368 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]] 1369 // CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 1370 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[SIVAR1]]), !llvm.access.group [[ACC_GRP4]] 1371 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1372 // CHECK5: omp.inner.for.inc: 1373 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 1374 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP4]] 1375 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 1376 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 1377 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 1378 // CHECK5: omp.inner.for.end: 1379 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1380 // CHECK5: omp.loop.exit: 1381 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 1382 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1383 // CHECK5-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 1384 // CHECK5-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1385 // CHECK5: .omp.final.then: 1386 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 1387 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 1388 // CHECK5: .omp.final.done: 1389 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 1390 // CHECK5-NEXT: store ptr [[SIVAR1]], ptr [[TMP16]], align 8 1391 // CHECK5-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 1392 // CHECK5-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1393 // CHECK5-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1394 // CHECK5-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1395 // CHECK5-NEXT: ] 1396 // CHECK5: .omp.reduction.case1: 1397 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 1398 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR1]], align 4 1399 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 1400 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 1401 // CHECK5-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) 1402 // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1403 // CHECK5: .omp.reduction.case2: 1404 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR1]], align 4 1405 // CHECK5-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 1406 // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1407 // CHECK5: .omp.reduction.default: 1408 // CHECK5-NEXT: ret void 1409 // 1410 // 1411 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44.omp_outlined.omp_outlined 1412 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { 1413 // CHECK5-NEXT: entry: 1414 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1415 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1416 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1417 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1418 // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 1419 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1420 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1421 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1422 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1423 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1424 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1425 // CHECK5-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 1426 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1427 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1428 // CHECK5-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 1429 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1430 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1431 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1432 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1433 // CHECK5-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 1434 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 1435 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1436 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1437 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1438 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 1439 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1440 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 1441 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1442 // CHECK5-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 1443 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1444 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1445 // CHECK5-NEXT: store i32 0, ptr [[SIVAR2]], align 4 1446 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1447 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 1448 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1449 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1450 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 1451 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1452 // CHECK5: cond.true: 1453 // CHECK5-NEXT: br label [[COND_END:%.*]] 1454 // CHECK5: cond.false: 1455 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1456 // CHECK5-NEXT: br label [[COND_END]] 1457 // CHECK5: cond.end: 1458 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 1459 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1460 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1461 // CHECK5-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 1462 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1463 // CHECK5: omp.inner.for.cond: 1464 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]] 1465 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]] 1466 // CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 1467 // CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1468 // CHECK5: omp.inner.for.body: 1469 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 1470 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 1471 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1472 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 1473 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 1474 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR2]], align 4, !llvm.access.group [[ACC_GRP8]] 1475 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 1476 // CHECK5-NEXT: store i32 [[ADD4]], ptr [[SIVAR2]], align 4, !llvm.access.group [[ACC_GRP8]] 1477 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 1478 // CHECK5-NEXT: store ptr [[SIVAR2]], ptr [[TMP13]], align 8, !llvm.access.group [[ACC_GRP8]] 1479 // CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group [[ACC_GRP8]] 1480 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1481 // CHECK5: omp.body.continue: 1482 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1483 // CHECK5: omp.inner.for.inc: 1484 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 1485 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 1486 // CHECK5-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 1487 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 1488 // CHECK5: omp.inner.for.end: 1489 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1490 // CHECK5: omp.loop.exit: 1491 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) 1492 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1493 // CHECK5-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 1494 // CHECK5-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1495 // CHECK5: .omp.final.then: 1496 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 1497 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 1498 // CHECK5: .omp.final.done: 1499 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 1500 // CHECK5-NEXT: store ptr [[SIVAR2]], ptr [[TMP17]], align 8 1501 // CHECK5-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 1502 // CHECK5-NEXT: switch i32 [[TMP18]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1503 // CHECK5-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1504 // CHECK5-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1505 // CHECK5-NEXT: ] 1506 // CHECK5: .omp.reduction.case1: 1507 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP0]], align 4 1508 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR2]], align 4 1509 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] 1510 // CHECK5-NEXT: store i32 [[ADD6]], ptr [[TMP0]], align 4 1511 // CHECK5-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) 1512 // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1513 // CHECK5: .omp.reduction.case2: 1514 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[SIVAR2]], align 4 1515 // CHECK5-NEXT: [[TMP22:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP21]] monotonic, align 4 1516 // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1517 // CHECK5: .omp.reduction.default: 1518 // CHECK5-NEXT: ret void 1519 // 1520 // 1521 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44.omp_outlined.omp_outlined.omp.reduction.reduction_func 1522 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { 1523 // CHECK5-NEXT: entry: 1524 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1525 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 1526 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1527 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 1528 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1529 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 1530 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 1531 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 1532 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 1533 // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 1534 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1535 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 1536 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 1537 // CHECK5-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 1538 // CHECK5-NEXT: ret void 1539 // 1540 // 1541 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44.omp_outlined.omp.reduction.reduction_func 1542 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR4]] { 1543 // CHECK5-NEXT: entry: 1544 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1545 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 1546 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1547 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 1548 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1549 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 1550 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 1551 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 1552 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 1553 // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 1554 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1555 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 1556 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 1557 // CHECK5-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 1558 // CHECK5-NEXT: ret void 1559 // 1560 // 1561 // CHECK7-LABEL: define {{[^@]+}}@main 1562 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 1563 // CHECK7-NEXT: entry: 1564 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1565 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 1566 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1567 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1568 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1569 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 1570 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1571 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 1572 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1573 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1574 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1575 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 1576 // CHECK7-NEXT: store i32 0, ptr [[SIVAR]], align 4 1577 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1578 // CHECK7: omp.inner.for.cond: 1579 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 1580 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 1581 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1582 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1583 // CHECK7: omp.inner.for.body: 1584 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1585 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1586 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1587 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1588 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1589 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] 1590 // CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 1591 // CHECK7-NEXT: store i32 [[ADD1]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] 1592 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1593 // CHECK7: omp.body.continue: 1594 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1595 // CHECK7: omp.inner.for.inc: 1596 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1597 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 1598 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1599 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1600 // CHECK7: omp.inner.for.end: 1601 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 1602 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 1603 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4 1604 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 1605 // CHECK7-NEXT: store i32 [[ADD3]], ptr @_ZZ4mainE5sivar, align 4 1606 // CHECK7-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 1607 // CHECK7-NEXT: ret i32 [[CALL]] 1608 // 1609 // 1610 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1611 // CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat { 1612 // CHECK7-NEXT: entry: 1613 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1614 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1615 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 1616 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1617 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1618 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1619 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 1620 // CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 1621 // CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 4 1622 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 1623 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1624 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1625 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1626 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 1627 // CHECK7-NEXT: store i32 0, ptr [[T_VAR1]], align 4 1628 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1629 // CHECK7: omp.inner.for.cond: 1630 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 1631 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 1632 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1633 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1634 // CHECK7: omp.inner.for.body: 1635 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1636 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1637 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1638 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1639 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1640 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP6]] 1641 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 1642 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP6]] 1643 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1644 // CHECK7: omp.body.continue: 1645 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1646 // CHECK7: omp.inner.for.inc: 1647 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1648 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP6]], 1 1649 // CHECK7-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1650 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1651 // CHECK7: omp.inner.for.end: 1652 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 1653 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4 1654 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR1]], align 4 1655 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 1656 // CHECK7-NEXT: store i32 [[ADD4]], ptr [[T_VAR]], align 4 1657 // CHECK7-NEXT: ret i32 0 1658 // 1659 // 1660 // CHECK9-LABEL: define {{[^@]+}}@main 1661 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 1662 // CHECK9-NEXT: entry: 1663 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1664 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1665 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1666 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1667 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1668 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1669 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1670 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 1671 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1672 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1673 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1674 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 1675 // CHECK9-NEXT: store i32 0, ptr [[SIVAR]], align 4 1676 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1677 // CHECK9: omp.inner.for.cond: 1678 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 1679 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 1680 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1681 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1682 // CHECK9: omp.inner.for.body: 1683 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 1684 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1685 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1686 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 1687 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 1688 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] 1689 // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 1690 // CHECK9-NEXT: store i32 [[ADD1]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] 1691 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1692 // CHECK9: omp.body.continue: 1693 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1694 // CHECK9: omp.inner.for.inc: 1695 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 1696 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 1697 // CHECK9-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 1698 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 1699 // CHECK9: omp.inner.for.end: 1700 // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 1701 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 1702 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4 1703 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 1704 // CHECK9-NEXT: store i32 [[ADD3]], ptr @_ZZ4mainE5sivar, align 4 1705 // CHECK9-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1706 // CHECK9-NEXT: ret i32 [[CALL]] 1707 // 1708 // 1709 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1710 // CHECK9-SAME: () #[[ATTR1:[0-9]+]] comdat { 1711 // CHECK9-NEXT: entry: 1712 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1713 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1714 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1715 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1716 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1717 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1718 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1719 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 1720 // CHECK9-NEXT: store i32 0, ptr [[T_VAR]], align 4 1721 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 1722 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1723 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1724 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1725 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 1726 // CHECK9-NEXT: store i32 0, ptr [[T_VAR1]], align 4 1727 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1728 // CHECK9: omp.inner.for.cond: 1729 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 1730 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]] 1731 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1732 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1733 // CHECK9: omp.inner.for.body: 1734 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 1735 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1736 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1737 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 1738 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 1739 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP7]] 1740 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 1741 // CHECK9-NEXT: store i32 [[ADD2]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP7]] 1742 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1743 // CHECK9: omp.body.continue: 1744 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1745 // CHECK9: omp.inner.for.inc: 1746 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 1747 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP6]], 1 1748 // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 1749 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 1750 // CHECK9: omp.inner.for.end: 1751 // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 1752 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4 1753 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR1]], align 4 1754 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 1755 // CHECK9-NEXT: store i32 [[ADD4]], ptr [[T_VAR]], align 4 1756 // CHECK9-NEXT: ret i32 0 1757 // 1758 // 1759 // CHECK11-LABEL: define {{[^@]+}}@main 1760 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 1761 // CHECK11-NEXT: entry: 1762 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1763 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1764 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 1765 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 1766 // CHECK11-NEXT: ret i32 0 1767 // 1768