1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 12 13 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 16 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 23 24 // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region) 25 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 26 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 27 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 28 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 29 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 30 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 31 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 32 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 33 34 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 35 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 36 37 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 38 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 39 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 40 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 41 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 42 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 43 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 44 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 45 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 46 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 47 48 // expected-no-diagnostics 49 #ifndef HEADER 50 #define HEADER 51 52 struct St { 53 int a, b; 54 St() : a(0), b(0) {} 55 St(const St &st) : a(st.a + st.b), b(0) {} 56 ~St() {} 57 }; 58 59 volatile int g = 1212; 60 volatile int &g1 = g; 61 62 template <class T> 63 struct S { 64 T f; 65 S(T a) : f(a + g) {} 66 S() : f(g) {} 67 S(const S &s, St t = St()) : f(s.f + t.a) {} 68 operator T() { return T(); } 69 ~S() {} 70 }; 71 72 73 template <typename T> 74 T tmain() { 75 S<T> test; 76 T t_var = T(); 77 T vec[] = {1, 2}; 78 S<T> s_arr[] = {1, 2}; 79 S<T> &var = test; 80 #pragma omp target teams distribute parallel for simd private(t_var, vec, s_arr, var) 81 for (int i = 0; i < 2; ++i) { 82 vec[i] = t_var; 83 s_arr[i] = var; 84 } 85 return T(); 86 } 87 88 // HCHECK-DAG: [[TEST:@.+]] ={{.*}} global [[S_FLOAT_TY]] zeroinitializer, 89 S<float> test; 90 // HCHECK-DAG: [[T_VAR:@.+]] ={{.+}} global i{{[0-9]+}} 333, 91 int t_var = 333; 92 // HCHECK-DAG: [[VEC:@.+]] ={{.+}} global [2 x i{{[0-9]+}}] [i{{[0-9]+}} 1, i{{[0-9]+}} 2], 93 int vec[] = {1, 2}; 94 // HCHECK-DAG: [[S_ARR:@.+]] ={{.+}} global [2 x [[S_FLOAT_TY]]] zeroinitializer, 95 S<float> s_arr[] = {1, 2}; 96 // HCHECK-DAG: [[VAR:@.+]] ={{.+}} global [[S_FLOAT_TY]] zeroinitializer, 97 S<float> var(3); 98 // HCHECK-DAG: [[SIVAR:@.+]] = internal global i{{[0-9]+}} 0, 99 100 int main() { 101 static int sivar; 102 #ifdef LAMBDA 103 [&]() { 104 #pragma omp target teams distribute parallel for simd private(g, g1, sivar) 105 for (int i = 0; i < 2; ++i) { 106 107 // Skip global, bound tid and loop vars 108 109 g = 1; 110 g1 = 1; 111 sivar = 2; 112 113 // Skip global, bound tid and loop vars 114 [&]() { 115 g = 2; 116 g1 = 2; 117 sivar = 4; 118 119 }(); 120 } 121 }(); 122 return 0; 123 #else 124 #pragma omp target teams distribute parallel for simd private(t_var, vec, s_arr, var, sivar) 125 for (int i = 0; i < 2; ++i) { 126 vec[i] = t_var; 127 s_arr[i] = var; 128 sivar += i; 129 } 130 return tmain<int>(); 131 #endif 132 } 133 134 // HCHECK: define {{.*}}i{{[0-9]+}} @main() 135 // HCHECK: call i32 @__tgt_target_teams_mapper(ptr @{{.+}}, i64 -1, ptr @{{[^,]+}}, i32 0, ptr null, ptr null, {{.+}} null, {{.+}} null, ptr null, ptr null, i32 0, i32 0) 136 // HCHECK: call void @[[OFFL1:.+]]() 137 // HCHECK: {{%.+}} = call{{.*}} i32 @[[TMAIN_INT:.+]]() 138 // HCHECK: ret 139 140 // HCHECK: define{{.*}} void @[[OFFL1]]() 141 142 // Skip global, bound tid and loop vars 143 144 // private(s_arr) 145 146 // private(var) 147 148 149 // Skip global, bound tid and loop vars 150 151 // private(s_arr) 152 153 // private(var) 154 155 156 // HCHECK: define{{.*}} i{{[0-9]+}} @[[TMAIN_INT]]() 157 // HCHECK: call i32 @__tgt_target_teams_mapper(ptr @{{.+}}, i64 -1, ptr @{{[^,]+}}, i32 0, 158 // HCHECK: call void @[[TOFFL1:.+]]() 159 // HCHECK: ret 160 161 // HCHECK: define {{.*}}void @[[TOFFL1]]() 162 163 // Skip global, bound tid and loop vars 164 165 // private(s_arr) 166 167 168 // private(var) 169 170 171 // Skip global, bound tid and loop vars 172 // prev lb and ub 173 // iter variables 174 175 // private(s_arr) 176 177 178 // private(var) 179 180 181 182 #endif 183 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 184 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 185 // CHECK1-NEXT: entry: 186 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 187 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 188 // CHECK1-NEXT: ret void 189 // 190 // 191 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 192 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 193 // CHECK1-NEXT: entry: 194 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 195 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 196 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 197 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 198 // CHECK1-NEXT: ret void 199 // 200 // 201 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 202 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 203 // CHECK1-NEXT: entry: 204 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 205 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 206 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 207 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 208 // CHECK1-NEXT: ret void 209 // 210 // 211 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 212 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 213 // CHECK1-NEXT: entry: 214 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 215 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 216 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 217 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 218 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 219 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 220 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 221 // CHECK1-NEXT: ret void 222 // 223 // 224 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 225 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 226 // CHECK1-NEXT: entry: 227 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 228 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 229 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 230 // CHECK1-NEXT: ret void 231 // 232 // 233 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 234 // CHECK1-SAME: () #[[ATTR0]] { 235 // CHECK1-NEXT: entry: 236 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 237 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 238 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 239 // CHECK1-NEXT: ret void 240 // 241 // 242 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 243 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 244 // CHECK1-NEXT: entry: 245 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 246 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 247 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 248 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 249 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 250 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 251 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 252 // CHECK1-NEXT: ret void 253 // 254 // 255 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 256 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 257 // CHECK1-NEXT: entry: 258 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 259 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 260 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 261 // CHECK1: arraydestroy.body: 262 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 263 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 264 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 265 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 266 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 267 // CHECK1: arraydestroy.done1: 268 // CHECK1-NEXT: ret void 269 // 270 // 271 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 272 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 273 // CHECK1-NEXT: entry: 274 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 275 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 276 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 277 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 278 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 279 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 280 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 281 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 282 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 283 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 284 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 285 // CHECK1-NEXT: ret void 286 // 287 // 288 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 289 // CHECK1-SAME: () #[[ATTR0]] { 290 // CHECK1-NEXT: entry: 291 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 292 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 293 // CHECK1-NEXT: ret void 294 // 295 // 296 // CHECK1-LABEL: define {{[^@]+}}@main 297 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 298 // CHECK1-NEXT: entry: 299 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 300 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 301 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 302 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 303 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 304 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 305 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 306 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 307 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 308 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 309 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 310 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 311 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 312 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 313 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 314 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 315 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 316 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 317 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 318 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 319 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 320 // CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8 321 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 322 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 323 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 324 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 325 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 326 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 327 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 328 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 329 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.region_id, ptr [[KERNEL_ARGS]]) 330 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 331 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 332 // CHECK1: omp_offload.failed: 333 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124() #[[ATTR2]] 334 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 335 // CHECK1: omp_offload.cont: 336 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 337 // CHECK1-NEXT: ret i32 [[CALL]] 338 // 339 // 340 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 341 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 342 // CHECK1-NEXT: entry: 343 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) 344 // CHECK1-NEXT: ret void 345 // 346 // 347 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined 348 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 349 // CHECK1-NEXT: entry: 350 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 351 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 352 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 353 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 354 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 355 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 356 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 357 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 358 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 359 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 360 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 361 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 362 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 363 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 364 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 365 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 366 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 367 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 368 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 369 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 370 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 371 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 372 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 373 // CHECK1: arrayctor.loop: 374 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 375 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 376 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 377 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 378 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 379 // CHECK1: arrayctor.cont: 380 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 381 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 382 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 383 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 384 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 385 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 386 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 387 // CHECK1: cond.true: 388 // CHECK1-NEXT: br label [[COND_END:%.*]] 389 // CHECK1: cond.false: 390 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 391 // CHECK1-NEXT: br label [[COND_END]] 392 // CHECK1: cond.end: 393 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 394 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 395 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 396 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 397 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 398 // CHECK1: omp.inner.for.cond: 399 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] 400 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 401 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 402 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 403 // CHECK1: omp.inner.for.cond.cleanup: 404 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 405 // CHECK1: omp.inner.for.body: 406 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP5]] 407 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 408 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 409 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 410 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP5]] 411 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 412 // CHECK1: omp.inner.for.inc: 413 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 414 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP5]] 415 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 416 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 417 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 418 // CHECK1: omp.inner.for.end: 419 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 420 // CHECK1: omp.loop.exit: 421 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 422 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 423 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 424 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 425 // CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 426 // CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 427 // CHECK1: .omp.final.then: 428 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 429 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 430 // CHECK1: .omp.final.done: 431 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 432 // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 433 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2 434 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 435 // CHECK1: arraydestroy.body: 436 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 437 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 438 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 439 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 440 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 441 // CHECK1: arraydestroy.done3: 442 // CHECK1-NEXT: ret void 443 // 444 // 445 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined 446 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 447 // CHECK1-NEXT: entry: 448 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 449 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 450 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 451 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 452 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 453 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 454 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 455 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 456 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 457 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 458 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 459 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 460 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 461 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 462 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 463 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 464 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 465 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 466 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 467 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 468 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 469 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 470 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 471 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 472 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 473 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 474 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 475 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 476 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 477 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 478 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 479 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 480 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 481 // CHECK1: arrayctor.loop: 482 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 483 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 484 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 485 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 486 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 487 // CHECK1: arrayctor.cont: 488 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 489 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 490 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 491 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 492 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 493 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 494 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 495 // CHECK1: cond.true: 496 // CHECK1-NEXT: br label [[COND_END:%.*]] 497 // CHECK1: cond.false: 498 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 499 // CHECK1-NEXT: br label [[COND_END]] 500 // CHECK1: cond.end: 501 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 502 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 503 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 504 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 505 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 506 // CHECK1: omp.inner.for.cond: 507 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] 508 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 509 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 510 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 511 // CHECK1: omp.inner.for.cond.cleanup: 512 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 513 // CHECK1: omp.inner.for.body: 514 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 515 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 516 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 517 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 518 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP9]] 519 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 520 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 521 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 522 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] 523 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 524 // CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 525 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] 526 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] 527 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 528 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP9]] 529 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 530 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP9]] 531 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 532 // CHECK1: omp.body.continue: 533 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 534 // CHECK1: omp.inner.for.inc: 535 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 536 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP15]], 1 537 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 538 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 539 // CHECK1: omp.inner.for.end: 540 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 541 // CHECK1: omp.loop.exit: 542 // CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 543 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 544 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) 545 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 546 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 547 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 548 // CHECK1: .omp.final.then: 549 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 550 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 551 // CHECK1: .omp.final.done: 552 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 553 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 554 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 555 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 556 // CHECK1: arraydestroy.body: 557 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 558 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 559 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 560 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 561 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 562 // CHECK1: arraydestroy.done8: 563 // CHECK1-NEXT: ret void 564 // 565 // 566 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 567 // CHECK1-SAME: () #[[ATTR1]] comdat { 568 // CHECK1-NEXT: entry: 569 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 570 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 571 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 572 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 573 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 574 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 575 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 576 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 577 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 578 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 579 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 580 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 581 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 582 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 583 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 584 // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 585 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 586 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 587 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 588 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 589 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 590 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 591 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 592 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 593 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 594 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 595 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 596 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 597 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 598 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 599 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 600 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 601 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 602 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 603 // CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8 604 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 605 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 606 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 607 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 608 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 609 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 610 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 611 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 612 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.region_id, ptr [[KERNEL_ARGS]]) 613 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 614 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 615 // CHECK1: omp_offload.failed: 616 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80() #[[ATTR2]] 617 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 618 // CHECK1: omp_offload.cont: 619 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 620 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 621 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 622 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 623 // CHECK1: arraydestroy.body: 624 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 625 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 626 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 627 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 628 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 629 // CHECK1: arraydestroy.done2: 630 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 631 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 632 // CHECK1-NEXT: ret i32 [[TMP16]] 633 // 634 // 635 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 636 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 637 // CHECK1-NEXT: entry: 638 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 639 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 640 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 641 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 642 // CHECK1-NEXT: ret void 643 // 644 // 645 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 646 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 647 // CHECK1-NEXT: entry: 648 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 649 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 650 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 651 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 652 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 653 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 654 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 655 // CHECK1-NEXT: ret void 656 // 657 // 658 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 659 // CHECK1-SAME: () #[[ATTR4]] { 660 // CHECK1-NEXT: entry: 661 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) 662 // CHECK1-NEXT: ret void 663 // 664 // 665 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined 666 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 667 // CHECK1-NEXT: entry: 668 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 669 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 670 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 671 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 672 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 673 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 674 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 675 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 676 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 677 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 678 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 679 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 680 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 681 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 682 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 683 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 684 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 685 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 686 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 687 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 688 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 689 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 690 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 691 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 692 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 693 // CHECK1: arrayctor.loop: 694 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 695 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 696 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 697 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 698 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 699 // CHECK1: arrayctor.cont: 700 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 701 // CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 8 702 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 703 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 704 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 705 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 706 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 707 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 708 // CHECK1: cond.true: 709 // CHECK1-NEXT: br label [[COND_END:%.*]] 710 // CHECK1: cond.false: 711 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 712 // CHECK1-NEXT: br label [[COND_END]] 713 // CHECK1: cond.end: 714 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 715 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 716 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 717 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 718 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 719 // CHECK1: omp.inner.for.cond: 720 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]] 721 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]] 722 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 723 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 724 // CHECK1: omp.inner.for.cond.cleanup: 725 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 726 // CHECK1: omp.inner.for.body: 727 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP14]] 728 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 729 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]] 730 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 731 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP14]] 732 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 733 // CHECK1: omp.inner.for.inc: 734 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 735 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP14]] 736 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 737 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 738 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 739 // CHECK1: omp.inner.for.end: 740 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 741 // CHECK1: omp.loop.exit: 742 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 743 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 744 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 745 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 746 // CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 747 // CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 748 // CHECK1: .omp.final.then: 749 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 750 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 751 // CHECK1: .omp.final.done: 752 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 753 // CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 754 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2 755 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 756 // CHECK1: arraydestroy.body: 757 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 758 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 759 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 760 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 761 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 762 // CHECK1: arraydestroy.done5: 763 // CHECK1-NEXT: ret void 764 // 765 // 766 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined 767 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 768 // CHECK1-NEXT: entry: 769 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 770 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 771 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 772 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 773 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 774 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 775 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 776 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 777 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 778 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 779 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 780 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 781 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 782 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 783 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 784 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 785 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 786 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 787 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 788 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 789 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 790 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 791 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 792 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 793 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 794 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 795 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 796 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 797 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 798 // CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 799 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 800 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 801 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 802 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 803 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 804 // CHECK1: arrayctor.loop: 805 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 806 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 807 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 808 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 809 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 810 // CHECK1: arrayctor.cont: 811 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 812 // CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP3]], align 8 813 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 814 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 815 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 816 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 817 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 818 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 819 // CHECK1: cond.true: 820 // CHECK1-NEXT: br label [[COND_END:%.*]] 821 // CHECK1: cond.false: 822 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 823 // CHECK1-NEXT: br label [[COND_END]] 824 // CHECK1: cond.end: 825 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 826 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 827 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 828 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 829 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 830 // CHECK1: omp.inner.for.cond: 831 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]] 832 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP17]] 833 // CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 834 // CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 835 // CHECK1: omp.inner.for.cond.cleanup: 836 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 837 // CHECK1: omp.inner.for.body: 838 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 839 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 840 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 841 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 842 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP17]] 843 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 844 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 845 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 846 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]] 847 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !llvm.access.group [[ACC_GRP17]] 848 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 849 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 850 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] 851 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group [[ACC_GRP17]] 852 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 853 // CHECK1: omp.body.continue: 854 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 855 // CHECK1: omp.inner.for.inc: 856 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 857 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP14]], 1 858 // CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 859 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 860 // CHECK1: omp.inner.for.end: 861 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 862 // CHECK1: omp.loop.exit: 863 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 864 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 865 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) 866 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 867 // CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 868 // CHECK1-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 869 // CHECK1: .omp.final.then: 870 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 871 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 872 // CHECK1: .omp.final.done: 873 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 874 // CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 875 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 876 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 877 // CHECK1: arraydestroy.body: 878 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 879 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 880 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 881 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 882 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 883 // CHECK1: arraydestroy.done9: 884 // CHECK1-NEXT: ret void 885 // 886 // 887 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 888 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 889 // CHECK1-NEXT: entry: 890 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 891 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 892 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 893 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 894 // CHECK1-NEXT: ret void 895 // 896 // 897 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 898 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 899 // CHECK1-NEXT: entry: 900 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 901 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 902 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 903 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 904 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 905 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 906 // CHECK1-NEXT: ret void 907 // 908 // 909 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 910 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 911 // CHECK1-NEXT: entry: 912 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 913 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 914 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 915 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 916 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 917 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 918 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 919 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 920 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 921 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 922 // CHECK1-NEXT: ret void 923 // 924 // 925 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 926 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 927 // CHECK1-NEXT: entry: 928 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 929 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 930 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 931 // CHECK1-NEXT: ret void 932 // 933 // 934 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_private_codegen.cpp 935 // CHECK1-SAME: () #[[ATTR0]] { 936 // CHECK1-NEXT: entry: 937 // CHECK1-NEXT: call void @__cxx_global_var_init() 938 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 939 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 940 // CHECK1-NEXT: ret void 941 // 942 // 943 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 944 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 945 // CHECK3-NEXT: entry: 946 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 947 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 948 // CHECK3-NEXT: ret void 949 // 950 // 951 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 952 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 953 // CHECK3-NEXT: entry: 954 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 955 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 956 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 957 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 958 // CHECK3-NEXT: ret void 959 // 960 // 961 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 962 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 963 // CHECK3-NEXT: entry: 964 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 965 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 966 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 967 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 968 // CHECK3-NEXT: ret void 969 // 970 // 971 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 972 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 973 // CHECK3-NEXT: entry: 974 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 975 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 976 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 977 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 978 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 979 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 980 // CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4 981 // CHECK3-NEXT: ret void 982 // 983 // 984 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 985 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 986 // CHECK3-NEXT: entry: 987 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 988 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 989 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 990 // CHECK3-NEXT: ret void 991 // 992 // 993 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 994 // CHECK3-SAME: () #[[ATTR0]] { 995 // CHECK3-NEXT: entry: 996 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 997 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 998 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 999 // CHECK3-NEXT: ret void 1000 // 1001 // 1002 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1003 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1004 // CHECK3-NEXT: entry: 1005 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1006 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1007 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1008 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1009 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1010 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1011 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1012 // CHECK3-NEXT: ret void 1013 // 1014 // 1015 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1016 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1017 // CHECK3-NEXT: entry: 1018 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 1019 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 1020 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1021 // CHECK3: arraydestroy.body: 1022 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1023 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1024 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1025 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1026 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1027 // CHECK3: arraydestroy.done1: 1028 // CHECK3-NEXT: ret void 1029 // 1030 // 1031 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1032 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1033 // CHECK3-NEXT: entry: 1034 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1035 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1036 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1037 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1038 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1039 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1040 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1041 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1042 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1043 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1044 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 1045 // CHECK3-NEXT: ret void 1046 // 1047 // 1048 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1049 // CHECK3-SAME: () #[[ATTR0]] { 1050 // CHECK3-NEXT: entry: 1051 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1052 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1053 // CHECK3-NEXT: ret void 1054 // 1055 // 1056 // CHECK3-LABEL: define {{[^@]+}}@main 1057 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1058 // CHECK3-NEXT: entry: 1059 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1060 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1061 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1062 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1063 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1064 // CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4 1065 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1066 // CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4 1067 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1068 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 1069 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1070 // CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4 1071 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1072 // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 1073 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1074 // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 1075 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1076 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1077 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1078 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 1079 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1080 // CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8 1081 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1082 // CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8 1083 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1084 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 1085 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1086 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 1087 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1088 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 1089 // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.region_id, ptr [[KERNEL_ARGS]]) 1090 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1091 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1092 // CHECK3: omp_offload.failed: 1093 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124() #[[ATTR2]] 1094 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1095 // CHECK3: omp_offload.cont: 1096 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1097 // CHECK3-NEXT: ret i32 [[CALL]] 1098 // 1099 // 1100 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 1101 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 1102 // CHECK3-NEXT: entry: 1103 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) 1104 // CHECK3-NEXT: ret void 1105 // 1106 // 1107 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined 1108 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1109 // CHECK3-NEXT: entry: 1110 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1111 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1112 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1113 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1114 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1115 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1116 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1117 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1118 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1119 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1120 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1121 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1122 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1123 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1124 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1125 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1126 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1127 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1128 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1129 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1130 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1131 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1132 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1133 // CHECK3: arrayctor.loop: 1134 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1135 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1136 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 1137 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1138 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1139 // CHECK3: arrayctor.cont: 1140 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1141 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1142 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1143 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1144 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1145 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1146 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1147 // CHECK3: cond.true: 1148 // CHECK3-NEXT: br label [[COND_END:%.*]] 1149 // CHECK3: cond.false: 1150 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1151 // CHECK3-NEXT: br label [[COND_END]] 1152 // CHECK3: cond.end: 1153 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1154 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1155 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1156 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1157 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1158 // CHECK3: omp.inner.for.cond: 1159 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 1160 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 1161 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1162 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1163 // CHECK3: omp.inner.for.cond.cleanup: 1164 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1165 // CHECK3: omp.inner.for.body: 1166 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP6]] 1167 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 1168 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP6]] 1169 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1170 // CHECK3: omp.inner.for.inc: 1171 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1172 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP6]] 1173 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] 1174 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1175 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1176 // CHECK3: omp.inner.for.end: 1177 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1178 // CHECK3: omp.loop.exit: 1179 // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1180 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 1181 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) 1182 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1183 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1184 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1185 // CHECK3: .omp.final.then: 1186 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 1187 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1188 // CHECK3: .omp.final.done: 1189 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1190 // CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1191 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i32 2 1192 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1193 // CHECK3: arraydestroy.body: 1194 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1195 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1196 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1197 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 1198 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 1199 // CHECK3: arraydestroy.done3: 1200 // CHECK3-NEXT: ret void 1201 // 1202 // 1203 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined 1204 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 1205 // CHECK3-NEXT: entry: 1206 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1207 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1208 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 1209 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 1210 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1211 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1212 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1213 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1214 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1215 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1216 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1217 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1218 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1219 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1220 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1221 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1222 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1223 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1224 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1225 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1226 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1227 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1228 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1229 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1230 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4 1231 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 1232 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1233 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1234 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1235 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1236 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1237 // CHECK3: arrayctor.loop: 1238 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1239 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1240 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 1241 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1242 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1243 // CHECK3: arrayctor.cont: 1244 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1245 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1246 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1247 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1248 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1249 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 1250 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1251 // CHECK3: cond.true: 1252 // CHECK3-NEXT: br label [[COND_END:%.*]] 1253 // CHECK3: cond.false: 1254 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1255 // CHECK3-NEXT: br label [[COND_END]] 1256 // CHECK3: cond.end: 1257 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1258 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1259 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1260 // CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1261 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1262 // CHECK3: omp.inner.for.cond: 1263 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 1264 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 1265 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1266 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1267 // CHECK3: omp.inner.for.cond.cleanup: 1268 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1269 // CHECK3: omp.inner.for.body: 1270 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 1271 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1272 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1273 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 1274 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP10]] 1275 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 1276 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] 1277 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] 1278 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 1279 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]] 1280 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] 1281 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 1282 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP10]] 1283 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 1284 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP10]] 1285 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1286 // CHECK3: omp.body.continue: 1287 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1288 // CHECK3: omp.inner.for.inc: 1289 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 1290 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 1291 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 1292 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 1293 // CHECK3: omp.inner.for.end: 1294 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1295 // CHECK3: omp.loop.exit: 1296 // CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1297 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 1298 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) 1299 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1300 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 1301 // CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1302 // CHECK3: .omp.final.then: 1303 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 1304 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1305 // CHECK3: .omp.final.done: 1306 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1307 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1308 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 1309 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1310 // CHECK3: arraydestroy.body: 1311 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1312 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1313 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1314 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 1315 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 1316 // CHECK3: arraydestroy.done6: 1317 // CHECK3-NEXT: ret void 1318 // 1319 // 1320 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1321 // CHECK3-SAME: () #[[ATTR1]] comdat { 1322 // CHECK3-NEXT: entry: 1323 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1324 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1325 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1326 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1327 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1328 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 1329 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1330 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 1331 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1332 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1333 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 1334 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 1335 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 1336 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 1337 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1338 // CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 1339 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 1340 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1341 // CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4 1342 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1343 // CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4 1344 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1345 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 1346 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1347 // CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4 1348 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1349 // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 1350 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1351 // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 1352 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1353 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1354 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1355 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 1356 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1357 // CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8 1358 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1359 // CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8 1360 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1361 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 1362 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1363 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 1364 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1365 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 1366 // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.region_id, ptr [[KERNEL_ARGS]]) 1367 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1368 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1369 // CHECK3: omp_offload.failed: 1370 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80() #[[ATTR2]] 1371 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1372 // CHECK3: omp_offload.cont: 1373 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1374 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1375 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1376 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1377 // CHECK3: arraydestroy.body: 1378 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1379 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1380 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1381 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1382 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1383 // CHECK3: arraydestroy.done2: 1384 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1385 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 1386 // CHECK3-NEXT: ret i32 [[TMP16]] 1387 // 1388 // 1389 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1390 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1391 // CHECK3-NEXT: entry: 1392 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1393 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1394 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1395 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1396 // CHECK3-NEXT: ret void 1397 // 1398 // 1399 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1400 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1401 // CHECK3-NEXT: entry: 1402 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1403 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1404 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1405 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1406 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1407 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1408 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1409 // CHECK3-NEXT: ret void 1410 // 1411 // 1412 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 1413 // CHECK3-SAME: () #[[ATTR4]] { 1414 // CHECK3-NEXT: entry: 1415 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) 1416 // CHECK3-NEXT: ret void 1417 // 1418 // 1419 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined 1420 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1421 // CHECK3-NEXT: entry: 1422 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1423 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1424 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1425 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1426 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 1427 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1428 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1429 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1430 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1431 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1432 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1433 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1434 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1435 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 1436 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1437 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1438 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1439 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 1440 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1441 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1442 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1443 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1444 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1445 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1446 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1447 // CHECK3: arrayctor.loop: 1448 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1449 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1450 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 1451 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1452 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1453 // CHECK3: arrayctor.cont: 1454 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1455 // CHECK3-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 4 1456 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1457 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1458 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1459 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1460 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1461 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1462 // CHECK3: cond.true: 1463 // CHECK3-NEXT: br label [[COND_END:%.*]] 1464 // CHECK3: cond.false: 1465 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1466 // CHECK3-NEXT: br label [[COND_END]] 1467 // CHECK3: cond.end: 1468 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1469 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1470 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1471 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1472 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1473 // CHECK3: omp.inner.for.cond: 1474 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] 1475 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 1476 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1477 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1478 // CHECK3: omp.inner.for.cond.cleanup: 1479 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1480 // CHECK3: omp.inner.for.body: 1481 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]] 1482 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 1483 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP15]] 1484 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1485 // CHECK3: omp.inner.for.inc: 1486 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 1487 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]] 1488 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] 1489 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 1490 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 1491 // CHECK3: omp.inner.for.end: 1492 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1493 // CHECK3: omp.loop.exit: 1494 // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1495 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 1496 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) 1497 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1498 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1499 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1500 // CHECK3: .omp.final.then: 1501 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 1502 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1503 // CHECK3: .omp.final.done: 1504 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1505 // CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1506 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2 1507 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1508 // CHECK3: arraydestroy.body: 1509 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1510 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1511 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1512 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 1513 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 1514 // CHECK3: arraydestroy.done5: 1515 // CHECK3-NEXT: ret void 1516 // 1517 // 1518 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined 1519 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 1520 // CHECK3-NEXT: entry: 1521 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1522 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1523 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 1524 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 1525 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1526 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1527 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 1528 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1529 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1530 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1531 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1532 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1533 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1534 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1535 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1536 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 1537 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1538 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1539 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1540 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1541 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1542 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 1543 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1544 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1545 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1546 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1547 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4 1548 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 1549 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1550 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1551 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1552 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1553 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1554 // CHECK3: arrayctor.loop: 1555 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1556 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1557 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 1558 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1559 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1560 // CHECK3: arrayctor.cont: 1561 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1562 // CHECK3-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 4 1563 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1564 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1565 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1566 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1567 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 1568 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1569 // CHECK3: cond.true: 1570 // CHECK3-NEXT: br label [[COND_END:%.*]] 1571 // CHECK3: cond.false: 1572 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1573 // CHECK3-NEXT: br label [[COND_END]] 1574 // CHECK3: cond.end: 1575 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1576 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1577 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1578 // CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1579 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1580 // CHECK3: omp.inner.for.cond: 1581 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] 1582 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] 1583 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1584 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1585 // CHECK3: omp.inner.for.cond.cleanup: 1586 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1587 // CHECK3: omp.inner.for.body: 1588 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 1589 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1590 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1591 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 1592 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP18]] 1593 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 1594 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] 1595 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] 1596 // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP18]] 1597 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 1598 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] 1599 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group [[ACC_GRP18]] 1600 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1601 // CHECK3: omp.body.continue: 1602 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1603 // CHECK3: omp.inner.for.inc: 1604 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 1605 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 1606 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 1607 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 1608 // CHECK3: omp.inner.for.end: 1609 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1610 // CHECK3: omp.loop.exit: 1611 // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1612 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 1613 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) 1614 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1615 // CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 1616 // CHECK3-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1617 // CHECK3: .omp.final.then: 1618 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 1619 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1620 // CHECK3: .omp.final.done: 1621 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1622 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1623 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 1624 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1625 // CHECK3: arraydestroy.body: 1626 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1627 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1628 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1629 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 1630 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1631 // CHECK3: arraydestroy.done7: 1632 // CHECK3-NEXT: ret void 1633 // 1634 // 1635 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1636 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1637 // CHECK3-NEXT: entry: 1638 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1639 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1640 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1641 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1642 // CHECK3-NEXT: ret void 1643 // 1644 // 1645 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1646 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1647 // CHECK3-NEXT: entry: 1648 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1649 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1650 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1651 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1652 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1653 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1654 // CHECK3-NEXT: ret void 1655 // 1656 // 1657 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1658 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1659 // CHECK3-NEXT: entry: 1660 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1661 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1662 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1663 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1664 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1665 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1666 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1667 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1668 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1669 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1670 // CHECK3-NEXT: ret void 1671 // 1672 // 1673 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1674 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1675 // CHECK3-NEXT: entry: 1676 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1677 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1678 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1679 // CHECK3-NEXT: ret void 1680 // 1681 // 1682 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_private_codegen.cpp 1683 // CHECK3-SAME: () #[[ATTR0]] { 1684 // CHECK3-NEXT: entry: 1685 // CHECK3-NEXT: call void @__cxx_global_var_init() 1686 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1687 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1688 // CHECK3-NEXT: ret void 1689 // 1690 // 1691 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 1692 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 1693 // CHECK5-NEXT: entry: 1694 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 1695 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 1696 // CHECK5-NEXT: ret void 1697 // 1698 // 1699 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1700 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 1701 // CHECK5-NEXT: entry: 1702 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1703 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1704 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1705 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1706 // CHECK5-NEXT: ret void 1707 // 1708 // 1709 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1710 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1711 // CHECK5-NEXT: entry: 1712 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1713 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1714 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1715 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1716 // CHECK5-NEXT: ret void 1717 // 1718 // 1719 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1720 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1721 // CHECK5-NEXT: entry: 1722 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1723 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1724 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1725 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1726 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1727 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1728 // CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4 1729 // CHECK5-NEXT: ret void 1730 // 1731 // 1732 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1733 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1734 // CHECK5-NEXT: entry: 1735 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1736 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1737 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1738 // CHECK5-NEXT: ret void 1739 // 1740 // 1741 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1742 // CHECK5-SAME: () #[[ATTR0]] { 1743 // CHECK5-NEXT: entry: 1744 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 1745 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 1746 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 1747 // CHECK5-NEXT: ret void 1748 // 1749 // 1750 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1751 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1752 // CHECK5-NEXT: entry: 1753 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1754 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1755 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1756 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1757 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1758 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1759 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1760 // CHECK5-NEXT: ret void 1761 // 1762 // 1763 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1764 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1765 // CHECK5-NEXT: entry: 1766 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1767 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1768 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1769 // CHECK5: arraydestroy.body: 1770 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1771 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1772 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1773 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1774 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1775 // CHECK5: arraydestroy.done1: 1776 // CHECK5-NEXT: ret void 1777 // 1778 // 1779 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1780 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1781 // CHECK5-NEXT: entry: 1782 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1783 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1784 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1785 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1786 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1787 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1788 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1789 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1790 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1791 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1792 // CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4 1793 // CHECK5-NEXT: ret void 1794 // 1795 // 1796 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1797 // CHECK5-SAME: () #[[ATTR0]] { 1798 // CHECK5-NEXT: entry: 1799 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1800 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1801 // CHECK5-NEXT: ret void 1802 // 1803 // 1804 // CHECK5-LABEL: define {{[^@]+}}@main 1805 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 1806 // CHECK5-NEXT: entry: 1807 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1808 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1809 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 1810 // CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 1811 // CHECK5-NEXT: ret i32 0 1812 // 1813 // 1814 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 1815 // CHECK5-SAME: () #[[ATTR4:[0-9]+]] { 1816 // CHECK5-NEXT: entry: 1817 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined) 1818 // CHECK5-NEXT: ret void 1819 // 1820 // 1821 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined 1822 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1823 // CHECK5-NEXT: entry: 1824 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1825 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1826 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1827 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1828 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1829 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1830 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1831 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1832 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1833 // CHECK5-NEXT: [[G:%.*]] = alloca i32, align 4 1834 // CHECK5-NEXT: [[G1:%.*]] = alloca i32, align 4 1835 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 1836 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1837 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1838 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1839 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1840 // CHECK5-NEXT: store ptr undef, ptr [[_TMP1]], align 8 1841 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1842 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1843 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1844 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1845 // CHECK5-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 8 1846 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1847 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1848 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1849 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1850 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1851 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1852 // CHECK5: cond.true: 1853 // CHECK5-NEXT: br label [[COND_END:%.*]] 1854 // CHECK5: cond.false: 1855 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1856 // CHECK5-NEXT: br label [[COND_END]] 1857 // CHECK5: cond.end: 1858 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1859 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1860 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1861 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1862 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1863 // CHECK5: omp.inner.for.cond: 1864 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]] 1865 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]] 1866 // CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1867 // CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1868 // CHECK5: omp.inner.for.body: 1869 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP4]] 1870 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 1871 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]] 1872 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 1873 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP4]] 1874 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1875 // CHECK5: omp.inner.for.inc: 1876 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 1877 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP4]] 1878 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 1879 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 1880 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 1881 // CHECK5: omp.inner.for.end: 1882 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1883 // CHECK5: omp.loop.exit: 1884 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1885 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1886 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1887 // CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1888 // CHECK5: .omp.final.then: 1889 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 1890 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 1891 // CHECK5: .omp.final.done: 1892 // CHECK5-NEXT: ret void 1893 // 1894 // 1895 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined.omp_outlined 1896 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 1897 // CHECK5-NEXT: entry: 1898 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1899 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1900 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1901 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1902 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1903 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1904 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1905 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1906 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1907 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1908 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1909 // CHECK5-NEXT: [[G:%.*]] = alloca i32, align 4 1910 // CHECK5-NEXT: [[G1:%.*]] = alloca i32, align 4 1911 // CHECK5-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 1912 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1913 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1914 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1915 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1916 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1917 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1918 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1919 // CHECK5-NEXT: store ptr undef, ptr [[_TMP1]], align 8 1920 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1921 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1922 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1923 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 1924 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1925 // CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 1926 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1927 // CHECK5-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 1928 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1929 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1930 // CHECK5-NEXT: store ptr [[G1]], ptr [[_TMP3]], align 8 1931 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1932 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1933 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1934 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1935 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 1936 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1937 // CHECK5: cond.true: 1938 // CHECK5-NEXT: br label [[COND_END:%.*]] 1939 // CHECK5: cond.false: 1940 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1941 // CHECK5-NEXT: br label [[COND_END]] 1942 // CHECK5: cond.end: 1943 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1944 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1945 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1946 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1947 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1948 // CHECK5: omp.inner.for.cond: 1949 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]] 1950 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]] 1951 // CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1952 // CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1953 // CHECK5: omp.inner.for.body: 1954 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 1955 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1956 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1957 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 1958 // CHECK5-NEXT: store i32 1, ptr [[G]], align 4, !llvm.access.group [[ACC_GRP8]] 1959 // CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !llvm.access.group [[ACC_GRP8]] 1960 // CHECK5-NEXT: store volatile i32 1, ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP8]] 1961 // CHECK5-NEXT: store i32 2, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP8]] 1962 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 1963 // CHECK5-NEXT: store ptr [[G]], ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP8]] 1964 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 1965 // CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8, !llvm.access.group [[ACC_GRP8]] 1966 // CHECK5-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP8]] 1967 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 1968 // CHECK5-NEXT: store ptr [[SIVAR]], ptr [[TMP14]], align 8, !llvm.access.group [[ACC_GRP8]] 1969 // CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group [[ACC_GRP8]] 1970 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1971 // CHECK5: omp.body.continue: 1972 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1973 // CHECK5: omp.inner.for.inc: 1974 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 1975 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 1976 // CHECK5-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 1977 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 1978 // CHECK5: omp.inner.for.end: 1979 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1980 // CHECK5: omp.loop.exit: 1981 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 1982 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1983 // CHECK5-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 1984 // CHECK5-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1985 // CHECK5: .omp.final.then: 1986 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 1987 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 1988 // CHECK5: .omp.final.done: 1989 // CHECK5-NEXT: ret void 1990 // 1991 // 1992 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_private_codegen.cpp 1993 // CHECK5-SAME: () #[[ATTR0]] { 1994 // CHECK5-NEXT: entry: 1995 // CHECK5-NEXT: call void @__cxx_global_var_init() 1996 // CHECK5-NEXT: call void @__cxx_global_var_init.1() 1997 // CHECK5-NEXT: call void @__cxx_global_var_init.2() 1998 // CHECK5-NEXT: ret void 1999 // 2000 // 2001 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init 2002 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 2003 // CHECK7-NEXT: entry: 2004 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 2005 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 2006 // CHECK7-NEXT: ret void 2007 // 2008 // 2009 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2010 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 2011 // CHECK7-NEXT: entry: 2012 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2013 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2014 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2015 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2016 // CHECK7-NEXT: ret void 2017 // 2018 // 2019 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2020 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2021 // CHECK7-NEXT: entry: 2022 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2023 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2024 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2025 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2026 // CHECK7-NEXT: ret void 2027 // 2028 // 2029 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2030 // CHECK7-SAME: () #[[ATTR0]] { 2031 // CHECK7-NEXT: entry: 2032 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 2033 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 2034 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 2035 // CHECK7-NEXT: ret void 2036 // 2037 // 2038 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2039 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2040 // CHECK7-NEXT: entry: 2041 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2042 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2043 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2044 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2045 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2046 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2047 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2048 // CHECK7-NEXT: ret void 2049 // 2050 // 2051 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2052 // CHECK7-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2053 // CHECK7-NEXT: entry: 2054 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2055 // CHECK7-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2056 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2057 // CHECK7: arraydestroy.body: 2058 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2059 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2060 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2061 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 2062 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2063 // CHECK7: arraydestroy.done1: 2064 // CHECK7-NEXT: ret void 2065 // 2066 // 2067 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2068 // CHECK7-SAME: () #[[ATTR0]] { 2069 // CHECK7-NEXT: entry: 2070 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2071 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 2072 // CHECK7-NEXT: ret void 2073 // 2074 // 2075 // CHECK7-LABEL: define {{[^@]+}}@main 2076 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] { 2077 // CHECK7-NEXT: entry: 2078 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2079 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 2080 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2081 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2082 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2083 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2084 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2085 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 2086 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2087 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 2088 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2089 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 2090 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2091 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2092 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2093 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 2094 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 2095 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 2096 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2097 // CHECK7: arrayctor.loop: 2098 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2099 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2100 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 2101 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2102 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2103 // CHECK7: arrayctor.cont: 2104 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 2105 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2106 // CHECK7: omp.inner.for.cond: 2107 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 2108 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 2109 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 2110 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2111 // CHECK7: omp.inner.for.cond.cleanup: 2112 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2113 // CHECK7: omp.inner.for.body: 2114 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 2115 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 2116 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2117 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 2118 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]] 2119 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 2120 // CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 2121 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 2122 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] 2123 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 2124 // CHECK7-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 2125 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM1]] 2126 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] 2127 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 2128 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] 2129 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] 2130 // CHECK7-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] 2131 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2132 // CHECK7: omp.body.continue: 2133 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2134 // CHECK7: omp.inner.for.inc: 2135 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 2136 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 2137 // CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 2138 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 2139 // CHECK7: omp.inner.for.end: 2140 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 2141 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 2142 // CHECK7-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 2143 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i64 2 2144 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2145 // CHECK7: arraydestroy.body: 2146 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2147 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2148 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2149 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 2150 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 2151 // CHECK7: arraydestroy.done6: 2152 // CHECK7-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 2153 // CHECK7-NEXT: ret i32 [[CALL]] 2154 // 2155 // 2156 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2157 // CHECK7-SAME: () #[[ATTR1]] comdat { 2158 // CHECK7-NEXT: entry: 2159 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2160 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2161 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2162 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2163 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2164 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 8 2165 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 2166 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 2167 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2168 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2169 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2170 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 2171 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 2172 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 2173 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 2174 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 2175 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2176 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 2177 // CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 4 2178 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 2179 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 2180 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 2181 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 2182 // CHECK7-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 2183 // CHECK7-NEXT: store ptr undef, ptr [[_TMP1]], align 8 2184 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2185 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2186 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2187 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 2188 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 2189 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 2190 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2191 // CHECK7: arrayctor.loop: 2192 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2193 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2194 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 2195 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2196 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2197 // CHECK7: arrayctor.cont: 2198 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 2199 // CHECK7-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 8 2200 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2201 // CHECK7: omp.inner.for.cond: 2202 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 2203 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 2204 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 2205 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2206 // CHECK7: omp.inner.for.cond.cleanup: 2207 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2208 // CHECK7: omp.inner.for.body: 2209 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 2210 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 2211 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2212 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 2213 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP6]] 2214 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 2215 // CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 2216 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] 2217 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] 2218 // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP6]] 2219 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 2220 // CHECK7-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 2221 // CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] 2222 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] 2223 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2224 // CHECK7: omp.body.continue: 2225 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2226 // CHECK7: omp.inner.for.inc: 2227 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 2228 // CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1 2229 // CHECK7-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 2230 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 2231 // CHECK7: omp.inner.for.end: 2232 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 2233 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 2234 // CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 2235 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 2236 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2237 // CHECK7: arraydestroy.body: 2238 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2239 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2240 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2241 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 2242 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 2243 // CHECK7: arraydestroy.done11: 2244 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 2245 // CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 2246 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 2247 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] 2248 // CHECK7: arraydestroy.body13: 2249 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] 2250 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 2251 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] 2252 // CHECK7-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] 2253 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] 2254 // CHECK7: arraydestroy.done17: 2255 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 2256 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 2257 // CHECK7-NEXT: ret i32 [[TMP11]] 2258 // 2259 // 2260 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2261 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2262 // CHECK7-NEXT: entry: 2263 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2264 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2265 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2266 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2267 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2268 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2269 // CHECK7-NEXT: store float [[CONV]], ptr [[F]], align 4 2270 // CHECK7-NEXT: ret void 2271 // 2272 // 2273 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2274 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2275 // CHECK7-NEXT: entry: 2276 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2277 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2278 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2279 // CHECK7-NEXT: ret void 2280 // 2281 // 2282 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2283 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2284 // CHECK7-NEXT: entry: 2285 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2286 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2287 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2288 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2289 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2290 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2291 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2292 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2293 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2294 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2295 // CHECK7-NEXT: store float [[ADD]], ptr [[F]], align 4 2296 // CHECK7-NEXT: ret void 2297 // 2298 // 2299 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2300 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2301 // CHECK7-NEXT: entry: 2302 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2303 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2304 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2305 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2306 // CHECK7-NEXT: ret void 2307 // 2308 // 2309 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2310 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2311 // CHECK7-NEXT: entry: 2312 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2313 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2314 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2315 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2316 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2317 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2318 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 2319 // CHECK7-NEXT: ret void 2320 // 2321 // 2322 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2323 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2324 // CHECK7-NEXT: entry: 2325 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2326 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2327 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2328 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2329 // CHECK7-NEXT: ret void 2330 // 2331 // 2332 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2333 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2334 // CHECK7-NEXT: entry: 2335 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2336 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2337 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2338 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2339 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2340 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 2341 // CHECK7-NEXT: ret void 2342 // 2343 // 2344 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2345 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2346 // CHECK7-NEXT: entry: 2347 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2348 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2349 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2350 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2351 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2352 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2353 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2354 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2355 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2356 // CHECK7-NEXT: store i32 [[ADD]], ptr [[F]], align 4 2357 // CHECK7-NEXT: ret void 2358 // 2359 // 2360 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2361 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2362 // CHECK7-NEXT: entry: 2363 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2364 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2365 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2366 // CHECK7-NEXT: ret void 2367 // 2368 // 2369 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_private_codegen.cpp 2370 // CHECK7-SAME: () #[[ATTR0]] { 2371 // CHECK7-NEXT: entry: 2372 // CHECK7-NEXT: call void @__cxx_global_var_init() 2373 // CHECK7-NEXT: call void @__cxx_global_var_init.1() 2374 // CHECK7-NEXT: call void @__cxx_global_var_init.2() 2375 // CHECK7-NEXT: ret void 2376 // 2377 // 2378 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 2379 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 2380 // CHECK9-NEXT: entry: 2381 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 2382 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 2383 // CHECK9-NEXT: ret void 2384 // 2385 // 2386 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2387 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2388 // CHECK9-NEXT: entry: 2389 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2390 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2391 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2392 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2393 // CHECK9-NEXT: ret void 2394 // 2395 // 2396 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2397 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2398 // CHECK9-NEXT: entry: 2399 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2400 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2401 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2402 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2403 // CHECK9-NEXT: ret void 2404 // 2405 // 2406 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2407 // CHECK9-SAME: () #[[ATTR0]] { 2408 // CHECK9-NEXT: entry: 2409 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 2410 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 2411 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 2412 // CHECK9-NEXT: ret void 2413 // 2414 // 2415 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2416 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2417 // CHECK9-NEXT: entry: 2418 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2419 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2420 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2421 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2422 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2423 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2424 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2425 // CHECK9-NEXT: ret void 2426 // 2427 // 2428 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2429 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2430 // CHECK9-NEXT: entry: 2431 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 2432 // CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 2433 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2434 // CHECK9: arraydestroy.body: 2435 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2436 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2437 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2438 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 2439 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2440 // CHECK9: arraydestroy.done1: 2441 // CHECK9-NEXT: ret void 2442 // 2443 // 2444 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2445 // CHECK9-SAME: () #[[ATTR0]] { 2446 // CHECK9-NEXT: entry: 2447 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2448 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 2449 // CHECK9-NEXT: ret void 2450 // 2451 // 2452 // CHECK9-LABEL: define {{[^@]+}}@main 2453 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 2454 // CHECK9-NEXT: entry: 2455 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2456 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 2457 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2458 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2459 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2460 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2461 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2462 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 2463 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2464 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 2465 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 2466 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 2467 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2468 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2469 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2470 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 2471 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 2472 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 2473 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2474 // CHECK9: arrayctor.loop: 2475 // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2476 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2477 // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 2478 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2479 // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2480 // CHECK9: arrayctor.cont: 2481 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 2482 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2483 // CHECK9: omp.inner.for.cond: 2484 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 2485 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 2486 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 2487 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2488 // CHECK9: omp.inner.for.cond.cleanup: 2489 // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2490 // CHECK9: omp.inner.for.body: 2491 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 2492 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 2493 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2494 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 2495 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP3]] 2496 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 2497 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP5]] 2498 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] 2499 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 2500 // CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP6]] 2501 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] 2502 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 2503 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] 2504 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] 2505 // CHECK9-NEXT: store i32 [[ADD2]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] 2506 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2507 // CHECK9: omp.body.continue: 2508 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2509 // CHECK9: omp.inner.for.inc: 2510 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 2511 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 2512 // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 2513 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 2514 // CHECK9: omp.inner.for.end: 2515 // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 2516 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 2517 // CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 2518 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i32 2 2519 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2520 // CHECK9: arraydestroy.body: 2521 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2522 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2523 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2524 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 2525 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 2526 // CHECK9: arraydestroy.done5: 2527 // CHECK9-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 2528 // CHECK9-NEXT: ret i32 [[CALL]] 2529 // 2530 // 2531 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2532 // CHECK9-SAME: () #[[ATTR1]] comdat { 2533 // CHECK9-NEXT: entry: 2534 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2535 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2536 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2537 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2538 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2539 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 4 2540 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 2541 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 2542 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2543 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2544 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2545 // CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 2546 // CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 2547 // CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 2548 // CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 2549 // CHECK9-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 2550 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 2551 // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 2552 // CHECK9-NEXT: store i32 0, ptr [[T_VAR]], align 4 2553 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 2554 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 2555 // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 2556 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 2557 // CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 2558 // CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 4 2559 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2560 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2561 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2562 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 2563 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 2564 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 2565 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2566 // CHECK9: arrayctor.loop: 2567 // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2568 // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2569 // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 2570 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2571 // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2572 // CHECK9: arrayctor.cont: 2573 // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 2574 // CHECK9-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 2575 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2576 // CHECK9: omp.inner.for.cond: 2577 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 2578 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]] 2579 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 2580 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2581 // CHECK9: omp.inner.for.cond.cleanup: 2582 // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2583 // CHECK9: omp.inner.for.body: 2584 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 2585 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 2586 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2587 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 2588 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP7]] 2589 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 2590 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP5]] 2591 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] 2592 // CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP7]] 2593 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 2594 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] 2595 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] 2596 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2597 // CHECK9: omp.body.continue: 2598 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2599 // CHECK9: omp.inner.for.inc: 2600 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 2601 // CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 2602 // CHECK9-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 2603 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 2604 // CHECK9: omp.inner.for.end: 2605 // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 2606 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 2607 // CHECK9-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 2608 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 2609 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2610 // CHECK9: arraydestroy.body: 2611 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2612 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2613 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2614 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] 2615 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] 2616 // CHECK9: arraydestroy.done10: 2617 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 2618 // CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 2619 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 2620 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]] 2621 // CHECK9: arraydestroy.body12: 2622 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] 2623 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 2624 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] 2625 // CHECK9-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] 2626 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] 2627 // CHECK9: arraydestroy.done16: 2628 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 2629 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 2630 // CHECK9-NEXT: ret i32 [[TMP11]] 2631 // 2632 // 2633 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2634 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2635 // CHECK9-NEXT: entry: 2636 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2637 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2638 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2639 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2640 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2641 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2642 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 2643 // CHECK9-NEXT: ret void 2644 // 2645 // 2646 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2647 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2648 // CHECK9-NEXT: entry: 2649 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2650 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2651 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2652 // CHECK9-NEXT: ret void 2653 // 2654 // 2655 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2656 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2657 // CHECK9-NEXT: entry: 2658 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2659 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2660 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2661 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2662 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2663 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2664 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2665 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2666 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2667 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2668 // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 2669 // CHECK9-NEXT: ret void 2670 // 2671 // 2672 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2673 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2674 // CHECK9-NEXT: entry: 2675 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2676 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2677 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2678 // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2679 // CHECK9-NEXT: ret void 2680 // 2681 // 2682 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2683 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2684 // CHECK9-NEXT: entry: 2685 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2686 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2687 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2688 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2689 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2690 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2691 // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 2692 // CHECK9-NEXT: ret void 2693 // 2694 // 2695 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2696 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2697 // CHECK9-NEXT: entry: 2698 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2699 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2700 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2701 // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2702 // CHECK9-NEXT: ret void 2703 // 2704 // 2705 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2706 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2707 // CHECK9-NEXT: entry: 2708 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2709 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2710 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2711 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2712 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2713 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 2714 // CHECK9-NEXT: ret void 2715 // 2716 // 2717 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2718 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2719 // CHECK9-NEXT: entry: 2720 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2721 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2722 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2723 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2724 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2725 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2726 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2727 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2728 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2729 // CHECK9-NEXT: store i32 [[ADD]], ptr [[F]], align 4 2730 // CHECK9-NEXT: ret void 2731 // 2732 // 2733 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2734 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2735 // CHECK9-NEXT: entry: 2736 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2737 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2738 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2739 // CHECK9-NEXT: ret void 2740 // 2741 // 2742 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_private_codegen.cpp 2743 // CHECK9-SAME: () #[[ATTR0]] { 2744 // CHECK9-NEXT: entry: 2745 // CHECK9-NEXT: call void @__cxx_global_var_init() 2746 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 2747 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 2748 // CHECK9-NEXT: ret void 2749 // 2750 // 2751 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init 2752 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 2753 // CHECK11-NEXT: entry: 2754 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 2755 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 2756 // CHECK11-NEXT: ret void 2757 // 2758 // 2759 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2760 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 2761 // CHECK11-NEXT: entry: 2762 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2763 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2764 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2765 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2766 // CHECK11-NEXT: ret void 2767 // 2768 // 2769 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2770 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2771 // CHECK11-NEXT: entry: 2772 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2773 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2774 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2775 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2776 // CHECK11-NEXT: ret void 2777 // 2778 // 2779 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2780 // CHECK11-SAME: () #[[ATTR0]] { 2781 // CHECK11-NEXT: entry: 2782 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 2783 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 2784 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 2785 // CHECK11-NEXT: ret void 2786 // 2787 // 2788 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2789 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2790 // CHECK11-NEXT: entry: 2791 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2792 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2793 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2794 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2795 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2796 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2797 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2798 // CHECK11-NEXT: ret void 2799 // 2800 // 2801 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2802 // CHECK11-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2803 // CHECK11-NEXT: entry: 2804 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2805 // CHECK11-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2806 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2807 // CHECK11: arraydestroy.body: 2808 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2809 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2810 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2811 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 2812 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2813 // CHECK11: arraydestroy.done1: 2814 // CHECK11-NEXT: ret void 2815 // 2816 // 2817 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2818 // CHECK11-SAME: () #[[ATTR0]] { 2819 // CHECK11-NEXT: entry: 2820 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2821 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 2822 // CHECK11-NEXT: ret void 2823 // 2824 // 2825 // CHECK11-LABEL: define {{[^@]+}}@main 2826 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 2827 // CHECK11-NEXT: entry: 2828 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2829 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2830 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 2831 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2832 // CHECK11-NEXT: ret i32 0 2833 // 2834 // 2835 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2836 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2837 // CHECK11-NEXT: entry: 2838 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2839 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2840 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2841 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2842 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2843 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2844 // CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4 2845 // CHECK11-NEXT: ret void 2846 // 2847 // 2848 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2849 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2850 // CHECK11-NEXT: entry: 2851 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2852 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2853 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2854 // CHECK11-NEXT: ret void 2855 // 2856 // 2857 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2858 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2859 // CHECK11-NEXT: entry: 2860 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2861 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2862 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2863 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2864 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2865 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2866 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2867 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2868 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2869 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2870 // CHECK11-NEXT: store float [[ADD]], ptr [[F]], align 4 2871 // CHECK11-NEXT: ret void 2872 // 2873 // 2874 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_private_codegen.cpp 2875 // CHECK11-SAME: () #[[ATTR0]] { 2876 // CHECK11-NEXT: entry: 2877 // CHECK11-NEXT: call void @__cxx_global_var_init() 2878 // CHECK11-NEXT: call void @__cxx_global_var_init.1() 2879 // CHECK11-NEXT: call void @__cxx_global_var_init.2() 2880 // CHECK11-NEXT: ret void 2881 // 2882 // 2883 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 2884 // CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { 2885 // CHECK13-NEXT: entry: 2886 // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 2887 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 2888 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) 2889 // CHECK13-NEXT: ret void 2890 // 2891 // 2892 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined 2893 // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2894 // CHECK13-NEXT: entry: 2895 // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2896 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2897 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2898 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 2899 // CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2900 // CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2901 // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2902 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2903 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2904 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2905 // CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 2906 // CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2907 // CHECK13-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 2908 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 2909 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2910 // CHECK13-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2911 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 2912 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 2913 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2914 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2915 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 2916 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 2917 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2918 // CHECK13: arrayctor.loop: 2919 // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2920 // CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2921 // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 2922 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2923 // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2924 // CHECK13: arrayctor.cont: 2925 // CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 2926 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2927 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2928 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2929 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2930 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 2931 // CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2932 // CHECK13: cond.true: 2933 // CHECK13-NEXT: br label [[COND_END:%.*]] 2934 // CHECK13: cond.false: 2935 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2936 // CHECK13-NEXT: br label [[COND_END]] 2937 // CHECK13: cond.end: 2938 // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2939 // CHECK13-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2940 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2941 // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2942 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2943 // CHECK13: omp.inner.for.cond: 2944 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 2945 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 2946 // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2947 // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2948 // CHECK13: omp.inner.for.cond.cleanup: 2949 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2950 // CHECK13: omp.inner.for.body: 2951 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP6]] 2952 // CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 2953 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 2954 // CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 2955 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP6]] 2956 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2957 // CHECK13: omp.inner.for.inc: 2958 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 2959 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP6]] 2960 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 2961 // CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 2962 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 2963 // CHECK13: omp.inner.for.end: 2964 // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2965 // CHECK13: omp.loop.exit: 2966 // CHECK13-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2967 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 2968 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 2969 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2970 // CHECK13-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 2971 // CHECK13-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2972 // CHECK13: .omp.final.then: 2973 // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 2974 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] 2975 // CHECK13: .omp.final.done: 2976 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2:[0-9]+]] 2977 // CHECK13-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 2978 // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2 2979 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2980 // CHECK13: arraydestroy.body: 2981 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2982 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2983 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2984 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 2985 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 2986 // CHECK13: arraydestroy.done3: 2987 // CHECK13-NEXT: ret void 2988 // 2989 // 2990 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2991 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 2992 // CHECK13-NEXT: entry: 2993 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2994 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2995 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2996 // CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2997 // CHECK13-NEXT: ret void 2998 // 2999 // 3000 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined 3001 // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { 3002 // CHECK13-NEXT: entry: 3003 // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3004 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3005 // CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 3006 // CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 3007 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3008 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 3009 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3010 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3011 // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3012 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3013 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3014 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3015 // CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 3016 // CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 3017 // CHECK13-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 3018 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 3019 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3020 // CHECK13-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3021 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 3022 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 3023 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3024 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 3025 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 3026 // CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 3027 // CHECK13-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 3028 // CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 3029 // CHECK13-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 3030 // CHECK13-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 3031 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3032 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3033 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 3034 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 3035 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 3036 // CHECK13: arrayctor.loop: 3037 // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 3038 // CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 3039 // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 3040 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 3041 // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 3042 // CHECK13: arrayctor.cont: 3043 // CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 3044 // CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3045 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 3046 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3047 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3048 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 3049 // CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3050 // CHECK13: cond.true: 3051 // CHECK13-NEXT: br label [[COND_END:%.*]] 3052 // CHECK13: cond.false: 3053 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3054 // CHECK13-NEXT: br label [[COND_END]] 3055 // CHECK13: cond.end: 3056 // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 3057 // CHECK13-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3058 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3059 // CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 3060 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3061 // CHECK13: omp.inner.for.cond: 3062 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 3063 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 3064 // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 3065 // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3066 // CHECK13: omp.inner.for.cond.cleanup: 3067 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3068 // CHECK13: omp.inner.for.body: 3069 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 3070 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 3071 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3072 // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 3073 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP10]] 3074 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 3075 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 3076 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 3077 // CHECK13-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] 3078 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 3079 // CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 3080 // CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] 3081 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP10]] 3082 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 3083 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP10]] 3084 // CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 3085 // CHECK13-NEXT: store i32 [[ADD5]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP10]] 3086 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3087 // CHECK13: omp.body.continue: 3088 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3089 // CHECK13: omp.inner.for.inc: 3090 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 3091 // CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP15]], 1 3092 // CHECK13-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 3093 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 3094 // CHECK13: omp.inner.for.end: 3095 // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3096 // CHECK13: omp.loop.exit: 3097 // CHECK13-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3098 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 3099 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) 3100 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3101 // CHECK13-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 3102 // CHECK13-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3103 // CHECK13: .omp.final.then: 3104 // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 3105 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] 3106 // CHECK13: .omp.final.done: 3107 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 3108 // CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 3109 // CHECK13-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 3110 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3111 // CHECK13: arraydestroy.body: 3112 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3113 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3114 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3115 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 3116 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 3117 // CHECK13: arraydestroy.done8: 3118 // CHECK13-NEXT: ret void 3119 // 3120 // 3121 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3122 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3123 // CHECK13-NEXT: entry: 3124 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3125 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3126 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3127 // CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3128 // CHECK13-NEXT: ret void 3129 // 3130 // 3131 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 3132 // CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { 3133 // CHECK13-NEXT: entry: 3134 // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 3135 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 3136 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) 3137 // CHECK13-NEXT: ret void 3138 // 3139 // 3140 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined 3141 // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 3142 // CHECK13-NEXT: entry: 3143 // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3144 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3145 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3146 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 3147 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 3148 // CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 3149 // CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 3150 // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3151 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3152 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3153 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3154 // CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 3155 // CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3156 // CHECK13-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 3157 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 3158 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3159 // CHECK13-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3160 // CHECK13-NEXT: store ptr undef, ptr [[_TMP1]], align 8 3161 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 3162 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 3163 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3164 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3165 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 3166 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 3167 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 3168 // CHECK13: arrayctor.loop: 3169 // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 3170 // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 3171 // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 3172 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 3173 // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 3174 // CHECK13: arrayctor.cont: 3175 // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 3176 // CHECK13-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 8 3177 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3178 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 3179 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3180 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3181 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 3182 // CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3183 // CHECK13: cond.true: 3184 // CHECK13-NEXT: br label [[COND_END:%.*]] 3185 // CHECK13: cond.false: 3186 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3187 // CHECK13-NEXT: br label [[COND_END]] 3188 // CHECK13: cond.end: 3189 // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3190 // CHECK13-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 3191 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 3192 // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 3193 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3194 // CHECK13: omp.inner.for.cond: 3195 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] 3196 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 3197 // CHECK13-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3198 // CHECK13-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3199 // CHECK13: omp.inner.for.cond.cleanup: 3200 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3201 // CHECK13: omp.inner.for.body: 3202 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]] 3203 // CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 3204 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 3205 // CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 3206 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP15]] 3207 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3208 // CHECK13: omp.inner.for.inc: 3209 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 3210 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]] 3211 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 3212 // CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 3213 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 3214 // CHECK13: omp.inner.for.end: 3215 // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3216 // CHECK13: omp.loop.exit: 3217 // CHECK13-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3218 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 3219 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 3220 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3221 // CHECK13-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 3222 // CHECK13-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3223 // CHECK13: .omp.final.then: 3224 // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 3225 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] 3226 // CHECK13: .omp.final.done: 3227 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 3228 // CHECK13-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 3229 // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2 3230 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3231 // CHECK13: arraydestroy.body: 3232 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3233 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3234 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3235 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 3236 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 3237 // CHECK13: arraydestroy.done5: 3238 // CHECK13-NEXT: ret void 3239 // 3240 // 3241 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3242 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3243 // CHECK13-NEXT: entry: 3244 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3245 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3246 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3247 // CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 3248 // CHECK13-NEXT: ret void 3249 // 3250 // 3251 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined 3252 // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { 3253 // CHECK13-NEXT: entry: 3254 // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3255 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3256 // CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 3257 // CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 3258 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3259 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 3260 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 3261 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3262 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3263 // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3264 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3265 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3266 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3267 // CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 3268 // CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3269 // CHECK13-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 3270 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 3271 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3272 // CHECK13-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3273 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 3274 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 3275 // CHECK13-NEXT: store ptr undef, ptr [[_TMP1]], align 8 3276 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3277 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 3278 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 3279 // CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 3280 // CHECK13-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 3281 // CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 3282 // CHECK13-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 3283 // CHECK13-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 3284 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3285 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3286 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 3287 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 3288 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 3289 // CHECK13: arrayctor.loop: 3290 // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 3291 // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 3292 // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 3293 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 3294 // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 3295 // CHECK13: arrayctor.cont: 3296 // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 3297 // CHECK13-NEXT: store ptr [[VAR]], ptr [[_TMP3]], align 8 3298 // CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3299 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 3300 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3301 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3302 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 3303 // CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3304 // CHECK13: cond.true: 3305 // CHECK13-NEXT: br label [[COND_END:%.*]] 3306 // CHECK13: cond.false: 3307 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3308 // CHECK13-NEXT: br label [[COND_END]] 3309 // CHECK13: cond.end: 3310 // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 3311 // CHECK13-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3312 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3313 // CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 3314 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3315 // CHECK13: omp.inner.for.cond: 3316 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] 3317 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] 3318 // CHECK13-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 3319 // CHECK13-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3320 // CHECK13: omp.inner.for.cond.cleanup: 3321 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3322 // CHECK13: omp.inner.for.body: 3323 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 3324 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 3325 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3326 // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 3327 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP18]] 3328 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 3329 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 3330 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 3331 // CHECK13-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] 3332 // CHECK13-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !llvm.access.group [[ACC_GRP18]] 3333 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 3334 // CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 3335 // CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] 3336 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group [[ACC_GRP18]] 3337 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3338 // CHECK13: omp.body.continue: 3339 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3340 // CHECK13: omp.inner.for.inc: 3341 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 3342 // CHECK13-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP14]], 1 3343 // CHECK13-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 3344 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 3345 // CHECK13: omp.inner.for.end: 3346 // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3347 // CHECK13: omp.loop.exit: 3348 // CHECK13-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3349 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 3350 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) 3351 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3352 // CHECK13-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 3353 // CHECK13-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3354 // CHECK13: .omp.final.then: 3355 // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 3356 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] 3357 // CHECK13: .omp.final.done: 3358 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 3359 // CHECK13-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 3360 // CHECK13-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 3361 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3362 // CHECK13: arraydestroy.body: 3363 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3364 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3365 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3366 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 3367 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 3368 // CHECK13: arraydestroy.done9: 3369 // CHECK13-NEXT: ret void 3370 // 3371 // 3372 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3373 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3374 // CHECK13-NEXT: entry: 3375 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3376 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3377 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3378 // CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3379 // CHECK13-NEXT: ret void 3380 // 3381 // 3382 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3383 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3384 // CHECK13-NEXT: entry: 3385 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3386 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3387 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3388 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 3389 // CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 3390 // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3391 // CHECK13-NEXT: store float [[CONV]], ptr [[F]], align 4 3392 // CHECK13-NEXT: ret void 3393 // 3394 // 3395 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3396 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3397 // CHECK13-NEXT: entry: 3398 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3399 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3400 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3401 // CHECK13-NEXT: ret void 3402 // 3403 // 3404 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3405 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3406 // CHECK13-NEXT: entry: 3407 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3408 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3409 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3410 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 3411 // CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 3412 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 3413 // CHECK13-NEXT: ret void 3414 // 3415 // 3416 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3417 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3418 // CHECK13-NEXT: entry: 3419 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3420 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3421 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3422 // CHECK13-NEXT: ret void 3423 // 3424 // 3425 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 3426 // CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { 3427 // CHECK15-NEXT: entry: 3428 // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 3429 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 3430 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) 3431 // CHECK15-NEXT: ret void 3432 // 3433 // 3434 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined 3435 // CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 3436 // CHECK15-NEXT: entry: 3437 // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3438 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3439 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3440 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 3441 // CHECK15-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 3442 // CHECK15-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 3443 // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3444 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3445 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3446 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3447 // CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 3448 // CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 3449 // CHECK15-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 3450 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 3451 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3452 // CHECK15-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3453 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 3454 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 3455 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3456 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3457 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 3458 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 3459 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 3460 // CHECK15: arrayctor.loop: 3461 // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 3462 // CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 3463 // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 3464 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 3465 // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 3466 // CHECK15: arrayctor.cont: 3467 // CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 3468 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3469 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 3470 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3471 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3472 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 3473 // CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3474 // CHECK15: cond.true: 3475 // CHECK15-NEXT: br label [[COND_END:%.*]] 3476 // CHECK15: cond.false: 3477 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3478 // CHECK15-NEXT: br label [[COND_END]] 3479 // CHECK15: cond.end: 3480 // CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3481 // CHECK15-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 3482 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 3483 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 3484 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3485 // CHECK15: omp.inner.for.cond: 3486 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 3487 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP7]] 3488 // CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3489 // CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3490 // CHECK15: omp.inner.for.cond.cleanup: 3491 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3492 // CHECK15: omp.inner.for.body: 3493 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP7]] 3494 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP7]] 3495 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP7]] 3496 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3497 // CHECK15: omp.inner.for.inc: 3498 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 3499 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP7]] 3500 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] 3501 // CHECK15-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 3502 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 3503 // CHECK15: omp.inner.for.end: 3504 // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3505 // CHECK15: omp.loop.exit: 3506 // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3507 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 3508 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) 3509 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3510 // CHECK15-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 3511 // CHECK15-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3512 // CHECK15: .omp.final.then: 3513 // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 3514 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] 3515 // CHECK15: .omp.final.done: 3516 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2:[0-9]+]] 3517 // CHECK15-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 3518 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i32 2 3519 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3520 // CHECK15: arraydestroy.body: 3521 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3522 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3523 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3524 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 3525 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 3526 // CHECK15: arraydestroy.done3: 3527 // CHECK15-NEXT: ret void 3528 // 3529 // 3530 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3531 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3532 // CHECK15-NEXT: entry: 3533 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3534 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3535 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3536 // CHECK15-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 3537 // CHECK15-NEXT: ret void 3538 // 3539 // 3540 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined 3541 // CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { 3542 // CHECK15-NEXT: entry: 3543 // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3544 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3545 // CHECK15-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 3546 // CHECK15-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 3547 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3548 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 3549 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3550 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3551 // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3552 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3553 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3554 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3555 // CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 3556 // CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 3557 // CHECK15-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 3558 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 3559 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3560 // CHECK15-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3561 // CHECK15-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 3562 // CHECK15-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 3563 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3564 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 3565 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 3566 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 3567 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4 3568 // CHECK15-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 3569 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3570 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3571 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 3572 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 3573 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 3574 // CHECK15: arrayctor.loop: 3575 // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 3576 // CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 3577 // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 3578 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 3579 // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 3580 // CHECK15: arrayctor.cont: 3581 // CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 3582 // CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3583 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 3584 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3585 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3586 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 3587 // CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3588 // CHECK15: cond.true: 3589 // CHECK15-NEXT: br label [[COND_END:%.*]] 3590 // CHECK15: cond.false: 3591 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3592 // CHECK15-NEXT: br label [[COND_END]] 3593 // CHECK15: cond.end: 3594 // CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 3595 // CHECK15-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3596 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3597 // CHECK15-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 3598 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3599 // CHECK15: omp.inner.for.cond: 3600 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 3601 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 3602 // CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 3603 // CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3604 // CHECK15: omp.inner.for.cond.cleanup: 3605 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3606 // CHECK15: omp.inner.for.body: 3607 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 3608 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 3609 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3610 // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 3611 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP11]] 3612 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 3613 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] 3614 // CHECK15-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] 3615 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 3616 // CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]] 3617 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP11]] 3618 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 3619 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP11]] 3620 // CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 3621 // CHECK15-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP11]] 3622 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3623 // CHECK15: omp.body.continue: 3624 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3625 // CHECK15: omp.inner.for.inc: 3626 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 3627 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 3628 // CHECK15-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 3629 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 3630 // CHECK15: omp.inner.for.end: 3631 // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3632 // CHECK15: omp.loop.exit: 3633 // CHECK15-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3634 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 3635 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) 3636 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3637 // CHECK15-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 3638 // CHECK15-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3639 // CHECK15: .omp.final.then: 3640 // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 3641 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] 3642 // CHECK15: .omp.final.done: 3643 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 3644 // CHECK15-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 3645 // CHECK15-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 3646 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3647 // CHECK15: arraydestroy.body: 3648 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3649 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3650 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3651 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 3652 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 3653 // CHECK15: arraydestroy.done6: 3654 // CHECK15-NEXT: ret void 3655 // 3656 // 3657 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3658 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3659 // CHECK15-NEXT: entry: 3660 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3661 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3662 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3663 // CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3664 // CHECK15-NEXT: ret void 3665 // 3666 // 3667 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 3668 // CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { 3669 // CHECK15-NEXT: entry: 3670 // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 3671 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 3672 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) 3673 // CHECK15-NEXT: ret void 3674 // 3675 // 3676 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined 3677 // CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 3678 // CHECK15-NEXT: entry: 3679 // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3680 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3681 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3682 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 3683 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 3684 // CHECK15-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 3685 // CHECK15-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 3686 // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3687 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3688 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3689 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3690 // CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 3691 // CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3692 // CHECK15-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 3693 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 3694 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3695 // CHECK15-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3696 // CHECK15-NEXT: store ptr undef, ptr [[_TMP1]], align 4 3697 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 3698 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 3699 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3700 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3701 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 3702 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 3703 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 3704 // CHECK15: arrayctor.loop: 3705 // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 3706 // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 3707 // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 3708 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 3709 // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 3710 // CHECK15: arrayctor.cont: 3711 // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 3712 // CHECK15-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 4 3713 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3714 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 3715 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3716 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3717 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 3718 // CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3719 // CHECK15: cond.true: 3720 // CHECK15-NEXT: br label [[COND_END:%.*]] 3721 // CHECK15: cond.false: 3722 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3723 // CHECK15-NEXT: br label [[COND_END]] 3724 // CHECK15: cond.end: 3725 // CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3726 // CHECK15-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 3727 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 3728 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 3729 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3730 // CHECK15: omp.inner.for.cond: 3731 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] 3732 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP16]] 3733 // CHECK15-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3734 // CHECK15-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3735 // CHECK15: omp.inner.for.cond.cleanup: 3736 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3737 // CHECK15: omp.inner.for.body: 3738 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP16]] 3739 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP16]] 3740 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP16]] 3741 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3742 // CHECK15: omp.inner.for.inc: 3743 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] 3744 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP16]] 3745 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] 3746 // CHECK15-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] 3747 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] 3748 // CHECK15: omp.inner.for.end: 3749 // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3750 // CHECK15: omp.loop.exit: 3751 // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3752 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 3753 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) 3754 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3755 // CHECK15-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 3756 // CHECK15-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3757 // CHECK15: .omp.final.then: 3758 // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 3759 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] 3760 // CHECK15: .omp.final.done: 3761 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 3762 // CHECK15-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 3763 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2 3764 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3765 // CHECK15: arraydestroy.body: 3766 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3767 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3768 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3769 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 3770 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 3771 // CHECK15: arraydestroy.done5: 3772 // CHECK15-NEXT: ret void 3773 // 3774 // 3775 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3776 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3777 // CHECK15-NEXT: entry: 3778 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3779 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3780 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3781 // CHECK15-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 3782 // CHECK15-NEXT: ret void 3783 // 3784 // 3785 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined 3786 // CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { 3787 // CHECK15-NEXT: entry: 3788 // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3789 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3790 // CHECK15-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 3791 // CHECK15-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 3792 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3793 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 3794 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 3795 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3796 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3797 // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3798 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3799 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3800 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3801 // CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 3802 // CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3803 // CHECK15-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 3804 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 3805 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3806 // CHECK15-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3807 // CHECK15-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 3808 // CHECK15-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 3809 // CHECK15-NEXT: store ptr undef, ptr [[_TMP1]], align 4 3810 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3811 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 3812 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 3813 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 3814 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4 3815 // CHECK15-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 3816 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3817 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3818 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 3819 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 3820 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 3821 // CHECK15: arrayctor.loop: 3822 // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 3823 // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 3824 // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 3825 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 3826 // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 3827 // CHECK15: arrayctor.cont: 3828 // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 3829 // CHECK15-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 4 3830 // CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3831 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 3832 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3833 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3834 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 3835 // CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3836 // CHECK15: cond.true: 3837 // CHECK15-NEXT: br label [[COND_END:%.*]] 3838 // CHECK15: cond.false: 3839 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3840 // CHECK15-NEXT: br label [[COND_END]] 3841 // CHECK15: cond.end: 3842 // CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 3843 // CHECK15-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3844 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3845 // CHECK15-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 3846 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3847 // CHECK15: omp.inner.for.cond: 3848 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] 3849 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] 3850 // CHECK15-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 3851 // CHECK15-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3852 // CHECK15: omp.inner.for.cond.cleanup: 3853 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3854 // CHECK15: omp.inner.for.body: 3855 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] 3856 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 3857 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3858 // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 3859 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP19]] 3860 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 3861 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] 3862 // CHECK15-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] 3863 // CHECK15-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP19]] 3864 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 3865 // CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] 3866 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group [[ACC_GRP19]] 3867 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3868 // CHECK15: omp.body.continue: 3869 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3870 // CHECK15: omp.inner.for.inc: 3871 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] 3872 // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 3873 // CHECK15-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] 3874 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 3875 // CHECK15: omp.inner.for.end: 3876 // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3877 // CHECK15: omp.loop.exit: 3878 // CHECK15-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3879 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 3880 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) 3881 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3882 // CHECK15-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 3883 // CHECK15-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3884 // CHECK15: .omp.final.then: 3885 // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 3886 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] 3887 // CHECK15: .omp.final.done: 3888 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 3889 // CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 3890 // CHECK15-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 3891 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3892 // CHECK15: arraydestroy.body: 3893 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3894 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3895 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3896 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 3897 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 3898 // CHECK15: arraydestroy.done7: 3899 // CHECK15-NEXT: ret void 3900 // 3901 // 3902 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3903 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3904 // CHECK15-NEXT: entry: 3905 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3906 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3907 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3908 // CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3909 // CHECK15-NEXT: ret void 3910 // 3911 // 3912 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3913 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3914 // CHECK15-NEXT: entry: 3915 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3916 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3917 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3918 // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 3919 // CHECK15-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 3920 // CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3921 // CHECK15-NEXT: store float [[CONV]], ptr [[F]], align 4 3922 // CHECK15-NEXT: ret void 3923 // 3924 // 3925 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3926 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3927 // CHECK15-NEXT: entry: 3928 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3929 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3930 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3931 // CHECK15-NEXT: ret void 3932 // 3933 // 3934 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3935 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3936 // CHECK15-NEXT: entry: 3937 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3938 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3939 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3940 // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 3941 // CHECK15-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 3942 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 3943 // CHECK15-NEXT: ret void 3944 // 3945 // 3946 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3947 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3948 // CHECK15-NEXT: entry: 3949 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3950 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3951 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3952 // CHECK15-NEXT: ret void 3953 // 3954 // 3955 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 3956 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { 3957 // CHECK17-NEXT: entry: 3958 // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 3959 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 3960 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined) 3961 // CHECK17-NEXT: ret void 3962 // 3963 // 3964 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined 3965 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 3966 // CHECK17-NEXT: entry: 3967 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3968 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3969 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3970 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 3971 // CHECK17-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 3972 // CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 3973 // CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 3974 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3975 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3976 // CHECK17-NEXT: [[G:%.*]] = alloca i32, align 4 3977 // CHECK17-NEXT: [[G1:%.*]] = alloca i32, align 4 3978 // CHECK17-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 3979 // CHECK17-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 3980 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 3981 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3982 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3983 // CHECK17-NEXT: store ptr undef, ptr [[_TMP1]], align 8 3984 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 3985 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 3986 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3987 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3988 // CHECK17-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 8 3989 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3990 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 3991 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3992 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3993 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 3994 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3995 // CHECK17: cond.true: 3996 // CHECK17-NEXT: br label [[COND_END:%.*]] 3997 // CHECK17: cond.false: 3998 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3999 // CHECK17-NEXT: br label [[COND_END]] 4000 // CHECK17: cond.end: 4001 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4002 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 4003 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 4004 // CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 4005 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4006 // CHECK17: omp.inner.for.cond: 4007 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] 4008 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 4009 // CHECK17-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4010 // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4011 // CHECK17: omp.inner.for.body: 4012 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP5]] 4013 // CHECK17-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 4014 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 4015 // CHECK17-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 4016 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP5]] 4017 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4018 // CHECK17: omp.inner.for.inc: 4019 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 4020 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP5]] 4021 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 4022 // CHECK17-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 4023 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 4024 // CHECK17: omp.inner.for.end: 4025 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4026 // CHECK17: omp.loop.exit: 4027 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 4028 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4029 // CHECK17-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 4030 // CHECK17-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4031 // CHECK17: .omp.final.then: 4032 // CHECK17-NEXT: store i32 2, ptr [[I]], align 4 4033 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 4034 // CHECK17: .omp.final.done: 4035 // CHECK17-NEXT: ret void 4036 // 4037 // 4038 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined.omp_outlined 4039 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { 4040 // CHECK17-NEXT: entry: 4041 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4042 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4043 // CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 4044 // CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 4045 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4046 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 4047 // CHECK17-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 4048 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4049 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4050 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4051 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4052 // CHECK17-NEXT: [[G:%.*]] = alloca i32, align 4 4053 // CHECK17-NEXT: [[G1:%.*]] = alloca i32, align 4 4054 // CHECK17-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 4055 // CHECK17-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 4056 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 4057 // CHECK17-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 4058 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4059 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4060 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 4061 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 4062 // CHECK17-NEXT: store ptr undef, ptr [[_TMP1]], align 8 4063 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4064 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 4065 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 4066 // CHECK17-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 4067 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 4068 // CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 4069 // CHECK17-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 4070 // CHECK17-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 4071 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4072 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4073 // CHECK17-NEXT: store ptr [[G1]], ptr [[_TMP3]], align 8 4074 // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4075 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 4076 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 4077 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4078 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 4079 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4080 // CHECK17: cond.true: 4081 // CHECK17-NEXT: br label [[COND_END:%.*]] 4082 // CHECK17: cond.false: 4083 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4084 // CHECK17-NEXT: br label [[COND_END]] 4085 // CHECK17: cond.end: 4086 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 4087 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4088 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4089 // CHECK17-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 4090 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4091 // CHECK17: omp.inner.for.cond: 4092 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] 4093 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 4094 // CHECK17-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 4095 // CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4096 // CHECK17: omp.inner.for.body: 4097 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 4098 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 4099 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4100 // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 4101 // CHECK17-NEXT: store i32 1, ptr [[G]], align 4, !llvm.access.group [[ACC_GRP9]] 4102 // CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !llvm.access.group [[ACC_GRP9]] 4103 // CHECK17-NEXT: store volatile i32 1, ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP9]] 4104 // CHECK17-NEXT: store i32 2, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP9]] 4105 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 4106 // CHECK17-NEXT: store ptr [[G]], ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP9]] 4107 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 4108 // CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8, !llvm.access.group [[ACC_GRP9]] 4109 // CHECK17-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP9]] 4110 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 2 4111 // CHECK17-NEXT: store ptr [[SIVAR]], ptr [[TMP14]], align 8, !llvm.access.group [[ACC_GRP9]] 4112 // CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group [[ACC_GRP9]] 4113 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4114 // CHECK17: omp.body.continue: 4115 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4116 // CHECK17: omp.inner.for.inc: 4117 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 4118 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 4119 // CHECK17-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 4120 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 4121 // CHECK17: omp.inner.for.end: 4122 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4123 // CHECK17: omp.loop.exit: 4124 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 4125 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4126 // CHECK17-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 4127 // CHECK17-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4128 // CHECK17: .omp.final.then: 4129 // CHECK17-NEXT: store i32 2, ptr [[I]], align 4 4130 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 4131 // CHECK17: .omp.final.done: 4132 // CHECK17-NEXT: ret void 4133 // 4134