1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 19 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 20 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 22 23 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 24 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 25 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 26 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 27 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 28 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 29 30 // expected-no-diagnostics 31 #ifndef HEADER 32 #define HEADER 33 34 template <class T> 35 struct S { 36 T f; 37 S(T a) : f(a) {} 38 S() : f() {} 39 operator T() { return T(); } 40 ~S() {} 41 }; 42 43 template <typename T> 44 T tmain() { 45 S<T> test; 46 T t_var = T(); 47 T vec[] = {1, 2}; 48 S<T> s_arr[] = {1, 2}; 49 S<T> &var = test; 50 #pragma omp target teams distribute parallel for simd lastprivate(t_var, vec, s_arr, s_arr, var, var) 51 for (int i = 0; i < 2; ++i) { 52 vec[i] = t_var; 53 s_arr[i] = var; 54 } 55 return T(); 56 } 57 58 int main() { 59 static int svar; 60 volatile double g; 61 volatile double &g1 = g; 62 63 #ifdef LAMBDA 64 [&]() { 65 static float sfvar; 66 67 #pragma omp target teams distribute parallel for simd lastprivate(g, g1, svar, sfvar) 68 for (int i = 0; i < 2; ++i) { 69 // skip gbl and bound tid 70 // loop variables 71 72 73 74 g1 = 1; 75 svar = 3; 76 sfvar = 4.0; 77 78 79 80 // skip tid and prev variables 81 // loop variables 82 83 84 85 86 87 88 89 [&]() { 90 g = 2; 91 g1 = 2; 92 svar = 4; 93 sfvar = 8.0; 94 95 }(); 96 } 97 }(); 98 return 0; 99 #else 100 S<float> test; 101 int t_var = 0; 102 int vec[] = {1, 2}; 103 S<float> s_arr[] = {1, 2}; 104 S<float> &var = test; 105 106 #pragma omp target teams distribute parallel for simd lastprivate(t_var, vec, s_arr, s_arr, var, var, svar) 107 for (int i = 0; i < 2; ++i) { 108 vec[i] = t_var; 109 s_arr[i] = var; 110 } 111 int i; 112 113 return tmain<int>(); 114 #endif 115 } 116 117 118 // skip loop variables 119 120 // copy from parameters to local address variables 121 122 // prepare lastprivate targets 123 124 // the distribute loop 125 126 // lastprivates 127 128 129 130 // gbl and bound tid vars, prev lb and ub vars 131 132 // skip loop variables 133 134 // copy from parameters to local address variables 135 136 // prepare lastprivate targets 137 138 // the distribute loop 139 // skip body: code generation routine is same as distribute parallel for lastprivate 140 141 // lastprivates 142 143 144 // template tmain 145 146 147 // skip alloca of global_tid and bound_tid 148 // skip loop variables 149 150 // copy from parameters to local address variables 151 152 // prepare lastprivate targets 153 154 155 // lastprivates 156 157 158 // skip alloca of global_tid and bound_tid, and prev lb and ub vars 159 160 // skip loop variables 161 162 // copy from parameters to local address variables 163 164 // prepare lastprivate targets 165 166 // skip body: code generation routine is same as distribute parallel for lastprivate 167 168 // lastprivates 169 170 171 #endif 172 // CHECK1-LABEL: define {{[^@]+}}@main 173 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 174 // CHECK1-NEXT: entry: 175 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 176 // CHECK1-NEXT: [[G:%.*]] = alloca double, align 8 177 // CHECK1-NEXT: [[G1:%.*]] = alloca ptr, align 8 178 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 179 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 180 // CHECK1-NEXT: store ptr [[G]], ptr [[G1]], align 8 181 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 182 // CHECK1-NEXT: store ptr [[G]], ptr [[TMP0]], align 8 183 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 184 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8 185 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8 186 // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) 187 // CHECK1-NEXT: ret i32 0 188 // 189 // 190 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 191 // CHECK1-SAME: (i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2:[0-9]+]] { 192 // CHECK1-NEXT: entry: 193 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 194 // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 195 // CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8 196 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 197 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 198 // CHECK1-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 199 // CHECK1-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 200 // CHECK1-NEXT: [[SFVAR_CASTED:%.*]] = alloca i64, align 8 201 // CHECK1-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 202 // CHECK1-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 203 // CHECK1-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 204 // CHECK1-NEXT: store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 205 // CHECK1-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 206 // CHECK1-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 207 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8 208 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile double, ptr [[TMP0]], align 8 209 // CHECK1-NEXT: store double [[TMP1]], ptr [[G1_CASTED]], align 8 210 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[G1_CASTED]], align 8 211 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[SVAR_ADDR]], align 4 212 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[SVAR_CASTED]], align 4 213 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8 214 // CHECK1-NEXT: [[TMP5:%.*]] = load float, ptr [[SFVAR_ADDR]], align 4 215 // CHECK1-NEXT: store float [[TMP5]], ptr [[SFVAR_CASTED]], align 4 216 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[SFVAR_CASTED]], align 8 217 // CHECK1-NEXT: [[TMP7:%.*]] = load double, ptr [[G_ADDR]], align 8 218 // CHECK1-NEXT: store double [[TMP7]], ptr [[G_CASTED]], align 8 219 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[G_CASTED]], align 8 220 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) 221 // CHECK1-NEXT: ret void 222 // 223 // 224 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined 225 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2]] { 226 // CHECK1-NEXT: entry: 227 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 228 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 229 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 230 // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 231 // CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8 232 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 233 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 234 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 235 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 236 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 237 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 238 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 239 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 240 // CHECK1-NEXT: [[G2:%.*]] = alloca double, align 8 241 // CHECK1-NEXT: [[G13:%.*]] = alloca double, align 8 242 // CHECK1-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8 243 // CHECK1-NEXT: [[SVAR5:%.*]] = alloca i32, align 4 244 // CHECK1-NEXT: [[SFVAR6:%.*]] = alloca float, align 4 245 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 246 // CHECK1-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 247 // CHECK1-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 248 // CHECK1-NEXT: [[SFVAR_CASTED:%.*]] = alloca i64, align 8 249 // CHECK1-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 250 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 251 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 252 // CHECK1-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 253 // CHECK1-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 254 // CHECK1-NEXT: store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 255 // CHECK1-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 256 // CHECK1-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 257 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 258 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 259 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 260 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 261 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8 262 // CHECK1-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 8 263 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 264 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 265 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 266 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 267 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 268 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 269 // CHECK1: cond.true: 270 // CHECK1-NEXT: br label [[COND_END:%.*]] 271 // CHECK1: cond.false: 272 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 273 // CHECK1-NEXT: br label [[COND_END]] 274 // CHECK1: cond.end: 275 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 276 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 277 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 278 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 279 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 280 // CHECK1: omp.inner.for.cond: 281 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]] 282 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]] 283 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 284 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 285 // CHECK1: omp.inner.for.body: 286 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP4]] 287 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 288 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]] 289 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 290 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8, !llvm.access.group [[ACC_GRP4]] 291 // CHECK1-NEXT: [[TMP13:%.*]] = load volatile double, ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP4]] 292 // CHECK1-NEXT: store double [[TMP13]], ptr [[G1_CASTED]], align 8, !llvm.access.group [[ACC_GRP4]] 293 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[G1_CASTED]], align 8, !llvm.access.group [[ACC_GRP4]] 294 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[SVAR5]], align 4, !llvm.access.group [[ACC_GRP4]] 295 // CHECK1-NEXT: store i32 [[TMP15]], ptr [[SVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP4]] 296 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP4]] 297 // CHECK1-NEXT: [[TMP17:%.*]] = load float, ptr [[SFVAR6]], align 4, !llvm.access.group [[ACC_GRP4]] 298 // CHECK1-NEXT: store float [[TMP17]], ptr [[SFVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP4]] 299 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[SFVAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP4]] 300 // CHECK1-NEXT: [[TMP19:%.*]] = load double, ptr [[G2]], align 8, !llvm.access.group [[ACC_GRP4]] 301 // CHECK1-NEXT: store double [[TMP19]], ptr [[G_CASTED]], align 8, !llvm.access.group [[ACC_GRP4]] 302 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, ptr [[G_CASTED]], align 8, !llvm.access.group [[ACC_GRP4]] 303 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP14]], i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]]), !llvm.access.group [[ACC_GRP4]] 304 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 305 // CHECK1: omp.inner.for.inc: 306 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 307 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP4]] 308 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] 309 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 310 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 311 // CHECK1: omp.inner.for.end: 312 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 313 // CHECK1: omp.loop.exit: 314 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 315 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 316 // CHECK1-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 317 // CHECK1-NEXT: br i1 [[TMP24]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 318 // CHECK1: .omp.final.then: 319 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 320 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 321 // CHECK1: .omp.final.done: 322 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 323 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 324 // CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] 325 // CHECK1: .omp.lastprivate.then: 326 // CHECK1-NEXT: [[TMP27:%.*]] = load double, ptr [[G2]], align 8 327 // CHECK1-NEXT: store volatile double [[TMP27]], ptr [[G_ADDR]], align 8 328 // CHECK1-NEXT: [[TMP28:%.*]] = load ptr, ptr [[_TMP4]], align 8 329 // CHECK1-NEXT: [[TMP29:%.*]] = load double, ptr [[TMP28]], align 8 330 // CHECK1-NEXT: store volatile double [[TMP29]], ptr [[TMP0]], align 8 331 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[SVAR5]], align 4 332 // CHECK1-NEXT: store i32 [[TMP30]], ptr [[SVAR_ADDR]], align 4 333 // CHECK1-NEXT: [[TMP31:%.*]] = load float, ptr [[SFVAR6]], align 4 334 // CHECK1-NEXT: store float [[TMP31]], ptr [[SFVAR_ADDR]], align 4 335 // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] 336 // CHECK1: .omp.lastprivate.done: 337 // CHECK1-NEXT: ret void 338 // 339 // 340 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined 341 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2]] { 342 // CHECK1-NEXT: entry: 343 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 344 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 345 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 346 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 347 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 348 // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 349 // CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8 350 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 351 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 352 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 353 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 354 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 355 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 356 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 357 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 358 // CHECK1-NEXT: [[G3:%.*]] = alloca double, align 8 359 // CHECK1-NEXT: [[G14:%.*]] = alloca double, align 8 360 // CHECK1-NEXT: [[_TMP5:%.*]] = alloca ptr, align 8 361 // CHECK1-NEXT: [[SVAR6:%.*]] = alloca i32, align 4 362 // CHECK1-NEXT: [[SFVAR7:%.*]] = alloca float, align 4 363 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 364 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 365 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 366 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 367 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 368 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 369 // CHECK1-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 370 // CHECK1-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 371 // CHECK1-NEXT: store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 372 // CHECK1-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 373 // CHECK1-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 374 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 375 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 376 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 377 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 378 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 379 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 380 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 381 // CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 382 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 383 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 384 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 385 // CHECK1-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 8 386 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 387 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 388 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 389 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 390 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 391 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 392 // CHECK1: cond.true: 393 // CHECK1-NEXT: br label [[COND_END:%.*]] 394 // CHECK1: cond.false: 395 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 396 // CHECK1-NEXT: br label [[COND_END]] 397 // CHECK1: cond.end: 398 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 399 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 400 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 401 // CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 402 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 403 // CHECK1: omp.inner.for.cond: 404 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]] 405 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]] 406 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 407 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 408 // CHECK1: omp.inner.for.body: 409 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 410 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 411 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 412 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 413 // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP5]], align 8, !llvm.access.group [[ACC_GRP8]] 414 // CHECK1-NEXT: store volatile double 1.000000e+00, ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP8]] 415 // CHECK1-NEXT: store i32 3, ptr [[SVAR6]], align 4, !llvm.access.group [[ACC_GRP8]] 416 // CHECK1-NEXT: store float 4.000000e+00, ptr [[SFVAR7]], align 4, !llvm.access.group [[ACC_GRP8]] 417 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 418 // CHECK1-NEXT: store ptr [[G3]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP8]] 419 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 420 // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP5]], align 8, !llvm.access.group [[ACC_GRP8]] 421 // CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !llvm.access.group [[ACC_GRP8]] 422 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 423 // CHECK1-NEXT: store ptr [[SVAR6]], ptr [[TMP15]], align 8, !llvm.access.group [[ACC_GRP8]] 424 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3 425 // CHECK1-NEXT: store ptr [[SFVAR7]], ptr [[TMP16]], align 8, !llvm.access.group [[ACC_GRP8]] 426 // CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group [[ACC_GRP8]] 427 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 428 // CHECK1: omp.body.continue: 429 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 430 // CHECK1: omp.inner.for.inc: 431 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 432 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], 1 433 // CHECK1-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 434 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 435 // CHECK1: omp.inner.for.end: 436 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 437 // CHECK1: omp.loop.exit: 438 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) 439 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 440 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 441 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 442 // CHECK1: .omp.final.then: 443 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 444 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 445 // CHECK1: .omp.final.done: 446 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 447 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 448 // CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] 449 // CHECK1: .omp.lastprivate.then: 450 // CHECK1-NEXT: [[TMP22:%.*]] = load double, ptr [[G3]], align 8 451 // CHECK1-NEXT: store volatile double [[TMP22]], ptr [[G_ADDR]], align 8 452 // CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[_TMP5]], align 8 453 // CHECK1-NEXT: [[TMP24:%.*]] = load double, ptr [[TMP23]], align 8 454 // CHECK1-NEXT: store volatile double [[TMP24]], ptr [[TMP2]], align 8 455 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[SVAR6]], align 4 456 // CHECK1-NEXT: store i32 [[TMP25]], ptr [[SVAR_ADDR]], align 4 457 // CHECK1-NEXT: [[TMP26:%.*]] = load float, ptr [[SFVAR7]], align 4 458 // CHECK1-NEXT: store float [[TMP26]], ptr [[SFVAR_ADDR]], align 4 459 // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] 460 // CHECK1: .omp.lastprivate.done: 461 // CHECK1-NEXT: ret void 462 // 463 // 464 // CHECK3-LABEL: define {{[^@]+}}@main 465 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 466 // CHECK3-NEXT: entry: 467 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 468 // CHECK3-NEXT: [[G:%.*]] = alloca double, align 8 469 // CHECK3-NEXT: [[G1:%.*]] = alloca ptr, align 4 470 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 471 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 472 // CHECK3-NEXT: store ptr [[G]], ptr [[G1]], align 4 473 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 474 // CHECK3-NEXT: store ptr [[G]], ptr [[TMP0]], align 4 475 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 476 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4 477 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 4 478 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]]) 479 // CHECK3-NEXT: ret i32 0 480 // 481 // 482 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 483 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2:[0-9]+]] { 484 // CHECK3-NEXT: entry: 485 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca ptr, align 4 486 // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 487 // CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4 488 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4 489 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 490 // CHECK3-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 491 // CHECK3-NEXT: [[SFVAR_CASTED:%.*]] = alloca i32, align 4 492 // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 493 // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 494 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 495 // CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4 496 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 497 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G_ADDR]], align 4 498 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 499 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4 500 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[SVAR_ADDR]], align 4 501 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[SVAR_CASTED]], align 4 502 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 503 // CHECK3-NEXT: [[TMP5:%.*]] = load float, ptr [[SFVAR_ADDR]], align 4 504 // CHECK3-NEXT: store float [[TMP5]], ptr [[SFVAR_CASTED]], align 4 505 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[SFVAR_CASTED]], align 4 506 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, ptr [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP1]]) 507 // CHECK3-NEXT: ret void 508 // 509 // 510 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined 511 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] { 512 // CHECK3-NEXT: entry: 513 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 514 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 515 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca ptr, align 4 516 // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 517 // CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4 518 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4 519 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 520 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 521 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 522 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 523 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 524 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 525 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 526 // CHECK3-NEXT: [[G2:%.*]] = alloca double, align 8 527 // CHECK3-NEXT: [[G13:%.*]] = alloca double, align 8 528 // CHECK3-NEXT: [[_TMP4:%.*]] = alloca ptr, align 4 529 // CHECK3-NEXT: [[SVAR5:%.*]] = alloca i32, align 4 530 // CHECK3-NEXT: [[SFVAR6:%.*]] = alloca float, align 4 531 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 532 // CHECK3-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 533 // CHECK3-NEXT: [[SFVAR_CASTED:%.*]] = alloca i32, align 4 534 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 535 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 536 // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 537 // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 538 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 539 // CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4 540 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 541 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G_ADDR]], align 4 542 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 543 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 544 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 545 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 546 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 547 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4 548 // CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4 549 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 550 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 551 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 552 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 553 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 554 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 555 // CHECK3: cond.true: 556 // CHECK3-NEXT: br label [[COND_END:%.*]] 557 // CHECK3: cond.false: 558 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 559 // CHECK3-NEXT: br label [[COND_END]] 560 // CHECK3: cond.end: 561 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 562 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 563 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 564 // CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 565 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 566 // CHECK3: omp.inner.for.cond: 567 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] 568 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 569 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 570 // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 571 // CHECK3: omp.inner.for.body: 572 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP5]] 573 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 574 // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 4, !llvm.access.group [[ACC_GRP5]] 575 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[SVAR5]], align 4, !llvm.access.group [[ACC_GRP5]] 576 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[SVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]] 577 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]] 578 // CHECK3-NEXT: [[TMP15:%.*]] = load float, ptr [[SFVAR6]], align 4, !llvm.access.group [[ACC_GRP5]] 579 // CHECK3-NEXT: store float [[TMP15]], ptr [[SFVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]] 580 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SFVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]] 581 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined, i32 [[TMP10]], i32 [[TMP11]], ptr [[TMP12]], i32 [[TMP14]], i32 [[TMP16]], ptr [[G2]]), !llvm.access.group [[ACC_GRP5]] 582 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 583 // CHECK3: omp.inner.for.inc: 584 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 585 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP5]] 586 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] 587 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 588 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 589 // CHECK3: omp.inner.for.end: 590 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 591 // CHECK3: omp.loop.exit: 592 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) 593 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 594 // CHECK3-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0 595 // CHECK3-NEXT: br i1 [[TMP20]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 596 // CHECK3: .omp.final.then: 597 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 598 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 599 // CHECK3: .omp.final.done: 600 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 601 // CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 602 // CHECK3-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] 603 // CHECK3: .omp.lastprivate.then: 604 // CHECK3-NEXT: [[TMP23:%.*]] = load double, ptr [[G2]], align 8 605 // CHECK3-NEXT: store volatile double [[TMP23]], ptr [[TMP1]], align 8 606 // CHECK3-NEXT: [[TMP24:%.*]] = load ptr, ptr [[_TMP4]], align 4 607 // CHECK3-NEXT: [[TMP25:%.*]] = load double, ptr [[TMP24]], align 4 608 // CHECK3-NEXT: store volatile double [[TMP25]], ptr [[TMP2]], align 4 609 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, ptr [[SVAR5]], align 4 610 // CHECK3-NEXT: store i32 [[TMP26]], ptr [[SVAR_ADDR]], align 4 611 // CHECK3-NEXT: [[TMP27:%.*]] = load float, ptr [[SFVAR6]], align 4 612 // CHECK3-NEXT: store float [[TMP27]], ptr [[SFVAR_ADDR]], align 4 613 // CHECK3-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] 614 // CHECK3: .omp.lastprivate.done: 615 // CHECK3-NEXT: ret void 616 // 617 // 618 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined 619 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] { 620 // CHECK3-NEXT: entry: 621 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 622 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 623 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 624 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 625 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca ptr, align 4 626 // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 627 // CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4 628 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4 629 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 630 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 631 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 632 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 633 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 634 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 635 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 636 // CHECK3-NEXT: [[G2:%.*]] = alloca double, align 8 637 // CHECK3-NEXT: [[G13:%.*]] = alloca double, align 8 638 // CHECK3-NEXT: [[_TMP4:%.*]] = alloca ptr, align 4 639 // CHECK3-NEXT: [[SVAR5:%.*]] = alloca i32, align 4 640 // CHECK3-NEXT: [[SFVAR6:%.*]] = alloca float, align 4 641 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 642 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 643 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 644 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 645 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 646 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 647 // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 648 // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 649 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 650 // CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4 651 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 652 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G_ADDR]], align 4 653 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 654 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 655 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 656 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 657 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 658 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_LB]], align 4 659 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_UB]], align 4 660 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 661 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 662 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 663 // CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4 664 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 665 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 666 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 667 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 668 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 669 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 670 // CHECK3: cond.true: 671 // CHECK3-NEXT: br label [[COND_END:%.*]] 672 // CHECK3: cond.false: 673 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 674 // CHECK3-NEXT: br label [[COND_END]] 675 // CHECK3: cond.end: 676 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 677 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 678 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 679 // CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 680 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 681 // CHECK3: omp.inner.for.cond: 682 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] 683 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 684 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 685 // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 686 // CHECK3: omp.inner.for.body: 687 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 688 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 689 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 690 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 691 // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP4]], align 4, !llvm.access.group [[ACC_GRP9]] 692 // CHECK3-NEXT: store volatile double 1.000000e+00, ptr [[TMP13]], align 4, !llvm.access.group [[ACC_GRP9]] 693 // CHECK3-NEXT: store i32 3, ptr [[SVAR5]], align 4, !llvm.access.group [[ACC_GRP9]] 694 // CHECK3-NEXT: store float 4.000000e+00, ptr [[SFVAR6]], align 4, !llvm.access.group [[ACC_GRP9]] 695 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 696 // CHECK3-NEXT: store ptr [[G2]], ptr [[TMP14]], align 4, !llvm.access.group [[ACC_GRP9]] 697 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 698 // CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP4]], align 4, !llvm.access.group [[ACC_GRP9]] 699 // CHECK3-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 4, !llvm.access.group [[ACC_GRP9]] 700 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 701 // CHECK3-NEXT: store ptr [[SVAR5]], ptr [[TMP17]], align 4, !llvm.access.group [[ACC_GRP9]] 702 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3 703 // CHECK3-NEXT: store ptr [[SFVAR6]], ptr [[TMP18]], align 4, !llvm.access.group [[ACC_GRP9]] 704 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group [[ACC_GRP9]] 705 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 706 // CHECK3: omp.body.continue: 707 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 708 // CHECK3: omp.inner.for.inc: 709 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 710 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 711 // CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 712 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 713 // CHECK3: omp.inner.for.end: 714 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 715 // CHECK3: omp.loop.exit: 716 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP6]]) 717 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 718 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 719 // CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 720 // CHECK3: .omp.final.then: 721 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 722 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 723 // CHECK3: .omp.final.done: 724 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 725 // CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 726 // CHECK3-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] 727 // CHECK3: .omp.lastprivate.then: 728 // CHECK3-NEXT: [[TMP24:%.*]] = load double, ptr [[G2]], align 8 729 // CHECK3-NEXT: store volatile double [[TMP24]], ptr [[TMP1]], align 8 730 // CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP4]], align 4 731 // CHECK3-NEXT: [[TMP26:%.*]] = load double, ptr [[TMP25]], align 4 732 // CHECK3-NEXT: store volatile double [[TMP26]], ptr [[TMP4]], align 4 733 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[SVAR5]], align 4 734 // CHECK3-NEXT: store i32 [[TMP27]], ptr [[SVAR_ADDR]], align 4 735 // CHECK3-NEXT: [[TMP28:%.*]] = load float, ptr [[SFVAR6]], align 4 736 // CHECK3-NEXT: store float [[TMP28]], ptr [[SFVAR_ADDR]], align 4 737 // CHECK3-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] 738 // CHECK3: .omp.lastprivate.done: 739 // CHECK3-NEXT: ret void 740 // 741 // 742 // CHECK5-LABEL: define {{[^@]+}}@main 743 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 744 // CHECK5-NEXT: entry: 745 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 746 // CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 747 // CHECK5-NEXT: [[G1:%.*]] = alloca ptr, align 8 748 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 749 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 750 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 751 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 752 // CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 8 753 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 754 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 755 // CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 756 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 757 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 758 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 759 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 760 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 761 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 762 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 763 // CHECK5-NEXT: store ptr [[G]], ptr [[G1]], align 8 764 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 765 // CHECK5-NEXT: store i32 0, ptr [[T_VAR]], align 4 766 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false) 767 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00) 768 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1 769 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) 770 // CHECK5-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 771 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 772 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 773 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 774 // CHECK5-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 775 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 776 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 777 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 778 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 779 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8 780 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 781 // CHECK5-NEXT: store ptr [[VEC]], ptr [[TMP6]], align 8 782 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 783 // CHECK5-NEXT: store ptr [[VEC]], ptr [[TMP7]], align 8 784 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 785 // CHECK5-NEXT: store ptr null, ptr [[TMP8]], align 8 786 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 787 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP9]], align 8 788 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 789 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP10]], align 8 790 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 791 // CHECK5-NEXT: store ptr null, ptr [[TMP11]], align 8 792 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 793 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 8 794 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 795 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 8 796 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 797 // CHECK5-NEXT: store ptr null, ptr [[TMP14]], align 8 798 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 799 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[TMP15]], align 8 800 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 801 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[TMP16]], align 8 802 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 803 // CHECK5-NEXT: store ptr null, ptr [[TMP17]], align 8 804 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 805 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP18]], align 8 806 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 807 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP19]], align 8 808 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 809 // CHECK5-NEXT: store ptr null, ptr [[TMP20]], align 8 810 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 811 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 812 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 813 // CHECK5-NEXT: store i32 3, ptr [[TMP23]], align 4 814 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 815 // CHECK5-NEXT: store i32 5, ptr [[TMP24]], align 4 816 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 817 // CHECK5-NEXT: store ptr [[TMP21]], ptr [[TMP25]], align 8 818 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 819 // CHECK5-NEXT: store ptr [[TMP22]], ptr [[TMP26]], align 8 820 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 821 // CHECK5-NEXT: store ptr @.offload_sizes, ptr [[TMP27]], align 8 822 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 823 // CHECK5-NEXT: store ptr @.offload_maptypes, ptr [[TMP28]], align 8 824 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 825 // CHECK5-NEXT: store ptr null, ptr [[TMP29]], align 8 826 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 827 // CHECK5-NEXT: store ptr null, ptr [[TMP30]], align 8 828 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 829 // CHECK5-NEXT: store i64 2, ptr [[TMP31]], align 8 830 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 831 // CHECK5-NEXT: store i64 0, ptr [[TMP32]], align 8 832 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 833 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP33]], align 4 834 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 835 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP34]], align 4 836 // CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 837 // CHECK5-NEXT: store i32 0, ptr [[TMP35]], align 4 838 // CHECK5-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, ptr [[KERNEL_ARGS]]) 839 // CHECK5-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 840 // CHECK5-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 841 // CHECK5: omp_offload.failed: 842 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(ptr [[VEC]], i64 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]], i64 [[TMP5]]) #[[ATTR4:[0-9]+]] 843 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 844 // CHECK5: omp_offload.cont: 845 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 846 // CHECK5-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 847 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 848 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 849 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 850 // CHECK5: arraydestroy.body: 851 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 852 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 853 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 854 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 855 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 856 // CHECK5: arraydestroy.done2: 857 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 858 // CHECK5-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4 859 // CHECK5-NEXT: ret i32 [[TMP39]] 860 // 861 // 862 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 863 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 864 // CHECK5-NEXT: entry: 865 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 866 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 867 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 868 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 869 // CHECK5-NEXT: ret void 870 // 871 // 872 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 873 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 874 // CHECK5-NEXT: entry: 875 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 876 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 877 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 878 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 879 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 880 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 881 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 882 // CHECK5-NEXT: ret void 883 // 884 // 885 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 886 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { 887 // CHECK5-NEXT: entry: 888 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 889 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 890 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 891 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 892 // CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 893 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 894 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 895 // CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 896 // CHECK5-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 897 // CHECK5-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 898 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 899 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 900 // CHECK5-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 901 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 902 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 903 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 904 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 905 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 906 // CHECK5-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 907 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 908 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 909 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[SVAR_ADDR]], align 4 910 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[SVAR_CASTED]], align 4 911 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8 912 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]], i64 [[TMP7]]) 913 // CHECK5-NEXT: ret void 914 // 915 // 916 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined 917 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] { 918 // CHECK5-NEXT: entry: 919 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 920 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 921 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 922 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 923 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 924 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 925 // CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 926 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 927 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 928 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 929 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 930 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 931 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 932 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 933 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 934 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 935 // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 936 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 937 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 938 // CHECK5-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 939 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 940 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 941 // CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 942 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 943 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 944 // CHECK5-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 945 // CHECK5-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 946 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 947 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 948 // CHECK5-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 949 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 950 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 951 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 952 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 953 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 954 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 955 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 956 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 957 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 958 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 959 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 960 // CHECK5: arrayctor.loop: 961 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 962 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 963 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 964 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 965 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 966 // CHECK5: arrayctor.cont: 967 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 968 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 969 // CHECK5-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 8 970 // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 971 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 972 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 973 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 974 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 975 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 976 // CHECK5: cond.true: 977 // CHECK5-NEXT: br label [[COND_END:%.*]] 978 // CHECK5: cond.false: 979 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 980 // CHECK5-NEXT: br label [[COND_END]] 981 // CHECK5: cond.end: 982 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 983 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 984 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 985 // CHECK5-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 986 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 987 // CHECK5: omp.inner.for.cond: 988 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] 989 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 990 // CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 991 // CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 992 // CHECK5: omp.inner.for.cond.cleanup: 993 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 994 // CHECK5: omp.inner.for.body: 995 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP5]] 996 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 997 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 998 // CHECK5-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 999 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP5]] 1000 // CHECK5-NEXT: store i32 [[TMP15]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]] 1001 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP5]] 1002 // CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP5]] 1003 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[SVAR7]], align 4, !llvm.access.group [[ACC_GRP5]] 1004 // CHECK5-NEXT: store i32 [[TMP18]], ptr [[SVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]] 1005 // CHECK5-NEXT: [[TMP19:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP5]] 1006 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], ptr [[VEC3]], i64 [[TMP16]], ptr [[S_ARR4]], ptr [[TMP17]], i64 [[TMP19]]), !llvm.access.group [[ACC_GRP5]] 1007 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1008 // CHECK5: omp.inner.for.inc: 1009 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 1010 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP5]] 1011 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] 1012 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 1013 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 1014 // CHECK5: omp.inner.for.end: 1015 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1016 // CHECK5: omp.loop.exit: 1017 // CHECK5-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1018 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4 1019 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP23]]) 1020 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1021 // CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 1022 // CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1023 // CHECK5: .omp.final.then: 1024 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 1025 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 1026 // CHECK5: .omp.final.done: 1027 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1028 // CHECK5-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 1029 // CHECK5-NEXT: br i1 [[TMP27]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] 1030 // CHECK5: .omp.lastprivate.then: 1031 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, ptr [[T_VAR2]], align 4 1032 // CHECK5-NEXT: store i32 [[TMP28]], ptr [[T_VAR_ADDR]], align 4 1033 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false) 1034 // CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0 1035 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i64 2 1036 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP29]] 1037 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1038 // CHECK5: omp.arraycpy.body: 1039 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1040 // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1041 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false) 1042 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1043 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1044 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] 1045 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] 1046 // CHECK5: omp.arraycpy.done10: 1047 // CHECK5-NEXT: [[TMP30:%.*]] = load ptr, ptr [[_TMP6]], align 8 1048 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP3]], ptr align 4 [[TMP30]], i64 4, i1 false) 1049 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, ptr [[SVAR7]], align 4 1050 // CHECK5-NEXT: store i32 [[TMP31]], ptr [[SVAR_ADDR]], align 4 1051 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] 1052 // CHECK5: .omp.lastprivate.done: 1053 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 1054 // CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 1055 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 1056 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1057 // CHECK5: arraydestroy.body: 1058 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP32]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1059 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1060 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1061 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 1062 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 1063 // CHECK5: arraydestroy.done12: 1064 // CHECK5-NEXT: ret void 1065 // 1066 // 1067 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined.omp_outlined 1068 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] { 1069 // CHECK5-NEXT: entry: 1070 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1071 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1072 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1073 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1074 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 1075 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1076 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 1077 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 1078 // CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 1079 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1080 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1081 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1082 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1083 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1084 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1085 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1086 // CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 1087 // CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 1088 // CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 1089 // CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1090 // CHECK5-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 1091 // CHECK5-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 1092 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1093 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1094 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1095 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1096 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1097 // CHECK5-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 1098 // CHECK5-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 1099 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 1100 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 1101 // CHECK5-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 1102 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 1103 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 1104 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 1105 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 1106 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1107 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1108 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1109 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 1110 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1111 // CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32 1112 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1113 // CHECK5-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 1114 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1115 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1116 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 1117 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 1118 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1119 // CHECK5: arrayctor.loop: 1120 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1121 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1122 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 1123 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1124 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1125 // CHECK5: arrayctor.cont: 1126 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 1127 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) 1128 // CHECK5-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 1129 // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1130 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 1131 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1132 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1133 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 1134 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1135 // CHECK5: cond.true: 1136 // CHECK5-NEXT: br label [[COND_END:%.*]] 1137 // CHECK5: cond.false: 1138 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1139 // CHECK5-NEXT: br label [[COND_END]] 1140 // CHECK5: cond.end: 1141 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] 1142 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1143 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1144 // CHECK5-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 1145 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1146 // CHECK5: omp.inner.for.cond: 1147 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] 1148 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 1149 // CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 1150 // CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1151 // CHECK5: omp.inner.for.cond.cleanup: 1152 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1153 // CHECK5: omp.inner.for.body: 1154 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 1155 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 1156 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1157 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 1158 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP9]] 1159 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 1160 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 1161 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] 1162 // CHECK5-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] 1163 // CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP9]] 1164 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 1165 // CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP17]] to i64 1166 // CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] 1167 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP16]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] 1168 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1169 // CHECK5: omp.body.continue: 1170 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1171 // CHECK5: omp.inner.for.inc: 1172 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 1173 // CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1 1174 // CHECK5-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 1175 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 1176 // CHECK5: omp.inner.for.end: 1177 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1178 // CHECK5: omp.loop.exit: 1179 // CHECK5-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1180 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 1181 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP20]]) 1182 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1183 // CHECK5-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 1184 // CHECK5-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1185 // CHECK5: .omp.final.then: 1186 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 1187 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 1188 // CHECK5: .omp.final.done: 1189 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1190 // CHECK5-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 1191 // CHECK5-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] 1192 // CHECK5: .omp.lastprivate.then: 1193 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR3]], align 4 1194 // CHECK5-NEXT: store i32 [[TMP25]], ptr [[T_VAR_ADDR]], align 4 1195 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC4]], i64 8, i1 false) 1196 // CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0 1197 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i64 2 1198 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN13]], [[TMP26]] 1199 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1200 // CHECK5: omp.arraycpy.body: 1201 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR5]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1202 // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1203 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false) 1204 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1205 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1206 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP26]] 1207 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] 1208 // CHECK5: omp.arraycpy.done14: 1209 // CHECK5-NEXT: [[TMP27:%.*]] = load ptr, ptr [[_TMP7]], align 8 1210 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP27]], i64 4, i1 false) 1211 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, ptr [[SVAR8]], align 4 1212 // CHECK5-NEXT: store i32 [[TMP28]], ptr [[SVAR_ADDR]], align 4 1213 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] 1214 // CHECK5: .omp.lastprivate.done: 1215 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] 1216 // CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 1217 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN15]], i64 2 1218 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1219 // CHECK5: arraydestroy.body: 1220 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1221 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1222 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1223 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] 1224 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] 1225 // CHECK5: arraydestroy.done16: 1226 // CHECK5-NEXT: ret void 1227 // 1228 // 1229 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1230 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1231 // CHECK5-NEXT: entry: 1232 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1233 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1234 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1235 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1236 // CHECK5-NEXT: ret void 1237 // 1238 // 1239 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1240 // CHECK5-SAME: () #[[ATTR1]] comdat { 1241 // CHECK5-NEXT: entry: 1242 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1243 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1244 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1245 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1246 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1247 // CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 8 1248 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1249 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1250 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 1251 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 1252 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 1253 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1254 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1255 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1256 // CHECK5-NEXT: store i32 0, ptr [[T_VAR]], align 4 1257 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 1258 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 1259 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 1260 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 1261 // CHECK5-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 1262 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 1263 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 1264 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 1265 // CHECK5-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 1266 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 1267 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 1268 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1269 // CHECK5-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 8 1270 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1271 // CHECK5-NEXT: store ptr [[VEC]], ptr [[TMP5]], align 8 1272 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1273 // CHECK5-NEXT: store ptr null, ptr [[TMP6]], align 8 1274 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1275 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP7]], align 8 1276 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1277 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP8]], align 8 1278 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1279 // CHECK5-NEXT: store ptr null, ptr [[TMP9]], align 8 1280 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1281 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[TMP10]], align 8 1282 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1283 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[TMP11]], align 8 1284 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1285 // CHECK5-NEXT: store ptr null, ptr [[TMP12]], align 8 1286 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1287 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 8 1288 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1289 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 8 1290 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1291 // CHECK5-NEXT: store ptr null, ptr [[TMP15]], align 8 1292 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1293 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1294 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1295 // CHECK5-NEXT: store i32 3, ptr [[TMP18]], align 4 1296 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1297 // CHECK5-NEXT: store i32 4, ptr [[TMP19]], align 4 1298 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1299 // CHECK5-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 8 1300 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1301 // CHECK5-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 8 1302 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1303 // CHECK5-NEXT: store ptr @.offload_sizes.1, ptr [[TMP22]], align 8 1304 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1305 // CHECK5-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP23]], align 8 1306 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1307 // CHECK5-NEXT: store ptr null, ptr [[TMP24]], align 8 1308 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1309 // CHECK5-NEXT: store ptr null, ptr [[TMP25]], align 8 1310 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1311 // CHECK5-NEXT: store i64 2, ptr [[TMP26]], align 8 1312 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1313 // CHECK5-NEXT: store i64 0, ptr [[TMP27]], align 8 1314 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1315 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 1316 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1317 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4 1318 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1319 // CHECK5-NEXT: store i32 0, ptr [[TMP30]], align 4 1320 // CHECK5-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.region_id, ptr [[KERNEL_ARGS]]) 1321 // CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1322 // CHECK5-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1323 // CHECK5: omp_offload.failed: 1324 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50(ptr [[VEC]], i64 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]] 1325 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 1326 // CHECK5: omp_offload.cont: 1327 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 1328 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1329 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 1330 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1331 // CHECK5: arraydestroy.body: 1332 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1333 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1334 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1335 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1336 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1337 // CHECK5: arraydestroy.done2: 1338 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 1339 // CHECK5-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 1340 // CHECK5-NEXT: ret i32 [[TMP34]] 1341 // 1342 // 1343 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1344 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1345 // CHECK5-NEXT: entry: 1346 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1347 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1348 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1349 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1350 // CHECK5-NEXT: store float 0.000000e+00, ptr [[F]], align 4 1351 // CHECK5-NEXT: ret void 1352 // 1353 // 1354 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1355 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1356 // CHECK5-NEXT: entry: 1357 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1358 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1359 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1360 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1361 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1362 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1363 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1364 // CHECK5-NEXT: store float [[TMP0]], ptr [[F]], align 4 1365 // CHECK5-NEXT: ret void 1366 // 1367 // 1368 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1369 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1370 // CHECK5-NEXT: entry: 1371 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1372 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1373 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1374 // CHECK5-NEXT: ret void 1375 // 1376 // 1377 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1378 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1379 // CHECK5-NEXT: entry: 1380 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1381 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1382 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1383 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1384 // CHECK5-NEXT: ret void 1385 // 1386 // 1387 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1388 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1389 // CHECK5-NEXT: entry: 1390 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1391 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1392 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1393 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1394 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1395 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1396 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 1397 // CHECK5-NEXT: ret void 1398 // 1399 // 1400 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50 1401 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 1402 // CHECK5-NEXT: entry: 1403 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 1404 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1405 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 1406 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 1407 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1408 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1409 // CHECK5-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 1410 // CHECK5-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 1411 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 1412 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 1413 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 1414 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 1415 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 1416 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 1417 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1418 // CHECK5-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 1419 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 1420 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 1421 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) 1422 // CHECK5-NEXT: ret void 1423 // 1424 // 1425 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined 1426 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 1427 // CHECK5-NEXT: entry: 1428 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1429 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1430 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 1431 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1432 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 1433 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 1434 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1435 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1436 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1437 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1438 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1439 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1440 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1441 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 1442 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 1443 // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 1444 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1445 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 1446 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1447 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1448 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1449 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1450 // CHECK5-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 1451 // CHECK5-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 1452 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 1453 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 1454 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 1455 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 1456 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 1457 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 1458 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1459 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1460 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1461 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1462 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 1463 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 1464 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1465 // CHECK5: arrayctor.loop: 1466 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1467 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1468 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 1469 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1470 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1471 // CHECK5: arrayctor.cont: 1472 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 1473 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 1474 // CHECK5-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 8 1475 // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1476 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 1477 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1478 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1479 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 1480 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1481 // CHECK5: cond.true: 1482 // CHECK5-NEXT: br label [[COND_END:%.*]] 1483 // CHECK5: cond.false: 1484 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1485 // CHECK5-NEXT: br label [[COND_END]] 1486 // CHECK5: cond.end: 1487 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1488 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1489 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1490 // CHECK5-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 1491 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1492 // CHECK5: omp.inner.for.cond: 1493 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]] 1494 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]] 1495 // CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1496 // CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1497 // CHECK5: omp.inner.for.cond.cleanup: 1498 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1499 // CHECK5: omp.inner.for.body: 1500 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP14]] 1501 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 1502 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]] 1503 // CHECK5-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 1504 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP14]] 1505 // CHECK5-NEXT: store i32 [[TMP15]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP14]] 1506 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP14]] 1507 // CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP14]] 1508 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], ptr [[VEC3]], i64 [[TMP16]], ptr [[S_ARR4]], ptr [[TMP17]]), !llvm.access.group [[ACC_GRP14]] 1509 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1510 // CHECK5: omp.inner.for.inc: 1511 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 1512 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP14]] 1513 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 1514 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 1515 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 1516 // CHECK5: omp.inner.for.end: 1517 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1518 // CHECK5: omp.loop.exit: 1519 // CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1520 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 1521 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP21]]) 1522 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1523 // CHECK5-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 1524 // CHECK5-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1525 // CHECK5: .omp.final.then: 1526 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 1527 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 1528 // CHECK5: .omp.final.done: 1529 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1530 // CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 1531 // CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] 1532 // CHECK5: .omp.lastprivate.then: 1533 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, ptr [[T_VAR2]], align 4 1534 // CHECK5-NEXT: store i32 [[TMP26]], ptr [[T_VAR_ADDR]], align 4 1535 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false) 1536 // CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0 1537 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 1538 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN8]], [[TMP27]] 1539 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1540 // CHECK5: omp.arraycpy.body: 1541 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1542 // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN8]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1543 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false) 1544 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1545 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1546 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] 1547 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]] 1548 // CHECK5: omp.arraycpy.done9: 1549 // CHECK5-NEXT: [[TMP28:%.*]] = load ptr, ptr [[_TMP6]], align 8 1550 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP3]], ptr align 4 [[TMP28]], i64 4, i1 false) 1551 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] 1552 // CHECK5: .omp.lastprivate.done: 1553 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 1554 // CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 1555 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 1556 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1557 // CHECK5: arraydestroy.body: 1558 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1559 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1560 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1561 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 1562 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 1563 // CHECK5: arraydestroy.done11: 1564 // CHECK5-NEXT: ret void 1565 // 1566 // 1567 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined.omp_outlined 1568 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 1569 // CHECK5-NEXT: entry: 1570 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1571 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1572 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1573 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1574 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 1575 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1576 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 1577 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 1578 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1579 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1580 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1581 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1582 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1583 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1584 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1585 // CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 1586 // CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 1587 // CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 1588 // CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1589 // CHECK5-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 1590 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1591 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1592 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1593 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1594 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1595 // CHECK5-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 1596 // CHECK5-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 1597 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 1598 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 1599 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 1600 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 1601 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 1602 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 1603 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1604 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1605 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1606 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 1607 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1608 // CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32 1609 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1610 // CHECK5-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 1611 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1612 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1613 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 1614 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 1615 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1616 // CHECK5: arrayctor.loop: 1617 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1618 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1619 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 1620 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1621 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1622 // CHECK5: arrayctor.cont: 1623 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 1624 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) 1625 // CHECK5-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 1626 // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1627 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 1628 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1629 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1630 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 1631 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1632 // CHECK5: cond.true: 1633 // CHECK5-NEXT: br label [[COND_END:%.*]] 1634 // CHECK5: cond.false: 1635 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1636 // CHECK5-NEXT: br label [[COND_END]] 1637 // CHECK5: cond.end: 1638 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] 1639 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1640 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1641 // CHECK5-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 1642 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1643 // CHECK5: omp.inner.for.cond: 1644 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]] 1645 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP17]] 1646 // CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 1647 // CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1648 // CHECK5: omp.inner.for.cond.cleanup: 1649 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1650 // CHECK5: omp.inner.for.body: 1651 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 1652 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 1653 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1654 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 1655 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP17]] 1656 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 1657 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 1658 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] 1659 // CHECK5-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]] 1660 // CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP17]] 1661 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 1662 // CHECK5-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 1663 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] 1664 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP16]], i64 4, i1 false), !llvm.access.group [[ACC_GRP17]] 1665 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1666 // CHECK5: omp.body.continue: 1667 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1668 // CHECK5: omp.inner.for.inc: 1669 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 1670 // CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP18]], 1 1671 // CHECK5-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 1672 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 1673 // CHECK5: omp.inner.for.end: 1674 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1675 // CHECK5: omp.loop.exit: 1676 // CHECK5-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1677 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 1678 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP20]]) 1679 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1680 // CHECK5-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 1681 // CHECK5-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1682 // CHECK5: .omp.final.then: 1683 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 1684 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 1685 // CHECK5: .omp.final.done: 1686 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1687 // CHECK5-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 1688 // CHECK5-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] 1689 // CHECK5: .omp.lastprivate.then: 1690 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR3]], align 4 1691 // CHECK5-NEXT: store i32 [[TMP25]], ptr [[T_VAR_ADDR]], align 4 1692 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC4]], i64 8, i1 false) 1693 // CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0 1694 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 1695 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP26]] 1696 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1697 // CHECK5: omp.arraycpy.body: 1698 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR5]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1699 // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1700 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false) 1701 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1702 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1703 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP26]] 1704 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] 1705 // CHECK5: omp.arraycpy.done13: 1706 // CHECK5-NEXT: [[TMP27:%.*]] = load ptr, ptr [[_TMP7]], align 8 1707 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP27]], i64 4, i1 false) 1708 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] 1709 // CHECK5: .omp.lastprivate.done: 1710 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] 1711 // CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 1712 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2 1713 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1714 // CHECK5: arraydestroy.body: 1715 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1716 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1717 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1718 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] 1719 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] 1720 // CHECK5: arraydestroy.done15: 1721 // CHECK5-NEXT: ret void 1722 // 1723 // 1724 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1725 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1726 // CHECK5-NEXT: entry: 1727 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1728 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1729 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1730 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1731 // CHECK5-NEXT: ret void 1732 // 1733 // 1734 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1735 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1736 // CHECK5-NEXT: entry: 1737 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1738 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1739 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1740 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1741 // CHECK5-NEXT: store i32 0, ptr [[F]], align 4 1742 // CHECK5-NEXT: ret void 1743 // 1744 // 1745 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1746 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1747 // CHECK5-NEXT: entry: 1748 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1749 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1750 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1751 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1752 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1753 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1754 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1755 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1756 // CHECK5-NEXT: ret void 1757 // 1758 // 1759 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1760 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1761 // CHECK5-NEXT: entry: 1762 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1763 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1764 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1765 // CHECK5-NEXT: ret void 1766 // 1767 // 1768 // CHECK7-LABEL: define {{[^@]+}}@main 1769 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 1770 // CHECK7-NEXT: entry: 1771 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1772 // CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 1773 // CHECK7-NEXT: [[G1:%.*]] = alloca ptr, align 4 1774 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1775 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1776 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1777 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1778 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 4 1779 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1780 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1781 // CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 1782 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 1783 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 1784 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 1785 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1786 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1787 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 1788 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 1789 // CHECK7-NEXT: store ptr [[G]], ptr [[G1]], align 4 1790 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1791 // CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 4 1792 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false) 1793 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00) 1794 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 1 1795 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) 1796 // CHECK7-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 1797 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 1798 // CHECK7-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 1799 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 1800 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 1801 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1802 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 1803 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 1804 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 1805 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 1806 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1807 // CHECK7-NEXT: store ptr [[VEC]], ptr [[TMP6]], align 4 1808 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1809 // CHECK7-NEXT: store ptr [[VEC]], ptr [[TMP7]], align 4 1810 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1811 // CHECK7-NEXT: store ptr null, ptr [[TMP8]], align 4 1812 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1813 // CHECK7-NEXT: store i32 [[TMP2]], ptr [[TMP9]], align 4 1814 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1815 // CHECK7-NEXT: store i32 [[TMP2]], ptr [[TMP10]], align 4 1816 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1817 // CHECK7-NEXT: store ptr null, ptr [[TMP11]], align 4 1818 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1819 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 4 1820 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1821 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 4 1822 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1823 // CHECK7-NEXT: store ptr null, ptr [[TMP14]], align 4 1824 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1825 // CHECK7-NEXT: store ptr [[TMP3]], ptr [[TMP15]], align 4 1826 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1827 // CHECK7-NEXT: store ptr [[TMP3]], ptr [[TMP16]], align 4 1828 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1829 // CHECK7-NEXT: store ptr null, ptr [[TMP17]], align 4 1830 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1831 // CHECK7-NEXT: store i32 [[TMP5]], ptr [[TMP18]], align 4 1832 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1833 // CHECK7-NEXT: store i32 [[TMP5]], ptr [[TMP19]], align 4 1834 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1835 // CHECK7-NEXT: store ptr null, ptr [[TMP20]], align 4 1836 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1837 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1838 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1839 // CHECK7-NEXT: store i32 3, ptr [[TMP23]], align 4 1840 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1841 // CHECK7-NEXT: store i32 5, ptr [[TMP24]], align 4 1842 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1843 // CHECK7-NEXT: store ptr [[TMP21]], ptr [[TMP25]], align 4 1844 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1845 // CHECK7-NEXT: store ptr [[TMP22]], ptr [[TMP26]], align 4 1846 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1847 // CHECK7-NEXT: store ptr @.offload_sizes, ptr [[TMP27]], align 4 1848 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1849 // CHECK7-NEXT: store ptr @.offload_maptypes, ptr [[TMP28]], align 4 1850 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1851 // CHECK7-NEXT: store ptr null, ptr [[TMP29]], align 4 1852 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1853 // CHECK7-NEXT: store ptr null, ptr [[TMP30]], align 4 1854 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1855 // CHECK7-NEXT: store i64 2, ptr [[TMP31]], align 8 1856 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1857 // CHECK7-NEXT: store i64 0, ptr [[TMP32]], align 8 1858 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1859 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP33]], align 4 1860 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1861 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP34]], align 4 1862 // CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1863 // CHECK7-NEXT: store i32 0, ptr [[TMP35]], align 4 1864 // CHECK7-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, ptr [[KERNEL_ARGS]]) 1865 // CHECK7-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 1866 // CHECK7-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1867 // CHECK7: omp_offload.failed: 1868 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(ptr [[VEC]], i32 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]], i32 [[TMP5]]) #[[ATTR4:[0-9]+]] 1869 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 1870 // CHECK7: omp_offload.cont: 1871 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1872 // CHECK7-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 1873 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1874 // CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1875 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1876 // CHECK7: arraydestroy.body: 1877 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1878 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1879 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1880 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1881 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1882 // CHECK7: arraydestroy.done2: 1883 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 1884 // CHECK7-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4 1885 // CHECK7-NEXT: ret i32 [[TMP39]] 1886 // 1887 // 1888 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1889 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1890 // CHECK7-NEXT: entry: 1891 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1892 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1893 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1894 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1895 // CHECK7-NEXT: ret void 1896 // 1897 // 1898 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1899 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1900 // CHECK7-NEXT: entry: 1901 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1902 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1903 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1904 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1905 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1906 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1907 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1908 // CHECK7-NEXT: ret void 1909 // 1910 // 1911 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 1912 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { 1913 // CHECK7-NEXT: entry: 1914 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1915 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1916 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1917 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1918 // CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 1919 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1920 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1921 // CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 1922 // CHECK7-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1923 // CHECK7-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1924 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1925 // CHECK7-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1926 // CHECK7-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 1927 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1928 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1929 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1930 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 1931 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1932 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 1933 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1934 // CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 1935 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[SVAR_ADDR]], align 4 1936 // CHECK7-NEXT: store i32 [[TMP6]], ptr [[SVAR_CASTED]], align 4 1937 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 1938 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]], i32 [[TMP7]]) 1939 // CHECK7-NEXT: ret void 1940 // 1941 // 1942 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined 1943 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] { 1944 // CHECK7-NEXT: entry: 1945 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1946 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1947 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1948 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1949 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1950 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1951 // CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 1952 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1953 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1954 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1955 // CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1956 // CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1957 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1958 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1959 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 1960 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 1961 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 1962 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1963 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 1964 // CHECK7-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 1965 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 1966 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1967 // CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 1968 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1969 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1970 // CHECK7-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1971 // CHECK7-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1972 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1973 // CHECK7-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1974 // CHECK7-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 1975 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1976 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1977 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1978 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 1979 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1980 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1981 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1982 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1983 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 1984 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1985 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1986 // CHECK7: arrayctor.loop: 1987 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1988 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1989 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 1990 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1991 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1992 // CHECK7: arrayctor.cont: 1993 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 1994 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 1995 // CHECK7-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 1996 // CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1997 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 1998 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1999 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2000 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 2001 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2002 // CHECK7: cond.true: 2003 // CHECK7-NEXT: br label [[COND_END:%.*]] 2004 // CHECK7: cond.false: 2005 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2006 // CHECK7-NEXT: br label [[COND_END]] 2007 // CHECK7: cond.end: 2008 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2009 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2010 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2011 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 2012 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2013 // CHECK7: omp.inner.for.cond: 2014 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 2015 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 2016 // CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2017 // CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2018 // CHECK7: omp.inner.for.cond.cleanup: 2019 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2020 // CHECK7: omp.inner.for.body: 2021 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP6]] 2022 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 2023 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP6]] 2024 // CHECK7-NEXT: store i32 [[TMP13]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP6]] 2025 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP6]] 2026 // CHECK7-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP6]] 2027 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[SVAR7]], align 4, !llvm.access.group [[ACC_GRP6]] 2028 // CHECK7-NEXT: store i32 [[TMP16]], ptr [[SVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP6]] 2029 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP6]] 2030 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined.omp_outlined, i32 [[TMP11]], i32 [[TMP12]], ptr [[VEC3]], i32 [[TMP14]], ptr [[S_ARR4]], ptr [[TMP15]], i32 [[TMP17]]), !llvm.access.group [[ACC_GRP6]] 2031 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2032 // CHECK7: omp.inner.for.inc: 2033 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 2034 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP6]] 2035 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 2036 // CHECK7-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 2037 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 2038 // CHECK7: omp.inner.for.end: 2039 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2040 // CHECK7: omp.loop.exit: 2041 // CHECK7-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2042 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 2043 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP21]]) 2044 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2045 // CHECK7-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 2046 // CHECK7-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2047 // CHECK7: .omp.final.then: 2048 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 2049 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 2050 // CHECK7: .omp.final.done: 2051 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2052 // CHECK7-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 2053 // CHECK7-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] 2054 // CHECK7: .omp.lastprivate.then: 2055 // CHECK7-NEXT: [[TMP26:%.*]] = load i32, ptr [[T_VAR2]], align 4 2056 // CHECK7-NEXT: store i32 [[TMP26]], ptr [[T_VAR_ADDR]], align 4 2057 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) 2058 // CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0 2059 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i32 2 2060 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP27]] 2061 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2062 // CHECK7: omp.arraycpy.body: 2063 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2064 // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2065 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false) 2066 // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2067 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2068 // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] 2069 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] 2070 // CHECK7: omp.arraycpy.done10: 2071 // CHECK7-NEXT: [[TMP28:%.*]] = load ptr, ptr [[_TMP6]], align 4 2072 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP3]], ptr align 4 [[TMP28]], i32 4, i1 false) 2073 // CHECK7-NEXT: [[TMP29:%.*]] = load i32, ptr [[SVAR7]], align 4 2074 // CHECK7-NEXT: store i32 [[TMP29]], ptr [[SVAR_ADDR]], align 4 2075 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] 2076 // CHECK7: .omp.lastprivate.done: 2077 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 2078 // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 2079 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 2080 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2081 // CHECK7: arraydestroy.body: 2082 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2083 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2084 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2085 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 2086 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 2087 // CHECK7: arraydestroy.done12: 2088 // CHECK7-NEXT: ret void 2089 // 2090 // 2091 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined.omp_outlined 2092 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] { 2093 // CHECK7-NEXT: entry: 2094 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2095 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2096 // CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 2097 // CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 2098 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 2099 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2100 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 2101 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 2102 // CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 2103 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4 2104 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2105 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2106 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2107 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2108 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2109 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2110 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 2111 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 2112 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 2113 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2114 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 2115 // CHECK7-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 2116 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2117 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2118 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2119 // CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 2120 // CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 2121 // CHECK7-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 2122 // CHECK7-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 2123 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 2124 // CHECK7-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 2125 // CHECK7-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 2126 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 2127 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 2128 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 2129 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 2130 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2131 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2132 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 2133 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 2134 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4 2135 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 2136 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2137 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2138 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 2139 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 2140 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2141 // CHECK7: arrayctor.loop: 2142 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2143 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2144 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 2145 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2146 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2147 // CHECK7: arrayctor.cont: 2148 // CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 2149 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 2150 // CHECK7-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 2151 // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2152 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 2153 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2154 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2155 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 2156 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2157 // CHECK7: cond.true: 2158 // CHECK7-NEXT: br label [[COND_END:%.*]] 2159 // CHECK7: cond.false: 2160 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2161 // CHECK7-NEXT: br label [[COND_END]] 2162 // CHECK7: cond.end: 2163 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] 2164 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2165 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2166 // CHECK7-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 2167 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2168 // CHECK7: omp.inner.for.cond: 2169 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 2170 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 2171 // CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 2172 // CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2173 // CHECK7: omp.inner.for.cond.cleanup: 2174 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2175 // CHECK7: omp.inner.for.body: 2176 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 2177 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 2178 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2179 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 2180 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP10]] 2181 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 2182 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP15]] 2183 // CHECK7-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] 2184 // CHECK7-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP10]] 2185 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 2186 // CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] 2187 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP16]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] 2188 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2189 // CHECK7: omp.body.continue: 2190 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2191 // CHECK7: omp.inner.for.inc: 2192 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 2193 // CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP18]], 1 2194 // CHECK7-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 2195 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 2196 // CHECK7: omp.inner.for.end: 2197 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2198 // CHECK7: omp.loop.exit: 2199 // CHECK7-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2200 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 2201 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP20]]) 2202 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2203 // CHECK7-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 2204 // CHECK7-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2205 // CHECK7: .omp.final.then: 2206 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 2207 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 2208 // CHECK7: .omp.final.done: 2209 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2210 // CHECK7-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 2211 // CHECK7-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] 2212 // CHECK7: .omp.lastprivate.then: 2213 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR2]], align 4 2214 // CHECK7-NEXT: store i32 [[TMP25]], ptr [[T_VAR_ADDR]], align 4 2215 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) 2216 // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0 2217 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 2218 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP26]] 2219 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2220 // CHECK7: omp.arraycpy.body: 2221 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2222 // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2223 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false) 2224 // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2225 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2226 // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP26]] 2227 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] 2228 // CHECK7: omp.arraycpy.done12: 2229 // CHECK7-NEXT: [[TMP27:%.*]] = load ptr, ptr [[_TMP6]], align 4 2230 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP27]], i32 4, i1 false) 2231 // CHECK7-NEXT: [[TMP28:%.*]] = load i32, ptr [[SVAR7]], align 4 2232 // CHECK7-NEXT: store i32 [[TMP28]], ptr [[SVAR_ADDR]], align 4 2233 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] 2234 // CHECK7: .omp.lastprivate.done: 2235 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 2236 // CHECK7-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 2237 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 2 2238 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2239 // CHECK7: arraydestroy.body: 2240 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2241 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2242 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2243 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] 2244 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] 2245 // CHECK7: arraydestroy.done14: 2246 // CHECK7-NEXT: ret void 2247 // 2248 // 2249 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2250 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2251 // CHECK7-NEXT: entry: 2252 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2253 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2254 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2255 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 2256 // CHECK7-NEXT: ret void 2257 // 2258 // 2259 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2260 // CHECK7-SAME: () #[[ATTR1]] comdat { 2261 // CHECK7-NEXT: entry: 2262 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2263 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2264 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2265 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2266 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2267 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 4 2268 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4 2269 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2270 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 2271 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 2272 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 2273 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2274 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2275 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 2276 // CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 4 2277 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 2278 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 2279 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 2280 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 2281 // CHECK7-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 2282 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 2283 // CHECK7-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 2284 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 2285 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 2286 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 2287 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 2288 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2289 // CHECK7-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 4 2290 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2291 // CHECK7-NEXT: store ptr [[VEC]], ptr [[TMP5]], align 4 2292 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2293 // CHECK7-NEXT: store ptr null, ptr [[TMP6]], align 4 2294 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2295 // CHECK7-NEXT: store i32 [[TMP2]], ptr [[TMP7]], align 4 2296 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2297 // CHECK7-NEXT: store i32 [[TMP2]], ptr [[TMP8]], align 4 2298 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2299 // CHECK7-NEXT: store ptr null, ptr [[TMP9]], align 4 2300 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2301 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[TMP10]], align 4 2302 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2303 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[TMP11]], align 4 2304 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2305 // CHECK7-NEXT: store ptr null, ptr [[TMP12]], align 4 2306 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2307 // CHECK7-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 4 2308 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2309 // CHECK7-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 4 2310 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2311 // CHECK7-NEXT: store ptr null, ptr [[TMP15]], align 4 2312 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2313 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2314 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2315 // CHECK7-NEXT: store i32 3, ptr [[TMP18]], align 4 2316 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2317 // CHECK7-NEXT: store i32 4, ptr [[TMP19]], align 4 2318 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2319 // CHECK7-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 4 2320 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2321 // CHECK7-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 4 2322 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2323 // CHECK7-NEXT: store ptr @.offload_sizes.1, ptr [[TMP22]], align 4 2324 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2325 // CHECK7-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP23]], align 4 2326 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 2327 // CHECK7-NEXT: store ptr null, ptr [[TMP24]], align 4 2328 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 2329 // CHECK7-NEXT: store ptr null, ptr [[TMP25]], align 4 2330 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 2331 // CHECK7-NEXT: store i64 2, ptr [[TMP26]], align 8 2332 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 2333 // CHECK7-NEXT: store i64 0, ptr [[TMP27]], align 8 2334 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 2335 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 2336 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 2337 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4 2338 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 2339 // CHECK7-NEXT: store i32 0, ptr [[TMP30]], align 4 2340 // CHECK7-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.region_id, ptr [[KERNEL_ARGS]]) 2341 // CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 2342 // CHECK7-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2343 // CHECK7: omp_offload.failed: 2344 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50(ptr [[VEC]], i32 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]] 2345 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 2346 // CHECK7: omp_offload.cont: 2347 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 2348 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 2349 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 2350 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2351 // CHECK7: arraydestroy.body: 2352 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2353 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2354 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2355 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2356 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 2357 // CHECK7: arraydestroy.done2: 2358 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 2359 // CHECK7-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 2360 // CHECK7-NEXT: ret i32 [[TMP34]] 2361 // 2362 // 2363 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2364 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2365 // CHECK7-NEXT: entry: 2366 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2367 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2368 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2369 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2370 // CHECK7-NEXT: store float 0.000000e+00, ptr [[F]], align 4 2371 // CHECK7-NEXT: ret void 2372 // 2373 // 2374 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2375 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2376 // CHECK7-NEXT: entry: 2377 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2378 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2379 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2380 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2381 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2382 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2383 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2384 // CHECK7-NEXT: store float [[TMP0]], ptr [[F]], align 4 2385 // CHECK7-NEXT: ret void 2386 // 2387 // 2388 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2389 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2390 // CHECK7-NEXT: entry: 2391 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2392 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2393 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2394 // CHECK7-NEXT: ret void 2395 // 2396 // 2397 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2398 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2399 // CHECK7-NEXT: entry: 2400 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2401 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2402 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2403 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2404 // CHECK7-NEXT: ret void 2405 // 2406 // 2407 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2408 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2409 // CHECK7-NEXT: entry: 2410 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2411 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2412 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2413 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2414 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2415 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2416 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 2417 // CHECK7-NEXT: ret void 2418 // 2419 // 2420 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50 2421 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 2422 // CHECK7-NEXT: entry: 2423 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 2424 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2425 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 2426 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 2427 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4 2428 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2429 // CHECK7-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 2430 // CHECK7-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 2431 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 2432 // CHECK7-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 2433 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 2434 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 2435 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 2436 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 2437 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 2438 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 2439 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 2440 // CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 2441 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) 2442 // CHECK7-NEXT: ret void 2443 // 2444 // 2445 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined 2446 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 2447 // CHECK7-NEXT: entry: 2448 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2449 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2450 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 2451 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2452 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 2453 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 2454 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4 2455 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2456 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2457 // CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2458 // CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2459 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2460 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2461 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 2462 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 2463 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 2464 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2465 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 2466 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2467 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2468 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2469 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2470 // CHECK7-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 2471 // CHECK7-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 2472 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 2473 // CHECK7-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 2474 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 2475 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 2476 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 2477 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 2478 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 2479 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 2480 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2481 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2482 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 2483 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 2484 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2485 // CHECK7: arrayctor.loop: 2486 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2487 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2488 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 2489 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2490 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2491 // CHECK7: arrayctor.cont: 2492 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 2493 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 2494 // CHECK7-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 2495 // CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2496 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 2497 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2498 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2499 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 2500 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2501 // CHECK7: cond.true: 2502 // CHECK7-NEXT: br label [[COND_END:%.*]] 2503 // CHECK7: cond.false: 2504 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2505 // CHECK7-NEXT: br label [[COND_END]] 2506 // CHECK7: cond.end: 2507 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2508 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2509 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2510 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 2511 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2512 // CHECK7: omp.inner.for.cond: 2513 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] 2514 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 2515 // CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2516 // CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2517 // CHECK7: omp.inner.for.cond.cleanup: 2518 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2519 // CHECK7: omp.inner.for.body: 2520 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]] 2521 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 2522 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP15]] 2523 // CHECK7-NEXT: store i32 [[TMP13]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP15]] 2524 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP15]] 2525 // CHECK7-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP15]] 2526 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined.omp_outlined, i32 [[TMP11]], i32 [[TMP12]], ptr [[VEC3]], i32 [[TMP14]], ptr [[S_ARR4]], ptr [[TMP15]]), !llvm.access.group [[ACC_GRP15]] 2527 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2528 // CHECK7: omp.inner.for.inc: 2529 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 2530 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]] 2531 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] 2532 // CHECK7-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 2533 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 2534 // CHECK7: omp.inner.for.end: 2535 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2536 // CHECK7: omp.loop.exit: 2537 // CHECK7-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2538 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 2539 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) 2540 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2541 // CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 2542 // CHECK7-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2543 // CHECK7: .omp.final.then: 2544 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 2545 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 2546 // CHECK7: .omp.final.done: 2547 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2548 // CHECK7-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 2549 // CHECK7-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] 2550 // CHECK7: .omp.lastprivate.then: 2551 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR2]], align 4 2552 // CHECK7-NEXT: store i32 [[TMP24]], ptr [[T_VAR_ADDR]], align 4 2553 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) 2554 // CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0 2555 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i32 2 2556 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN8]], [[TMP25]] 2557 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2558 // CHECK7: omp.arraycpy.body: 2559 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2560 // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN8]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2561 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false) 2562 // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2563 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2564 // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP25]] 2565 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]] 2566 // CHECK7: omp.arraycpy.done9: 2567 // CHECK7-NEXT: [[TMP26:%.*]] = load ptr, ptr [[_TMP6]], align 4 2568 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP3]], ptr align 4 [[TMP26]], i32 4, i1 false) 2569 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] 2570 // CHECK7: .omp.lastprivate.done: 2571 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 2572 // CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 2573 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 2574 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2575 // CHECK7: arraydestroy.body: 2576 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2577 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2578 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2579 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 2580 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 2581 // CHECK7: arraydestroy.done11: 2582 // CHECK7-NEXT: ret void 2583 // 2584 // 2585 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined.omp_outlined 2586 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 2587 // CHECK7-NEXT: entry: 2588 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2589 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2590 // CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 2591 // CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 2592 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 2593 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2594 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 2595 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 2596 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4 2597 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2598 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2599 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2600 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2601 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2602 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2603 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 2604 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 2605 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 2606 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2607 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 2608 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2609 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2610 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2611 // CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 2612 // CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 2613 // CHECK7-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 2614 // CHECK7-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 2615 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 2616 // CHECK7-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 2617 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 2618 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 2619 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 2620 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 2621 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2622 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2623 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 2624 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 2625 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4 2626 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 2627 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2628 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2629 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 2630 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 2631 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2632 // CHECK7: arrayctor.loop: 2633 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2634 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2635 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 2636 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2637 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2638 // CHECK7: arrayctor.cont: 2639 // CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 2640 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 2641 // CHECK7-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 2642 // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2643 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 2644 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2645 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2646 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 2647 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2648 // CHECK7: cond.true: 2649 // CHECK7-NEXT: br label [[COND_END:%.*]] 2650 // CHECK7: cond.false: 2651 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2652 // CHECK7-NEXT: br label [[COND_END]] 2653 // CHECK7: cond.end: 2654 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] 2655 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2656 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2657 // CHECK7-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 2658 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2659 // CHECK7: omp.inner.for.cond: 2660 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] 2661 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] 2662 // CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 2663 // CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2664 // CHECK7: omp.inner.for.cond.cleanup: 2665 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2666 // CHECK7: omp.inner.for.body: 2667 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 2668 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 2669 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2670 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 2671 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP18]] 2672 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 2673 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP15]] 2674 // CHECK7-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] 2675 // CHECK7-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP18]] 2676 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 2677 // CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] 2678 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP16]], i32 4, i1 false), !llvm.access.group [[ACC_GRP18]] 2679 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2680 // CHECK7: omp.body.continue: 2681 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2682 // CHECK7: omp.inner.for.inc: 2683 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 2684 // CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], 1 2685 // CHECK7-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 2686 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 2687 // CHECK7: omp.inner.for.end: 2688 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2689 // CHECK7: omp.loop.exit: 2690 // CHECK7-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2691 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 2692 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP20]]) 2693 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2694 // CHECK7-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 2695 // CHECK7-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2696 // CHECK7: .omp.final.then: 2697 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 2698 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 2699 // CHECK7: .omp.final.done: 2700 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2701 // CHECK7-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 2702 // CHECK7-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] 2703 // CHECK7: .omp.lastprivate.then: 2704 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR2]], align 4 2705 // CHECK7-NEXT: store i32 [[TMP25]], ptr [[T_VAR_ADDR]], align 4 2706 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) 2707 // CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0 2708 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 2709 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP26]] 2710 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2711 // CHECK7: omp.arraycpy.body: 2712 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2713 // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2714 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false) 2715 // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2716 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2717 // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP26]] 2718 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] 2719 // CHECK7: omp.arraycpy.done11: 2720 // CHECK7-NEXT: [[TMP27:%.*]] = load ptr, ptr [[_TMP6]], align 4 2721 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP27]], i32 4, i1 false) 2722 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] 2723 // CHECK7: .omp.lastprivate.done: 2724 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 2725 // CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 2726 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2 2727 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2728 // CHECK7: arraydestroy.body: 2729 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2730 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2731 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2732 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 2733 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 2734 // CHECK7: arraydestroy.done13: 2735 // CHECK7-NEXT: ret void 2736 // 2737 // 2738 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2739 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2740 // CHECK7-NEXT: entry: 2741 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2742 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2743 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2744 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 2745 // CHECK7-NEXT: ret void 2746 // 2747 // 2748 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2749 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2750 // CHECK7-NEXT: entry: 2751 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2752 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2753 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2754 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2755 // CHECK7-NEXT: store i32 0, ptr [[F]], align 4 2756 // CHECK7-NEXT: ret void 2757 // 2758 // 2759 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2760 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2761 // CHECK7-NEXT: entry: 2762 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2763 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2764 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2765 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2766 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2767 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2768 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2769 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 2770 // CHECK7-NEXT: ret void 2771 // 2772 // 2773 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2774 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2775 // CHECK7-NEXT: entry: 2776 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2777 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2778 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2779 // CHECK7-NEXT: ret void 2780 // 2781 // 2782 // CHECK9-LABEL: define {{[^@]+}}@main 2783 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 2784 // CHECK9-NEXT: entry: 2785 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2786 // CHECK9-NEXT: [[G:%.*]] = alloca double, align 8 2787 // CHECK9-NEXT: [[G1:%.*]] = alloca ptr, align 8 2788 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 2789 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 2790 // CHECK9-NEXT: store ptr [[G]], ptr [[G1]], align 8 2791 // CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 2792 // CHECK9-NEXT: store ptr [[G]], ptr [[TMP0]], align 8 2793 // CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 2794 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8 2795 // CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8 2796 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) 2797 // CHECK9-NEXT: ret i32 0 2798 // 2799 // 2800 // CHECK11-LABEL: define {{[^@]+}}@main 2801 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 2802 // CHECK11-NEXT: entry: 2803 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2804 // CHECK11-NEXT: [[G:%.*]] = alloca double, align 8 2805 // CHECK11-NEXT: [[G1:%.*]] = alloca ptr, align 4 2806 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 2807 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 2808 // CHECK11-NEXT: store ptr [[G]], ptr [[G1]], align 4 2809 // CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 2810 // CHECK11-NEXT: store ptr [[G]], ptr [[TMP0]], align 4 2811 // CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 2812 // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4 2813 // CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 4 2814 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]]) 2815 // CHECK11-NEXT: ret i32 0 2816 // 2817 // 2818 // CHECK13-LABEL: define {{[^@]+}}@main 2819 // CHECK13-SAME: () #[[ATTR0:[0-9]+]] { 2820 // CHECK13-NEXT: entry: 2821 // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2822 // CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 2823 // CHECK13-NEXT: [[G1:%.*]] = alloca ptr, align 8 2824 // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2825 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2826 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2827 // CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 2828 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 2829 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 2830 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2831 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2832 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2833 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2834 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 2835 // CHECK13-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 2836 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 2837 // CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 2838 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 2839 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 2840 // CHECK13-NEXT: [[SVAR:%.*]] = alloca i32, align 4 2841 // CHECK13-NEXT: [[I14:%.*]] = alloca i32, align 4 2842 // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 2843 // CHECK13-NEXT: store ptr [[G]], ptr [[G1]], align 8 2844 // CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 2845 // CHECK13-NEXT: store i32 0, ptr [[T_VAR]], align 4 2846 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false) 2847 // CHECK13-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00) 2848 // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1 2849 // CHECK13-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) 2850 // CHECK13-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 2851 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 2852 // CHECK13-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 2853 // CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8 2854 // CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR]], align 8 2855 // CHECK13-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR]], align 8 2856 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2857 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2858 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2859 // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2860 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 2861 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 2862 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2863 // CHECK13: arrayctor.loop: 2864 // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2865 // CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2866 // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 2867 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2868 // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2869 // CHECK13: arrayctor.cont: 2870 // CHECK13-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 2871 // CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 2872 // CHECK13-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 8 2873 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2874 // CHECK13: omp.inner.for.cond: 2875 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 2876 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 2877 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 2878 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2879 // CHECK13: omp.inner.for.cond.cleanup: 2880 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2881 // CHECK13: omp.inner.for.body: 2882 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 2883 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 2884 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2885 // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 2886 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP2]] 2887 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 2888 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 2889 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] 2890 // CHECK13-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] 2891 // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP2]] 2892 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 2893 // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 2894 // CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] 2895 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] 2896 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2897 // CHECK13: omp.body.continue: 2898 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2899 // CHECK13: omp.inner.for.inc: 2900 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 2901 // CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 2902 // CHECK13-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 2903 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 2904 // CHECK13: omp.inner.for.end: 2905 // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 2906 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4 2907 // CHECK13-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 2908 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC3]], i64 8, i1 false) 2909 // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 2910 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i64 2 2911 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP15]] 2912 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2913 // CHECK13: omp.arraycpy.body: 2914 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2915 // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN10]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2916 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false) 2917 // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2918 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2919 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP15]] 2920 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] 2921 // CHECK13: omp.arraycpy.done11: 2922 // CHECK13-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 8 2923 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i64 4, i1 false) 2924 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[SVAR]], align 4 2925 // CHECK13-NEXT: store i32 [[TMP17]], ptr @_ZZ4mainE4svar, align 4 2926 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] 2927 // CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 2928 // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 2929 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2930 // CHECK13: arraydestroy.body: 2931 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2932 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2933 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 2934 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 2935 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 2936 // CHECK13: arraydestroy.done13: 2937 // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 2938 // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 2939 // CHECK13-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 2940 // CHECK13-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN15]], i64 2 2941 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY16:%.*]] 2942 // CHECK13: arraydestroy.body16: 2943 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi ptr [ [[TMP19]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] 2944 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST17]], i64 -1 2945 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR3]] 2946 // CHECK13-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] 2947 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] 2948 // CHECK13: arraydestroy.done20: 2949 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] 2950 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 2951 // CHECK13-NEXT: ret i32 [[TMP20]] 2952 // 2953 // 2954 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2955 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 2956 // CHECK13-NEXT: entry: 2957 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2958 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2959 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2960 // CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2961 // CHECK13-NEXT: ret void 2962 // 2963 // 2964 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2965 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2966 // CHECK13-NEXT: entry: 2967 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2968 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2969 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2970 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2971 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2972 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2973 // CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2974 // CHECK13-NEXT: ret void 2975 // 2976 // 2977 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2978 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2979 // CHECK13-NEXT: entry: 2980 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2981 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2982 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2983 // CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] 2984 // CHECK13-NEXT: ret void 2985 // 2986 // 2987 // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2988 // CHECK13-SAME: () #[[ATTR1]] comdat { 2989 // CHECK13-NEXT: entry: 2990 // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2991 // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2992 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2993 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2994 // CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2995 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 2996 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 2997 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2998 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2999 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3000 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3001 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 3002 // CHECK13-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 3003 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 3004 // CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 3005 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 3006 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 3007 // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 3008 // CHECK13-NEXT: store i32 0, ptr [[T_VAR]], align 4 3009 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 3010 // CHECK13-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 3011 // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 3012 // CHECK13-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 3013 // CHECK13-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 3014 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 3015 // CHECK13-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 3016 // CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8 3017 // CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR]], align 8 3018 // CHECK13-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR]], align 8 3019 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3020 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 3021 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3022 // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 3023 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 3024 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 3025 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 3026 // CHECK13: arrayctor.loop: 3027 // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 3028 // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 3029 // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 3030 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 3031 // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 3032 // CHECK13: arrayctor.cont: 3033 // CHECK13-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 3034 // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 3035 // CHECK13-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 8 3036 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3037 // CHECK13: omp.inner.for.cond: 3038 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 3039 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 3040 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 3041 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3042 // CHECK13: omp.inner.for.cond.cleanup: 3043 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3044 // CHECK13: omp.inner.for.body: 3045 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 3046 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 3047 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3048 // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 3049 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP6]] 3050 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 3051 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 3052 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] 3053 // CHECK13-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] 3054 // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP6]] 3055 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 3056 // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 3057 // CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] 3058 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] 3059 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3060 // CHECK13: omp.body.continue: 3061 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3062 // CHECK13: omp.inner.for.inc: 3063 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 3064 // CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 3065 // CHECK13-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 3066 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 3067 // CHECK13: omp.inner.for.end: 3068 // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 3069 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4 3070 // CHECK13-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 3071 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC3]], i64 8, i1 false) 3072 // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 3073 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 3074 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP15]] 3075 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3076 // CHECK13: omp.arraycpy.body: 3077 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3078 // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN10]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3079 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false) 3080 // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3081 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3082 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP15]] 3083 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]] 3084 // CHECK13: omp.arraycpy.done11: 3085 // CHECK13-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 8 3086 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i64 4, i1 false) 3087 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] 3088 // CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 3089 // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 3090 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3091 // CHECK13: arraydestroy.body: 3092 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3093 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3094 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 3095 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 3096 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 3097 // CHECK13: arraydestroy.done13: 3098 // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 3099 // CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 3100 // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2 3101 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY15:%.*]] 3102 // CHECK13: arraydestroy.body15: 3103 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi ptr [ [[TMP18]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] 3104 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST16]], i64 -1 3105 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] 3106 // CHECK13-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] 3107 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] 3108 // CHECK13: arraydestroy.done19: 3109 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] 3110 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 3111 // CHECK13-NEXT: ret i32 [[TMP19]] 3112 // 3113 // 3114 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3115 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3116 // CHECK13-NEXT: entry: 3117 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3118 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3119 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3120 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 3121 // CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4 3122 // CHECK13-NEXT: ret void 3123 // 3124 // 3125 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3126 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3127 // CHECK13-NEXT: entry: 3128 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3129 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3130 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3131 // CHECK13-NEXT: ret void 3132 // 3133 // 3134 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3135 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3136 // CHECK13-NEXT: entry: 3137 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3138 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3139 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3140 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 3141 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3142 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 3143 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 3144 // CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4 3145 // CHECK13-NEXT: ret void 3146 // 3147 // 3148 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3149 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3150 // CHECK13-NEXT: entry: 3151 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3152 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3153 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3154 // CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 3155 // CHECK13-NEXT: ret void 3156 // 3157 // 3158 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3159 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3160 // CHECK13-NEXT: entry: 3161 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3162 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3163 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3164 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3165 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3166 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3167 // CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 3168 // CHECK13-NEXT: ret void 3169 // 3170 // 3171 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3172 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3173 // CHECK13-NEXT: entry: 3174 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3175 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3176 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3177 // CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] 3178 // CHECK13-NEXT: ret void 3179 // 3180 // 3181 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3182 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3183 // CHECK13-NEXT: entry: 3184 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3185 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3186 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3187 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 3188 // CHECK13-NEXT: store i32 0, ptr [[F]], align 4 3189 // CHECK13-NEXT: ret void 3190 // 3191 // 3192 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3193 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3194 // CHECK13-NEXT: entry: 3195 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3196 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3197 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3198 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3199 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3200 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 3201 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3202 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 3203 // CHECK13-NEXT: ret void 3204 // 3205 // 3206 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3207 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3208 // CHECK13-NEXT: entry: 3209 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3210 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3211 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3212 // CHECK13-NEXT: ret void 3213 // 3214 // 3215 // CHECK15-LABEL: define {{[^@]+}}@main 3216 // CHECK15-SAME: () #[[ATTR0:[0-9]+]] { 3217 // CHECK15-NEXT: entry: 3218 // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3219 // CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 3220 // CHECK15-NEXT: [[G1:%.*]] = alloca ptr, align 4 3221 // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 3222 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3223 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3224 // CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 3225 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 3226 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 3227 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3228 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3229 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3230 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3231 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 3232 // CHECK15-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 3233 // CHECK15-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 3234 // CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 3235 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 3236 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 3237 // CHECK15-NEXT: [[SVAR:%.*]] = alloca i32, align 4 3238 // CHECK15-NEXT: [[I13:%.*]] = alloca i32, align 4 3239 // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 3240 // CHECK15-NEXT: store ptr [[G]], ptr [[G1]], align 4 3241 // CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 3242 // CHECK15-NEXT: store i32 0, ptr [[T_VAR]], align 4 3243 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false) 3244 // CHECK15-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00) 3245 // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 1 3246 // CHECK15-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) 3247 // CHECK15-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 3248 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 3249 // CHECK15-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 3250 // CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 4 3251 // CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR]], align 4 3252 // CHECK15-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR]], align 4 3253 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3254 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 3255 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3256 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 3257 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 3258 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 3259 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 3260 // CHECK15: arrayctor.loop: 3261 // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 3262 // CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 3263 // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 3264 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 3265 // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 3266 // CHECK15: arrayctor.cont: 3267 // CHECK15-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 3268 // CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 3269 // CHECK15-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 3270 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3271 // CHECK15: omp.inner.for.cond: 3272 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 3273 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 3274 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 3275 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3276 // CHECK15: omp.inner.for.cond.cleanup: 3277 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3278 // CHECK15: omp.inner.for.body: 3279 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 3280 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 3281 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3282 // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 3283 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP3]] 3284 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 3285 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP10]] 3286 // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] 3287 // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP3]] 3288 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 3289 // CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP12]] 3290 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] 3291 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3292 // CHECK15: omp.body.continue: 3293 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3294 // CHECK15: omp.inner.for.inc: 3295 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 3296 // CHECK15-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 3297 // CHECK15-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 3298 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 3299 // CHECK15: omp.inner.for.end: 3300 // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 3301 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4 3302 // CHECK15-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 3303 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 [[VEC3]], i32 8, i1 false) 3304 // CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 3305 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i32 2 3306 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP15]] 3307 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3308 // CHECK15: omp.arraycpy.body: 3309 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3310 // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN9]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3311 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false) 3312 // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3313 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3314 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP15]] 3315 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] 3316 // CHECK15: omp.arraycpy.done10: 3317 // CHECK15-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4 3318 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i32 4, i1 false) 3319 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[SVAR]], align 4 3320 // CHECK15-NEXT: store i32 [[TMP17]], ptr @_ZZ4mainE4svar, align 4 3321 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] 3322 // CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 3323 // CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 3324 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3325 // CHECK15: arraydestroy.body: 3326 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_ARRAYCPY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3327 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3328 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 3329 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 3330 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 3331 // CHECK15: arraydestroy.done12: 3332 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 3333 // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 3334 // CHECK15-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 3335 // CHECK15-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN14]], i32 2 3336 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY15:%.*]] 3337 // CHECK15: arraydestroy.body15: 3338 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi ptr [ [[TMP19]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] 3339 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST16]], i32 -1 3340 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] 3341 // CHECK15-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] 3342 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] 3343 // CHECK15: arraydestroy.done19: 3344 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] 3345 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 3346 // CHECK15-NEXT: ret i32 [[TMP20]] 3347 // 3348 // 3349 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3350 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3351 // CHECK15-NEXT: entry: 3352 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3353 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3354 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3355 // CHECK15-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 3356 // CHECK15-NEXT: ret void 3357 // 3358 // 3359 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3360 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3361 // CHECK15-NEXT: entry: 3362 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3363 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3364 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3365 // CHECK15-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 3366 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3367 // CHECK15-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 3368 // CHECK15-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 3369 // CHECK15-NEXT: ret void 3370 // 3371 // 3372 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3373 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3374 // CHECK15-NEXT: entry: 3375 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3376 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3377 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3378 // CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] 3379 // CHECK15-NEXT: ret void 3380 // 3381 // 3382 // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 3383 // CHECK15-SAME: () #[[ATTR1]] comdat { 3384 // CHECK15-NEXT: entry: 3385 // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3386 // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3387 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3388 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3389 // CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 3390 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 3391 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 3392 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3393 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3394 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3395 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3396 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 3397 // CHECK15-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 3398 // CHECK15-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 3399 // CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 3400 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 3401 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 3402 // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 3403 // CHECK15-NEXT: store i32 0, ptr [[T_VAR]], align 4 3404 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 3405 // CHECK15-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 3406 // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 3407 // CHECK15-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 3408 // CHECK15-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 3409 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 3410 // CHECK15-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 3411 // CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 4 3412 // CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR]], align 4 3413 // CHECK15-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR]], align 4 3414 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3415 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 3416 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3417 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 3418 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 3419 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 3420 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 3421 // CHECK15: arrayctor.loop: 3422 // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 3423 // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 3424 // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 3425 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 3426 // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 3427 // CHECK15: arrayctor.cont: 3428 // CHECK15-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 3429 // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 3430 // CHECK15-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 3431 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3432 // CHECK15: omp.inner.for.cond: 3433 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 3434 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]] 3435 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 3436 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3437 // CHECK15: omp.inner.for.cond.cleanup: 3438 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3439 // CHECK15: omp.inner.for.body: 3440 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 3441 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 3442 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3443 // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 3444 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP7]] 3445 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 3446 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP10]] 3447 // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] 3448 // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP7]] 3449 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 3450 // CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP12]] 3451 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] 3452 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3453 // CHECK15: omp.body.continue: 3454 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3455 // CHECK15: omp.inner.for.inc: 3456 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 3457 // CHECK15-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 3458 // CHECK15-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 3459 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 3460 // CHECK15: omp.inner.for.end: 3461 // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 3462 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4 3463 // CHECK15-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 3464 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 [[VEC3]], i32 8, i1 false) 3465 // CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 3466 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 3467 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP15]] 3468 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3469 // CHECK15: omp.arraycpy.body: 3470 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3471 // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN9]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3472 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false) 3473 // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3474 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3475 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP15]] 3476 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] 3477 // CHECK15: omp.arraycpy.done10: 3478 // CHECK15-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4 3479 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i32 4, i1 false) 3480 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] 3481 // CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 3482 // CHECK15-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 3483 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3484 // CHECK15: arraydestroy.body: 3485 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_ARRAYCPY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3486 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3487 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 3488 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 3489 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 3490 // CHECK15: arraydestroy.done12: 3491 // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 3492 // CHECK15-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 3493 // CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i32 2 3494 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY14:%.*]] 3495 // CHECK15: arraydestroy.body14: 3496 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST15:%.*]] = phi ptr [ [[TMP18]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT16:%.*]], [[ARRAYDESTROY_BODY14]] ] 3497 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT16]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST15]], i32 -1 3498 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR3]] 3499 // CHECK15-NEXT: [[ARRAYDESTROY_DONE17:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT16]], [[ARRAY_BEGIN13]] 3500 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE17]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY14]] 3501 // CHECK15: arraydestroy.done18: 3502 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] 3503 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 3504 // CHECK15-NEXT: ret i32 [[TMP19]] 3505 // 3506 // 3507 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3508 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3509 // CHECK15-NEXT: entry: 3510 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3511 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3512 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3513 // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 3514 // CHECK15-NEXT: store float 0.000000e+00, ptr [[F]], align 4 3515 // CHECK15-NEXT: ret void 3516 // 3517 // 3518 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3519 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3520 // CHECK15-NEXT: entry: 3521 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3522 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3523 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3524 // CHECK15-NEXT: ret void 3525 // 3526 // 3527 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3528 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3529 // CHECK15-NEXT: entry: 3530 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3531 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3532 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3533 // CHECK15-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 3534 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3535 // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 3536 // CHECK15-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 3537 // CHECK15-NEXT: store float [[TMP0]], ptr [[F]], align 4 3538 // CHECK15-NEXT: ret void 3539 // 3540 // 3541 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3542 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3543 // CHECK15-NEXT: entry: 3544 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3545 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3546 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3547 // CHECK15-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 3548 // CHECK15-NEXT: ret void 3549 // 3550 // 3551 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3552 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3553 // CHECK15-NEXT: entry: 3554 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3555 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3556 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3557 // CHECK15-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3558 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3559 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3560 // CHECK15-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 3561 // CHECK15-NEXT: ret void 3562 // 3563 // 3564 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3565 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3566 // CHECK15-NEXT: entry: 3567 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3568 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3569 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3570 // CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] 3571 // CHECK15-NEXT: ret void 3572 // 3573 // 3574 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3575 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3576 // CHECK15-NEXT: entry: 3577 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3578 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3579 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3580 // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 3581 // CHECK15-NEXT: store i32 0, ptr [[F]], align 4 3582 // CHECK15-NEXT: ret void 3583 // 3584 // 3585 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3586 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3587 // CHECK15-NEXT: entry: 3588 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3589 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3590 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3591 // CHECK15-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3592 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3593 // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 3594 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3595 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 3596 // CHECK15-NEXT: ret void 3597 // 3598 // 3599 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3600 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3601 // CHECK15-NEXT: entry: 3602 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3603 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3604 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3605 // CHECK15-NEXT: ret void 3606 // 3607