1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 12 13 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 16 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 23 24 // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region) 25 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 26 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 27 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 28 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 29 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 30 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 31 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 32 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 33 34 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 35 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17 36 37 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 38 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK7 39 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 40 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 41 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 42 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK9 43 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 44 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 45 46 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 47 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK11 48 49 // expected-no-diagnostics 50 #ifndef HEADER 51 #define HEADER 52 53 struct St { 54 int a, b; 55 St() : a(0), b(0) {} 56 St(const St &st) : a(st.a + st.b), b(0) {} 57 ~St() {} 58 }; 59 60 volatile int g = 1212; 61 volatile int &g1 = g; 62 63 template <class T> 64 struct S { 65 T f; 66 S(T a) : f(a + g) {} 67 S() : f(g) {} 68 S(const S &s, St t = St()) : f(s.f + t.a) {} 69 operator T() { return T(); } 70 ~S() {} 71 }; 72 73 74 template <typename T> 75 T tmain() { 76 S<T> test; 77 T t_var = T(); 78 T vec[] = {1, 2}; 79 S<T> s_arr[] = {1, 2}; 80 S<T> &var = test; 81 #pragma omp target teams distribute parallel for simd firstprivate(t_var, vec, s_arr, var) 82 for (int i = 0; i < 2; ++i) { 83 vec[i] = t_var; 84 s_arr[i] = var; 85 } 86 return T(); 87 } 88 89 S<float> test; 90 int t_var = 333; 91 int vec[] = {1, 2}; 92 S<float> s_arr[] = {1, 2}; 93 S<float> var(3); 94 95 int main() { 96 static int sivar; 97 #ifdef LAMBDA 98 [&]() { 99 #pragma omp target teams distribute parallel for simd firstprivate(g, g1, sivar) 100 for (int i = 0; i < 2; ++i) { 101 102 // Skip global and bound tid vars 103 // skip loop vars 104 g = 1; 105 g1 = 1; 106 sivar = 2; 107 108 // Skip global and bound tid vars, and prev lb and ub vars 109 // skip loop vars 110 111 // use of private vars 112 [&]() { 113 g = 2; 114 g1 = 2; 115 sivar = 4; 116 117 }(); 118 } 119 }(); 120 return 0; 121 #else 122 #pragma omp target teams distribute parallel for simd firstprivate(t_var, vec, s_arr, var, sivar) 123 for (int i = 0; i < 2; ++i) { 124 vec[i] = t_var; 125 s_arr[i] = var; 126 sivar += i; 127 } 128 return tmain<int>(); 129 #endif 130 } 131 132 133 134 135 136 // Skip global and bound tid vars 137 // Skip temp vars for loop 138 139 // param copy 140 141 // T_VAR and SIVAR 142 143 // preparation vars 144 145 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 146 147 // firstprivate(s_arr) 148 149 // firstprivate(var) 150 151 152 // Skip global and bound tid vars, and prev lb ub vars 153 // Skip temp vars for loop 154 155 // param copy 156 157 // T_VAR and SIVAR 158 159 // preparation vars 160 161 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 162 163 // firstprivate(s_arr) 164 165 // firstprivate(var) 166 167 168 169 170 171 172 // Skip global and bound tid vars 173 // Skip temp vars for loop 174 175 // param copy 176 177 // T_VAR and preparation variables 178 179 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 180 181 // firstprivate(s_arr) 182 183 // firstprivate(var) 184 185 186 // Skip global and bound tid vars 187 // Skip temp vars for loop 188 189 // param copy 190 191 // T_VAR and preparation variables 192 193 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 194 195 // firstprivate(s_arr) 196 197 // firstprivate(var) 198 199 200 #endif 201 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 202 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 203 // CHECK1-NEXT: entry: 204 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 205 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 206 // CHECK1-NEXT: ret void 207 // 208 // 209 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 210 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 211 // CHECK1-NEXT: entry: 212 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 213 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 214 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 215 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 216 // CHECK1-NEXT: ret void 217 // 218 // 219 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 220 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 221 // CHECK1-NEXT: entry: 222 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 223 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 224 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 225 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 226 // CHECK1-NEXT: ret void 227 // 228 // 229 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 230 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 231 // CHECK1-NEXT: entry: 232 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 233 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 234 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 235 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 236 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 237 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 238 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 239 // CHECK1-NEXT: ret void 240 // 241 // 242 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 243 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 244 // CHECK1-NEXT: entry: 245 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 246 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 247 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 248 // CHECK1-NEXT: ret void 249 // 250 // 251 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 252 // CHECK1-SAME: () #[[ATTR0]] { 253 // CHECK1-NEXT: entry: 254 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 255 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 256 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 257 // CHECK1-NEXT: ret void 258 // 259 // 260 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 261 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 262 // CHECK1-NEXT: entry: 263 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 264 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 265 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 266 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 267 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 268 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 269 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 270 // CHECK1-NEXT: ret void 271 // 272 // 273 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 274 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 275 // CHECK1-NEXT: entry: 276 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 277 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 278 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 279 // CHECK1: arraydestroy.body: 280 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 281 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 282 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 283 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 284 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 285 // CHECK1: arraydestroy.done1: 286 // CHECK1-NEXT: ret void 287 // 288 // 289 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 290 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 291 // CHECK1-NEXT: entry: 292 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 293 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 294 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 295 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 296 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 297 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 298 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 299 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 300 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 301 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 302 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 303 // CHECK1-NEXT: ret void 304 // 305 // 306 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 307 // CHECK1-SAME: () #[[ATTR0]] { 308 // CHECK1-NEXT: entry: 309 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 310 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 311 // CHECK1-NEXT: ret void 312 // 313 // 314 // CHECK1-LABEL: define {{[^@]+}}@main 315 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 316 // CHECK1-NEXT: entry: 317 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 318 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 319 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 320 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 321 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 322 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 323 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 324 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 325 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 326 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr @t_var, align 4 327 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 328 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 329 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 330 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 331 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 332 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 333 // CHECK1-NEXT: store ptr @vec, ptr [[TMP4]], align 8 334 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 335 // CHECK1-NEXT: store ptr @vec, ptr [[TMP5]], align 8 336 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 337 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 338 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 339 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP7]], align 8 340 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 341 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP8]], align 8 342 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 343 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 344 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 345 // CHECK1-NEXT: store ptr @s_arr, ptr [[TMP10]], align 8 346 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 347 // CHECK1-NEXT: store ptr @s_arr, ptr [[TMP11]], align 8 348 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 349 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 350 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 351 // CHECK1-NEXT: store ptr @var, ptr [[TMP13]], align 8 352 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 353 // CHECK1-NEXT: store ptr @var, ptr [[TMP14]], align 8 354 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 355 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 356 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 357 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP16]], align 8 358 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 359 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP17]], align 8 360 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 361 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 362 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 363 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 364 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 365 // CHECK1-NEXT: store i32 3, ptr [[TMP21]], align 4 366 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 367 // CHECK1-NEXT: store i32 5, ptr [[TMP22]], align 4 368 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 369 // CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8 370 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 371 // CHECK1-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8 372 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 373 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 8 374 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 375 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 8 376 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 377 // CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8 378 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 379 // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8 380 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 381 // CHECK1-NEXT: store i64 2, ptr [[TMP29]], align 8 382 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 383 // CHECK1-NEXT: store i64 0, ptr [[TMP30]], align 8 384 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 385 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 386 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 387 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 388 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 389 // CHECK1-NEXT: store i32 0, ptr [[TMP33]], align 4 390 // CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.region_id, ptr [[KERNEL_ARGS]]) 391 // CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 392 // CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 393 // CHECK1: omp_offload.failed: 394 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122(ptr @vec, i64 [[TMP1]], ptr @s_arr, ptr @var, i64 [[TMP3]]) #[[ATTR2]] 395 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 396 // CHECK1: omp_offload.cont: 397 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 398 // CHECK1-NEXT: ret i32 [[CALL]] 399 // 400 // 401 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 402 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 403 // CHECK1-NEXT: entry: 404 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 405 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 406 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 407 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 408 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 409 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 410 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 411 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 412 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 413 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 414 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 415 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 416 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 417 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 418 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 419 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 420 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 421 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 422 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 423 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 424 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 425 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]]) 426 // CHECK1-NEXT: ret void 427 // 428 // 429 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined 430 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 431 // CHECK1-NEXT: entry: 432 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 433 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 434 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 435 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 436 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 437 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 438 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 439 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 440 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 441 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 442 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 443 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 444 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 445 // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 446 // CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 447 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 448 // CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 449 // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 450 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 451 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 452 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 453 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 454 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 455 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 456 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 457 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 458 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 459 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 460 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 461 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 462 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 463 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 464 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 465 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 466 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 467 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) 468 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 469 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 470 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 471 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 472 // CHECK1: omp.arraycpy.body: 473 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 474 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 475 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 476 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 477 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 478 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 479 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 480 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 481 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 482 // CHECK1: omp.arraycpy.done3: 483 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 484 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 485 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 486 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 487 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 488 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 489 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 490 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 491 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 492 // CHECK1: cond.true: 493 // CHECK1-NEXT: br label [[COND_END:%.*]] 494 // CHECK1: cond.false: 495 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 496 // CHECK1-NEXT: br label [[COND_END]] 497 // CHECK1: cond.end: 498 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 499 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 500 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 501 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 502 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 503 // CHECK1: omp.inner.for.cond: 504 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] 505 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 506 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 507 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 508 // CHECK1: omp.inner.for.cond.cleanup: 509 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 510 // CHECK1: omp.inner.for.body: 511 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP5]] 512 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 513 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 514 // CHECK1-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 515 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP5]] 516 // CHECK1-NEXT: store i32 [[TMP15]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]] 517 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP5]] 518 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP5]] 519 // CHECK1-NEXT: store i32 [[TMP17]], ptr [[SIVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]] 520 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP5]] 521 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], ptr [[VEC1]], i64 [[TMP16]], ptr [[S_ARR2]], ptr [[VAR4]], i64 [[TMP18]]), !llvm.access.group [[ACC_GRP5]] 522 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 523 // CHECK1: omp.inner.for.inc: 524 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 525 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP5]] 526 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] 527 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 528 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 529 // CHECK1: omp.inner.for.end: 530 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 531 // CHECK1: omp.loop.exit: 532 // CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 533 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 534 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) 535 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 536 // CHECK1-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 537 // CHECK1-NEXT: br i1 [[TMP24]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 538 // CHECK1: .omp.final.then: 539 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 540 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 541 // CHECK1: .omp.final.done: 542 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 543 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 544 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 545 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 546 // CHECK1: arraydestroy.body: 547 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 548 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 549 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 550 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 551 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 552 // CHECK1: arraydestroy.done8: 553 // CHECK1-NEXT: ret void 554 // 555 // 556 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev 557 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 558 // CHECK1-NEXT: entry: 559 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 560 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 561 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 562 // CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 563 // CHECK1-NEXT: ret void 564 // 565 // 566 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 567 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 568 // CHECK1-NEXT: entry: 569 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 570 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 571 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 572 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 573 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 574 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 575 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 576 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 577 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 578 // CHECK1-NEXT: ret void 579 // 580 // 581 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev 582 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 583 // CHECK1-NEXT: entry: 584 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 585 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 586 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 587 // CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 588 // CHECK1-NEXT: ret void 589 // 590 // 591 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined.omp_outlined 592 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 593 // CHECK1-NEXT: entry: 594 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 595 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 596 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 597 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 598 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 599 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 600 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 601 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 602 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 603 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 604 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 605 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 606 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 607 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 608 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 609 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 610 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 611 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 612 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 613 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 614 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 615 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 616 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 617 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 618 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 619 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 620 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 621 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 622 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 623 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 624 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 625 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 626 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 627 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 628 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 629 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 630 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 631 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 632 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP4]] to i32 633 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 634 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 635 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 636 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 637 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) 638 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 639 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 640 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 641 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 642 // CHECK1: omp.arraycpy.body: 643 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 644 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 645 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 646 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 647 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 648 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 649 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 650 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 651 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 652 // CHECK1: omp.arraycpy.done4: 653 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 654 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP6]]) 655 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 656 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 657 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 658 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 659 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 660 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 661 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 662 // CHECK1: cond.true: 663 // CHECK1-NEXT: br label [[COND_END:%.*]] 664 // CHECK1: cond.false: 665 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 666 // CHECK1-NEXT: br label [[COND_END]] 667 // CHECK1: cond.end: 668 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] 669 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 670 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 671 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 672 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 673 // CHECK1: omp.inner.for.cond: 674 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] 675 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 676 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 677 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 678 // CHECK1: omp.inner.for.cond.cleanup: 679 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 680 // CHECK1: omp.inner.for.body: 681 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 682 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 683 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 684 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 685 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]] 686 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 687 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 688 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] 689 // CHECK1-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] 690 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 691 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 692 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] 693 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR5]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] 694 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 695 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]] 696 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP18]], [[TMP17]] 697 // CHECK1-NEXT: store i32 [[ADD10]], ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]] 698 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 699 // CHECK1: omp.body.continue: 700 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 701 // CHECK1: omp.inner.for.inc: 702 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 703 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP19]], 1 704 // CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 705 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 706 // CHECK1: omp.inner.for.end: 707 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 708 // CHECK1: omp.loop.exit: 709 // CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 710 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 711 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 712 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 713 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 714 // CHECK1-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 715 // CHECK1: .omp.final.then: 716 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 717 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 718 // CHECK1: .omp.final.done: 719 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 720 // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 721 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 722 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 723 // CHECK1: arraydestroy.body: 724 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 725 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 726 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 727 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 728 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 729 // CHECK1: arraydestroy.done13: 730 // CHECK1-NEXT: ret void 731 // 732 // 733 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 734 // CHECK1-SAME: () #[[ATTR1]] comdat { 735 // CHECK1-NEXT: entry: 736 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 737 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 738 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 739 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 740 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 741 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 742 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 743 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 744 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 745 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 746 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 747 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 748 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 749 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 750 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 751 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 752 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 753 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 754 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 755 // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 756 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 757 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 758 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 759 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 760 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 761 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 762 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 763 // CHECK1-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 8 764 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 765 // CHECK1-NEXT: store ptr [[VEC]], ptr [[TMP5]], align 8 766 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 767 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 768 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 769 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP7]], align 8 770 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 771 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP8]], align 8 772 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 773 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 774 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 775 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[TMP10]], align 8 776 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 777 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[TMP11]], align 8 778 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 779 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 780 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 781 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 8 782 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 783 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 8 784 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 785 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 786 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 787 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 788 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 789 // CHECK1-NEXT: store i32 3, ptr [[TMP18]], align 4 790 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 791 // CHECK1-NEXT: store i32 4, ptr [[TMP19]], align 4 792 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 793 // CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 8 794 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 795 // CHECK1-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 8 796 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 797 // CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP22]], align 8 798 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 799 // CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP23]], align 8 800 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 801 // CHECK1-NEXT: store ptr null, ptr [[TMP24]], align 8 802 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 803 // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 804 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 805 // CHECK1-NEXT: store i64 2, ptr [[TMP26]], align 8 806 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 807 // CHECK1-NEXT: store i64 0, ptr [[TMP27]], align 8 808 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 809 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 810 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 811 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4 812 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 813 // CHECK1-NEXT: store i32 0, ptr [[TMP30]], align 4 814 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, ptr [[KERNEL_ARGS]]) 815 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 816 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 817 // CHECK1: omp_offload.failed: 818 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(ptr [[VEC]], i64 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]] 819 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 820 // CHECK1: omp_offload.cont: 821 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 822 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 823 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 824 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 825 // CHECK1: arraydestroy.body: 826 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 827 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 828 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 829 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 830 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 831 // CHECK1: arraydestroy.done2: 832 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 833 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 834 // CHECK1-NEXT: ret i32 [[TMP34]] 835 // 836 // 837 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev 838 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 839 // CHECK1-NEXT: entry: 840 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 841 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 842 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 843 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 844 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 845 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 846 // CHECK1-NEXT: store i32 0, ptr [[B]], align 4 847 // CHECK1-NEXT: ret void 848 // 849 // 850 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 851 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 852 // CHECK1-NEXT: entry: 853 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 854 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 855 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 856 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 857 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 858 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 859 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 860 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 861 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 862 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 863 // CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 864 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 865 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 866 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 867 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 868 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 869 // CHECK1-NEXT: ret void 870 // 871 // 872 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev 873 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 874 // CHECK1-NEXT: entry: 875 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 876 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 877 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 878 // CHECK1-NEXT: ret void 879 // 880 // 881 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 882 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 883 // CHECK1-NEXT: entry: 884 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 885 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 886 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 887 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 888 // CHECK1-NEXT: ret void 889 // 890 // 891 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 892 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 893 // CHECK1-NEXT: entry: 894 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 895 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 896 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 897 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 898 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 899 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 900 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 901 // CHECK1-NEXT: ret void 902 // 903 // 904 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 905 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 906 // CHECK1-NEXT: entry: 907 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 908 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 909 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 910 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 911 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 912 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 913 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 914 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 915 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 916 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 917 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 918 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 919 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 920 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 921 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 922 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 923 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 924 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 925 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) 926 // CHECK1-NEXT: ret void 927 // 928 // 929 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined 930 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 931 // CHECK1-NEXT: entry: 932 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 933 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 934 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 935 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 936 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 937 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 938 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 939 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 940 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 941 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 942 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 943 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 944 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 945 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 946 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 947 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 948 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 949 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 950 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 951 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 952 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 953 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 954 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 955 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 956 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 957 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 958 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 959 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 960 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 961 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 962 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 963 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 964 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 965 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 966 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 967 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) 968 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 969 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 970 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 971 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 972 // CHECK1: omp.arraycpy.body: 973 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 974 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 975 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 976 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 977 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 978 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 979 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 980 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 981 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 982 // CHECK1: omp.arraycpy.done4: 983 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 984 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 985 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) 986 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 987 // CHECK1-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8 988 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 989 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 990 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 991 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 992 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 993 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 994 // CHECK1: cond.true: 995 // CHECK1-NEXT: br label [[COND_END:%.*]] 996 // CHECK1: cond.false: 997 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 998 // CHECK1-NEXT: br label [[COND_END]] 999 // CHECK1: cond.end: 1000 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 1001 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1002 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1003 // CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 1004 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1005 // CHECK1: omp.inner.for.cond: 1006 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]] 1007 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]] 1008 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 1009 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1010 // CHECK1: omp.inner.for.cond.cleanup: 1011 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1012 // CHECK1: omp.inner.for.body: 1013 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP14]] 1014 // CHECK1-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 1015 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]] 1016 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 1017 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP14]] 1018 // CHECK1-NEXT: store i32 [[TMP16]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP14]] 1019 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP14]] 1020 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP14]] 1021 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined.omp_outlined, i64 [[TMP13]], i64 [[TMP15]], ptr [[VEC2]], i64 [[TMP17]], ptr [[S_ARR3]], ptr [[TMP18]]), !llvm.access.group [[ACC_GRP14]] 1022 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1023 // CHECK1: omp.inner.for.inc: 1024 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 1025 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP14]] 1026 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] 1027 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 1028 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 1029 // CHECK1: omp.inner.for.end: 1030 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1031 // CHECK1: omp.loop.exit: 1032 // CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1033 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 1034 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) 1035 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1036 // CHECK1-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 1037 // CHECK1-NEXT: br i1 [[TMP24]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1038 // CHECK1: .omp.final.then: 1039 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 1040 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1041 // CHECK1: .omp.final.done: 1042 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1043 // CHECK1-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 1044 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 2 1045 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1046 // CHECK1: arraydestroy.body: 1047 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1048 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1049 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1050 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] 1051 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] 1052 // CHECK1: arraydestroy.done10: 1053 // CHECK1-NEXT: ret void 1054 // 1055 // 1056 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1057 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1058 // CHECK1-NEXT: entry: 1059 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1060 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 1061 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 1062 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1063 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 1064 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 1065 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1066 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 1067 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 1068 // CHECK1-NEXT: ret void 1069 // 1070 // 1071 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined.omp_outlined 1072 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1073 // CHECK1-NEXT: entry: 1074 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1075 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1076 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1077 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1078 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 1079 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1080 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 1081 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 1082 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1083 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1084 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1085 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1086 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1087 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1088 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1089 // CHECK1-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 1090 // CHECK1-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 1091 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1092 // CHECK1-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1093 // CHECK1-NEXT: [[AGG_TMP7:%.*]] = alloca [[STRUCT_ST]], align 4 1094 // CHECK1-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 1095 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1096 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1097 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1098 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1099 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1100 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 1101 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 1102 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 1103 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 1104 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 1105 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 1106 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 1107 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 1108 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1109 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1110 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1111 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 1112 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1113 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32 1114 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1115 // CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 1116 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1117 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1118 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false) 1119 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 1120 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 1121 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 1122 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1123 // CHECK1: omp.arraycpy.body: 1124 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1125 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1126 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1127 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 1128 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1129 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1130 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1131 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 1132 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]] 1133 // CHECK1: omp.arraycpy.done5: 1134 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 1135 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) 1136 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP7]]) 1137 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) #[[ATTR2]] 1138 // CHECK1-NEXT: store ptr [[VAR6]], ptr [[_TMP8]], align 8 1139 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1140 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1141 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1142 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1143 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 1144 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1145 // CHECK1: cond.true: 1146 // CHECK1-NEXT: br label [[COND_END:%.*]] 1147 // CHECK1: cond.false: 1148 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1149 // CHECK1-NEXT: br label [[COND_END]] 1150 // CHECK1: cond.end: 1151 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 1152 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1153 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1154 // CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 1155 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1156 // CHECK1: omp.inner.for.cond: 1157 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]] 1158 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP17]] 1159 // CHECK1-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 1160 // CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1161 // CHECK1: omp.inner.for.cond.cleanup: 1162 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1163 // CHECK1: omp.inner.for.body: 1164 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 1165 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 1166 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1167 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 1168 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP17]] 1169 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 1170 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 1171 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] 1172 // CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]] 1173 // CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8, !llvm.access.group [[ACC_GRP17]] 1174 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 1175 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 1176 // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] 1177 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP17]] 1178 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1179 // CHECK1: omp.body.continue: 1180 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1181 // CHECK1: omp.inner.for.inc: 1182 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 1183 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 1184 // CHECK1-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 1185 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 1186 // CHECK1: omp.inner.for.end: 1187 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1188 // CHECK1: omp.loop.exit: 1189 // CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1190 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 1191 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 1192 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1193 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 1194 // CHECK1-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1195 // CHECK1: .omp.final.then: 1196 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 1197 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1198 // CHECK1: .omp.final.done: 1199 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR2]] 1200 // CHECK1-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 1201 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 1202 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1203 // CHECK1: arraydestroy.body: 1204 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1205 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1206 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1207 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] 1208 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] 1209 // CHECK1: arraydestroy.done14: 1210 // CHECK1-NEXT: ret void 1211 // 1212 // 1213 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1214 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1215 // CHECK1-NEXT: entry: 1216 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1217 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1218 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1219 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1220 // CHECK1-NEXT: ret void 1221 // 1222 // 1223 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1224 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1225 // CHECK1-NEXT: entry: 1226 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1227 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1228 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1229 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1230 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1231 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1232 // CHECK1-NEXT: ret void 1233 // 1234 // 1235 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1236 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1237 // CHECK1-NEXT: entry: 1238 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1239 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1240 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1241 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1242 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1243 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1244 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1245 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1246 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1247 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1248 // CHECK1-NEXT: ret void 1249 // 1250 // 1251 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1252 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1253 // CHECK1-NEXT: entry: 1254 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1255 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 1256 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 1257 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1258 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 1259 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 1260 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1261 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1262 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 1263 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 1264 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 1265 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 1266 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1267 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1268 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1269 // CHECK1-NEXT: ret void 1270 // 1271 // 1272 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1273 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1274 // CHECK1-NEXT: entry: 1275 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1276 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1277 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1278 // CHECK1-NEXT: ret void 1279 // 1280 // 1281 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp 1282 // CHECK1-SAME: () #[[ATTR0]] { 1283 // CHECK1-NEXT: entry: 1284 // CHECK1-NEXT: call void @__cxx_global_var_init() 1285 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 1286 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 1287 // CHECK1-NEXT: ret void 1288 // 1289 // 1290 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 1291 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 1292 // CHECK3-NEXT: entry: 1293 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 1294 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 1295 // CHECK3-NEXT: ret void 1296 // 1297 // 1298 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1299 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1300 // CHECK3-NEXT: entry: 1301 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1302 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1303 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1304 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1305 // CHECK3-NEXT: ret void 1306 // 1307 // 1308 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1309 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1310 // CHECK3-NEXT: entry: 1311 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1312 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1313 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1314 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1315 // CHECK3-NEXT: ret void 1316 // 1317 // 1318 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1319 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1320 // CHECK3-NEXT: entry: 1321 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1322 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1323 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1324 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1325 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1326 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1327 // CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4 1328 // CHECK3-NEXT: ret void 1329 // 1330 // 1331 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1332 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1333 // CHECK3-NEXT: entry: 1334 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1335 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1336 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1337 // CHECK3-NEXT: ret void 1338 // 1339 // 1340 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1341 // CHECK3-SAME: () #[[ATTR0]] { 1342 // CHECK3-NEXT: entry: 1343 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 1344 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 1345 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 1346 // CHECK3-NEXT: ret void 1347 // 1348 // 1349 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1350 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1351 // CHECK3-NEXT: entry: 1352 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1353 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1354 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1355 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1356 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1357 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1358 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1359 // CHECK3-NEXT: ret void 1360 // 1361 // 1362 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1363 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1364 // CHECK3-NEXT: entry: 1365 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 1366 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 1367 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1368 // CHECK3: arraydestroy.body: 1369 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1370 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1371 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1372 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1373 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1374 // CHECK3: arraydestroy.done1: 1375 // CHECK3-NEXT: ret void 1376 // 1377 // 1378 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1379 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1380 // CHECK3-NEXT: entry: 1381 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1382 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1383 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1384 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1385 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1386 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1387 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1388 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1389 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1390 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1391 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 1392 // CHECK3-NEXT: ret void 1393 // 1394 // 1395 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1396 // CHECK3-SAME: () #[[ATTR0]] { 1397 // CHECK3-NEXT: entry: 1398 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1399 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1400 // CHECK3-NEXT: ret void 1401 // 1402 // 1403 // CHECK3-LABEL: define {{[^@]+}}@main 1404 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1405 // CHECK3-NEXT: entry: 1406 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1407 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1408 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1409 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 1410 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 1411 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 1412 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1413 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1414 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1415 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr @t_var, align 4 1416 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 1417 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1418 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 1419 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 1420 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 1421 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1422 // CHECK3-NEXT: store ptr @vec, ptr [[TMP4]], align 4 1423 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1424 // CHECK3-NEXT: store ptr @vec, ptr [[TMP5]], align 4 1425 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1426 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1427 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1428 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 4 1429 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1430 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 4 1431 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1432 // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 1433 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1434 // CHECK3-NEXT: store ptr @s_arr, ptr [[TMP10]], align 4 1435 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1436 // CHECK3-NEXT: store ptr @s_arr, ptr [[TMP11]], align 4 1437 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1438 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 1439 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1440 // CHECK3-NEXT: store ptr @var, ptr [[TMP13]], align 4 1441 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1442 // CHECK3-NEXT: store ptr @var, ptr [[TMP14]], align 4 1443 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1444 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 1445 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1446 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP16]], align 4 1447 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1448 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP17]], align 4 1449 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1450 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 1451 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1452 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1453 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1454 // CHECK3-NEXT: store i32 3, ptr [[TMP21]], align 4 1455 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1456 // CHECK3-NEXT: store i32 5, ptr [[TMP22]], align 4 1457 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1458 // CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4 1459 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1460 // CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4 1461 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1462 // CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 4 1463 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1464 // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 4 1465 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1466 // CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 4 1467 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1468 // CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 4 1469 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1470 // CHECK3-NEXT: store i64 2, ptr [[TMP29]], align 8 1471 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1472 // CHECK3-NEXT: store i64 0, ptr [[TMP30]], align 8 1473 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1474 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 1475 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1476 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 1477 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1478 // CHECK3-NEXT: store i32 0, ptr [[TMP33]], align 4 1479 // CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.region_id, ptr [[KERNEL_ARGS]]) 1480 // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 1481 // CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1482 // CHECK3: omp_offload.failed: 1483 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122(ptr @vec, i32 [[TMP1]], ptr @s_arr, ptr @var, i32 [[TMP3]]) #[[ATTR2]] 1484 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1485 // CHECK3: omp_offload.cont: 1486 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1487 // CHECK3-NEXT: ret i32 [[CALL]] 1488 // 1489 // 1490 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 1491 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 1492 // CHECK3-NEXT: entry: 1493 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1494 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1495 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1496 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1497 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1498 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1499 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1500 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1501 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1502 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1503 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1504 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 1505 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1506 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1507 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1508 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1509 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 1510 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1511 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 1512 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 1513 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 1514 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]]) 1515 // CHECK3-NEXT: ret void 1516 // 1517 // 1518 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined 1519 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 1520 // CHECK3-NEXT: entry: 1521 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1522 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1523 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1524 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1525 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1526 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1527 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1528 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1529 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1530 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1531 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1532 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1533 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1534 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 1535 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 1536 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1537 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1538 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 1539 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1540 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1541 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1542 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1543 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1544 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1545 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1546 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1547 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1548 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 1549 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1550 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1551 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1552 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1553 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1554 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1555 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1556 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) 1557 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1558 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1559 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 1560 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1561 // CHECK3: omp.arraycpy.body: 1562 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1563 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1564 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1565 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 1566 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1567 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1568 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1569 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 1570 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 1571 // CHECK3: omp.arraycpy.done3: 1572 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 1573 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 1574 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 1575 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1576 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 1577 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1578 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1579 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 1580 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1581 // CHECK3: cond.true: 1582 // CHECK3-NEXT: br label [[COND_END:%.*]] 1583 // CHECK3: cond.false: 1584 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1585 // CHECK3-NEXT: br label [[COND_END]] 1586 // CHECK3: cond.end: 1587 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1588 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1589 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1590 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 1591 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1592 // CHECK3: omp.inner.for.cond: 1593 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 1594 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 1595 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1596 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1597 // CHECK3: omp.inner.for.cond.cleanup: 1598 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1599 // CHECK3: omp.inner.for.body: 1600 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP6]] 1601 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 1602 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP6]] 1603 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP6]] 1604 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP6]] 1605 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP6]] 1606 // CHECK3-NEXT: store i32 [[TMP15]], ptr [[SIVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP6]] 1607 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP6]] 1608 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined.omp_outlined, i32 [[TMP11]], i32 [[TMP12]], ptr [[VEC1]], i32 [[TMP14]], ptr [[S_ARR2]], ptr [[VAR4]], i32 [[TMP16]]), !llvm.access.group [[ACC_GRP6]] 1609 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1610 // CHECK3: omp.inner.for.inc: 1611 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1612 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP6]] 1613 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] 1614 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1615 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1616 // CHECK3: omp.inner.for.end: 1617 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1618 // CHECK3: omp.loop.exit: 1619 // CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1620 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 1621 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) 1622 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1623 // CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 1624 // CHECK3-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1625 // CHECK3: .omp.final.then: 1626 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 1627 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1628 // CHECK3: .omp.final.done: 1629 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 1630 // CHECK3-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1631 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 2 1632 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1633 // CHECK3: arraydestroy.body: 1634 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1635 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1636 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1637 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 1638 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 1639 // CHECK3: arraydestroy.done8: 1640 // CHECK3-NEXT: ret void 1641 // 1642 // 1643 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev 1644 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1645 // CHECK3-NEXT: entry: 1646 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1647 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1648 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1649 // CHECK3-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 1650 // CHECK3-NEXT: ret void 1651 // 1652 // 1653 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 1654 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1655 // CHECK3-NEXT: entry: 1656 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1657 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1658 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1659 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1660 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1661 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1662 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1663 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1664 // CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 1665 // CHECK3-NEXT: ret void 1666 // 1667 // 1668 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev 1669 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1670 // CHECK3-NEXT: entry: 1671 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1672 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1673 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1674 // CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 1675 // CHECK3-NEXT: ret void 1676 // 1677 // 1678 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined.omp_outlined 1679 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 1680 // CHECK3-NEXT: entry: 1681 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1682 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1683 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 1684 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 1685 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1686 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1687 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1688 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1689 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1690 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1691 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1692 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1693 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1694 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1695 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1696 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 1697 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 1698 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1699 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1700 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 1701 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1702 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1703 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1704 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1705 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1706 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1707 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1708 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1709 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1710 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 1711 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1712 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1713 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1714 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1715 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1716 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1717 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1718 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4 1719 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 1720 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1721 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1722 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) 1723 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1724 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1725 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 1726 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1727 // CHECK3: omp.arraycpy.body: 1728 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1729 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1730 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1731 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 1732 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1733 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1734 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1735 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 1736 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 1737 // CHECK3: omp.arraycpy.done3: 1738 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 1739 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 1740 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 1741 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1742 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 1743 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1744 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1745 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 1746 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1747 // CHECK3: cond.true: 1748 // CHECK3-NEXT: br label [[COND_END:%.*]] 1749 // CHECK3: cond.false: 1750 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1751 // CHECK3-NEXT: br label [[COND_END]] 1752 // CHECK3: cond.end: 1753 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] 1754 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1755 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1756 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 1757 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1758 // CHECK3: omp.inner.for.cond: 1759 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 1760 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 1761 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 1762 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1763 // CHECK3: omp.inner.for.cond.cleanup: 1764 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1765 // CHECK3: omp.inner.for.body: 1766 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 1767 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 1768 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1769 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 1770 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]] 1771 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 1772 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP15]] 1773 // CHECK3-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] 1774 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 1775 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] 1776 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] 1777 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 1778 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]] 1779 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP18]], [[TMP17]] 1780 // CHECK3-NEXT: store i32 [[ADD8]], ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]] 1781 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1782 // CHECK3: omp.body.continue: 1783 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1784 // CHECK3: omp.inner.for.inc: 1785 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 1786 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1 1787 // CHECK3-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 1788 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 1789 // CHECK3: omp.inner.for.end: 1790 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1791 // CHECK3: omp.loop.exit: 1792 // CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1793 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 1794 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 1795 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1796 // CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 1797 // CHECK3-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1798 // CHECK3: .omp.final.then: 1799 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 1800 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1801 // CHECK3: .omp.final.done: 1802 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 1803 // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1804 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 1805 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1806 // CHECK3: arraydestroy.body: 1807 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1808 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1809 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1810 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 1811 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 1812 // CHECK3: arraydestroy.done11: 1813 // CHECK3-NEXT: ret void 1814 // 1815 // 1816 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1817 // CHECK3-SAME: () #[[ATTR1]] comdat { 1818 // CHECK3-NEXT: entry: 1819 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1820 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1821 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1822 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1823 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1824 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 1825 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1826 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1827 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 1828 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 1829 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 1830 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1831 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1832 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1833 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 1834 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 1835 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 1836 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 1837 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1838 // CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 1839 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 1840 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 1841 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 1842 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 1843 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1844 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 1845 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1846 // CHECK3-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 4 1847 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1848 // CHECK3-NEXT: store ptr [[VEC]], ptr [[TMP5]], align 4 1849 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1850 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1851 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1852 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP7]], align 4 1853 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1854 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP8]], align 4 1855 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1856 // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 1857 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1858 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[TMP10]], align 4 1859 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1860 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[TMP11]], align 4 1861 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1862 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 1863 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1864 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 4 1865 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1866 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 4 1867 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1868 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 1869 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1870 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1871 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1872 // CHECK3-NEXT: store i32 3, ptr [[TMP18]], align 4 1873 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1874 // CHECK3-NEXT: store i32 4, ptr [[TMP19]], align 4 1875 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1876 // CHECK3-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 4 1877 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1878 // CHECK3-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 4 1879 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1880 // CHECK3-NEXT: store ptr @.offload_sizes.3, ptr [[TMP22]], align 4 1881 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1882 // CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP23]], align 4 1883 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1884 // CHECK3-NEXT: store ptr null, ptr [[TMP24]], align 4 1885 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1886 // CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4 1887 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1888 // CHECK3-NEXT: store i64 2, ptr [[TMP26]], align 8 1889 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1890 // CHECK3-NEXT: store i64 0, ptr [[TMP27]], align 8 1891 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1892 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 1893 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1894 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4 1895 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1896 // CHECK3-NEXT: store i32 0, ptr [[TMP30]], align 4 1897 // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, ptr [[KERNEL_ARGS]]) 1898 // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1899 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1900 // CHECK3: omp_offload.failed: 1901 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(ptr [[VEC]], i32 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]] 1902 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1903 // CHECK3: omp_offload.cont: 1904 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1905 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1906 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1907 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1908 // CHECK3: arraydestroy.body: 1909 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1910 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1911 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1912 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1913 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1914 // CHECK3: arraydestroy.done2: 1915 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1916 // CHECK3-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 1917 // CHECK3-NEXT: ret i32 [[TMP34]] 1918 // 1919 // 1920 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev 1921 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1922 // CHECK3-NEXT: entry: 1923 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1924 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1925 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1926 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 1927 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 1928 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 1929 // CHECK3-NEXT: store i32 0, ptr [[B]], align 4 1930 // CHECK3-NEXT: ret void 1931 // 1932 // 1933 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 1934 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1935 // CHECK3-NEXT: entry: 1936 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1937 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1938 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1939 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1940 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1941 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1942 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1943 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1944 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1945 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 1946 // CHECK3-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 1947 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 1948 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1949 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 1950 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 1951 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 1952 // CHECK3-NEXT: ret void 1953 // 1954 // 1955 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev 1956 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1957 // CHECK3-NEXT: entry: 1958 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1959 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1960 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1961 // CHECK3-NEXT: ret void 1962 // 1963 // 1964 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1965 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1966 // CHECK3-NEXT: entry: 1967 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1968 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1969 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1970 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1971 // CHECK3-NEXT: ret void 1972 // 1973 // 1974 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1975 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1976 // CHECK3-NEXT: entry: 1977 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1978 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1979 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1980 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1981 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1982 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1983 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1984 // CHECK3-NEXT: ret void 1985 // 1986 // 1987 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 1988 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1989 // CHECK3-NEXT: entry: 1990 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1991 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1992 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1993 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1994 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1995 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1996 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1997 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1998 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1999 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 2000 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 2001 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 2002 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 2003 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 2004 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 2005 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 2006 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 2007 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 2008 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) 2009 // CHECK3-NEXT: ret void 2010 // 2011 // 2012 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined 2013 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 2014 // CHECK3-NEXT: entry: 2015 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2016 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2017 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 2018 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2019 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 2020 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 2021 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 2022 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2023 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2024 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2025 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2026 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2027 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2028 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 2029 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 2030 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2031 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2032 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 2033 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 2034 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2035 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2036 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2037 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2038 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 2039 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 2040 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 2041 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 2042 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 2043 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 2044 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 2045 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 2046 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 2047 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 2048 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2049 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2050 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) 2051 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 2052 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 2053 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 2054 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2055 // CHECK3: omp.arraycpy.body: 2056 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2057 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2058 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2059 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 2060 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 2061 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2062 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2063 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 2064 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 2065 // CHECK3: omp.arraycpy.done4: 2066 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 2067 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 2068 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) 2069 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 2070 // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 2071 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2072 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 2073 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2074 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2075 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 2076 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2077 // CHECK3: cond.true: 2078 // CHECK3-NEXT: br label [[COND_END:%.*]] 2079 // CHECK3: cond.false: 2080 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2081 // CHECK3-NEXT: br label [[COND_END]] 2082 // CHECK3: cond.end: 2083 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 2084 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2085 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2086 // CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 2087 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2088 // CHECK3: omp.inner.for.cond: 2089 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] 2090 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 2091 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 2092 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2093 // CHECK3: omp.inner.for.cond.cleanup: 2094 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2095 // CHECK3: omp.inner.for.body: 2096 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]] 2097 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 2098 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP15]] 2099 // CHECK3-NEXT: store i32 [[TMP14]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP15]] 2100 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP15]] 2101 // CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP15]] 2102 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined.omp_outlined, i32 [[TMP12]], i32 [[TMP13]], ptr [[VEC2]], i32 [[TMP15]], ptr [[S_ARR3]], ptr [[TMP16]]), !llvm.access.group [[ACC_GRP15]] 2103 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2104 // CHECK3: omp.inner.for.inc: 2105 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 2106 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]] 2107 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] 2108 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 2109 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 2110 // CHECK3: omp.inner.for.end: 2111 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2112 // CHECK3: omp.loop.exit: 2113 // CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2114 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 2115 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) 2116 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2117 // CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 2118 // CHECK3-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2119 // CHECK3: .omp.final.then: 2120 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 2121 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2122 // CHECK3: .omp.final.done: 2123 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 2124 // CHECK3-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 2125 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 2126 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2127 // CHECK3: arraydestroy.body: 2128 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2129 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2130 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2131 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] 2132 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] 2133 // CHECK3: arraydestroy.done10: 2134 // CHECK3-NEXT: ret void 2135 // 2136 // 2137 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 2138 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2139 // CHECK3-NEXT: entry: 2140 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2141 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 2142 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 2143 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2144 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 2145 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 2146 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2147 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 2148 // CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 2149 // CHECK3-NEXT: ret void 2150 // 2151 // 2152 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined.omp_outlined 2153 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 2154 // CHECK3-NEXT: entry: 2155 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2156 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2157 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 2158 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 2159 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 2160 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2161 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 2162 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 2163 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 2164 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2165 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2166 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2167 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2168 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2169 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2170 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 2171 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 2172 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2173 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2174 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 2175 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 2176 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2177 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2178 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2179 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 2180 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 2181 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 2182 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 2183 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 2184 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 2185 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 2186 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 2187 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 2188 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 2189 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2190 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2191 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 2192 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 2193 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4 2194 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 2195 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2196 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2197 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) 2198 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 2199 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 2200 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 2201 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2202 // CHECK3: omp.arraycpy.body: 2203 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2204 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2205 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2206 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 2207 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 2208 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2209 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2210 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 2211 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 2212 // CHECK3: omp.arraycpy.done4: 2213 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 2214 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 2215 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP6]]) 2216 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 2217 // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 2218 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2219 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 2220 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2221 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2222 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 2223 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2224 // CHECK3: cond.true: 2225 // CHECK3-NEXT: br label [[COND_END:%.*]] 2226 // CHECK3: cond.false: 2227 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2228 // CHECK3-NEXT: br label [[COND_END]] 2229 // CHECK3: cond.end: 2230 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 2231 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2232 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2233 // CHECK3-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 2234 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2235 // CHECK3: omp.inner.for.cond: 2236 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] 2237 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] 2238 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 2239 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2240 // CHECK3: omp.inner.for.cond.cleanup: 2241 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2242 // CHECK3: omp.inner.for.body: 2243 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 2244 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 2245 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2246 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 2247 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP18]] 2248 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 2249 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]] 2250 // CHECK3-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] 2251 // CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP18]] 2252 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 2253 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] 2254 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP18]] 2255 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2256 // CHECK3: omp.body.continue: 2257 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2258 // CHECK3: omp.inner.for.inc: 2259 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 2260 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 2261 // CHECK3-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 2262 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 2263 // CHECK3: omp.inner.for.end: 2264 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2265 // CHECK3: omp.loop.exit: 2266 // CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2267 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 2268 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 2269 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2270 // CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 2271 // CHECK3-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2272 // CHECK3: .omp.final.then: 2273 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 2274 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2275 // CHECK3: .omp.final.done: 2276 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 2277 // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 2278 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 2279 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2280 // CHECK3: arraydestroy.body: 2281 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2282 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2283 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2284 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 2285 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 2286 // CHECK3: arraydestroy.done12: 2287 // CHECK3-NEXT: ret void 2288 // 2289 // 2290 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2291 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2292 // CHECK3-NEXT: entry: 2293 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2294 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2295 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2296 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2297 // CHECK3-NEXT: ret void 2298 // 2299 // 2300 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2301 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2302 // CHECK3-NEXT: entry: 2303 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2304 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2305 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2306 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2307 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2308 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 2309 // CHECK3-NEXT: ret void 2310 // 2311 // 2312 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2313 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2314 // CHECK3-NEXT: entry: 2315 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2316 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2317 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2318 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2319 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2320 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2321 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2322 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2323 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2324 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 2325 // CHECK3-NEXT: ret void 2326 // 2327 // 2328 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 2329 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2330 // CHECK3-NEXT: entry: 2331 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2332 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 2333 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 2334 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2335 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 2336 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 2337 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2338 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2339 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 2340 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 2341 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 2342 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 2343 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 2344 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 2345 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 2346 // CHECK3-NEXT: ret void 2347 // 2348 // 2349 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2350 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2351 // CHECK3-NEXT: entry: 2352 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2353 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2354 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2355 // CHECK3-NEXT: ret void 2356 // 2357 // 2358 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp 2359 // CHECK3-SAME: () #[[ATTR0]] { 2360 // CHECK3-NEXT: entry: 2361 // CHECK3-NEXT: call void @__cxx_global_var_init() 2362 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 2363 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 2364 // CHECK3-NEXT: ret void 2365 // 2366 // 2367 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 2368 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 2369 // CHECK5-NEXT: entry: 2370 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 2371 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 2372 // CHECK5-NEXT: ret void 2373 // 2374 // 2375 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2376 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 2377 // CHECK5-NEXT: entry: 2378 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2379 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2380 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2381 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2382 // CHECK5-NEXT: ret void 2383 // 2384 // 2385 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2386 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2387 // CHECK5-NEXT: entry: 2388 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2389 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2390 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2391 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2392 // CHECK5-NEXT: ret void 2393 // 2394 // 2395 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2396 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2397 // CHECK5-NEXT: entry: 2398 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2399 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2400 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2401 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2402 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2403 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2404 // CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4 2405 // CHECK5-NEXT: ret void 2406 // 2407 // 2408 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2409 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2410 // CHECK5-NEXT: entry: 2411 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2412 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2413 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2414 // CHECK5-NEXT: ret void 2415 // 2416 // 2417 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2418 // CHECK5-SAME: () #[[ATTR0]] { 2419 // CHECK5-NEXT: entry: 2420 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 2421 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 2422 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 2423 // CHECK5-NEXT: ret void 2424 // 2425 // 2426 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2427 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2428 // CHECK5-NEXT: entry: 2429 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2430 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2431 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2432 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2433 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2434 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2435 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2436 // CHECK5-NEXT: ret void 2437 // 2438 // 2439 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2440 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2441 // CHECK5-NEXT: entry: 2442 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2443 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2444 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2445 // CHECK5: arraydestroy.body: 2446 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2447 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2448 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2449 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 2450 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2451 // CHECK5: arraydestroy.done1: 2452 // CHECK5-NEXT: ret void 2453 // 2454 // 2455 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2456 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2457 // CHECK5-NEXT: entry: 2458 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2459 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2460 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2461 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2462 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2463 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2464 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2465 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2466 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2467 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2468 // CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4 2469 // CHECK5-NEXT: ret void 2470 // 2471 // 2472 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2473 // CHECK5-SAME: () #[[ATTR0]] { 2474 // CHECK5-NEXT: entry: 2475 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2476 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 2477 // CHECK5-NEXT: ret void 2478 // 2479 // 2480 // CHECK5-LABEL: define {{[^@]+}}@main 2481 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 2482 // CHECK5-NEXT: entry: 2483 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2484 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2485 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 2486 // CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2487 // CHECK5-NEXT: ret i32 0 2488 // 2489 // 2490 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 2491 // CHECK5-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 2492 // CHECK5-NEXT: entry: 2493 // CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 2494 // CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 2495 // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2496 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 2497 // CHECK5-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 2498 // CHECK5-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 2499 // CHECK5-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 2500 // CHECK5-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 2501 // CHECK5-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 2502 // CHECK5-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 2503 // CHECK5-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 2504 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 4 2505 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4 2506 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8 2507 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 2508 // CHECK5-NEXT: [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 4 2509 // CHECK5-NEXT: store i32 [[TMP3]], ptr [[G1_CASTED]], align 4 2510 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 8 2511 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 2512 // CHECK5-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 2513 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 2514 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) 2515 // CHECK5-NEXT: ret void 2516 // 2517 // 2518 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined 2519 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 2520 // CHECK5-NEXT: entry: 2521 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2522 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2523 // CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 2524 // CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 2525 // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2526 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 2527 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2528 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2529 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2530 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2531 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2532 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2533 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2534 // CHECK5-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 2535 // CHECK5-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 2536 // CHECK5-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 2537 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2538 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2539 // CHECK5-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 2540 // CHECK5-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 2541 // CHECK5-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 2542 // CHECK5-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 2543 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 2544 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 2545 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2546 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2547 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2548 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2549 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2550 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2551 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 2552 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2553 // CHECK5: cond.true: 2554 // CHECK5-NEXT: br label [[COND_END:%.*]] 2555 // CHECK5: cond.false: 2556 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2557 // CHECK5-NEXT: br label [[COND_END]] 2558 // CHECK5: cond.end: 2559 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2560 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2561 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2562 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2563 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2564 // CHECK5: omp.inner.for.cond: 2565 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]] 2566 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]] 2567 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2568 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2569 // CHECK5: omp.inner.for.body: 2570 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP4]] 2571 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 2572 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]] 2573 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 2574 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[G_ADDR]], align 4, !llvm.access.group [[ACC_GRP4]] 2575 // CHECK5-NEXT: store i32 [[TMP11]], ptr [[G_CASTED]], align 4, !llvm.access.group [[ACC_GRP4]] 2576 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[G_CASTED]], align 8, !llvm.access.group [[ACC_GRP4]] 2577 // CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8, !llvm.access.group [[ACC_GRP4]] 2578 // CHECK5-NEXT: [[TMP14:%.*]] = load volatile i32, ptr [[TMP13]], align 4, !llvm.access.group [[ACC_GRP4]] 2579 // CHECK5-NEXT: store i32 [[TMP14]], ptr [[G1_CASTED]], align 4, !llvm.access.group [[ACC_GRP4]] 2580 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[G1_CASTED]], align 8, !llvm.access.group [[ACC_GRP4]] 2581 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP4]] 2582 // CHECK5-NEXT: store i32 [[TMP16]], ptr [[SIVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP4]] 2583 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP4]] 2584 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group [[ACC_GRP4]] 2585 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2586 // CHECK5: omp.inner.for.inc: 2587 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 2588 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP4]] 2589 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 2590 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 2591 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 2592 // CHECK5: omp.inner.for.end: 2593 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2594 // CHECK5: omp.loop.exit: 2595 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2596 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2597 // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 2598 // CHECK5-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2599 // CHECK5: .omp.final.then: 2600 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 2601 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2602 // CHECK5: .omp.final.done: 2603 // CHECK5-NEXT: ret void 2604 // 2605 // 2606 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined.omp_outlined 2607 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 2608 // CHECK5-NEXT: entry: 2609 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2610 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2611 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 2612 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 2613 // CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 2614 // CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 2615 // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2616 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 2617 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2618 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2619 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2620 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2621 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2622 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2623 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2624 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 2625 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2626 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2627 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2628 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2629 // CHECK5-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 2630 // CHECK5-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 2631 // CHECK5-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 2632 // CHECK5-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 2633 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2634 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2635 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2636 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 2637 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2638 // CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 2639 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 2640 // CHECK5-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 2641 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2642 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2643 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2644 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 2645 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2646 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2647 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 2648 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2649 // CHECK5: cond.true: 2650 // CHECK5-NEXT: br label [[COND_END:%.*]] 2651 // CHECK5: cond.false: 2652 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2653 // CHECK5-NEXT: br label [[COND_END]] 2654 // CHECK5: cond.end: 2655 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2656 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2657 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2658 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 2659 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2660 // CHECK5: omp.inner.for.cond: 2661 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]] 2662 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]] 2663 // CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2664 // CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2665 // CHECK5: omp.inner.for.body: 2666 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 2667 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 2668 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2669 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 2670 // CHECK5-NEXT: store i32 1, ptr [[G_ADDR]], align 4, !llvm.access.group [[ACC_GRP8]] 2671 // CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP]], align 8, !llvm.access.group [[ACC_GRP8]] 2672 // CHECK5-NEXT: store volatile i32 1, ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP8]] 2673 // CHECK5-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP8]] 2674 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 2675 // CHECK5-NEXT: store ptr [[G_ADDR]], ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP8]] 2676 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 2677 // CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8, !llvm.access.group [[ACC_GRP8]] 2678 // CHECK5-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP8]] 2679 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 2680 // CHECK5-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP14]], align 8, !llvm.access.group [[ACC_GRP8]] 2681 // CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group [[ACC_GRP8]] 2682 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2683 // CHECK5: omp.body.continue: 2684 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2685 // CHECK5: omp.inner.for.inc: 2686 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 2687 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 2688 // CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 2689 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 2690 // CHECK5: omp.inner.for.end: 2691 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2692 // CHECK5: omp.loop.exit: 2693 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 2694 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2695 // CHECK5-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 2696 // CHECK5-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2697 // CHECK5: .omp.final.then: 2698 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 2699 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2700 // CHECK5: .omp.final.done: 2701 // CHECK5-NEXT: ret void 2702 // 2703 // 2704 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp 2705 // CHECK5-SAME: () #[[ATTR0]] { 2706 // CHECK5-NEXT: entry: 2707 // CHECK5-NEXT: call void @__cxx_global_var_init() 2708 // CHECK5-NEXT: call void @__cxx_global_var_init.1() 2709 // CHECK5-NEXT: call void @__cxx_global_var_init.2() 2710 // CHECK5-NEXT: ret void 2711 // 2712 // 2713 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init 2714 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 2715 // CHECK7-NEXT: entry: 2716 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 2717 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 2718 // CHECK7-NEXT: ret void 2719 // 2720 // 2721 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2722 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 2723 // CHECK7-NEXT: entry: 2724 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2725 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2726 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2727 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2728 // CHECK7-NEXT: ret void 2729 // 2730 // 2731 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2732 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2733 // CHECK7-NEXT: entry: 2734 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2735 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2736 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2737 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2738 // CHECK7-NEXT: ret void 2739 // 2740 // 2741 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2742 // CHECK7-SAME: () #[[ATTR0]] { 2743 // CHECK7-NEXT: entry: 2744 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 2745 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 2746 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 2747 // CHECK7-NEXT: ret void 2748 // 2749 // 2750 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2751 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2752 // CHECK7-NEXT: entry: 2753 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2754 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2755 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2756 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2757 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2758 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2759 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2760 // CHECK7-NEXT: ret void 2761 // 2762 // 2763 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2764 // CHECK7-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2765 // CHECK7-NEXT: entry: 2766 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2767 // CHECK7-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2768 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2769 // CHECK7: arraydestroy.body: 2770 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2771 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2772 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2773 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 2774 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2775 // CHECK7: arraydestroy.done1: 2776 // CHECK7-NEXT: ret void 2777 // 2778 // 2779 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2780 // CHECK7-SAME: () #[[ATTR0]] { 2781 // CHECK7-NEXT: entry: 2782 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2783 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 2784 // CHECK7-NEXT: ret void 2785 // 2786 // 2787 // CHECK7-LABEL: define {{[^@]+}}@main 2788 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] { 2789 // CHECK7-NEXT: entry: 2790 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2791 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 2792 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2793 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2794 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2795 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2796 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 2797 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2798 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2799 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2800 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 2801 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2802 // CHECK7: omp.inner.for.cond: 2803 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 2804 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 2805 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 2806 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2807 // CHECK7: omp.inner.for.body: 2808 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 2809 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 2810 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2811 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 2812 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP2]] 2813 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 2814 // CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 2815 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i64 0, i64 [[IDXPROM]] 2816 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] 2817 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 2818 // CHECK7-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 2819 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i64 0, i64 [[IDXPROM1]] 2820 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 @var, i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] 2821 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 2822 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] 2823 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] 2824 // CHECK7-NEXT: store i32 [[ADD3]], ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] 2825 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2826 // CHECK7: omp.body.continue: 2827 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2828 // CHECK7: omp.inner.for.inc: 2829 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 2830 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 2831 // CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 2832 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 2833 // CHECK7: omp.inner.for.end: 2834 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 2835 // CHECK7-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 2836 // CHECK7-NEXT: ret i32 [[CALL]] 2837 // 2838 // 2839 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2840 // CHECK7-SAME: () #[[ATTR1]] comdat { 2841 // CHECK7-NEXT: entry: 2842 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2843 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2844 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2845 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2846 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2847 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 8 2848 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 8 2849 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2850 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2851 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2852 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2853 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2854 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 2855 // CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 4 2856 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 2857 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 2858 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 2859 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 2860 // CHECK7-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 2861 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 2862 // CHECK7-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 2863 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8 2864 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR]], align 8 2865 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR]], align 8 2866 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2867 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2868 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2869 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2870 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2871 // CHECK7: omp.inner.for.cond: 2872 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 2873 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 2874 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2875 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2876 // CHECK7: omp.inner.for.body: 2877 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 2878 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2879 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2880 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 2881 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP6]] 2882 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 2883 // CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 2884 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 2885 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] 2886 // CHECK7-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP]], align 8, !llvm.access.group [[ACC_GRP6]] 2887 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 2888 // CHECK7-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP11]] to i64 2889 // CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] 2890 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] 2891 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2892 // CHECK7: omp.body.continue: 2893 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2894 // CHECK7: omp.inner.for.inc: 2895 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 2896 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 2897 // CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 2898 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 2899 // CHECK7: omp.inner.for.end: 2900 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 2901 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 2902 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 2903 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 2904 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2905 // CHECK7: arraydestroy.body: 2906 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2907 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2908 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2909 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2910 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 2911 // CHECK7: arraydestroy.done5: 2912 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 2913 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 2914 // CHECK7-NEXT: ret i32 [[TMP14]] 2915 // 2916 // 2917 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2918 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2919 // CHECK7-NEXT: entry: 2920 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2921 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2922 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2923 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2924 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2925 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2926 // CHECK7-NEXT: store float [[CONV]], ptr [[F]], align 4 2927 // CHECK7-NEXT: ret void 2928 // 2929 // 2930 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2931 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2932 // CHECK7-NEXT: entry: 2933 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2934 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2935 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2936 // CHECK7-NEXT: ret void 2937 // 2938 // 2939 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2940 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2941 // CHECK7-NEXT: entry: 2942 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2943 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2944 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2945 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2946 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2947 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2948 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2949 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2950 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2951 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2952 // CHECK7-NEXT: store float [[ADD]], ptr [[F]], align 4 2953 // CHECK7-NEXT: ret void 2954 // 2955 // 2956 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2957 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2958 // CHECK7-NEXT: entry: 2959 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2960 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2961 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2962 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2963 // CHECK7-NEXT: ret void 2964 // 2965 // 2966 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2967 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2968 // CHECK7-NEXT: entry: 2969 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2970 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2971 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2972 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2973 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2974 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2975 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 2976 // CHECK7-NEXT: ret void 2977 // 2978 // 2979 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2980 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2981 // CHECK7-NEXT: entry: 2982 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2983 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2984 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2985 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2986 // CHECK7-NEXT: ret void 2987 // 2988 // 2989 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2990 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2991 // CHECK7-NEXT: entry: 2992 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2993 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2994 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2995 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2996 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2997 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 2998 // CHECK7-NEXT: ret void 2999 // 3000 // 3001 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3002 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3003 // CHECK7-NEXT: entry: 3004 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3005 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3006 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3007 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3008 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3009 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 3010 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3011 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 3012 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3013 // CHECK7-NEXT: store i32 [[ADD]], ptr [[F]], align 4 3014 // CHECK7-NEXT: ret void 3015 // 3016 // 3017 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3018 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3019 // CHECK7-NEXT: entry: 3020 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3021 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3022 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3023 // CHECK7-NEXT: ret void 3024 // 3025 // 3026 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp 3027 // CHECK7-SAME: () #[[ATTR0]] { 3028 // CHECK7-NEXT: entry: 3029 // CHECK7-NEXT: call void @__cxx_global_var_init() 3030 // CHECK7-NEXT: call void @__cxx_global_var_init.1() 3031 // CHECK7-NEXT: call void @__cxx_global_var_init.2() 3032 // CHECK7-NEXT: ret void 3033 // 3034 // 3035 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 3036 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 3037 // CHECK9-NEXT: entry: 3038 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 3039 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 3040 // CHECK9-NEXT: ret void 3041 // 3042 // 3043 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3044 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3045 // CHECK9-NEXT: entry: 3046 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3047 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3048 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3049 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 3050 // CHECK9-NEXT: ret void 3051 // 3052 // 3053 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3054 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3055 // CHECK9-NEXT: entry: 3056 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3057 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3058 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3059 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3060 // CHECK9-NEXT: ret void 3061 // 3062 // 3063 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 3064 // CHECK9-SAME: () #[[ATTR0]] { 3065 // CHECK9-NEXT: entry: 3066 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 3067 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 3068 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 3069 // CHECK9-NEXT: ret void 3070 // 3071 // 3072 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3073 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3074 // CHECK9-NEXT: entry: 3075 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3076 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3077 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3078 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 3079 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3080 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 3081 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 3082 // CHECK9-NEXT: ret void 3083 // 3084 // 3085 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 3086 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 3087 // CHECK9-NEXT: entry: 3088 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 3089 // CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 3090 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3091 // CHECK9: arraydestroy.body: 3092 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3093 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3094 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3095 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 3096 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3097 // CHECK9: arraydestroy.done1: 3098 // CHECK9-NEXT: ret void 3099 // 3100 // 3101 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 3102 // CHECK9-SAME: () #[[ATTR0]] { 3103 // CHECK9-NEXT: entry: 3104 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 3105 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 3106 // CHECK9-NEXT: ret void 3107 // 3108 // 3109 // CHECK9-LABEL: define {{[^@]+}}@main 3110 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 3111 // CHECK9-NEXT: entry: 3112 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3113 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 3114 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3115 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3116 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3117 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 3118 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 3119 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3120 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 3121 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3122 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 3123 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3124 // CHECK9: omp.inner.for.cond: 3125 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 3126 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 3127 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 3128 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3129 // CHECK9: omp.inner.for.body: 3130 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 3131 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 3132 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3133 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 3134 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP3]] 3135 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 3136 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i32 0, i32 [[TMP5]] 3137 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] 3138 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 3139 // CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i32 0, i32 [[TMP6]] 3140 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 @var, i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] 3141 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 3142 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]] 3143 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] 3144 // CHECK9-NEXT: store i32 [[ADD2]], ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]] 3145 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3146 // CHECK9: omp.body.continue: 3147 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3148 // CHECK9: omp.inner.for.inc: 3149 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 3150 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 3151 // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 3152 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 3153 // CHECK9: omp.inner.for.end: 3154 // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 3155 // CHECK9-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 3156 // CHECK9-NEXT: ret i32 [[CALL]] 3157 // 3158 // 3159 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 3160 // CHECK9-SAME: () #[[ATTR1]] comdat { 3161 // CHECK9-NEXT: entry: 3162 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3163 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3164 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3165 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3166 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 3167 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 4 3168 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 4 3169 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3170 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3171 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3172 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3173 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 3174 // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 3175 // CHECK9-NEXT: store i32 0, ptr [[T_VAR]], align 4 3176 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 3177 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 3178 // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 3179 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 3180 // CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 3181 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 3182 // CHECK9-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 3183 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 4 3184 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR]], align 4 3185 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR]], align 4 3186 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3187 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 3188 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3189 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 3190 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3191 // CHECK9: omp.inner.for.cond: 3192 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 3193 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]] 3194 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3195 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3196 // CHECK9: omp.inner.for.body: 3197 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 3198 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 3199 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3200 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 3201 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP7]] 3202 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 3203 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] 3204 // CHECK9-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] 3205 // CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP]], align 4, !llvm.access.group [[ACC_GRP7]] 3206 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 3207 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] 3208 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] 3209 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3210 // CHECK9: omp.body.continue: 3211 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3212 // CHECK9: omp.inner.for.inc: 3213 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 3214 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 3215 // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 3216 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 3217 // CHECK9: omp.inner.for.end: 3218 // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 3219 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 3220 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 3221 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 3222 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3223 // CHECK9: arraydestroy.body: 3224 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3225 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3226 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3227 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 3228 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] 3229 // CHECK9: arraydestroy.done4: 3230 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 3231 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 3232 // CHECK9-NEXT: ret i32 [[TMP14]] 3233 // 3234 // 3235 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3236 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3237 // CHECK9-NEXT: entry: 3238 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3239 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3240 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3241 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 3242 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 3243 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3244 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 3245 // CHECK9-NEXT: ret void 3246 // 3247 // 3248 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3249 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3250 // CHECK9-NEXT: entry: 3251 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3252 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3253 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3254 // CHECK9-NEXT: ret void 3255 // 3256 // 3257 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3258 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3259 // CHECK9-NEXT: entry: 3260 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3261 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3262 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3263 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 3264 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3265 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 3266 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 3267 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 3268 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3269 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3270 // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 3271 // CHECK9-NEXT: ret void 3272 // 3273 // 3274 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3275 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3276 // CHECK9-NEXT: entry: 3277 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3278 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3279 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3280 // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 3281 // CHECK9-NEXT: ret void 3282 // 3283 // 3284 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3285 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3286 // CHECK9-NEXT: entry: 3287 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3288 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3289 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3290 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3291 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3292 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3293 // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 3294 // CHECK9-NEXT: ret void 3295 // 3296 // 3297 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3298 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3299 // CHECK9-NEXT: entry: 3300 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3301 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3302 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3303 // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3304 // CHECK9-NEXT: ret void 3305 // 3306 // 3307 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3308 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3309 // CHECK9-NEXT: entry: 3310 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3311 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3312 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3313 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 3314 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 3315 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 3316 // CHECK9-NEXT: ret void 3317 // 3318 // 3319 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3320 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3321 // CHECK9-NEXT: entry: 3322 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3323 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3324 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3325 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3326 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3327 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 3328 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3329 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 3330 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3331 // CHECK9-NEXT: store i32 [[ADD]], ptr [[F]], align 4 3332 // CHECK9-NEXT: ret void 3333 // 3334 // 3335 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3336 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3337 // CHECK9-NEXT: entry: 3338 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3339 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3340 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3341 // CHECK9-NEXT: ret void 3342 // 3343 // 3344 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp 3345 // CHECK9-SAME: () #[[ATTR0]] { 3346 // CHECK9-NEXT: entry: 3347 // CHECK9-NEXT: call void @__cxx_global_var_init() 3348 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 3349 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 3350 // CHECK9-NEXT: ret void 3351 // 3352 // 3353 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init 3354 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 3355 // CHECK11-NEXT: entry: 3356 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 3357 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 3358 // CHECK11-NEXT: ret void 3359 // 3360 // 3361 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3362 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 3363 // CHECK11-NEXT: entry: 3364 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3365 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3366 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3367 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 3368 // CHECK11-NEXT: ret void 3369 // 3370 // 3371 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3372 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3373 // CHECK11-NEXT: entry: 3374 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3375 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3376 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3377 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3378 // CHECK11-NEXT: ret void 3379 // 3380 // 3381 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 3382 // CHECK11-SAME: () #[[ATTR0]] { 3383 // CHECK11-NEXT: entry: 3384 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 3385 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 3386 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 3387 // CHECK11-NEXT: ret void 3388 // 3389 // 3390 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3391 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3392 // CHECK11-NEXT: entry: 3393 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3394 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3395 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3396 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 3397 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3398 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 3399 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 3400 // CHECK11-NEXT: ret void 3401 // 3402 // 3403 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 3404 // CHECK11-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 3405 // CHECK11-NEXT: entry: 3406 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 3407 // CHECK11-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 3408 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3409 // CHECK11: arraydestroy.body: 3410 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3411 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3412 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3413 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 3414 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3415 // CHECK11: arraydestroy.done1: 3416 // CHECK11-NEXT: ret void 3417 // 3418 // 3419 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 3420 // CHECK11-SAME: () #[[ATTR0]] { 3421 // CHECK11-NEXT: entry: 3422 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 3423 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 3424 // CHECK11-NEXT: ret void 3425 // 3426 // 3427 // CHECK11-LABEL: define {{[^@]+}}@main 3428 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 3429 // CHECK11-NEXT: entry: 3430 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3431 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 3432 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 3433 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 3434 // CHECK11-NEXT: ret i32 0 3435 // 3436 // 3437 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3438 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3439 // CHECK11-NEXT: entry: 3440 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3441 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3442 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3443 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 3444 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 3445 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3446 // CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4 3447 // CHECK11-NEXT: ret void 3448 // 3449 // 3450 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3451 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3452 // CHECK11-NEXT: entry: 3453 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3454 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3455 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3456 // CHECK11-NEXT: ret void 3457 // 3458 // 3459 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3460 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 3461 // CHECK11-NEXT: entry: 3462 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3463 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3464 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3465 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 3466 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3467 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 3468 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 3469 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 3470 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3471 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3472 // CHECK11-NEXT: store float [[ADD]], ptr [[F]], align 4 3473 // CHECK11-NEXT: ret void 3474 // 3475 // 3476 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp 3477 // CHECK11-SAME: () #[[ATTR0]] { 3478 // CHECK11-NEXT: entry: 3479 // CHECK11-NEXT: call void @__cxx_global_var_init() 3480 // CHECK11-NEXT: call void @__cxx_global_var_init.1() 3481 // CHECK11-NEXT: call void @__cxx_global_var_init.2() 3482 // CHECK11-NEXT: ret void 3483 // 3484 // 3485 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 3486 // CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { 3487 // CHECK13-NEXT: entry: 3488 // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 3489 // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 3490 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 3491 // CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 3492 // CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 3493 // CHECK13-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 3494 // CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 3495 // CHECK13-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 3496 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 3497 // CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 3498 // CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 3499 // CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 3500 // CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 3501 // CHECK13-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 3502 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 3503 // CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 3504 // CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 3505 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 3506 // CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 3507 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 3508 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 3509 // CHECK13-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 3510 // CHECK13-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 3511 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]]) 3512 // CHECK13-NEXT: ret void 3513 // 3514 // 3515 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined 3516 // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { 3517 // CHECK13-NEXT: entry: 3518 // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3519 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3520 // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 3521 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 3522 // CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 3523 // CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 3524 // CHECK13-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 3525 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3526 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 3527 // CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 3528 // CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 3529 // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3530 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3531 // CHECK13-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 3532 // CHECK13-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 3533 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 3534 // CHECK13-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 3535 // CHECK13-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 3536 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 3537 // CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 3538 // CHECK13-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 3539 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3540 // CHECK13-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3541 // CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 3542 // CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 3543 // CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 3544 // CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 3545 // CHECK13-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 3546 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 3547 // CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 3548 // CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 3549 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 3550 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 3551 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3552 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3553 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) 3554 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 3555 // CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 3556 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 3557 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3558 // CHECK13: omp.arraycpy.body: 3559 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3560 // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3561 // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 3562 // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 3563 // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3:[0-9]+]] 3564 // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3565 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3566 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 3567 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 3568 // CHECK13: omp.arraycpy.done3: 3569 // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 3570 // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 3571 // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR3]] 3572 // CHECK13-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3573 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 3574 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3575 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3576 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 3577 // CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3578 // CHECK13: cond.true: 3579 // CHECK13-NEXT: br label [[COND_END:%.*]] 3580 // CHECK13: cond.false: 3581 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3582 // CHECK13-NEXT: br label [[COND_END]] 3583 // CHECK13: cond.end: 3584 // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3585 // CHECK13-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 3586 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 3587 // CHECK13-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 3588 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3589 // CHECK13: omp.inner.for.cond: 3590 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 3591 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 3592 // CHECK13-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 3593 // CHECK13-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3594 // CHECK13: omp.inner.for.cond.cleanup: 3595 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3596 // CHECK13: omp.inner.for.body: 3597 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP6]] 3598 // CHECK13-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 3599 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 3600 // CHECK13-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 3601 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP6]] 3602 // CHECK13-NEXT: store i32 [[TMP15]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP6]] 3603 // CHECK13-NEXT: [[TMP16:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP6]] 3604 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP6]] 3605 // CHECK13-NEXT: store i32 [[TMP17]], ptr [[SIVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP6]] 3606 // CHECK13-NEXT: [[TMP18:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP6]] 3607 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], ptr [[VEC1]], i64 [[TMP16]], ptr [[S_ARR2]], ptr [[VAR4]], i64 [[TMP18]]), !llvm.access.group [[ACC_GRP6]] 3608 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3609 // CHECK13: omp.inner.for.inc: 3610 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 3611 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP6]] 3612 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] 3613 // CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 3614 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 3615 // CHECK13: omp.inner.for.end: 3616 // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3617 // CHECK13: omp.loop.exit: 3618 // CHECK13-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3619 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 3620 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) 3621 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3622 // CHECK13-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 3623 // CHECK13-NEXT: br i1 [[TMP24]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3624 // CHECK13: .omp.final.then: 3625 // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 3626 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] 3627 // CHECK13: .omp.final.done: 3628 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR3]] 3629 // CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 3630 // CHECK13-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 3631 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3632 // CHECK13: arraydestroy.body: 3633 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3634 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3635 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 3636 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 3637 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 3638 // CHECK13: arraydestroy.done8: 3639 // CHECK13-NEXT: ret void 3640 // 3641 // 3642 // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC1Ev 3643 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat { 3644 // CHECK13-NEXT: entry: 3645 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3646 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3647 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3648 // CHECK13-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 3649 // CHECK13-NEXT: ret void 3650 // 3651 // 3652 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 3653 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat { 3654 // CHECK13-NEXT: entry: 3655 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3656 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 3657 // CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 3658 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3659 // CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 3660 // CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 3661 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3662 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 3663 // CHECK13-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 3664 // CHECK13-NEXT: ret void 3665 // 3666 // 3667 // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD1Ev 3668 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 3669 // CHECK13-NEXT: entry: 3670 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3671 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3672 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3673 // CHECK13-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] 3674 // CHECK13-NEXT: ret void 3675 // 3676 // 3677 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined.omp_outlined 3678 // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { 3679 // CHECK13-NEXT: entry: 3680 // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3681 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3682 // CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 3683 // CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 3684 // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 3685 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 3686 // CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 3687 // CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 3688 // CHECK13-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 3689 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3690 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 3691 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3692 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3693 // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3694 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3695 // CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 3696 // CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 3697 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 3698 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 3699 // CHECK13-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 3700 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 3701 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3702 // CHECK13-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3703 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 3704 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 3705 // CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 3706 // CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 3707 // CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 3708 // CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 3709 // CHECK13-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 3710 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 3711 // CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 3712 // CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 3713 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3714 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 3715 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 3716 // CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 3717 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 3718 // CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP4]] to i32 3719 // CHECK13-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 3720 // CHECK13-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 3721 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3722 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3723 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) 3724 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 3725 // CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 3726 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 3727 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3728 // CHECK13: omp.arraycpy.body: 3729 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3730 // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3731 // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 3732 // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 3733 // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] 3734 // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3735 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3736 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 3737 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 3738 // CHECK13: omp.arraycpy.done4: 3739 // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 3740 // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP6]]) 3741 // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] 3742 // CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3743 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 3744 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3745 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3746 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 3747 // CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3748 // CHECK13: cond.true: 3749 // CHECK13-NEXT: br label [[COND_END:%.*]] 3750 // CHECK13: cond.false: 3751 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3752 // CHECK13-NEXT: br label [[COND_END]] 3753 // CHECK13: cond.end: 3754 // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] 3755 // CHECK13-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3756 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3757 // CHECK13-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 3758 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3759 // CHECK13: omp.inner.for.cond: 3760 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 3761 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 3762 // CHECK13-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 3763 // CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3764 // CHECK13: omp.inner.for.cond.cleanup: 3765 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3766 // CHECK13: omp.inner.for.body: 3767 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 3768 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 3769 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3770 // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 3771 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]] 3772 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 3773 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 3774 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] 3775 // CHECK13-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] 3776 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 3777 // CHECK13-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 3778 // CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] 3779 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR5]], i64 4, i1 false), !llvm.access.group [[ACC_GRP10]] 3780 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 3781 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]] 3782 // CHECK13-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP18]], [[TMP17]] 3783 // CHECK13-NEXT: store i32 [[ADD10]], ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]] 3784 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3785 // CHECK13: omp.body.continue: 3786 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3787 // CHECK13: omp.inner.for.inc: 3788 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 3789 // CHECK13-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP19]], 1 3790 // CHECK13-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 3791 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 3792 // CHECK13: omp.inner.for.end: 3793 // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3794 // CHECK13: omp.loop.exit: 3795 // CHECK13-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3796 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 3797 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 3798 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3799 // CHECK13-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 3800 // CHECK13-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3801 // CHECK13: .omp.final.then: 3802 // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 3803 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] 3804 // CHECK13: .omp.final.done: 3805 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] 3806 // CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 3807 // CHECK13-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 3808 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3809 // CHECK13: arraydestroy.body: 3810 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3811 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3812 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 3813 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 3814 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 3815 // CHECK13: arraydestroy.done13: 3816 // CHECK13-NEXT: ret void 3817 // 3818 // 3819 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3820 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 3821 // CHECK13-NEXT: entry: 3822 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3823 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3824 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3825 // CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] 3826 // CHECK13-NEXT: ret void 3827 // 3828 // 3829 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 3830 // CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { 3831 // CHECK13-NEXT: entry: 3832 // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 3833 // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 3834 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 3835 // CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 3836 // CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 3837 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 3838 // CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 3839 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 3840 // CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 3841 // CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 3842 // CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 3843 // CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 3844 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 3845 // CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 3846 // CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 3847 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 3848 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 3849 // CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 3850 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 3851 // CHECK13-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 3852 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) 3853 // CHECK13-NEXT: ret void 3854 // 3855 // 3856 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined 3857 // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { 3858 // CHECK13-NEXT: entry: 3859 // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3860 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3861 // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 3862 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 3863 // CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 3864 // CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 3865 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 3866 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3867 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3868 // CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 3869 // CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 3870 // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3871 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3872 // CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 3873 // CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 3874 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 3875 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3876 // CHECK13-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 3877 // CHECK13-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 3878 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 3879 // CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 3880 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3881 // CHECK13-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3882 // CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 3883 // CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 3884 // CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 3885 // CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 3886 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 3887 // CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 3888 // CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 3889 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 3890 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 3891 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 3892 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3893 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3894 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) 3895 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 3896 // CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 3897 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 3898 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3899 // CHECK13: omp.arraycpy.body: 3900 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3901 // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3902 // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 3903 // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 3904 // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] 3905 // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3906 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3907 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 3908 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 3909 // CHECK13: omp.arraycpy.done4: 3910 // CHECK13-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 3911 // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 3912 // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) 3913 // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] 3914 // CHECK13-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8 3915 // CHECK13-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3916 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 3917 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3918 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3919 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 3920 // CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3921 // CHECK13: cond.true: 3922 // CHECK13-NEXT: br label [[COND_END:%.*]] 3923 // CHECK13: cond.false: 3924 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3925 // CHECK13-NEXT: br label [[COND_END]] 3926 // CHECK13: cond.end: 3927 // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 3928 // CHECK13-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 3929 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 3930 // CHECK13-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 3931 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3932 // CHECK13: omp.inner.for.cond: 3933 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] 3934 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 3935 // CHECK13-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 3936 // CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3937 // CHECK13: omp.inner.for.cond.cleanup: 3938 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3939 // CHECK13: omp.inner.for.body: 3940 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]] 3941 // CHECK13-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 3942 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 3943 // CHECK13-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 3944 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP15]] 3945 // CHECK13-NEXT: store i32 [[TMP16]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP15]] 3946 // CHECK13-NEXT: [[TMP17:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP15]] 3947 // CHECK13-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP15]] 3948 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined.omp_outlined, i64 [[TMP13]], i64 [[TMP15]], ptr [[VEC2]], i64 [[TMP17]], ptr [[S_ARR3]], ptr [[TMP18]]), !llvm.access.group [[ACC_GRP15]] 3949 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3950 // CHECK13: omp.inner.for.inc: 3951 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 3952 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]] 3953 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] 3954 // CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 3955 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 3956 // CHECK13: omp.inner.for.end: 3957 // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3958 // CHECK13: omp.loop.exit: 3959 // CHECK13-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3960 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 3961 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) 3962 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3963 // CHECK13-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 3964 // CHECK13-NEXT: br i1 [[TMP24]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3965 // CHECK13: .omp.final.then: 3966 // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 3967 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] 3968 // CHECK13: .omp.final.done: 3969 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] 3970 // CHECK13-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 3971 // CHECK13-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 2 3972 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3973 // CHECK13: arraydestroy.body: 3974 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3975 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3976 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 3977 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] 3978 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] 3979 // CHECK13: arraydestroy.done10: 3980 // CHECK13-NEXT: ret void 3981 // 3982 // 3983 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 3984 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat { 3985 // CHECK13-NEXT: entry: 3986 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3987 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 3988 // CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 3989 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3990 // CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 3991 // CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 3992 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3993 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 3994 // CHECK13-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 3995 // CHECK13-NEXT: ret void 3996 // 3997 // 3998 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined.omp_outlined 3999 // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { 4000 // CHECK13-NEXT: entry: 4001 // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4002 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4003 // CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 4004 // CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 4005 // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 4006 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 4007 // CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 4008 // CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 4009 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 4010 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4011 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 4012 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4013 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4014 // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4015 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4016 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 4017 // CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 4018 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 4019 // CHECK13-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 4020 // CHECK13-NEXT: [[AGG_TMP7:%.*]] = alloca [[STRUCT_ST]], align 4 4021 // CHECK13-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 4022 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 4023 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4024 // CHECK13-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4025 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 4026 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 4027 // CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 4028 // CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 4029 // CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 4030 // CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 4031 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 4032 // CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 4033 // CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 4034 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 4035 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4036 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 4037 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 4038 // CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 4039 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 4040 // CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32 4041 // CHECK13-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 4042 // CHECK13-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 4043 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4044 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4045 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false) 4046 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 4047 // CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 4048 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 4049 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 4050 // CHECK13: omp.arraycpy.body: 4051 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 4052 // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 4053 // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 4054 // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 4055 // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] 4056 // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 4057 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 4058 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 4059 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]] 4060 // CHECK13: omp.arraycpy.done5: 4061 // CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 4062 // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) 4063 // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP7]]) 4064 // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) #[[ATTR3]] 4065 // CHECK13-NEXT: store ptr [[VAR6]], ptr [[_TMP8]], align 8 4066 // CHECK13-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4067 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 4068 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 4069 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4070 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 4071 // CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4072 // CHECK13: cond.true: 4073 // CHECK13-NEXT: br label [[COND_END:%.*]] 4074 // CHECK13: cond.false: 4075 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4076 // CHECK13-NEXT: br label [[COND_END]] 4077 // CHECK13: cond.end: 4078 // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 4079 // CHECK13-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4080 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4081 // CHECK13-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 4082 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4083 // CHECK13: omp.inner.for.cond: 4084 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] 4085 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] 4086 // CHECK13-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 4087 // CHECK13-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 4088 // CHECK13: omp.inner.for.cond.cleanup: 4089 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 4090 // CHECK13: omp.inner.for.body: 4091 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 4092 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 4093 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4094 // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 4095 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP18]] 4096 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 4097 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 4098 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] 4099 // CHECK13-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] 4100 // CHECK13-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8, !llvm.access.group [[ACC_GRP18]] 4101 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 4102 // CHECK13-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 4103 // CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] 4104 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP18]] 4105 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4106 // CHECK13: omp.body.continue: 4107 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4108 // CHECK13: omp.inner.for.inc: 4109 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 4110 // CHECK13-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 4111 // CHECK13-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 4112 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 4113 // CHECK13: omp.inner.for.end: 4114 // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4115 // CHECK13: omp.loop.exit: 4116 // CHECK13-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4117 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 4118 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 4119 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4120 // CHECK13-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 4121 // CHECK13-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4122 // CHECK13: .omp.final.then: 4123 // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 4124 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] 4125 // CHECK13: .omp.final.done: 4126 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR3]] 4127 // CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 4128 // CHECK13-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 4129 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4130 // CHECK13: arraydestroy.body: 4131 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4132 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4133 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 4134 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] 4135 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] 4136 // CHECK13: arraydestroy.done14: 4137 // CHECK13-NEXT: ret void 4138 // 4139 // 4140 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 4141 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 4142 // CHECK13-NEXT: entry: 4143 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4144 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4145 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4146 // CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] 4147 // CHECK13-NEXT: ret void 4148 // 4149 // 4150 // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC2Ev 4151 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 4152 // CHECK13-NEXT: entry: 4153 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4154 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4155 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4156 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 4157 // CHECK13-NEXT: store i32 0, ptr [[A]], align 4 4158 // CHECK13-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 4159 // CHECK13-NEXT: store i32 0, ptr [[B]], align 4 4160 // CHECK13-NEXT: ret void 4161 // 4162 // 4163 // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD2Ev 4164 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 4165 // CHECK13-NEXT: entry: 4166 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4167 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4168 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4169 // CHECK13-NEXT: ret void 4170 // 4171 // 4172 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4173 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 4174 // CHECK13-NEXT: entry: 4175 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4176 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4177 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4178 // CHECK13-NEXT: ret void 4179 // 4180 // 4181 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 4182 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat { 4183 // CHECK13-NEXT: entry: 4184 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4185 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 4186 // CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 4187 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4188 // CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 4189 // CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 4190 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4191 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 4192 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 4193 // CHECK13-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 4194 // CHECK13-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 4195 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 4196 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 4197 // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 4198 // CHECK13-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 4199 // CHECK13-NEXT: store float [[ADD]], ptr [[F]], align 4 4200 // CHECK13-NEXT: ret void 4201 // 4202 // 4203 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 4204 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 4205 // CHECK13-NEXT: entry: 4206 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4207 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4208 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4209 // CHECK13-NEXT: ret void 4210 // 4211 // 4212 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 4213 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat { 4214 // CHECK13-NEXT: entry: 4215 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4216 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 4217 // CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 4218 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4219 // CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 4220 // CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 4221 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4222 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 4223 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 4224 // CHECK13-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 4225 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 4226 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 4227 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 4228 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 4229 // CHECK13-NEXT: store i32 [[ADD]], ptr [[F]], align 4 4230 // CHECK13-NEXT: ret void 4231 // 4232 // 4233 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 4234 // CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { 4235 // CHECK15-NEXT: entry: 4236 // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 4237 // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 4238 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 4239 // CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 4240 // CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 4241 // CHECK15-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 4242 // CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 4243 // CHECK15-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 4244 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 4245 // CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 4246 // CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 4247 // CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 4248 // CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 4249 // CHECK15-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 4250 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 4251 // CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 4252 // CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 4253 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 4254 // CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 4255 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 4256 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 4257 // CHECK15-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 4258 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 4259 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]]) 4260 // CHECK15-NEXT: ret void 4261 // 4262 // 4263 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined 4264 // CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0]] { 4265 // CHECK15-NEXT: entry: 4266 // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4267 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4268 // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 4269 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 4270 // CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 4271 // CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 4272 // CHECK15-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 4273 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4274 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 4275 // CHECK15-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 4276 // CHECK15-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 4277 // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4278 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4279 // CHECK15-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 4280 // CHECK15-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 4281 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 4282 // CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 4283 // CHECK15-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 4284 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 4285 // CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 4286 // CHECK15-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 4287 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4288 // CHECK15-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4289 // CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 4290 // CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 4291 // CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 4292 // CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 4293 // CHECK15-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 4294 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 4295 // CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 4296 // CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 4297 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 4298 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 4299 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4300 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4301 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) 4302 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 4303 // CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 4304 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 4305 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 4306 // CHECK15: omp.arraycpy.body: 4307 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 4308 // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 4309 // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 4310 // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 4311 // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3:[0-9]+]] 4312 // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 4313 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 4314 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 4315 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 4316 // CHECK15: omp.arraycpy.done3: 4317 // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 4318 // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 4319 // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR3]] 4320 // CHECK15-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 4321 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 4322 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 4323 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 4324 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 4325 // CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4326 // CHECK15: cond.true: 4327 // CHECK15-NEXT: br label [[COND_END:%.*]] 4328 // CHECK15: cond.false: 4329 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 4330 // CHECK15-NEXT: br label [[COND_END]] 4331 // CHECK15: cond.end: 4332 // CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 4333 // CHECK15-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 4334 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 4335 // CHECK15-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 4336 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4337 // CHECK15: omp.inner.for.cond: 4338 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 4339 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP7]] 4340 // CHECK15-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 4341 // CHECK15-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 4342 // CHECK15: omp.inner.for.cond.cleanup: 4343 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 4344 // CHECK15: omp.inner.for.body: 4345 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP7]] 4346 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP7]] 4347 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP7]] 4348 // CHECK15-NEXT: store i32 [[TMP13]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP7]] 4349 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP7]] 4350 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP7]] 4351 // CHECK15-NEXT: store i32 [[TMP15]], ptr [[SIVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP7]] 4352 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP7]] 4353 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined.omp_outlined, i32 [[TMP11]], i32 [[TMP12]], ptr [[VEC1]], i32 [[TMP14]], ptr [[S_ARR2]], ptr [[VAR4]], i32 [[TMP16]]), !llvm.access.group [[ACC_GRP7]] 4354 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4355 // CHECK15: omp.inner.for.inc: 4356 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 4357 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP7]] 4358 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] 4359 // CHECK15-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 4360 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 4361 // CHECK15: omp.inner.for.end: 4362 // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4363 // CHECK15: omp.loop.exit: 4364 // CHECK15-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 4365 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 4366 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) 4367 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4368 // CHECK15-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 4369 // CHECK15-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4370 // CHECK15: .omp.final.then: 4371 // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 4372 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] 4373 // CHECK15: .omp.final.done: 4374 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR3]] 4375 // CHECK15-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 4376 // CHECK15-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 2 4377 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4378 // CHECK15: arraydestroy.body: 4379 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4380 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4381 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 4382 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 4383 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 4384 // CHECK15: arraydestroy.done8: 4385 // CHECK15-NEXT: ret void 4386 // 4387 // 4388 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC1Ev 4389 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { 4390 // CHECK15-NEXT: entry: 4391 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 4392 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 4393 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 4394 // CHECK15-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 4395 // CHECK15-NEXT: ret void 4396 // 4397 // 4398 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 4399 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 4400 // CHECK15-NEXT: entry: 4401 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 4402 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 4403 // CHECK15-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 4404 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 4405 // CHECK15-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 4406 // CHECK15-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 4407 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 4408 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 4409 // CHECK15-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 4410 // CHECK15-NEXT: ret void 4411 // 4412 // 4413 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD1Ev 4414 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 4415 // CHECK15-NEXT: entry: 4416 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 4417 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 4418 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 4419 // CHECK15-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] 4420 // CHECK15-NEXT: ret void 4421 // 4422 // 4423 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined.omp_outlined 4424 // CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0]] { 4425 // CHECK15-NEXT: entry: 4426 // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4427 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4428 // CHECK15-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 4429 // CHECK15-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 4430 // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 4431 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 4432 // CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 4433 // CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 4434 // CHECK15-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 4435 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4436 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 4437 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4438 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4439 // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4440 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4441 // CHECK15-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 4442 // CHECK15-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 4443 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 4444 // CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 4445 // CHECK15-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 4446 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 4447 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4448 // CHECK15-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4449 // CHECK15-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 4450 // CHECK15-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 4451 // CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 4452 // CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 4453 // CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 4454 // CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 4455 // CHECK15-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 4456 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 4457 // CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 4458 // CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 4459 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4460 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 4461 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 4462 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 4463 // CHECK15-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4 4464 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 4465 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4466 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4467 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) 4468 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 4469 // CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 4470 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 4471 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 4472 // CHECK15: omp.arraycpy.body: 4473 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 4474 // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 4475 // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 4476 // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 4477 // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] 4478 // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 4479 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 4480 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 4481 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 4482 // CHECK15: omp.arraycpy.done3: 4483 // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 4484 // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 4485 // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR3]] 4486 // CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 4487 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 4488 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 4489 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4490 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 4491 // CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4492 // CHECK15: cond.true: 4493 // CHECK15-NEXT: br label [[COND_END:%.*]] 4494 // CHECK15: cond.false: 4495 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4496 // CHECK15-NEXT: br label [[COND_END]] 4497 // CHECK15: cond.end: 4498 // CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] 4499 // CHECK15-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4500 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4501 // CHECK15-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 4502 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4503 // CHECK15: omp.inner.for.cond: 4504 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 4505 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 4506 // CHECK15-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 4507 // CHECK15-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 4508 // CHECK15: omp.inner.for.cond.cleanup: 4509 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 4510 // CHECK15: omp.inner.for.body: 4511 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 4512 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 4513 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4514 // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 4515 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP11]] 4516 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 4517 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP15]] 4518 // CHECK15-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] 4519 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 4520 // CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] 4521 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false), !llvm.access.group [[ACC_GRP11]] 4522 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 4523 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP11]] 4524 // CHECK15-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP18]], [[TMP17]] 4525 // CHECK15-NEXT: store i32 [[ADD8]], ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP11]] 4526 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4527 // CHECK15: omp.body.continue: 4528 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4529 // CHECK15: omp.inner.for.inc: 4530 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 4531 // CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1 4532 // CHECK15-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 4533 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 4534 // CHECK15: omp.inner.for.end: 4535 // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4536 // CHECK15: omp.loop.exit: 4537 // CHECK15-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 4538 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 4539 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 4540 // CHECK15-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4541 // CHECK15-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 4542 // CHECK15-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4543 // CHECK15: .omp.final.then: 4544 // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 4545 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] 4546 // CHECK15: .omp.final.done: 4547 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR3]] 4548 // CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 4549 // CHECK15-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 4550 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4551 // CHECK15: arraydestroy.body: 4552 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4553 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4554 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 4555 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 4556 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 4557 // CHECK15: arraydestroy.done11: 4558 // CHECK15-NEXT: ret void 4559 // 4560 // 4561 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4562 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 4563 // CHECK15-NEXT: entry: 4564 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 4565 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 4566 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 4567 // CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] 4568 // CHECK15-NEXT: ret void 4569 // 4570 // 4571 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 4572 // CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { 4573 // CHECK15-NEXT: entry: 4574 // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 4575 // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 4576 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 4577 // CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 4578 // CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 4579 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 4580 // CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 4581 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 4582 // CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 4583 // CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 4584 // CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 4585 // CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 4586 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 4587 // CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 4588 // CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 4589 // CHECK15-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 4590 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 4591 // CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 4592 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 4593 // CHECK15-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 4594 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) 4595 // CHECK15-NEXT: ret void 4596 // 4597 // 4598 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined 4599 // CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { 4600 // CHECK15-NEXT: entry: 4601 // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4602 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4603 // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 4604 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 4605 // CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 4606 // CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 4607 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 4608 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4609 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 4610 // CHECK15-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 4611 // CHECK15-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 4612 // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4613 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4614 // CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 4615 // CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 4616 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 4617 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 4618 // CHECK15-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 4619 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 4620 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 4621 // CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 4622 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4623 // CHECK15-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4624 // CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 4625 // CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 4626 // CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 4627 // CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 4628 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 4629 // CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 4630 // CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 4631 // CHECK15-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 4632 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 4633 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 4634 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4635 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4636 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) 4637 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 4638 // CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 4639 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 4640 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 4641 // CHECK15: omp.arraycpy.body: 4642 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 4643 // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 4644 // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 4645 // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 4646 // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] 4647 // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 4648 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 4649 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 4650 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 4651 // CHECK15: omp.arraycpy.done4: 4652 // CHECK15-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 4653 // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 4654 // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) 4655 // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] 4656 // CHECK15-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 4657 // CHECK15-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 4658 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 4659 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 4660 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 4661 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 4662 // CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4663 // CHECK15: cond.true: 4664 // CHECK15-NEXT: br label [[COND_END:%.*]] 4665 // CHECK15: cond.false: 4666 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 4667 // CHECK15-NEXT: br label [[COND_END]] 4668 // CHECK15: cond.end: 4669 // CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 4670 // CHECK15-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 4671 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 4672 // CHECK15-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 4673 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4674 // CHECK15: omp.inner.for.cond: 4675 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] 4676 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP16]] 4677 // CHECK15-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 4678 // CHECK15-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 4679 // CHECK15: omp.inner.for.cond.cleanup: 4680 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 4681 // CHECK15: omp.inner.for.body: 4682 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP16]] 4683 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP16]] 4684 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP16]] 4685 // CHECK15-NEXT: store i32 [[TMP14]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP16]] 4686 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP16]] 4687 // CHECK15-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP16]] 4688 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined.omp_outlined, i32 [[TMP12]], i32 [[TMP13]], ptr [[VEC2]], i32 [[TMP15]], ptr [[S_ARR3]], ptr [[TMP16]]), !llvm.access.group [[ACC_GRP16]] 4689 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4690 // CHECK15: omp.inner.for.inc: 4691 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] 4692 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP16]] 4693 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] 4694 // CHECK15-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] 4695 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] 4696 // CHECK15: omp.inner.for.end: 4697 // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4698 // CHECK15: omp.loop.exit: 4699 // CHECK15-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 4700 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 4701 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) 4702 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4703 // CHECK15-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 4704 // CHECK15-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4705 // CHECK15: .omp.final.then: 4706 // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 4707 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] 4708 // CHECK15: .omp.final.done: 4709 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] 4710 // CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 4711 // CHECK15-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 4712 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4713 // CHECK15: arraydestroy.body: 4714 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4715 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4716 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 4717 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] 4718 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] 4719 // CHECK15: arraydestroy.done10: 4720 // CHECK15-NEXT: ret void 4721 // 4722 // 4723 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 4724 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 4725 // CHECK15-NEXT: entry: 4726 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 4727 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 4728 // CHECK15-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 4729 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 4730 // CHECK15-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 4731 // CHECK15-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 4732 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 4733 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 4734 // CHECK15-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 4735 // CHECK15-NEXT: ret void 4736 // 4737 // 4738 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined.omp_outlined 4739 // CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { 4740 // CHECK15-NEXT: entry: 4741 // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4742 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4743 // CHECK15-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 4744 // CHECK15-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 4745 // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 4746 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 4747 // CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 4748 // CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 4749 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 4750 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4751 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 4752 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4753 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4754 // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4755 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4756 // CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 4757 // CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 4758 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 4759 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 4760 // CHECK15-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 4761 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 4762 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 4763 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4764 // CHECK15-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4765 // CHECK15-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 4766 // CHECK15-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 4767 // CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 4768 // CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 4769 // CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 4770 // CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 4771 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 4772 // CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 4773 // CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 4774 // CHECK15-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 4775 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4776 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 4777 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 4778 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 4779 // CHECK15-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4 4780 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 4781 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4782 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4783 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) 4784 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 4785 // CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 4786 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 4787 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 4788 // CHECK15: omp.arraycpy.body: 4789 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 4790 // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 4791 // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 4792 // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 4793 // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] 4794 // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 4795 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 4796 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 4797 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 4798 // CHECK15: omp.arraycpy.done4: 4799 // CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 4800 // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 4801 // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP6]]) 4802 // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] 4803 // CHECK15-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 4804 // CHECK15-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 4805 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 4806 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 4807 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4808 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 4809 // CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4810 // CHECK15: cond.true: 4811 // CHECK15-NEXT: br label [[COND_END:%.*]] 4812 // CHECK15: cond.false: 4813 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4814 // CHECK15-NEXT: br label [[COND_END]] 4815 // CHECK15: cond.end: 4816 // CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 4817 // CHECK15-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4818 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4819 // CHECK15-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 4820 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4821 // CHECK15: omp.inner.for.cond: 4822 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] 4823 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] 4824 // CHECK15-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 4825 // CHECK15-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 4826 // CHECK15: omp.inner.for.cond.cleanup: 4827 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 4828 // CHECK15: omp.inner.for.body: 4829 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] 4830 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 4831 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4832 // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 4833 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP19]] 4834 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 4835 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]] 4836 // CHECK15-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] 4837 // CHECK15-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP19]] 4838 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 4839 // CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] 4840 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP19]] 4841 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4842 // CHECK15: omp.body.continue: 4843 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4844 // CHECK15: omp.inner.for.inc: 4845 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] 4846 // CHECK15-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 4847 // CHECK15-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] 4848 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 4849 // CHECK15: omp.inner.for.end: 4850 // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4851 // CHECK15: omp.loop.exit: 4852 // CHECK15-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 4853 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 4854 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 4855 // CHECK15-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4856 // CHECK15-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 4857 // CHECK15-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4858 // CHECK15: .omp.final.then: 4859 // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 4860 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] 4861 // CHECK15: .omp.final.done: 4862 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] 4863 // CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 4864 // CHECK15-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 4865 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4866 // CHECK15: arraydestroy.body: 4867 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4868 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4869 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 4870 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 4871 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 4872 // CHECK15: arraydestroy.done12: 4873 // CHECK15-NEXT: ret void 4874 // 4875 // 4876 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 4877 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 4878 // CHECK15-NEXT: entry: 4879 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 4880 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 4881 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 4882 // CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] 4883 // CHECK15-NEXT: ret void 4884 // 4885 // 4886 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC2Ev 4887 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 4888 // CHECK15-NEXT: entry: 4889 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 4890 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 4891 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 4892 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 4893 // CHECK15-NEXT: store i32 0, ptr [[A]], align 4 4894 // CHECK15-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 4895 // CHECK15-NEXT: store i32 0, ptr [[B]], align 4 4896 // CHECK15-NEXT: ret void 4897 // 4898 // 4899 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD2Ev 4900 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 4901 // CHECK15-NEXT: entry: 4902 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 4903 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 4904 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 4905 // CHECK15-NEXT: ret void 4906 // 4907 // 4908 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4909 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 4910 // CHECK15-NEXT: entry: 4911 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 4912 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 4913 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 4914 // CHECK15-NEXT: ret void 4915 // 4916 // 4917 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 4918 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 4919 // CHECK15-NEXT: entry: 4920 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 4921 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 4922 // CHECK15-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 4923 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 4924 // CHECK15-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 4925 // CHECK15-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 4926 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 4927 // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 4928 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 4929 // CHECK15-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 4930 // CHECK15-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 4931 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 4932 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 4933 // CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 4934 // CHECK15-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 4935 // CHECK15-NEXT: store float [[ADD]], ptr [[F]], align 4 4936 // CHECK15-NEXT: ret void 4937 // 4938 // 4939 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 4940 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 4941 // CHECK15-NEXT: entry: 4942 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 4943 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 4944 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 4945 // CHECK15-NEXT: ret void 4946 // 4947 // 4948 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 4949 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 4950 // CHECK15-NEXT: entry: 4951 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 4952 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 4953 // CHECK15-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 4954 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 4955 // CHECK15-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 4956 // CHECK15-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 4957 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 4958 // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 4959 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 4960 // CHECK15-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 4961 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 4962 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 4963 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 4964 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 4965 // CHECK15-NEXT: store i32 [[ADD]], ptr [[F]], align 4 4966 // CHECK15-NEXT: ret void 4967 // 4968 // 4969 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 4970 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { 4971 // CHECK17-NEXT: entry: 4972 // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 4973 // CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 4974 // CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 4975 // CHECK17-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 4976 // CHECK17-NEXT: [[TMP:%.*]] = alloca ptr, align 8 4977 // CHECK17-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 4978 // CHECK17-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 4979 // CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 4980 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 4981 // CHECK17-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 4982 // CHECK17-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 4983 // CHECK17-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 4984 // CHECK17-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 4985 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 4 4986 // CHECK17-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4 4987 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8 4988 // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 4989 // CHECK17-NEXT: [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 4 4990 // CHECK17-NEXT: store i32 [[TMP3]], ptr [[G1_CASTED]], align 4 4991 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 8 4992 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 4993 // CHECK17-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 4994 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 4995 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) 4996 // CHECK17-NEXT: ret void 4997 // 4998 // 4999 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined 5000 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { 5001 // CHECK17-NEXT: entry: 5002 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 5003 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 5004 // CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 5005 // CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 5006 // CHECK17-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 5007 // CHECK17-NEXT: [[TMP:%.*]] = alloca ptr, align 8 5008 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5009 // CHECK17-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 5010 // CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 5011 // CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 5012 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5013 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5014 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 5015 // CHECK17-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 5016 // CHECK17-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 5017 // CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 5018 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 5019 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 5020 // CHECK17-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 5021 // CHECK17-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 5022 // CHECK17-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 5023 // CHECK17-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 5024 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 5025 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 5026 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 5027 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5028 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 5029 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 5030 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 5031 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 5032 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 5033 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5034 // CHECK17: cond.true: 5035 // CHECK17-NEXT: br label [[COND_END:%.*]] 5036 // CHECK17: cond.false: 5037 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 5038 // CHECK17-NEXT: br label [[COND_END]] 5039 // CHECK17: cond.end: 5040 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 5041 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 5042 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 5043 // CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 5044 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5045 // CHECK17: omp.inner.for.cond: 5046 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] 5047 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 5048 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 5049 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5050 // CHECK17: omp.inner.for.body: 5051 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP5]] 5052 // CHECK17-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 5053 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 5054 // CHECK17-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 5055 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[G_ADDR]], align 4, !llvm.access.group [[ACC_GRP5]] 5056 // CHECK17-NEXT: store i32 [[TMP11]], ptr [[G_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]] 5057 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[G_CASTED]], align 8, !llvm.access.group [[ACC_GRP5]] 5058 // CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8, !llvm.access.group [[ACC_GRP5]] 5059 // CHECK17-NEXT: [[TMP14:%.*]] = load volatile i32, ptr [[TMP13]], align 4, !llvm.access.group [[ACC_GRP5]] 5060 // CHECK17-NEXT: store i32 [[TMP14]], ptr [[G1_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]] 5061 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[G1_CASTED]], align 8, !llvm.access.group [[ACC_GRP5]] 5062 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP5]] 5063 // CHECK17-NEXT: store i32 [[TMP16]], ptr [[SIVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]] 5064 // CHECK17-NEXT: [[TMP17:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP5]] 5065 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group [[ACC_GRP5]] 5066 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5067 // CHECK17: omp.inner.for.inc: 5068 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 5069 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP5]] 5070 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 5071 // CHECK17-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 5072 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 5073 // CHECK17: omp.inner.for.end: 5074 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5075 // CHECK17: omp.loop.exit: 5076 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 5077 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5078 // CHECK17-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 5079 // CHECK17-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5080 // CHECK17: .omp.final.then: 5081 // CHECK17-NEXT: store i32 2, ptr [[I]], align 4 5082 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 5083 // CHECK17: .omp.final.done: 5084 // CHECK17-NEXT: ret void 5085 // 5086 // 5087 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined.omp_outlined 5088 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { 5089 // CHECK17-NEXT: entry: 5090 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 5091 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 5092 // CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 5093 // CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 5094 // CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 5095 // CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 5096 // CHECK17-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 5097 // CHECK17-NEXT: [[TMP:%.*]] = alloca ptr, align 8 5098 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5099 // CHECK17-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 5100 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5101 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5102 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5103 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5104 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 5105 // CHECK17-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 5106 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 5107 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 5108 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 5109 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 5110 // CHECK17-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 5111 // CHECK17-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 5112 // CHECK17-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 5113 // CHECK17-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 5114 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5115 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 5116 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 5117 // CHECK17-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 5118 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 5119 // CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 5120 // CHECK17-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 5121 // CHECK17-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 5122 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 5123 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5124 // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 5125 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 5126 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 5127 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5128 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 5129 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5130 // CHECK17: cond.true: 5131 // CHECK17-NEXT: br label [[COND_END:%.*]] 5132 // CHECK17: cond.false: 5133 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5134 // CHECK17-NEXT: br label [[COND_END]] 5135 // CHECK17: cond.end: 5136 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 5137 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 5138 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5139 // CHECK17-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 5140 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5141 // CHECK17: omp.inner.for.cond: 5142 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] 5143 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 5144 // CHECK17-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 5145 // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5146 // CHECK17: omp.inner.for.body: 5147 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 5148 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 5149 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 5150 // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 5151 // CHECK17-NEXT: store i32 1, ptr [[G_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]] 5152 // CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP]], align 8, !llvm.access.group [[ACC_GRP9]] 5153 // CHECK17-NEXT: store volatile i32 1, ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP9]] 5154 // CHECK17-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]] 5155 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 5156 // CHECK17-NEXT: store ptr [[G_ADDR]], ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP9]] 5157 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 5158 // CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8, !llvm.access.group [[ACC_GRP9]] 5159 // CHECK17-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP9]] 5160 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 2 5161 // CHECK17-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP14]], align 8, !llvm.access.group [[ACC_GRP9]] 5162 // CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group [[ACC_GRP9]] 5163 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5164 // CHECK17: omp.body.continue: 5165 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5166 // CHECK17: omp.inner.for.inc: 5167 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 5168 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 5169 // CHECK17-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 5170 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 5171 // CHECK17: omp.inner.for.end: 5172 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5173 // CHECK17: omp.loop.exit: 5174 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 5175 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5176 // CHECK17-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 5177 // CHECK17-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5178 // CHECK17: .omp.final.then: 5179 // CHECK17-NEXT: store i32 2, ptr [[I]], align 4 5180 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 5181 // CHECK17: .omp.final.done: 5182 // CHECK17-NEXT: ret void 5183 // 5184