1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 12 13 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 17 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 23 24 // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region) 25 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 26 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 27 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 28 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 29 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 30 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 31 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 32 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 33 34 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 35 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17 36 37 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 38 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 39 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 40 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 41 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 42 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 43 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 44 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 45 46 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 47 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 48 49 // expected-no-diagnostics 50 #ifndef HEADER 51 #define HEADER 52 53 struct St { 54 int a, b; 55 St() : a(0), b(0) {} 56 St(const St &st) : a(st.a + st.b), b(0) {} 57 ~St() {} 58 }; 59 60 volatile int g = 1212; 61 volatile int &g1 = g; 62 63 template <class T> 64 struct S { 65 T f; 66 S(T a) : f(a + g) {} 67 S() : f(g) {} 68 S(const S &s, St t = St()) : f(s.f + t.a) {} 69 operator T() { return T(); } 70 ~S() {} 71 }; 72 73 74 template <typename T> 75 T tmain() { 76 S<T> test; 77 T t_var = T(); 78 T vec[] = {1, 2}; 79 S<T> s_arr[] = {1, 2}; 80 S<T> &var = test; 81 #pragma omp target teams distribute parallel for firstprivate(t_var, vec, s_arr, var) 82 for (int i = 0; i < 2; ++i) { 83 vec[i] = t_var; 84 s_arr[i] = var; 85 } 86 return T(); 87 } 88 89 S<float> test; 90 int t_var = 333; 91 int vec[] = {1, 2}; 92 S<float> s_arr[] = {1, 2}; 93 S<float> var(3); 94 95 int main() { 96 static int sivar; 97 #ifdef LAMBDA 98 [&]() { 99 #pragma omp target teams distribute parallel for firstprivate(g, g1, sivar) 100 for (int i = 0; i < 2; ++i) { 101 102 // Skip global and bound tid vars 103 // skip loop vars 104 g = 1; 105 g1 = 1; 106 sivar = 2; 107 108 // Skip global and bound tid vars, and prev lb and ub vars 109 // skip loop vars 110 111 // use of private vars 112 [&]() { 113 g = 2; 114 g1 = 2; 115 sivar = 4; 116 117 }(); 118 } 119 }(); 120 return 0; 121 #else 122 #pragma omp target teams distribute parallel for firstprivate(t_var, vec, s_arr, var, sivar) 123 for (int i = 0; i < 2; ++i) { 124 vec[i] = t_var; 125 s_arr[i] = var; 126 sivar += i; 127 } 128 return tmain<int>(); 129 #endif 130 } 131 132 133 134 135 136 // Skip global and bound tid vars 137 // Skip temp vars for loop 138 139 // param copy 140 141 // T_VAR and SIVAR 142 143 // preparation vars 144 145 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 146 147 // firstprivate(s_arr) 148 149 // firstprivate(var) 150 151 152 // Skip global and bound tid vars, and prev lb ub vars 153 // Skip temp vars for loop 154 155 // param copy 156 157 // T_VAR and SIVAR 158 159 // preparation vars 160 161 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 162 163 // firstprivate(s_arr) 164 165 // firstprivate(var) 166 167 168 169 170 171 172 // Skip global and bound tid vars 173 // Skip temp vars for loop 174 175 // param copy 176 177 // T_VAR and preparation variables 178 179 180 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 181 182 // firstprivate(s_arr) 183 184 // firstprivate(var) 185 186 187 // Skip global and bound tid vars 188 // Skip temp vars for loop 189 190 // param copy 191 192 // T_VAR and preparation variables 193 194 195 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 196 197 // firstprivate(s_arr) 198 199 // firstprivate(var) 200 201 202 #endif 203 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 204 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 205 // CHECK1-NEXT: entry: 206 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 207 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 208 // CHECK1-NEXT: ret void 209 // 210 // 211 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 212 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 213 // CHECK1-NEXT: entry: 214 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 215 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 216 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 217 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 218 // CHECK1-NEXT: ret void 219 // 220 // 221 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 222 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 223 // CHECK1-NEXT: entry: 224 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 225 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 226 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 227 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 228 // CHECK1-NEXT: ret void 229 // 230 // 231 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 232 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 233 // CHECK1-NEXT: entry: 234 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 235 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 236 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 237 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 238 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 239 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 240 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 241 // CHECK1-NEXT: ret void 242 // 243 // 244 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 245 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 246 // CHECK1-NEXT: entry: 247 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 248 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 249 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 250 // CHECK1-NEXT: ret void 251 // 252 // 253 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 254 // CHECK1-SAME: () #[[ATTR0]] { 255 // CHECK1-NEXT: entry: 256 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 257 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 258 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 259 // CHECK1-NEXT: ret void 260 // 261 // 262 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 263 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 264 // CHECK1-NEXT: entry: 265 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 266 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 267 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 268 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 269 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 270 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 271 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 272 // CHECK1-NEXT: ret void 273 // 274 // 275 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 276 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 277 // CHECK1-NEXT: entry: 278 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 279 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 280 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 281 // CHECK1: arraydestroy.body: 282 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 283 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 284 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 285 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 286 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 287 // CHECK1: arraydestroy.done1: 288 // CHECK1-NEXT: ret void 289 // 290 // 291 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 292 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 293 // CHECK1-NEXT: entry: 294 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 295 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 296 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 297 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 298 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 299 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 300 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 301 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 302 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 303 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 304 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 305 // CHECK1-NEXT: ret void 306 // 307 // 308 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 309 // CHECK1-SAME: () #[[ATTR0]] { 310 // CHECK1-NEXT: entry: 311 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 312 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 313 // CHECK1-NEXT: ret void 314 // 315 // 316 // CHECK1-LABEL: define {{[^@]+}}@main 317 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 318 // CHECK1-NEXT: entry: 319 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 320 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 321 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 322 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 323 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 324 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 325 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 326 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 327 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 328 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr @t_var, align 4 329 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 330 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 331 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 332 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 333 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 334 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 335 // CHECK1-NEXT: store ptr @vec, ptr [[TMP4]], align 8 336 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 337 // CHECK1-NEXT: store ptr @vec, ptr [[TMP5]], align 8 338 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 339 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 340 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 341 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP7]], align 8 342 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 343 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP8]], align 8 344 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 345 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 346 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 347 // CHECK1-NEXT: store ptr @s_arr, ptr [[TMP10]], align 8 348 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 349 // CHECK1-NEXT: store ptr @s_arr, ptr [[TMP11]], align 8 350 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 351 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 352 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 353 // CHECK1-NEXT: store ptr @var, ptr [[TMP13]], align 8 354 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 355 // CHECK1-NEXT: store ptr @var, ptr [[TMP14]], align 8 356 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 357 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 358 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 359 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP16]], align 8 360 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 361 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP17]], align 8 362 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 363 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 364 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 365 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 366 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 367 // CHECK1-NEXT: store i32 3, ptr [[TMP21]], align 4 368 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 369 // CHECK1-NEXT: store i32 5, ptr [[TMP22]], align 4 370 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 371 // CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8 372 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 373 // CHECK1-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8 374 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 375 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 8 376 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 377 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 8 378 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 379 // CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8 380 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 381 // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8 382 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 383 // CHECK1-NEXT: store i64 2, ptr [[TMP29]], align 8 384 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 385 // CHECK1-NEXT: store i64 0, ptr [[TMP30]], align 8 386 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 387 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 388 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 389 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 390 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 391 // CHECK1-NEXT: store i32 0, ptr [[TMP33]], align 4 392 // CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.region_id, ptr [[KERNEL_ARGS]]) 393 // CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 394 // CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 395 // CHECK1: omp_offload.failed: 396 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122(ptr @vec, i64 [[TMP1]], ptr @s_arr, ptr @var, i64 [[TMP3]]) #[[ATTR2]] 397 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 398 // CHECK1: omp_offload.cont: 399 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 400 // CHECK1-NEXT: ret i32 [[CALL]] 401 // 402 // 403 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 404 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 405 // CHECK1-NEXT: entry: 406 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 407 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 408 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 409 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 410 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 411 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 412 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 413 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 414 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 415 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 416 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 417 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 418 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 419 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 420 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 421 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 422 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 423 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 424 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 425 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 426 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 427 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]]) 428 // CHECK1-NEXT: ret void 429 // 430 // 431 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined 432 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 433 // CHECK1-NEXT: entry: 434 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 435 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 436 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 437 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 438 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 439 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 440 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 441 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 442 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 443 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 444 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 445 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 446 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 447 // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 448 // CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 449 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 450 // CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 451 // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 452 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 453 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 454 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 455 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 456 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 457 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 458 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 459 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 460 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 461 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 462 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 463 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 464 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 465 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 466 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 467 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 468 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 469 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) 470 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 471 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 472 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 473 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 474 // CHECK1: omp.arraycpy.body: 475 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 476 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 477 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 478 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 479 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 480 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 481 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 482 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 483 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 484 // CHECK1: omp.arraycpy.done3: 485 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 486 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 487 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 488 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 489 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 490 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 491 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 492 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 493 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 494 // CHECK1: cond.true: 495 // CHECK1-NEXT: br label [[COND_END:%.*]] 496 // CHECK1: cond.false: 497 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 498 // CHECK1-NEXT: br label [[COND_END]] 499 // CHECK1: cond.end: 500 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 501 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 502 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 503 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 504 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 505 // CHECK1: omp.inner.for.cond: 506 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 507 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 508 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 509 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 510 // CHECK1: omp.inner.for.cond.cleanup: 511 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 512 // CHECK1: omp.inner.for.body: 513 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 514 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 515 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 516 // CHECK1-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 517 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 518 // CHECK1-NEXT: store i32 [[TMP15]], ptr [[T_VAR_CASTED]], align 4 519 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 520 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 521 // CHECK1-NEXT: store i32 [[TMP17]], ptr [[SIVAR_CASTED]], align 4 522 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 523 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], ptr [[VEC1]], i64 [[TMP16]], ptr [[S_ARR2]], ptr [[VAR4]], i64 [[TMP18]]) 524 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 525 // CHECK1: omp.inner.for.inc: 526 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 527 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 528 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] 529 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 530 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 531 // CHECK1: omp.inner.for.end: 532 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 533 // CHECK1: omp.loop.exit: 534 // CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 535 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 536 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) 537 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 538 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 539 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 540 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 541 // CHECK1: arraydestroy.body: 542 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 543 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 544 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 545 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 546 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 547 // CHECK1: arraydestroy.done8: 548 // CHECK1-NEXT: ret void 549 // 550 // 551 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev 552 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 553 // CHECK1-NEXT: entry: 554 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 555 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 556 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 557 // CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 558 // CHECK1-NEXT: ret void 559 // 560 // 561 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 562 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 563 // CHECK1-NEXT: entry: 564 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 565 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 566 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 567 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 568 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 569 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 570 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 571 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 572 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 573 // CHECK1-NEXT: ret void 574 // 575 // 576 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev 577 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 578 // CHECK1-NEXT: entry: 579 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 580 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 581 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 582 // CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 583 // CHECK1-NEXT: ret void 584 // 585 // 586 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined.omp_outlined 587 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 588 // CHECK1-NEXT: entry: 589 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 590 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 591 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 592 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 593 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 594 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 595 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 596 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 597 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 598 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 599 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 600 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 601 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 602 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 603 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 604 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 605 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 606 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 607 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 608 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 609 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 610 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 611 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 612 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 613 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 614 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 615 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 616 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 617 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 618 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 619 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 620 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 621 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 622 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 623 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 624 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 625 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 626 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 627 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP4]] to i32 628 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 629 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 630 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 631 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 632 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) 633 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 634 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 635 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 636 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 637 // CHECK1: omp.arraycpy.body: 638 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 639 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 640 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 641 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 642 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 643 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 644 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 645 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 646 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 647 // CHECK1: omp.arraycpy.done4: 648 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 649 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP6]]) 650 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 651 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 652 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 653 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 654 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 655 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 656 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 657 // CHECK1: cond.true: 658 // CHECK1-NEXT: br label [[COND_END:%.*]] 659 // CHECK1: cond.false: 660 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 661 // CHECK1-NEXT: br label [[COND_END]] 662 // CHECK1: cond.end: 663 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] 664 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 665 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 666 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 667 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 668 // CHECK1: omp.inner.for.cond: 669 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 670 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 671 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 672 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 673 // CHECK1: omp.inner.for.cond.cleanup: 674 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 675 // CHECK1: omp.inner.for.body: 676 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 677 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 678 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 679 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 680 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 681 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 682 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 683 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] 684 // CHECK1-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 685 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 686 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 687 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] 688 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR5]], i64 4, i1 false) 689 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 690 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 691 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP18]], [[TMP17]] 692 // CHECK1-NEXT: store i32 [[ADD10]], ptr [[SIVAR_ADDR]], align 4 693 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 694 // CHECK1: omp.body.continue: 695 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 696 // CHECK1: omp.inner.for.inc: 697 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 698 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP19]], 1 699 // CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4 700 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 701 // CHECK1: omp.inner.for.end: 702 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 703 // CHECK1: omp.loop.exit: 704 // CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 705 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 706 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 707 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 708 // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 709 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 710 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 711 // CHECK1: arraydestroy.body: 712 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 713 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 714 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 715 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 716 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 717 // CHECK1: arraydestroy.done13: 718 // CHECK1-NEXT: ret void 719 // 720 // 721 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 722 // CHECK1-SAME: () #[[ATTR1]] comdat { 723 // CHECK1-NEXT: entry: 724 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 725 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 726 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 727 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 728 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 729 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 730 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 731 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 732 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 733 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 734 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 735 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 736 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 737 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 738 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 739 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 740 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 741 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 742 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 743 // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 744 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 745 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 746 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 747 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 748 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 749 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 750 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 751 // CHECK1-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 8 752 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 753 // CHECK1-NEXT: store ptr [[VEC]], ptr [[TMP5]], align 8 754 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 755 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 756 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 757 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP7]], align 8 758 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 759 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP8]], align 8 760 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 761 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 762 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 763 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[TMP10]], align 8 764 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 765 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[TMP11]], align 8 766 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 767 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 768 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 769 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 8 770 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 771 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 8 772 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 773 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 774 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 775 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 776 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 777 // CHECK1-NEXT: store i32 3, ptr [[TMP18]], align 4 778 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 779 // CHECK1-NEXT: store i32 4, ptr [[TMP19]], align 4 780 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 781 // CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 8 782 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 783 // CHECK1-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 8 784 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 785 // CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP22]], align 8 786 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 787 // CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP23]], align 8 788 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 789 // CHECK1-NEXT: store ptr null, ptr [[TMP24]], align 8 790 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 791 // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 792 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 793 // CHECK1-NEXT: store i64 2, ptr [[TMP26]], align 8 794 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 795 // CHECK1-NEXT: store i64 0, ptr [[TMP27]], align 8 796 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 797 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 798 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 799 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4 800 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 801 // CHECK1-NEXT: store i32 0, ptr [[TMP30]], align 4 802 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, ptr [[KERNEL_ARGS]]) 803 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 804 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 805 // CHECK1: omp_offload.failed: 806 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(ptr [[VEC]], i64 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]] 807 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 808 // CHECK1: omp_offload.cont: 809 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 810 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 811 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 812 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 813 // CHECK1: arraydestroy.body: 814 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 815 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 816 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 817 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 818 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 819 // CHECK1: arraydestroy.done2: 820 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 821 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 822 // CHECK1-NEXT: ret i32 [[TMP34]] 823 // 824 // 825 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev 826 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 827 // CHECK1-NEXT: entry: 828 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 829 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 830 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 831 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 832 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 833 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 834 // CHECK1-NEXT: store i32 0, ptr [[B]], align 4 835 // CHECK1-NEXT: ret void 836 // 837 // 838 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 839 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 840 // CHECK1-NEXT: entry: 841 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 842 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 843 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 844 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 845 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 846 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 847 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 848 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 849 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 850 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 851 // CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 852 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 853 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 854 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 855 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 856 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 857 // CHECK1-NEXT: ret void 858 // 859 // 860 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev 861 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 862 // CHECK1-NEXT: entry: 863 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 864 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 865 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 866 // CHECK1-NEXT: ret void 867 // 868 // 869 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 870 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 871 // CHECK1-NEXT: entry: 872 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 873 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 874 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 875 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 876 // CHECK1-NEXT: ret void 877 // 878 // 879 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 880 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 881 // CHECK1-NEXT: entry: 882 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 883 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 884 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 885 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 886 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 887 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 888 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 889 // CHECK1-NEXT: ret void 890 // 891 // 892 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 893 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 894 // CHECK1-NEXT: entry: 895 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 896 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 897 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 898 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 899 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 900 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 901 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 902 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 903 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 904 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 905 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 906 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 907 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 908 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 909 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 910 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 911 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 912 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 913 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) 914 // CHECK1-NEXT: ret void 915 // 916 // 917 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined 918 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 919 // CHECK1-NEXT: entry: 920 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 921 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 922 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 923 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 924 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 925 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 926 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 927 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 928 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 929 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 930 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 931 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 932 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 933 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 934 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 935 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 936 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 937 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 938 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 939 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 940 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 941 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 942 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 943 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 944 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 945 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 946 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 947 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 948 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 949 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 950 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 951 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 952 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 953 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 954 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 955 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) 956 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 957 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 958 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 959 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 960 // CHECK1: omp.arraycpy.body: 961 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 962 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 963 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 964 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 965 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 966 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 967 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 968 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 969 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 970 // CHECK1: omp.arraycpy.done4: 971 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 972 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 973 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) 974 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 975 // CHECK1-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8 976 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 977 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 978 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 979 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 980 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 981 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 982 // CHECK1: cond.true: 983 // CHECK1-NEXT: br label [[COND_END:%.*]] 984 // CHECK1: cond.false: 985 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 986 // CHECK1-NEXT: br label [[COND_END]] 987 // CHECK1: cond.end: 988 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 989 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 990 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 991 // CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 992 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 993 // CHECK1: omp.inner.for.cond: 994 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 995 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 996 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 997 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 998 // CHECK1: omp.inner.for.cond.cleanup: 999 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1000 // CHECK1: omp.inner.for.body: 1001 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1002 // CHECK1-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 1003 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1004 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 1005 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1006 // CHECK1-NEXT: store i32 [[TMP16]], ptr [[T_VAR_CASTED]], align 4 1007 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 1008 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP7]], align 8 1009 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined.omp_outlined, i64 [[TMP13]], i64 [[TMP15]], ptr [[VEC2]], i64 [[TMP17]], ptr [[S_ARR3]], ptr [[TMP18]]) 1010 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1011 // CHECK1: omp.inner.for.inc: 1012 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1013 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1014 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] 1015 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 1016 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1017 // CHECK1: omp.inner.for.end: 1018 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1019 // CHECK1: omp.loop.exit: 1020 // CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1021 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 1022 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) 1023 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1024 // CHECK1-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 1025 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 2 1026 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1027 // CHECK1: arraydestroy.body: 1028 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1029 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1030 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1031 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] 1032 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] 1033 // CHECK1: arraydestroy.done10: 1034 // CHECK1-NEXT: ret void 1035 // 1036 // 1037 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1038 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1039 // CHECK1-NEXT: entry: 1040 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1041 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 1042 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 1043 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1044 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 1045 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 1046 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1047 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 1048 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 1049 // CHECK1-NEXT: ret void 1050 // 1051 // 1052 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined.omp_outlined 1053 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1054 // CHECK1-NEXT: entry: 1055 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1056 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1057 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1058 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1059 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 1060 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1061 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 1062 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 1063 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1064 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1065 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1066 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1067 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1068 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1069 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1070 // CHECK1-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 1071 // CHECK1-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 1072 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1073 // CHECK1-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1074 // CHECK1-NEXT: [[AGG_TMP7:%.*]] = alloca [[STRUCT_ST]], align 4 1075 // CHECK1-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 1076 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1077 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1078 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1079 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1080 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1081 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 1082 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 1083 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 1084 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 1085 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 1086 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 1087 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 1088 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 1089 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1090 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1091 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1092 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 1093 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1094 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32 1095 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1096 // CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 1097 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1098 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1099 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false) 1100 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 1101 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 1102 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 1103 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1104 // CHECK1: omp.arraycpy.body: 1105 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1106 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1107 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1108 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 1109 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1110 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1111 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1112 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 1113 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]] 1114 // CHECK1: omp.arraycpy.done5: 1115 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 1116 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) 1117 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP7]]) 1118 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) #[[ATTR2]] 1119 // CHECK1-NEXT: store ptr [[VAR6]], ptr [[_TMP8]], align 8 1120 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1121 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1122 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1123 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1124 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 1125 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1126 // CHECK1: cond.true: 1127 // CHECK1-NEXT: br label [[COND_END:%.*]] 1128 // CHECK1: cond.false: 1129 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1130 // CHECK1-NEXT: br label [[COND_END]] 1131 // CHECK1: cond.end: 1132 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 1133 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1134 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1135 // CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 1136 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1137 // CHECK1: omp.inner.for.cond: 1138 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1139 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1140 // CHECK1-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 1141 // CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1142 // CHECK1: omp.inner.for.cond.cleanup: 1143 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1144 // CHECK1: omp.inner.for.body: 1145 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1146 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 1147 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1148 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1149 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1150 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 1151 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 1152 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] 1153 // CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 1154 // CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8 1155 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 1156 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 1157 // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] 1158 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false) 1159 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1160 // CHECK1: omp.body.continue: 1161 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1162 // CHECK1: omp.inner.for.inc: 1163 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1164 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 1165 // CHECK1-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4 1166 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1167 // CHECK1: omp.inner.for.end: 1168 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1169 // CHECK1: omp.loop.exit: 1170 // CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1171 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 1172 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 1173 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR2]] 1174 // CHECK1-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 1175 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 1176 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1177 // CHECK1: arraydestroy.body: 1178 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1179 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1180 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1181 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] 1182 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] 1183 // CHECK1: arraydestroy.done14: 1184 // CHECK1-NEXT: ret void 1185 // 1186 // 1187 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1188 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1189 // CHECK1-NEXT: entry: 1190 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1191 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1192 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1193 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1194 // CHECK1-NEXT: ret void 1195 // 1196 // 1197 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1198 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1199 // CHECK1-NEXT: entry: 1200 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1201 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1202 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1203 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1204 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1205 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1206 // CHECK1-NEXT: ret void 1207 // 1208 // 1209 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1210 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1211 // CHECK1-NEXT: entry: 1212 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1213 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1214 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1215 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1216 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1217 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1218 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1219 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1220 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1221 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1222 // CHECK1-NEXT: ret void 1223 // 1224 // 1225 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1226 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1227 // CHECK1-NEXT: entry: 1228 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1229 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 1230 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 1231 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1232 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 1233 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 1234 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1235 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1236 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 1237 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 1238 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 1239 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 1240 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1241 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1242 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1243 // CHECK1-NEXT: ret void 1244 // 1245 // 1246 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1247 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1248 // CHECK1-NEXT: entry: 1249 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1250 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1251 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1252 // CHECK1-NEXT: ret void 1253 // 1254 // 1255 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp 1256 // CHECK1-SAME: () #[[ATTR0]] { 1257 // CHECK1-NEXT: entry: 1258 // CHECK1-NEXT: call void @__cxx_global_var_init() 1259 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 1260 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 1261 // CHECK1-NEXT: ret void 1262 // 1263 // 1264 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 1265 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 1266 // CHECK3-NEXT: entry: 1267 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 1268 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 1269 // CHECK3-NEXT: ret void 1270 // 1271 // 1272 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1273 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1274 // CHECK3-NEXT: entry: 1275 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1276 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1277 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1278 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1279 // CHECK3-NEXT: ret void 1280 // 1281 // 1282 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1283 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1284 // CHECK3-NEXT: entry: 1285 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1286 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1287 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1288 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1289 // CHECK3-NEXT: ret void 1290 // 1291 // 1292 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1293 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1294 // CHECK3-NEXT: entry: 1295 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1296 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1297 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1298 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1299 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1300 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1301 // CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4 1302 // CHECK3-NEXT: ret void 1303 // 1304 // 1305 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1306 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1307 // CHECK3-NEXT: entry: 1308 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1309 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1310 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1311 // CHECK3-NEXT: ret void 1312 // 1313 // 1314 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1315 // CHECK3-SAME: () #[[ATTR0]] { 1316 // CHECK3-NEXT: entry: 1317 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 1318 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 1319 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 1320 // CHECK3-NEXT: ret void 1321 // 1322 // 1323 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1324 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1325 // CHECK3-NEXT: entry: 1326 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1327 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1328 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1329 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1330 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1331 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1332 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1333 // CHECK3-NEXT: ret void 1334 // 1335 // 1336 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1337 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1338 // CHECK3-NEXT: entry: 1339 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 1340 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 1341 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1342 // CHECK3: arraydestroy.body: 1343 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1344 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1345 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1346 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1347 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1348 // CHECK3: arraydestroy.done1: 1349 // CHECK3-NEXT: ret void 1350 // 1351 // 1352 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1353 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1354 // CHECK3-NEXT: entry: 1355 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1356 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1357 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1358 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1359 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1360 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1361 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1362 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1363 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1364 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1365 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 1366 // CHECK3-NEXT: ret void 1367 // 1368 // 1369 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1370 // CHECK3-SAME: () #[[ATTR0]] { 1371 // CHECK3-NEXT: entry: 1372 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1373 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1374 // CHECK3-NEXT: ret void 1375 // 1376 // 1377 // CHECK3-LABEL: define {{[^@]+}}@main 1378 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1379 // CHECK3-NEXT: entry: 1380 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1381 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1382 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1383 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 1384 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 1385 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 1386 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1387 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1388 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1389 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr @t_var, align 4 1390 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 1391 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1392 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 1393 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 1394 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 1395 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1396 // CHECK3-NEXT: store ptr @vec, ptr [[TMP4]], align 4 1397 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1398 // CHECK3-NEXT: store ptr @vec, ptr [[TMP5]], align 4 1399 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1400 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1401 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1402 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 4 1403 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1404 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 4 1405 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1406 // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 1407 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1408 // CHECK3-NEXT: store ptr @s_arr, ptr [[TMP10]], align 4 1409 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1410 // CHECK3-NEXT: store ptr @s_arr, ptr [[TMP11]], align 4 1411 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1412 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 1413 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1414 // CHECK3-NEXT: store ptr @var, ptr [[TMP13]], align 4 1415 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1416 // CHECK3-NEXT: store ptr @var, ptr [[TMP14]], align 4 1417 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1418 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 1419 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1420 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP16]], align 4 1421 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1422 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP17]], align 4 1423 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1424 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 1425 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1426 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1427 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1428 // CHECK3-NEXT: store i32 3, ptr [[TMP21]], align 4 1429 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1430 // CHECK3-NEXT: store i32 5, ptr [[TMP22]], align 4 1431 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1432 // CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4 1433 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1434 // CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4 1435 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1436 // CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 4 1437 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1438 // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 4 1439 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1440 // CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 4 1441 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1442 // CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 4 1443 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1444 // CHECK3-NEXT: store i64 2, ptr [[TMP29]], align 8 1445 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1446 // CHECK3-NEXT: store i64 0, ptr [[TMP30]], align 8 1447 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1448 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 1449 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1450 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 1451 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1452 // CHECK3-NEXT: store i32 0, ptr [[TMP33]], align 4 1453 // CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.region_id, ptr [[KERNEL_ARGS]]) 1454 // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 1455 // CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1456 // CHECK3: omp_offload.failed: 1457 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122(ptr @vec, i32 [[TMP1]], ptr @s_arr, ptr @var, i32 [[TMP3]]) #[[ATTR2]] 1458 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1459 // CHECK3: omp_offload.cont: 1460 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1461 // CHECK3-NEXT: ret i32 [[CALL]] 1462 // 1463 // 1464 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 1465 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 1466 // CHECK3-NEXT: entry: 1467 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1468 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1469 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1470 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1471 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1472 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1473 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1474 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1475 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1476 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1477 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1478 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 1479 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1480 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1481 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1482 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1483 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 1484 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1485 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 1486 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 1487 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 1488 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]]) 1489 // CHECK3-NEXT: ret void 1490 // 1491 // 1492 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined 1493 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 1494 // CHECK3-NEXT: entry: 1495 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1496 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1497 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1498 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1499 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1500 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1501 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1502 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1503 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1504 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1505 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1506 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1507 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1508 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 1509 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 1510 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1511 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1512 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 1513 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1514 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1515 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1516 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1517 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1518 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1519 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1520 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1521 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1522 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 1523 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1524 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1525 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1526 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1527 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1528 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1529 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1530 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) 1531 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1532 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1533 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 1534 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1535 // CHECK3: omp.arraycpy.body: 1536 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1537 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1538 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1539 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 1540 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1541 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1542 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1543 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 1544 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 1545 // CHECK3: omp.arraycpy.done3: 1546 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 1547 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 1548 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 1549 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1550 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 1551 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1552 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1553 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 1554 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1555 // CHECK3: cond.true: 1556 // CHECK3-NEXT: br label [[COND_END:%.*]] 1557 // CHECK3: cond.false: 1558 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1559 // CHECK3-NEXT: br label [[COND_END]] 1560 // CHECK3: cond.end: 1561 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1562 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1563 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1564 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 1565 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1566 // CHECK3: omp.inner.for.cond: 1567 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1568 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1569 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1570 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1571 // CHECK3: omp.inner.for.cond.cleanup: 1572 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1573 // CHECK3: omp.inner.for.body: 1574 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1575 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1576 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1577 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[T_VAR_CASTED]], align 4 1578 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1579 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 1580 // CHECK3-NEXT: store i32 [[TMP15]], ptr [[SIVAR_CASTED]], align 4 1581 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 1582 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined.omp_outlined, i32 [[TMP11]], i32 [[TMP12]], ptr [[VEC1]], i32 [[TMP14]], ptr [[S_ARR2]], ptr [[VAR4]], i32 [[TMP16]]) 1583 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1584 // CHECK3: omp.inner.for.inc: 1585 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1586 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1587 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] 1588 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 1589 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1590 // CHECK3: omp.inner.for.end: 1591 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1592 // CHECK3: omp.loop.exit: 1593 // CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1594 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 1595 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) 1596 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 1597 // CHECK3-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1598 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 2 1599 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1600 // CHECK3: arraydestroy.body: 1601 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP21]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1602 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1603 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1604 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 1605 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 1606 // CHECK3: arraydestroy.done8: 1607 // CHECK3-NEXT: ret void 1608 // 1609 // 1610 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev 1611 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1612 // CHECK3-NEXT: entry: 1613 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1614 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1615 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1616 // CHECK3-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 1617 // CHECK3-NEXT: ret void 1618 // 1619 // 1620 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 1621 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1622 // CHECK3-NEXT: entry: 1623 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1624 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1625 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1626 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1627 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1628 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1629 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1630 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1631 // CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 1632 // CHECK3-NEXT: ret void 1633 // 1634 // 1635 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev 1636 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1637 // CHECK3-NEXT: entry: 1638 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1639 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1640 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1641 // CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 1642 // CHECK3-NEXT: ret void 1643 // 1644 // 1645 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined.omp_outlined 1646 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 1647 // CHECK3-NEXT: entry: 1648 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1649 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1650 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 1651 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 1652 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1653 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1654 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1655 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1656 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1657 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1658 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1659 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1660 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1661 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1662 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1663 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 1664 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 1665 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1666 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1667 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 1668 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1669 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1670 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1671 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1672 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1673 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1674 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1675 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1676 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1677 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 1678 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1679 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1680 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1681 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1682 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1683 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1684 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1685 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4 1686 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 1687 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1688 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1689 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) 1690 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1691 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1692 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 1693 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1694 // CHECK3: omp.arraycpy.body: 1695 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1696 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1697 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1698 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 1699 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1700 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1701 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1702 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 1703 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 1704 // CHECK3: omp.arraycpy.done3: 1705 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 1706 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 1707 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 1708 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1709 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 1710 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1711 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1712 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 1713 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1714 // CHECK3: cond.true: 1715 // CHECK3-NEXT: br label [[COND_END:%.*]] 1716 // CHECK3: cond.false: 1717 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1718 // CHECK3-NEXT: br label [[COND_END]] 1719 // CHECK3: cond.end: 1720 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] 1721 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1722 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1723 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 1724 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1725 // CHECK3: omp.inner.for.cond: 1726 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1727 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1728 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 1729 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1730 // CHECK3: omp.inner.for.cond.cleanup: 1731 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1732 // CHECK3: omp.inner.for.body: 1733 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1734 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 1735 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1736 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1737 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1738 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 1739 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP15]] 1740 // CHECK3-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 1741 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 1742 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] 1743 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false) 1744 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 1745 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 1746 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP18]], [[TMP17]] 1747 // CHECK3-NEXT: store i32 [[ADD8]], ptr [[SIVAR_ADDR]], align 4 1748 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1749 // CHECK3: omp.body.continue: 1750 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1751 // CHECK3: omp.inner.for.inc: 1752 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1753 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1 1754 // CHECK3-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4 1755 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1756 // CHECK3: omp.inner.for.end: 1757 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1758 // CHECK3: omp.loop.exit: 1759 // CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1760 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 1761 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 1762 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 1763 // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1764 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 1765 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1766 // CHECK3: arraydestroy.body: 1767 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1768 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1769 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1770 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 1771 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 1772 // CHECK3: arraydestroy.done11: 1773 // CHECK3-NEXT: ret void 1774 // 1775 // 1776 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1777 // CHECK3-SAME: () #[[ATTR1]] comdat { 1778 // CHECK3-NEXT: entry: 1779 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1780 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1781 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1782 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1783 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1784 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 1785 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1786 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1787 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 1788 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 1789 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 1790 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1791 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1792 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1793 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 1794 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 1795 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 1796 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 1797 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1798 // CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 1799 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 1800 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 1801 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 1802 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 1803 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1804 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 1805 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1806 // CHECK3-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 4 1807 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1808 // CHECK3-NEXT: store ptr [[VEC]], ptr [[TMP5]], align 4 1809 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1810 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1811 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1812 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP7]], align 4 1813 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1814 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP8]], align 4 1815 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1816 // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 1817 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1818 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[TMP10]], align 4 1819 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1820 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[TMP11]], align 4 1821 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1822 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 1823 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1824 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 4 1825 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1826 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 4 1827 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1828 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 1829 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1830 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1831 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1832 // CHECK3-NEXT: store i32 3, ptr [[TMP18]], align 4 1833 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1834 // CHECK3-NEXT: store i32 4, ptr [[TMP19]], align 4 1835 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1836 // CHECK3-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 4 1837 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1838 // CHECK3-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 4 1839 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1840 // CHECK3-NEXT: store ptr @.offload_sizes.3, ptr [[TMP22]], align 4 1841 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1842 // CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP23]], align 4 1843 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1844 // CHECK3-NEXT: store ptr null, ptr [[TMP24]], align 4 1845 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1846 // CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4 1847 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1848 // CHECK3-NEXT: store i64 2, ptr [[TMP26]], align 8 1849 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1850 // CHECK3-NEXT: store i64 0, ptr [[TMP27]], align 8 1851 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1852 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 1853 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1854 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4 1855 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1856 // CHECK3-NEXT: store i32 0, ptr [[TMP30]], align 4 1857 // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, ptr [[KERNEL_ARGS]]) 1858 // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1859 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1860 // CHECK3: omp_offload.failed: 1861 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(ptr [[VEC]], i32 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]] 1862 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1863 // CHECK3: omp_offload.cont: 1864 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1865 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1866 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1867 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1868 // CHECK3: arraydestroy.body: 1869 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1870 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1871 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1872 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1873 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1874 // CHECK3: arraydestroy.done2: 1875 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1876 // CHECK3-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 1877 // CHECK3-NEXT: ret i32 [[TMP34]] 1878 // 1879 // 1880 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev 1881 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1882 // CHECK3-NEXT: entry: 1883 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1884 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1885 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1886 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 1887 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 1888 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 1889 // CHECK3-NEXT: store i32 0, ptr [[B]], align 4 1890 // CHECK3-NEXT: ret void 1891 // 1892 // 1893 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 1894 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1895 // CHECK3-NEXT: entry: 1896 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1897 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1898 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1899 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1900 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1901 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1902 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1903 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1904 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1905 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 1906 // CHECK3-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 1907 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 1908 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1909 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 1910 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 1911 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 1912 // CHECK3-NEXT: ret void 1913 // 1914 // 1915 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev 1916 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1917 // CHECK3-NEXT: entry: 1918 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1919 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1920 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1921 // CHECK3-NEXT: ret void 1922 // 1923 // 1924 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1925 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1926 // CHECK3-NEXT: entry: 1927 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1928 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1929 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1930 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1931 // CHECK3-NEXT: ret void 1932 // 1933 // 1934 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1935 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1936 // CHECK3-NEXT: entry: 1937 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1938 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1939 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1940 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1941 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1942 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1943 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1944 // CHECK3-NEXT: ret void 1945 // 1946 // 1947 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 1948 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1949 // CHECK3-NEXT: entry: 1950 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1951 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1952 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1953 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1954 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1955 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1956 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1957 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1958 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1959 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1960 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1961 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1962 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1963 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 1964 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1965 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 1966 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1967 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 1968 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) 1969 // CHECK3-NEXT: ret void 1970 // 1971 // 1972 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined 1973 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1974 // CHECK3-NEXT: entry: 1975 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1976 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1977 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1978 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1979 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1980 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1981 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1982 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1983 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1984 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1985 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1986 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1987 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1988 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 1989 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 1990 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1991 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1992 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1993 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 1994 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1995 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1996 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1997 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1998 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1999 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 2000 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 2001 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 2002 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 2003 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 2004 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 2005 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 2006 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 2007 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 2008 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2009 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2010 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) 2011 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 2012 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 2013 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 2014 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2015 // CHECK3: omp.arraycpy.body: 2016 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2017 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2018 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2019 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 2020 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 2021 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2022 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2023 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 2024 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 2025 // CHECK3: omp.arraycpy.done4: 2026 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 2027 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 2028 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) 2029 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 2030 // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 2031 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2032 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 2033 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2034 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2035 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 2036 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2037 // CHECK3: cond.true: 2038 // CHECK3-NEXT: br label [[COND_END:%.*]] 2039 // CHECK3: cond.false: 2040 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2041 // CHECK3-NEXT: br label [[COND_END]] 2042 // CHECK3: cond.end: 2043 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 2044 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2045 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2046 // CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 2047 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2048 // CHECK3: omp.inner.for.cond: 2049 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2050 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2051 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 2052 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2053 // CHECK3: omp.inner.for.cond.cleanup: 2054 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2055 // CHECK3: omp.inner.for.body: 2056 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2057 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2058 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 2059 // CHECK3-NEXT: store i32 [[TMP14]], ptr [[T_VAR_CASTED]], align 4 2060 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 2061 // CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 4 2062 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined.omp_outlined, i32 [[TMP12]], i32 [[TMP13]], ptr [[VEC2]], i32 [[TMP15]], ptr [[S_ARR3]], ptr [[TMP16]]) 2063 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2064 // CHECK3: omp.inner.for.inc: 2065 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2066 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2067 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] 2068 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 2069 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2070 // CHECK3: omp.inner.for.end: 2071 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2072 // CHECK3: omp.loop.exit: 2073 // CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2074 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 2075 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) 2076 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 2077 // CHECK3-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 2078 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 2079 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2080 // CHECK3: arraydestroy.body: 2081 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP21]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2082 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2083 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2084 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] 2085 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] 2086 // CHECK3: arraydestroy.done10: 2087 // CHECK3-NEXT: ret void 2088 // 2089 // 2090 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 2091 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2092 // CHECK3-NEXT: entry: 2093 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2094 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 2095 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 2096 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2097 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 2098 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 2099 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2100 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 2101 // CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 2102 // CHECK3-NEXT: ret void 2103 // 2104 // 2105 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined.omp_outlined 2106 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 2107 // CHECK3-NEXT: entry: 2108 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2109 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2110 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 2111 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 2112 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 2113 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2114 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 2115 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 2116 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 2117 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2118 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2119 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2120 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2121 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2122 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2123 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 2124 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 2125 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2126 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2127 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 2128 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 2129 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2130 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2131 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2132 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 2133 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 2134 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 2135 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 2136 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 2137 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 2138 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 2139 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 2140 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 2141 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 2142 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2143 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2144 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 2145 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 2146 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4 2147 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 2148 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2149 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2150 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) 2151 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 2152 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 2153 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 2154 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2155 // CHECK3: omp.arraycpy.body: 2156 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2157 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2158 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2159 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 2160 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 2161 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2162 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2163 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 2164 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 2165 // CHECK3: omp.arraycpy.done4: 2166 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 2167 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 2168 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP6]]) 2169 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 2170 // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 2171 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2172 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 2173 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2174 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2175 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 2176 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2177 // CHECK3: cond.true: 2178 // CHECK3-NEXT: br label [[COND_END:%.*]] 2179 // CHECK3: cond.false: 2180 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2181 // CHECK3-NEXT: br label [[COND_END]] 2182 // CHECK3: cond.end: 2183 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 2184 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2185 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2186 // CHECK3-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 2187 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2188 // CHECK3: omp.inner.for.cond: 2189 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2190 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2191 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 2192 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2193 // CHECK3: omp.inner.for.cond.cleanup: 2194 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2195 // CHECK3: omp.inner.for.body: 2196 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2197 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 2198 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2199 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 2200 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 2201 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 2202 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]] 2203 // CHECK3-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 2204 // CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4 2205 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 2206 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] 2207 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false) 2208 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2209 // CHECK3: omp.body.continue: 2210 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2211 // CHECK3: omp.inner.for.inc: 2212 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2213 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 2214 // CHECK3-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4 2215 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2216 // CHECK3: omp.inner.for.end: 2217 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2218 // CHECK3: omp.loop.exit: 2219 // CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2220 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 2221 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 2222 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 2223 // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 2224 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 2225 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2226 // CHECK3: arraydestroy.body: 2227 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2228 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2229 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2230 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 2231 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 2232 // CHECK3: arraydestroy.done12: 2233 // CHECK3-NEXT: ret void 2234 // 2235 // 2236 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2237 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2238 // CHECK3-NEXT: entry: 2239 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2240 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2241 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2242 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2243 // CHECK3-NEXT: ret void 2244 // 2245 // 2246 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2247 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2248 // CHECK3-NEXT: entry: 2249 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2250 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2251 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2252 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2253 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2254 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 2255 // CHECK3-NEXT: ret void 2256 // 2257 // 2258 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2259 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2260 // CHECK3-NEXT: entry: 2261 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2262 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2263 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2264 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2265 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2266 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2267 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2268 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2269 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2270 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 2271 // CHECK3-NEXT: ret void 2272 // 2273 // 2274 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 2275 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2276 // CHECK3-NEXT: entry: 2277 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2278 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 2279 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 2280 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2281 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 2282 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 2283 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2284 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2285 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 2286 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 2287 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 2288 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 2289 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 2290 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 2291 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 2292 // CHECK3-NEXT: ret void 2293 // 2294 // 2295 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2296 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2297 // CHECK3-NEXT: entry: 2298 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2299 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2300 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2301 // CHECK3-NEXT: ret void 2302 // 2303 // 2304 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp 2305 // CHECK3-SAME: () #[[ATTR0]] { 2306 // CHECK3-NEXT: entry: 2307 // CHECK3-NEXT: call void @__cxx_global_var_init() 2308 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 2309 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 2310 // CHECK3-NEXT: ret void 2311 // 2312 // 2313 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 2314 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 2315 // CHECK5-NEXT: entry: 2316 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 2317 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 2318 // CHECK5-NEXT: ret void 2319 // 2320 // 2321 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2322 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 2323 // CHECK5-NEXT: entry: 2324 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2325 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2326 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2327 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2328 // CHECK5-NEXT: ret void 2329 // 2330 // 2331 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2332 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2333 // CHECK5-NEXT: entry: 2334 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2335 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2336 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2337 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2338 // CHECK5-NEXT: ret void 2339 // 2340 // 2341 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2342 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2343 // CHECK5-NEXT: entry: 2344 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2345 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2346 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2347 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2348 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2349 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2350 // CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4 2351 // CHECK5-NEXT: ret void 2352 // 2353 // 2354 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2355 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2356 // CHECK5-NEXT: entry: 2357 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2358 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2359 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2360 // CHECK5-NEXT: ret void 2361 // 2362 // 2363 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2364 // CHECK5-SAME: () #[[ATTR0]] { 2365 // CHECK5-NEXT: entry: 2366 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 2367 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 2368 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 2369 // CHECK5-NEXT: ret void 2370 // 2371 // 2372 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2373 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2374 // CHECK5-NEXT: entry: 2375 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2376 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2377 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2378 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2379 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2380 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2381 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2382 // CHECK5-NEXT: ret void 2383 // 2384 // 2385 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2386 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2387 // CHECK5-NEXT: entry: 2388 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2389 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2390 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2391 // CHECK5: arraydestroy.body: 2392 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2393 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2394 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2395 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 2396 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2397 // CHECK5: arraydestroy.done1: 2398 // CHECK5-NEXT: ret void 2399 // 2400 // 2401 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2402 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 2403 // CHECK5-NEXT: entry: 2404 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2405 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2406 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2407 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2408 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2409 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2410 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2411 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2412 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2413 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2414 // CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4 2415 // CHECK5-NEXT: ret void 2416 // 2417 // 2418 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2419 // CHECK5-SAME: () #[[ATTR0]] { 2420 // CHECK5-NEXT: entry: 2421 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2422 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 2423 // CHECK5-NEXT: ret void 2424 // 2425 // 2426 // CHECK5-LABEL: define {{[^@]+}}@main 2427 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 2428 // CHECK5-NEXT: entry: 2429 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2430 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2431 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 2432 // CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2433 // CHECK5-NEXT: ret i32 0 2434 // 2435 // 2436 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 2437 // CHECK5-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 2438 // CHECK5-NEXT: entry: 2439 // CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 2440 // CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 2441 // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2442 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 2443 // CHECK5-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 2444 // CHECK5-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 2445 // CHECK5-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 2446 // CHECK5-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 2447 // CHECK5-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 2448 // CHECK5-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 2449 // CHECK5-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 2450 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 4 2451 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4 2452 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8 2453 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 2454 // CHECK5-NEXT: [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 4 2455 // CHECK5-NEXT: store i32 [[TMP3]], ptr [[G1_CASTED]], align 4 2456 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 8 2457 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 2458 // CHECK5-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 2459 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 2460 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) 2461 // CHECK5-NEXT: ret void 2462 // 2463 // 2464 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined 2465 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 2466 // CHECK5-NEXT: entry: 2467 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2468 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2469 // CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 2470 // CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 2471 // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2472 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 2473 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2474 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2475 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2476 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2477 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2478 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2479 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2480 // CHECK5-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 2481 // CHECK5-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 2482 // CHECK5-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 2483 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2484 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2485 // CHECK5-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 2486 // CHECK5-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 2487 // CHECK5-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 2488 // CHECK5-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 2489 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 2490 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 2491 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2492 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2493 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2494 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2495 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2496 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2497 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 2498 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2499 // CHECK5: cond.true: 2500 // CHECK5-NEXT: br label [[COND_END:%.*]] 2501 // CHECK5: cond.false: 2502 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2503 // CHECK5-NEXT: br label [[COND_END]] 2504 // CHECK5: cond.end: 2505 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2506 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2507 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2508 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2509 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2510 // CHECK5: omp.inner.for.cond: 2511 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2512 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2513 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2514 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2515 // CHECK5: omp.inner.for.body: 2516 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2517 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 2518 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2519 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 2520 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[G_ADDR]], align 4 2521 // CHECK5-NEXT: store i32 [[TMP11]], ptr [[G_CASTED]], align 4 2522 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[G_CASTED]], align 8 2523 // CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8 2524 // CHECK5-NEXT: [[TMP14:%.*]] = load volatile i32, ptr [[TMP13]], align 4 2525 // CHECK5-NEXT: store i32 [[TMP14]], ptr [[G1_CASTED]], align 4 2526 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[G1_CASTED]], align 8 2527 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 2528 // CHECK5-NEXT: store i32 [[TMP16]], ptr [[SIVAR_CASTED]], align 4 2529 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 2530 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) 2531 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2532 // CHECK5: omp.inner.for.inc: 2533 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2534 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2535 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 2536 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 2537 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] 2538 // CHECK5: omp.inner.for.end: 2539 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2540 // CHECK5: omp.loop.exit: 2541 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2542 // CHECK5-NEXT: ret void 2543 // 2544 // 2545 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined.omp_outlined 2546 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 2547 // CHECK5-NEXT: entry: 2548 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2549 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2550 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 2551 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 2552 // CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 2553 // CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 2554 // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2555 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 2556 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2557 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2558 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2559 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2560 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2561 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2562 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2563 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 2564 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2565 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2566 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2567 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2568 // CHECK5-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 2569 // CHECK5-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 2570 // CHECK5-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 2571 // CHECK5-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 2572 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2573 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2574 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2575 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 2576 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2577 // CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 2578 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 2579 // CHECK5-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 2580 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2581 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2582 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2583 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 2584 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2585 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2586 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 2587 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2588 // CHECK5: cond.true: 2589 // CHECK5-NEXT: br label [[COND_END:%.*]] 2590 // CHECK5: cond.false: 2591 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2592 // CHECK5-NEXT: br label [[COND_END]] 2593 // CHECK5: cond.end: 2594 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2595 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2596 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2597 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 2598 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2599 // CHECK5: omp.inner.for.cond: 2600 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2601 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2602 // CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2603 // CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2604 // CHECK5: omp.inner.for.body: 2605 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2606 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 2607 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2608 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 2609 // CHECK5-NEXT: store i32 1, ptr [[G_ADDR]], align 4 2610 // CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP]], align 8 2611 // CHECK5-NEXT: store volatile i32 1, ptr [[TMP10]], align 4 2612 // CHECK5-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 2613 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 2614 // CHECK5-NEXT: store ptr [[G_ADDR]], ptr [[TMP11]], align 8 2615 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 2616 // CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8 2617 // CHECK5-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 2618 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 2619 // CHECK5-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP14]], align 8 2620 // CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 2621 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2622 // CHECK5: omp.body.continue: 2623 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2624 // CHECK5: omp.inner.for.inc: 2625 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2626 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 2627 // CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 2628 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] 2629 // CHECK5: omp.inner.for.end: 2630 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2631 // CHECK5: omp.loop.exit: 2632 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 2633 // CHECK5-NEXT: ret void 2634 // 2635 // 2636 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp 2637 // CHECK5-SAME: () #[[ATTR0]] { 2638 // CHECK5-NEXT: entry: 2639 // CHECK5-NEXT: call void @__cxx_global_var_init() 2640 // CHECK5-NEXT: call void @__cxx_global_var_init.1() 2641 // CHECK5-NEXT: call void @__cxx_global_var_init.2() 2642 // CHECK5-NEXT: ret void 2643 // 2644 // 2645 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 2646 // CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { 2647 // CHECK13-NEXT: entry: 2648 // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 2649 // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 2650 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 2651 // CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 2652 // CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 2653 // CHECK13-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2654 // CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 2655 // CHECK13-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 2656 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 2657 // CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 2658 // CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 2659 // CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 2660 // CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 2661 // CHECK13-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 2662 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 2663 // CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 2664 // CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 2665 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 2666 // CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 2667 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 2668 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 2669 // CHECK13-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 2670 // CHECK13-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 2671 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]]) 2672 // CHECK13-NEXT: ret void 2673 // 2674 // 2675 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined 2676 // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { 2677 // CHECK13-NEXT: entry: 2678 // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2679 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2680 // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 2681 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 2682 // CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 2683 // CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 2684 // CHECK13-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2685 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2686 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 2687 // CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2688 // CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2689 // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2690 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2691 // CHECK13-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 2692 // CHECK13-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 2693 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2694 // CHECK13-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2695 // CHECK13-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 2696 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 2697 // CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 2698 // CHECK13-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 2699 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2700 // CHECK13-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2701 // CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 2702 // CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 2703 // CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 2704 // CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 2705 // CHECK13-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 2706 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 2707 // CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 2708 // CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 2709 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 2710 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 2711 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2712 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2713 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) 2714 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 2715 // CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 2716 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 2717 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2718 // CHECK13: omp.arraycpy.body: 2719 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2720 // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2721 // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2722 // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 2723 // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3:[0-9]+]] 2724 // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2725 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2726 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 2727 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 2728 // CHECK13: omp.arraycpy.done3: 2729 // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 2730 // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 2731 // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR3]] 2732 // CHECK13-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2733 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 2734 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2735 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2736 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 2737 // CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2738 // CHECK13: cond.true: 2739 // CHECK13-NEXT: br label [[COND_END:%.*]] 2740 // CHECK13: cond.false: 2741 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2742 // CHECK13-NEXT: br label [[COND_END]] 2743 // CHECK13: cond.end: 2744 // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2745 // CHECK13-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2746 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2747 // CHECK13-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 2748 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2749 // CHECK13: omp.inner.for.cond: 2750 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2751 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2752 // CHECK13-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2753 // CHECK13-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2754 // CHECK13: omp.inner.for.cond.cleanup: 2755 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2756 // CHECK13: omp.inner.for.body: 2757 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2758 // CHECK13-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 2759 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2760 // CHECK13-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 2761 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 2762 // CHECK13-NEXT: store i32 [[TMP15]], ptr [[T_VAR_CASTED]], align 4 2763 // CHECK13-NEXT: [[TMP16:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 2764 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 2765 // CHECK13-NEXT: store i32 [[TMP17]], ptr [[SIVAR_CASTED]], align 4 2766 // CHECK13-NEXT: [[TMP18:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 2767 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], ptr [[VEC1]], i64 [[TMP16]], ptr [[S_ARR2]], ptr [[VAR4]], i64 [[TMP18]]) 2768 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2769 // CHECK13: omp.inner.for.inc: 2770 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2771 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2772 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] 2773 // CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 2774 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] 2775 // CHECK13: omp.inner.for.end: 2776 // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2777 // CHECK13: omp.loop.exit: 2778 // CHECK13-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2779 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 2780 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) 2781 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR3]] 2782 // CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 2783 // CHECK13-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 2784 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2785 // CHECK13: arraydestroy.body: 2786 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2787 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2788 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 2789 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 2790 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 2791 // CHECK13: arraydestroy.done8: 2792 // CHECK13-NEXT: ret void 2793 // 2794 // 2795 // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC1Ev 2796 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat { 2797 // CHECK13-NEXT: entry: 2798 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2799 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2800 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2801 // CHECK13-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 2802 // CHECK13-NEXT: ret void 2803 // 2804 // 2805 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 2806 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat { 2807 // CHECK13-NEXT: entry: 2808 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2809 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 2810 // CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 2811 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2812 // CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 2813 // CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 2814 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2815 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 2816 // CHECK13-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 2817 // CHECK13-NEXT: ret void 2818 // 2819 // 2820 // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD1Ev 2821 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 2822 // CHECK13-NEXT: entry: 2823 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2824 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2825 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2826 // CHECK13-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] 2827 // CHECK13-NEXT: ret void 2828 // 2829 // 2830 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined.omp_outlined 2831 // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { 2832 // CHECK13-NEXT: entry: 2833 // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2834 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2835 // CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 2836 // CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 2837 // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 2838 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 2839 // CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 2840 // CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 2841 // CHECK13-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2842 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2843 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 2844 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2845 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2846 // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2847 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2848 // CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 2849 // CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 2850 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2851 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2852 // CHECK13-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 2853 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 2854 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2855 // CHECK13-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2856 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2857 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2858 // CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 2859 // CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 2860 // CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 2861 // CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 2862 // CHECK13-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 2863 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 2864 // CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 2865 // CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 2866 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2867 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2868 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 2869 // CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 2870 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 2871 // CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP4]] to i32 2872 // CHECK13-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 2873 // CHECK13-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 2874 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2875 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2876 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) 2877 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 2878 // CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 2879 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 2880 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2881 // CHECK13: omp.arraycpy.body: 2882 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2883 // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2884 // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2885 // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 2886 // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] 2887 // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2888 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2889 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 2890 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 2891 // CHECK13: omp.arraycpy.done4: 2892 // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 2893 // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP6]]) 2894 // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] 2895 // CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2896 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 2897 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2898 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2899 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 2900 // CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2901 // CHECK13: cond.true: 2902 // CHECK13-NEXT: br label [[COND_END:%.*]] 2903 // CHECK13: cond.false: 2904 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2905 // CHECK13-NEXT: br label [[COND_END]] 2906 // CHECK13: cond.end: 2907 // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] 2908 // CHECK13-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2909 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2910 // CHECK13-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 2911 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2912 // CHECK13: omp.inner.for.cond: 2913 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2914 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2915 // CHECK13-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 2916 // CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2917 // CHECK13: omp.inner.for.cond.cleanup: 2918 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2919 // CHECK13: omp.inner.for.body: 2920 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2921 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 2922 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2923 // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 2924 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 2925 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 2926 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 2927 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] 2928 // CHECK13-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 2929 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 2930 // CHECK13-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 2931 // CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] 2932 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR5]], i64 4, i1 false) 2933 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 2934 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 2935 // CHECK13-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP18]], [[TMP17]] 2936 // CHECK13-NEXT: store i32 [[ADD10]], ptr [[SIVAR_ADDR]], align 4 2937 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2938 // CHECK13: omp.body.continue: 2939 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2940 // CHECK13: omp.inner.for.inc: 2941 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2942 // CHECK13-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP19]], 1 2943 // CHECK13-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4 2944 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] 2945 // CHECK13: omp.inner.for.end: 2946 // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2947 // CHECK13: omp.loop.exit: 2948 // CHECK13-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2949 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 2950 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 2951 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] 2952 // CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 2953 // CHECK13-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 2954 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2955 // CHECK13: arraydestroy.body: 2956 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2957 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2958 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 2959 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 2960 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 2961 // CHECK13: arraydestroy.done13: 2962 // CHECK13-NEXT: ret void 2963 // 2964 // 2965 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2966 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 2967 // CHECK13-NEXT: entry: 2968 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2969 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2970 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2971 // CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] 2972 // CHECK13-NEXT: ret void 2973 // 2974 // 2975 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 2976 // CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { 2977 // CHECK13-NEXT: entry: 2978 // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 2979 // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 2980 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 2981 // CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 2982 // CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 2983 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 2984 // CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 2985 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 2986 // CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 2987 // CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 2988 // CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 2989 // CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 2990 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 2991 // CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 2992 // CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 2993 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 2994 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 2995 // CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 2996 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 2997 // CHECK13-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 2998 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) 2999 // CHECK13-NEXT: ret void 3000 // 3001 // 3002 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined 3003 // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { 3004 // CHECK13-NEXT: entry: 3005 // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3006 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3007 // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 3008 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 3009 // CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 3010 // CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 3011 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 3012 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3013 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3014 // CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 3015 // CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 3016 // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3017 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3018 // CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 3019 // CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 3020 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 3021 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3022 // CHECK13-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 3023 // CHECK13-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 3024 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 3025 // CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 3026 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3027 // CHECK13-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3028 // CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 3029 // CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 3030 // CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 3031 // CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 3032 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 3033 // CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 3034 // CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 3035 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 3036 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 3037 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 3038 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3039 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3040 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) 3041 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 3042 // CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 3043 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 3044 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3045 // CHECK13: omp.arraycpy.body: 3046 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3047 // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3048 // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 3049 // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 3050 // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] 3051 // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3052 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3053 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 3054 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 3055 // CHECK13: omp.arraycpy.done4: 3056 // CHECK13-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 3057 // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 3058 // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) 3059 // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] 3060 // CHECK13-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8 3061 // CHECK13-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3062 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 3063 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3064 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3065 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 3066 // CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3067 // CHECK13: cond.true: 3068 // CHECK13-NEXT: br label [[COND_END:%.*]] 3069 // CHECK13: cond.false: 3070 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3071 // CHECK13-NEXT: br label [[COND_END]] 3072 // CHECK13: cond.end: 3073 // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 3074 // CHECK13-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 3075 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 3076 // CHECK13-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 3077 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3078 // CHECK13: omp.inner.for.cond: 3079 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3080 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3081 // CHECK13-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 3082 // CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3083 // CHECK13: omp.inner.for.cond.cleanup: 3084 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3085 // CHECK13: omp.inner.for.body: 3086 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 3087 // CHECK13-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 3088 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3089 // CHECK13-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 3090 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 3091 // CHECK13-NEXT: store i32 [[TMP16]], ptr [[T_VAR_CASTED]], align 4 3092 // CHECK13-NEXT: [[TMP17:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 3093 // CHECK13-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP7]], align 8 3094 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined.omp_outlined, i64 [[TMP13]], i64 [[TMP15]], ptr [[VEC2]], i64 [[TMP17]], ptr [[S_ARR3]], ptr [[TMP18]]) 3095 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3096 // CHECK13: omp.inner.for.inc: 3097 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3098 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 3099 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] 3100 // CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 3101 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] 3102 // CHECK13: omp.inner.for.end: 3103 // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3104 // CHECK13: omp.loop.exit: 3105 // CHECK13-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3106 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 3107 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) 3108 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] 3109 // CHECK13-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 3110 // CHECK13-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 2 3111 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3112 // CHECK13: arraydestroy.body: 3113 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3114 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3115 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 3116 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] 3117 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] 3118 // CHECK13: arraydestroy.done10: 3119 // CHECK13-NEXT: ret void 3120 // 3121 // 3122 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 3123 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat { 3124 // CHECK13-NEXT: entry: 3125 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3126 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 3127 // CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 3128 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3129 // CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 3130 // CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 3131 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3132 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 3133 // CHECK13-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 3134 // CHECK13-NEXT: ret void 3135 // 3136 // 3137 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined.omp_outlined 3138 // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { 3139 // CHECK13-NEXT: entry: 3140 // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3141 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3142 // CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 3143 // CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 3144 // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 3145 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 3146 // CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 3147 // CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 3148 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 3149 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3150 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3151 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3152 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3153 // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3154 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3155 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 3156 // CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 3157 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 3158 // CHECK13-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3159 // CHECK13-NEXT: [[AGG_TMP7:%.*]] = alloca [[STRUCT_ST]], align 4 3160 // CHECK13-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 3161 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 3162 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3163 // CHECK13-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3164 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 3165 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 3166 // CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 3167 // CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 3168 // CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 3169 // CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 3170 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 3171 // CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 3172 // CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 3173 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 3174 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3175 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 3176 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 3177 // CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 3178 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 3179 // CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32 3180 // CHECK13-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 3181 // CHECK13-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 3182 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3183 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3184 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false) 3185 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 3186 // CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 3187 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 3188 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3189 // CHECK13: omp.arraycpy.body: 3190 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3191 // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3192 // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 3193 // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 3194 // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] 3195 // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3196 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3197 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 3198 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]] 3199 // CHECK13: omp.arraycpy.done5: 3200 // CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 3201 // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) 3202 // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP7]]) 3203 // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) #[[ATTR3]] 3204 // CHECK13-NEXT: store ptr [[VAR6]], ptr [[_TMP8]], align 8 3205 // CHECK13-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3206 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 3207 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3208 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3209 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 3210 // CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3211 // CHECK13: cond.true: 3212 // CHECK13-NEXT: br label [[COND_END:%.*]] 3213 // CHECK13: cond.false: 3214 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3215 // CHECK13-NEXT: br label [[COND_END]] 3216 // CHECK13: cond.end: 3217 // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 3218 // CHECK13-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3219 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3220 // CHECK13-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 3221 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3222 // CHECK13: omp.inner.for.cond: 3223 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3224 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3225 // CHECK13-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 3226 // CHECK13-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3227 // CHECK13: omp.inner.for.cond.cleanup: 3228 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3229 // CHECK13: omp.inner.for.body: 3230 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3231 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 3232 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3233 // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 3234 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 3235 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 3236 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 3237 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] 3238 // CHECK13-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 3239 // CHECK13-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8 3240 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 3241 // CHECK13-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 3242 // CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] 3243 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false) 3244 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3245 // CHECK13: omp.body.continue: 3246 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3247 // CHECK13: omp.inner.for.inc: 3248 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3249 // CHECK13-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 3250 // CHECK13-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4 3251 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] 3252 // CHECK13: omp.inner.for.end: 3253 // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3254 // CHECK13: omp.loop.exit: 3255 // CHECK13-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3256 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 3257 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 3258 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR3]] 3259 // CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 3260 // CHECK13-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 3261 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3262 // CHECK13: arraydestroy.body: 3263 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3264 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3265 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 3266 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] 3267 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] 3268 // CHECK13: arraydestroy.done14: 3269 // CHECK13-NEXT: ret void 3270 // 3271 // 3272 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3273 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 3274 // CHECK13-NEXT: entry: 3275 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3276 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3277 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3278 // CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] 3279 // CHECK13-NEXT: ret void 3280 // 3281 // 3282 // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC2Ev 3283 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 3284 // CHECK13-NEXT: entry: 3285 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3286 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3287 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3288 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 3289 // CHECK13-NEXT: store i32 0, ptr [[A]], align 4 3290 // CHECK13-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 3291 // CHECK13-NEXT: store i32 0, ptr [[B]], align 4 3292 // CHECK13-NEXT: ret void 3293 // 3294 // 3295 // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD2Ev 3296 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 3297 // CHECK13-NEXT: entry: 3298 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3299 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3300 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3301 // CHECK13-NEXT: ret void 3302 // 3303 // 3304 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3305 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 3306 // CHECK13-NEXT: entry: 3307 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3308 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3309 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3310 // CHECK13-NEXT: ret void 3311 // 3312 // 3313 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 3314 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat { 3315 // CHECK13-NEXT: entry: 3316 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3317 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 3318 // CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 3319 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3320 // CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 3321 // CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 3322 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3323 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 3324 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 3325 // CHECK13-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 3326 // CHECK13-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 3327 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 3328 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 3329 // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 3330 // CHECK13-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 3331 // CHECK13-NEXT: store float [[ADD]], ptr [[F]], align 4 3332 // CHECK13-NEXT: ret void 3333 // 3334 // 3335 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3336 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { 3337 // CHECK13-NEXT: entry: 3338 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3339 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3340 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3341 // CHECK13-NEXT: ret void 3342 // 3343 // 3344 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 3345 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat { 3346 // CHECK13-NEXT: entry: 3347 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 3348 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 3349 // CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 3350 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 3351 // CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 3352 // CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 3353 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 3354 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 3355 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 3356 // CHECK13-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 3357 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 3358 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 3359 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 3360 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 3361 // CHECK13-NEXT: store i32 [[ADD]], ptr [[F]], align 4 3362 // CHECK13-NEXT: ret void 3363 // 3364 // 3365 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 3366 // CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { 3367 // CHECK15-NEXT: entry: 3368 // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 3369 // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 3370 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 3371 // CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 3372 // CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 3373 // CHECK15-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 3374 // CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 3375 // CHECK15-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 3376 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 3377 // CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 3378 // CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 3379 // CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 3380 // CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 3381 // CHECK15-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 3382 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 3383 // CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 3384 // CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 3385 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 3386 // CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 3387 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 3388 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 3389 // CHECK15-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 3390 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 3391 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]]) 3392 // CHECK15-NEXT: ret void 3393 // 3394 // 3395 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined 3396 // CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0]] { 3397 // CHECK15-NEXT: entry: 3398 // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3399 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3400 // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 3401 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 3402 // CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 3403 // CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 3404 // CHECK15-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 3405 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3406 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 3407 // CHECK15-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 3408 // CHECK15-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 3409 // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3410 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3411 // CHECK15-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 3412 // CHECK15-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 3413 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 3414 // CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 3415 // CHECK15-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 3416 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 3417 // CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 3418 // CHECK15-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 3419 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3420 // CHECK15-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3421 // CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 3422 // CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 3423 // CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 3424 // CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 3425 // CHECK15-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 3426 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 3427 // CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 3428 // CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 3429 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 3430 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 3431 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3432 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3433 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) 3434 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 3435 // CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 3436 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 3437 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3438 // CHECK15: omp.arraycpy.body: 3439 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3440 // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3441 // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 3442 // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 3443 // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3:[0-9]+]] 3444 // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3445 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3446 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 3447 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 3448 // CHECK15: omp.arraycpy.done3: 3449 // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 3450 // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 3451 // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR3]] 3452 // CHECK15-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3453 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 3454 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3455 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3456 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 3457 // CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3458 // CHECK15: cond.true: 3459 // CHECK15-NEXT: br label [[COND_END:%.*]] 3460 // CHECK15: cond.false: 3461 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3462 // CHECK15-NEXT: br label [[COND_END]] 3463 // CHECK15: cond.end: 3464 // CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3465 // CHECK15-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 3466 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 3467 // CHECK15-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 3468 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3469 // CHECK15: omp.inner.for.cond: 3470 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3471 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3472 // CHECK15-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 3473 // CHECK15-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3474 // CHECK15: omp.inner.for.cond.cleanup: 3475 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3476 // CHECK15: omp.inner.for.body: 3477 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 3478 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3479 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 3480 // CHECK15-NEXT: store i32 [[TMP13]], ptr [[T_VAR_CASTED]], align 4 3481 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 3482 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 3483 // CHECK15-NEXT: store i32 [[TMP15]], ptr [[SIVAR_CASTED]], align 4 3484 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 3485 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined.omp_outlined, i32 [[TMP11]], i32 [[TMP12]], ptr [[VEC1]], i32 [[TMP14]], ptr [[S_ARR2]], ptr [[VAR4]], i32 [[TMP16]]) 3486 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3487 // CHECK15: omp.inner.for.inc: 3488 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3489 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 3490 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] 3491 // CHECK15-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 3492 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] 3493 // CHECK15: omp.inner.for.end: 3494 // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3495 // CHECK15: omp.loop.exit: 3496 // CHECK15-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3497 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 3498 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) 3499 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR3]] 3500 // CHECK15-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 3501 // CHECK15-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 2 3502 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3503 // CHECK15: arraydestroy.body: 3504 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP21]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3505 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3506 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 3507 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 3508 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 3509 // CHECK15: arraydestroy.done8: 3510 // CHECK15-NEXT: ret void 3511 // 3512 // 3513 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC1Ev 3514 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { 3515 // CHECK15-NEXT: entry: 3516 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3517 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3518 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3519 // CHECK15-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 3520 // CHECK15-NEXT: ret void 3521 // 3522 // 3523 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 3524 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 3525 // CHECK15-NEXT: entry: 3526 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3527 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 3528 // CHECK15-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 3529 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3530 // CHECK15-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 3531 // CHECK15-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 3532 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3533 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 3534 // CHECK15-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 3535 // CHECK15-NEXT: ret void 3536 // 3537 // 3538 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD1Ev 3539 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 3540 // CHECK15-NEXT: entry: 3541 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3542 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3543 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3544 // CHECK15-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] 3545 // CHECK15-NEXT: ret void 3546 // 3547 // 3548 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined.omp_outlined 3549 // CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0]] { 3550 // CHECK15-NEXT: entry: 3551 // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3552 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3553 // CHECK15-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 3554 // CHECK15-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 3555 // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 3556 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 3557 // CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 3558 // CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 3559 // CHECK15-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 3560 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3561 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 3562 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3563 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3564 // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3565 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3566 // CHECK15-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 3567 // CHECK15-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 3568 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 3569 // CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 3570 // CHECK15-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 3571 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 3572 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3573 // CHECK15-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3574 // CHECK15-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 3575 // CHECK15-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 3576 // CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 3577 // CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 3578 // CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 3579 // CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 3580 // CHECK15-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 3581 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 3582 // CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 3583 // CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 3584 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3585 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 3586 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 3587 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 3588 // CHECK15-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4 3589 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 3590 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3591 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3592 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) 3593 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 3594 // CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 3595 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 3596 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3597 // CHECK15: omp.arraycpy.body: 3598 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3599 // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3600 // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 3601 // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 3602 // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] 3603 // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3604 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3605 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 3606 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 3607 // CHECK15: omp.arraycpy.done3: 3608 // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 3609 // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 3610 // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR3]] 3611 // CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3612 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 3613 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3614 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3615 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 3616 // CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3617 // CHECK15: cond.true: 3618 // CHECK15-NEXT: br label [[COND_END:%.*]] 3619 // CHECK15: cond.false: 3620 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3621 // CHECK15-NEXT: br label [[COND_END]] 3622 // CHECK15: cond.end: 3623 // CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] 3624 // CHECK15-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3625 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3626 // CHECK15-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 3627 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3628 // CHECK15: omp.inner.for.cond: 3629 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3630 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3631 // CHECK15-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 3632 // CHECK15-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3633 // CHECK15: omp.inner.for.cond.cleanup: 3634 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3635 // CHECK15: omp.inner.for.body: 3636 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3637 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 3638 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3639 // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4 3640 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 3641 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 3642 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP15]] 3643 // CHECK15-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 3644 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 3645 // CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] 3646 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false) 3647 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 3648 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 3649 // CHECK15-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP18]], [[TMP17]] 3650 // CHECK15-NEXT: store i32 [[ADD8]], ptr [[SIVAR_ADDR]], align 4 3651 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3652 // CHECK15: omp.body.continue: 3653 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3654 // CHECK15: omp.inner.for.inc: 3655 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3656 // CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1 3657 // CHECK15-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4 3658 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] 3659 // CHECK15: omp.inner.for.end: 3660 // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3661 // CHECK15: omp.loop.exit: 3662 // CHECK15-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3663 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 3664 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 3665 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR3]] 3666 // CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 3667 // CHECK15-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 3668 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3669 // CHECK15: arraydestroy.body: 3670 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3671 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3672 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 3673 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 3674 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 3675 // CHECK15: arraydestroy.done11: 3676 // CHECK15-NEXT: ret void 3677 // 3678 // 3679 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3680 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 3681 // CHECK15-NEXT: entry: 3682 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3683 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3684 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3685 // CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] 3686 // CHECK15-NEXT: ret void 3687 // 3688 // 3689 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 3690 // CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { 3691 // CHECK15-NEXT: entry: 3692 // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 3693 // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 3694 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 3695 // CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 3696 // CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 3697 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 3698 // CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 3699 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 3700 // CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 3701 // CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 3702 // CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 3703 // CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 3704 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 3705 // CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 3706 // CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 3707 // CHECK15-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 3708 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 3709 // CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 3710 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 3711 // CHECK15-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 3712 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) 3713 // CHECK15-NEXT: ret void 3714 // 3715 // 3716 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined 3717 // CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { 3718 // CHECK15-NEXT: entry: 3719 // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3720 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3721 // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 3722 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 3723 // CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 3724 // CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 3725 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 3726 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3727 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3728 // CHECK15-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 3729 // CHECK15-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 3730 // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3731 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3732 // CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 3733 // CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 3734 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 3735 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3736 // CHECK15-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 3737 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 3738 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 3739 // CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 3740 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3741 // CHECK15-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3742 // CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 3743 // CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 3744 // CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 3745 // CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 3746 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 3747 // CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 3748 // CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 3749 // CHECK15-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 3750 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 3751 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 3752 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3753 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3754 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) 3755 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 3756 // CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 3757 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 3758 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3759 // CHECK15: omp.arraycpy.body: 3760 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3761 // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3762 // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 3763 // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 3764 // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] 3765 // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3766 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3767 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 3768 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 3769 // CHECK15: omp.arraycpy.done4: 3770 // CHECK15-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 3771 // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 3772 // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) 3773 // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] 3774 // CHECK15-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 3775 // CHECK15-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3776 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 3777 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3778 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3779 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 3780 // CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3781 // CHECK15: cond.true: 3782 // CHECK15-NEXT: br label [[COND_END:%.*]] 3783 // CHECK15: cond.false: 3784 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3785 // CHECK15-NEXT: br label [[COND_END]] 3786 // CHECK15: cond.end: 3787 // CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 3788 // CHECK15-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 3789 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 3790 // CHECK15-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 3791 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3792 // CHECK15: omp.inner.for.cond: 3793 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3794 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3795 // CHECK15-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 3796 // CHECK15-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3797 // CHECK15: omp.inner.for.cond.cleanup: 3798 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3799 // CHECK15: omp.inner.for.body: 3800 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 3801 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 3802 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 3803 // CHECK15-NEXT: store i32 [[TMP14]], ptr [[T_VAR_CASTED]], align 4 3804 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 3805 // CHECK15-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 4 3806 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined.omp_outlined, i32 [[TMP12]], i32 [[TMP13]], ptr [[VEC2]], i32 [[TMP15]], ptr [[S_ARR3]], ptr [[TMP16]]) 3807 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3808 // CHECK15: omp.inner.for.inc: 3809 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3810 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 3811 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] 3812 // CHECK15-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 3813 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] 3814 // CHECK15: omp.inner.for.end: 3815 // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3816 // CHECK15: omp.loop.exit: 3817 // CHECK15-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3818 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 3819 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) 3820 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] 3821 // CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 3822 // CHECK15-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 3823 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3824 // CHECK15: arraydestroy.body: 3825 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP21]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3826 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3827 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 3828 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] 3829 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] 3830 // CHECK15: arraydestroy.done10: 3831 // CHECK15-NEXT: ret void 3832 // 3833 // 3834 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 3835 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 3836 // CHECK15-NEXT: entry: 3837 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3838 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 3839 // CHECK15-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 3840 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3841 // CHECK15-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 3842 // CHECK15-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 3843 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3844 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 3845 // CHECK15-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 3846 // CHECK15-NEXT: ret void 3847 // 3848 // 3849 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined.omp_outlined 3850 // CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { 3851 // CHECK15-NEXT: entry: 3852 // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3853 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3854 // CHECK15-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 3855 // CHECK15-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 3856 // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 3857 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 3858 // CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 3859 // CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 3860 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 3861 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3862 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3863 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3864 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3865 // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3866 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3867 // CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 3868 // CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 3869 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 3870 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3871 // CHECK15-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 3872 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 3873 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 3874 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3875 // CHECK15-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3876 // CHECK15-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 3877 // CHECK15-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 3878 // CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 3879 // CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 3880 // CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 3881 // CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 3882 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 3883 // CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 3884 // CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 3885 // CHECK15-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 3886 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3887 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 3888 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 3889 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 3890 // CHECK15-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4 3891 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 3892 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3893 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3894 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) 3895 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 3896 // CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 3897 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 3898 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3899 // CHECK15: omp.arraycpy.body: 3900 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3901 // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3902 // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 3903 // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 3904 // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] 3905 // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3906 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3907 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 3908 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 3909 // CHECK15: omp.arraycpy.done4: 3910 // CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 3911 // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 3912 // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP6]]) 3913 // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] 3914 // CHECK15-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 3915 // CHECK15-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3916 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 3917 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3918 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3919 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 3920 // CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3921 // CHECK15: cond.true: 3922 // CHECK15-NEXT: br label [[COND_END:%.*]] 3923 // CHECK15: cond.false: 3924 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3925 // CHECK15-NEXT: br label [[COND_END]] 3926 // CHECK15: cond.end: 3927 // CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 3928 // CHECK15-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3929 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3930 // CHECK15-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 3931 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3932 // CHECK15: omp.inner.for.cond: 3933 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3934 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3935 // CHECK15-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 3936 // CHECK15-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3937 // CHECK15: omp.inner.for.cond.cleanup: 3938 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3939 // CHECK15: omp.inner.for.body: 3940 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3941 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 3942 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3943 // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4 3944 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 3945 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 3946 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]] 3947 // CHECK15-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 3948 // CHECK15-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4 3949 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 3950 // CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] 3951 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false) 3952 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3953 // CHECK15: omp.body.continue: 3954 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3955 // CHECK15: omp.inner.for.inc: 3956 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3957 // CHECK15-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 3958 // CHECK15-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4 3959 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] 3960 // CHECK15: omp.inner.for.end: 3961 // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3962 // CHECK15: omp.loop.exit: 3963 // CHECK15-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3964 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 3965 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 3966 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] 3967 // CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 3968 // CHECK15-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 3969 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3970 // CHECK15: arraydestroy.body: 3971 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3972 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3973 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 3974 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 3975 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 3976 // CHECK15: arraydestroy.done12: 3977 // CHECK15-NEXT: ret void 3978 // 3979 // 3980 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3981 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 3982 // CHECK15-NEXT: entry: 3983 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3984 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3985 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3986 // CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] 3987 // CHECK15-NEXT: ret void 3988 // 3989 // 3990 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC2Ev 3991 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 3992 // CHECK15-NEXT: entry: 3993 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3994 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3995 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3996 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 3997 // CHECK15-NEXT: store i32 0, ptr [[A]], align 4 3998 // CHECK15-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 3999 // CHECK15-NEXT: store i32 0, ptr [[B]], align 4 4000 // CHECK15-NEXT: ret void 4001 // 4002 // 4003 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD2Ev 4004 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 4005 // CHECK15-NEXT: entry: 4006 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 4007 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 4008 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 4009 // CHECK15-NEXT: ret void 4010 // 4011 // 4012 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4013 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 4014 // CHECK15-NEXT: entry: 4015 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 4016 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 4017 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 4018 // CHECK15-NEXT: ret void 4019 // 4020 // 4021 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 4022 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 4023 // CHECK15-NEXT: entry: 4024 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 4025 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 4026 // CHECK15-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 4027 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 4028 // CHECK15-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 4029 // CHECK15-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 4030 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 4031 // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 4032 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 4033 // CHECK15-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 4034 // CHECK15-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 4035 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 4036 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 4037 // CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 4038 // CHECK15-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 4039 // CHECK15-NEXT: store float [[ADD]], ptr [[F]], align 4 4040 // CHECK15-NEXT: ret void 4041 // 4042 // 4043 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 4044 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 4045 // CHECK15-NEXT: entry: 4046 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 4047 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 4048 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 4049 // CHECK15-NEXT: ret void 4050 // 4051 // 4052 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 4053 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 4054 // CHECK15-NEXT: entry: 4055 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 4056 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 4057 // CHECK15-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 4058 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 4059 // CHECK15-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 4060 // CHECK15-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 4061 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 4062 // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 4063 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 4064 // CHECK15-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 4065 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 4066 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 4067 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 4068 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 4069 // CHECK15-NEXT: store i32 [[ADD]], ptr [[F]], align 4 4070 // CHECK15-NEXT: ret void 4071 // 4072 // 4073 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 4074 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { 4075 // CHECK17-NEXT: entry: 4076 // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 4077 // CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 4078 // CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 4079 // CHECK17-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 4080 // CHECK17-NEXT: [[TMP:%.*]] = alloca ptr, align 8 4081 // CHECK17-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 4082 // CHECK17-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 4083 // CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 4084 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 4085 // CHECK17-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 4086 // CHECK17-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 4087 // CHECK17-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 4088 // CHECK17-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 4089 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 4 4090 // CHECK17-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4 4091 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8 4092 // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 4093 // CHECK17-NEXT: [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 4 4094 // CHECK17-NEXT: store i32 [[TMP3]], ptr [[G1_CASTED]], align 4 4095 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 8 4096 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 4097 // CHECK17-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 4098 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 4099 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) 4100 // CHECK17-NEXT: ret void 4101 // 4102 // 4103 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined 4104 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { 4105 // CHECK17-NEXT: entry: 4106 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4107 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4108 // CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 4109 // CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 4110 // CHECK17-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 4111 // CHECK17-NEXT: [[TMP:%.*]] = alloca ptr, align 8 4112 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4113 // CHECK17-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 4114 // CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 4115 // CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 4116 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4117 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4118 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 4119 // CHECK17-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 4120 // CHECK17-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 4121 // CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 4122 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4123 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4124 // CHECK17-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 4125 // CHECK17-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 4126 // CHECK17-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 4127 // CHECK17-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 4128 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 4129 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 4130 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4131 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4132 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4133 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 4134 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 4135 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 4136 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 4137 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4138 // CHECK17: cond.true: 4139 // CHECK17-NEXT: br label [[COND_END:%.*]] 4140 // CHECK17: cond.false: 4141 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 4142 // CHECK17-NEXT: br label [[COND_END]] 4143 // CHECK17: cond.end: 4144 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4145 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 4146 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 4147 // CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 4148 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4149 // CHECK17: omp.inner.for.cond: 4150 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4151 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 4152 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4153 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4154 // CHECK17: omp.inner.for.body: 4155 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 4156 // CHECK17-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 4157 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 4158 // CHECK17-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 4159 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[G_ADDR]], align 4 4160 // CHECK17-NEXT: store i32 [[TMP11]], ptr [[G_CASTED]], align 4 4161 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[G_CASTED]], align 8 4162 // CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8 4163 // CHECK17-NEXT: [[TMP14:%.*]] = load volatile i32, ptr [[TMP13]], align 4 4164 // CHECK17-NEXT: store i32 [[TMP14]], ptr [[G1_CASTED]], align 4 4165 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[G1_CASTED]], align 8 4166 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 4167 // CHECK17-NEXT: store i32 [[TMP16]], ptr [[SIVAR_CASTED]], align 4 4168 // CHECK17-NEXT: [[TMP17:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 4169 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) 4170 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4171 // CHECK17: omp.inner.for.inc: 4172 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4173 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 4174 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 4175 // CHECK17-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 4176 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 4177 // CHECK17: omp.inner.for.end: 4178 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4179 // CHECK17: omp.loop.exit: 4180 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 4181 // CHECK17-NEXT: ret void 4182 // 4183 // 4184 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined.omp_outlined 4185 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { 4186 // CHECK17-NEXT: entry: 4187 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4188 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4189 // CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 4190 // CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 4191 // CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 4192 // CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 4193 // CHECK17-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 4194 // CHECK17-NEXT: [[TMP:%.*]] = alloca ptr, align 8 4195 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4196 // CHECK17-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 4197 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4198 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4199 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4200 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4201 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 4202 // CHECK17-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 4203 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4204 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4205 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 4206 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 4207 // CHECK17-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 4208 // CHECK17-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 4209 // CHECK17-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 4210 // CHECK17-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 4211 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4212 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 4213 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 4214 // CHECK17-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 4215 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 4216 // CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 4217 // CHECK17-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 4218 // CHECK17-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 4219 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4220 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4221 // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4222 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 4223 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 4224 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4225 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 4226 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4227 // CHECK17: cond.true: 4228 // CHECK17-NEXT: br label [[COND_END:%.*]] 4229 // CHECK17: cond.false: 4230 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4231 // CHECK17-NEXT: br label [[COND_END]] 4232 // CHECK17: cond.end: 4233 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 4234 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4235 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4236 // CHECK17-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 4237 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4238 // CHECK17: omp.inner.for.cond: 4239 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4240 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4241 // CHECK17-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 4242 // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4243 // CHECK17: omp.inner.for.body: 4244 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4245 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 4246 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4247 // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4 4248 // CHECK17-NEXT: store i32 1, ptr [[G_ADDR]], align 4 4249 // CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP]], align 8 4250 // CHECK17-NEXT: store volatile i32 1, ptr [[TMP10]], align 4 4251 // CHECK17-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 4252 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 4253 // CHECK17-NEXT: store ptr [[G_ADDR]], ptr [[TMP11]], align 8 4254 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 4255 // CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8 4256 // CHECK17-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 4257 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 2 4258 // CHECK17-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP14]], align 8 4259 // CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 4260 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4261 // CHECK17: omp.body.continue: 4262 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4263 // CHECK17: omp.inner.for.inc: 4264 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4265 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 4266 // CHECK17-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 4267 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 4268 // CHECK17: omp.inner.for.end: 4269 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4270 // CHECK17: omp.loop.exit: 4271 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 4272 // CHECK17-NEXT: ret void 4273 // 4274