1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target teams distribute firstprivate(t_var, vec, s_arr, var) 57 for (int i = 0; i < 2; ++i) { 58 vec[i] = t_var; 59 s_arr[i] = var; 60 } 61 return T(); 62 } 63 64 S<float> test; 65 int t_var = 333; 66 int vec[] = {1, 2}; 67 S<float> s_arr[] = {1, 2}; 68 S<float> var(3); 69 70 int main() { 71 static int sivar; 72 #ifdef LAMBDA 73 [&]() { 74 #pragma omp target teams distribute firstprivate(g, g1, sivar) 75 for (int i = 0; i < 2; ++i) { 76 77 // Skip global and bound tid vars 78 // skip loop vars 79 g = 1; 80 g1 = 1; 81 sivar = 2; 82 [&]() { 83 g = 2; 84 g1 = 2; 85 sivar = 4; 86 87 }(); 88 } 89 }(); 90 return 0; 91 #else 92 #pragma omp target teams distribute firstprivate(t_var, vec, s_arr, var, sivar) 93 for (int i = 0; i < 2; ++i) { 94 vec[i] = t_var; 95 s_arr[i] = var; 96 sivar += i; 97 } 98 return tmain<int>(); 99 #endif 100 } 101 102 103 104 105 106 // Skip global and bound tid vars 107 // Skip temp vars for loop 108 109 // param copy 110 111 // T_VAR and SIVAR 112 113 // preparation vars 114 115 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 116 117 // firstprivate(s_arr) 118 119 // firstprivate(var) 120 121 122 123 124 125 126 // Skip global and bound tid vars 127 // Skip temp vars for loop 128 129 // param copy 130 131 // T_VAR and preparation variables 132 133 134 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 135 136 // firstprivate(s_arr) 137 138 // firstprivate(var) 139 140 141 #endif 142 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 143 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 144 // CHECK1-NEXT: entry: 145 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 146 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 147 // CHECK1-NEXT: ret void 148 // 149 // 150 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 151 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 152 // CHECK1-NEXT: entry: 153 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 154 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 155 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 156 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 157 // CHECK1-NEXT: ret void 158 // 159 // 160 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 161 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 162 // CHECK1-NEXT: entry: 163 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 164 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 165 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 166 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 167 // CHECK1-NEXT: ret void 168 // 169 // 170 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 171 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 172 // CHECK1-NEXT: entry: 173 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 174 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 175 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 176 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 177 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 178 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 179 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 180 // CHECK1-NEXT: ret void 181 // 182 // 183 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 184 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 185 // CHECK1-NEXT: entry: 186 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 187 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 188 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 189 // CHECK1-NEXT: ret void 190 // 191 // 192 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 193 // CHECK1-SAME: () #[[ATTR0]] { 194 // CHECK1-NEXT: entry: 195 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 196 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 197 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 198 // CHECK1-NEXT: ret void 199 // 200 // 201 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 202 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 203 // CHECK1-NEXT: entry: 204 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 205 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 206 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 207 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 208 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 209 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 210 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 211 // CHECK1-NEXT: ret void 212 // 213 // 214 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 215 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 216 // CHECK1-NEXT: entry: 217 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 218 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 219 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 220 // CHECK1: arraydestroy.body: 221 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 222 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 223 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 224 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 225 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 226 // CHECK1: arraydestroy.done1: 227 // CHECK1-NEXT: ret void 228 // 229 // 230 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 231 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 232 // CHECK1-NEXT: entry: 233 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 234 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 235 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 236 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 237 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 238 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 239 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 240 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 241 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 242 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 243 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 244 // CHECK1-NEXT: ret void 245 // 246 // 247 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 248 // CHECK1-SAME: () #[[ATTR0]] { 249 // CHECK1-NEXT: entry: 250 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 251 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 252 // CHECK1-NEXT: ret void 253 // 254 // 255 // CHECK1-LABEL: define {{[^@]+}}@main 256 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 257 // CHECK1-NEXT: entry: 258 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 259 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 260 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 261 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 262 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 263 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 264 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 265 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 266 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 267 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr @t_var, align 4 268 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 269 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 270 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 271 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 272 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 273 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 274 // CHECK1-NEXT: store ptr @vec, ptr [[TMP4]], align 8 275 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 276 // CHECK1-NEXT: store ptr @vec, ptr [[TMP5]], align 8 277 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 278 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 279 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 280 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP7]], align 8 281 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 282 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP8]], align 8 283 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 284 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 285 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 286 // CHECK1-NEXT: store ptr @s_arr, ptr [[TMP10]], align 8 287 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 288 // CHECK1-NEXT: store ptr @s_arr, ptr [[TMP11]], align 8 289 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 290 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 291 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 292 // CHECK1-NEXT: store ptr @var, ptr [[TMP13]], align 8 293 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 294 // CHECK1-NEXT: store ptr @var, ptr [[TMP14]], align 8 295 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 296 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 297 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 298 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP16]], align 8 299 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 300 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP17]], align 8 301 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 302 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 303 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 304 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 305 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 306 // CHECK1-NEXT: store i32 3, ptr [[TMP21]], align 4 307 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 308 // CHECK1-NEXT: store i32 5, ptr [[TMP22]], align 4 309 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 310 // CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8 311 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 312 // CHECK1-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8 313 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 314 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 8 315 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 316 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 8 317 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 318 // CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8 319 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 320 // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8 321 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 322 // CHECK1-NEXT: store i64 2, ptr [[TMP29]], align 8 323 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 324 // CHECK1-NEXT: store i64 0, ptr [[TMP30]], align 8 325 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 326 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 327 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 328 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 329 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 330 // CHECK1-NEXT: store i32 0, ptr [[TMP33]], align 4 331 // CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.region_id, ptr [[KERNEL_ARGS]]) 332 // CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 333 // CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 334 // CHECK1: omp_offload.failed: 335 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92(ptr @vec, i64 [[TMP1]], ptr @s_arr, ptr @var, i64 [[TMP3]]) #[[ATTR2]] 336 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 337 // CHECK1: omp_offload.cont: 338 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 339 // CHECK1-NEXT: ret i32 [[CALL]] 340 // 341 // 342 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 343 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 344 // CHECK1-NEXT: entry: 345 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 346 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 347 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 348 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 349 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 350 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 351 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 352 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 353 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 354 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 355 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 356 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 357 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 358 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 359 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 360 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 361 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 362 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 363 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 364 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 365 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 366 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]]) 367 // CHECK1-NEXT: ret void 368 // 369 // 370 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.omp_outlined 371 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 372 // CHECK1-NEXT: entry: 373 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 374 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 375 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 376 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 377 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 378 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 379 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 380 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 381 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 382 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 383 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 384 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 385 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 386 // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 387 // CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 388 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 389 // CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 390 // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 391 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 392 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 393 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 394 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 395 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 396 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 397 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 398 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 399 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 400 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 401 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 402 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 403 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 404 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 405 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 406 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) 407 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 408 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 409 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 410 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 411 // CHECK1: omp.arraycpy.body: 412 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 413 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 414 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 415 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 416 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 417 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 418 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 419 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 420 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 421 // CHECK1: omp.arraycpy.done3: 422 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 423 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 424 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 425 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 426 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 427 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 428 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 429 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 430 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 431 // CHECK1: cond.true: 432 // CHECK1-NEXT: br label [[COND_END:%.*]] 433 // CHECK1: cond.false: 434 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 435 // CHECK1-NEXT: br label [[COND_END]] 436 // CHECK1: cond.end: 437 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 438 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 439 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 440 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 441 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 442 // CHECK1: omp.inner.for.cond: 443 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 444 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 445 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 446 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 447 // CHECK1: omp.inner.for.cond.cleanup: 448 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 449 // CHECK1: omp.inner.for.body: 450 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 451 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 452 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 453 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 454 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 455 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 456 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 457 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 [[IDXPROM]] 458 // CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 459 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 460 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 461 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]] 462 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR4]], i64 4, i1 false) 463 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 464 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 465 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 466 // CHECK1-NEXT: store i32 [[ADD9]], ptr [[SIVAR_ADDR]], align 4 467 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 468 // CHECK1: omp.body.continue: 469 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 470 // CHECK1: omp.inner.for.inc: 471 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 472 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP17]], 1 473 // CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4 474 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 475 // CHECK1: omp.inner.for.end: 476 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 477 // CHECK1: omp.loop.exit: 478 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 479 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 480 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) 481 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 482 // CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 483 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 484 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 485 // CHECK1: arraydestroy.body: 486 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 487 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 488 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 489 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 490 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 491 // CHECK1: arraydestroy.done12: 492 // CHECK1-NEXT: ret void 493 // 494 // 495 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev 496 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 497 // CHECK1-NEXT: entry: 498 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 499 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 500 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 501 // CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 502 // CHECK1-NEXT: ret void 503 // 504 // 505 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 506 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 507 // CHECK1-NEXT: entry: 508 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 509 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 510 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 511 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 512 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 513 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 514 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 515 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 516 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 517 // CHECK1-NEXT: ret void 518 // 519 // 520 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev 521 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 522 // CHECK1-NEXT: entry: 523 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 524 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 525 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 526 // CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 527 // CHECK1-NEXT: ret void 528 // 529 // 530 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 531 // CHECK1-SAME: () #[[ATTR1]] comdat { 532 // CHECK1-NEXT: entry: 533 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 534 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 535 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 536 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 537 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 538 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 539 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 540 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 541 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 542 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 543 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 544 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 545 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 546 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 547 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 548 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 549 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 550 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 551 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 552 // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 553 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 554 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 555 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 556 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 557 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 558 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 559 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 560 // CHECK1-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 8 561 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 562 // CHECK1-NEXT: store ptr [[VEC]], ptr [[TMP5]], align 8 563 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 564 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 565 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 566 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP7]], align 8 567 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 568 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP8]], align 8 569 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 570 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 571 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 572 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[TMP10]], align 8 573 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 574 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[TMP11]], align 8 575 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 576 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 577 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 578 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 8 579 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 580 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 8 581 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 582 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 583 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 584 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 585 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 586 // CHECK1-NEXT: store i32 3, ptr [[TMP18]], align 4 587 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 588 // CHECK1-NEXT: store i32 4, ptr [[TMP19]], align 4 589 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 590 // CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 8 591 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 592 // CHECK1-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 8 593 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 594 // CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP22]], align 8 595 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 596 // CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP23]], align 8 597 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 598 // CHECK1-NEXT: store ptr null, ptr [[TMP24]], align 8 599 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 600 // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 601 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 602 // CHECK1-NEXT: store i64 2, ptr [[TMP26]], align 8 603 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 604 // CHECK1-NEXT: store i64 0, ptr [[TMP27]], align 8 605 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 606 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 607 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 608 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4 609 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 610 // CHECK1-NEXT: store i32 0, ptr [[TMP30]], align 4 611 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 612 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 613 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 614 // CHECK1: omp_offload.failed: 615 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(ptr [[VEC]], i64 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]] 616 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 617 // CHECK1: omp_offload.cont: 618 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 619 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 620 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 621 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 622 // CHECK1: arraydestroy.body: 623 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 624 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 625 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 626 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 627 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 628 // CHECK1: arraydestroy.done2: 629 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 630 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 631 // CHECK1-NEXT: ret i32 [[TMP34]] 632 // 633 // 634 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev 635 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 636 // CHECK1-NEXT: entry: 637 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 638 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 639 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 640 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 641 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 642 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 643 // CHECK1-NEXT: store i32 0, ptr [[B]], align 4 644 // CHECK1-NEXT: ret void 645 // 646 // 647 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 648 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 649 // CHECK1-NEXT: entry: 650 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 651 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 652 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 653 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 654 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 655 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 656 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 657 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 658 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 659 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 660 // CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 661 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 662 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 663 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 664 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 665 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 666 // CHECK1-NEXT: ret void 667 // 668 // 669 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev 670 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 671 // CHECK1-NEXT: entry: 672 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 673 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 674 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 675 // CHECK1-NEXT: ret void 676 // 677 // 678 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 679 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 680 // CHECK1-NEXT: entry: 681 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 682 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 683 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 684 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 685 // CHECK1-NEXT: ret void 686 // 687 // 688 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 689 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 690 // CHECK1-NEXT: entry: 691 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 692 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 693 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 694 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 695 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 696 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 697 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 698 // CHECK1-NEXT: ret void 699 // 700 // 701 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 702 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 703 // CHECK1-NEXT: entry: 704 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 705 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 706 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 707 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 708 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 709 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 710 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 711 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 712 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 713 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 714 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 715 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 716 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 717 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 718 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 719 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 720 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 721 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 722 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) 723 // CHECK1-NEXT: ret void 724 // 725 // 726 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 727 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 728 // CHECK1-NEXT: entry: 729 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 730 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 731 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 732 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 733 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 734 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 735 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 736 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 737 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 738 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 739 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 740 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 741 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 742 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 743 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 744 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 745 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 746 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 747 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 748 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 749 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 750 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 751 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 752 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 753 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 754 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 755 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 756 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 757 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 758 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 759 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 760 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 761 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 762 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 763 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) 764 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 765 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 766 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 767 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 768 // CHECK1: omp.arraycpy.body: 769 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 770 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 771 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 772 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 773 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 774 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 775 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 776 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 777 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 778 // CHECK1: omp.arraycpy.done4: 779 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 780 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 781 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) 782 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 783 // CHECK1-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8 784 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 785 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 786 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 787 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 788 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 789 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 790 // CHECK1: cond.true: 791 // CHECK1-NEXT: br label [[COND_END:%.*]] 792 // CHECK1: cond.false: 793 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 794 // CHECK1-NEXT: br label [[COND_END]] 795 // CHECK1: cond.end: 796 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 797 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 798 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 799 // CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 800 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 801 // CHECK1: omp.inner.for.cond: 802 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 803 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 804 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 805 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 806 // CHECK1: omp.inner.for.cond.cleanup: 807 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 808 // CHECK1: omp.inner.for.body: 809 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 810 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 811 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 812 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 813 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 814 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 815 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 816 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] 817 // CHECK1-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 818 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8 819 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 820 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP16]] to i64 821 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]] 822 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP15]], i64 4, i1 false) 823 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 824 // CHECK1: omp.body.continue: 825 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 826 // CHECK1: omp.inner.for.inc: 827 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 828 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 829 // CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4 830 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 831 // CHECK1: omp.inner.for.end: 832 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 833 // CHECK1: omp.loop.exit: 834 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 835 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 836 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) 837 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 838 // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 839 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 840 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 841 // CHECK1: arraydestroy.body: 842 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 843 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 844 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 845 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 846 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 847 // CHECK1: arraydestroy.done13: 848 // CHECK1-NEXT: ret void 849 // 850 // 851 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 852 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 853 // CHECK1-NEXT: entry: 854 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 855 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 856 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 857 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 858 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 859 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 860 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 861 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 862 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 863 // CHECK1-NEXT: ret void 864 // 865 // 866 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 867 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 868 // CHECK1-NEXT: entry: 869 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 870 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 871 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 872 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 873 // CHECK1-NEXT: ret void 874 // 875 // 876 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 877 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 878 // CHECK1-NEXT: entry: 879 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 880 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 881 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 882 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 883 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 884 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 885 // CHECK1-NEXT: ret void 886 // 887 // 888 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 889 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 890 // CHECK1-NEXT: entry: 891 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 892 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 893 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 894 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 895 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 896 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 897 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 898 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 899 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 900 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 901 // CHECK1-NEXT: ret void 902 // 903 // 904 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 905 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 906 // CHECK1-NEXT: entry: 907 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 908 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 909 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 910 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 911 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 912 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 913 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 914 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 915 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 916 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 917 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 918 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 919 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 920 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 921 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 922 // CHECK1-NEXT: ret void 923 // 924 // 925 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 926 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 927 // CHECK1-NEXT: entry: 928 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 929 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 930 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 931 // CHECK1-NEXT: ret void 932 // 933 // 934 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp 935 // CHECK1-SAME: () #[[ATTR0]] { 936 // CHECK1-NEXT: entry: 937 // CHECK1-NEXT: call void @__cxx_global_var_init() 938 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 939 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 940 // CHECK1-NEXT: ret void 941 // 942 // 943 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 944 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 945 // CHECK3-NEXT: entry: 946 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 947 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 948 // CHECK3-NEXT: ret void 949 // 950 // 951 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 952 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 953 // CHECK3-NEXT: entry: 954 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 955 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 956 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 957 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 958 // CHECK3-NEXT: ret void 959 // 960 // 961 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 962 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 963 // CHECK3-NEXT: entry: 964 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 965 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 966 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 967 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 968 // CHECK3-NEXT: ret void 969 // 970 // 971 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 972 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 973 // CHECK3-NEXT: entry: 974 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 975 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 976 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 977 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 978 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 979 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 980 // CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4 981 // CHECK3-NEXT: ret void 982 // 983 // 984 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 985 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 986 // CHECK3-NEXT: entry: 987 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 988 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 989 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 990 // CHECK3-NEXT: ret void 991 // 992 // 993 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 994 // CHECK3-SAME: () #[[ATTR0]] { 995 // CHECK3-NEXT: entry: 996 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 997 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 998 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 999 // CHECK3-NEXT: ret void 1000 // 1001 // 1002 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1003 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1004 // CHECK3-NEXT: entry: 1005 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1006 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1007 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1008 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1009 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1010 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1011 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1012 // CHECK3-NEXT: ret void 1013 // 1014 // 1015 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1016 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1017 // CHECK3-NEXT: entry: 1018 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 1019 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 1020 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1021 // CHECK3: arraydestroy.body: 1022 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1023 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1024 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1025 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1026 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1027 // CHECK3: arraydestroy.done1: 1028 // CHECK3-NEXT: ret void 1029 // 1030 // 1031 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1032 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1033 // CHECK3-NEXT: entry: 1034 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1035 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1036 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1037 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1038 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1039 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1040 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1041 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1042 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1043 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1044 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 1045 // CHECK3-NEXT: ret void 1046 // 1047 // 1048 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1049 // CHECK3-SAME: () #[[ATTR0]] { 1050 // CHECK3-NEXT: entry: 1051 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1052 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1053 // CHECK3-NEXT: ret void 1054 // 1055 // 1056 // CHECK3-LABEL: define {{[^@]+}}@main 1057 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1058 // CHECK3-NEXT: entry: 1059 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1060 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1061 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1062 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 1063 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 1064 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 1065 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1066 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1067 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1068 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr @t_var, align 4 1069 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 1070 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1071 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 1072 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 1073 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 1074 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1075 // CHECK3-NEXT: store ptr @vec, ptr [[TMP4]], align 4 1076 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1077 // CHECK3-NEXT: store ptr @vec, ptr [[TMP5]], align 4 1078 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1079 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1080 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1081 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 4 1082 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1083 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 4 1084 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1085 // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 1086 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1087 // CHECK3-NEXT: store ptr @s_arr, ptr [[TMP10]], align 4 1088 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1089 // CHECK3-NEXT: store ptr @s_arr, ptr [[TMP11]], align 4 1090 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1091 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 1092 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1093 // CHECK3-NEXT: store ptr @var, ptr [[TMP13]], align 4 1094 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1095 // CHECK3-NEXT: store ptr @var, ptr [[TMP14]], align 4 1096 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1097 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 1098 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1099 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP16]], align 4 1100 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1101 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP17]], align 4 1102 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1103 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 1104 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1105 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1106 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1107 // CHECK3-NEXT: store i32 3, ptr [[TMP21]], align 4 1108 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1109 // CHECK3-NEXT: store i32 5, ptr [[TMP22]], align 4 1110 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1111 // CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4 1112 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1113 // CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4 1114 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1115 // CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 4 1116 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1117 // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 4 1118 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1119 // CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 4 1120 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1121 // CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 4 1122 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1123 // CHECK3-NEXT: store i64 2, ptr [[TMP29]], align 8 1124 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1125 // CHECK3-NEXT: store i64 0, ptr [[TMP30]], align 8 1126 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1127 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 1128 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1129 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 1130 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1131 // CHECK3-NEXT: store i32 0, ptr [[TMP33]], align 4 1132 // CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.region_id, ptr [[KERNEL_ARGS]]) 1133 // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 1134 // CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1135 // CHECK3: omp_offload.failed: 1136 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92(ptr @vec, i32 [[TMP1]], ptr @s_arr, ptr @var, i32 [[TMP3]]) #[[ATTR2]] 1137 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1138 // CHECK3: omp_offload.cont: 1139 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1140 // CHECK3-NEXT: ret i32 [[CALL]] 1141 // 1142 // 1143 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 1144 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 1145 // CHECK3-NEXT: entry: 1146 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1147 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1148 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1149 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1150 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1151 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1152 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1153 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1154 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1155 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1156 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1157 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 1158 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1159 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1160 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1161 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1162 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 1163 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1164 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 1165 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 1166 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 1167 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]]) 1168 // CHECK3-NEXT: ret void 1169 // 1170 // 1171 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.omp_outlined 1172 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 1173 // CHECK3-NEXT: entry: 1174 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1175 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1176 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1177 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1178 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1179 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1180 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1181 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1182 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1183 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1184 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1185 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1186 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1187 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 1188 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 1189 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1190 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1191 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 1192 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1193 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1194 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1195 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1196 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1197 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1198 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1199 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 1200 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1201 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1202 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1203 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1204 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1205 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1206 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1207 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) 1208 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1209 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1210 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 1211 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1212 // CHECK3: omp.arraycpy.body: 1213 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1214 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1215 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1216 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 1217 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1218 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1219 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1220 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 1221 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 1222 // CHECK3: omp.arraycpy.done3: 1223 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 1224 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) 1225 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 1226 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1227 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 1228 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1229 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1230 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 1231 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1232 // CHECK3: cond.true: 1233 // CHECK3-NEXT: br label [[COND_END:%.*]] 1234 // CHECK3: cond.false: 1235 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1236 // CHECK3-NEXT: br label [[COND_END]] 1237 // CHECK3: cond.end: 1238 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1239 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1240 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1241 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 1242 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1243 // CHECK3: omp.inner.for.cond: 1244 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1245 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1246 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1247 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1248 // CHECK3: omp.inner.for.cond.cleanup: 1249 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1250 // CHECK3: omp.inner.for.body: 1251 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1252 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 1253 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1254 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1255 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1256 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 1257 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP13]] 1258 // CHECK3-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 1259 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 1260 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP14]] 1261 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false) 1262 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 1263 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 1264 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 1265 // CHECK3-NEXT: store i32 [[ADD8]], ptr [[SIVAR_ADDR]], align 4 1266 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1267 // CHECK3: omp.body.continue: 1268 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1269 // CHECK3: omp.inner.for.inc: 1270 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1271 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], 1 1272 // CHECK3-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4 1273 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1274 // CHECK3: omp.inner.for.end: 1275 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1276 // CHECK3: omp.loop.exit: 1277 // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1278 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 1279 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) 1280 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 1281 // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1282 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 1283 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1284 // CHECK3: arraydestroy.body: 1285 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1286 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1287 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1288 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 1289 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 1290 // CHECK3: arraydestroy.done11: 1291 // CHECK3-NEXT: ret void 1292 // 1293 // 1294 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev 1295 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1296 // CHECK3-NEXT: entry: 1297 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1298 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1299 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1300 // CHECK3-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 1301 // CHECK3-NEXT: ret void 1302 // 1303 // 1304 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 1305 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1306 // CHECK3-NEXT: entry: 1307 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1308 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1309 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1310 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1311 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1312 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1313 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1314 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1315 // CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 1316 // CHECK3-NEXT: ret void 1317 // 1318 // 1319 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev 1320 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1321 // CHECK3-NEXT: entry: 1322 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1323 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1324 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1325 // CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 1326 // CHECK3-NEXT: ret void 1327 // 1328 // 1329 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1330 // CHECK3-SAME: () #[[ATTR1]] comdat { 1331 // CHECK3-NEXT: entry: 1332 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1333 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1334 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1335 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1336 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1337 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 1338 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1339 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1340 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 1341 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 1342 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 1343 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1344 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1345 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1346 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 1347 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 1348 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 1349 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 1350 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1351 // CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 1352 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 1353 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 1354 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 1355 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 1356 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1357 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 1358 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1359 // CHECK3-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 4 1360 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1361 // CHECK3-NEXT: store ptr [[VEC]], ptr [[TMP5]], align 4 1362 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1363 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1364 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1365 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP7]], align 4 1366 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1367 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP8]], align 4 1368 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1369 // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 1370 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1371 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[TMP10]], align 4 1372 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1373 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[TMP11]], align 4 1374 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1375 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 1376 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1377 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 4 1378 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1379 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 4 1380 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1381 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 1382 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1383 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1384 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1385 // CHECK3-NEXT: store i32 3, ptr [[TMP18]], align 4 1386 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1387 // CHECK3-NEXT: store i32 4, ptr [[TMP19]], align 4 1388 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1389 // CHECK3-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 4 1390 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1391 // CHECK3-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 4 1392 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1393 // CHECK3-NEXT: store ptr @.offload_sizes.3, ptr [[TMP22]], align 4 1394 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1395 // CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP23]], align 4 1396 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1397 // CHECK3-NEXT: store ptr null, ptr [[TMP24]], align 4 1398 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1399 // CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4 1400 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1401 // CHECK3-NEXT: store i64 2, ptr [[TMP26]], align 8 1402 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1403 // CHECK3-NEXT: store i64 0, ptr [[TMP27]], align 8 1404 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1405 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 1406 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1407 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4 1408 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1409 // CHECK3-NEXT: store i32 0, ptr [[TMP30]], align 4 1410 // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 1411 // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1412 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1413 // CHECK3: omp_offload.failed: 1414 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(ptr [[VEC]], i32 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]] 1415 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1416 // CHECK3: omp_offload.cont: 1417 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1418 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1419 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1420 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1421 // CHECK3: arraydestroy.body: 1422 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1423 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1424 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1425 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1426 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1427 // CHECK3: arraydestroy.done2: 1428 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1429 // CHECK3-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 1430 // CHECK3-NEXT: ret i32 [[TMP34]] 1431 // 1432 // 1433 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev 1434 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1435 // CHECK3-NEXT: entry: 1436 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1437 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1438 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1439 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 1440 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 1441 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 1442 // CHECK3-NEXT: store i32 0, ptr [[B]], align 4 1443 // CHECK3-NEXT: ret void 1444 // 1445 // 1446 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 1447 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1448 // CHECK3-NEXT: entry: 1449 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1450 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1451 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1452 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1453 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1454 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1455 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1456 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1457 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1458 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 1459 // CHECK3-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 1460 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 1461 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1462 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 1463 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 1464 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 1465 // CHECK3-NEXT: ret void 1466 // 1467 // 1468 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev 1469 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1470 // CHECK3-NEXT: entry: 1471 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1472 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1473 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1474 // CHECK3-NEXT: ret void 1475 // 1476 // 1477 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1478 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1479 // CHECK3-NEXT: entry: 1480 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1481 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1482 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1483 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1484 // CHECK3-NEXT: ret void 1485 // 1486 // 1487 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1488 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1489 // CHECK3-NEXT: entry: 1490 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1491 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1492 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1493 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1494 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1495 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1496 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1497 // CHECK3-NEXT: ret void 1498 // 1499 // 1500 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1501 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1502 // CHECK3-NEXT: entry: 1503 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1504 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1505 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1506 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1507 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1508 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1509 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1510 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1511 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1512 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1513 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1514 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1515 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1516 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 1517 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1518 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 1519 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1520 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 1521 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) 1522 // CHECK3-NEXT: ret void 1523 // 1524 // 1525 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 1526 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1527 // CHECK3-NEXT: entry: 1528 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1529 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1530 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1531 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1532 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1533 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1534 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1535 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1536 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1537 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1538 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1539 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1540 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1541 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 1542 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 1543 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1544 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1545 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1546 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 1547 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1548 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1549 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1550 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1551 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1552 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1553 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1554 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1555 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1556 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1557 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 1558 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1559 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1560 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1561 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1562 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) 1563 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 1564 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1565 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 1566 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1567 // CHECK3: omp.arraycpy.body: 1568 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1569 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1570 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1571 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 1572 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1573 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1574 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1575 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 1576 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1577 // CHECK3: omp.arraycpy.done4: 1578 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 1579 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1580 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) 1581 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 1582 // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 1583 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1584 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 1585 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1586 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1587 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 1588 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1589 // CHECK3: cond.true: 1590 // CHECK3-NEXT: br label [[COND_END:%.*]] 1591 // CHECK3: cond.false: 1592 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1593 // CHECK3-NEXT: br label [[COND_END]] 1594 // CHECK3: cond.end: 1595 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 1596 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1597 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1598 // CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 1599 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1600 // CHECK3: omp.inner.for.cond: 1601 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1602 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1603 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 1604 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1605 // CHECK3: omp.inner.for.cond.cleanup: 1606 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1607 // CHECK3: omp.inner.for.body: 1608 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1609 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 1610 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1611 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1612 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1613 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 1614 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP14]] 1615 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 1616 // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 4 1617 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 1618 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP16]] 1619 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i32 4, i1 false) 1620 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1621 // CHECK3: omp.body.continue: 1622 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1623 // CHECK3: omp.inner.for.inc: 1624 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1625 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP17]], 1 1626 // CHECK3-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4 1627 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1628 // CHECK3: omp.inner.for.end: 1629 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1630 // CHECK3: omp.loop.exit: 1631 // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1632 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 1633 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) 1634 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1635 // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 1636 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 1637 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1638 // CHECK3: arraydestroy.body: 1639 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1640 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1641 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1642 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 1643 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 1644 // CHECK3: arraydestroy.done12: 1645 // CHECK3-NEXT: ret void 1646 // 1647 // 1648 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1649 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1650 // CHECK3-NEXT: entry: 1651 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1652 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1653 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1654 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1655 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1656 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1657 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1658 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1659 // CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 1660 // CHECK3-NEXT: ret void 1661 // 1662 // 1663 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1664 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1665 // CHECK3-NEXT: entry: 1666 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1667 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1668 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1669 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1670 // CHECK3-NEXT: ret void 1671 // 1672 // 1673 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1674 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1675 // CHECK3-NEXT: entry: 1676 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1677 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1678 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1679 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1680 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1681 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1682 // CHECK3-NEXT: ret void 1683 // 1684 // 1685 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1686 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1687 // CHECK3-NEXT: entry: 1688 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1689 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1690 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1691 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1692 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1693 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1694 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1695 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1696 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1697 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1698 // CHECK3-NEXT: ret void 1699 // 1700 // 1701 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1702 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1703 // CHECK3-NEXT: entry: 1704 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1705 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1706 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1707 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1708 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1709 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1710 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1711 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1712 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1713 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 1714 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 1715 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 1716 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1717 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1718 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1719 // CHECK3-NEXT: ret void 1720 // 1721 // 1722 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1723 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1724 // CHECK3-NEXT: entry: 1725 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1726 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1727 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1728 // CHECK3-NEXT: ret void 1729 // 1730 // 1731 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp 1732 // CHECK3-SAME: () #[[ATTR0]] { 1733 // CHECK3-NEXT: entry: 1734 // CHECK3-NEXT: call void @__cxx_global_var_init() 1735 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1736 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1737 // CHECK3-NEXT: ret void 1738 // 1739 // 1740 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 1741 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 1742 // CHECK9-NEXT: entry: 1743 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 1744 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 1745 // CHECK9-NEXT: ret void 1746 // 1747 // 1748 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1749 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 1750 // CHECK9-NEXT: entry: 1751 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1752 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1753 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1754 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1755 // CHECK9-NEXT: ret void 1756 // 1757 // 1758 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1759 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1760 // CHECK9-NEXT: entry: 1761 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1762 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1763 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1764 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1765 // CHECK9-NEXT: ret void 1766 // 1767 // 1768 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1769 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1770 // CHECK9-NEXT: entry: 1771 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1772 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1773 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1774 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1775 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1776 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1777 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 1778 // CHECK9-NEXT: ret void 1779 // 1780 // 1781 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1782 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1783 // CHECK9-NEXT: entry: 1784 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1785 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1786 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1787 // CHECK9-NEXT: ret void 1788 // 1789 // 1790 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1791 // CHECK9-SAME: () #[[ATTR0]] { 1792 // CHECK9-NEXT: entry: 1793 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 1794 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 1795 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 1796 // CHECK9-NEXT: ret void 1797 // 1798 // 1799 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1800 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1801 // CHECK9-NEXT: entry: 1802 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1803 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1804 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1805 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1806 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1807 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1808 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1809 // CHECK9-NEXT: ret void 1810 // 1811 // 1812 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1813 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1814 // CHECK9-NEXT: entry: 1815 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1816 // CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1817 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1818 // CHECK9: arraydestroy.body: 1819 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1820 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1821 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1822 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1823 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1824 // CHECK9: arraydestroy.done1: 1825 // CHECK9-NEXT: ret void 1826 // 1827 // 1828 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1829 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1830 // CHECK9-NEXT: entry: 1831 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1832 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1833 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1834 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1835 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1836 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1837 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1838 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1839 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1840 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1841 // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 1842 // CHECK9-NEXT: ret void 1843 // 1844 // 1845 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1846 // CHECK9-SAME: () #[[ATTR0]] { 1847 // CHECK9-NEXT: entry: 1848 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1849 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1850 // CHECK9-NEXT: ret void 1851 // 1852 // 1853 // CHECK9-LABEL: define {{[^@]+}}@main 1854 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 1855 // CHECK9-NEXT: entry: 1856 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1857 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1858 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 1859 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 1860 // CHECK9-NEXT: ret i32 0 1861 // 1862 // 1863 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 1864 // CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 1865 // CHECK9-NEXT: entry: 1866 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 1867 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 1868 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 1869 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1870 // CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 1871 // CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 1872 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 1873 // CHECK9-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 1874 // CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 1875 // CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 1876 // CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 1877 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 4 1878 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4 1879 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8 1880 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 1881 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 4 1882 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[G1_CASTED]], align 4 1883 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 8 1884 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 1885 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 1886 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 1887 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined, i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) 1888 // CHECK9-NEXT: ret void 1889 // 1890 // 1891 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined 1892 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 1893 // CHECK9-NEXT: entry: 1894 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1895 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1896 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 1897 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 1898 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 1899 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1900 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1901 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1902 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1903 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1904 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1905 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1906 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1907 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1908 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1909 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1910 // CHECK9-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 1911 // CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 1912 // CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 1913 // CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 1914 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1915 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1916 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1917 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1918 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1919 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1920 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1921 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1922 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1923 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1924 // CHECK9: cond.true: 1925 // CHECK9-NEXT: br label [[COND_END:%.*]] 1926 // CHECK9: cond.false: 1927 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1928 // CHECK9-NEXT: br label [[COND_END]] 1929 // CHECK9: cond.end: 1930 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1931 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1932 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1933 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1934 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1935 // CHECK9: omp.inner.for.cond: 1936 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1937 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1938 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1939 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1940 // CHECK9: omp.inner.for.body: 1941 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1942 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1943 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1944 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1945 // CHECK9-NEXT: store i32 1, ptr [[G_ADDR]], align 4 1946 // CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8 1947 // CHECK9-NEXT: store volatile i32 1, ptr [[TMP8]], align 4 1948 // CHECK9-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 1949 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 1950 // CHECK9-NEXT: store ptr [[G_ADDR]], ptr [[TMP9]], align 8 1951 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 1952 // CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP]], align 8 1953 // CHECK9-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8 1954 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 1955 // CHECK9-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP12]], align 8 1956 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 1957 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1958 // CHECK9: omp.body.continue: 1959 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1960 // CHECK9: omp.inner.for.inc: 1961 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1962 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], 1 1963 // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 1964 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 1965 // CHECK9: omp.inner.for.end: 1966 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1967 // CHECK9: omp.loop.exit: 1968 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1969 // CHECK9-NEXT: ret void 1970 // 1971 // 1972 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp 1973 // CHECK9-SAME: () #[[ATTR0]] { 1974 // CHECK9-NEXT: entry: 1975 // CHECK9-NEXT: call void @__cxx_global_var_init() 1976 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 1977 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 1978 // CHECK9-NEXT: ret void 1979 // 1980