1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 9 10 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 17 // Test target codegen - host bc file has to be created first. 18 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 19 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 20 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 21 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 22 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 23 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 24 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 25 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 26 27 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 28 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 29 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 30 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 31 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 32 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 33 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 34 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 35 36 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 37 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 38 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 39 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 40 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 41 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 42 43 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 44 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 45 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 46 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 47 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 48 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 49 50 // Test target codegen - host bc file has to be created first. 51 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 52 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 53 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 54 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 55 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 56 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 57 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 58 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 59 60 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 61 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 62 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 63 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 64 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 65 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 66 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 67 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 68 69 // expected-no-diagnostics 70 #ifndef HEADER 71 #define HEADER 72 73 74 75 76 // We have 8 target regions, but only 6 that actually will generate offloading 77 // code and have mapped arguments, and only 4 have all-constant map sizes. 78 79 80 81 // Check target registration is registered as a Ctor. 82 83 84 template<typename tx, typename ty> 85 struct TT{ 86 tx X; 87 ty Y; 88 }; 89 90 int global; 91 92 int foo(int n) { 93 int a = 0; 94 short aa = 0; 95 float b[10]; 96 float bn[n]; 97 double c[5][10]; 98 double cn[5][n]; 99 TT<long long, char> d; 100 101 #pragma omp target teams num_teams(a) thread_limit(a) firstprivate(aa) nowait 102 { 103 } 104 105 #pragma omp target teams if(target: 0) 106 { 107 a += 1; 108 } 109 110 111 #pragma omp target teams if(target: 1) 112 { 113 aa += 1; 114 } 115 116 117 118 #pragma omp target teams if(target: n>10) 119 { 120 a += 1; 121 aa += 1; 122 } 123 124 #pragma omp target teams ompx_bare num_teams(1) thread_limit(1) 125 { 126 a += 1; 127 aa += 1; 128 } 129 130 #pragma omp target teams ompx_bare num_teams(1, 2) thread_limit(1, 2) 131 { 132 a += 1; 133 aa += 1; 134 } 135 136 #pragma omp target teams ompx_bare num_teams(1, 2, 3) thread_limit(1, 2, 3) 137 { 138 a += 1; 139 aa += 1; 140 } 141 142 // We capture 3 VLA sizes in this target region 143 144 145 146 147 148 // The names below are not necessarily consistent with the names used for the 149 // addresses above as some are repeated. 150 151 152 153 154 155 156 157 158 159 160 #pragma omp target teams if(target: n>20) 161 { 162 a += 1; 163 b[2] += 1.0; 164 bn[3] += 1.0; 165 c[1][2] += 1.0; 166 cn[1][3] += 1.0; 167 d.X += 1; 168 d.Y += 1; 169 } 170 171 const int nn = 0; 172 #pragma omp target teams shared(nn) 173 #pragma omp parallel firstprivate(nn) 174 (void)nn; 175 #pragma omp target teams firstprivate(nn) 176 #pragma omp parallel shared(nn) 177 (void)nn; 178 return a; 179 } 180 181 // Check that the offloading functions are emitted and that the arguments are 182 // correct and loaded correctly for the target regions in foo(). 183 184 185 186 // Create stack storage and store argument in there. 187 188 // Create stack storage and store argument in there. 189 190 // Create stack storage and store argument in there. 191 192 // Create local storage for each capture. 193 194 195 196 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 197 198 199 void bazzzz(int n, int f[n]) { 200 #pragma omp target teams private(f) 201 ; 202 } 203 204 template<typename tx> 205 tx ftemplate(int n) { 206 tx a = 0; 207 short aa = 0; 208 tx b[10]; 209 210 #pragma omp target teams if(target: n>40) 211 { 212 a += 1; 213 aa += 1; 214 b[2] += 1; 215 } 216 217 return a; 218 } 219 220 static 221 int fstatic(int n) { 222 int a = 0; 223 short aa = 0; 224 char aaa = 0; 225 int b[10]; 226 227 #pragma omp target teams if(target: n>50) 228 { 229 a += 1; 230 aa += 1; 231 aaa += 1; 232 b[2] += 1; 233 } 234 235 return a; 236 } 237 238 struct S1 { 239 double a; 240 241 int r1(int n){ 242 int b = n+1; 243 short int c[2][n]; 244 245 #pragma omp target teams if(target: n>60) 246 { 247 this->a = (double)b + 1.5; 248 c[1][1] = ++a; 249 } 250 251 return c[1][1] + (int)b; 252 } 253 }; 254 255 int bar(int n){ 256 int a = 0; 257 258 a += foo(n); 259 260 S1 S; 261 a += S.r1(n); 262 263 a += fstatic(n); 264 265 a += ftemplate<int>(n); 266 267 return a; 268 } 269 270 271 272 // We capture 2 VLA sizes in this target region 273 274 275 // The names below are not necessarily consistent with the names used for the 276 // addresses above as some are repeated. 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 // Check that the offloading functions are emitted and that the arguments are 298 // correct and loaded correctly for the target regions of the callees of bar(). 299 300 // Create local storage for each capture. 301 // Store captures in the context. 302 303 304 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 305 306 307 // Create local storage for each capture. 308 // Store captures in the context. 309 310 311 312 313 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 314 315 // Create local storage for each capture. 316 // Store captures in the context. 317 318 319 320 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 321 322 #endif 323 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 324 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 325 // CHECK1-NEXT: entry: 326 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 327 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 328 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 329 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 330 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 331 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 332 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 333 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 334 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 335 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 336 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 337 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 338 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 339 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i64, align 8 340 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 341 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 342 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 343 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 344 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 345 // CHECK1-NEXT: [[AA_CASTED4:%.*]] = alloca i64, align 8 346 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 8 347 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 8 348 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 8 349 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 350 // CHECK1-NEXT: [[A_CASTED8:%.*]] = alloca i64, align 8 351 // CHECK1-NEXT: [[AA_CASTED9:%.*]] = alloca i64, align 8 352 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 8 353 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 8 354 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 8 355 // CHECK1-NEXT: [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 356 // CHECK1-NEXT: [[A_CASTED16:%.*]] = alloca i64, align 8 357 // CHECK1-NEXT: [[AA_CASTED17:%.*]] = alloca i64, align 8 358 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [2 x ptr], align 8 359 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS19:%.*]] = alloca [2 x ptr], align 8 360 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [2 x ptr], align 8 361 // CHECK1-NEXT: [[KERNEL_ARGS21:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 362 // CHECK1-NEXT: [[A_CASTED24:%.*]] = alloca i64, align 8 363 // CHECK1-NEXT: [[AA_CASTED25:%.*]] = alloca i64, align 8 364 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS26:%.*]] = alloca [2 x ptr], align 8 365 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS27:%.*]] = alloca [2 x ptr], align 8 366 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS28:%.*]] = alloca [2 x ptr], align 8 367 // CHECK1-NEXT: [[KERNEL_ARGS29:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 368 // CHECK1-NEXT: [[A_CASTED32:%.*]] = alloca i64, align 8 369 // CHECK1-NEXT: [[AA_CASTED33:%.*]] = alloca i64, align 8 370 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS34:%.*]] = alloca [2 x ptr], align 8 371 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS35:%.*]] = alloca [2 x ptr], align 8 372 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS36:%.*]] = alloca [2 x ptr], align 8 373 // CHECK1-NEXT: [[KERNEL_ARGS37:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 374 // CHECK1-NEXT: [[A_CASTED40:%.*]] = alloca i64, align 8 375 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS43:%.*]] = alloca [9 x ptr], align 8 376 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS44:%.*]] = alloca [9 x ptr], align 8 377 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS45:%.*]] = alloca [9 x ptr], align 8 378 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 379 // CHECK1-NEXT: [[KERNEL_ARGS46:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 380 // CHECK1-NEXT: [[NN:%.*]] = alloca i32, align 4 381 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 382 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS51:%.*]] = alloca [1 x ptr], align 8 383 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS52:%.*]] = alloca [1 x ptr], align 8 384 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS53:%.*]] = alloca [1 x ptr], align 8 385 // CHECK1-NEXT: [[KERNEL_ARGS54:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 386 // CHECK1-NEXT: [[NN_CASTED57:%.*]] = alloca i64, align 8 387 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS58:%.*]] = alloca [1 x ptr], align 8 388 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS59:%.*]] = alloca [1 x ptr], align 8 389 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS60:%.*]] = alloca [1 x ptr], align 8 390 // CHECK1-NEXT: [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 391 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) 392 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 393 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 394 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 395 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 396 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 397 // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0() 398 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 399 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 400 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 401 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 402 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 403 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 404 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 405 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 406 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 407 // CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4 408 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 409 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_2]], align 4 410 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2 411 // CHECK1-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2 412 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[AA_CASTED]], align 8 413 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 414 // CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 415 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 416 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 417 // CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4 418 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 8 419 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 420 // CHECK1-NEXT: store i64 [[TMP10]], ptr [[TMP15]], align 8 421 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 422 // CHECK1-NEXT: store i64 [[TMP10]], ptr [[TMP16]], align 8 423 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 424 // CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8 425 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 426 // CHECK1-NEXT: store i64 [[TMP12]], ptr [[TMP18]], align 8 427 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 428 // CHECK1-NEXT: store i64 [[TMP12]], ptr [[TMP19]], align 8 429 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 430 // CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8 431 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 432 // CHECK1-NEXT: store i64 [[TMP14]], ptr [[TMP21]], align 8 433 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 434 // CHECK1-NEXT: store i64 [[TMP14]], ptr [[TMP22]], align 8 435 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 436 // CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8 437 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 438 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 439 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 440 // CHECK1-NEXT: [[TMP27:%.*]] = load i16, ptr [[AA]], align 2 441 // CHECK1-NEXT: store i16 [[TMP27]], ptr [[TMP26]], align 4 442 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1 443 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 444 // CHECK1-NEXT: store i32 [[TMP29]], ptr [[TMP28]], align 4 445 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2 446 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 447 // CHECK1-NEXT: store i32 [[TMP31]], ptr [[TMP30]], align 4 448 // CHECK1-NEXT: [[TMP32:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, ptr @.omp_task_entry., i64 -1) 449 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP32]], i32 0, i32 0 450 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP33]], i32 0, i32 0 451 // CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[TMP34]], align 8 452 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP35]], ptr align 4 [[AGG_CAPTURED]], i64 12, i1 false) 453 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP32]], i32 0, i32 1 454 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP36]], i32 0, i32 0 455 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP37]], ptr align 8 [[TMP24]], i64 24, i1 false) 456 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 1 457 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP38]], ptr align 8 [[TMP25]], i64 24, i1 false) 458 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 2 459 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP39]], ptr align 8 @.offload_sizes, i64 24, i1 false) 460 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 3 461 // CHECK1-NEXT: [[TMP41:%.*]] = load i16, ptr [[AA]], align 2 462 // CHECK1-NEXT: store i16 [[TMP41]], ptr [[TMP40]], align 8 463 // CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP32]]) 464 // CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[A]], align 4 465 // CHECK1-NEXT: store i32 [[TMP43]], ptr [[A_CASTED]], align 4 466 // CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[A_CASTED]], align 8 467 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP44]]) #[[ATTR3:[0-9]+]] 468 // CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[AA]], align 2 469 // CHECK1-NEXT: store i16 [[TMP45]], ptr [[AA_CASTED4]], align 2 470 // CHECK1-NEXT: [[TMP46:%.*]] = load i64, ptr [[AA_CASTED4]], align 8 471 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 472 // CHECK1-NEXT: store i64 [[TMP46]], ptr [[TMP47]], align 8 473 // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 474 // CHECK1-NEXT: store i64 [[TMP46]], ptr [[TMP48]], align 8 475 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 476 // CHECK1-NEXT: store ptr null, ptr [[TMP49]], align 8 477 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 478 // CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 479 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 480 // CHECK1-NEXT: store i32 3, ptr [[TMP52]], align 4 481 // CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 482 // CHECK1-NEXT: store i32 1, ptr [[TMP53]], align 4 483 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 484 // CHECK1-NEXT: store ptr [[TMP50]], ptr [[TMP54]], align 8 485 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 486 // CHECK1-NEXT: store ptr [[TMP51]], ptr [[TMP55]], align 8 487 // CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 488 // CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP56]], align 8 489 // CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 490 // CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP57]], align 8 491 // CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 492 // CHECK1-NEXT: store ptr null, ptr [[TMP58]], align 8 493 // CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 494 // CHECK1-NEXT: store ptr null, ptr [[TMP59]], align 8 495 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 496 // CHECK1-NEXT: store i64 0, ptr [[TMP60]], align 8 497 // CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 498 // CHECK1-NEXT: store i64 0, ptr [[TMP61]], align 8 499 // CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 500 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP62]], align 4 501 // CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 502 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP63]], align 4 503 // CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 504 // CHECK1-NEXT: store i32 0, ptr [[TMP64]], align 4 505 // CHECK1-NEXT: [[TMP65:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, ptr [[KERNEL_ARGS]]) 506 // CHECK1-NEXT: [[TMP66:%.*]] = icmp ne i32 [[TMP65]], 0 507 // CHECK1-NEXT: br i1 [[TMP66]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 508 // CHECK1: omp_offload.failed: 509 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP46]]) #[[ATTR3]] 510 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 511 // CHECK1: omp_offload.cont: 512 // CHECK1-NEXT: [[TMP67:%.*]] = load i32, ptr [[A]], align 4 513 // CHECK1-NEXT: store i32 [[TMP67]], ptr [[A_CASTED8]], align 4 514 // CHECK1-NEXT: [[TMP68:%.*]] = load i64, ptr [[A_CASTED8]], align 8 515 // CHECK1-NEXT: [[TMP69:%.*]] = load i16, ptr [[AA]], align 2 516 // CHECK1-NEXT: store i16 [[TMP69]], ptr [[AA_CASTED9]], align 2 517 // CHECK1-NEXT: [[TMP70:%.*]] = load i64, ptr [[AA_CASTED9]], align 8 518 // CHECK1-NEXT: [[TMP71:%.*]] = load i32, ptr [[N_ADDR]], align 4 519 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP71]], 10 520 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 521 // CHECK1: omp_if.then: 522 // CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 523 // CHECK1-NEXT: store i64 [[TMP68]], ptr [[TMP72]], align 8 524 // CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 525 // CHECK1-NEXT: store i64 [[TMP68]], ptr [[TMP73]], align 8 526 // CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 527 // CHECK1-NEXT: store ptr null, ptr [[TMP74]], align 8 528 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 529 // CHECK1-NEXT: store i64 [[TMP70]], ptr [[TMP75]], align 8 530 // CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 531 // CHECK1-NEXT: store i64 [[TMP70]], ptr [[TMP76]], align 8 532 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 533 // CHECK1-NEXT: store ptr null, ptr [[TMP77]], align 8 534 // CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 535 // CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 536 // CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 0 537 // CHECK1-NEXT: store i32 3, ptr [[TMP80]], align 4 538 // CHECK1-NEXT: [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 1 539 // CHECK1-NEXT: store i32 2, ptr [[TMP81]], align 4 540 // CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 2 541 // CHECK1-NEXT: store ptr [[TMP78]], ptr [[TMP82]], align 8 542 // CHECK1-NEXT: [[TMP83:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 3 543 // CHECK1-NEXT: store ptr [[TMP79]], ptr [[TMP83]], align 8 544 // CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 4 545 // CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP84]], align 8 546 // CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 5 547 // CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP85]], align 8 548 // CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 6 549 // CHECK1-NEXT: store ptr null, ptr [[TMP86]], align 8 550 // CHECK1-NEXT: [[TMP87:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 7 551 // CHECK1-NEXT: store ptr null, ptr [[TMP87]], align 8 552 // CHECK1-NEXT: [[TMP88:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 8 553 // CHECK1-NEXT: store i64 0, ptr [[TMP88]], align 8 554 // CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 9 555 // CHECK1-NEXT: store i64 0, ptr [[TMP89]], align 8 556 // CHECK1-NEXT: [[TMP90:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 10 557 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP90]], align 4 558 // CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 11 559 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP91]], align 4 560 // CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 12 561 // CHECK1-NEXT: store i32 0, ptr [[TMP92]], align 4 562 // CHECK1-NEXT: [[TMP93:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, ptr [[KERNEL_ARGS13]]) 563 // CHECK1-NEXT: [[TMP94:%.*]] = icmp ne i32 [[TMP93]], 0 564 // CHECK1-NEXT: br i1 [[TMP94]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]] 565 // CHECK1: omp_offload.failed14: 566 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]] 567 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT15]] 568 // CHECK1: omp_offload.cont15: 569 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 570 // CHECK1: omp_if.else: 571 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]] 572 // CHECK1-NEXT: br label [[OMP_IF_END]] 573 // CHECK1: omp_if.end: 574 // CHECK1-NEXT: [[TMP95:%.*]] = load i32, ptr [[A]], align 4 575 // CHECK1-NEXT: store i32 [[TMP95]], ptr [[A_CASTED16]], align 4 576 // CHECK1-NEXT: [[TMP96:%.*]] = load i64, ptr [[A_CASTED16]], align 8 577 // CHECK1-NEXT: [[TMP97:%.*]] = load i16, ptr [[AA]], align 2 578 // CHECK1-NEXT: store i16 [[TMP97]], ptr [[AA_CASTED17]], align 2 579 // CHECK1-NEXT: [[TMP98:%.*]] = load i64, ptr [[AA_CASTED17]], align 8 580 // CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 581 // CHECK1-NEXT: store i64 [[TMP96]], ptr [[TMP99]], align 8 582 // CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 583 // CHECK1-NEXT: store i64 [[TMP96]], ptr [[TMP100]], align 8 584 // CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS20]], i64 0, i64 0 585 // CHECK1-NEXT: store ptr null, ptr [[TMP101]], align 8 586 // CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 1 587 // CHECK1-NEXT: store i64 [[TMP98]], ptr [[TMP102]], align 8 588 // CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS19]], i32 0, i32 1 589 // CHECK1-NEXT: store i64 [[TMP98]], ptr [[TMP103]], align 8 590 // CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS20]], i64 0, i64 1 591 // CHECK1-NEXT: store ptr null, ptr [[TMP104]], align 8 592 // CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 593 // CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 594 // CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 0 595 // CHECK1-NEXT: store i32 3, ptr [[TMP107]], align 4 596 // CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 1 597 // CHECK1-NEXT: store i32 2, ptr [[TMP108]], align 4 598 // CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 2 599 // CHECK1-NEXT: store ptr [[TMP105]], ptr [[TMP109]], align 8 600 // CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 3 601 // CHECK1-NEXT: store ptr [[TMP106]], ptr [[TMP110]], align 8 602 // CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 4 603 // CHECK1-NEXT: store ptr @.offload_sizes.5, ptr [[TMP111]], align 8 604 // CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 5 605 // CHECK1-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP112]], align 8 606 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 6 607 // CHECK1-NEXT: store ptr null, ptr [[TMP113]], align 8 608 // CHECK1-NEXT: [[TMP114:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 7 609 // CHECK1-NEXT: store ptr null, ptr [[TMP114]], align 8 610 // CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 8 611 // CHECK1-NEXT: store i64 0, ptr [[TMP115]], align 8 612 // CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 9 613 // CHECK1-NEXT: store i64 0, ptr [[TMP116]], align 8 614 // CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 10 615 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP117]], align 4 616 // CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 11 617 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP118]], align 4 618 // CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 12 619 // CHECK1-NEXT: store i32 0, ptr [[TMP119]], align 4 620 // CHECK1-NEXT: [[TMP120:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.region_id, ptr [[KERNEL_ARGS21]]) 621 // CHECK1-NEXT: [[TMP121:%.*]] = icmp ne i32 [[TMP120]], 0 622 // CHECK1-NEXT: br i1 [[TMP121]], label [[OMP_OFFLOAD_FAILED22:%.*]], label [[OMP_OFFLOAD_CONT23:%.*]] 623 // CHECK1: omp_offload.failed22: 624 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124(i64 [[TMP96]], i64 [[TMP98]]) #[[ATTR3]] 625 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT23]] 626 // CHECK1: omp_offload.cont23: 627 // CHECK1-NEXT: [[TMP122:%.*]] = load i32, ptr [[A]], align 4 628 // CHECK1-NEXT: store i32 [[TMP122]], ptr [[A_CASTED24]], align 4 629 // CHECK1-NEXT: [[TMP123:%.*]] = load i64, ptr [[A_CASTED24]], align 8 630 // CHECK1-NEXT: [[TMP124:%.*]] = load i16, ptr [[AA]], align 2 631 // CHECK1-NEXT: store i16 [[TMP124]], ptr [[AA_CASTED25]], align 2 632 // CHECK1-NEXT: [[TMP125:%.*]] = load i64, ptr [[AA_CASTED25]], align 8 633 // CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0 634 // CHECK1-NEXT: store i64 [[TMP123]], ptr [[TMP126]], align 8 635 // CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS27]], i32 0, i32 0 636 // CHECK1-NEXT: store i64 [[TMP123]], ptr [[TMP127]], align 8 637 // CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 0 638 // CHECK1-NEXT: store ptr null, ptr [[TMP128]], align 8 639 // CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 1 640 // CHECK1-NEXT: store i64 [[TMP125]], ptr [[TMP129]], align 8 641 // CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS27]], i32 0, i32 1 642 // CHECK1-NEXT: store i64 [[TMP125]], ptr [[TMP130]], align 8 643 // CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 1 644 // CHECK1-NEXT: store ptr null, ptr [[TMP131]], align 8 645 // CHECK1-NEXT: [[TMP132:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0 646 // CHECK1-NEXT: [[TMP133:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS27]], i32 0, i32 0 647 // CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 0 648 // CHECK1-NEXT: store i32 3, ptr [[TMP134]], align 4 649 // CHECK1-NEXT: [[TMP135:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 1 650 // CHECK1-NEXT: store i32 2, ptr [[TMP135]], align 4 651 // CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 2 652 // CHECK1-NEXT: store ptr [[TMP132]], ptr [[TMP136]], align 8 653 // CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 3 654 // CHECK1-NEXT: store ptr [[TMP133]], ptr [[TMP137]], align 8 655 // CHECK1-NEXT: [[TMP138:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 4 656 // CHECK1-NEXT: store ptr @.offload_sizes.7, ptr [[TMP138]], align 8 657 // CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 5 658 // CHECK1-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP139]], align 8 659 // CHECK1-NEXT: [[TMP140:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 6 660 // CHECK1-NEXT: store ptr null, ptr [[TMP140]], align 8 661 // CHECK1-NEXT: [[TMP141:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 7 662 // CHECK1-NEXT: store ptr null, ptr [[TMP141]], align 8 663 // CHECK1-NEXT: [[TMP142:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 8 664 // CHECK1-NEXT: store i64 0, ptr [[TMP142]], align 8 665 // CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 9 666 // CHECK1-NEXT: store i64 0, ptr [[TMP143]], align 8 667 // CHECK1-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 10 668 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 2, i32 0], ptr [[TMP144]], align 4 669 // CHECK1-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 11 670 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 2, i32 0], ptr [[TMP145]], align 4 671 // CHECK1-NEXT: [[TMP146:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 12 672 // CHECK1-NEXT: store i32 0, ptr [[TMP146]], align 4 673 // CHECK1-NEXT: [[TMP147:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.region_id, ptr [[KERNEL_ARGS29]]) 674 // CHECK1-NEXT: [[TMP148:%.*]] = icmp ne i32 [[TMP147]], 0 675 // CHECK1-NEXT: br i1 [[TMP148]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] 676 // CHECK1: omp_offload.failed30: 677 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130(i64 [[TMP123]], i64 [[TMP125]]) #[[ATTR3]] 678 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT31]] 679 // CHECK1: omp_offload.cont31: 680 // CHECK1-NEXT: [[TMP149:%.*]] = load i32, ptr [[A]], align 4 681 // CHECK1-NEXT: store i32 [[TMP149]], ptr [[A_CASTED32]], align 4 682 // CHECK1-NEXT: [[TMP150:%.*]] = load i64, ptr [[A_CASTED32]], align 8 683 // CHECK1-NEXT: [[TMP151:%.*]] = load i16, ptr [[AA]], align 2 684 // CHECK1-NEXT: store i16 [[TMP151]], ptr [[AA_CASTED33]], align 2 685 // CHECK1-NEXT: [[TMP152:%.*]] = load i64, ptr [[AA_CASTED33]], align 8 686 // CHECK1-NEXT: [[TMP153:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 687 // CHECK1-NEXT: store i64 [[TMP150]], ptr [[TMP153]], align 8 688 // CHECK1-NEXT: [[TMP154:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 689 // CHECK1-NEXT: store i64 [[TMP150]], ptr [[TMP154]], align 8 690 // CHECK1-NEXT: [[TMP155:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 0 691 // CHECK1-NEXT: store ptr null, ptr [[TMP155]], align 8 692 // CHECK1-NEXT: [[TMP156:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 1 693 // CHECK1-NEXT: store i64 [[TMP152]], ptr [[TMP156]], align 8 694 // CHECK1-NEXT: [[TMP157:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS35]], i32 0, i32 1 695 // CHECK1-NEXT: store i64 [[TMP152]], ptr [[TMP157]], align 8 696 // CHECK1-NEXT: [[TMP158:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 1 697 // CHECK1-NEXT: store ptr null, ptr [[TMP158]], align 8 698 // CHECK1-NEXT: [[TMP159:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 699 // CHECK1-NEXT: [[TMP160:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 700 // CHECK1-NEXT: [[TMP161:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 0 701 // CHECK1-NEXT: store i32 3, ptr [[TMP161]], align 4 702 // CHECK1-NEXT: [[TMP162:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 1 703 // CHECK1-NEXT: store i32 2, ptr [[TMP162]], align 4 704 // CHECK1-NEXT: [[TMP163:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 2 705 // CHECK1-NEXT: store ptr [[TMP159]], ptr [[TMP163]], align 8 706 // CHECK1-NEXT: [[TMP164:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 3 707 // CHECK1-NEXT: store ptr [[TMP160]], ptr [[TMP164]], align 8 708 // CHECK1-NEXT: [[TMP165:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 4 709 // CHECK1-NEXT: store ptr @.offload_sizes.9, ptr [[TMP165]], align 8 710 // CHECK1-NEXT: [[TMP166:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 5 711 // CHECK1-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP166]], align 8 712 // CHECK1-NEXT: [[TMP167:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 6 713 // CHECK1-NEXT: store ptr null, ptr [[TMP167]], align 8 714 // CHECK1-NEXT: [[TMP168:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 7 715 // CHECK1-NEXT: store ptr null, ptr [[TMP168]], align 8 716 // CHECK1-NEXT: [[TMP169:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 8 717 // CHECK1-NEXT: store i64 0, ptr [[TMP169]], align 8 718 // CHECK1-NEXT: [[TMP170:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 9 719 // CHECK1-NEXT: store i64 0, ptr [[TMP170]], align 8 720 // CHECK1-NEXT: [[TMP171:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 10 721 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 2, i32 3], ptr [[TMP171]], align 4 722 // CHECK1-NEXT: [[TMP172:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 11 723 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 2, i32 3], ptr [[TMP172]], align 4 724 // CHECK1-NEXT: [[TMP173:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 12 725 // CHECK1-NEXT: store i32 0, ptr [[TMP173]], align 4 726 // CHECK1-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.region_id, ptr [[KERNEL_ARGS37]]) 727 // CHECK1-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0 728 // CHECK1-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED38:%.*]], label [[OMP_OFFLOAD_CONT39:%.*]] 729 // CHECK1: omp_offload.failed38: 730 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP150]], i64 [[TMP152]]) #[[ATTR3]] 731 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT39]] 732 // CHECK1: omp_offload.cont39: 733 // CHECK1-NEXT: [[TMP176:%.*]] = load i32, ptr [[A]], align 4 734 // CHECK1-NEXT: store i32 [[TMP176]], ptr [[A_CASTED40]], align 4 735 // CHECK1-NEXT: [[TMP177:%.*]] = load i64, ptr [[A_CASTED40]], align 8 736 // CHECK1-NEXT: [[TMP178:%.*]] = load i32, ptr [[N_ADDR]], align 4 737 // CHECK1-NEXT: [[CMP41:%.*]] = icmp sgt i32 [[TMP178]], 20 738 // CHECK1-NEXT: br i1 [[CMP41]], label [[OMP_IF_THEN42:%.*]], label [[OMP_IF_ELSE49:%.*]] 739 // CHECK1: omp_if.then42: 740 // CHECK1-NEXT: [[TMP179:%.*]] = mul nuw i64 [[TMP2]], 4 741 // CHECK1-NEXT: [[TMP180:%.*]] = mul nuw i64 5, [[TMP5]] 742 // CHECK1-NEXT: [[TMP181:%.*]] = mul nuw i64 [[TMP180]], 8 743 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.11, i64 72, i1 false) 744 // CHECK1-NEXT: [[TMP182:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 0 745 // CHECK1-NEXT: store i64 [[TMP177]], ptr [[TMP182]], align 8 746 // CHECK1-NEXT: [[TMP183:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 0 747 // CHECK1-NEXT: store i64 [[TMP177]], ptr [[TMP183]], align 8 748 // CHECK1-NEXT: [[TMP184:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i64 0, i64 0 749 // CHECK1-NEXT: store ptr null, ptr [[TMP184]], align 8 750 // CHECK1-NEXT: [[TMP185:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 1 751 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP185]], align 8 752 // CHECK1-NEXT: [[TMP186:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 1 753 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP186]], align 8 754 // CHECK1-NEXT: [[TMP187:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i64 0, i64 1 755 // CHECK1-NEXT: store ptr null, ptr [[TMP187]], align 8 756 // CHECK1-NEXT: [[TMP188:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 2 757 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP188]], align 8 758 // CHECK1-NEXT: [[TMP189:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 2 759 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP189]], align 8 760 // CHECK1-NEXT: [[TMP190:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i64 0, i64 2 761 // CHECK1-NEXT: store ptr null, ptr [[TMP190]], align 8 762 // CHECK1-NEXT: [[TMP191:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 3 763 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP191]], align 8 764 // CHECK1-NEXT: [[TMP192:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 3 765 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP192]], align 8 766 // CHECK1-NEXT: [[TMP193:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 767 // CHECK1-NEXT: store i64 [[TMP179]], ptr [[TMP193]], align 8 768 // CHECK1-NEXT: [[TMP194:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i64 0, i64 3 769 // CHECK1-NEXT: store ptr null, ptr [[TMP194]], align 8 770 // CHECK1-NEXT: [[TMP195:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 4 771 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP195]], align 8 772 // CHECK1-NEXT: [[TMP196:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 4 773 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP196]], align 8 774 // CHECK1-NEXT: [[TMP197:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i64 0, i64 4 775 // CHECK1-NEXT: store ptr null, ptr [[TMP197]], align 8 776 // CHECK1-NEXT: [[TMP198:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 5 777 // CHECK1-NEXT: store i64 5, ptr [[TMP198]], align 8 778 // CHECK1-NEXT: [[TMP199:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 5 779 // CHECK1-NEXT: store i64 5, ptr [[TMP199]], align 8 780 // CHECK1-NEXT: [[TMP200:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i64 0, i64 5 781 // CHECK1-NEXT: store ptr null, ptr [[TMP200]], align 8 782 // CHECK1-NEXT: [[TMP201:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 6 783 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP201]], align 8 784 // CHECK1-NEXT: [[TMP202:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 6 785 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP202]], align 8 786 // CHECK1-NEXT: [[TMP203:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i64 0, i64 6 787 // CHECK1-NEXT: store ptr null, ptr [[TMP203]], align 8 788 // CHECK1-NEXT: [[TMP204:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 7 789 // CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP204]], align 8 790 // CHECK1-NEXT: [[TMP205:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 7 791 // CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP205]], align 8 792 // CHECK1-NEXT: [[TMP206:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 793 // CHECK1-NEXT: store i64 [[TMP181]], ptr [[TMP206]], align 8 794 // CHECK1-NEXT: [[TMP207:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i64 0, i64 7 795 // CHECK1-NEXT: store ptr null, ptr [[TMP207]], align 8 796 // CHECK1-NEXT: [[TMP208:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 8 797 // CHECK1-NEXT: store ptr [[D]], ptr [[TMP208]], align 8 798 // CHECK1-NEXT: [[TMP209:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 8 799 // CHECK1-NEXT: store ptr [[D]], ptr [[TMP209]], align 8 800 // CHECK1-NEXT: [[TMP210:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i64 0, i64 8 801 // CHECK1-NEXT: store ptr null, ptr [[TMP210]], align 8 802 // CHECK1-NEXT: [[TMP211:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 0 803 // CHECK1-NEXT: [[TMP212:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 0 804 // CHECK1-NEXT: [[TMP213:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 805 // CHECK1-NEXT: [[TMP214:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 0 806 // CHECK1-NEXT: store i32 3, ptr [[TMP214]], align 4 807 // CHECK1-NEXT: [[TMP215:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 1 808 // CHECK1-NEXT: store i32 9, ptr [[TMP215]], align 4 809 // CHECK1-NEXT: [[TMP216:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 2 810 // CHECK1-NEXT: store ptr [[TMP211]], ptr [[TMP216]], align 8 811 // CHECK1-NEXT: [[TMP217:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 3 812 // CHECK1-NEXT: store ptr [[TMP212]], ptr [[TMP217]], align 8 813 // CHECK1-NEXT: [[TMP218:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 4 814 // CHECK1-NEXT: store ptr [[TMP213]], ptr [[TMP218]], align 8 815 // CHECK1-NEXT: [[TMP219:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 5 816 // CHECK1-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP219]], align 8 817 // CHECK1-NEXT: [[TMP220:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 6 818 // CHECK1-NEXT: store ptr null, ptr [[TMP220]], align 8 819 // CHECK1-NEXT: [[TMP221:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 7 820 // CHECK1-NEXT: store ptr null, ptr [[TMP221]], align 8 821 // CHECK1-NEXT: [[TMP222:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 8 822 // CHECK1-NEXT: store i64 0, ptr [[TMP222]], align 8 823 // CHECK1-NEXT: [[TMP223:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 9 824 // CHECK1-NEXT: store i64 0, ptr [[TMP223]], align 8 825 // CHECK1-NEXT: [[TMP224:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 10 826 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP224]], align 4 827 // CHECK1-NEXT: [[TMP225:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 11 828 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP225]], align 4 829 // CHECK1-NEXT: [[TMP226:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 12 830 // CHECK1-NEXT: store i32 0, ptr [[TMP226]], align 4 831 // CHECK1-NEXT: [[TMP227:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.region_id, ptr [[KERNEL_ARGS46]]) 832 // CHECK1-NEXT: [[TMP228:%.*]] = icmp ne i32 [[TMP227]], 0 833 // CHECK1-NEXT: br i1 [[TMP228]], label [[OMP_OFFLOAD_FAILED47:%.*]], label [[OMP_OFFLOAD_CONT48:%.*]] 834 // CHECK1: omp_offload.failed47: 835 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP177]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] 836 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT48]] 837 // CHECK1: omp_offload.cont48: 838 // CHECK1-NEXT: br label [[OMP_IF_END50:%.*]] 839 // CHECK1: omp_if.else49: 840 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP177]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] 841 // CHECK1-NEXT: br label [[OMP_IF_END50]] 842 // CHECK1: omp_if.end50: 843 // CHECK1-NEXT: store i32 0, ptr [[NN]], align 4 844 // CHECK1-NEXT: [[TMP229:%.*]] = load i32, ptr [[NN]], align 4 845 // CHECK1-NEXT: store i32 [[TMP229]], ptr [[NN_CASTED]], align 4 846 // CHECK1-NEXT: [[TMP230:%.*]] = load i64, ptr [[NN_CASTED]], align 8 847 // CHECK1-NEXT: [[TMP231:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS51]], i32 0, i32 0 848 // CHECK1-NEXT: store i64 [[TMP230]], ptr [[TMP231]], align 8 849 // CHECK1-NEXT: [[TMP232:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS52]], i32 0, i32 0 850 // CHECK1-NEXT: store i64 [[TMP230]], ptr [[TMP232]], align 8 851 // CHECK1-NEXT: [[TMP233:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS53]], i64 0, i64 0 852 // CHECK1-NEXT: store ptr null, ptr [[TMP233]], align 8 853 // CHECK1-NEXT: [[TMP234:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS51]], i32 0, i32 0 854 // CHECK1-NEXT: [[TMP235:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS52]], i32 0, i32 0 855 // CHECK1-NEXT: [[TMP236:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 0 856 // CHECK1-NEXT: store i32 3, ptr [[TMP236]], align 4 857 // CHECK1-NEXT: [[TMP237:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 1 858 // CHECK1-NEXT: store i32 1, ptr [[TMP237]], align 4 859 // CHECK1-NEXT: [[TMP238:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 2 860 // CHECK1-NEXT: store ptr [[TMP234]], ptr [[TMP238]], align 8 861 // CHECK1-NEXT: [[TMP239:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 3 862 // CHECK1-NEXT: store ptr [[TMP235]], ptr [[TMP239]], align 8 863 // CHECK1-NEXT: [[TMP240:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 4 864 // CHECK1-NEXT: store ptr @.offload_sizes.13, ptr [[TMP240]], align 8 865 // CHECK1-NEXT: [[TMP241:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 5 866 // CHECK1-NEXT: store ptr @.offload_maptypes.14, ptr [[TMP241]], align 8 867 // CHECK1-NEXT: [[TMP242:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 6 868 // CHECK1-NEXT: store ptr null, ptr [[TMP242]], align 8 869 // CHECK1-NEXT: [[TMP243:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 7 870 // CHECK1-NEXT: store ptr null, ptr [[TMP243]], align 8 871 // CHECK1-NEXT: [[TMP244:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 8 872 // CHECK1-NEXT: store i64 0, ptr [[TMP244]], align 8 873 // CHECK1-NEXT: [[TMP245:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 9 874 // CHECK1-NEXT: store i64 0, ptr [[TMP245]], align 8 875 // CHECK1-NEXT: [[TMP246:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 10 876 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP246]], align 4 877 // CHECK1-NEXT: [[TMP247:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 11 878 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP247]], align 4 879 // CHECK1-NEXT: [[TMP248:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 12 880 // CHECK1-NEXT: store i32 0, ptr [[TMP248]], align 4 881 // CHECK1-NEXT: [[TMP249:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.region_id, ptr [[KERNEL_ARGS54]]) 882 // CHECK1-NEXT: [[TMP250:%.*]] = icmp ne i32 [[TMP249]], 0 883 // CHECK1-NEXT: br i1 [[TMP250]], label [[OMP_OFFLOAD_FAILED55:%.*]], label [[OMP_OFFLOAD_CONT56:%.*]] 884 // CHECK1: omp_offload.failed55: 885 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172(i64 [[TMP230]]) #[[ATTR3]] 886 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT56]] 887 // CHECK1: omp_offload.cont56: 888 // CHECK1-NEXT: [[TMP251:%.*]] = load i32, ptr [[NN]], align 4 889 // CHECK1-NEXT: store i32 [[TMP251]], ptr [[NN_CASTED57]], align 4 890 // CHECK1-NEXT: [[TMP252:%.*]] = load i64, ptr [[NN_CASTED57]], align 8 891 // CHECK1-NEXT: [[TMP253:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS58]], i32 0, i32 0 892 // CHECK1-NEXT: store i64 [[TMP252]], ptr [[TMP253]], align 8 893 // CHECK1-NEXT: [[TMP254:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS59]], i32 0, i32 0 894 // CHECK1-NEXT: store i64 [[TMP252]], ptr [[TMP254]], align 8 895 // CHECK1-NEXT: [[TMP255:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS60]], i64 0, i64 0 896 // CHECK1-NEXT: store ptr null, ptr [[TMP255]], align 8 897 // CHECK1-NEXT: [[TMP256:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS58]], i32 0, i32 0 898 // CHECK1-NEXT: [[TMP257:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS59]], i32 0, i32 0 899 // CHECK1-NEXT: [[TMP258:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 0 900 // CHECK1-NEXT: store i32 3, ptr [[TMP258]], align 4 901 // CHECK1-NEXT: [[TMP259:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 1 902 // CHECK1-NEXT: store i32 1, ptr [[TMP259]], align 4 903 // CHECK1-NEXT: [[TMP260:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 2 904 // CHECK1-NEXT: store ptr [[TMP256]], ptr [[TMP260]], align 8 905 // CHECK1-NEXT: [[TMP261:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 3 906 // CHECK1-NEXT: store ptr [[TMP257]], ptr [[TMP261]], align 8 907 // CHECK1-NEXT: [[TMP262:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 4 908 // CHECK1-NEXT: store ptr @.offload_sizes.15, ptr [[TMP262]], align 8 909 // CHECK1-NEXT: [[TMP263:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 5 910 // CHECK1-NEXT: store ptr @.offload_maptypes.16, ptr [[TMP263]], align 8 911 // CHECK1-NEXT: [[TMP264:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 6 912 // CHECK1-NEXT: store ptr null, ptr [[TMP264]], align 8 913 // CHECK1-NEXT: [[TMP265:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 7 914 // CHECK1-NEXT: store ptr null, ptr [[TMP265]], align 8 915 // CHECK1-NEXT: [[TMP266:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 8 916 // CHECK1-NEXT: store i64 0, ptr [[TMP266]], align 8 917 // CHECK1-NEXT: [[TMP267:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 9 918 // CHECK1-NEXT: store i64 0, ptr [[TMP267]], align 8 919 // CHECK1-NEXT: [[TMP268:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 10 920 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP268]], align 4 921 // CHECK1-NEXT: [[TMP269:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 11 922 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP269]], align 4 923 // CHECK1-NEXT: [[TMP270:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 12 924 // CHECK1-NEXT: store i32 0, ptr [[TMP270]], align 4 925 // CHECK1-NEXT: [[TMP271:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.region_id, ptr [[KERNEL_ARGS61]]) 926 // CHECK1-NEXT: [[TMP272:%.*]] = icmp ne i32 [[TMP271]], 0 927 // CHECK1-NEXT: br i1 [[TMP272]], label [[OMP_OFFLOAD_FAILED62:%.*]], label [[OMP_OFFLOAD_CONT63:%.*]] 928 // CHECK1: omp_offload.failed62: 929 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175(i64 [[TMP252]]) #[[ATTR3]] 930 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT63]] 931 // CHECK1: omp_offload.cont63: 932 // CHECK1-NEXT: [[TMP273:%.*]] = load i32, ptr [[A]], align 4 933 // CHECK1-NEXT: [[TMP274:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 934 // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP274]]) 935 // CHECK1-NEXT: ret i32 [[TMP273]] 936 // 937 // 938 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 939 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 940 // CHECK1-NEXT: entry: 941 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 942 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 943 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 944 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 945 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 946 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 947 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 948 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8 949 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 950 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 951 // CHECK1-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 952 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 953 // CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 954 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 955 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i64 [[TMP4]]) 956 // CHECK1-NEXT: ret void 957 // 958 // 959 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined 960 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 961 // CHECK1-NEXT: entry: 962 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 963 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 964 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 965 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 966 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 967 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 968 // CHECK1-NEXT: ret void 969 // 970 // 971 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. 972 // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 973 // CHECK1-NEXT: entry: 974 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 975 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 976 // CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8 977 // CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 978 // CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 979 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 980 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 981 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 982 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 983 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8 984 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8 985 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0 986 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 987 // CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8 988 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1 989 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 990 // CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 8 991 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2 992 // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR4]], align 8 993 // CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 8 994 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3 995 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 996 // CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 8 997 // CHECK1-NEXT: ret void 998 // 999 // 1000 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 1001 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 1002 // CHECK1-NEXT: entry: 1003 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 1004 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 1005 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 1006 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 1007 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 1008 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 1009 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8 1010 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8 1011 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8 1012 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8 1013 // CHECK1-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1014 // CHECK1-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 1015 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 1016 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i64, align 8 1017 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 1018 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 1019 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 1020 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 1021 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 1022 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 1023 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 1024 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 1025 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 1026 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 1027 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 1028 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 1029 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 1030 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 1031 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]]) 1032 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META27:![0-9]+]] 1033 // CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META27]] 1034 // CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META27]] 1035 // CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META27]] 1036 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META27]] 1037 // CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META27]] 1038 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META27]] 1039 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META27]] 1040 // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META27]] 1041 // CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 1042 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META27]] 1043 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META27]] 1044 // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META27]] 1045 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META27]] 1046 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1 1047 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2 1048 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4 1049 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP17]], align 4 1050 // CHECK1-NEXT: [[TMP20:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 0 1051 // CHECK1-NEXT: [[TMP21:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP19]], 0 1052 // CHECK1-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META27]] 1053 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 1054 // CHECK1-NEXT: store i32 3, ptr [[TMP22]], align 4, !noalias [[META27]] 1055 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 1056 // CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP23]], align 8, !noalias [[META27]] 1057 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 1058 // CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP24]], align 8, !noalias [[META27]] 1059 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 1060 // CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP25]], align 8, !noalias [[META27]] 1061 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 1062 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 8, !noalias [[META27]] 1063 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 1064 // CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8, !noalias [[META27]] 1065 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 1066 // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8, !noalias [[META27]] 1067 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 1068 // CHECK1-NEXT: store i64 0, ptr [[TMP29]], align 8, !noalias [[META27]] 1069 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9 1070 // CHECK1-NEXT: store i64 1, ptr [[TMP30]], align 8, !noalias [[META27]] 1071 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10 1072 // CHECK1-NEXT: store [3 x i32] [[TMP20]], ptr [[TMP31]], align 4, !noalias [[META27]] 1073 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11 1074 // CHECK1-NEXT: store [3 x i32] [[TMP21]], ptr [[TMP32]], align 4, !noalias [[META27]] 1075 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12 1076 // CHECK1-NEXT: store i32 0, ptr [[TMP33]], align 4, !noalias [[META27]] 1077 // CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 [[TMP18]], i32 [[TMP19]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, ptr [[KERNEL_ARGS_I]]) 1078 // CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 1079 // CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] 1080 // CHECK1: omp_offload.failed.i: 1081 // CHECK1-NEXT: [[TMP36:%.*]] = load i16, ptr [[TMP12]], align 2 1082 // CHECK1-NEXT: store i16 [[TMP36]], ptr [[AA_CASTED_I]], align 2, !noalias [[META27]] 1083 // CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias [[META27]] 1084 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP16]], align 4 1085 // CHECK1-NEXT: store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias [[META27]] 1086 // CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias [[META27]] 1087 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP17]], align 4 1088 // CHECK1-NEXT: store i32 [[TMP40]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias [[META27]] 1089 // CHECK1-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 8, !noalias [[META27]] 1090 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP37]], i64 [[TMP39]], i64 [[TMP41]]) #[[ATTR3]] 1091 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] 1092 // CHECK1: .omp_outlined..exit: 1093 // CHECK1-NEXT: ret i32 0 1094 // 1095 // 1096 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 1097 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { 1098 // CHECK1-NEXT: entry: 1099 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1100 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1101 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1102 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1103 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 1104 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 1105 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105.omp_outlined, i64 [[TMP1]]) 1106 // CHECK1-NEXT: ret void 1107 // 1108 // 1109 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105.omp_outlined 1110 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 1111 // CHECK1-NEXT: entry: 1112 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1113 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1114 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1115 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1116 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1117 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1118 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1119 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1120 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 1121 // CHECK1-NEXT: ret void 1122 // 1123 // 1124 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 1125 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1126 // CHECK1-NEXT: entry: 1127 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1128 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1129 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1130 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1131 // CHECK1-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 1132 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1133 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP1]]) 1134 // CHECK1-NEXT: ret void 1135 // 1136 // 1137 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined 1138 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1139 // CHECK1-NEXT: entry: 1140 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1141 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1142 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1143 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1144 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1145 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1146 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1147 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 1148 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 1149 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 1150 // CHECK1-NEXT: store i16 [[CONV1]], ptr [[AA_ADDR]], align 2 1151 // CHECK1-NEXT: ret void 1152 // 1153 // 1154 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 1155 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1156 // CHECK1-NEXT: entry: 1157 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1158 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1159 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1160 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1161 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1162 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1163 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1164 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 1165 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 1166 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1167 // CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 1168 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1169 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) 1170 // CHECK1-NEXT: ret void 1171 // 1172 // 1173 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined 1174 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1175 // CHECK1-NEXT: entry: 1176 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1177 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1178 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1179 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1180 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1181 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1182 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1183 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1184 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1185 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1186 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 1187 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1188 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 1189 // CHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 1190 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 1191 // CHECK1-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 1192 // CHECK1-NEXT: ret void 1193 // 1194 // 1195 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124 1196 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1197 // CHECK1-NEXT: entry: 1198 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1199 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1200 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1201 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1202 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 1203 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1204 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1205 // CHECK1-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1) 1206 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 1207 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 1208 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 1209 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1210 // CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 1211 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1212 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i64 [[TMP2]], i64 [[TMP4]]) 1213 // CHECK1-NEXT: ret void 1214 // 1215 // 1216 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined 1217 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1218 // CHECK1-NEXT: entry: 1219 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1220 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1221 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1222 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1223 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1224 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1225 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1226 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1227 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1228 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1229 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 1230 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1231 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 1232 // CHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 1233 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 1234 // CHECK1-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 1235 // CHECK1-NEXT: ret void 1236 // 1237 // 1238 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130 1239 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1240 // CHECK1-NEXT: entry: 1241 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1242 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1243 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1244 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1245 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 1246 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1247 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1248 // CHECK1-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1) 1249 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 1250 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 1251 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 1252 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1253 // CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 1254 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1255 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined, i64 [[TMP2]], i64 [[TMP4]]) 1256 // CHECK1-NEXT: ret void 1257 // 1258 // 1259 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined 1260 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1261 // CHECK1-NEXT: entry: 1262 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1263 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1264 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1265 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1266 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1267 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1268 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1269 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1270 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1271 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1272 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 1273 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1274 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 1275 // CHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 1276 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 1277 // CHECK1-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 1278 // CHECK1-NEXT: ret void 1279 // 1280 // 1281 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136 1282 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1283 // CHECK1-NEXT: entry: 1284 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1285 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1286 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1287 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1288 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 1289 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1290 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1291 // CHECK1-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1) 1292 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 1293 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 1294 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 1295 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1296 // CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 1297 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1298 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i64 [[TMP2]], i64 [[TMP4]]) 1299 // CHECK1-NEXT: ret void 1300 // 1301 // 1302 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined 1303 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1304 // CHECK1-NEXT: entry: 1305 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1306 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1307 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1308 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1309 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1310 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1311 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1312 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1313 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1314 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1315 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 1316 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1317 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 1318 // CHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 1319 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 1320 // CHECK1-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 1321 // CHECK1-NEXT: ret void 1322 // 1323 // 1324 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160 1325 // CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 1326 // CHECK1-NEXT: entry: 1327 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1328 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1329 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1330 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 1331 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1332 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1333 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1334 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 1335 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 1336 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1337 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1338 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1339 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1340 // CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 1341 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1342 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1343 // CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 1344 // CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 1345 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 1346 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1347 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1348 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 1349 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1350 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1351 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 1352 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 1353 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 1354 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 1355 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 1356 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 1357 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]]) 1358 // CHECK1-NEXT: ret void 1359 // 1360 // 1361 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined 1362 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 1363 // CHECK1-NEXT: entry: 1364 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1365 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1366 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1367 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1368 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1369 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 1370 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1371 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1372 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1373 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 1374 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 1375 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1376 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1377 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1378 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1379 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1380 // CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 1381 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1382 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1383 // CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 1384 // CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 1385 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 1386 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1387 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1388 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 1389 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1390 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1391 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 1392 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 1393 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 1394 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 1395 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 1396 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 1397 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 1398 // CHECK1-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4 1399 // CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 1400 // CHECK1-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 1401 // CHECK1-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 1402 // CHECK1-NEXT: store float [[CONV6]], ptr [[ARRAYIDX]], align 4 1403 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 1404 // CHECK1-NEXT: [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 4 1405 // CHECK1-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 1406 // CHECK1-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 1407 // CHECK1-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 1408 // CHECK1-NEXT: store float [[CONV10]], ptr [[ARRAYIDX7]], align 4 1409 // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 1410 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i64 0, i64 2 1411 // CHECK1-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8 1412 // CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 1413 // CHECK1-NEXT: store double [[ADD13]], ptr [[ARRAYIDX12]], align 8 1414 // CHECK1-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 1415 // CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP12]] 1416 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3 1417 // CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 8 1418 // CHECK1-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 1419 // CHECK1-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8 1420 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 1421 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[X]], align 8 1422 // CHECK1-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 1423 // CHECK1-NEXT: store i64 [[ADD17]], ptr [[X]], align 8 1424 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 1425 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, ptr [[Y]], align 8 1426 // CHECK1-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 1427 // CHECK1-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 1428 // CHECK1-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 1429 // CHECK1-NEXT: store i8 [[CONV20]], ptr [[Y]], align 8 1430 // CHECK1-NEXT: ret void 1431 // 1432 // 1433 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172 1434 // CHECK1-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1435 // CHECK1-NEXT: entry: 1436 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1437 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 1438 // CHECK1-NEXT: store i64 [[NN]], ptr [[NN_ADDR]], align 8 1439 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4 1440 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[NN_CASTED]], align 4 1441 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 8 1442 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined, i64 [[TMP1]]) 1443 // CHECK1-NEXT: ret void 1444 // 1445 // 1446 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined 1447 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1448 // CHECK1-NEXT: entry: 1449 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1450 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1451 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1452 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 1453 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1454 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1455 // CHECK1-NEXT: store i64 [[NN]], ptr [[NN_ADDR]], align 8 1456 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4 1457 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[NN_CASTED]], align 4 1458 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 8 1459 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined.omp_outlined, i64 [[TMP1]]) 1460 // CHECK1-NEXT: ret void 1461 // 1462 // 1463 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined.omp_outlined 1464 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1465 // CHECK1-NEXT: entry: 1466 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1467 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1468 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1469 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1470 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1471 // CHECK1-NEXT: store i64 [[NN]], ptr [[NN_ADDR]], align 8 1472 // CHECK1-NEXT: ret void 1473 // 1474 // 1475 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175 1476 // CHECK1-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1477 // CHECK1-NEXT: entry: 1478 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1479 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 1480 // CHECK1-NEXT: store i64 [[NN]], ptr [[NN_ADDR]], align 8 1481 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4 1482 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[NN_CASTED]], align 4 1483 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 8 1484 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined, i64 [[TMP1]]) 1485 // CHECK1-NEXT: ret void 1486 // 1487 // 1488 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined 1489 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1490 // CHECK1-NEXT: entry: 1491 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1492 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1493 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1494 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1495 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1496 // CHECK1-NEXT: store i64 [[NN]], ptr [[NN_ADDR]], align 8 1497 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined.omp_outlined, ptr [[NN_ADDR]]) 1498 // CHECK1-NEXT: ret void 1499 // 1500 // 1501 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined.omp_outlined 1502 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 1503 // CHECK1-NEXT: entry: 1504 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1505 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1506 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca ptr, align 8 1507 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1508 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1509 // CHECK1-NEXT: store ptr [[NN]], ptr [[NN_ADDR]], align 8 1510 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[NN_ADDR]], align 8 1511 // CHECK1-NEXT: ret void 1512 // 1513 // 1514 // CHECK1-LABEL: define {{[^@]+}}@_Z6bazzzziPi 1515 // CHECK1-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[F:%.*]]) #[[ATTR0]] { 1516 // CHECK1-NEXT: entry: 1517 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1518 // CHECK1-NEXT: [[F_ADDR:%.*]] = alloca ptr, align 8 1519 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 1520 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 1521 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 1522 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1523 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1524 // CHECK1-NEXT: store ptr [[F]], ptr [[F_ADDR]], align 8 1525 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 1526 // CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1527 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1528 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8 1529 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1530 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8 1531 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1532 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 1533 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1534 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1535 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1536 // CHECK1-NEXT: store i32 3, ptr [[TMP7]], align 4 1537 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1538 // CHECK1-NEXT: store i32 1, ptr [[TMP8]], align 4 1539 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1540 // CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8 1541 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1542 // CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8 1543 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1544 // CHECK1-NEXT: store ptr @.offload_sizes.17, ptr [[TMP11]], align 8 1545 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1546 // CHECK1-NEXT: store ptr @.offload_maptypes.18, ptr [[TMP12]], align 8 1547 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1548 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8 1549 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1550 // CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8 1551 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1552 // CHECK1-NEXT: store i64 0, ptr [[TMP15]], align 8 1553 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1554 // CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8 1555 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1556 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 1557 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1558 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 1559 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1560 // CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4 1561 // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.region_id, ptr [[KERNEL_ARGS]]) 1562 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 1563 // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1564 // CHECK1: omp_offload.failed: 1565 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200(i64 [[TMP1]]) #[[ATTR3]] 1566 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1567 // CHECK1: omp_offload.cont: 1568 // CHECK1-NEXT: ret void 1569 // 1570 // 1571 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200 1572 // CHECK1-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR2]] { 1573 // CHECK1-NEXT: entry: 1574 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1575 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1576 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1577 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined, i64 [[TMP0]]) 1578 // CHECK1-NEXT: ret void 1579 // 1580 // 1581 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined 1582 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] { 1583 // CHECK1-NEXT: entry: 1584 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1585 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1586 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1587 // CHECK1-NEXT: [[F:%.*]] = alloca ptr, align 8 1588 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1589 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1590 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1591 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1592 // CHECK1-NEXT: ret void 1593 // 1594 // 1595 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 1596 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1597 // CHECK1-NEXT: entry: 1598 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1599 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1600 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1601 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1602 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 1603 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 1604 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 1605 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 1606 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1607 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A]], align 4 1608 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 1609 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 1610 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 1611 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1612 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 1613 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 1614 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 1615 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 1616 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1617 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 1618 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 1619 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 1620 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 1621 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 1622 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 1623 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 1624 // CHECK1-NEXT: ret i32 [[TMP8]] 1625 // 1626 // 1627 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1628 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1629 // CHECK1-NEXT: entry: 1630 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1631 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1632 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 1633 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 1634 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1635 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1636 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 1637 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 1638 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 1639 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1640 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1641 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1642 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1643 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1644 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 1645 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1646 // CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4 1647 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 1648 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1649 // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0() 1650 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 1651 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 1652 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 1653 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 1654 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 1655 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 1656 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 1657 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 1658 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 1659 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1660 // CHECK1: omp_if.then: 1661 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 1662 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 1663 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 1664 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.19, i64 40, i1 false) 1665 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1666 // CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 8 1667 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1668 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP11]], align 8 1669 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1670 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 1671 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1672 // CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP13]], align 8 1673 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1674 // CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP14]], align 8 1675 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1676 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 1677 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1678 // CHECK1-NEXT: store i64 2, ptr [[TMP16]], align 8 1679 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1680 // CHECK1-NEXT: store i64 2, ptr [[TMP17]], align 8 1681 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1682 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 1683 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1684 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP19]], align 8 1685 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1686 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP20]], align 8 1687 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1688 // CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8 1689 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1690 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 8 1691 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1692 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 8 1693 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1694 // CHECK1-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 8 1695 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1696 // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 1697 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1698 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1699 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1700 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1701 // CHECK1-NEXT: store i32 3, ptr [[TMP29]], align 4 1702 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1703 // CHECK1-NEXT: store i32 5, ptr [[TMP30]], align 4 1704 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1705 // CHECK1-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 8 1706 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1707 // CHECK1-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 8 1708 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1709 // CHECK1-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 8 1710 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1711 // CHECK1-NEXT: store ptr @.offload_maptypes.20, ptr [[TMP34]], align 8 1712 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1713 // CHECK1-NEXT: store ptr null, ptr [[TMP35]], align 8 1714 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1715 // CHECK1-NEXT: store ptr null, ptr [[TMP36]], align 8 1716 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1717 // CHECK1-NEXT: store i64 0, ptr [[TMP37]], align 8 1718 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1719 // CHECK1-NEXT: store i64 0, ptr [[TMP38]], align 8 1720 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1721 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 4 1722 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1723 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4 1724 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1725 // CHECK1-NEXT: store i32 0, ptr [[TMP41]], align 4 1726 // CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.region_id, ptr [[KERNEL_ARGS]]) 1727 // CHECK1-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 1728 // CHECK1-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1729 // CHECK1: omp_offload.failed: 1730 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]] 1731 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1732 // CHECK1: omp_offload.cont: 1733 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1734 // CHECK1: omp_if.else: 1735 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]] 1736 // CHECK1-NEXT: br label [[OMP_IF_END]] 1737 // CHECK1: omp_if.end: 1738 // CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]] 1739 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]] 1740 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 1741 // CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 1742 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 1743 // CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 1744 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] 1745 // CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 1746 // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]]) 1747 // CHECK1-NEXT: ret i32 [[ADD3]] 1748 // 1749 // 1750 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 1751 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1752 // CHECK1-NEXT: entry: 1753 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1754 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1755 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1756 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 1757 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1758 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1759 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1760 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1761 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 1762 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 1763 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 1764 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1765 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1766 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 1767 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 1768 // CHECK1-NEXT: store i8 0, ptr [[AAA]], align 1 1769 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 1770 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 1771 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 1772 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 1773 // CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 1774 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1775 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1 1776 // CHECK1-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1 1777 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 1778 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 1779 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 1780 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1781 // CHECK1: omp_if.then: 1782 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1783 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP7]], align 8 1784 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1785 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP8]], align 8 1786 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1787 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 1788 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1789 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP10]], align 8 1790 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1791 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP11]], align 8 1792 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1793 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 1794 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1795 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP13]], align 8 1796 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1797 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP14]], align 8 1798 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1799 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 1800 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1801 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP16]], align 8 1802 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1803 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP17]], align 8 1804 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1805 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 1806 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1807 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1808 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1809 // CHECK1-NEXT: store i32 3, ptr [[TMP21]], align 4 1810 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1811 // CHECK1-NEXT: store i32 4, ptr [[TMP22]], align 4 1812 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1813 // CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8 1814 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1815 // CHECK1-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8 1816 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1817 // CHECK1-NEXT: store ptr @.offload_sizes.21, ptr [[TMP25]], align 8 1818 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1819 // CHECK1-NEXT: store ptr @.offload_maptypes.22, ptr [[TMP26]], align 8 1820 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1821 // CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8 1822 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1823 // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8 1824 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1825 // CHECK1-NEXT: store i64 0, ptr [[TMP29]], align 8 1826 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1827 // CHECK1-NEXT: store i64 0, ptr [[TMP30]], align 8 1828 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1829 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 1830 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1831 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 1832 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1833 // CHECK1-NEXT: store i32 0, ptr [[TMP33]], align 4 1834 // CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.region_id, ptr [[KERNEL_ARGS]]) 1835 // CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 1836 // CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1837 // CHECK1: omp_offload.failed: 1838 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]] 1839 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1840 // CHECK1: omp_offload.cont: 1841 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1842 // CHECK1: omp_if.else: 1843 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]] 1844 // CHECK1-NEXT: br label [[OMP_IF_END]] 1845 // CHECK1: omp_if.end: 1846 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 1847 // CHECK1-NEXT: ret i32 [[TMP36]] 1848 // 1849 // 1850 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1851 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1852 // CHECK1-NEXT: entry: 1853 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1854 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1855 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1856 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1857 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1858 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1859 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 1860 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 1861 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 1862 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1863 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1864 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 1865 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 1866 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 1867 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 1868 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 1869 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 1870 // CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 1871 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1872 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 1873 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1874 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1875 // CHECK1: omp_if.then: 1876 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1877 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 1878 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1879 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 8 1880 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1881 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 1882 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1883 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 8 1884 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1885 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP9]], align 8 1886 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1887 // CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8 1888 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1889 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP11]], align 8 1890 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1891 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP12]], align 8 1892 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1893 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8 1894 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1895 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1896 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1897 // CHECK1-NEXT: store i32 3, ptr [[TMP16]], align 4 1898 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1899 // CHECK1-NEXT: store i32 3, ptr [[TMP17]], align 4 1900 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1901 // CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8 1902 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1903 // CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8 1904 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1905 // CHECK1-NEXT: store ptr @.offload_sizes.23, ptr [[TMP20]], align 8 1906 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1907 // CHECK1-NEXT: store ptr @.offload_maptypes.24, ptr [[TMP21]], align 8 1908 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1909 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 1910 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1911 // CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8 1912 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1913 // CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 8 1914 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1915 // CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 8 1916 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1917 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 1918 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1919 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 1920 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1921 // CHECK1-NEXT: store i32 0, ptr [[TMP28]], align 4 1922 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.region_id, ptr [[KERNEL_ARGS]]) 1923 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 1924 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1925 // CHECK1: omp_offload.failed: 1926 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] 1927 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1928 // CHECK1: omp_offload.cont: 1929 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1930 // CHECK1: omp_if.else: 1931 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] 1932 // CHECK1-NEXT: br label [[OMP_IF_END]] 1933 // CHECK1: omp_if.end: 1934 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 1935 // CHECK1-NEXT: ret i32 [[TMP31]] 1936 // 1937 // 1938 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245 1939 // CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1940 // CHECK1-NEXT: entry: 1941 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1942 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1943 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1944 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1945 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1946 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1947 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1948 // CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 1949 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1950 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1951 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1952 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1953 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1954 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1955 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1956 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 1957 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 1958 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8 1959 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) 1960 // CHECK1-NEXT: ret void 1961 // 1962 // 1963 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined 1964 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1965 // CHECK1-NEXT: entry: 1966 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1967 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1968 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1969 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1970 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1971 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1972 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1973 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1974 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1975 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1976 // CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 1977 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1978 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1979 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1980 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1981 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1982 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1983 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1984 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 1985 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 1986 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 1987 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 1988 // CHECK1-NEXT: store double [[ADD]], ptr [[A]], align 8 1989 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 1990 // CHECK1-NEXT: [[TMP5:%.*]] = load double, ptr [[A3]], align 8 1991 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 1992 // CHECK1-NEXT: store double [[INC]], ptr [[A3]], align 8 1993 // CHECK1-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 1994 // CHECK1-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 1995 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP6]] 1996 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 1997 // CHECK1-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2 1998 // CHECK1-NEXT: ret void 1999 // 2000 // 2001 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227 2002 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2003 // CHECK1-NEXT: entry: 2004 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2005 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2006 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 2007 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 2008 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2009 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2010 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 2011 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 2012 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 2013 // CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 2014 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 2015 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 2016 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 2017 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 2018 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 2019 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2020 // CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 2021 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 2022 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 2023 // CHECK1-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 2024 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 2025 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]]) 2026 // CHECK1-NEXT: ret void 2027 // 2028 // 2029 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined 2030 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2031 // CHECK1-NEXT: entry: 2032 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2033 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2034 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2035 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2036 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 2037 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 2038 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2039 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2040 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 2041 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 2042 // CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 2043 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 2044 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 2045 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 2046 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2047 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 2048 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2049 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 2050 // CHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 2051 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 2052 // CHECK1-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 2053 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 2054 // CHECK1-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 2055 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 2056 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 2057 // CHECK1-NEXT: store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1 2058 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 2059 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 2060 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 2061 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4 2062 // CHECK1-NEXT: ret void 2063 // 2064 // 2065 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210 2066 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2067 // CHECK1-NEXT: entry: 2068 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2069 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2070 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 2071 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2072 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2073 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 2074 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 2075 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 2076 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 2077 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 2078 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 2079 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 2080 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2081 // CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 2082 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 2083 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) 2084 // CHECK1-NEXT: ret void 2085 // 2086 // 2087 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined 2088 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2089 // CHECK1-NEXT: entry: 2090 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2091 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2092 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2093 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2094 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 2095 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2096 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2097 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 2098 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 2099 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 2100 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 2101 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 2102 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2103 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 2104 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2105 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 2106 // CHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 2107 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 2108 // CHECK1-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 2109 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 2110 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 2111 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 2112 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 2113 // CHECK1-NEXT: ret void 2114 // 2115 // 2116 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 2117 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { 2118 // CHECK3-NEXT: entry: 2119 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2120 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2121 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 2122 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 2123 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 2124 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2125 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 2126 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2127 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 2128 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2129 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 2130 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2131 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 2132 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 2133 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 2134 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 2135 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 2136 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 2137 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2138 // CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 2139 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 4 2140 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 4 2141 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 4 2142 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2143 // CHECK3-NEXT: [[A_CASTED8:%.*]] = alloca i32, align 4 2144 // CHECK3-NEXT: [[AA_CASTED9:%.*]] = alloca i32, align 4 2145 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 4 2146 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 4 2147 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 4 2148 // CHECK3-NEXT: [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 2149 // CHECK3-NEXT: [[A_CASTED16:%.*]] = alloca i32, align 4 2150 // CHECK3-NEXT: [[AA_CASTED17:%.*]] = alloca i32, align 4 2151 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [2 x ptr], align 4 2152 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS19:%.*]] = alloca [2 x ptr], align 4 2153 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [2 x ptr], align 4 2154 // CHECK3-NEXT: [[KERNEL_ARGS21:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 2155 // CHECK3-NEXT: [[A_CASTED24:%.*]] = alloca i32, align 4 2156 // CHECK3-NEXT: [[AA_CASTED25:%.*]] = alloca i32, align 4 2157 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS26:%.*]] = alloca [2 x ptr], align 4 2158 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS27:%.*]] = alloca [2 x ptr], align 4 2159 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS28:%.*]] = alloca [2 x ptr], align 4 2160 // CHECK3-NEXT: [[KERNEL_ARGS29:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 2161 // CHECK3-NEXT: [[A_CASTED32:%.*]] = alloca i32, align 4 2162 // CHECK3-NEXT: [[AA_CASTED33:%.*]] = alloca i32, align 4 2163 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS34:%.*]] = alloca [2 x ptr], align 4 2164 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS35:%.*]] = alloca [2 x ptr], align 4 2165 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS36:%.*]] = alloca [2 x ptr], align 4 2166 // CHECK3-NEXT: [[KERNEL_ARGS37:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 2167 // CHECK3-NEXT: [[A_CASTED40:%.*]] = alloca i32, align 4 2168 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS43:%.*]] = alloca [9 x ptr], align 4 2169 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS44:%.*]] = alloca [9 x ptr], align 4 2170 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS45:%.*]] = alloca [9 x ptr], align 4 2171 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 2172 // CHECK3-NEXT: [[KERNEL_ARGS46:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 2173 // CHECK3-NEXT: [[NN:%.*]] = alloca i32, align 4 2174 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 2175 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS51:%.*]] = alloca [1 x ptr], align 4 2176 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS52:%.*]] = alloca [1 x ptr], align 4 2177 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS53:%.*]] = alloca [1 x ptr], align 4 2178 // CHECK3-NEXT: [[KERNEL_ARGS54:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 2179 // CHECK3-NEXT: [[NN_CASTED57:%.*]] = alloca i32, align 4 2180 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS58:%.*]] = alloca [1 x ptr], align 4 2181 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS59:%.*]] = alloca [1 x ptr], align 4 2182 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS60:%.*]] = alloca [1 x ptr], align 4 2183 // CHECK3-NEXT: [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 2184 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) 2185 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2186 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 2187 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 2188 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 2189 // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0() 2190 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 2191 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 2192 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 2193 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 2194 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 2195 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 2196 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 2197 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 2198 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4 2199 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 2200 // CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_2]], align 4 2201 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 2202 // CHECK3-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 2203 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4 2204 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 2205 // CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 2206 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 2207 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 2208 // CHECK3-NEXT: store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4 2209 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4 2210 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2211 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[TMP13]], align 4 2212 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2213 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[TMP14]], align 4 2214 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2215 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 2216 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2217 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[TMP16]], align 4 2218 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2219 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[TMP17]], align 4 2220 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2221 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 2222 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2223 // CHECK3-NEXT: store i32 [[TMP12]], ptr [[TMP19]], align 4 2224 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2225 // CHECK3-NEXT: store i32 [[TMP12]], ptr [[TMP20]], align 4 2226 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2227 // CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 4 2228 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2229 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2230 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 2231 // CHECK3-NEXT: [[TMP25:%.*]] = load i16, ptr [[AA]], align 2 2232 // CHECK3-NEXT: store i16 [[TMP25]], ptr [[TMP24]], align 4 2233 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1 2234 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 2235 // CHECK3-NEXT: store i32 [[TMP27]], ptr [[TMP26]], align 4 2236 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2 2237 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 2238 // CHECK3-NEXT: store i32 [[TMP29]], ptr [[TMP28]], align 4 2239 // CHECK3-NEXT: [[TMP30:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, ptr @.omp_task_entry., i64 -1) 2240 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP30]], i32 0, i32 0 2241 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP31]], i32 0, i32 0 2242 // CHECK3-NEXT: [[TMP33:%.*]] = load ptr, ptr [[TMP32]], align 4 2243 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP33]], ptr align 4 [[AGG_CAPTURED]], i32 12, i1 false) 2244 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP30]], i32 0, i32 1 2245 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP34]], i32 0, i32 0 2246 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP35]], ptr align 4 @.offload_sizes, i32 24, i1 false) 2247 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 1 2248 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP36]], ptr align 4 [[TMP22]], i32 12, i1 false) 2249 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 2 2250 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP37]], ptr align 4 [[TMP23]], i32 12, i1 false) 2251 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 3 2252 // CHECK3-NEXT: [[TMP39:%.*]] = load i16, ptr [[AA]], align 2 2253 // CHECK3-NEXT: store i16 [[TMP39]], ptr [[TMP38]], align 4 2254 // CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP30]]) 2255 // CHECK3-NEXT: [[TMP41:%.*]] = load i32, ptr [[A]], align 4 2256 // CHECK3-NEXT: store i32 [[TMP41]], ptr [[A_CASTED]], align 4 2257 // CHECK3-NEXT: [[TMP42:%.*]] = load i32, ptr [[A_CASTED]], align 4 2258 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP42]]) #[[ATTR3:[0-9]+]] 2259 // CHECK3-NEXT: [[TMP43:%.*]] = load i16, ptr [[AA]], align 2 2260 // CHECK3-NEXT: store i16 [[TMP43]], ptr [[AA_CASTED4]], align 2 2261 // CHECK3-NEXT: [[TMP44:%.*]] = load i32, ptr [[AA_CASTED4]], align 4 2262 // CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 2263 // CHECK3-NEXT: store i32 [[TMP44]], ptr [[TMP45]], align 4 2264 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 2265 // CHECK3-NEXT: store i32 [[TMP44]], ptr [[TMP46]], align 4 2266 // CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 2267 // CHECK3-NEXT: store ptr null, ptr [[TMP47]], align 4 2268 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 2269 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 2270 // CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2271 // CHECK3-NEXT: store i32 3, ptr [[TMP50]], align 4 2272 // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2273 // CHECK3-NEXT: store i32 1, ptr [[TMP51]], align 4 2274 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2275 // CHECK3-NEXT: store ptr [[TMP48]], ptr [[TMP52]], align 4 2276 // CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2277 // CHECK3-NEXT: store ptr [[TMP49]], ptr [[TMP53]], align 4 2278 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2279 // CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP54]], align 4 2280 // CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2281 // CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP55]], align 4 2282 // CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 2283 // CHECK3-NEXT: store ptr null, ptr [[TMP56]], align 4 2284 // CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 2285 // CHECK3-NEXT: store ptr null, ptr [[TMP57]], align 4 2286 // CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 2287 // CHECK3-NEXT: store i64 0, ptr [[TMP58]], align 8 2288 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 2289 // CHECK3-NEXT: store i64 0, ptr [[TMP59]], align 8 2290 // CHECK3-NEXT: [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 2291 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP60]], align 4 2292 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 2293 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP61]], align 4 2294 // CHECK3-NEXT: [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 2295 // CHECK3-NEXT: store i32 0, ptr [[TMP62]], align 4 2296 // CHECK3-NEXT: [[TMP63:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, ptr [[KERNEL_ARGS]]) 2297 // CHECK3-NEXT: [[TMP64:%.*]] = icmp ne i32 [[TMP63]], 0 2298 // CHECK3-NEXT: br i1 [[TMP64]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2299 // CHECK3: omp_offload.failed: 2300 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP44]]) #[[ATTR3]] 2301 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2302 // CHECK3: omp_offload.cont: 2303 // CHECK3-NEXT: [[TMP65:%.*]] = load i32, ptr [[A]], align 4 2304 // CHECK3-NEXT: store i32 [[TMP65]], ptr [[A_CASTED8]], align 4 2305 // CHECK3-NEXT: [[TMP66:%.*]] = load i32, ptr [[A_CASTED8]], align 4 2306 // CHECK3-NEXT: [[TMP67:%.*]] = load i16, ptr [[AA]], align 2 2307 // CHECK3-NEXT: store i16 [[TMP67]], ptr [[AA_CASTED9]], align 2 2308 // CHECK3-NEXT: [[TMP68:%.*]] = load i32, ptr [[AA_CASTED9]], align 4 2309 // CHECK3-NEXT: [[TMP69:%.*]] = load i32, ptr [[N_ADDR]], align 4 2310 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP69]], 10 2311 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2312 // CHECK3: omp_if.then: 2313 // CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 2314 // CHECK3-NEXT: store i32 [[TMP66]], ptr [[TMP70]], align 4 2315 // CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 2316 // CHECK3-NEXT: store i32 [[TMP66]], ptr [[TMP71]], align 4 2317 // CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 0 2318 // CHECK3-NEXT: store ptr null, ptr [[TMP72]], align 4 2319 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 2320 // CHECK3-NEXT: store i32 [[TMP68]], ptr [[TMP73]], align 4 2321 // CHECK3-NEXT: [[TMP74:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 2322 // CHECK3-NEXT: store i32 [[TMP68]], ptr [[TMP74]], align 4 2323 // CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 1 2324 // CHECK3-NEXT: store ptr null, ptr [[TMP75]], align 4 2325 // CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 2326 // CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 2327 // CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 0 2328 // CHECK3-NEXT: store i32 3, ptr [[TMP78]], align 4 2329 // CHECK3-NEXT: [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 1 2330 // CHECK3-NEXT: store i32 2, ptr [[TMP79]], align 4 2331 // CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 2 2332 // CHECK3-NEXT: store ptr [[TMP76]], ptr [[TMP80]], align 4 2333 // CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 3 2334 // CHECK3-NEXT: store ptr [[TMP77]], ptr [[TMP81]], align 4 2335 // CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 4 2336 // CHECK3-NEXT: store ptr @.offload_sizes.3, ptr [[TMP82]], align 4 2337 // CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 5 2338 // CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP83]], align 4 2339 // CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 6 2340 // CHECK3-NEXT: store ptr null, ptr [[TMP84]], align 4 2341 // CHECK3-NEXT: [[TMP85:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 7 2342 // CHECK3-NEXT: store ptr null, ptr [[TMP85]], align 4 2343 // CHECK3-NEXT: [[TMP86:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 8 2344 // CHECK3-NEXT: store i64 0, ptr [[TMP86]], align 8 2345 // CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 9 2346 // CHECK3-NEXT: store i64 0, ptr [[TMP87]], align 8 2347 // CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 10 2348 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP88]], align 4 2349 // CHECK3-NEXT: [[TMP89:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 11 2350 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP89]], align 4 2351 // CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 12 2352 // CHECK3-NEXT: store i32 0, ptr [[TMP90]], align 4 2353 // CHECK3-NEXT: [[TMP91:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, ptr [[KERNEL_ARGS13]]) 2354 // CHECK3-NEXT: [[TMP92:%.*]] = icmp ne i32 [[TMP91]], 0 2355 // CHECK3-NEXT: br i1 [[TMP92]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]] 2356 // CHECK3: omp_offload.failed14: 2357 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]] 2358 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT15]] 2359 // CHECK3: omp_offload.cont15: 2360 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2361 // CHECK3: omp_if.else: 2362 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]] 2363 // CHECK3-NEXT: br label [[OMP_IF_END]] 2364 // CHECK3: omp_if.end: 2365 // CHECK3-NEXT: [[TMP93:%.*]] = load i32, ptr [[A]], align 4 2366 // CHECK3-NEXT: store i32 [[TMP93]], ptr [[A_CASTED16]], align 4 2367 // CHECK3-NEXT: [[TMP94:%.*]] = load i32, ptr [[A_CASTED16]], align 4 2368 // CHECK3-NEXT: [[TMP95:%.*]] = load i16, ptr [[AA]], align 2 2369 // CHECK3-NEXT: store i16 [[TMP95]], ptr [[AA_CASTED17]], align 2 2370 // CHECK3-NEXT: [[TMP96:%.*]] = load i32, ptr [[AA_CASTED17]], align 4 2371 // CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 2372 // CHECK3-NEXT: store i32 [[TMP94]], ptr [[TMP97]], align 4 2373 // CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 2374 // CHECK3-NEXT: store i32 [[TMP94]], ptr [[TMP98]], align 4 2375 // CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 0 2376 // CHECK3-NEXT: store ptr null, ptr [[TMP99]], align 4 2377 // CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 1 2378 // CHECK3-NEXT: store i32 [[TMP96]], ptr [[TMP100]], align 4 2379 // CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS19]], i32 0, i32 1 2380 // CHECK3-NEXT: store i32 [[TMP96]], ptr [[TMP101]], align 4 2381 // CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 1 2382 // CHECK3-NEXT: store ptr null, ptr [[TMP102]], align 4 2383 // CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0 2384 // CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS19]], i32 0, i32 0 2385 // CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 0 2386 // CHECK3-NEXT: store i32 3, ptr [[TMP105]], align 4 2387 // CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 1 2388 // CHECK3-NEXT: store i32 2, ptr [[TMP106]], align 4 2389 // CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 2 2390 // CHECK3-NEXT: store ptr [[TMP103]], ptr [[TMP107]], align 4 2391 // CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 3 2392 // CHECK3-NEXT: store ptr [[TMP104]], ptr [[TMP108]], align 4 2393 // CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 4 2394 // CHECK3-NEXT: store ptr @.offload_sizes.5, ptr [[TMP109]], align 4 2395 // CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 5 2396 // CHECK3-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP110]], align 4 2397 // CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 6 2398 // CHECK3-NEXT: store ptr null, ptr [[TMP111]], align 4 2399 // CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 7 2400 // CHECK3-NEXT: store ptr null, ptr [[TMP112]], align 4 2401 // CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 8 2402 // CHECK3-NEXT: store i64 0, ptr [[TMP113]], align 8 2403 // CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 9 2404 // CHECK3-NEXT: store i64 0, ptr [[TMP114]], align 8 2405 // CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 10 2406 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP115]], align 4 2407 // CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 11 2408 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP116]], align 4 2409 // CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 12 2410 // CHECK3-NEXT: store i32 0, ptr [[TMP117]], align 4 2411 // CHECK3-NEXT: [[TMP118:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.region_id, ptr [[KERNEL_ARGS21]]) 2412 // CHECK3-NEXT: [[TMP119:%.*]] = icmp ne i32 [[TMP118]], 0 2413 // CHECK3-NEXT: br i1 [[TMP119]], label [[OMP_OFFLOAD_FAILED22:%.*]], label [[OMP_OFFLOAD_CONT23:%.*]] 2414 // CHECK3: omp_offload.failed22: 2415 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124(i32 [[TMP94]], i32 [[TMP96]]) #[[ATTR3]] 2416 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT23]] 2417 // CHECK3: omp_offload.cont23: 2418 // CHECK3-NEXT: [[TMP120:%.*]] = load i32, ptr [[A]], align 4 2419 // CHECK3-NEXT: store i32 [[TMP120]], ptr [[A_CASTED24]], align 4 2420 // CHECK3-NEXT: [[TMP121:%.*]] = load i32, ptr [[A_CASTED24]], align 4 2421 // CHECK3-NEXT: [[TMP122:%.*]] = load i16, ptr [[AA]], align 2 2422 // CHECK3-NEXT: store i16 [[TMP122]], ptr [[AA_CASTED25]], align 2 2423 // CHECK3-NEXT: [[TMP123:%.*]] = load i32, ptr [[AA_CASTED25]], align 4 2424 // CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0 2425 // CHECK3-NEXT: store i32 [[TMP121]], ptr [[TMP124]], align 4 2426 // CHECK3-NEXT: [[TMP125:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS27]], i32 0, i32 0 2427 // CHECK3-NEXT: store i32 [[TMP121]], ptr [[TMP125]], align 4 2428 // CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS28]], i32 0, i32 0 2429 // CHECK3-NEXT: store ptr null, ptr [[TMP126]], align 4 2430 // CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 1 2431 // CHECK3-NEXT: store i32 [[TMP123]], ptr [[TMP127]], align 4 2432 // CHECK3-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS27]], i32 0, i32 1 2433 // CHECK3-NEXT: store i32 [[TMP123]], ptr [[TMP128]], align 4 2434 // CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS28]], i32 0, i32 1 2435 // CHECK3-NEXT: store ptr null, ptr [[TMP129]], align 4 2436 // CHECK3-NEXT: [[TMP130:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0 2437 // CHECK3-NEXT: [[TMP131:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS27]], i32 0, i32 0 2438 // CHECK3-NEXT: [[TMP132:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 0 2439 // CHECK3-NEXT: store i32 3, ptr [[TMP132]], align 4 2440 // CHECK3-NEXT: [[TMP133:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 1 2441 // CHECK3-NEXT: store i32 2, ptr [[TMP133]], align 4 2442 // CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 2 2443 // CHECK3-NEXT: store ptr [[TMP130]], ptr [[TMP134]], align 4 2444 // CHECK3-NEXT: [[TMP135:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 3 2445 // CHECK3-NEXT: store ptr [[TMP131]], ptr [[TMP135]], align 4 2446 // CHECK3-NEXT: [[TMP136:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 4 2447 // CHECK3-NEXT: store ptr @.offload_sizes.7, ptr [[TMP136]], align 4 2448 // CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 5 2449 // CHECK3-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP137]], align 4 2450 // CHECK3-NEXT: [[TMP138:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 6 2451 // CHECK3-NEXT: store ptr null, ptr [[TMP138]], align 4 2452 // CHECK3-NEXT: [[TMP139:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 7 2453 // CHECK3-NEXT: store ptr null, ptr [[TMP139]], align 4 2454 // CHECK3-NEXT: [[TMP140:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 8 2455 // CHECK3-NEXT: store i64 0, ptr [[TMP140]], align 8 2456 // CHECK3-NEXT: [[TMP141:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 9 2457 // CHECK3-NEXT: store i64 0, ptr [[TMP141]], align 8 2458 // CHECK3-NEXT: [[TMP142:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 10 2459 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 2, i32 0], ptr [[TMP142]], align 4 2460 // CHECK3-NEXT: [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 11 2461 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 2, i32 0], ptr [[TMP143]], align 4 2462 // CHECK3-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 12 2463 // CHECK3-NEXT: store i32 0, ptr [[TMP144]], align 4 2464 // CHECK3-NEXT: [[TMP145:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.region_id, ptr [[KERNEL_ARGS29]]) 2465 // CHECK3-NEXT: [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 0 2466 // CHECK3-NEXT: br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] 2467 // CHECK3: omp_offload.failed30: 2468 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130(i32 [[TMP121]], i32 [[TMP123]]) #[[ATTR3]] 2469 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT31]] 2470 // CHECK3: omp_offload.cont31: 2471 // CHECK3-NEXT: [[TMP147:%.*]] = load i32, ptr [[A]], align 4 2472 // CHECK3-NEXT: store i32 [[TMP147]], ptr [[A_CASTED32]], align 4 2473 // CHECK3-NEXT: [[TMP148:%.*]] = load i32, ptr [[A_CASTED32]], align 4 2474 // CHECK3-NEXT: [[TMP149:%.*]] = load i16, ptr [[AA]], align 2 2475 // CHECK3-NEXT: store i16 [[TMP149]], ptr [[AA_CASTED33]], align 2 2476 // CHECK3-NEXT: [[TMP150:%.*]] = load i32, ptr [[AA_CASTED33]], align 4 2477 // CHECK3-NEXT: [[TMP151:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 2478 // CHECK3-NEXT: store i32 [[TMP148]], ptr [[TMP151]], align 4 2479 // CHECK3-NEXT: [[TMP152:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 2480 // CHECK3-NEXT: store i32 [[TMP148]], ptr [[TMP152]], align 4 2481 // CHECK3-NEXT: [[TMP153:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS36]], i32 0, i32 0 2482 // CHECK3-NEXT: store ptr null, ptr [[TMP153]], align 4 2483 // CHECK3-NEXT: [[TMP154:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 1 2484 // CHECK3-NEXT: store i32 [[TMP150]], ptr [[TMP154]], align 4 2485 // CHECK3-NEXT: [[TMP155:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS35]], i32 0, i32 1 2486 // CHECK3-NEXT: store i32 [[TMP150]], ptr [[TMP155]], align 4 2487 // CHECK3-NEXT: [[TMP156:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS36]], i32 0, i32 1 2488 // CHECK3-NEXT: store ptr null, ptr [[TMP156]], align 4 2489 // CHECK3-NEXT: [[TMP157:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0 2490 // CHECK3-NEXT: [[TMP158:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS35]], i32 0, i32 0 2491 // CHECK3-NEXT: [[TMP159:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 0 2492 // CHECK3-NEXT: store i32 3, ptr [[TMP159]], align 4 2493 // CHECK3-NEXT: [[TMP160:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 1 2494 // CHECK3-NEXT: store i32 2, ptr [[TMP160]], align 4 2495 // CHECK3-NEXT: [[TMP161:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 2 2496 // CHECK3-NEXT: store ptr [[TMP157]], ptr [[TMP161]], align 4 2497 // CHECK3-NEXT: [[TMP162:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 3 2498 // CHECK3-NEXT: store ptr [[TMP158]], ptr [[TMP162]], align 4 2499 // CHECK3-NEXT: [[TMP163:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 4 2500 // CHECK3-NEXT: store ptr @.offload_sizes.9, ptr [[TMP163]], align 4 2501 // CHECK3-NEXT: [[TMP164:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 5 2502 // CHECK3-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP164]], align 4 2503 // CHECK3-NEXT: [[TMP165:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 6 2504 // CHECK3-NEXT: store ptr null, ptr [[TMP165]], align 4 2505 // CHECK3-NEXT: [[TMP166:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 7 2506 // CHECK3-NEXT: store ptr null, ptr [[TMP166]], align 4 2507 // CHECK3-NEXT: [[TMP167:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 8 2508 // CHECK3-NEXT: store i64 0, ptr [[TMP167]], align 8 2509 // CHECK3-NEXT: [[TMP168:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 9 2510 // CHECK3-NEXT: store i64 0, ptr [[TMP168]], align 8 2511 // CHECK3-NEXT: [[TMP169:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 10 2512 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 2, i32 3], ptr [[TMP169]], align 4 2513 // CHECK3-NEXT: [[TMP170:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 11 2514 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 2, i32 3], ptr [[TMP170]], align 4 2515 // CHECK3-NEXT: [[TMP171:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 12 2516 // CHECK3-NEXT: store i32 0, ptr [[TMP171]], align 4 2517 // CHECK3-NEXT: [[TMP172:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.region_id, ptr [[KERNEL_ARGS37]]) 2518 // CHECK3-NEXT: [[TMP173:%.*]] = icmp ne i32 [[TMP172]], 0 2519 // CHECK3-NEXT: br i1 [[TMP173]], label [[OMP_OFFLOAD_FAILED38:%.*]], label [[OMP_OFFLOAD_CONT39:%.*]] 2520 // CHECK3: omp_offload.failed38: 2521 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP148]], i32 [[TMP150]]) #[[ATTR3]] 2522 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT39]] 2523 // CHECK3: omp_offload.cont39: 2524 // CHECK3-NEXT: [[TMP174:%.*]] = load i32, ptr [[A]], align 4 2525 // CHECK3-NEXT: store i32 [[TMP174]], ptr [[A_CASTED40]], align 4 2526 // CHECK3-NEXT: [[TMP175:%.*]] = load i32, ptr [[A_CASTED40]], align 4 2527 // CHECK3-NEXT: [[TMP176:%.*]] = load i32, ptr [[N_ADDR]], align 4 2528 // CHECK3-NEXT: [[CMP41:%.*]] = icmp sgt i32 [[TMP176]], 20 2529 // CHECK3-NEXT: br i1 [[CMP41]], label [[OMP_IF_THEN42:%.*]], label [[OMP_IF_ELSE49:%.*]] 2530 // CHECK3: omp_if.then42: 2531 // CHECK3-NEXT: [[TMP177:%.*]] = mul nuw i32 [[TMP1]], 4 2532 // CHECK3-NEXT: [[TMP178:%.*]] = sext i32 [[TMP177]] to i64 2533 // CHECK3-NEXT: [[TMP179:%.*]] = mul nuw i32 5, [[TMP3]] 2534 // CHECK3-NEXT: [[TMP180:%.*]] = mul nuw i32 [[TMP179]], 8 2535 // CHECK3-NEXT: [[TMP181:%.*]] = sext i32 [[TMP180]] to i64 2536 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.11, i32 72, i1 false) 2537 // CHECK3-NEXT: [[TMP182:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 0 2538 // CHECK3-NEXT: store i32 [[TMP175]], ptr [[TMP182]], align 4 2539 // CHECK3-NEXT: [[TMP183:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 0 2540 // CHECK3-NEXT: store i32 [[TMP175]], ptr [[TMP183]], align 4 2541 // CHECK3-NEXT: [[TMP184:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i32 0, i32 0 2542 // CHECK3-NEXT: store ptr null, ptr [[TMP184]], align 4 2543 // CHECK3-NEXT: [[TMP185:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 1 2544 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP185]], align 4 2545 // CHECK3-NEXT: [[TMP186:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 1 2546 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP186]], align 4 2547 // CHECK3-NEXT: [[TMP187:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i32 0, i32 1 2548 // CHECK3-NEXT: store ptr null, ptr [[TMP187]], align 4 2549 // CHECK3-NEXT: [[TMP188:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 2 2550 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP188]], align 4 2551 // CHECK3-NEXT: [[TMP189:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 2 2552 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP189]], align 4 2553 // CHECK3-NEXT: [[TMP190:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i32 0, i32 2 2554 // CHECK3-NEXT: store ptr null, ptr [[TMP190]], align 4 2555 // CHECK3-NEXT: [[TMP191:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 3 2556 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP191]], align 4 2557 // CHECK3-NEXT: [[TMP192:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 3 2558 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP192]], align 4 2559 // CHECK3-NEXT: [[TMP193:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 2560 // CHECK3-NEXT: store i64 [[TMP178]], ptr [[TMP193]], align 4 2561 // CHECK3-NEXT: [[TMP194:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i32 0, i32 3 2562 // CHECK3-NEXT: store ptr null, ptr [[TMP194]], align 4 2563 // CHECK3-NEXT: [[TMP195:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 4 2564 // CHECK3-NEXT: store ptr [[C]], ptr [[TMP195]], align 4 2565 // CHECK3-NEXT: [[TMP196:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 4 2566 // CHECK3-NEXT: store ptr [[C]], ptr [[TMP196]], align 4 2567 // CHECK3-NEXT: [[TMP197:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i32 0, i32 4 2568 // CHECK3-NEXT: store ptr null, ptr [[TMP197]], align 4 2569 // CHECK3-NEXT: [[TMP198:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 5 2570 // CHECK3-NEXT: store i32 5, ptr [[TMP198]], align 4 2571 // CHECK3-NEXT: [[TMP199:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 5 2572 // CHECK3-NEXT: store i32 5, ptr [[TMP199]], align 4 2573 // CHECK3-NEXT: [[TMP200:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i32 0, i32 5 2574 // CHECK3-NEXT: store ptr null, ptr [[TMP200]], align 4 2575 // CHECK3-NEXT: [[TMP201:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 6 2576 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP201]], align 4 2577 // CHECK3-NEXT: [[TMP202:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 6 2578 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP202]], align 4 2579 // CHECK3-NEXT: [[TMP203:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i32 0, i32 6 2580 // CHECK3-NEXT: store ptr null, ptr [[TMP203]], align 4 2581 // CHECK3-NEXT: [[TMP204:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 7 2582 // CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP204]], align 4 2583 // CHECK3-NEXT: [[TMP205:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 7 2584 // CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP205]], align 4 2585 // CHECK3-NEXT: [[TMP206:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 2586 // CHECK3-NEXT: store i64 [[TMP181]], ptr [[TMP206]], align 4 2587 // CHECK3-NEXT: [[TMP207:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i32 0, i32 7 2588 // CHECK3-NEXT: store ptr null, ptr [[TMP207]], align 4 2589 // CHECK3-NEXT: [[TMP208:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 8 2590 // CHECK3-NEXT: store ptr [[D]], ptr [[TMP208]], align 4 2591 // CHECK3-NEXT: [[TMP209:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 8 2592 // CHECK3-NEXT: store ptr [[D]], ptr [[TMP209]], align 4 2593 // CHECK3-NEXT: [[TMP210:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i32 0, i32 8 2594 // CHECK3-NEXT: store ptr null, ptr [[TMP210]], align 4 2595 // CHECK3-NEXT: [[TMP211:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 0 2596 // CHECK3-NEXT: [[TMP212:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 0 2597 // CHECK3-NEXT: [[TMP213:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2598 // CHECK3-NEXT: [[TMP214:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 0 2599 // CHECK3-NEXT: store i32 3, ptr [[TMP214]], align 4 2600 // CHECK3-NEXT: [[TMP215:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 1 2601 // CHECK3-NEXT: store i32 9, ptr [[TMP215]], align 4 2602 // CHECK3-NEXT: [[TMP216:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 2 2603 // CHECK3-NEXT: store ptr [[TMP211]], ptr [[TMP216]], align 4 2604 // CHECK3-NEXT: [[TMP217:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 3 2605 // CHECK3-NEXT: store ptr [[TMP212]], ptr [[TMP217]], align 4 2606 // CHECK3-NEXT: [[TMP218:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 4 2607 // CHECK3-NEXT: store ptr [[TMP213]], ptr [[TMP218]], align 4 2608 // CHECK3-NEXT: [[TMP219:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 5 2609 // CHECK3-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP219]], align 4 2610 // CHECK3-NEXT: [[TMP220:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 6 2611 // CHECK3-NEXT: store ptr null, ptr [[TMP220]], align 4 2612 // CHECK3-NEXT: [[TMP221:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 7 2613 // CHECK3-NEXT: store ptr null, ptr [[TMP221]], align 4 2614 // CHECK3-NEXT: [[TMP222:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 8 2615 // CHECK3-NEXT: store i64 0, ptr [[TMP222]], align 8 2616 // CHECK3-NEXT: [[TMP223:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 9 2617 // CHECK3-NEXT: store i64 0, ptr [[TMP223]], align 8 2618 // CHECK3-NEXT: [[TMP224:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 10 2619 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP224]], align 4 2620 // CHECK3-NEXT: [[TMP225:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 11 2621 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP225]], align 4 2622 // CHECK3-NEXT: [[TMP226:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 12 2623 // CHECK3-NEXT: store i32 0, ptr [[TMP226]], align 4 2624 // CHECK3-NEXT: [[TMP227:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.region_id, ptr [[KERNEL_ARGS46]]) 2625 // CHECK3-NEXT: [[TMP228:%.*]] = icmp ne i32 [[TMP227]], 0 2626 // CHECK3-NEXT: br i1 [[TMP228]], label [[OMP_OFFLOAD_FAILED47:%.*]], label [[OMP_OFFLOAD_CONT48:%.*]] 2627 // CHECK3: omp_offload.failed47: 2628 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP175]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] 2629 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT48]] 2630 // CHECK3: omp_offload.cont48: 2631 // CHECK3-NEXT: br label [[OMP_IF_END50:%.*]] 2632 // CHECK3: omp_if.else49: 2633 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP175]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] 2634 // CHECK3-NEXT: br label [[OMP_IF_END50]] 2635 // CHECK3: omp_if.end50: 2636 // CHECK3-NEXT: store i32 0, ptr [[NN]], align 4 2637 // CHECK3-NEXT: [[TMP229:%.*]] = load i32, ptr [[NN]], align 4 2638 // CHECK3-NEXT: store i32 [[TMP229]], ptr [[NN_CASTED]], align 4 2639 // CHECK3-NEXT: [[TMP230:%.*]] = load i32, ptr [[NN_CASTED]], align 4 2640 // CHECK3-NEXT: [[TMP231:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS51]], i32 0, i32 0 2641 // CHECK3-NEXT: store i32 [[TMP230]], ptr [[TMP231]], align 4 2642 // CHECK3-NEXT: [[TMP232:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS52]], i32 0, i32 0 2643 // CHECK3-NEXT: store i32 [[TMP230]], ptr [[TMP232]], align 4 2644 // CHECK3-NEXT: [[TMP233:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS53]], i32 0, i32 0 2645 // CHECK3-NEXT: store ptr null, ptr [[TMP233]], align 4 2646 // CHECK3-NEXT: [[TMP234:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS51]], i32 0, i32 0 2647 // CHECK3-NEXT: [[TMP235:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS52]], i32 0, i32 0 2648 // CHECK3-NEXT: [[TMP236:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 0 2649 // CHECK3-NEXT: store i32 3, ptr [[TMP236]], align 4 2650 // CHECK3-NEXT: [[TMP237:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 1 2651 // CHECK3-NEXT: store i32 1, ptr [[TMP237]], align 4 2652 // CHECK3-NEXT: [[TMP238:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 2 2653 // CHECK3-NEXT: store ptr [[TMP234]], ptr [[TMP238]], align 4 2654 // CHECK3-NEXT: [[TMP239:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 3 2655 // CHECK3-NEXT: store ptr [[TMP235]], ptr [[TMP239]], align 4 2656 // CHECK3-NEXT: [[TMP240:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 4 2657 // CHECK3-NEXT: store ptr @.offload_sizes.13, ptr [[TMP240]], align 4 2658 // CHECK3-NEXT: [[TMP241:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 5 2659 // CHECK3-NEXT: store ptr @.offload_maptypes.14, ptr [[TMP241]], align 4 2660 // CHECK3-NEXT: [[TMP242:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 6 2661 // CHECK3-NEXT: store ptr null, ptr [[TMP242]], align 4 2662 // CHECK3-NEXT: [[TMP243:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 7 2663 // CHECK3-NEXT: store ptr null, ptr [[TMP243]], align 4 2664 // CHECK3-NEXT: [[TMP244:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 8 2665 // CHECK3-NEXT: store i64 0, ptr [[TMP244]], align 8 2666 // CHECK3-NEXT: [[TMP245:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 9 2667 // CHECK3-NEXT: store i64 0, ptr [[TMP245]], align 8 2668 // CHECK3-NEXT: [[TMP246:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 10 2669 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP246]], align 4 2670 // CHECK3-NEXT: [[TMP247:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 11 2671 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP247]], align 4 2672 // CHECK3-NEXT: [[TMP248:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 12 2673 // CHECK3-NEXT: store i32 0, ptr [[TMP248]], align 4 2674 // CHECK3-NEXT: [[TMP249:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.region_id, ptr [[KERNEL_ARGS54]]) 2675 // CHECK3-NEXT: [[TMP250:%.*]] = icmp ne i32 [[TMP249]], 0 2676 // CHECK3-NEXT: br i1 [[TMP250]], label [[OMP_OFFLOAD_FAILED55:%.*]], label [[OMP_OFFLOAD_CONT56:%.*]] 2677 // CHECK3: omp_offload.failed55: 2678 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172(i32 [[TMP230]]) #[[ATTR3]] 2679 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT56]] 2680 // CHECK3: omp_offload.cont56: 2681 // CHECK3-NEXT: [[TMP251:%.*]] = load i32, ptr [[NN]], align 4 2682 // CHECK3-NEXT: store i32 [[TMP251]], ptr [[NN_CASTED57]], align 4 2683 // CHECK3-NEXT: [[TMP252:%.*]] = load i32, ptr [[NN_CASTED57]], align 4 2684 // CHECK3-NEXT: [[TMP253:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS58]], i32 0, i32 0 2685 // CHECK3-NEXT: store i32 [[TMP252]], ptr [[TMP253]], align 4 2686 // CHECK3-NEXT: [[TMP254:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS59]], i32 0, i32 0 2687 // CHECK3-NEXT: store i32 [[TMP252]], ptr [[TMP254]], align 4 2688 // CHECK3-NEXT: [[TMP255:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS60]], i32 0, i32 0 2689 // CHECK3-NEXT: store ptr null, ptr [[TMP255]], align 4 2690 // CHECK3-NEXT: [[TMP256:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS58]], i32 0, i32 0 2691 // CHECK3-NEXT: [[TMP257:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS59]], i32 0, i32 0 2692 // CHECK3-NEXT: [[TMP258:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 0 2693 // CHECK3-NEXT: store i32 3, ptr [[TMP258]], align 4 2694 // CHECK3-NEXT: [[TMP259:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 1 2695 // CHECK3-NEXT: store i32 1, ptr [[TMP259]], align 4 2696 // CHECK3-NEXT: [[TMP260:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 2 2697 // CHECK3-NEXT: store ptr [[TMP256]], ptr [[TMP260]], align 4 2698 // CHECK3-NEXT: [[TMP261:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 3 2699 // CHECK3-NEXT: store ptr [[TMP257]], ptr [[TMP261]], align 4 2700 // CHECK3-NEXT: [[TMP262:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 4 2701 // CHECK3-NEXT: store ptr @.offload_sizes.15, ptr [[TMP262]], align 4 2702 // CHECK3-NEXT: [[TMP263:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 5 2703 // CHECK3-NEXT: store ptr @.offload_maptypes.16, ptr [[TMP263]], align 4 2704 // CHECK3-NEXT: [[TMP264:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 6 2705 // CHECK3-NEXT: store ptr null, ptr [[TMP264]], align 4 2706 // CHECK3-NEXT: [[TMP265:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 7 2707 // CHECK3-NEXT: store ptr null, ptr [[TMP265]], align 4 2708 // CHECK3-NEXT: [[TMP266:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 8 2709 // CHECK3-NEXT: store i64 0, ptr [[TMP266]], align 8 2710 // CHECK3-NEXT: [[TMP267:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 9 2711 // CHECK3-NEXT: store i64 0, ptr [[TMP267]], align 8 2712 // CHECK3-NEXT: [[TMP268:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 10 2713 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP268]], align 4 2714 // CHECK3-NEXT: [[TMP269:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 11 2715 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP269]], align 4 2716 // CHECK3-NEXT: [[TMP270:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 12 2717 // CHECK3-NEXT: store i32 0, ptr [[TMP270]], align 4 2718 // CHECK3-NEXT: [[TMP271:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.region_id, ptr [[KERNEL_ARGS61]]) 2719 // CHECK3-NEXT: [[TMP272:%.*]] = icmp ne i32 [[TMP271]], 0 2720 // CHECK3-NEXT: br i1 [[TMP272]], label [[OMP_OFFLOAD_FAILED62:%.*]], label [[OMP_OFFLOAD_CONT63:%.*]] 2721 // CHECK3: omp_offload.failed62: 2722 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175(i32 [[TMP252]]) #[[ATTR3]] 2723 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT63]] 2724 // CHECK3: omp_offload.cont63: 2725 // CHECK3-NEXT: [[TMP273:%.*]] = load i32, ptr [[A]], align 4 2726 // CHECK3-NEXT: [[TMP274:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 2727 // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP274]]) 2728 // CHECK3-NEXT: ret i32 [[TMP273]] 2729 // 2730 // 2731 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 2732 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 2733 // CHECK3-NEXT: entry: 2734 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2735 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2736 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 2737 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2738 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 2739 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2740 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2741 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 2742 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2743 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 2744 // CHECK3-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 2745 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2746 // CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 2747 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 2748 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i32 [[TMP4]]) 2749 // CHECK3-NEXT: ret void 2750 // 2751 // 2752 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined 2753 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2754 // CHECK3-NEXT: entry: 2755 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2756 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2757 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2758 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2759 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2760 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2761 // CHECK3-NEXT: ret void 2762 // 2763 // 2764 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. 2765 // CHECK3-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 2766 // CHECK3-NEXT: entry: 2767 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 2768 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 2769 // CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 4 2770 // CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 4 2771 // CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 4 2772 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 2773 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 2774 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 4 2775 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 4 2776 // CHECK3-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 4 2777 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 4 2778 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0 2779 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR4]], align 4 2780 // CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 4 2781 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1 2782 // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 4 2783 // CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 4 2784 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2 2785 // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 4 2786 // CHECK3-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 4 2787 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3 2788 // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 2789 // CHECK3-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 4 2790 // CHECK3-NEXT: ret void 2791 // 2792 // 2793 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 2794 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 2795 // CHECK3-NEXT: entry: 2796 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 2797 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4 2798 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4 2799 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4 2800 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4 2801 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4 2802 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 4 2803 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 4 2804 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 4 2805 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 4 2806 // CHECK3-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2807 // CHECK3-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 2808 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 2809 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 2810 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 2811 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 2812 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 2813 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 2814 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 2815 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 2816 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 2817 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 2818 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 2819 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 2820 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 2821 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 2822 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 2823 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) 2824 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]]) 2825 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META28:![0-9]+]] 2826 // CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias [[META28]] 2827 // CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META28]] 2828 // CHECK3-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META28]] 2829 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias [[META28]] 2830 // CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META28]] 2831 // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META28]] 2832 // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META28]] 2833 // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META28]] 2834 // CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 2835 // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias [[META28]] 2836 // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META28]] 2837 // CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META28]] 2838 // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias [[META28]] 2839 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1 2840 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2 2841 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4 2842 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP17]], align 4 2843 // CHECK3-NEXT: [[TMP20:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 0 2844 // CHECK3-NEXT: [[TMP21:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP19]], 0 2845 // CHECK3-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META28]] 2846 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 2847 // CHECK3-NEXT: store i32 3, ptr [[TMP22]], align 4, !noalias [[META28]] 2848 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 2849 // CHECK3-NEXT: store ptr [[TMP13]], ptr [[TMP23]], align 4, !noalias [[META28]] 2850 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 2851 // CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP24]], align 4, !noalias [[META28]] 2852 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 2853 // CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP25]], align 4, !noalias [[META28]] 2854 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 2855 // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 4, !noalias [[META28]] 2856 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 2857 // CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 4, !noalias [[META28]] 2858 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 2859 // CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 4, !noalias [[META28]] 2860 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 2861 // CHECK3-NEXT: store i64 0, ptr [[TMP29]], align 8, !noalias [[META28]] 2862 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9 2863 // CHECK3-NEXT: store i64 1, ptr [[TMP30]], align 8, !noalias [[META28]] 2864 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10 2865 // CHECK3-NEXT: store [3 x i32] [[TMP20]], ptr [[TMP31]], align 4, !noalias [[META28]] 2866 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11 2867 // CHECK3-NEXT: store [3 x i32] [[TMP21]], ptr [[TMP32]], align 4, !noalias [[META28]] 2868 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12 2869 // CHECK3-NEXT: store i32 0, ptr [[TMP33]], align 4, !noalias [[META28]] 2870 // CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 [[TMP18]], i32 [[TMP19]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, ptr [[KERNEL_ARGS_I]]) 2871 // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 2872 // CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] 2873 // CHECK3: omp_offload.failed.i: 2874 // CHECK3-NEXT: [[TMP36:%.*]] = load i16, ptr [[TMP12]], align 2 2875 // CHECK3-NEXT: store i16 [[TMP36]], ptr [[AA_CASTED_I]], align 2, !noalias [[META28]] 2876 // CHECK3-NEXT: [[TMP37:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias [[META28]] 2877 // CHECK3-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP16]], align 4 2878 // CHECK3-NEXT: store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias [[META28]] 2879 // CHECK3-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias [[META28]] 2880 // CHECK3-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP17]], align 4 2881 // CHECK3-NEXT: store i32 [[TMP40]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias [[META28]] 2882 // CHECK3-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias [[META28]] 2883 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP37]], i32 [[TMP39]], i32 [[TMP41]]) #[[ATTR3]] 2884 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] 2885 // CHECK3: .omp_outlined..exit: 2886 // CHECK3-NEXT: ret i32 0 2887 // 2888 // 2889 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 2890 // CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { 2891 // CHECK3-NEXT: entry: 2892 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2893 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2894 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2895 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2896 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 2897 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 2898 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105.omp_outlined, i32 [[TMP1]]) 2899 // CHECK3-NEXT: ret void 2900 // 2901 // 2902 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105.omp_outlined 2903 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 2904 // CHECK3-NEXT: entry: 2905 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2906 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2907 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2908 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2909 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2910 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2911 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2912 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2913 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 2914 // CHECK3-NEXT: ret void 2915 // 2916 // 2917 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 2918 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2919 // CHECK3-NEXT: entry: 2920 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2921 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2922 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2923 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2924 // CHECK3-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 2925 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 2926 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP1]]) 2927 // CHECK3-NEXT: ret void 2928 // 2929 // 2930 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined 2931 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2932 // CHECK3-NEXT: entry: 2933 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2934 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2935 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2936 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2937 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2938 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2939 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2940 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 2941 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 2942 // CHECK3-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 2943 // CHECK3-NEXT: store i16 [[CONV1]], ptr [[AA_ADDR]], align 2 2944 // CHECK3-NEXT: ret void 2945 // 2946 // 2947 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 2948 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2949 // CHECK3-NEXT: entry: 2950 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2951 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2952 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2953 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2954 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2955 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2956 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2957 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 2958 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 2959 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2960 // CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 2961 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 2962 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) 2963 // CHECK3-NEXT: ret void 2964 // 2965 // 2966 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined 2967 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2968 // CHECK3-NEXT: entry: 2969 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2970 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2971 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2972 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2973 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2974 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2975 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2976 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2977 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2978 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2979 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 2980 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2981 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 2982 // CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 2983 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 2984 // CHECK3-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 2985 // CHECK3-NEXT: ret void 2986 // 2987 // 2988 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124 2989 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2990 // CHECK3-NEXT: entry: 2991 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2992 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2993 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2994 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2995 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 2996 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2997 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2998 // CHECK3-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1) 2999 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 3000 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 3001 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 3002 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3003 // CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 3004 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3005 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i32 [[TMP2]], i32 [[TMP4]]) 3006 // CHECK3-NEXT: ret void 3007 // 3008 // 3009 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined 3010 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 3011 // CHECK3-NEXT: entry: 3012 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3013 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3014 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3015 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3016 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3017 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3018 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3019 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3020 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3021 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3022 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 3023 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3024 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 3025 // CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 3026 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 3027 // CHECK3-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 3028 // CHECK3-NEXT: ret void 3029 // 3030 // 3031 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130 3032 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 3033 // CHECK3-NEXT: entry: 3034 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3035 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3036 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3037 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3038 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 3039 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3040 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3041 // CHECK3-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1) 3042 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 3043 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 3044 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 3045 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3046 // CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 3047 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3048 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined, i32 [[TMP2]], i32 [[TMP4]]) 3049 // CHECK3-NEXT: ret void 3050 // 3051 // 3052 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined 3053 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 3054 // CHECK3-NEXT: entry: 3055 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3056 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3057 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3058 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3059 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3060 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3061 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3062 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3063 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3064 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3065 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 3066 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3067 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 3068 // CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 3069 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 3070 // CHECK3-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 3071 // CHECK3-NEXT: ret void 3072 // 3073 // 3074 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136 3075 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 3076 // CHECK3-NEXT: entry: 3077 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3078 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3079 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3080 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3081 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 3082 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3083 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3084 // CHECK3-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1) 3085 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 3086 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 3087 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 3088 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3089 // CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 3090 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3091 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i32 [[TMP2]], i32 [[TMP4]]) 3092 // CHECK3-NEXT: ret void 3093 // 3094 // 3095 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined 3096 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 3097 // CHECK3-NEXT: entry: 3098 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3099 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3100 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3101 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3102 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3103 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3104 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3105 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3106 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3107 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3108 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 3109 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3110 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 3111 // CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 3112 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 3113 // CHECK3-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 3114 // CHECK3-NEXT: ret void 3115 // 3116 // 3117 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160 3118 // CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 3119 // CHECK3-NEXT: entry: 3120 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3121 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3122 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3123 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 3124 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3125 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3126 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 3127 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 3128 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 3129 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3130 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3131 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3132 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 3133 // CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 3134 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3135 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 3136 // CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 3137 // CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 3138 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 3139 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3140 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 3141 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 3142 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 3143 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 3144 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 3145 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 3146 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 3147 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 3148 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 3149 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 3150 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]]) 3151 // CHECK3-NEXT: ret void 3152 // 3153 // 3154 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined 3155 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 3156 // CHECK3-NEXT: entry: 3157 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3158 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3159 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3160 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3161 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3162 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 3163 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3164 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3165 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 3166 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 3167 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 3168 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3169 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3170 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3171 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3172 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 3173 // CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 3174 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3175 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 3176 // CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 3177 // CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 3178 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 3179 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3180 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 3181 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 3182 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 3183 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 3184 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 3185 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 3186 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 3187 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 3188 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 3189 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 3190 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 3191 // CHECK3-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4 3192 // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 3193 // CHECK3-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 3194 // CHECK3-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 3195 // CHECK3-NEXT: store float [[CONV6]], ptr [[ARRAYIDX]], align 4 3196 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 3197 // CHECK3-NEXT: [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 4 3198 // CHECK3-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 3199 // CHECK3-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 3200 // CHECK3-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 3201 // CHECK3-NEXT: store float [[CONV10]], ptr [[ARRAYIDX7]], align 4 3202 // CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 3203 // CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i32 0, i32 2 3204 // CHECK3-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8 3205 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 3206 // CHECK3-NEXT: store double [[ADD13]], ptr [[ARRAYIDX12]], align 8 3207 // CHECK3-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 3208 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP12]] 3209 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3 3210 // CHECK3-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 8 3211 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 3212 // CHECK3-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8 3213 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 3214 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, ptr [[X]], align 4 3215 // CHECK3-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 3216 // CHECK3-NEXT: store i64 [[ADD17]], ptr [[X]], align 4 3217 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 3218 // CHECK3-NEXT: [[TMP15:%.*]] = load i8, ptr [[Y]], align 4 3219 // CHECK3-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 3220 // CHECK3-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 3221 // CHECK3-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 3222 // CHECK3-NEXT: store i8 [[CONV20]], ptr [[Y]], align 4 3223 // CHECK3-NEXT: ret void 3224 // 3225 // 3226 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172 3227 // CHECK3-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { 3228 // CHECK3-NEXT: entry: 3229 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3230 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 3231 // CHECK3-NEXT: store i32 [[NN]], ptr [[NN_ADDR]], align 4 3232 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4 3233 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[NN_CASTED]], align 4 3234 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 4 3235 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined, i32 [[TMP1]]) 3236 // CHECK3-NEXT: ret void 3237 // 3238 // 3239 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined 3240 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 3241 // CHECK3-NEXT: entry: 3242 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3243 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3244 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3245 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 3246 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3247 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3248 // CHECK3-NEXT: store i32 [[NN]], ptr [[NN_ADDR]], align 4 3249 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4 3250 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[NN_CASTED]], align 4 3251 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 4 3252 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined.omp_outlined, i32 [[TMP1]]) 3253 // CHECK3-NEXT: ret void 3254 // 3255 // 3256 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined.omp_outlined 3257 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 3258 // CHECK3-NEXT: entry: 3259 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3260 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3261 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3262 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3263 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3264 // CHECK3-NEXT: store i32 [[NN]], ptr [[NN_ADDR]], align 4 3265 // CHECK3-NEXT: ret void 3266 // 3267 // 3268 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175 3269 // CHECK3-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { 3270 // CHECK3-NEXT: entry: 3271 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3272 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 3273 // CHECK3-NEXT: store i32 [[NN]], ptr [[NN_ADDR]], align 4 3274 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4 3275 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[NN_CASTED]], align 4 3276 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 4 3277 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined, i32 [[TMP1]]) 3278 // CHECK3-NEXT: ret void 3279 // 3280 // 3281 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined 3282 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 3283 // CHECK3-NEXT: entry: 3284 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3285 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3286 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3287 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3288 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3289 // CHECK3-NEXT: store i32 [[NN]], ptr [[NN_ADDR]], align 4 3290 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined.omp_outlined, ptr [[NN_ADDR]]) 3291 // CHECK3-NEXT: ret void 3292 // 3293 // 3294 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined.omp_outlined 3295 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 3296 // CHECK3-NEXT: entry: 3297 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3298 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3299 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca ptr, align 4 3300 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3301 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3302 // CHECK3-NEXT: store ptr [[NN]], ptr [[NN_ADDR]], align 4 3303 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[NN_ADDR]], align 4 3304 // CHECK3-NEXT: ret void 3305 // 3306 // 3307 // CHECK3-LABEL: define {{[^@]+}}@_Z6bazzzziPi 3308 // CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef [[F:%.*]]) #[[ATTR0]] { 3309 // CHECK3-NEXT: entry: 3310 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3311 // CHECK3-NEXT: [[F_ADDR:%.*]] = alloca ptr, align 4 3312 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 3313 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 3314 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 3315 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3316 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 3317 // CHECK3-NEXT: store ptr [[F]], ptr [[F_ADDR]], align 4 3318 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 3319 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3320 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[TMP1]], align 4 3321 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3322 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[TMP2]], align 4 3323 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3324 // CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4 3325 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3326 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3327 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3328 // CHECK3-NEXT: store i32 3, ptr [[TMP6]], align 4 3329 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3330 // CHECK3-NEXT: store i32 1, ptr [[TMP7]], align 4 3331 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3332 // CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4 3333 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3334 // CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4 3335 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3336 // CHECK3-NEXT: store ptr @.offload_sizes.17, ptr [[TMP10]], align 4 3337 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3338 // CHECK3-NEXT: store ptr @.offload_maptypes.18, ptr [[TMP11]], align 4 3339 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3340 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 3341 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3342 // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4 3343 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3344 // CHECK3-NEXT: store i64 0, ptr [[TMP14]], align 8 3345 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 3346 // CHECK3-NEXT: store i64 0, ptr [[TMP15]], align 8 3347 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 3348 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 3349 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 3350 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 3351 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 3352 // CHECK3-NEXT: store i32 0, ptr [[TMP18]], align 4 3353 // CHECK3-NEXT: [[TMP19:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.region_id, ptr [[KERNEL_ARGS]]) 3354 // CHECK3-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0 3355 // CHECK3-NEXT: br i1 [[TMP20]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3356 // CHECK3: omp_offload.failed: 3357 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200(i32 [[TMP0]]) #[[ATTR3]] 3358 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3359 // CHECK3: omp_offload.cont: 3360 // CHECK3-NEXT: ret void 3361 // 3362 // 3363 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200 3364 // CHECK3-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR2]] { 3365 // CHECK3-NEXT: entry: 3366 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3367 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 3368 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 3369 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined, i32 [[TMP0]]) 3370 // CHECK3-NEXT: ret void 3371 // 3372 // 3373 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined 3374 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR2]] { 3375 // CHECK3-NEXT: entry: 3376 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3377 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3378 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3379 // CHECK3-NEXT: [[F:%.*]] = alloca ptr, align 4 3380 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3381 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3382 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 3383 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 3384 // CHECK3-NEXT: ret void 3385 // 3386 // 3387 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 3388 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 3389 // CHECK3-NEXT: entry: 3390 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3391 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3392 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 3393 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 3394 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 3395 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 3396 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 3397 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 3398 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 3399 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A]], align 4 3400 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 3401 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 3402 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 3403 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 3404 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 3405 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 3406 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 3407 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 3408 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 3409 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 3410 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 3411 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 3412 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 3413 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 3414 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 3415 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 3416 // CHECK3-NEXT: ret i32 [[TMP8]] 3417 // 3418 // 3419 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3420 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3421 // CHECK3-NEXT: entry: 3422 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3423 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3424 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 3425 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 3426 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 3427 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3428 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 3429 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 3430 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 3431 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 3432 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3433 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3434 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 3435 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3436 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 3437 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3438 // CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4 3439 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 3440 // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0() 3441 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 3442 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 3443 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 3444 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 3445 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 3446 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 3447 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 3448 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 3449 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 3450 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3451 // CHECK3: omp_if.then: 3452 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 3453 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 3454 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 3455 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 3456 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.19, i32 40, i1 false) 3457 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3458 // CHECK3-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 4 3459 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3460 // CHECK3-NEXT: store ptr [[A]], ptr [[TMP11]], align 4 3461 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3462 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 3463 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3464 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 4 3465 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3466 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 4 3467 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3468 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 3469 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3470 // CHECK3-NEXT: store i32 2, ptr [[TMP16]], align 4 3471 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3472 // CHECK3-NEXT: store i32 2, ptr [[TMP17]], align 4 3473 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3474 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 3475 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3476 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP19]], align 4 3477 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3478 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP20]], align 4 3479 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3480 // CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 4 3481 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3482 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 4 3483 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3484 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 4 3485 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 3486 // CHECK3-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 4 3487 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 3488 // CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4 3489 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3490 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3491 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3492 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3493 // CHECK3-NEXT: store i32 3, ptr [[TMP29]], align 4 3494 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3495 // CHECK3-NEXT: store i32 5, ptr [[TMP30]], align 4 3496 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3497 // CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 4 3498 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3499 // CHECK3-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 4 3500 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3501 // CHECK3-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 4 3502 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3503 // CHECK3-NEXT: store ptr @.offload_maptypes.20, ptr [[TMP34]], align 4 3504 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3505 // CHECK3-NEXT: store ptr null, ptr [[TMP35]], align 4 3506 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3507 // CHECK3-NEXT: store ptr null, ptr [[TMP36]], align 4 3508 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3509 // CHECK3-NEXT: store i64 0, ptr [[TMP37]], align 8 3510 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 3511 // CHECK3-NEXT: store i64 0, ptr [[TMP38]], align 8 3512 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 3513 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 4 3514 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 3515 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4 3516 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 3517 // CHECK3-NEXT: store i32 0, ptr [[TMP41]], align 4 3518 // CHECK3-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.region_id, ptr [[KERNEL_ARGS]]) 3519 // CHECK3-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 3520 // CHECK3-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3521 // CHECK3: omp_offload.failed: 3522 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] 3523 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3524 // CHECK3: omp_offload.cont: 3525 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3526 // CHECK3: omp_if.else: 3527 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] 3528 // CHECK3-NEXT: br label [[OMP_IF_END]] 3529 // CHECK3: omp_if.end: 3530 // CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]] 3531 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]] 3532 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 3533 // CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 3534 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 3535 // CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 3536 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] 3537 // CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 3538 // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]]) 3539 // CHECK3-NEXT: ret i32 [[ADD3]] 3540 // 3541 // 3542 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 3543 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 3544 // CHECK3-NEXT: entry: 3545 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3546 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3547 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3548 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 3549 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3550 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3551 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3552 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3553 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 3554 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 3555 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 3556 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3557 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 3558 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 3559 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 3560 // CHECK3-NEXT: store i8 0, ptr [[AAA]], align 1 3561 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 3562 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 3563 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 3564 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 3565 // CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 3566 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3567 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1 3568 // CHECK3-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1 3569 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 3570 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 3571 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 3572 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3573 // CHECK3: omp_if.then: 3574 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3575 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 4 3576 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3577 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 4 3578 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3579 // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 3580 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3581 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP10]], align 4 3582 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3583 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP11]], align 4 3584 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3585 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 3586 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3587 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 4 3588 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3589 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 4 3590 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3591 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 3592 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3593 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP16]], align 4 3594 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3595 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP17]], align 4 3596 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3597 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 3598 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3599 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3600 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3601 // CHECK3-NEXT: store i32 3, ptr [[TMP21]], align 4 3602 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3603 // CHECK3-NEXT: store i32 4, ptr [[TMP22]], align 4 3604 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3605 // CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4 3606 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3607 // CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4 3608 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3609 // CHECK3-NEXT: store ptr @.offload_sizes.21, ptr [[TMP25]], align 4 3610 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3611 // CHECK3-NEXT: store ptr @.offload_maptypes.22, ptr [[TMP26]], align 4 3612 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3613 // CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 4 3614 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3615 // CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 4 3616 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3617 // CHECK3-NEXT: store i64 0, ptr [[TMP29]], align 8 3618 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 3619 // CHECK3-NEXT: store i64 0, ptr [[TMP30]], align 8 3620 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 3621 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 3622 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 3623 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 3624 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 3625 // CHECK3-NEXT: store i32 0, ptr [[TMP33]], align 4 3626 // CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.region_id, ptr [[KERNEL_ARGS]]) 3627 // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 3628 // CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3629 // CHECK3: omp_offload.failed: 3630 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]] 3631 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3632 // CHECK3: omp_offload.cont: 3633 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3634 // CHECK3: omp_if.else: 3635 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]] 3636 // CHECK3-NEXT: br label [[OMP_IF_END]] 3637 // CHECK3: omp_if.end: 3638 // CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 3639 // CHECK3-NEXT: ret i32 [[TMP36]] 3640 // 3641 // 3642 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3643 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 3644 // CHECK3-NEXT: entry: 3645 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3646 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3647 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3648 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3649 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3650 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3651 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 3652 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 3653 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 3654 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3655 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 3656 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 3657 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 3658 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 3659 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 3660 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 3661 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 3662 // CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 3663 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3664 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 3665 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 3666 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3667 // CHECK3: omp_if.then: 3668 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3669 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 3670 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3671 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 4 3672 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3673 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 3674 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3675 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 4 3676 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3677 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP9]], align 4 3678 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3679 // CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 4 3680 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3681 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP11]], align 4 3682 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3683 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP12]], align 4 3684 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3685 // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4 3686 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3687 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3688 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3689 // CHECK3-NEXT: store i32 3, ptr [[TMP16]], align 4 3690 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3691 // CHECK3-NEXT: store i32 3, ptr [[TMP17]], align 4 3692 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3693 // CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4 3694 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3695 // CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 4 3696 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3697 // CHECK3-NEXT: store ptr @.offload_sizes.23, ptr [[TMP20]], align 4 3698 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3699 // CHECK3-NEXT: store ptr @.offload_maptypes.24, ptr [[TMP21]], align 4 3700 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3701 // CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 4 3702 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3703 // CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 4 3704 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3705 // CHECK3-NEXT: store i64 0, ptr [[TMP24]], align 8 3706 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 3707 // CHECK3-NEXT: store i64 0, ptr [[TMP25]], align 8 3708 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 3709 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 3710 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 3711 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 3712 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 3713 // CHECK3-NEXT: store i32 0, ptr [[TMP28]], align 4 3714 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.region_id, ptr [[KERNEL_ARGS]]) 3715 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 3716 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3717 // CHECK3: omp_offload.failed: 3718 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] 3719 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3720 // CHECK3: omp_offload.cont: 3721 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3722 // CHECK3: omp_if.else: 3723 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] 3724 // CHECK3-NEXT: br label [[OMP_IF_END]] 3725 // CHECK3: omp_if.end: 3726 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 3727 // CHECK3-NEXT: ret i32 [[TMP31]] 3728 // 3729 // 3730 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245 3731 // CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3732 // CHECK3-NEXT: entry: 3733 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3734 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3735 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3736 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3737 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3738 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3739 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3740 // CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 3741 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 3742 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 3743 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3744 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3745 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 3746 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 3747 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 3748 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 3749 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 3750 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 3751 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]]) 3752 // CHECK3-NEXT: ret void 3753 // 3754 // 3755 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined 3756 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3757 // CHECK3-NEXT: entry: 3758 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3759 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3760 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3761 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3762 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3763 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3764 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3765 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3766 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3767 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3768 // CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 3769 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 3770 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 3771 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3772 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3773 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 3774 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 3775 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 3776 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 3777 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 3778 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3779 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 3780 // CHECK3-NEXT: store double [[ADD]], ptr [[A]], align 4 3781 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 3782 // CHECK3-NEXT: [[TMP5:%.*]] = load double, ptr [[A3]], align 4 3783 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 3784 // CHECK3-NEXT: store double [[INC]], ptr [[A3]], align 4 3785 // CHECK3-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 3786 // CHECK3-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 3787 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP6]] 3788 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 3789 // CHECK3-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2 3790 // CHECK3-NEXT: ret void 3791 // 3792 // 3793 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227 3794 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3795 // CHECK3-NEXT: entry: 3796 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3797 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3798 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3799 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3800 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3801 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3802 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3803 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3804 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3805 // CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 3806 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3807 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3808 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 3809 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 3810 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 3811 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3812 // CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 3813 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3814 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 3815 // CHECK3-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 3816 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 3817 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]]) 3818 // CHECK3-NEXT: ret void 3819 // 3820 // 3821 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined 3822 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3823 // CHECK3-NEXT: entry: 3824 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3825 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3826 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3827 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3828 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3829 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3830 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3831 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3832 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3833 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3834 // CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 3835 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3836 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3837 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 3838 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 3839 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 3840 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3841 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 3842 // CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 3843 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 3844 // CHECK3-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 3845 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 3846 // CHECK3-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 3847 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 3848 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 3849 // CHECK3-NEXT: store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1 3850 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 3851 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 3852 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 3853 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4 3854 // CHECK3-NEXT: ret void 3855 // 3856 // 3857 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210 3858 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3859 // CHECK3-NEXT: entry: 3860 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3861 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3862 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3863 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3864 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3865 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3866 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3867 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3868 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3869 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 3870 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 3871 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 3872 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3873 // CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 3874 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3875 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) 3876 // CHECK3-NEXT: ret void 3877 // 3878 // 3879 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined 3880 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3881 // CHECK3-NEXT: entry: 3882 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3883 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3884 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3885 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3886 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3887 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3888 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3889 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3890 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3891 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3892 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3893 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 3894 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 3895 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 3896 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3897 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 3898 // CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 3899 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 3900 // CHECK3-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 3901 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 3902 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 3903 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 3904 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 3905 // CHECK3-NEXT: ret void 3906 // 3907 // 3908 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 3909 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 3910 // CHECK9-NEXT: entry: 3911 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 3912 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3913 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3914 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 3915 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3916 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) 3917 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 3918 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 3919 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 3920 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8 3921 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 3922 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 3923 // CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 3924 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3925 // CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 3926 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 3927 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i64 [[TMP4]]) 3928 // CHECK9-NEXT: ret void 3929 // 3930 // 3931 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined 3932 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3933 // CHECK9-NEXT: entry: 3934 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3935 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3936 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3937 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3938 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3939 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 3940 // CHECK9-NEXT: ret void 3941 // 3942 // 3943 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 3944 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3945 // CHECK9-NEXT: entry: 3946 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 3947 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3948 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3949 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 3950 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 3951 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3952 // CHECK9-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 3953 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 3954 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP1]]) 3955 // CHECK9-NEXT: ret void 3956 // 3957 // 3958 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined 3959 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3960 // CHECK9-NEXT: entry: 3961 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3962 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3963 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3964 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3965 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3966 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 3967 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3968 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 3969 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 3970 // CHECK9-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 3971 // CHECK9-NEXT: store i16 [[CONV1]], ptr [[AA_ADDR]], align 2 3972 // CHECK9-NEXT: ret void 3973 // 3974 // 3975 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 3976 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3977 // CHECK9-NEXT: entry: 3978 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 3979 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3980 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3981 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3982 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3983 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 3984 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 3985 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 3986 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3987 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 3988 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 3989 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3990 // CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 3991 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 3992 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) 3993 // CHECK9-NEXT: ret void 3994 // 3995 // 3996 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined 3997 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3998 // CHECK9-NEXT: entry: 3999 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4000 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4001 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4002 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4003 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4004 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4005 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4006 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4007 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4008 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4009 // CHECK9-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 4010 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4011 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 4012 // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 4013 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 4014 // CHECK9-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 4015 // CHECK9-NEXT: ret void 4016 // 4017 // 4018 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124 4019 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 4020 // CHECK9-NEXT: entry: 4021 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 4022 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4023 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4024 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4025 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4026 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 4027 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 4028 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4029 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4030 // CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1) 4031 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 4032 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 4033 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 4034 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4035 // CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 4036 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 4037 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i64 [[TMP2]], i64 [[TMP4]]) 4038 // CHECK9-NEXT: ret void 4039 // 4040 // 4041 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined 4042 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 4043 // CHECK9-NEXT: entry: 4044 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4045 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4046 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4047 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4048 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4049 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4050 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4051 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4052 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4053 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4054 // CHECK9-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 4055 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4056 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 4057 // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 4058 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 4059 // CHECK9-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 4060 // CHECK9-NEXT: ret void 4061 // 4062 // 4063 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130 4064 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 4065 // CHECK9-NEXT: entry: 4066 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 4067 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4068 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4069 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4070 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4071 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 4072 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 4073 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4074 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4075 // CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1) 4076 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 4077 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 4078 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 4079 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4080 // CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 4081 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 4082 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined, i64 [[TMP2]], i64 [[TMP4]]) 4083 // CHECK9-NEXT: ret void 4084 // 4085 // 4086 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined 4087 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 4088 // CHECK9-NEXT: entry: 4089 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4090 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4091 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4092 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4093 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4094 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4095 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4096 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4097 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4098 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4099 // CHECK9-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 4100 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4101 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 4102 // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 4103 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 4104 // CHECK9-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 4105 // CHECK9-NEXT: ret void 4106 // 4107 // 4108 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136 4109 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 4110 // CHECK9-NEXT: entry: 4111 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 4112 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4113 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4114 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4115 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4116 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 4117 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 4118 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4119 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4120 // CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1) 4121 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 4122 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 4123 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 4124 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4125 // CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 4126 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 4127 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i64 [[TMP2]], i64 [[TMP4]]) 4128 // CHECK9-NEXT: ret void 4129 // 4130 // 4131 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined 4132 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 4133 // CHECK9-NEXT: entry: 4134 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4135 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4136 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4137 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4138 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4139 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4140 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4141 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4142 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4143 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4144 // CHECK9-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 4145 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4146 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 4147 // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 4148 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 4149 // CHECK9-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 4150 // CHECK9-NEXT: ret void 4151 // 4152 // 4153 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160 4154 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 4155 // CHECK9-NEXT: entry: 4156 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 4157 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4158 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4159 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4160 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 4161 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4162 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4163 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4164 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 4165 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 4166 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4167 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 4168 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4169 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4170 // CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4171 // CHECK9-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 4172 // CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4173 // CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 4174 // CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 4175 // CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 4176 // CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 4177 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 4178 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4179 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 4180 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4181 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 4182 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 4183 // CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 4184 // CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 4185 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 4186 // CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 4187 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 4188 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]]) 4189 // CHECK9-NEXT: ret void 4190 // 4191 // 4192 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined 4193 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 4194 // CHECK9-NEXT: entry: 4195 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4196 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4197 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4198 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4199 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4200 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 4201 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4202 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4203 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4204 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 4205 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 4206 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4207 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4208 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4209 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4210 // CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4211 // CHECK9-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 4212 // CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4213 // CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 4214 // CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 4215 // CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 4216 // CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 4217 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 4218 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4219 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 4220 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4221 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 4222 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 4223 // CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 4224 // CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 4225 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 4226 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 4227 // CHECK9-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 4228 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 4229 // CHECK9-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4 4230 // CHECK9-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 4231 // CHECK9-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 4232 // CHECK9-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 4233 // CHECK9-NEXT: store float [[CONV6]], ptr [[ARRAYIDX]], align 4 4234 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 4235 // CHECK9-NEXT: [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 4 4236 // CHECK9-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 4237 // CHECK9-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 4238 // CHECK9-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 4239 // CHECK9-NEXT: store float [[CONV10]], ptr [[ARRAYIDX7]], align 4 4240 // CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 4241 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i64 0, i64 2 4242 // CHECK9-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8 4243 // CHECK9-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 4244 // CHECK9-NEXT: store double [[ADD13]], ptr [[ARRAYIDX12]], align 8 4245 // CHECK9-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 4246 // CHECK9-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP12]] 4247 // CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3 4248 // CHECK9-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 8 4249 // CHECK9-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 4250 // CHECK9-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8 4251 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 4252 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[X]], align 8 4253 // CHECK9-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 4254 // CHECK9-NEXT: store i64 [[ADD17]], ptr [[X]], align 8 4255 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 4256 // CHECK9-NEXT: [[TMP15:%.*]] = load i8, ptr [[Y]], align 8 4257 // CHECK9-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 4258 // CHECK9-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 4259 // CHECK9-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 4260 // CHECK9-NEXT: store i8 [[CONV20]], ptr [[Y]], align 8 4261 // CHECK9-NEXT: ret void 4262 // 4263 // 4264 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172 4265 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 4266 // CHECK9-NEXT: entry: 4267 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 4268 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 4269 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 4270 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 4271 // CHECK9-NEXT: store i64 [[NN]], ptr [[NN_ADDR]], align 8 4272 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4 4273 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[NN_CASTED]], align 4 4274 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 8 4275 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined, i64 [[TMP1]]) 4276 // CHECK9-NEXT: ret void 4277 // 4278 // 4279 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined 4280 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 4281 // CHECK9-NEXT: entry: 4282 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4283 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4284 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 4285 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 4286 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4287 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4288 // CHECK9-NEXT: store i64 [[NN]], ptr [[NN_ADDR]], align 8 4289 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4 4290 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[NN_CASTED]], align 4 4291 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 8 4292 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined.omp_outlined, i64 [[TMP1]]) 4293 // CHECK9-NEXT: ret void 4294 // 4295 // 4296 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined.omp_outlined 4297 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 4298 // CHECK9-NEXT: entry: 4299 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4300 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4301 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 4302 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4303 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4304 // CHECK9-NEXT: store i64 [[NN]], ptr [[NN_ADDR]], align 8 4305 // CHECK9-NEXT: ret void 4306 // 4307 // 4308 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175 4309 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 4310 // CHECK9-NEXT: entry: 4311 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 4312 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 4313 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 4314 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 4315 // CHECK9-NEXT: store i64 [[NN]], ptr [[NN_ADDR]], align 8 4316 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4 4317 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[NN_CASTED]], align 4 4318 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 8 4319 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined, i64 [[TMP1]]) 4320 // CHECK9-NEXT: ret void 4321 // 4322 // 4323 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined 4324 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 4325 // CHECK9-NEXT: entry: 4326 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4327 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4328 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 4329 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4330 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4331 // CHECK9-NEXT: store i64 [[NN]], ptr [[NN_ADDR]], align 8 4332 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined.omp_outlined, ptr [[NN_ADDR]]) 4333 // CHECK9-NEXT: ret void 4334 // 4335 // 4336 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined.omp_outlined 4337 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 4338 // CHECK9-NEXT: entry: 4339 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4340 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4341 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca ptr, align 8 4342 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4343 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4344 // CHECK9-NEXT: store ptr [[NN]], ptr [[NN_ADDR]], align 8 4345 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[NN_ADDR]], align 8 4346 // CHECK9-NEXT: ret void 4347 // 4348 // 4349 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200 4350 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR0]] { 4351 // CHECK9-NEXT: entry: 4352 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 4353 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4354 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 4355 // CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4356 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4357 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined, i64 [[TMP0]]) 4358 // CHECK9-NEXT: ret void 4359 // 4360 // 4361 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined 4362 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR0]] { 4363 // CHECK9-NEXT: entry: 4364 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4365 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4366 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4367 // CHECK9-NEXT: [[F:%.*]] = alloca ptr, align 8 4368 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4369 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4370 // CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4371 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4372 // CHECK9-NEXT: ret void 4373 // 4374 // 4375 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227 4376 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4377 // CHECK9-NEXT: entry: 4378 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 4379 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4380 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4381 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 4382 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4383 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4384 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4385 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 4386 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 4387 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4388 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4389 // CHECK9-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 4390 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4391 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 4392 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 4393 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 4394 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 4395 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4396 // CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 4397 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 4398 // CHECK9-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 4399 // CHECK9-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 4400 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 4401 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]]) 4402 // CHECK9-NEXT: ret void 4403 // 4404 // 4405 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined 4406 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4407 // CHECK9-NEXT: entry: 4408 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4409 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4410 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4411 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4412 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 4413 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4414 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4415 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4416 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4417 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4418 // CHECK9-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 4419 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4420 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 4421 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 4422 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 4423 // CHECK9-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 4424 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4425 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 4426 // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 4427 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 4428 // CHECK9-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 4429 // CHECK9-NEXT: [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 4430 // CHECK9-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 4431 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 4432 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 4433 // CHECK9-NEXT: store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1 4434 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 4435 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 4436 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 4437 // CHECK9-NEXT: store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4 4438 // CHECK9-NEXT: ret void 4439 // 4440 // 4441 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245 4442 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 4443 // CHECK9-NEXT: entry: 4444 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 4445 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4446 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4447 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4448 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4449 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4450 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4451 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 4452 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4453 // CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 4454 // CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4455 // CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 4456 // CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4457 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4458 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4459 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 4460 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4461 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 4462 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 4463 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8 4464 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) 4465 // CHECK9-NEXT: ret void 4466 // 4467 // 4468 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined 4469 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 4470 // CHECK9-NEXT: entry: 4471 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4472 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4473 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4474 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4475 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4476 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4477 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4478 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4479 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4480 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4481 // CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 4482 // CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4483 // CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 4484 // CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4485 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4486 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4487 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 4488 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4489 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 4490 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 4491 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 4492 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 4493 // CHECK9-NEXT: store double [[ADD]], ptr [[A]], align 8 4494 // CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 4495 // CHECK9-NEXT: [[TMP5:%.*]] = load double, ptr [[A3]], align 8 4496 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 4497 // CHECK9-NEXT: store double [[INC]], ptr [[A3]], align 8 4498 // CHECK9-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 4499 // CHECK9-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 4500 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP6]] 4501 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 4502 // CHECK9-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2 4503 // CHECK9-NEXT: ret void 4504 // 4505 // 4506 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210 4507 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4508 // CHECK9-NEXT: entry: 4509 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 4510 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4511 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4512 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4513 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4514 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4515 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 4516 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4517 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4518 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4519 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 4520 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 4521 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 4522 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 4523 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4524 // CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 4525 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 4526 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) 4527 // CHECK9-NEXT: ret void 4528 // 4529 // 4530 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined 4531 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4532 // CHECK9-NEXT: entry: 4533 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4534 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4535 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4536 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4537 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4538 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4539 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4540 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4541 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4542 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4543 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 4544 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 4545 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 4546 // CHECK9-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 4547 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4548 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 4549 // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 4550 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 4551 // CHECK9-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 4552 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 4553 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 4554 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 4555 // CHECK9-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 4556 // CHECK9-NEXT: ret void 4557 // 4558 // 4559 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 4560 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 4561 // CHECK11-NEXT: entry: 4562 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 4563 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4564 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4565 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 4566 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4567 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) 4568 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 4569 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4570 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 4571 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 4572 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 4573 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 4574 // CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 4575 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4576 // CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 4577 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 4578 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i32 [[TMP4]]) 4579 // CHECK11-NEXT: ret void 4580 // 4581 // 4582 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined 4583 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4584 // CHECK11-NEXT: entry: 4585 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4586 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4587 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4588 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4589 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4590 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4591 // CHECK11-NEXT: ret void 4592 // 4593 // 4594 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 4595 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4596 // CHECK11-NEXT: entry: 4597 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 4598 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4599 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4600 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 4601 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4602 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4603 // CHECK11-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 4604 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 4605 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP1]]) 4606 // CHECK11-NEXT: ret void 4607 // 4608 // 4609 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined 4610 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4611 // CHECK11-NEXT: entry: 4612 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4613 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4614 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4615 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4616 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4617 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4618 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4619 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 4620 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 4621 // CHECK11-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 4622 // CHECK11-NEXT: store i16 [[CONV1]], ptr [[AA_ADDR]], align 2 4623 // CHECK11-NEXT: ret void 4624 // 4625 // 4626 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 4627 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4628 // CHECK11-NEXT: entry: 4629 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 4630 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4631 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4632 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4633 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4634 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 4635 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4636 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4637 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4638 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 4639 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 4640 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4641 // CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 4642 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 4643 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) 4644 // CHECK11-NEXT: ret void 4645 // 4646 // 4647 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined 4648 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4649 // CHECK11-NEXT: entry: 4650 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4651 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4652 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4653 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4654 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4655 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4656 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4657 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4658 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4659 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4660 // CHECK11-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 4661 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4662 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 4663 // CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 4664 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 4665 // CHECK11-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 4666 // CHECK11-NEXT: ret void 4667 // 4668 // 4669 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124 4670 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4671 // CHECK11-NEXT: entry: 4672 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 4673 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4674 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4675 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4676 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4677 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 4678 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 4679 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4680 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4681 // CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1) 4682 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 4683 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 4684 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 4685 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4686 // CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 4687 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 4688 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i32 [[TMP2]], i32 [[TMP4]]) 4689 // CHECK11-NEXT: ret void 4690 // 4691 // 4692 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined 4693 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4694 // CHECK11-NEXT: entry: 4695 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4696 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4697 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4698 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4699 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4700 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4701 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4702 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4703 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4704 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4705 // CHECK11-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 4706 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4707 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 4708 // CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 4709 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 4710 // CHECK11-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 4711 // CHECK11-NEXT: ret void 4712 // 4713 // 4714 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130 4715 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4716 // CHECK11-NEXT: entry: 4717 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 4718 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4719 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4720 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4721 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4722 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 4723 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 4724 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4725 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4726 // CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1) 4727 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 4728 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 4729 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 4730 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4731 // CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 4732 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 4733 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined, i32 [[TMP2]], i32 [[TMP4]]) 4734 // CHECK11-NEXT: ret void 4735 // 4736 // 4737 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined 4738 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4739 // CHECK11-NEXT: entry: 4740 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4741 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4742 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4743 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4744 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4745 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4746 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4747 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4748 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4749 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4750 // CHECK11-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 4751 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4752 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 4753 // CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 4754 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 4755 // CHECK11-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 4756 // CHECK11-NEXT: ret void 4757 // 4758 // 4759 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136 4760 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4761 // CHECK11-NEXT: entry: 4762 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 4763 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4764 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4765 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4766 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4767 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 4768 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 4769 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4770 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4771 // CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1) 4772 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 4773 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 4774 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 4775 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4776 // CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 4777 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 4778 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i32 [[TMP2]], i32 [[TMP4]]) 4779 // CHECK11-NEXT: ret void 4780 // 4781 // 4782 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined 4783 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4784 // CHECK11-NEXT: entry: 4785 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4786 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4787 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4788 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4789 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4790 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4791 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4792 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4793 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4794 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4795 // CHECK11-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 4796 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4797 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 4798 // CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 4799 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 4800 // CHECK11-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 4801 // CHECK11-NEXT: ret void 4802 // 4803 // 4804 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160 4805 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 4806 // CHECK11-NEXT: entry: 4807 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 4808 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4809 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 4810 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4811 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 4812 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 4813 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4814 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 4815 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 4816 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 4817 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4818 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 4819 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4820 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 4821 // CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 4822 // CHECK11-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 4823 // CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 4824 // CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 4825 // CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 4826 // CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 4827 // CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 4828 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 4829 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 4830 // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 4831 // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 4832 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 4833 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 4834 // CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 4835 // CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 4836 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 4837 // CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 4838 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 4839 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]]) 4840 // CHECK11-NEXT: ret void 4841 // 4842 // 4843 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined 4844 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 4845 // CHECK11-NEXT: entry: 4846 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4847 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4848 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4849 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 4850 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4851 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 4852 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 4853 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4854 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 4855 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 4856 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 4857 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4858 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4859 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4860 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 4861 // CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 4862 // CHECK11-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 4863 // CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 4864 // CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 4865 // CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 4866 // CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 4867 // CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 4868 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 4869 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 4870 // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 4871 // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 4872 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 4873 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 4874 // CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 4875 // CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 4876 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 4877 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 4878 // CHECK11-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 4879 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 4880 // CHECK11-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4 4881 // CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 4882 // CHECK11-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 4883 // CHECK11-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 4884 // CHECK11-NEXT: store float [[CONV6]], ptr [[ARRAYIDX]], align 4 4885 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 4886 // CHECK11-NEXT: [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 4 4887 // CHECK11-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 4888 // CHECK11-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 4889 // CHECK11-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 4890 // CHECK11-NEXT: store float [[CONV10]], ptr [[ARRAYIDX7]], align 4 4891 // CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 4892 // CHECK11-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i32 0, i32 2 4893 // CHECK11-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8 4894 // CHECK11-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 4895 // CHECK11-NEXT: store double [[ADD13]], ptr [[ARRAYIDX12]], align 8 4896 // CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 4897 // CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP12]] 4898 // CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3 4899 // CHECK11-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 8 4900 // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 4901 // CHECK11-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8 4902 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 4903 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, ptr [[X]], align 4 4904 // CHECK11-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 4905 // CHECK11-NEXT: store i64 [[ADD17]], ptr [[X]], align 4 4906 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 4907 // CHECK11-NEXT: [[TMP15:%.*]] = load i8, ptr [[Y]], align 4 4908 // CHECK11-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 4909 // CHECK11-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 4910 // CHECK11-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 4911 // CHECK11-NEXT: store i8 [[CONV20]], ptr [[Y]], align 4 4912 // CHECK11-NEXT: ret void 4913 // 4914 // 4915 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172 4916 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 4917 // CHECK11-NEXT: entry: 4918 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 4919 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 4920 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 4921 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 4922 // CHECK11-NEXT: store i32 [[NN]], ptr [[NN_ADDR]], align 4 4923 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4 4924 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[NN_CASTED]], align 4 4925 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 4 4926 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined, i32 [[TMP1]]) 4927 // CHECK11-NEXT: ret void 4928 // 4929 // 4930 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined 4931 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 4932 // CHECK11-NEXT: entry: 4933 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4934 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4935 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 4936 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 4937 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4938 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4939 // CHECK11-NEXT: store i32 [[NN]], ptr [[NN_ADDR]], align 4 4940 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4 4941 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[NN_CASTED]], align 4 4942 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 4 4943 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined.omp_outlined, i32 [[TMP1]]) 4944 // CHECK11-NEXT: ret void 4945 // 4946 // 4947 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined.omp_outlined 4948 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 4949 // CHECK11-NEXT: entry: 4950 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4951 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4952 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 4953 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4954 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4955 // CHECK11-NEXT: store i32 [[NN]], ptr [[NN_ADDR]], align 4 4956 // CHECK11-NEXT: ret void 4957 // 4958 // 4959 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175 4960 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 4961 // CHECK11-NEXT: entry: 4962 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 4963 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 4964 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 4965 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 4966 // CHECK11-NEXT: store i32 [[NN]], ptr [[NN_ADDR]], align 4 4967 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4 4968 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[NN_CASTED]], align 4 4969 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 4 4970 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined, i32 [[TMP1]]) 4971 // CHECK11-NEXT: ret void 4972 // 4973 // 4974 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined 4975 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 4976 // CHECK11-NEXT: entry: 4977 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4978 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4979 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 4980 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4981 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4982 // CHECK11-NEXT: store i32 [[NN]], ptr [[NN_ADDR]], align 4 4983 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined.omp_outlined, ptr [[NN_ADDR]]) 4984 // CHECK11-NEXT: ret void 4985 // 4986 // 4987 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined.omp_outlined 4988 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 4989 // CHECK11-NEXT: entry: 4990 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4991 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4992 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca ptr, align 4 4993 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4994 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4995 // CHECK11-NEXT: store ptr [[NN]], ptr [[NN_ADDR]], align 4 4996 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[NN_ADDR]], align 4 4997 // CHECK11-NEXT: ret void 4998 // 4999 // 5000 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200 5001 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR0]] { 5002 // CHECK11-NEXT: entry: 5003 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 5004 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5005 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 5006 // CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 5007 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 5008 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined, i32 [[TMP0]]) 5009 // CHECK11-NEXT: ret void 5010 // 5011 // 5012 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined 5013 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR0]] { 5014 // CHECK11-NEXT: entry: 5015 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 5016 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 5017 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5018 // CHECK11-NEXT: [[F:%.*]] = alloca ptr, align 4 5019 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 5020 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 5021 // CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 5022 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 5023 // CHECK11-NEXT: ret void 5024 // 5025 // 5026 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227 5027 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 5028 // CHECK11-NEXT: entry: 5029 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 5030 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5031 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5032 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 5033 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 5034 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5035 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5036 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 5037 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 5038 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5039 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 5040 // CHECK11-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 5041 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 5042 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 5043 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 5044 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 5045 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 5046 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 5047 // CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 5048 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 5049 // CHECK11-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 5050 // CHECK11-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 5051 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 5052 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]]) 5053 // CHECK11-NEXT: ret void 5054 // 5055 // 5056 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined 5057 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 5058 // CHECK11-NEXT: entry: 5059 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 5060 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 5061 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5062 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5063 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 5064 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 5065 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 5066 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 5067 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5068 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 5069 // CHECK11-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 5070 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 5071 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 5072 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 5073 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 5074 // CHECK11-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 5075 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 5076 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 5077 // CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 5078 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 5079 // CHECK11-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 5080 // CHECK11-NEXT: [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 5081 // CHECK11-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 5082 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 5083 // CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 5084 // CHECK11-NEXT: store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1 5085 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 5086 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 5087 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 5088 // CHECK11-NEXT: store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4 5089 // CHECK11-NEXT: ret void 5090 // 5091 // 5092 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245 5093 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 5094 // CHECK11-NEXT: entry: 5095 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 5096 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 5097 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5098 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5099 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5100 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 5101 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 5102 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 5103 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 5104 // CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 5105 // CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 5106 // CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 5107 // CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 5108 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 5109 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 5110 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 5111 // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 5112 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 5113 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 5114 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 5115 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]]) 5116 // CHECK11-NEXT: ret void 5117 // 5118 // 5119 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined 5120 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 5121 // CHECK11-NEXT: entry: 5122 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 5123 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 5124 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 5125 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5126 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5127 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5128 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 5129 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 5130 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 5131 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 5132 // CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 5133 // CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 5134 // CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 5135 // CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 5136 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 5137 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 5138 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 5139 // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 5140 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 5141 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 5142 // CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 5143 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 5144 // CHECK11-NEXT: store double [[ADD]], ptr [[A]], align 4 5145 // CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 5146 // CHECK11-NEXT: [[TMP5:%.*]] = load double, ptr [[A3]], align 4 5147 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 5148 // CHECK11-NEXT: store double [[INC]], ptr [[A3]], align 4 5149 // CHECK11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 5150 // CHECK11-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 5151 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP6]] 5152 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 5153 // CHECK11-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2 5154 // CHECK11-NEXT: ret void 5155 // 5156 // 5157 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210 5158 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 5159 // CHECK11-NEXT: entry: 5160 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 5161 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5162 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5163 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 5164 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5165 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5166 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 5167 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5168 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 5169 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 5170 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 5171 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 5172 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 5173 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 5174 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 5175 // CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 5176 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 5177 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) 5178 // CHECK11-NEXT: ret void 5179 // 5180 // 5181 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined 5182 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 5183 // CHECK11-NEXT: entry: 5184 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 5185 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 5186 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5187 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5188 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 5189 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 5190 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 5191 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5192 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 5193 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 5194 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 5195 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 5196 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 5197 // CHECK11-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 5198 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 5199 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 5200 // CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 5201 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 5202 // CHECK11-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 5203 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 5204 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 5205 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 5206 // CHECK11-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 5207 // CHECK11-NEXT: ret void 5208 // 5209