1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ --version 2 2 // Test host codegen. 3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s 4 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s 6 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK-X86 7 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK-X86 9 10 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s 11 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s 13 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0-X86 %s 14 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0-X86 %s 16 17 // Test target parallel for codegen - host bc file has to be created first. 18 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 19 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s -check-prefix=TCHECK-TARGET 20 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 21 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -check-prefix=TCHECK-TARGET 22 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 23 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s -check-prefix=TCHECK-TARGET-X86 24 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 25 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -check-prefix=TCHECK-TARGET-X86 26 27 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 28 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1-TARGET %s 29 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 30 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1-TARGET %s 31 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 32 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1-TARGET-X86 %s 33 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 34 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1-TARGET-X86 %s 35 36 // expected-no-diagnostics 37 #ifndef HEADER 38 #define HEADER 39 40 41 int nested(int a){ 42 #pragma omp target parallel loop 43 for (int i = 0; i < 10; ++i) 44 ++a; 45 46 auto F = [&](){ 47 #pragma omp parallel 48 { 49 #pragma omp target parallel loop 50 for (int i = 0; i < 10; ++i) 51 ++a; 52 } 53 }; 54 55 F(); 56 57 return a; 58 } 59 60 61 62 63 64 65 // Check metadata is properly generated: 66 67 #endif 68 // CHECK-LABEL: define dso_local noundef signext i32 @_Z6nestedi 69 // CHECK-SAME: (i32 noundef signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { 70 // CHECK-NEXT: entry: 71 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 72 // CHECK-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 73 // CHECK-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 74 // CHECK-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 75 // CHECK-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 76 // CHECK-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 77 // CHECK-NEXT: [[F:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 78 // CHECK-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 79 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 80 // CHECK-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 81 // CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 82 // CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 83 // CHECK-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8 84 // CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 85 // CHECK-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8 86 // CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 87 // CHECK-NEXT: store ptr null, ptr [[TMP4]], align 8 88 // CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 89 // CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 90 // CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 91 // CHECK-NEXT: store i32 2, ptr [[TMP7]], align 4 92 // CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 93 // CHECK-NEXT: store i32 1, ptr [[TMP8]], align 4 94 // CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 95 // CHECK-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8 96 // CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 97 // CHECK-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8 98 // CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 99 // CHECK-NEXT: store ptr @.offload_sizes, ptr [[TMP11]], align 8 100 // CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 101 // CHECK-NEXT: store ptr @.offload_maptypes, ptr [[TMP12]], align 8 102 // CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 103 // CHECK-NEXT: store ptr null, ptr [[TMP13]], align 8 104 // CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 105 // CHECK-NEXT: store ptr null, ptr [[TMP14]], align 8 106 // CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 107 // CHECK-NEXT: store i64 0, ptr [[TMP15]], align 8 108 // CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 109 // CHECK-NEXT: store i64 0, ptr [[TMP16]], align 8 110 // CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 111 // CHECK-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP17]], align 4 112 // CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 113 // CHECK-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 114 // CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 115 // CHECK-NEXT: store i32 0, ptr [[TMP19]], align 4 116 // CHECK-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.region_id, ptr [[KERNEL_ARGS]]) 117 // CHECK-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 118 // CHECK-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 119 // CHECK: omp_offload.failed: 120 // CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42(i64 [[TMP1]]) #[[ATTR3:[0-9]+]] 121 // CHECK-NEXT: br label [[OMP_OFFLOAD_CONT]] 122 // CHECK: omp_offload.cont: 123 // CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[F]], i32 0, i32 0 124 // CHECK-NEXT: store ptr [[A_ADDR]], ptr [[TMP22]], align 8 125 // CHECK-NEXT: call void @"_ZZ6nestediENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[F]]) 126 // CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4 127 // CHECK-NEXT: ret i32 [[TMP23]] 128 // 129 // 130 // CHECK-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42 131 // CHECK-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1:[0-9]+]] { 132 // CHECK-NEXT: entry: 133 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 134 // CHECK-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 135 // CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 136 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 137 // CHECK-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 138 // CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 139 // CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i64 [[TMP1]]) 140 // CHECK-NEXT: ret void 141 // 142 // 143 // CHECK-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined 144 // CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2:[0-9]+]] { 145 // CHECK-NEXT: entry: 146 // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 147 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 148 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 149 // CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 150 // CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 151 // CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 152 // CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 153 // CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 154 // CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 155 // CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 156 // CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 157 // CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 158 // CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 159 // CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 160 // CHECK-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 161 // CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 162 // CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 163 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 164 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 165 // CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 166 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 167 // CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 168 // CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 169 // CHECK: cond.true: 170 // CHECK-NEXT: br label [[COND_END:%.*]] 171 // CHECK: cond.false: 172 // CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 173 // CHECK-NEXT: br label [[COND_END]] 174 // CHECK: cond.end: 175 // CHECK-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 176 // CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 177 // CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 178 // CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 179 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 180 // CHECK: omp.inner.for.cond: 181 // CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 182 // CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 183 // CHECK-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 184 // CHECK-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 185 // CHECK: omp.inner.for.body: 186 // CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 187 // CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 188 // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 189 // CHECK-NEXT: store i32 [[ADD]], ptr [[I]], align 4 190 // CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 191 // CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 192 // CHECK-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 193 // CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 194 // CHECK: omp.body.continue: 195 // CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 196 // CHECK: omp.inner.for.inc: 197 // CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 198 // CHECK-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 199 // CHECK-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 200 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] 201 // CHECK: omp.inner.for.end: 202 // CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 203 // CHECK: omp.loop.exit: 204 // CHECK-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 205 // CHECK-NEXT: ret void 206 // 207 // 208 // CHECK-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49 209 // CHECK-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] { 210 // CHECK-NEXT: entry: 211 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 212 // CHECK-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 213 // CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 214 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 215 // CHECK-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 216 // CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 217 // CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i64 [[TMP1]]) 218 // CHECK-NEXT: ret void 219 // 220 // 221 // CHECK-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined 222 // CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 223 // CHECK-NEXT: entry: 224 // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 225 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 226 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 227 // CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 228 // CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 229 // CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 230 // CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 231 // CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 232 // CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 233 // CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 234 // CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 235 // CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 236 // CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 237 // CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 238 // CHECK-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 239 // CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 240 // CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 241 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 242 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 243 // CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 244 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 245 // CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 246 // CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 247 // CHECK: cond.true: 248 // CHECK-NEXT: br label [[COND_END:%.*]] 249 // CHECK: cond.false: 250 // CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 251 // CHECK-NEXT: br label [[COND_END]] 252 // CHECK: cond.end: 253 // CHECK-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 254 // CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 255 // CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 256 // CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 257 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 258 // CHECK: omp.inner.for.cond: 259 // CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 260 // CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 261 // CHECK-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 262 // CHECK-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 263 // CHECK: omp.inner.for.body: 264 // CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 265 // CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 266 // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 267 // CHECK-NEXT: store i32 [[ADD]], ptr [[I]], align 4 268 // CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 269 // CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 270 // CHECK-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 271 // CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 272 // CHECK: omp.body.continue: 273 // CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 274 // CHECK: omp.inner.for.inc: 275 // CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 276 // CHECK-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 277 // CHECK-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 278 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] 279 // CHECK: omp.inner.for.end: 280 // CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 281 // CHECK: omp.loop.exit: 282 // CHECK-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 283 // CHECK-NEXT: ret void 284 // 285 // 286 // CHECK-LABEL: define internal void @.omp_offloading.requires_reg 287 // CHECK-SAME: () #[[ATTR4:[0-9]+]] { 288 // CHECK-NEXT: entry: 289 // CHECK-NEXT: call void @__tgt_register_requires(i64 1) 290 // CHECK-NEXT: ret void 291 // 292 // 293 // CHECK-X86-LABEL: define dso_local noundef i32 @_Z6nestedi 294 // CHECK-X86-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { 295 // CHECK-X86-NEXT: entry: 296 // CHECK-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 297 // CHECK-X86-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 298 // CHECK-X86-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 299 // CHECK-X86-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 300 // CHECK-X86-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 301 // CHECK-X86-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 302 // CHECK-X86-NEXT: [[F:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 303 // CHECK-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 304 // CHECK-X86-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 305 // CHECK-X86-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 306 // CHECK-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 307 // CHECK-X86-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 308 // CHECK-X86-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4 309 // CHECK-X86-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 310 // CHECK-X86-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4 311 // CHECK-X86-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 312 // CHECK-X86-NEXT: store ptr null, ptr [[TMP4]], align 4 313 // CHECK-X86-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 314 // CHECK-X86-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 315 // CHECK-X86-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 316 // CHECK-X86-NEXT: store i32 2, ptr [[TMP7]], align 4 317 // CHECK-X86-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 318 // CHECK-X86-NEXT: store i32 1, ptr [[TMP8]], align 4 319 // CHECK-X86-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 320 // CHECK-X86-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4 321 // CHECK-X86-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 322 // CHECK-X86-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4 323 // CHECK-X86-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 324 // CHECK-X86-NEXT: store ptr @.offload_sizes, ptr [[TMP11]], align 4 325 // CHECK-X86-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 326 // CHECK-X86-NEXT: store ptr @.offload_maptypes, ptr [[TMP12]], align 4 327 // CHECK-X86-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 328 // CHECK-X86-NEXT: store ptr null, ptr [[TMP13]], align 4 329 // CHECK-X86-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 330 // CHECK-X86-NEXT: store ptr null, ptr [[TMP14]], align 4 331 // CHECK-X86-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 332 // CHECK-X86-NEXT: store i64 0, ptr [[TMP15]], align 8 333 // CHECK-X86-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 334 // CHECK-X86-NEXT: store i64 0, ptr [[TMP16]], align 8 335 // CHECK-X86-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 336 // CHECK-X86-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP17]], align 4 337 // CHECK-X86-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 338 // CHECK-X86-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 339 // CHECK-X86-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 340 // CHECK-X86-NEXT: store i32 0, ptr [[TMP19]], align 4 341 // CHECK-X86-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.region_id, ptr [[KERNEL_ARGS]]) 342 // CHECK-X86-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 343 // CHECK-X86-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 344 // CHECK-X86: omp_offload.failed: 345 // CHECK-X86-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42(i32 [[TMP1]]) #[[ATTR3:[0-9]+]] 346 // CHECK-X86-NEXT: br label [[OMP_OFFLOAD_CONT]] 347 // CHECK-X86: omp_offload.cont: 348 // CHECK-X86-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[F]], i32 0, i32 0 349 // CHECK-X86-NEXT: store ptr [[A_ADDR]], ptr [[TMP22]], align 4 350 // CHECK-X86-NEXT: call void @"_ZZ6nestediENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(4) [[F]]) 351 // CHECK-X86-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4 352 // CHECK-X86-NEXT: ret i32 [[TMP23]] 353 // 354 // 355 // CHECK-X86-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42 356 // CHECK-X86-SAME: (i32 noundef [[A:%.*]]) #[[ATTR1:[0-9]+]] { 357 // CHECK-X86-NEXT: entry: 358 // CHECK-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 359 // CHECK-X86-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 360 // CHECK-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 361 // CHECK-X86-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 362 // CHECK-X86-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 363 // CHECK-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 364 // CHECK-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i32 [[TMP1]]) 365 // CHECK-X86-NEXT: ret void 366 // 367 // 368 // CHECK-X86-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined 369 // CHECK-X86-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2:[0-9]+]] { 370 // CHECK-X86-NEXT: entry: 371 // CHECK-X86-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 372 // CHECK-X86-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 373 // CHECK-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 374 // CHECK-X86-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 375 // CHECK-X86-NEXT: [[TMP:%.*]] = alloca i32, align 4 376 // CHECK-X86-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 377 // CHECK-X86-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 378 // CHECK-X86-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 379 // CHECK-X86-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 380 // CHECK-X86-NEXT: [[I:%.*]] = alloca i32, align 4 381 // CHECK-X86-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 382 // CHECK-X86-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 383 // CHECK-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 384 // CHECK-X86-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 385 // CHECK-X86-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 386 // CHECK-X86-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 387 // CHECK-X86-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 388 // CHECK-X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 389 // CHECK-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 390 // CHECK-X86-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 391 // CHECK-X86-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 392 // CHECK-X86-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 393 // CHECK-X86-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 394 // CHECK-X86: cond.true: 395 // CHECK-X86-NEXT: br label [[COND_END:%.*]] 396 // CHECK-X86: cond.false: 397 // CHECK-X86-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 398 // CHECK-X86-NEXT: br label [[COND_END]] 399 // CHECK-X86: cond.end: 400 // CHECK-X86-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 401 // CHECK-X86-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 402 // CHECK-X86-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 403 // CHECK-X86-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 404 // CHECK-X86-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 405 // CHECK-X86: omp.inner.for.cond: 406 // CHECK-X86-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 407 // CHECK-X86-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 408 // CHECK-X86-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 409 // CHECK-X86-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 410 // CHECK-X86: omp.inner.for.body: 411 // CHECK-X86-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 412 // CHECK-X86-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 413 // CHECK-X86-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 414 // CHECK-X86-NEXT: store i32 [[ADD]], ptr [[I]], align 4 415 // CHECK-X86-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 416 // CHECK-X86-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 417 // CHECK-X86-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 418 // CHECK-X86-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 419 // CHECK-X86: omp.body.continue: 420 // CHECK-X86-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 421 // CHECK-X86: omp.inner.for.inc: 422 // CHECK-X86-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 423 // CHECK-X86-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 424 // CHECK-X86-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 425 // CHECK-X86-NEXT: br label [[OMP_INNER_FOR_COND]] 426 // CHECK-X86: omp.inner.for.end: 427 // CHECK-X86-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 428 // CHECK-X86: omp.loop.exit: 429 // CHECK-X86-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 430 // CHECK-X86-NEXT: ret void 431 // 432 // 433 // CHECK-X86-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49 434 // CHECK-X86-SAME: (i32 noundef [[A:%.*]]) #[[ATTR1]] { 435 // CHECK-X86-NEXT: entry: 436 // CHECK-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 437 // CHECK-X86-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 438 // CHECK-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 439 // CHECK-X86-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 440 // CHECK-X86-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 441 // CHECK-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 442 // CHECK-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i32 [[TMP1]]) 443 // CHECK-X86-NEXT: ret void 444 // 445 // 446 // CHECK-X86-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined 447 // CHECK-X86-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 448 // CHECK-X86-NEXT: entry: 449 // CHECK-X86-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 450 // CHECK-X86-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 451 // CHECK-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 452 // CHECK-X86-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 453 // CHECK-X86-NEXT: [[TMP:%.*]] = alloca i32, align 4 454 // CHECK-X86-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 455 // CHECK-X86-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 456 // CHECK-X86-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 457 // CHECK-X86-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 458 // CHECK-X86-NEXT: [[I:%.*]] = alloca i32, align 4 459 // CHECK-X86-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 460 // CHECK-X86-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 461 // CHECK-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 462 // CHECK-X86-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 463 // CHECK-X86-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 464 // CHECK-X86-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 465 // CHECK-X86-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 466 // CHECK-X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 467 // CHECK-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 468 // CHECK-X86-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 469 // CHECK-X86-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 470 // CHECK-X86-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 471 // CHECK-X86-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 472 // CHECK-X86: cond.true: 473 // CHECK-X86-NEXT: br label [[COND_END:%.*]] 474 // CHECK-X86: cond.false: 475 // CHECK-X86-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 476 // CHECK-X86-NEXT: br label [[COND_END]] 477 // CHECK-X86: cond.end: 478 // CHECK-X86-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 479 // CHECK-X86-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 480 // CHECK-X86-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 481 // CHECK-X86-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 482 // CHECK-X86-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 483 // CHECK-X86: omp.inner.for.cond: 484 // CHECK-X86-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 485 // CHECK-X86-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 486 // CHECK-X86-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 487 // CHECK-X86-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 488 // CHECK-X86: omp.inner.for.body: 489 // CHECK-X86-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 490 // CHECK-X86-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 491 // CHECK-X86-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 492 // CHECK-X86-NEXT: store i32 [[ADD]], ptr [[I]], align 4 493 // CHECK-X86-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 494 // CHECK-X86-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 495 // CHECK-X86-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 496 // CHECK-X86-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 497 // CHECK-X86: omp.body.continue: 498 // CHECK-X86-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 499 // CHECK-X86: omp.inner.for.inc: 500 // CHECK-X86-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 501 // CHECK-X86-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 502 // CHECK-X86-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 503 // CHECK-X86-NEXT: br label [[OMP_INNER_FOR_COND]] 504 // CHECK-X86: omp.inner.for.end: 505 // CHECK-X86-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 506 // CHECK-X86: omp.loop.exit: 507 // CHECK-X86-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 508 // CHECK-X86-NEXT: ret void 509 // 510 // 511 // CHECK-X86-LABEL: define internal void @.omp_offloading.requires_reg 512 // CHECK-X86-SAME: () #[[ATTR4:[0-9]+]] { 513 // CHECK-X86-NEXT: entry: 514 // CHECK-X86-NEXT: call void @__tgt_register_requires(i64 1) 515 // CHECK-X86-NEXT: ret void 516 // 517 // 518 // SIMD-ONLY0-LABEL: define dso_local noundef signext i32 @_Z6nestedi 519 // SIMD-ONLY0-SAME: (i32 noundef signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { 520 // SIMD-ONLY0-NEXT: entry: 521 // SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 522 // SIMD-ONLY0-NEXT: [[I:%.*]] = alloca i32, align 4 523 // SIMD-ONLY0-NEXT: [[F:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 524 // SIMD-ONLY0-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 525 // SIMD-ONLY0-NEXT: store i32 0, ptr [[I]], align 4 526 // SIMD-ONLY0-NEXT: br label [[FOR_COND:%.*]] 527 // SIMD-ONLY0: for.cond: 528 // SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 529 // SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 530 // SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 531 // SIMD-ONLY0: for.body: 532 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 533 // SIMD-ONLY0-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 534 // SIMD-ONLY0-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 535 // SIMD-ONLY0-NEXT: br label [[FOR_INC:%.*]] 536 // SIMD-ONLY0: for.inc: 537 // SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 538 // SIMD-ONLY0-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP2]], 1 539 // SIMD-ONLY0-NEXT: store i32 [[INC1]], ptr [[I]], align 4 540 // SIMD-ONLY0-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 541 // SIMD-ONLY0: for.end: 542 // SIMD-ONLY0-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[F]], i32 0, i32 0 543 // SIMD-ONLY0-NEXT: store ptr [[A_ADDR]], ptr [[TMP3]], align 8 544 // SIMD-ONLY0-NEXT: call void @"_ZZ6nestediENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[F]]) 545 // SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 546 // SIMD-ONLY0-NEXT: ret i32 [[TMP4]] 547 // 548 // 549 // SIMD-ONLY0-X86-LABEL: define dso_local noundef i32 @_Z6nestedi 550 // SIMD-ONLY0-X86-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { 551 // SIMD-ONLY0-X86-NEXT: entry: 552 // SIMD-ONLY0-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 553 // SIMD-ONLY0-X86-NEXT: [[I:%.*]] = alloca i32, align 4 554 // SIMD-ONLY0-X86-NEXT: [[F:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 555 // SIMD-ONLY0-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 556 // SIMD-ONLY0-X86-NEXT: store i32 0, ptr [[I]], align 4 557 // SIMD-ONLY0-X86-NEXT: br label [[FOR_COND:%.*]] 558 // SIMD-ONLY0-X86: for.cond: 559 // SIMD-ONLY0-X86-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 560 // SIMD-ONLY0-X86-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 561 // SIMD-ONLY0-X86-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 562 // SIMD-ONLY0-X86: for.body: 563 // SIMD-ONLY0-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 564 // SIMD-ONLY0-X86-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 565 // SIMD-ONLY0-X86-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 566 // SIMD-ONLY0-X86-NEXT: br label [[FOR_INC:%.*]] 567 // SIMD-ONLY0-X86: for.inc: 568 // SIMD-ONLY0-X86-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 569 // SIMD-ONLY0-X86-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP2]], 1 570 // SIMD-ONLY0-X86-NEXT: store i32 [[INC1]], ptr [[I]], align 4 571 // SIMD-ONLY0-X86-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 572 // SIMD-ONLY0-X86: for.end: 573 // SIMD-ONLY0-X86-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[F]], i32 0, i32 0 574 // SIMD-ONLY0-X86-NEXT: store ptr [[A_ADDR]], ptr [[TMP3]], align 4 575 // SIMD-ONLY0-X86-NEXT: call void @"_ZZ6nestediENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(4) [[F]]) 576 // SIMD-ONLY0-X86-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 577 // SIMD-ONLY0-X86-NEXT: ret i32 [[TMP4]] 578 // 579 // 580 // TCHECK-TARGET-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42 581 // TCHECK-TARGET-SAME: (i64 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { 582 // TCHECK-TARGET-NEXT: entry: 583 // TCHECK-TARGET-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 584 // TCHECK-TARGET-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 585 // TCHECK-TARGET-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 586 // TCHECK-TARGET-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 587 // TCHECK-TARGET-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 588 // TCHECK-TARGET-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 589 // TCHECK-TARGET-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i64 [[TMP1]]) 590 // TCHECK-TARGET-NEXT: ret void 591 // 592 // 593 // TCHECK-TARGET-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined 594 // TCHECK-TARGET-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1:[0-9]+]] { 595 // TCHECK-TARGET-NEXT: entry: 596 // TCHECK-TARGET-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 597 // TCHECK-TARGET-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 598 // TCHECK-TARGET-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 599 // TCHECK-TARGET-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 600 // TCHECK-TARGET-NEXT: [[TMP:%.*]] = alloca i32, align 4 601 // TCHECK-TARGET-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 602 // TCHECK-TARGET-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 603 // TCHECK-TARGET-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 604 // TCHECK-TARGET-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 605 // TCHECK-TARGET-NEXT: [[I:%.*]] = alloca i32, align 4 606 // TCHECK-TARGET-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 607 // TCHECK-TARGET-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 608 // TCHECK-TARGET-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 609 // TCHECK-TARGET-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 610 // TCHECK-TARGET-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 611 // TCHECK-TARGET-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 612 // TCHECK-TARGET-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 613 // TCHECK-TARGET-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 614 // TCHECK-TARGET-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 615 // TCHECK-TARGET-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 616 // TCHECK-TARGET-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 617 // TCHECK-TARGET-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 618 // TCHECK-TARGET-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 619 // TCHECK-TARGET: cond.true: 620 // TCHECK-TARGET-NEXT: br label [[COND_END:%.*]] 621 // TCHECK-TARGET: cond.false: 622 // TCHECK-TARGET-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 623 // TCHECK-TARGET-NEXT: br label [[COND_END]] 624 // TCHECK-TARGET: cond.end: 625 // TCHECK-TARGET-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 626 // TCHECK-TARGET-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 627 // TCHECK-TARGET-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 628 // TCHECK-TARGET-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 629 // TCHECK-TARGET-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 630 // TCHECK-TARGET: omp.inner.for.cond: 631 // TCHECK-TARGET-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 632 // TCHECK-TARGET-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 633 // TCHECK-TARGET-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 634 // TCHECK-TARGET-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 635 // TCHECK-TARGET: omp.inner.for.body: 636 // TCHECK-TARGET-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 637 // TCHECK-TARGET-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 638 // TCHECK-TARGET-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 639 // TCHECK-TARGET-NEXT: store i32 [[ADD]], ptr [[I]], align 4 640 // TCHECK-TARGET-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 641 // TCHECK-TARGET-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 642 // TCHECK-TARGET-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 643 // TCHECK-TARGET-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 644 // TCHECK-TARGET: omp.body.continue: 645 // TCHECK-TARGET-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 646 // TCHECK-TARGET: omp.inner.for.inc: 647 // TCHECK-TARGET-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 648 // TCHECK-TARGET-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 649 // TCHECK-TARGET-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 650 // TCHECK-TARGET-NEXT: br label [[OMP_INNER_FOR_COND]] 651 // TCHECK-TARGET: omp.inner.for.end: 652 // TCHECK-TARGET-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 653 // TCHECK-TARGET: omp.loop.exit: 654 // TCHECK-TARGET-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 655 // TCHECK-TARGET-NEXT: ret void 656 // 657 // 658 // TCHECK-TARGET-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49 659 // TCHECK-TARGET-SAME: (i64 noundef [[A:%.*]]) #[[ATTR0]] { 660 // TCHECK-TARGET-NEXT: entry: 661 // TCHECK-TARGET-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 662 // TCHECK-TARGET-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 663 // TCHECK-TARGET-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 664 // TCHECK-TARGET-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 665 // TCHECK-TARGET-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 666 // TCHECK-TARGET-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 667 // TCHECK-TARGET-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i64 [[TMP1]]) 668 // TCHECK-TARGET-NEXT: ret void 669 // 670 // 671 // TCHECK-TARGET-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined 672 // TCHECK-TARGET-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 673 // TCHECK-TARGET-NEXT: entry: 674 // TCHECK-TARGET-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 675 // TCHECK-TARGET-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 676 // TCHECK-TARGET-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 677 // TCHECK-TARGET-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 678 // TCHECK-TARGET-NEXT: [[TMP:%.*]] = alloca i32, align 4 679 // TCHECK-TARGET-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 680 // TCHECK-TARGET-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 681 // TCHECK-TARGET-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 682 // TCHECK-TARGET-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 683 // TCHECK-TARGET-NEXT: [[I:%.*]] = alloca i32, align 4 684 // TCHECK-TARGET-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 685 // TCHECK-TARGET-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 686 // TCHECK-TARGET-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 687 // TCHECK-TARGET-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 688 // TCHECK-TARGET-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 689 // TCHECK-TARGET-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 690 // TCHECK-TARGET-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 691 // TCHECK-TARGET-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 692 // TCHECK-TARGET-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 693 // TCHECK-TARGET-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 694 // TCHECK-TARGET-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 695 // TCHECK-TARGET-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 696 // TCHECK-TARGET-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 697 // TCHECK-TARGET: cond.true: 698 // TCHECK-TARGET-NEXT: br label [[COND_END:%.*]] 699 // TCHECK-TARGET: cond.false: 700 // TCHECK-TARGET-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 701 // TCHECK-TARGET-NEXT: br label [[COND_END]] 702 // TCHECK-TARGET: cond.end: 703 // TCHECK-TARGET-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 704 // TCHECK-TARGET-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 705 // TCHECK-TARGET-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 706 // TCHECK-TARGET-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 707 // TCHECK-TARGET-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 708 // TCHECK-TARGET: omp.inner.for.cond: 709 // TCHECK-TARGET-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 710 // TCHECK-TARGET-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 711 // TCHECK-TARGET-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 712 // TCHECK-TARGET-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 713 // TCHECK-TARGET: omp.inner.for.body: 714 // TCHECK-TARGET-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 715 // TCHECK-TARGET-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 716 // TCHECK-TARGET-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 717 // TCHECK-TARGET-NEXT: store i32 [[ADD]], ptr [[I]], align 4 718 // TCHECK-TARGET-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 719 // TCHECK-TARGET-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 720 // TCHECK-TARGET-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 721 // TCHECK-TARGET-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 722 // TCHECK-TARGET: omp.body.continue: 723 // TCHECK-TARGET-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 724 // TCHECK-TARGET: omp.inner.for.inc: 725 // TCHECK-TARGET-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 726 // TCHECK-TARGET-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 727 // TCHECK-TARGET-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 728 // TCHECK-TARGET-NEXT: br label [[OMP_INNER_FOR_COND]] 729 // TCHECK-TARGET: omp.inner.for.end: 730 // TCHECK-TARGET-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 731 // TCHECK-TARGET: omp.loop.exit: 732 // TCHECK-TARGET-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 733 // TCHECK-TARGET-NEXT: ret void 734 // 735 // 736 // TCHECK-TARGET-X86-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42 737 // TCHECK-TARGET-X86-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { 738 // TCHECK-TARGET-X86-NEXT: entry: 739 // TCHECK-TARGET-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 740 // TCHECK-TARGET-X86-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 741 // TCHECK-TARGET-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 742 // TCHECK-TARGET-X86-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 743 // TCHECK-TARGET-X86-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 744 // TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 745 // TCHECK-TARGET-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i32 [[TMP1]]) 746 // TCHECK-TARGET-X86-NEXT: ret void 747 // 748 // 749 // TCHECK-TARGET-X86-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined 750 // TCHECK-TARGET-X86-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1:[0-9]+]] { 751 // TCHECK-TARGET-X86-NEXT: entry: 752 // TCHECK-TARGET-X86-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 753 // TCHECK-TARGET-X86-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 754 // TCHECK-TARGET-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 755 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 756 // TCHECK-TARGET-X86-NEXT: [[TMP:%.*]] = alloca i32, align 4 757 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 758 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 759 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 760 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 761 // TCHECK-TARGET-X86-NEXT: [[I:%.*]] = alloca i32, align 4 762 // TCHECK-TARGET-X86-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 763 // TCHECK-TARGET-X86-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 764 // TCHECK-TARGET-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 765 // TCHECK-TARGET-X86-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 766 // TCHECK-TARGET-X86-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 767 // TCHECK-TARGET-X86-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 768 // TCHECK-TARGET-X86-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 769 // TCHECK-TARGET-X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 770 // TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 771 // TCHECK-TARGET-X86-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 772 // TCHECK-TARGET-X86-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 773 // TCHECK-TARGET-X86-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 774 // TCHECK-TARGET-X86-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 775 // TCHECK-TARGET-X86: cond.true: 776 // TCHECK-TARGET-X86-NEXT: br label [[COND_END:%.*]] 777 // TCHECK-TARGET-X86: cond.false: 778 // TCHECK-TARGET-X86-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 779 // TCHECK-TARGET-X86-NEXT: br label [[COND_END]] 780 // TCHECK-TARGET-X86: cond.end: 781 // TCHECK-TARGET-X86-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 782 // TCHECK-TARGET-X86-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 783 // TCHECK-TARGET-X86-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 784 // TCHECK-TARGET-X86-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 785 // TCHECK-TARGET-X86-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 786 // TCHECK-TARGET-X86: omp.inner.for.cond: 787 // TCHECK-TARGET-X86-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 788 // TCHECK-TARGET-X86-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 789 // TCHECK-TARGET-X86-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 790 // TCHECK-TARGET-X86-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 791 // TCHECK-TARGET-X86: omp.inner.for.body: 792 // TCHECK-TARGET-X86-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 793 // TCHECK-TARGET-X86-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 794 // TCHECK-TARGET-X86-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 795 // TCHECK-TARGET-X86-NEXT: store i32 [[ADD]], ptr [[I]], align 4 796 // TCHECK-TARGET-X86-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 797 // TCHECK-TARGET-X86-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 798 // TCHECK-TARGET-X86-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 799 // TCHECK-TARGET-X86-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 800 // TCHECK-TARGET-X86: omp.body.continue: 801 // TCHECK-TARGET-X86-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 802 // TCHECK-TARGET-X86: omp.inner.for.inc: 803 // TCHECK-TARGET-X86-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 804 // TCHECK-TARGET-X86-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 805 // TCHECK-TARGET-X86-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 806 // TCHECK-TARGET-X86-NEXT: br label [[OMP_INNER_FOR_COND]] 807 // TCHECK-TARGET-X86: omp.inner.for.end: 808 // TCHECK-TARGET-X86-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 809 // TCHECK-TARGET-X86: omp.loop.exit: 810 // TCHECK-TARGET-X86-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 811 // TCHECK-TARGET-X86-NEXT: ret void 812 // 813 // 814 // TCHECK-TARGET-X86-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49 815 // TCHECK-TARGET-X86-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0]] { 816 // TCHECK-TARGET-X86-NEXT: entry: 817 // TCHECK-TARGET-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 818 // TCHECK-TARGET-X86-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 819 // TCHECK-TARGET-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 820 // TCHECK-TARGET-X86-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 821 // TCHECK-TARGET-X86-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 822 // TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 823 // TCHECK-TARGET-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i32 [[TMP1]]) 824 // TCHECK-TARGET-X86-NEXT: ret void 825 // 826 // 827 // TCHECK-TARGET-X86-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined 828 // TCHECK-TARGET-X86-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 829 // TCHECK-TARGET-X86-NEXT: entry: 830 // TCHECK-TARGET-X86-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 831 // TCHECK-TARGET-X86-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 832 // TCHECK-TARGET-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 833 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 834 // TCHECK-TARGET-X86-NEXT: [[TMP:%.*]] = alloca i32, align 4 835 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 836 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 837 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 838 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 839 // TCHECK-TARGET-X86-NEXT: [[I:%.*]] = alloca i32, align 4 840 // TCHECK-TARGET-X86-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 841 // TCHECK-TARGET-X86-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 842 // TCHECK-TARGET-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 843 // TCHECK-TARGET-X86-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 844 // TCHECK-TARGET-X86-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 845 // TCHECK-TARGET-X86-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 846 // TCHECK-TARGET-X86-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 847 // TCHECK-TARGET-X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 848 // TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 849 // TCHECK-TARGET-X86-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 850 // TCHECK-TARGET-X86-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 851 // TCHECK-TARGET-X86-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 852 // TCHECK-TARGET-X86-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 853 // TCHECK-TARGET-X86: cond.true: 854 // TCHECK-TARGET-X86-NEXT: br label [[COND_END:%.*]] 855 // TCHECK-TARGET-X86: cond.false: 856 // TCHECK-TARGET-X86-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 857 // TCHECK-TARGET-X86-NEXT: br label [[COND_END]] 858 // TCHECK-TARGET-X86: cond.end: 859 // TCHECK-TARGET-X86-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 860 // TCHECK-TARGET-X86-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 861 // TCHECK-TARGET-X86-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 862 // TCHECK-TARGET-X86-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 863 // TCHECK-TARGET-X86-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 864 // TCHECK-TARGET-X86: omp.inner.for.cond: 865 // TCHECK-TARGET-X86-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 866 // TCHECK-TARGET-X86-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 867 // TCHECK-TARGET-X86-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 868 // TCHECK-TARGET-X86-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 869 // TCHECK-TARGET-X86: omp.inner.for.body: 870 // TCHECK-TARGET-X86-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 871 // TCHECK-TARGET-X86-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 872 // TCHECK-TARGET-X86-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 873 // TCHECK-TARGET-X86-NEXT: store i32 [[ADD]], ptr [[I]], align 4 874 // TCHECK-TARGET-X86-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 875 // TCHECK-TARGET-X86-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 876 // TCHECK-TARGET-X86-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 877 // TCHECK-TARGET-X86-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 878 // TCHECK-TARGET-X86: omp.body.continue: 879 // TCHECK-TARGET-X86-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 880 // TCHECK-TARGET-X86: omp.inner.for.inc: 881 // TCHECK-TARGET-X86-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 882 // TCHECK-TARGET-X86-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 883 // TCHECK-TARGET-X86-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 884 // TCHECK-TARGET-X86-NEXT: br label [[OMP_INNER_FOR_COND]] 885 // TCHECK-TARGET-X86: omp.inner.for.end: 886 // TCHECK-TARGET-X86-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 887 // TCHECK-TARGET-X86: omp.loop.exit: 888 // TCHECK-TARGET-X86-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 889 // TCHECK-TARGET-X86-NEXT: ret void 890 // 891 // 892 // SIMD-ONLY1-TARGET-LABEL: define dso_local noundef signext i32 @_Z6nestedi 893 // SIMD-ONLY1-TARGET-SAME: (i32 noundef signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { 894 // SIMD-ONLY1-TARGET-NEXT: entry: 895 // SIMD-ONLY1-TARGET-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 896 // SIMD-ONLY1-TARGET-NEXT: [[I:%.*]] = alloca i32, align 4 897 // SIMD-ONLY1-TARGET-NEXT: [[F:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 898 // SIMD-ONLY1-TARGET-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 899 // SIMD-ONLY1-TARGET-NEXT: store i32 0, ptr [[I]], align 4 900 // SIMD-ONLY1-TARGET-NEXT: br label [[FOR_COND:%.*]] 901 // SIMD-ONLY1-TARGET: for.cond: 902 // SIMD-ONLY1-TARGET-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 903 // SIMD-ONLY1-TARGET-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 904 // SIMD-ONLY1-TARGET-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 905 // SIMD-ONLY1-TARGET: for.body: 906 // SIMD-ONLY1-TARGET-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 907 // SIMD-ONLY1-TARGET-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 908 // SIMD-ONLY1-TARGET-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 909 // SIMD-ONLY1-TARGET-NEXT: br label [[FOR_INC:%.*]] 910 // SIMD-ONLY1-TARGET: for.inc: 911 // SIMD-ONLY1-TARGET-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 912 // SIMD-ONLY1-TARGET-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP2]], 1 913 // SIMD-ONLY1-TARGET-NEXT: store i32 [[INC1]], ptr [[I]], align 4 914 // SIMD-ONLY1-TARGET-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 915 // SIMD-ONLY1-TARGET: for.end: 916 // SIMD-ONLY1-TARGET-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[F]], i32 0, i32 0 917 // SIMD-ONLY1-TARGET-NEXT: store ptr [[A_ADDR]], ptr [[TMP3]], align 8 918 // SIMD-ONLY1-TARGET-NEXT: call void @"_ZZ6nestediENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[F]]) 919 // SIMD-ONLY1-TARGET-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 920 // SIMD-ONLY1-TARGET-NEXT: ret i32 [[TMP4]] 921 // 922 // 923 // SIMD-ONLY1-TARGET-X86-LABEL: define dso_local noundef i32 @_Z6nestedi 924 // SIMD-ONLY1-TARGET-X86-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { 925 // SIMD-ONLY1-TARGET-X86-NEXT: entry: 926 // SIMD-ONLY1-TARGET-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 927 // SIMD-ONLY1-TARGET-X86-NEXT: [[I:%.*]] = alloca i32, align 4 928 // SIMD-ONLY1-TARGET-X86-NEXT: [[F:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 929 // SIMD-ONLY1-TARGET-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 930 // SIMD-ONLY1-TARGET-X86-NEXT: store i32 0, ptr [[I]], align 4 931 // SIMD-ONLY1-TARGET-X86-NEXT: br label [[FOR_COND:%.*]] 932 // SIMD-ONLY1-TARGET-X86: for.cond: 933 // SIMD-ONLY1-TARGET-X86-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 934 // SIMD-ONLY1-TARGET-X86-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 935 // SIMD-ONLY1-TARGET-X86-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 936 // SIMD-ONLY1-TARGET-X86: for.body: 937 // SIMD-ONLY1-TARGET-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 938 // SIMD-ONLY1-TARGET-X86-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 939 // SIMD-ONLY1-TARGET-X86-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 940 // SIMD-ONLY1-TARGET-X86-NEXT: br label [[FOR_INC:%.*]] 941 // SIMD-ONLY1-TARGET-X86: for.inc: 942 // SIMD-ONLY1-TARGET-X86-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 943 // SIMD-ONLY1-TARGET-X86-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP2]], 1 944 // SIMD-ONLY1-TARGET-X86-NEXT: store i32 [[INC1]], ptr [[I]], align 4 945 // SIMD-ONLY1-TARGET-X86-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 946 // SIMD-ONLY1-TARGET-X86: for.end: 947 // SIMD-ONLY1-TARGET-X86-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[F]], i32 0, i32 0 948 // SIMD-ONLY1-TARGET-X86-NEXT: store ptr [[A_ADDR]], ptr [[TMP3]], align 4 949 // SIMD-ONLY1-TARGET-X86-NEXT: call void @"_ZZ6nestediENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(4) [[F]]) 950 // SIMD-ONLY1-TARGET-X86-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 951 // SIMD-ONLY1-TARGET-X86-NEXT: ret i32 [[TMP4]] 952 // 953