1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ --version 2 2 // Test host codegen. 3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s 4 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s 6 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK-X86 7 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK-X86 9 10 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s 11 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s 13 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0-X86 %s 14 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0-X86 %s 16 17 // Test target parallel for codegen - host bc file has to be created first. 18 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 19 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s -check-prefix=TCHECK-TARGET 20 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 21 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -check-prefix=TCHECK-TARGET 22 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 23 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s -check-prefix=TCHECK-TARGET-X86 24 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 25 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -check-prefix=TCHECK-TARGET-X86 26 27 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 28 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1-TARGET %s 29 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 30 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1-TARGET %s 31 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 32 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1-TARGET-X86 %s 33 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 34 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1-TARGET-X86 %s 35 36 // expected-no-diagnostics 37 #ifndef HEADER 38 #define HEADER 39 40 41 int nested(int a){ 42 #pragma omp target parallel loop 43 for (int i = 0; i < 10; ++i) 44 ++a; 45 46 auto F = [&](){ 47 #pragma omp parallel 48 { 49 #pragma omp target parallel loop 50 for (int i = 0; i < 10; ++i) 51 ++a; 52 } 53 }; 54 55 F(); 56 57 return a; 58 } 59 60 61 62 63 64 65 // Check metadata is properly generated: 66 67 #endif 68 // CHECK-LABEL: define dso_local noundef signext i32 @_Z6nestedi 69 // CHECK-SAME: (i32 noundef signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { 70 // CHECK-NEXT: entry: 71 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 72 // CHECK-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 73 // CHECK-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 74 // CHECK-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 75 // CHECK-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 76 // CHECK-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 77 // CHECK-NEXT: [[F:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 78 // CHECK-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 79 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 80 // CHECK-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 81 // CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 82 // CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 83 // CHECK-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8 84 // CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 85 // CHECK-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8 86 // CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 87 // CHECK-NEXT: store ptr null, ptr [[TMP4]], align 8 88 // CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 89 // CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 90 // CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 91 // CHECK-NEXT: store i32 3, ptr [[TMP7]], align 4 92 // CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 93 // CHECK-NEXT: store i32 1, ptr [[TMP8]], align 4 94 // CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 95 // CHECK-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8 96 // CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 97 // CHECK-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8 98 // CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 99 // CHECK-NEXT: store ptr @.offload_sizes, ptr [[TMP11]], align 8 100 // CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 101 // CHECK-NEXT: store ptr @.offload_maptypes, ptr [[TMP12]], align 8 102 // CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 103 // CHECK-NEXT: store ptr null, ptr [[TMP13]], align 8 104 // CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 105 // CHECK-NEXT: store ptr null, ptr [[TMP14]], align 8 106 // CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 107 // CHECK-NEXT: store i64 0, ptr [[TMP15]], align 8 108 // CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 109 // CHECK-NEXT: store i64 0, ptr [[TMP16]], align 8 110 // CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 111 // CHECK-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP17]], align 4 112 // CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 113 // CHECK-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 114 // CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 115 // CHECK-NEXT: store i32 0, ptr [[TMP19]], align 4 116 // CHECK-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.region_id, ptr [[KERNEL_ARGS]]) 117 // CHECK-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 118 // CHECK-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 119 // CHECK: omp_offload.failed: 120 // CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] 121 // CHECK-NEXT: br label [[OMP_OFFLOAD_CONT]] 122 // CHECK: omp_offload.cont: 123 // CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[F]], i32 0, i32 0 124 // CHECK-NEXT: store ptr [[A_ADDR]], ptr [[TMP22]], align 8 125 // CHECK-NEXT: call void @"_ZZ6nestediENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[F]]) 126 // CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4 127 // CHECK-NEXT: ret i32 [[TMP23]] 128 // 129 // 130 // CHECK-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42 131 // CHECK-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1:[0-9]+]] { 132 // CHECK-NEXT: entry: 133 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 134 // CHECK-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 135 // CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 136 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 137 // CHECK-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 138 // CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 139 // CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i64 [[TMP1]]) 140 // CHECK-NEXT: ret void 141 // 142 // 143 // CHECK-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined 144 // CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 145 // CHECK-NEXT: entry: 146 // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 147 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 148 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 149 // CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 150 // CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 151 // CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 152 // CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 153 // CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 154 // CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 155 // CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 156 // CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 157 // CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 158 // CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 159 // CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 160 // CHECK-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 161 // CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 162 // CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 163 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 164 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 165 // CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 166 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 167 // CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 168 // CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 169 // CHECK: cond.true: 170 // CHECK-NEXT: br label [[COND_END:%.*]] 171 // CHECK: cond.false: 172 // CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 173 // CHECK-NEXT: br label [[COND_END]] 174 // CHECK: cond.end: 175 // CHECK-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 176 // CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 177 // CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 178 // CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 179 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 180 // CHECK: omp.inner.for.cond: 181 // CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 182 // CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 183 // CHECK-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 184 // CHECK-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 185 // CHECK: omp.inner.for.body: 186 // CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 187 // CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 188 // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 189 // CHECK-NEXT: store i32 [[ADD]], ptr [[I]], align 4 190 // CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 191 // CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 192 // CHECK-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 193 // CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 194 // CHECK: omp.body.continue: 195 // CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 196 // CHECK: omp.inner.for.inc: 197 // CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 198 // CHECK-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 199 // CHECK-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 200 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] 201 // CHECK: omp.inner.for.end: 202 // CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 203 // CHECK: omp.loop.exit: 204 // CHECK-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 205 // CHECK-NEXT: ret void 206 // 207 // 208 // CHECK-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49 209 // CHECK-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] { 210 // CHECK-NEXT: entry: 211 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 212 // CHECK-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 213 // CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 214 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 215 // CHECK-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 216 // CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 217 // CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i64 [[TMP1]]) 218 // CHECK-NEXT: ret void 219 // 220 // 221 // CHECK-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined 222 // CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 223 // CHECK-NEXT: entry: 224 // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 225 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 226 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 227 // CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 228 // CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 229 // CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 230 // CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 231 // CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 232 // CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 233 // CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 234 // CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 235 // CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 236 // CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 237 // CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 238 // CHECK-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 239 // CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 240 // CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 241 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 242 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 243 // CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 244 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 245 // CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 246 // CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 247 // CHECK: cond.true: 248 // CHECK-NEXT: br label [[COND_END:%.*]] 249 // CHECK: cond.false: 250 // CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 251 // CHECK-NEXT: br label [[COND_END]] 252 // CHECK: cond.end: 253 // CHECK-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 254 // CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 255 // CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 256 // CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 257 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 258 // CHECK: omp.inner.for.cond: 259 // CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 260 // CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 261 // CHECK-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 262 // CHECK-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 263 // CHECK: omp.inner.for.body: 264 // CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 265 // CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 266 // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 267 // CHECK-NEXT: store i32 [[ADD]], ptr [[I]], align 4 268 // CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 269 // CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 270 // CHECK-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 271 // CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 272 // CHECK: omp.body.continue: 273 // CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 274 // CHECK: omp.inner.for.inc: 275 // CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 276 // CHECK-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 277 // CHECK-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 278 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] 279 // CHECK: omp.inner.for.end: 280 // CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 281 // CHECK: omp.loop.exit: 282 // CHECK-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 283 // CHECK-NEXT: ret void 284 // 285 // 286 // CHECK-X86-LABEL: define dso_local noundef i32 @_Z6nestedi 287 // CHECK-X86-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { 288 // CHECK-X86-NEXT: entry: 289 // CHECK-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 290 // CHECK-X86-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 291 // CHECK-X86-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 292 // CHECK-X86-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 293 // CHECK-X86-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 294 // CHECK-X86-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 295 // CHECK-X86-NEXT: [[F:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 296 // CHECK-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 297 // CHECK-X86-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 298 // CHECK-X86-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 299 // CHECK-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 300 // CHECK-X86-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 301 // CHECK-X86-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4 302 // CHECK-X86-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 303 // CHECK-X86-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4 304 // CHECK-X86-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 305 // CHECK-X86-NEXT: store ptr null, ptr [[TMP4]], align 4 306 // CHECK-X86-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 307 // CHECK-X86-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 308 // CHECK-X86-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 309 // CHECK-X86-NEXT: store i32 3, ptr [[TMP7]], align 4 310 // CHECK-X86-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 311 // CHECK-X86-NEXT: store i32 1, ptr [[TMP8]], align 4 312 // CHECK-X86-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 313 // CHECK-X86-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4 314 // CHECK-X86-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 315 // CHECK-X86-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4 316 // CHECK-X86-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 317 // CHECK-X86-NEXT: store ptr @.offload_sizes, ptr [[TMP11]], align 4 318 // CHECK-X86-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 319 // CHECK-X86-NEXT: store ptr @.offload_maptypes, ptr [[TMP12]], align 4 320 // CHECK-X86-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 321 // CHECK-X86-NEXT: store ptr null, ptr [[TMP13]], align 4 322 // CHECK-X86-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 323 // CHECK-X86-NEXT: store ptr null, ptr [[TMP14]], align 4 324 // CHECK-X86-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 325 // CHECK-X86-NEXT: store i64 0, ptr [[TMP15]], align 8 326 // CHECK-X86-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 327 // CHECK-X86-NEXT: store i64 0, ptr [[TMP16]], align 8 328 // CHECK-X86-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 329 // CHECK-X86-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP17]], align 4 330 // CHECK-X86-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 331 // CHECK-X86-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 332 // CHECK-X86-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 333 // CHECK-X86-NEXT: store i32 0, ptr [[TMP19]], align 4 334 // CHECK-X86-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.region_id, ptr [[KERNEL_ARGS]]) 335 // CHECK-X86-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 336 // CHECK-X86-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 337 // CHECK-X86: omp_offload.failed: 338 // CHECK-X86-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] 339 // CHECK-X86-NEXT: br label [[OMP_OFFLOAD_CONT]] 340 // CHECK-X86: omp_offload.cont: 341 // CHECK-X86-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[F]], i32 0, i32 0 342 // CHECK-X86-NEXT: store ptr [[A_ADDR]], ptr [[TMP22]], align 4 343 // CHECK-X86-NEXT: call void @"_ZZ6nestediENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(4) [[F]]) 344 // CHECK-X86-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4 345 // CHECK-X86-NEXT: ret i32 [[TMP23]] 346 // 347 // 348 // CHECK-X86-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42 349 // CHECK-X86-SAME: (i32 noundef [[A:%.*]]) #[[ATTR1:[0-9]+]] { 350 // CHECK-X86-NEXT: entry: 351 // CHECK-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 352 // CHECK-X86-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 353 // CHECK-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 354 // CHECK-X86-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 355 // CHECK-X86-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 356 // CHECK-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 357 // CHECK-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i32 [[TMP1]]) 358 // CHECK-X86-NEXT: ret void 359 // 360 // 361 // CHECK-X86-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined 362 // CHECK-X86-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 363 // CHECK-X86-NEXT: entry: 364 // CHECK-X86-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 365 // CHECK-X86-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 366 // CHECK-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 367 // CHECK-X86-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 368 // CHECK-X86-NEXT: [[TMP:%.*]] = alloca i32, align 4 369 // CHECK-X86-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 370 // CHECK-X86-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 371 // CHECK-X86-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 372 // CHECK-X86-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 373 // CHECK-X86-NEXT: [[I:%.*]] = alloca i32, align 4 374 // CHECK-X86-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 375 // CHECK-X86-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 376 // CHECK-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 377 // CHECK-X86-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 378 // CHECK-X86-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 379 // CHECK-X86-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 380 // CHECK-X86-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 381 // CHECK-X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 382 // CHECK-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 383 // CHECK-X86-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 384 // CHECK-X86-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 385 // CHECK-X86-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 386 // CHECK-X86-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 387 // CHECK-X86: cond.true: 388 // CHECK-X86-NEXT: br label [[COND_END:%.*]] 389 // CHECK-X86: cond.false: 390 // CHECK-X86-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 391 // CHECK-X86-NEXT: br label [[COND_END]] 392 // CHECK-X86: cond.end: 393 // CHECK-X86-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 394 // CHECK-X86-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 395 // CHECK-X86-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 396 // CHECK-X86-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 397 // CHECK-X86-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 398 // CHECK-X86: omp.inner.for.cond: 399 // CHECK-X86-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 400 // CHECK-X86-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 401 // CHECK-X86-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 402 // CHECK-X86-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 403 // CHECK-X86: omp.inner.for.body: 404 // CHECK-X86-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 405 // CHECK-X86-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 406 // CHECK-X86-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 407 // CHECK-X86-NEXT: store i32 [[ADD]], ptr [[I]], align 4 408 // CHECK-X86-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 409 // CHECK-X86-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 410 // CHECK-X86-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 411 // CHECK-X86-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 412 // CHECK-X86: omp.body.continue: 413 // CHECK-X86-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 414 // CHECK-X86: omp.inner.for.inc: 415 // CHECK-X86-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 416 // CHECK-X86-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 417 // CHECK-X86-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 418 // CHECK-X86-NEXT: br label [[OMP_INNER_FOR_COND]] 419 // CHECK-X86: omp.inner.for.end: 420 // CHECK-X86-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 421 // CHECK-X86: omp.loop.exit: 422 // CHECK-X86-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 423 // CHECK-X86-NEXT: ret void 424 // 425 // 426 // CHECK-X86-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49 427 // CHECK-X86-SAME: (i32 noundef [[A:%.*]]) #[[ATTR1]] { 428 // CHECK-X86-NEXT: entry: 429 // CHECK-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 430 // CHECK-X86-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 431 // CHECK-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 432 // CHECK-X86-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 433 // CHECK-X86-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 434 // CHECK-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 435 // CHECK-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i32 [[TMP1]]) 436 // CHECK-X86-NEXT: ret void 437 // 438 // 439 // CHECK-X86-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined 440 // CHECK-X86-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 441 // CHECK-X86-NEXT: entry: 442 // CHECK-X86-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 443 // CHECK-X86-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 444 // CHECK-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 445 // CHECK-X86-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 446 // CHECK-X86-NEXT: [[TMP:%.*]] = alloca i32, align 4 447 // CHECK-X86-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 448 // CHECK-X86-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 449 // CHECK-X86-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 450 // CHECK-X86-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 451 // CHECK-X86-NEXT: [[I:%.*]] = alloca i32, align 4 452 // CHECK-X86-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 453 // CHECK-X86-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 454 // CHECK-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 455 // CHECK-X86-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 456 // CHECK-X86-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 457 // CHECK-X86-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 458 // CHECK-X86-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 459 // CHECK-X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 460 // CHECK-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 461 // CHECK-X86-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 462 // CHECK-X86-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 463 // CHECK-X86-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 464 // CHECK-X86-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 465 // CHECK-X86: cond.true: 466 // CHECK-X86-NEXT: br label [[COND_END:%.*]] 467 // CHECK-X86: cond.false: 468 // CHECK-X86-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 469 // CHECK-X86-NEXT: br label [[COND_END]] 470 // CHECK-X86: cond.end: 471 // CHECK-X86-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 472 // CHECK-X86-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 473 // CHECK-X86-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 474 // CHECK-X86-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 475 // CHECK-X86-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 476 // CHECK-X86: omp.inner.for.cond: 477 // CHECK-X86-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 478 // CHECK-X86-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 479 // CHECK-X86-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 480 // CHECK-X86-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 481 // CHECK-X86: omp.inner.for.body: 482 // CHECK-X86-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 483 // CHECK-X86-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 484 // CHECK-X86-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 485 // CHECK-X86-NEXT: store i32 [[ADD]], ptr [[I]], align 4 486 // CHECK-X86-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 487 // CHECK-X86-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 488 // CHECK-X86-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 489 // CHECK-X86-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 490 // CHECK-X86: omp.body.continue: 491 // CHECK-X86-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 492 // CHECK-X86: omp.inner.for.inc: 493 // CHECK-X86-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 494 // CHECK-X86-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 495 // CHECK-X86-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 496 // CHECK-X86-NEXT: br label [[OMP_INNER_FOR_COND]] 497 // CHECK-X86: omp.inner.for.end: 498 // CHECK-X86-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 499 // CHECK-X86: omp.loop.exit: 500 // CHECK-X86-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 501 // CHECK-X86-NEXT: ret void 502 // 503 // 504 // SIMD-ONLY0-LABEL: define dso_local noundef signext i32 @_Z6nestedi 505 // SIMD-ONLY0-SAME: (i32 noundef signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { 506 // SIMD-ONLY0-NEXT: entry: 507 // SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 508 // SIMD-ONLY0-NEXT: [[I:%.*]] = alloca i32, align 4 509 // SIMD-ONLY0-NEXT: [[F:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 510 // SIMD-ONLY0-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 511 // SIMD-ONLY0-NEXT: store i32 0, ptr [[I]], align 4 512 // SIMD-ONLY0-NEXT: br label [[FOR_COND:%.*]] 513 // SIMD-ONLY0: for.cond: 514 // SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 515 // SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 516 // SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 517 // SIMD-ONLY0: for.body: 518 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 519 // SIMD-ONLY0-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 520 // SIMD-ONLY0-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 521 // SIMD-ONLY0-NEXT: br label [[FOR_INC:%.*]] 522 // SIMD-ONLY0: for.inc: 523 // SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 524 // SIMD-ONLY0-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP2]], 1 525 // SIMD-ONLY0-NEXT: store i32 [[INC1]], ptr [[I]], align 4 526 // SIMD-ONLY0-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 527 // SIMD-ONLY0: for.end: 528 // SIMD-ONLY0-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[F]], i32 0, i32 0 529 // SIMD-ONLY0-NEXT: store ptr [[A_ADDR]], ptr [[TMP3]], align 8 530 // SIMD-ONLY0-NEXT: call void @"_ZZ6nestediENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[F]]) 531 // SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 532 // SIMD-ONLY0-NEXT: ret i32 [[TMP4]] 533 // 534 // 535 // SIMD-ONLY0-X86-LABEL: define dso_local noundef i32 @_Z6nestedi 536 // SIMD-ONLY0-X86-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { 537 // SIMD-ONLY0-X86-NEXT: entry: 538 // SIMD-ONLY0-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 539 // SIMD-ONLY0-X86-NEXT: [[I:%.*]] = alloca i32, align 4 540 // SIMD-ONLY0-X86-NEXT: [[F:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 541 // SIMD-ONLY0-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 542 // SIMD-ONLY0-X86-NEXT: store i32 0, ptr [[I]], align 4 543 // SIMD-ONLY0-X86-NEXT: br label [[FOR_COND:%.*]] 544 // SIMD-ONLY0-X86: for.cond: 545 // SIMD-ONLY0-X86-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 546 // SIMD-ONLY0-X86-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 547 // SIMD-ONLY0-X86-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 548 // SIMD-ONLY0-X86: for.body: 549 // SIMD-ONLY0-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 550 // SIMD-ONLY0-X86-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 551 // SIMD-ONLY0-X86-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 552 // SIMD-ONLY0-X86-NEXT: br label [[FOR_INC:%.*]] 553 // SIMD-ONLY0-X86: for.inc: 554 // SIMD-ONLY0-X86-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 555 // SIMD-ONLY0-X86-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP2]], 1 556 // SIMD-ONLY0-X86-NEXT: store i32 [[INC1]], ptr [[I]], align 4 557 // SIMD-ONLY0-X86-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 558 // SIMD-ONLY0-X86: for.end: 559 // SIMD-ONLY0-X86-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[F]], i32 0, i32 0 560 // SIMD-ONLY0-X86-NEXT: store ptr [[A_ADDR]], ptr [[TMP3]], align 4 561 // SIMD-ONLY0-X86-NEXT: call void @"_ZZ6nestediENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(4) [[F]]) 562 // SIMD-ONLY0-X86-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 563 // SIMD-ONLY0-X86-NEXT: ret i32 [[TMP4]] 564 // 565 // 566 // TCHECK-TARGET-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42 567 // TCHECK-TARGET-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { 568 // TCHECK-TARGET-NEXT: entry: 569 // TCHECK-TARGET-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 570 // TCHECK-TARGET-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 571 // TCHECK-TARGET-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 572 // TCHECK-TARGET-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 573 // TCHECK-TARGET-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 574 // TCHECK-TARGET-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 575 // TCHECK-TARGET-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 576 // TCHECK-TARGET-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 577 // TCHECK-TARGET-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i64 [[TMP1]]) 578 // TCHECK-TARGET-NEXT: ret void 579 // 580 // 581 // TCHECK-TARGET-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined 582 // TCHECK-TARGET-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 583 // TCHECK-TARGET-NEXT: entry: 584 // TCHECK-TARGET-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 585 // TCHECK-TARGET-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 586 // TCHECK-TARGET-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 587 // TCHECK-TARGET-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 588 // TCHECK-TARGET-NEXT: [[TMP:%.*]] = alloca i32, align 4 589 // TCHECK-TARGET-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 590 // TCHECK-TARGET-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 591 // TCHECK-TARGET-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 592 // TCHECK-TARGET-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 593 // TCHECK-TARGET-NEXT: [[I:%.*]] = alloca i32, align 4 594 // TCHECK-TARGET-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 595 // TCHECK-TARGET-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 596 // TCHECK-TARGET-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 597 // TCHECK-TARGET-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 598 // TCHECK-TARGET-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 599 // TCHECK-TARGET-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 600 // TCHECK-TARGET-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 601 // TCHECK-TARGET-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 602 // TCHECK-TARGET-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 603 // TCHECK-TARGET-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 604 // TCHECK-TARGET-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 605 // TCHECK-TARGET-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 606 // TCHECK-TARGET-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 607 // TCHECK-TARGET: cond.true: 608 // TCHECK-TARGET-NEXT: br label [[COND_END:%.*]] 609 // TCHECK-TARGET: cond.false: 610 // TCHECK-TARGET-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 611 // TCHECK-TARGET-NEXT: br label [[COND_END]] 612 // TCHECK-TARGET: cond.end: 613 // TCHECK-TARGET-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 614 // TCHECK-TARGET-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 615 // TCHECK-TARGET-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 616 // TCHECK-TARGET-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 617 // TCHECK-TARGET-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 618 // TCHECK-TARGET: omp.inner.for.cond: 619 // TCHECK-TARGET-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 620 // TCHECK-TARGET-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 621 // TCHECK-TARGET-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 622 // TCHECK-TARGET-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 623 // TCHECK-TARGET: omp.inner.for.body: 624 // TCHECK-TARGET-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 625 // TCHECK-TARGET-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 626 // TCHECK-TARGET-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 627 // TCHECK-TARGET-NEXT: store i32 [[ADD]], ptr [[I]], align 4 628 // TCHECK-TARGET-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 629 // TCHECK-TARGET-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 630 // TCHECK-TARGET-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 631 // TCHECK-TARGET-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 632 // TCHECK-TARGET: omp.body.continue: 633 // TCHECK-TARGET-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 634 // TCHECK-TARGET: omp.inner.for.inc: 635 // TCHECK-TARGET-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 636 // TCHECK-TARGET-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 637 // TCHECK-TARGET-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 638 // TCHECK-TARGET-NEXT: br label [[OMP_INNER_FOR_COND]] 639 // TCHECK-TARGET: omp.inner.for.end: 640 // TCHECK-TARGET-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 641 // TCHECK-TARGET: omp.loop.exit: 642 // TCHECK-TARGET-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 643 // TCHECK-TARGET-NEXT: ret void 644 // 645 // 646 // TCHECK-TARGET-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49 647 // TCHECK-TARGET-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 648 // TCHECK-TARGET-NEXT: entry: 649 // TCHECK-TARGET-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 650 // TCHECK-TARGET-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 651 // TCHECK-TARGET-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 652 // TCHECK-TARGET-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 653 // TCHECK-TARGET-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 654 // TCHECK-TARGET-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 655 // TCHECK-TARGET-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 656 // TCHECK-TARGET-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 657 // TCHECK-TARGET-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i64 [[TMP1]]) 658 // TCHECK-TARGET-NEXT: ret void 659 // 660 // 661 // TCHECK-TARGET-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined 662 // TCHECK-TARGET-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 663 // TCHECK-TARGET-NEXT: entry: 664 // TCHECK-TARGET-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 665 // TCHECK-TARGET-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 666 // TCHECK-TARGET-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 667 // TCHECK-TARGET-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 668 // TCHECK-TARGET-NEXT: [[TMP:%.*]] = alloca i32, align 4 669 // TCHECK-TARGET-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 670 // TCHECK-TARGET-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 671 // TCHECK-TARGET-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 672 // TCHECK-TARGET-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 673 // TCHECK-TARGET-NEXT: [[I:%.*]] = alloca i32, align 4 674 // TCHECK-TARGET-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 675 // TCHECK-TARGET-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 676 // TCHECK-TARGET-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 677 // TCHECK-TARGET-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 678 // TCHECK-TARGET-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 679 // TCHECK-TARGET-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 680 // TCHECK-TARGET-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 681 // TCHECK-TARGET-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 682 // TCHECK-TARGET-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 683 // TCHECK-TARGET-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 684 // TCHECK-TARGET-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 685 // TCHECK-TARGET-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 686 // TCHECK-TARGET-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 687 // TCHECK-TARGET: cond.true: 688 // TCHECK-TARGET-NEXT: br label [[COND_END:%.*]] 689 // TCHECK-TARGET: cond.false: 690 // TCHECK-TARGET-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 691 // TCHECK-TARGET-NEXT: br label [[COND_END]] 692 // TCHECK-TARGET: cond.end: 693 // TCHECK-TARGET-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 694 // TCHECK-TARGET-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 695 // TCHECK-TARGET-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 696 // TCHECK-TARGET-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 697 // TCHECK-TARGET-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 698 // TCHECK-TARGET: omp.inner.for.cond: 699 // TCHECK-TARGET-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 700 // TCHECK-TARGET-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 701 // TCHECK-TARGET-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 702 // TCHECK-TARGET-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 703 // TCHECK-TARGET: omp.inner.for.body: 704 // TCHECK-TARGET-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 705 // TCHECK-TARGET-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 706 // TCHECK-TARGET-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 707 // TCHECK-TARGET-NEXT: store i32 [[ADD]], ptr [[I]], align 4 708 // TCHECK-TARGET-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 709 // TCHECK-TARGET-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 710 // TCHECK-TARGET-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 711 // TCHECK-TARGET-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 712 // TCHECK-TARGET: omp.body.continue: 713 // TCHECK-TARGET-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 714 // TCHECK-TARGET: omp.inner.for.inc: 715 // TCHECK-TARGET-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 716 // TCHECK-TARGET-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 717 // TCHECK-TARGET-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 718 // TCHECK-TARGET-NEXT: br label [[OMP_INNER_FOR_COND]] 719 // TCHECK-TARGET: omp.inner.for.end: 720 // TCHECK-TARGET-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 721 // TCHECK-TARGET: omp.loop.exit: 722 // TCHECK-TARGET-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 723 // TCHECK-TARGET-NEXT: ret void 724 // 725 // 726 // TCHECK-TARGET-X86-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42 727 // TCHECK-TARGET-X86-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { 728 // TCHECK-TARGET-X86-NEXT: entry: 729 // TCHECK-TARGET-X86-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 730 // TCHECK-TARGET-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 731 // TCHECK-TARGET-X86-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 732 // TCHECK-TARGET-X86-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 733 // TCHECK-TARGET-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 734 // TCHECK-TARGET-X86-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 735 // TCHECK-TARGET-X86-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 736 // TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 737 // TCHECK-TARGET-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i32 [[TMP1]]) 738 // TCHECK-TARGET-X86-NEXT: ret void 739 // 740 // 741 // TCHECK-TARGET-X86-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined 742 // TCHECK-TARGET-X86-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 743 // TCHECK-TARGET-X86-NEXT: entry: 744 // TCHECK-TARGET-X86-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 745 // TCHECK-TARGET-X86-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 746 // TCHECK-TARGET-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 747 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 748 // TCHECK-TARGET-X86-NEXT: [[TMP:%.*]] = alloca i32, align 4 749 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 750 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 751 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 752 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 753 // TCHECK-TARGET-X86-NEXT: [[I:%.*]] = alloca i32, align 4 754 // TCHECK-TARGET-X86-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 755 // TCHECK-TARGET-X86-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 756 // TCHECK-TARGET-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 757 // TCHECK-TARGET-X86-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 758 // TCHECK-TARGET-X86-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 759 // TCHECK-TARGET-X86-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 760 // TCHECK-TARGET-X86-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 761 // TCHECK-TARGET-X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 762 // TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 763 // TCHECK-TARGET-X86-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 764 // TCHECK-TARGET-X86-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 765 // TCHECK-TARGET-X86-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 766 // TCHECK-TARGET-X86-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 767 // TCHECK-TARGET-X86: cond.true: 768 // TCHECK-TARGET-X86-NEXT: br label [[COND_END:%.*]] 769 // TCHECK-TARGET-X86: cond.false: 770 // TCHECK-TARGET-X86-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 771 // TCHECK-TARGET-X86-NEXT: br label [[COND_END]] 772 // TCHECK-TARGET-X86: cond.end: 773 // TCHECK-TARGET-X86-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 774 // TCHECK-TARGET-X86-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 775 // TCHECK-TARGET-X86-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 776 // TCHECK-TARGET-X86-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 777 // TCHECK-TARGET-X86-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 778 // TCHECK-TARGET-X86: omp.inner.for.cond: 779 // TCHECK-TARGET-X86-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 780 // TCHECK-TARGET-X86-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 781 // TCHECK-TARGET-X86-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 782 // TCHECK-TARGET-X86-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 783 // TCHECK-TARGET-X86: omp.inner.for.body: 784 // TCHECK-TARGET-X86-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 785 // TCHECK-TARGET-X86-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 786 // TCHECK-TARGET-X86-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 787 // TCHECK-TARGET-X86-NEXT: store i32 [[ADD]], ptr [[I]], align 4 788 // TCHECK-TARGET-X86-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 789 // TCHECK-TARGET-X86-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 790 // TCHECK-TARGET-X86-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 791 // TCHECK-TARGET-X86-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 792 // TCHECK-TARGET-X86: omp.body.continue: 793 // TCHECK-TARGET-X86-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 794 // TCHECK-TARGET-X86: omp.inner.for.inc: 795 // TCHECK-TARGET-X86-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 796 // TCHECK-TARGET-X86-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 797 // TCHECK-TARGET-X86-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 798 // TCHECK-TARGET-X86-NEXT: br label [[OMP_INNER_FOR_COND]] 799 // TCHECK-TARGET-X86: omp.inner.for.end: 800 // TCHECK-TARGET-X86-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 801 // TCHECK-TARGET-X86: omp.loop.exit: 802 // TCHECK-TARGET-X86-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 803 // TCHECK-TARGET-X86-NEXT: ret void 804 // 805 // 806 // TCHECK-TARGET-X86-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49 807 // TCHECK-TARGET-X86-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 808 // TCHECK-TARGET-X86-NEXT: entry: 809 // TCHECK-TARGET-X86-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 810 // TCHECK-TARGET-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 811 // TCHECK-TARGET-X86-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 812 // TCHECK-TARGET-X86-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 813 // TCHECK-TARGET-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 814 // TCHECK-TARGET-X86-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 815 // TCHECK-TARGET-X86-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 816 // TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 817 // TCHECK-TARGET-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i32 [[TMP1]]) 818 // TCHECK-TARGET-X86-NEXT: ret void 819 // 820 // 821 // TCHECK-TARGET-X86-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined 822 // TCHECK-TARGET-X86-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 823 // TCHECK-TARGET-X86-NEXT: entry: 824 // TCHECK-TARGET-X86-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 825 // TCHECK-TARGET-X86-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 826 // TCHECK-TARGET-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 827 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 828 // TCHECK-TARGET-X86-NEXT: [[TMP:%.*]] = alloca i32, align 4 829 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 830 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 831 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 832 // TCHECK-TARGET-X86-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 833 // TCHECK-TARGET-X86-NEXT: [[I:%.*]] = alloca i32, align 4 834 // TCHECK-TARGET-X86-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 835 // TCHECK-TARGET-X86-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 836 // TCHECK-TARGET-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 837 // TCHECK-TARGET-X86-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 838 // TCHECK-TARGET-X86-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 839 // TCHECK-TARGET-X86-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 840 // TCHECK-TARGET-X86-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 841 // TCHECK-TARGET-X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 842 // TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 843 // TCHECK-TARGET-X86-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 844 // TCHECK-TARGET-X86-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 845 // TCHECK-TARGET-X86-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 846 // TCHECK-TARGET-X86-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 847 // TCHECK-TARGET-X86: cond.true: 848 // TCHECK-TARGET-X86-NEXT: br label [[COND_END:%.*]] 849 // TCHECK-TARGET-X86: cond.false: 850 // TCHECK-TARGET-X86-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 851 // TCHECK-TARGET-X86-NEXT: br label [[COND_END]] 852 // TCHECK-TARGET-X86: cond.end: 853 // TCHECK-TARGET-X86-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 854 // TCHECK-TARGET-X86-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 855 // TCHECK-TARGET-X86-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 856 // TCHECK-TARGET-X86-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 857 // TCHECK-TARGET-X86-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 858 // TCHECK-TARGET-X86: omp.inner.for.cond: 859 // TCHECK-TARGET-X86-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 860 // TCHECK-TARGET-X86-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 861 // TCHECK-TARGET-X86-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 862 // TCHECK-TARGET-X86-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 863 // TCHECK-TARGET-X86: omp.inner.for.body: 864 // TCHECK-TARGET-X86-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 865 // TCHECK-TARGET-X86-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 866 // TCHECK-TARGET-X86-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 867 // TCHECK-TARGET-X86-NEXT: store i32 [[ADD]], ptr [[I]], align 4 868 // TCHECK-TARGET-X86-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 869 // TCHECK-TARGET-X86-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 870 // TCHECK-TARGET-X86-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 871 // TCHECK-TARGET-X86-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 872 // TCHECK-TARGET-X86: omp.body.continue: 873 // TCHECK-TARGET-X86-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 874 // TCHECK-TARGET-X86: omp.inner.for.inc: 875 // TCHECK-TARGET-X86-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 876 // TCHECK-TARGET-X86-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 877 // TCHECK-TARGET-X86-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 878 // TCHECK-TARGET-X86-NEXT: br label [[OMP_INNER_FOR_COND]] 879 // TCHECK-TARGET-X86: omp.inner.for.end: 880 // TCHECK-TARGET-X86-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 881 // TCHECK-TARGET-X86: omp.loop.exit: 882 // TCHECK-TARGET-X86-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 883 // TCHECK-TARGET-X86-NEXT: ret void 884 // 885 // 886 // SIMD-ONLY1-TARGET-LABEL: define dso_local noundef signext i32 @_Z6nestedi 887 // SIMD-ONLY1-TARGET-SAME: (i32 noundef signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { 888 // SIMD-ONLY1-TARGET-NEXT: entry: 889 // SIMD-ONLY1-TARGET-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 890 // SIMD-ONLY1-TARGET-NEXT: [[I:%.*]] = alloca i32, align 4 891 // SIMD-ONLY1-TARGET-NEXT: [[F:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 892 // SIMD-ONLY1-TARGET-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 893 // SIMD-ONLY1-TARGET-NEXT: store i32 0, ptr [[I]], align 4 894 // SIMD-ONLY1-TARGET-NEXT: br label [[FOR_COND:%.*]] 895 // SIMD-ONLY1-TARGET: for.cond: 896 // SIMD-ONLY1-TARGET-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 897 // SIMD-ONLY1-TARGET-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 898 // SIMD-ONLY1-TARGET-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 899 // SIMD-ONLY1-TARGET: for.body: 900 // SIMD-ONLY1-TARGET-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 901 // SIMD-ONLY1-TARGET-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 902 // SIMD-ONLY1-TARGET-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 903 // SIMD-ONLY1-TARGET-NEXT: br label [[FOR_INC:%.*]] 904 // SIMD-ONLY1-TARGET: for.inc: 905 // SIMD-ONLY1-TARGET-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 906 // SIMD-ONLY1-TARGET-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP2]], 1 907 // SIMD-ONLY1-TARGET-NEXT: store i32 [[INC1]], ptr [[I]], align 4 908 // SIMD-ONLY1-TARGET-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 909 // SIMD-ONLY1-TARGET: for.end: 910 // SIMD-ONLY1-TARGET-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[F]], i32 0, i32 0 911 // SIMD-ONLY1-TARGET-NEXT: store ptr [[A_ADDR]], ptr [[TMP3]], align 8 912 // SIMD-ONLY1-TARGET-NEXT: call void @"_ZZ6nestediENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[F]]) 913 // SIMD-ONLY1-TARGET-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 914 // SIMD-ONLY1-TARGET-NEXT: ret i32 [[TMP4]] 915 // 916 // 917 // SIMD-ONLY1-TARGET-X86-LABEL: define dso_local noundef i32 @_Z6nestedi 918 // SIMD-ONLY1-TARGET-X86-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { 919 // SIMD-ONLY1-TARGET-X86-NEXT: entry: 920 // SIMD-ONLY1-TARGET-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 921 // SIMD-ONLY1-TARGET-X86-NEXT: [[I:%.*]] = alloca i32, align 4 922 // SIMD-ONLY1-TARGET-X86-NEXT: [[F:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 923 // SIMD-ONLY1-TARGET-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 924 // SIMD-ONLY1-TARGET-X86-NEXT: store i32 0, ptr [[I]], align 4 925 // SIMD-ONLY1-TARGET-X86-NEXT: br label [[FOR_COND:%.*]] 926 // SIMD-ONLY1-TARGET-X86: for.cond: 927 // SIMD-ONLY1-TARGET-X86-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 928 // SIMD-ONLY1-TARGET-X86-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 929 // SIMD-ONLY1-TARGET-X86-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 930 // SIMD-ONLY1-TARGET-X86: for.body: 931 // SIMD-ONLY1-TARGET-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 932 // SIMD-ONLY1-TARGET-X86-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 933 // SIMD-ONLY1-TARGET-X86-NEXT: store i32 [[INC]], ptr [[A_ADDR]], align 4 934 // SIMD-ONLY1-TARGET-X86-NEXT: br label [[FOR_INC:%.*]] 935 // SIMD-ONLY1-TARGET-X86: for.inc: 936 // SIMD-ONLY1-TARGET-X86-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 937 // SIMD-ONLY1-TARGET-X86-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP2]], 1 938 // SIMD-ONLY1-TARGET-X86-NEXT: store i32 [[INC1]], ptr [[I]], align 4 939 // SIMD-ONLY1-TARGET-X86-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 940 // SIMD-ONLY1-TARGET-X86: for.end: 941 // SIMD-ONLY1-TARGET-X86-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[F]], i32 0, i32 0 942 // SIMD-ONLY1-TARGET-X86-NEXT: store ptr [[A_ADDR]], ptr [[TMP3]], align 4 943 // SIMD-ONLY1-TARGET-X86-NEXT: call void @"_ZZ6nestediENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(4) [[F]]) 944 // SIMD-ONLY1-TARGET-X86-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 945 // SIMD-ONLY1-TARGET-X86-NEXT: ret i32 [[TMP4]] 946 // 947