1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 9 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 20 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 21 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 22 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 23 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 24 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 25 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 26 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 27 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 28 29 // Test target codegen - host bc file has to be created first. 30 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 31 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 33 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 34 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 35 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 36 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 37 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 38 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 39 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 40 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 41 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 42 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 43 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 44 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 45 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 46 47 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 48 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 49 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 50 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 51 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 52 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 53 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 54 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 55 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 56 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 57 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 58 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 59 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 60 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 61 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 62 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 63 64 // expected-no-diagnostics 65 #ifndef HEADER 66 #define HEADER 67 68 69 70 // We have 8 target regions, but only 7 that actually will generate offloading 71 // code, only 6 will have mapped arguments, and only 4 have all-constant map 72 // sizes. 73 74 75 76 // Check target registration is registered as a Ctor. 77 78 79 template<typename tx, typename ty> 80 struct TT{ 81 tx X; 82 ty Y; 83 }; 84 85 long long get_val() { return 0; } 86 87 int foo(int n) { 88 int a = 0; 89 short aa = 0; 90 float b[10]; 91 float bn[n]; 92 double c[5][10]; 93 double cn[5][n]; 94 TT<long long, char> d; 95 96 #pragma omp target parallel for simd nowait 97 for (int i = 3; i < 32; i += 5) { 98 } 99 100 long long k = get_val(); 101 #pragma omp target parallel for simd if(target: 0) linear(k : 3) schedule(dynamic) 102 for (int i = 10; i > 1; i--) { 103 a += 1; 104 } 105 106 107 int lin = 12; 108 #pragma omp target parallel for simd if(target: 1) linear(lin, a : get_val()) 109 for (unsigned long long it = 2000; it >= 600; it-=400) { 110 aa += 1; 111 } 112 113 114 115 116 #pragma omp target parallel for simd if(target: n>10) 117 for (short it = 6; it <= 20; it-=-4) { 118 a += 1; 119 aa += 1; 120 } 121 122 // We capture 3 VLA sizes in this target region 123 124 125 126 127 128 // The names below are not necessarily consistent with the names used for the 129 // addresses above as some are repeated. 130 131 132 133 134 135 136 137 138 139 140 #pragma omp target parallel for simd if(target: n>20) schedule(static, a) 141 for (unsigned char it = 'z'; it >= 'a'; it+=-1) { 142 a += 1; 143 b[2] += 1.0; 144 bn[3] += 1.0; 145 c[1][2] += 1.0; 146 cn[1][3] += 1.0; 147 d.X += 1; 148 d.Y += 1; 149 } 150 151 return a; 152 } 153 154 // Check that the offloading functions are emitted and that the arguments are 155 // correct and loaded correctly for the target regions in foo(). 156 157 158 159 160 // Create stack storage and store argument in there. 161 162 // Create stack storage and store argument in there. 163 164 // Create stack storage and store argument in there. 165 166 // Create local storage for each capture. 167 168 169 170 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 171 172 template<typename tx> 173 tx ftemplate(int n) { 174 tx a = 0; 175 short aa = 0; 176 tx b[10]; 177 178 #pragma omp target parallel for simd if(target: n>40) 179 for (long long i = -10; i < 10; i += 3) { 180 a += 1; 181 aa += 1; 182 b[2] += 1; 183 } 184 185 return a; 186 } 187 188 static 189 int fstatic(int n) { 190 int a = 0; 191 short aa = 0; 192 char aaa = 0; 193 int b[10]; 194 195 #pragma omp target parallel for simd if(target: n>50) 196 for (unsigned i=100; i<10; i+=10) { 197 a += 1; 198 aa += 1; 199 aaa += 1; 200 b[2] += 1; 201 } 202 203 return a; 204 } 205 206 struct S1 { 207 double a; 208 209 int r1(int n){ 210 int b = n+1; 211 short int c[2][n]; 212 213 #ifdef OMP5 214 #pragma omp target parallel for simd if(n>60) nontemporal(a) 215 #else 216 #pragma omp target parallel for simd if(target: n>60) 217 #endif // OMP5 218 for (unsigned long long it = 2000; it >= 600; it -= 400) { 219 this->a = (double)b + 1.5; 220 c[1][1] = ++a; 221 } 222 223 return c[1][1] + (int)b; 224 } 225 }; 226 227 int bar(int n){ 228 int a = 0; 229 230 a += foo(n); 231 232 S1 S; 233 a += S.r1(n); 234 235 a += fstatic(n); 236 237 a += ftemplate<int>(n); 238 239 return a; 240 } 241 242 243 244 // We capture 2 VLA sizes in this target region 245 246 247 // The names below are not necessarily consistent with the names used for the 248 // addresses above as some are repeated. 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 // Check that the offloading functions are emitted and that the arguments are 269 // correct and loaded correctly for the target regions of the callees of bar(). 270 271 // Create local storage for each capture. 272 // Store captures in the context. 273 274 275 276 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 277 278 279 // Create local storage for each capture. 280 // Store captures in the context. 281 282 283 284 285 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 286 287 // Create local storage for each capture. 288 // Store captures in the context. 289 290 291 292 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 293 294 295 #endif 296 // CHECK1-LABEL: define {{[^@]+}}@_Z7get_valv 297 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 298 // CHECK1-NEXT: entry: 299 // CHECK1-NEXT: ret i64 0 300 // 301 // 302 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 303 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 304 // CHECK1-NEXT: entry: 305 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 306 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 307 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 308 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 309 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 310 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 311 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 312 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 313 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 314 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 315 // CHECK1-NEXT: [[K:%.*]] = alloca i64, align 8 316 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 317 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 318 // CHECK1-NEXT: [[LIN:%.*]] = alloca i32, align 4 319 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 320 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 321 // CHECK1-NEXT: [[A_CASTED2:%.*]] = alloca i64, align 8 322 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 323 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 324 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 325 // CHECK1-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 326 // CHECK1-NEXT: [[AA_CASTED4:%.*]] = alloca i64, align 8 327 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 8 328 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 8 329 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 8 330 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 331 // CHECK1-NEXT: [[A_CASTED11:%.*]] = alloca i64, align 8 332 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 333 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 8 334 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 8 335 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 8 336 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 337 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 338 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 339 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 340 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 341 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 342 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 343 // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() 344 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 345 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 346 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 347 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 348 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 349 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 350 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 351 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 352 // CHECK1-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, ptr @.omp_task_entry., i64 -1) 353 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP7]], i32 0, i32 0 354 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP7]]) 355 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 356 // CHECK1-NEXT: store i64 [[CALL]], ptr [[K]], align 8 357 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4 358 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4 359 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8 360 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[K]], align 8 361 // CHECK1-NEXT: store i64 [[TMP12]], ptr [[K_CASTED]], align 8 362 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, ptr [[K_CASTED]], align 8 363 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR4:[0-9]+]] 364 // CHECK1-NEXT: store i32 12, ptr [[LIN]], align 4 365 // CHECK1-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2 366 // CHECK1-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2 367 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[AA_CASTED]], align 8 368 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[LIN]], align 4 369 // CHECK1-NEXT: store i32 [[TMP16]], ptr [[LIN_CASTED]], align 4 370 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 371 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A]], align 4 372 // CHECK1-NEXT: store i32 [[TMP18]], ptr [[A_CASTED2]], align 4 373 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[A_CASTED2]], align 8 374 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 375 // CHECK1-NEXT: store i64 [[TMP15]], ptr [[TMP20]], align 8 376 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 377 // CHECK1-NEXT: store i64 [[TMP15]], ptr [[TMP21]], align 8 378 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 379 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 380 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 381 // CHECK1-NEXT: store i64 [[TMP17]], ptr [[TMP23]], align 8 382 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 383 // CHECK1-NEXT: store i64 [[TMP17]], ptr [[TMP24]], align 8 384 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 385 // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 386 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 387 // CHECK1-NEXT: store i64 [[TMP19]], ptr [[TMP26]], align 8 388 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 389 // CHECK1-NEXT: store i64 [[TMP19]], ptr [[TMP27]], align 8 390 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 391 // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8 392 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 393 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 394 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 395 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 396 // CHECK1-NEXT: store i32 1, ptr [[TMP31]], align 4 397 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 398 // CHECK1-NEXT: store i32 3, ptr [[TMP32]], align 4 399 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 400 // CHECK1-NEXT: store ptr [[TMP29]], ptr [[TMP33]], align 8 401 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 402 // CHECK1-NEXT: store ptr [[TMP30]], ptr [[TMP34]], align 8 403 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 404 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP35]], align 8 405 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 406 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP36]], align 8 407 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 408 // CHECK1-NEXT: store ptr null, ptr [[TMP37]], align 8 409 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 410 // CHECK1-NEXT: store ptr null, ptr [[TMP38]], align 8 411 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 412 // CHECK1-NEXT: store i64 0, ptr [[TMP39]], align 8 413 // CHECK1-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, ptr [[KERNEL_ARGS]]) 414 // CHECK1-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 415 // CHECK1-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 416 // CHECK1: omp_offload.failed: 417 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]]) #[[ATTR4]] 418 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 419 // CHECK1: omp_offload.cont: 420 // CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[A]], align 4 421 // CHECK1-NEXT: store i32 [[TMP42]], ptr [[A_CASTED3]], align 4 422 // CHECK1-NEXT: [[TMP43:%.*]] = load i64, ptr [[A_CASTED3]], align 8 423 // CHECK1-NEXT: [[TMP44:%.*]] = load i16, ptr [[AA]], align 2 424 // CHECK1-NEXT: store i16 [[TMP44]], ptr [[AA_CASTED4]], align 2 425 // CHECK1-NEXT: [[TMP45:%.*]] = load i64, ptr [[AA_CASTED4]], align 8 426 // CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[N_ADDR]], align 4 427 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP46]], 10 428 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 429 // CHECK1: omp_if.then: 430 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 431 // CHECK1-NEXT: store i64 [[TMP43]], ptr [[TMP47]], align 8 432 // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 433 // CHECK1-NEXT: store i64 [[TMP43]], ptr [[TMP48]], align 8 434 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 435 // CHECK1-NEXT: store ptr null, ptr [[TMP49]], align 8 436 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 437 // CHECK1-NEXT: store i64 [[TMP45]], ptr [[TMP50]], align 8 438 // CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 439 // CHECK1-NEXT: store i64 [[TMP45]], ptr [[TMP51]], align 8 440 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 441 // CHECK1-NEXT: store ptr null, ptr [[TMP52]], align 8 442 // CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 443 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 444 // CHECK1-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 445 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0 446 // CHECK1-NEXT: store i32 1, ptr [[TMP55]], align 4 447 // CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1 448 // CHECK1-NEXT: store i32 2, ptr [[TMP56]], align 4 449 // CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2 450 // CHECK1-NEXT: store ptr [[TMP53]], ptr [[TMP57]], align 8 451 // CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3 452 // CHECK1-NEXT: store ptr [[TMP54]], ptr [[TMP58]], align 8 453 // CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4 454 // CHECK1-NEXT: store ptr @.offload_sizes.5, ptr [[TMP59]], align 8 455 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5 456 // CHECK1-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP60]], align 8 457 // CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6 458 // CHECK1-NEXT: store ptr null, ptr [[TMP61]], align 8 459 // CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7 460 // CHECK1-NEXT: store ptr null, ptr [[TMP62]], align 8 461 // CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8 462 // CHECK1-NEXT: store i64 0, ptr [[TMP63]], align 8 463 // CHECK1-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, ptr [[KERNEL_ARGS8]]) 464 // CHECK1-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 465 // CHECK1-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 466 // CHECK1: omp_offload.failed9: 467 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP43]], i64 [[TMP45]]) #[[ATTR4]] 468 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT10]] 469 // CHECK1: omp_offload.cont10: 470 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 471 // CHECK1: omp_if.else: 472 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP43]], i64 [[TMP45]]) #[[ATTR4]] 473 // CHECK1-NEXT: br label [[OMP_IF_END]] 474 // CHECK1: omp_if.end: 475 // CHECK1-NEXT: [[TMP66:%.*]] = load i32, ptr [[A]], align 4 476 // CHECK1-NEXT: store i32 [[TMP66]], ptr [[DOTCAPTURE_EXPR_]], align 4 477 // CHECK1-NEXT: [[TMP67:%.*]] = load i32, ptr [[A]], align 4 478 // CHECK1-NEXT: store i32 [[TMP67]], ptr [[A_CASTED11]], align 4 479 // CHECK1-NEXT: [[TMP68:%.*]] = load i64, ptr [[A_CASTED11]], align 8 480 // CHECK1-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 481 // CHECK1-NEXT: store i32 [[TMP69]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 482 // CHECK1-NEXT: [[TMP70:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 483 // CHECK1-NEXT: [[TMP71:%.*]] = load i32, ptr [[N_ADDR]], align 4 484 // CHECK1-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP71]], 20 485 // CHECK1-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]] 486 // CHECK1: omp_if.then13: 487 // CHECK1-NEXT: [[TMP72:%.*]] = mul nuw i64 [[TMP2]], 4 488 // CHECK1-NEXT: [[TMP73:%.*]] = mul nuw i64 5, [[TMP5]] 489 // CHECK1-NEXT: [[TMP74:%.*]] = mul nuw i64 [[TMP73]], 8 490 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.8, i64 80, i1 false) 491 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 492 // CHECK1-NEXT: store i64 [[TMP68]], ptr [[TMP75]], align 8 493 // CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 494 // CHECK1-NEXT: store i64 [[TMP68]], ptr [[TMP76]], align 8 495 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0 496 // CHECK1-NEXT: store ptr null, ptr [[TMP77]], align 8 497 // CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 498 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP78]], align 8 499 // CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 500 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP79]], align 8 501 // CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1 502 // CHECK1-NEXT: store ptr null, ptr [[TMP80]], align 8 503 // CHECK1-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 504 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP81]], align 8 505 // CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 506 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP82]], align 8 507 // CHECK1-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 2 508 // CHECK1-NEXT: store ptr null, ptr [[TMP83]], align 8 509 // CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 510 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP84]], align 8 511 // CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 512 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP85]], align 8 513 // CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 514 // CHECK1-NEXT: store i64 [[TMP72]], ptr [[TMP86]], align 8 515 // CHECK1-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 3 516 // CHECK1-NEXT: store ptr null, ptr [[TMP87]], align 8 517 // CHECK1-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 518 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP88]], align 8 519 // CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 520 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP89]], align 8 521 // CHECK1-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 4 522 // CHECK1-NEXT: store ptr null, ptr [[TMP90]], align 8 523 // CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 524 // CHECK1-NEXT: store i64 5, ptr [[TMP91]], align 8 525 // CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 526 // CHECK1-NEXT: store i64 5, ptr [[TMP92]], align 8 527 // CHECK1-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 5 528 // CHECK1-NEXT: store ptr null, ptr [[TMP93]], align 8 529 // CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 530 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP94]], align 8 531 // CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 532 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP95]], align 8 533 // CHECK1-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 6 534 // CHECK1-NEXT: store ptr null, ptr [[TMP96]], align 8 535 // CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 536 // CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP97]], align 8 537 // CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 538 // CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP98]], align 8 539 // CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 540 // CHECK1-NEXT: store i64 [[TMP74]], ptr [[TMP99]], align 8 541 // CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 7 542 // CHECK1-NEXT: store ptr null, ptr [[TMP100]], align 8 543 // CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 544 // CHECK1-NEXT: store ptr [[D]], ptr [[TMP101]], align 8 545 // CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 546 // CHECK1-NEXT: store ptr [[D]], ptr [[TMP102]], align 8 547 // CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 8 548 // CHECK1-NEXT: store ptr null, ptr [[TMP103]], align 8 549 // CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 550 // CHECK1-NEXT: store i64 [[TMP70]], ptr [[TMP104]], align 8 551 // CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 552 // CHECK1-NEXT: store i64 [[TMP70]], ptr [[TMP105]], align 8 553 // CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 9 554 // CHECK1-NEXT: store ptr null, ptr [[TMP106]], align 8 555 // CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 556 // CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 557 // CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 558 // CHECK1-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 559 // CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0 560 // CHECK1-NEXT: store i32 1, ptr [[TMP110]], align 4 561 // CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1 562 // CHECK1-NEXT: store i32 10, ptr [[TMP111]], align 4 563 // CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2 564 // CHECK1-NEXT: store ptr [[TMP107]], ptr [[TMP112]], align 8 565 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3 566 // CHECK1-NEXT: store ptr [[TMP108]], ptr [[TMP113]], align 8 567 // CHECK1-NEXT: [[TMP114:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4 568 // CHECK1-NEXT: store ptr [[TMP109]], ptr [[TMP114]], align 8 569 // CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5 570 // CHECK1-NEXT: store ptr @.offload_maptypes.9, ptr [[TMP115]], align 8 571 // CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6 572 // CHECK1-NEXT: store ptr null, ptr [[TMP116]], align 8 573 // CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7 574 // CHECK1-NEXT: store ptr null, ptr [[TMP117]], align 8 575 // CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8 576 // CHECK1-NEXT: store i64 0, ptr [[TMP118]], align 8 577 // CHECK1-NEXT: [[TMP119:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, ptr [[KERNEL_ARGS17]]) 578 // CHECK1-NEXT: [[TMP120:%.*]] = icmp ne i32 [[TMP119]], 0 579 // CHECK1-NEXT: br i1 [[TMP120]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] 580 // CHECK1: omp_offload.failed18: 581 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP68]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP70]]) #[[ATTR4]] 582 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT19]] 583 // CHECK1: omp_offload.cont19: 584 // CHECK1-NEXT: br label [[OMP_IF_END21:%.*]] 585 // CHECK1: omp_if.else20: 586 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP68]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP70]]) #[[ATTR4]] 587 // CHECK1-NEXT: br label [[OMP_IF_END21]] 588 // CHECK1: omp_if.end21: 589 // CHECK1-NEXT: [[TMP121:%.*]] = load i32, ptr [[A]], align 4 590 // CHECK1-NEXT: [[TMP122:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 591 // CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP122]]) 592 // CHECK1-NEXT: ret i32 [[TMP121]] 593 // 594 // 595 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 596 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] { 597 // CHECK1-NEXT: entry: 598 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @.omp_outlined.) 599 // CHECK1-NEXT: ret void 600 // 601 // 602 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 603 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 604 // CHECK1-NEXT: entry: 605 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 606 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 607 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 608 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 609 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 610 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 611 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 612 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 613 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 614 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 615 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 616 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 617 // CHECK1-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 618 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 619 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 620 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 621 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 622 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 623 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 624 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 625 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 626 // CHECK1: cond.true: 627 // CHECK1-NEXT: br label [[COND_END:%.*]] 628 // CHECK1: cond.false: 629 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 630 // CHECK1-NEXT: br label [[COND_END]] 631 // CHECK1: cond.end: 632 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 633 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 634 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 635 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 636 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 637 // CHECK1: omp.inner.for.cond: 638 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 639 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 640 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 641 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 642 // CHECK1: omp.inner.for.body: 643 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 644 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 645 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 646 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 647 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 648 // CHECK1: omp.body.continue: 649 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 650 // CHECK1: omp.inner.for.inc: 651 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 652 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 653 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 654 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 655 // CHECK1: omp.inner.for.end: 656 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 657 // CHECK1: omp.loop.exit: 658 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 659 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 660 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 661 // CHECK1-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 662 // CHECK1: .omp.final.then: 663 // CHECK1-NEXT: store i32 33, ptr [[I]], align 4 664 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 665 // CHECK1: .omp.final.done: 666 // CHECK1-NEXT: ret void 667 // 668 // 669 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 670 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 671 // CHECK1-NEXT: entry: 672 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 673 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 674 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 675 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 676 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 677 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 678 // CHECK1-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 679 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 680 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 681 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 682 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 683 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 684 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 685 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 686 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 687 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 688 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 689 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 690 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 691 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 692 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 693 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 694 // CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !25 695 // CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25 696 // CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25 697 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !25 698 // CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !25 699 // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !25 700 // CHECK1-NEXT: store i32 1, ptr [[KERNEL_ARGS_I]], align 4, !noalias !25 701 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 702 // CHECK1-NEXT: store i32 0, ptr [[TMP9]], align 4, !noalias !25 703 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 704 // CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8, !noalias !25 705 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 706 // CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8, !noalias !25 707 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 708 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8, !noalias !25 709 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 710 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8, !noalias !25 711 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 712 // CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8, !noalias !25 713 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 714 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8, !noalias !25 715 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 716 // CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8, !noalias !25 717 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__tgt_target_kernel_nowait(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, ptr [[KERNEL_ARGS_I]], i32 0, ptr null, i32 0, ptr null) 718 // CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 719 // CHECK1-NEXT: br i1 [[TMP18]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 720 // CHECK1: omp_offload.failed.i: 721 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] 722 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 723 // CHECK1: .omp_outlined..1.exit: 724 // CHECK1-NEXT: ret i32 0 725 // 726 // 727 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 728 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 729 // CHECK1-NEXT: entry: 730 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 731 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 732 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 733 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 734 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 735 // CHECK1-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8 736 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 737 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 738 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 739 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[K_ADDR]], align 8 740 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[K_CASTED]], align 8 741 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[K_CASTED]], align 8 742 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..2, i64 [[TMP1]], i64 [[TMP3]]) 743 // CHECK1-NEXT: ret void 744 // 745 // 746 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 747 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 748 // CHECK1-NEXT: entry: 749 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 750 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 751 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 752 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 753 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 754 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 755 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 756 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 757 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 758 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 759 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 760 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 761 // CHECK1-NEXT: [[K1:%.*]] = alloca i64, align 8 762 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 763 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 764 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 765 // CHECK1-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8 766 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[K_ADDR]], align 8 767 // CHECK1-NEXT: store i64 [[TMP0]], ptr [[DOTLINEAR_START]], align 8 768 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 769 // CHECK1-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 4 770 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 771 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 772 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 773 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 774 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 775 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1) 776 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 777 // CHECK1: omp.dispatch.cond: 778 // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP2]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]) 779 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 780 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 781 // CHECK1: omp.dispatch.body: 782 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 783 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 784 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 785 // CHECK1: omp.inner.for.cond: 786 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] 787 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] 788 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 789 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 790 // CHECK1: omp.inner.for.body: 791 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 792 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 793 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 794 // CHECK1-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] 795 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP26]] 796 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 797 // CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 798 // CHECK1-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 799 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV]] 800 // CHECK1-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP26]] 801 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] 802 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 803 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] 804 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 805 // CHECK1: omp.body.continue: 806 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 807 // CHECK1: omp.inner.for.inc: 808 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 809 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 810 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 811 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] 812 // CHECK1: omp.inner.for.end: 813 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 814 // CHECK1: omp.dispatch.inc: 815 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 816 // CHECK1: omp.dispatch.end: 817 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 818 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 819 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 820 // CHECK1: .omp.final.then: 821 // CHECK1-NEXT: store i32 1, ptr [[I]], align 4 822 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 823 // CHECK1: .omp.final.done: 824 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 825 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 826 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 827 // CHECK1: .omp.linear.pu: 828 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, ptr [[K1]], align 8 829 // CHECK1-NEXT: store i64 [[TMP16]], ptr [[K_ADDR]], align 8 830 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 831 // CHECK1: .omp.linear.pu.done: 832 // CHECK1-NEXT: ret void 833 // 834 // 835 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 836 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 837 // CHECK1-NEXT: entry: 838 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 839 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 840 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 841 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 842 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 843 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 844 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 845 // CHECK1-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 846 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 847 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 848 // CHECK1-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 849 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 850 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 851 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 852 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 853 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 854 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 855 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8 856 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..3, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 857 // CHECK1-NEXT: ret void 858 // 859 // 860 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 861 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 862 // CHECK1-NEXT: entry: 863 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 864 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 865 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 866 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 867 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 868 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 869 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 870 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 871 // CHECK1-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 872 // CHECK1-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 873 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 874 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 875 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 876 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 877 // CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8 878 // CHECK1-NEXT: [[LIN2:%.*]] = alloca i32, align 4 879 // CHECK1-NEXT: [[A3:%.*]] = alloca i32, align 4 880 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 881 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 882 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 883 // CHECK1-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 884 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 885 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 886 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 887 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 888 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 889 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 890 // CHECK1-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 891 // CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 892 // CHECK1-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 893 // CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 894 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 895 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 896 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 897 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]]) 898 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 899 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 900 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 901 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 902 // CHECK1: cond.true: 903 // CHECK1-NEXT: br label [[COND_END:%.*]] 904 // CHECK1: cond.false: 905 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 906 // CHECK1-NEXT: br label [[COND_END]] 907 // CHECK1: cond.end: 908 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 909 // CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 910 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 911 // CHECK1-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 912 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 913 // CHECK1: omp.inner.for.cond: 914 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29:![0-9]+]] 915 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP29]] 916 // CHECK1-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 917 // CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 918 // CHECK1: omp.inner.for.body: 919 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 920 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 921 // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 922 // CHECK1-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP29]] 923 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP29]] 924 // CHECK1-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 925 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 926 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]] 927 // CHECK1-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 928 // CHECK1-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 929 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 930 // CHECK1-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP29]] 931 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP29]] 932 // CHECK1-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 933 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 934 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]] 935 // CHECK1-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 936 // CHECK1-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 937 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 938 // CHECK1-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP29]] 939 // CHECK1-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] 940 // CHECK1-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 941 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 942 // CHECK1-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 943 // CHECK1-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] 944 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 945 // CHECK1: omp.body.continue: 946 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 947 // CHECK1: omp.inner.for.inc: 948 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 949 // CHECK1-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 950 // CHECK1-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 951 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] 952 // CHECK1: omp.inner.for.end: 953 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 954 // CHECK1: omp.loop.exit: 955 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 956 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 957 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 958 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 959 // CHECK1: .omp.final.then: 960 // CHECK1-NEXT: store i64 400, ptr [[IT]], align 8 961 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 962 // CHECK1: .omp.final.done: 963 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 964 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 965 // CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 966 // CHECK1: .omp.linear.pu: 967 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 968 // CHECK1-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 969 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 970 // CHECK1-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 971 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 972 // CHECK1: .omp.linear.pu.done: 973 // CHECK1-NEXT: ret void 974 // 975 // 976 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 977 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 978 // CHECK1-NEXT: entry: 979 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 980 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 981 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 982 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 983 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 984 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 985 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 986 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 987 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 988 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 989 // CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 990 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 991 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..4, i64 [[TMP1]], i64 [[TMP3]]) 992 // CHECK1-NEXT: ret void 993 // 994 // 995 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 996 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 997 // CHECK1-NEXT: entry: 998 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 999 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1000 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1001 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1002 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1003 // CHECK1-NEXT: [[TMP:%.*]] = alloca i16, align 2 1004 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1005 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1006 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1007 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1008 // CHECK1-NEXT: [[IT:%.*]] = alloca i16, align 2 1009 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1010 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1011 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1012 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1013 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1014 // CHECK1-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 1015 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1016 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1017 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1018 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1019 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1020 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1021 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 1022 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1023 // CHECK1: cond.true: 1024 // CHECK1-NEXT: br label [[COND_END:%.*]] 1025 // CHECK1: cond.false: 1026 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1027 // CHECK1-NEXT: br label [[COND_END]] 1028 // CHECK1: cond.end: 1029 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1030 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1031 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1032 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1033 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1034 // CHECK1: omp.inner.for.cond: 1035 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]] 1036 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]] 1037 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1038 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1039 // CHECK1: omp.inner.for.body: 1040 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 1041 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 1042 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 1043 // CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 1044 // CHECK1-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP32]] 1045 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] 1046 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 1047 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] 1048 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] 1049 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 1050 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 1051 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 1052 // CHECK1-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] 1053 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1054 // CHECK1: omp.body.continue: 1055 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1056 // CHECK1: omp.inner.for.inc: 1057 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 1058 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 1059 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 1060 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] 1061 // CHECK1: omp.inner.for.end: 1062 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1063 // CHECK1: omp.loop.exit: 1064 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1065 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1066 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 1067 // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1068 // CHECK1: .omp.final.then: 1069 // CHECK1-NEXT: store i16 22, ptr [[IT]], align 2 1070 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1071 // CHECK1: .omp.final.done: 1072 // CHECK1-NEXT: ret void 1073 // 1074 // 1075 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 1076 // CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 1077 // CHECK1-NEXT: entry: 1078 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1079 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1080 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1081 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 1082 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1083 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1084 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1085 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 1086 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 1087 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1088 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1089 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1090 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1091 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1092 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1093 // CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 1094 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1095 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1096 // CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 1097 // CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 1098 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 1099 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 1100 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1101 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1102 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 1103 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1104 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1105 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 1106 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 1107 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 1108 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 1109 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 1110 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 1111 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 1112 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 1113 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 1114 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @.omp_outlined..7, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]]) 1115 // CHECK1-NEXT: ret void 1116 // 1117 // 1118 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 1119 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 1120 // CHECK1-NEXT: entry: 1121 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1122 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1123 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1124 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1125 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1126 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 1127 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1128 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1129 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1130 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 1131 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 1132 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1133 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1134 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 1135 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1136 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1137 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1138 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1139 // CHECK1-NEXT: [[IT:%.*]] = alloca i8, align 1 1140 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1141 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1142 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1143 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1144 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1145 // CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 1146 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1147 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1148 // CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 1149 // CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 1150 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 1151 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 1152 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1153 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1154 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 1155 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1156 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1157 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 1158 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 1159 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 1160 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1161 // CHECK1-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 1162 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1163 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1164 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 1165 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1166 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 1167 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 1168 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1169 // CHECK1: omp.dispatch.cond: 1170 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1171 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 1172 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1173 // CHECK1: cond.true: 1174 // CHECK1-NEXT: br label [[COND_END:%.*]] 1175 // CHECK1: cond.false: 1176 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1177 // CHECK1-NEXT: br label [[COND_END]] 1178 // CHECK1: cond.end: 1179 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 1180 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1181 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1182 // CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 1183 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1184 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1185 // CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 1186 // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1187 // CHECK1: omp.dispatch.body: 1188 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1189 // CHECK1: omp.inner.for.cond: 1190 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]] 1191 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]] 1192 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 1193 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1194 // CHECK1: omp.inner.for.body: 1195 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 1196 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 1197 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 1198 // CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 1199 // CHECK1-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP35]] 1200 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] 1201 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 1202 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] 1203 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 1204 // CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] 1205 // CHECK1-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 1206 // CHECK1-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 1207 // CHECK1-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 1208 // CHECK1-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] 1209 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 1210 // CHECK1-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP35]] 1211 // CHECK1-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 1212 // CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 1213 // CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 1214 // CHECK1-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP35]] 1215 // CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 1216 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 1217 // CHECK1-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]] 1218 // CHECK1-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 1219 // CHECK1-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]] 1220 // CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 1221 // CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]] 1222 // CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3 1223 // CHECK1-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP35]] 1224 // CHECK1-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 1225 // CHECK1-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP35]] 1226 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 1227 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]] 1228 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 1229 // CHECK1-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]] 1230 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 1231 // CHECK1-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]] 1232 // CHECK1-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 1233 // CHECK1-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 1234 // CHECK1-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 1235 // CHECK1-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]] 1236 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1237 // CHECK1: omp.body.continue: 1238 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1239 // CHECK1: omp.inner.for.inc: 1240 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 1241 // CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 1242 // CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 1243 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] 1244 // CHECK1: omp.inner.for.end: 1245 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1246 // CHECK1: omp.dispatch.inc: 1247 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1248 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1249 // CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 1250 // CHECK1-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 1251 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1252 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1253 // CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 1254 // CHECK1-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 1255 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1256 // CHECK1: omp.dispatch.end: 1257 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 1258 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1259 // CHECK1-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 1260 // CHECK1-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1261 // CHECK1: .omp.final.then: 1262 // CHECK1-NEXT: store i8 96, ptr [[IT]], align 1 1263 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1264 // CHECK1: .omp.final.done: 1265 // CHECK1-NEXT: ret void 1266 // 1267 // 1268 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 1269 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1270 // CHECK1-NEXT: entry: 1271 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1272 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1273 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1274 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1275 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 1276 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 1277 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 1278 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 1279 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1280 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A]], align 4 1281 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 1282 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 1283 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 1284 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1285 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 1286 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 1287 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 1288 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 1289 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1290 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 1291 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 1292 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 1293 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 1294 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 1295 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 1296 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 1297 // CHECK1-NEXT: ret i32 [[TMP8]] 1298 // 1299 // 1300 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1301 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1302 // CHECK1-NEXT: entry: 1303 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1304 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1305 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 1306 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 1307 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1308 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1309 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 1310 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 1311 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 1312 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1313 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1314 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1315 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1316 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 1317 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1318 // CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4 1319 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 1320 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1321 // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() 1322 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 1323 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 1324 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 1325 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 1326 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 1327 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 1328 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 1329 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 1330 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 1331 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1332 // CHECK1: omp_if.then: 1333 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 1334 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 1335 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 1336 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.11, i64 40, i1 false) 1337 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1338 // CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 8 1339 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1340 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP11]], align 8 1341 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1342 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 1343 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1344 // CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP13]], align 8 1345 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1346 // CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP14]], align 8 1347 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1348 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 1349 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1350 // CHECK1-NEXT: store i64 2, ptr [[TMP16]], align 8 1351 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1352 // CHECK1-NEXT: store i64 2, ptr [[TMP17]], align 8 1353 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1354 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 1355 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1356 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP19]], align 8 1357 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1358 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP20]], align 8 1359 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1360 // CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8 1361 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1362 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 8 1363 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1364 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 8 1365 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1366 // CHECK1-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 8 1367 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1368 // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 1369 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1370 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1371 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1372 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1373 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1374 // CHECK1-NEXT: store i32 1, ptr [[TMP29]], align 4 1375 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1376 // CHECK1-NEXT: store i32 5, ptr [[TMP30]], align 4 1377 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1378 // CHECK1-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 8 1379 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1380 // CHECK1-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 8 1381 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1382 // CHECK1-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 8 1383 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1384 // CHECK1-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP34]], align 8 1385 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1386 // CHECK1-NEXT: store ptr null, ptr [[TMP35]], align 8 1387 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1388 // CHECK1-NEXT: store ptr null, ptr [[TMP36]], align 8 1389 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1390 // CHECK1-NEXT: store i64 0, ptr [[TMP37]], align 8 1391 // CHECK1-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, ptr [[KERNEL_ARGS]]) 1392 // CHECK1-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 1393 // CHECK1-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1394 // CHECK1: omp_offload.failed: 1395 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR4]] 1396 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1397 // CHECK1: omp_offload.cont: 1398 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1399 // CHECK1: omp_if.else: 1400 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR4]] 1401 // CHECK1-NEXT: br label [[OMP_IF_END]] 1402 // CHECK1: omp_if.end: 1403 // CHECK1-NEXT: [[TMP40:%.*]] = mul nsw i64 1, [[TMP2]] 1404 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP40]] 1405 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 1406 // CHECK1-NEXT: [[TMP41:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 1407 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP41]] to i32 1408 // CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[B]], align 4 1409 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP42]] 1410 // CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 1411 // CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP43]]) 1412 // CHECK1-NEXT: ret i32 [[ADD3]] 1413 // 1414 // 1415 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 1416 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1417 // CHECK1-NEXT: entry: 1418 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1419 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1420 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1421 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 1422 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1423 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1424 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1425 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1426 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 1427 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 1428 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 1429 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1430 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 1431 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 1432 // CHECK1-NEXT: store i8 0, ptr [[AAA]], align 1 1433 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 1434 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 1435 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 1436 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 1437 // CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 1438 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1439 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1 1440 // CHECK1-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1 1441 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 1442 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 1443 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 1444 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1445 // CHECK1: omp_if.then: 1446 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1447 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP7]], align 8 1448 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1449 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP8]], align 8 1450 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1451 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 1452 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1453 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP10]], align 8 1454 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1455 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP11]], align 8 1456 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1457 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 1458 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1459 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP13]], align 8 1460 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1461 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP14]], align 8 1462 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1463 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 1464 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1465 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP16]], align 8 1466 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1467 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP17]], align 8 1468 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1469 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 1470 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1471 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1472 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1473 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1474 // CHECK1-NEXT: store i32 1, ptr [[TMP21]], align 4 1475 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1476 // CHECK1-NEXT: store i32 4, ptr [[TMP22]], align 4 1477 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1478 // CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8 1479 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1480 // CHECK1-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8 1481 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1482 // CHECK1-NEXT: store ptr @.offload_sizes.14, ptr [[TMP25]], align 8 1483 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1484 // CHECK1-NEXT: store ptr @.offload_maptypes.15, ptr [[TMP26]], align 8 1485 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1486 // CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8 1487 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1488 // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8 1489 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1490 // CHECK1-NEXT: store i64 0, ptr [[TMP29]], align 8 1491 // CHECK1-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, ptr [[KERNEL_ARGS]]) 1492 // CHECK1-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 1493 // CHECK1-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1494 // CHECK1: omp_offload.failed: 1495 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]] 1496 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1497 // CHECK1: omp_offload.cont: 1498 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1499 // CHECK1: omp_if.else: 1500 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]] 1501 // CHECK1-NEXT: br label [[OMP_IF_END]] 1502 // CHECK1: omp_if.end: 1503 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[A]], align 4 1504 // CHECK1-NEXT: ret i32 [[TMP32]] 1505 // 1506 // 1507 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1508 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1509 // CHECK1-NEXT: entry: 1510 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1511 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1512 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1513 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1514 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1515 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1516 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 1517 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 1518 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 1519 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1520 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 1521 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 1522 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 1523 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 1524 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 1525 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 1526 // CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 1527 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1528 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 1529 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1530 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1531 // CHECK1: omp_if.then: 1532 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1533 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 1534 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1535 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 8 1536 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1537 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 1538 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1539 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 8 1540 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1541 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP9]], align 8 1542 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1543 // CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8 1544 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1545 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP11]], align 8 1546 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1547 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP12]], align 8 1548 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1549 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8 1550 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1551 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1552 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1553 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1554 // CHECK1-NEXT: store i32 1, ptr [[TMP16]], align 4 1555 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1556 // CHECK1-NEXT: store i32 3, ptr [[TMP17]], align 4 1557 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1558 // CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8 1559 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1560 // CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8 1561 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1562 // CHECK1-NEXT: store ptr @.offload_sizes.17, ptr [[TMP20]], align 8 1563 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1564 // CHECK1-NEXT: store ptr @.offload_maptypes.18, ptr [[TMP21]], align 8 1565 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1566 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 1567 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1568 // CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8 1569 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1570 // CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 8 1571 // CHECK1-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, ptr [[KERNEL_ARGS]]) 1572 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 1573 // CHECK1-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1574 // CHECK1: omp_offload.failed: 1575 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] 1576 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1577 // CHECK1: omp_offload.cont: 1578 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1579 // CHECK1: omp_if.else: 1580 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] 1581 // CHECK1-NEXT: br label [[OMP_IF_END]] 1582 // CHECK1: omp_if.end: 1583 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[A]], align 4 1584 // CHECK1-NEXT: ret i32 [[TMP27]] 1585 // 1586 // 1587 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 1588 // CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1589 // CHECK1-NEXT: entry: 1590 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1591 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1592 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1593 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1594 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1595 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1596 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1597 // CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 1598 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1599 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1600 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1601 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1602 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1603 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1604 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1605 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 1606 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 1607 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8 1608 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @.omp_outlined..10, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) 1609 // CHECK1-NEXT: ret void 1610 // 1611 // 1612 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 1613 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 1614 // CHECK1-NEXT: entry: 1615 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1616 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1617 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1618 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1619 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1620 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1621 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1622 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1623 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 1624 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1625 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1626 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1627 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1628 // CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8 1629 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1630 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1631 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1632 // CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 1633 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1634 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1635 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1636 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1637 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1638 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1639 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1640 // CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 1641 // CHECK1-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 1642 // CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 1643 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1644 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1645 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 1646 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 1647 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 1648 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 1649 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1650 // CHECK1: cond.true: 1651 // CHECK1-NEXT: br label [[COND_END:%.*]] 1652 // CHECK1: cond.false: 1653 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 1654 // CHECK1-NEXT: br label [[COND_END]] 1655 // CHECK1: cond.end: 1656 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1657 // CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 1658 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 1659 // CHECK1-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8 1660 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1661 // CHECK1: omp.inner.for.cond: 1662 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38:![0-9]+]] 1663 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP38]] 1664 // CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 1665 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1666 // CHECK1: omp.inner.for.body: 1667 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 1668 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 1669 // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 1670 // CHECK1-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP38]] 1671 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]] 1672 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 1673 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 1674 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 1675 // CHECK1-NEXT: store double [[ADD]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP38]] 1676 // CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 1677 // CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP38]] 1678 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 1679 // CHECK1-NEXT: store double [[INC]], ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP38]] 1680 // CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 1681 // CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 1682 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]] 1683 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 1684 // CHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP38]] 1685 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1686 // CHECK1: omp.body.continue: 1687 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1688 // CHECK1: omp.inner.for.inc: 1689 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 1690 // CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 1691 // CHECK1-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 1692 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]] 1693 // CHECK1: omp.inner.for.end: 1694 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1695 // CHECK1: omp.loop.exit: 1696 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 1697 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1698 // CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 1699 // CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1700 // CHECK1: .omp.final.then: 1701 // CHECK1-NEXT: store i64 400, ptr [[IT]], align 8 1702 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1703 // CHECK1: .omp.final.done: 1704 // CHECK1-NEXT: ret void 1705 // 1706 // 1707 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 1708 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1709 // CHECK1-NEXT: entry: 1710 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1711 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1712 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1713 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1714 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1715 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1716 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1717 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1718 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1719 // CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 1720 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1721 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1722 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 1723 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 1724 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 1725 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1726 // CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 1727 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1728 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 1729 // CHECK1-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 1730 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 1731 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @.omp_outlined..13, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]]) 1732 // CHECK1-NEXT: ret void 1733 // 1734 // 1735 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 1736 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1737 // CHECK1-NEXT: entry: 1738 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1739 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1740 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1741 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1742 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1743 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1744 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1745 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1746 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1747 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1748 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1749 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1750 // CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 1751 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1752 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1753 // CHECK1-NEXT: ret void 1754 // 1755 // 1756 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 1757 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1758 // CHECK1-NEXT: entry: 1759 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1760 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1761 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1762 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1763 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1764 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1765 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1766 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1767 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1768 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 1769 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 1770 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 1771 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1772 // CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 1773 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1774 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..16, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) 1775 // CHECK1-NEXT: ret void 1776 // 1777 // 1778 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 1779 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1780 // CHECK1-NEXT: entry: 1781 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1782 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1783 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1784 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1785 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1786 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1787 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 1788 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1789 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1790 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1791 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1792 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 1793 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1794 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1795 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1796 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1797 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1798 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1799 // CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 1800 // CHECK1-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 1801 // CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 1802 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1803 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1804 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 1805 // CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 1806 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 1807 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 1808 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1809 // CHECK1: cond.true: 1810 // CHECK1-NEXT: br label [[COND_END:%.*]] 1811 // CHECK1: cond.false: 1812 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 1813 // CHECK1-NEXT: br label [[COND_END]] 1814 // CHECK1: cond.end: 1815 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1816 // CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 1817 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 1818 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 1819 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1820 // CHECK1: omp.inner.for.cond: 1821 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41:![0-9]+]] 1822 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP41]] 1823 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 1824 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1825 // CHECK1: omp.inner.for.body: 1826 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41]] 1827 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 1828 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 1829 // CHECK1-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP41]] 1830 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]] 1831 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 1832 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]] 1833 // CHECK1-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]] 1834 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 1835 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 1836 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 1837 // CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]] 1838 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 1839 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]] 1840 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 1841 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]] 1842 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1843 // CHECK1: omp.body.continue: 1844 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1845 // CHECK1: omp.inner.for.inc: 1846 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41]] 1847 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 1848 // CHECK1-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41]] 1849 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]] 1850 // CHECK1: omp.inner.for.end: 1851 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1852 // CHECK1: omp.loop.exit: 1853 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 1854 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1855 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1856 // CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1857 // CHECK1: .omp.final.then: 1858 // CHECK1-NEXT: store i64 11, ptr [[I]], align 8 1859 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1860 // CHECK1: .omp.final.done: 1861 // CHECK1-NEXT: ret void 1862 // 1863 // 1864 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1865 // CHECK1-SAME: () #[[ATTR8:[0-9]+]] { 1866 // CHECK1-NEXT: entry: 1867 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1868 // CHECK1-NEXT: ret void 1869 // 1870 // 1871 // CHECK3-LABEL: define {{[^@]+}}@_Z7get_valv 1872 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 1873 // CHECK3-NEXT: entry: 1874 // CHECK3-NEXT: ret i64 0 1875 // 1876 // 1877 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 1878 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 1879 // CHECK3-NEXT: entry: 1880 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1881 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 1882 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 1883 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 1884 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 1885 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1886 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 1887 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1888 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 1889 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 1890 // CHECK3-NEXT: [[K:%.*]] = alloca i64, align 8 1891 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1892 // CHECK3-NEXT: [[LIN:%.*]] = alloca i32, align 4 1893 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 1894 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 1895 // CHECK3-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 1896 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 1897 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 1898 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 1899 // CHECK3-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 1900 // CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 1901 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 4 1902 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 4 1903 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 4 1904 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1905 // CHECK3-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 1906 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 1907 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 4 1908 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 4 1909 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 4 1910 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 1911 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 1912 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1913 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 1914 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 1915 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 1916 // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() 1917 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 1918 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 1919 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 1920 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 1921 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 1922 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 1923 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 1924 // CHECK3-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, ptr @.omp_task_entry., i64 -1) 1925 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP5]], i32 0, i32 0 1926 // CHECK3-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP5]]) 1927 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 1928 // CHECK3-NEXT: store i64 [[CALL]], ptr [[K]], align 8 1929 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 1930 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 1931 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 1932 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP9]], ptr [[K]]) #[[ATTR4:[0-9]+]] 1933 // CHECK3-NEXT: store i32 12, ptr [[LIN]], align 4 1934 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2 1935 // CHECK3-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2 1936 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4 1937 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[LIN]], align 4 1938 // CHECK3-NEXT: store i32 [[TMP12]], ptr [[LIN_CASTED]], align 4 1939 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 1940 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4 1941 // CHECK3-NEXT: store i32 [[TMP14]], ptr [[A_CASTED2]], align 4 1942 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[A_CASTED2]], align 4 1943 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1944 // CHECK3-NEXT: store i32 [[TMP11]], ptr [[TMP16]], align 4 1945 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1946 // CHECK3-NEXT: store i32 [[TMP11]], ptr [[TMP17]], align 4 1947 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1948 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 1949 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1950 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[TMP19]], align 4 1951 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1952 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[TMP20]], align 4 1953 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1954 // CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 4 1955 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1956 // CHECK3-NEXT: store i32 [[TMP15]], ptr [[TMP22]], align 4 1957 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1958 // CHECK3-NEXT: store i32 [[TMP15]], ptr [[TMP23]], align 4 1959 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1960 // CHECK3-NEXT: store ptr null, ptr [[TMP24]], align 4 1961 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1962 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1963 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1964 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1965 // CHECK3-NEXT: store i32 1, ptr [[TMP27]], align 4 1966 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1967 // CHECK3-NEXT: store i32 3, ptr [[TMP28]], align 4 1968 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1969 // CHECK3-NEXT: store ptr [[TMP25]], ptr [[TMP29]], align 4 1970 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1971 // CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP30]], align 4 1972 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1973 // CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP31]], align 4 1974 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1975 // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP32]], align 4 1976 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1977 // CHECK3-NEXT: store ptr null, ptr [[TMP33]], align 4 1978 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1979 // CHECK3-NEXT: store ptr null, ptr [[TMP34]], align 4 1980 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1981 // CHECK3-NEXT: store i64 0, ptr [[TMP35]], align 8 1982 // CHECK3-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, ptr [[KERNEL_ARGS]]) 1983 // CHECK3-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 1984 // CHECK3-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1985 // CHECK3: omp_offload.failed: 1986 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP11]], i32 [[TMP13]], i32 [[TMP15]]) #[[ATTR4]] 1987 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1988 // CHECK3: omp_offload.cont: 1989 // CHECK3-NEXT: [[TMP38:%.*]] = load i32, ptr [[A]], align 4 1990 // CHECK3-NEXT: store i32 [[TMP38]], ptr [[A_CASTED3]], align 4 1991 // CHECK3-NEXT: [[TMP39:%.*]] = load i32, ptr [[A_CASTED3]], align 4 1992 // CHECK3-NEXT: [[TMP40:%.*]] = load i16, ptr [[AA]], align 2 1993 // CHECK3-NEXT: store i16 [[TMP40]], ptr [[AA_CASTED4]], align 2 1994 // CHECK3-NEXT: [[TMP41:%.*]] = load i32, ptr [[AA_CASTED4]], align 4 1995 // CHECK3-NEXT: [[TMP42:%.*]] = load i32, ptr [[N_ADDR]], align 4 1996 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP42]], 10 1997 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1998 // CHECK3: omp_if.then: 1999 // CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 2000 // CHECK3-NEXT: store i32 [[TMP39]], ptr [[TMP43]], align 4 2001 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 2002 // CHECK3-NEXT: store i32 [[TMP39]], ptr [[TMP44]], align 4 2003 // CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 2004 // CHECK3-NEXT: store ptr null, ptr [[TMP45]], align 4 2005 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 2006 // CHECK3-NEXT: store i32 [[TMP41]], ptr [[TMP46]], align 4 2007 // CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 2008 // CHECK3-NEXT: store i32 [[TMP41]], ptr [[TMP47]], align 4 2009 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 2010 // CHECK3-NEXT: store ptr null, ptr [[TMP48]], align 4 2011 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 2012 // CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 2013 // CHECK3-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 2014 // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0 2015 // CHECK3-NEXT: store i32 1, ptr [[TMP51]], align 4 2016 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1 2017 // CHECK3-NEXT: store i32 2, ptr [[TMP52]], align 4 2018 // CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2 2019 // CHECK3-NEXT: store ptr [[TMP49]], ptr [[TMP53]], align 4 2020 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3 2021 // CHECK3-NEXT: store ptr [[TMP50]], ptr [[TMP54]], align 4 2022 // CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4 2023 // CHECK3-NEXT: store ptr @.offload_sizes.5, ptr [[TMP55]], align 4 2024 // CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5 2025 // CHECK3-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP56]], align 4 2026 // CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6 2027 // CHECK3-NEXT: store ptr null, ptr [[TMP57]], align 4 2028 // CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7 2029 // CHECK3-NEXT: store ptr null, ptr [[TMP58]], align 4 2030 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8 2031 // CHECK3-NEXT: store i64 0, ptr [[TMP59]], align 8 2032 // CHECK3-NEXT: [[TMP60:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, ptr [[KERNEL_ARGS8]]) 2033 // CHECK3-NEXT: [[TMP61:%.*]] = icmp ne i32 [[TMP60]], 0 2034 // CHECK3-NEXT: br i1 [[TMP61]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 2035 // CHECK3: omp_offload.failed9: 2036 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP39]], i32 [[TMP41]]) #[[ATTR4]] 2037 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT10]] 2038 // CHECK3: omp_offload.cont10: 2039 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2040 // CHECK3: omp_if.else: 2041 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP39]], i32 [[TMP41]]) #[[ATTR4]] 2042 // CHECK3-NEXT: br label [[OMP_IF_END]] 2043 // CHECK3: omp_if.end: 2044 // CHECK3-NEXT: [[TMP62:%.*]] = load i32, ptr [[A]], align 4 2045 // CHECK3-NEXT: store i32 [[TMP62]], ptr [[DOTCAPTURE_EXPR_]], align 4 2046 // CHECK3-NEXT: [[TMP63:%.*]] = load i32, ptr [[A]], align 4 2047 // CHECK3-NEXT: store i32 [[TMP63]], ptr [[A_CASTED11]], align 4 2048 // CHECK3-NEXT: [[TMP64:%.*]] = load i32, ptr [[A_CASTED11]], align 4 2049 // CHECK3-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 2050 // CHECK3-NEXT: store i32 [[TMP65]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 2051 // CHECK3-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 2052 // CHECK3-NEXT: [[TMP67:%.*]] = load i32, ptr [[N_ADDR]], align 4 2053 // CHECK3-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP67]], 20 2054 // CHECK3-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]] 2055 // CHECK3: omp_if.then13: 2056 // CHECK3-NEXT: [[TMP68:%.*]] = mul nuw i32 [[TMP1]], 4 2057 // CHECK3-NEXT: [[TMP69:%.*]] = sext i32 [[TMP68]] to i64 2058 // CHECK3-NEXT: [[TMP70:%.*]] = mul nuw i32 5, [[TMP3]] 2059 // CHECK3-NEXT: [[TMP71:%.*]] = mul nuw i32 [[TMP70]], 8 2060 // CHECK3-NEXT: [[TMP72:%.*]] = sext i32 [[TMP71]] to i64 2061 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.8, i32 80, i1 false) 2062 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 2063 // CHECK3-NEXT: store i32 [[TMP64]], ptr [[TMP73]], align 4 2064 // CHECK3-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 2065 // CHECK3-NEXT: store i32 [[TMP64]], ptr [[TMP74]], align 4 2066 // CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 2067 // CHECK3-NEXT: store ptr null, ptr [[TMP75]], align 4 2068 // CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 2069 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP76]], align 4 2070 // CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 2071 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP77]], align 4 2072 // CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 2073 // CHECK3-NEXT: store ptr null, ptr [[TMP78]], align 4 2074 // CHECK3-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 2075 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP79]], align 4 2076 // CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 2077 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP80]], align 4 2078 // CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 2079 // CHECK3-NEXT: store ptr null, ptr [[TMP81]], align 4 2080 // CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 2081 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP82]], align 4 2082 // CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 2083 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP83]], align 4 2084 // CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 2085 // CHECK3-NEXT: store i64 [[TMP69]], ptr [[TMP84]], align 4 2086 // CHECK3-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 2087 // CHECK3-NEXT: store ptr null, ptr [[TMP85]], align 4 2088 // CHECK3-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 2089 // CHECK3-NEXT: store ptr [[C]], ptr [[TMP86]], align 4 2090 // CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 2091 // CHECK3-NEXT: store ptr [[C]], ptr [[TMP87]], align 4 2092 // CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 2093 // CHECK3-NEXT: store ptr null, ptr [[TMP88]], align 4 2094 // CHECK3-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 2095 // CHECK3-NEXT: store i32 5, ptr [[TMP89]], align 4 2096 // CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 2097 // CHECK3-NEXT: store i32 5, ptr [[TMP90]], align 4 2098 // CHECK3-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 2099 // CHECK3-NEXT: store ptr null, ptr [[TMP91]], align 4 2100 // CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 2101 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP92]], align 4 2102 // CHECK3-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 2103 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP93]], align 4 2104 // CHECK3-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 2105 // CHECK3-NEXT: store ptr null, ptr [[TMP94]], align 4 2106 // CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 2107 // CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP95]], align 4 2108 // CHECK3-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 2109 // CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP96]], align 4 2110 // CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 2111 // CHECK3-NEXT: store i64 [[TMP72]], ptr [[TMP97]], align 4 2112 // CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 2113 // CHECK3-NEXT: store ptr null, ptr [[TMP98]], align 4 2114 // CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 2115 // CHECK3-NEXT: store ptr [[D]], ptr [[TMP99]], align 4 2116 // CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 2117 // CHECK3-NEXT: store ptr [[D]], ptr [[TMP100]], align 4 2118 // CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 2119 // CHECK3-NEXT: store ptr null, ptr [[TMP101]], align 4 2120 // CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 2121 // CHECK3-NEXT: store i32 [[TMP66]], ptr [[TMP102]], align 4 2122 // CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 2123 // CHECK3-NEXT: store i32 [[TMP66]], ptr [[TMP103]], align 4 2124 // CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 2125 // CHECK3-NEXT: store ptr null, ptr [[TMP104]], align 4 2126 // CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 2127 // CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 2128 // CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2129 // CHECK3-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 2130 // CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0 2131 // CHECK3-NEXT: store i32 1, ptr [[TMP108]], align 4 2132 // CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1 2133 // CHECK3-NEXT: store i32 10, ptr [[TMP109]], align 4 2134 // CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2 2135 // CHECK3-NEXT: store ptr [[TMP105]], ptr [[TMP110]], align 4 2136 // CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3 2137 // CHECK3-NEXT: store ptr [[TMP106]], ptr [[TMP111]], align 4 2138 // CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4 2139 // CHECK3-NEXT: store ptr [[TMP107]], ptr [[TMP112]], align 4 2140 // CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5 2141 // CHECK3-NEXT: store ptr @.offload_maptypes.9, ptr [[TMP113]], align 4 2142 // CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6 2143 // CHECK3-NEXT: store ptr null, ptr [[TMP114]], align 4 2144 // CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7 2145 // CHECK3-NEXT: store ptr null, ptr [[TMP115]], align 4 2146 // CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8 2147 // CHECK3-NEXT: store i64 0, ptr [[TMP116]], align 8 2148 // CHECK3-NEXT: [[TMP117:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, ptr [[KERNEL_ARGS17]]) 2149 // CHECK3-NEXT: [[TMP118:%.*]] = icmp ne i32 [[TMP117]], 0 2150 // CHECK3-NEXT: br i1 [[TMP118]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] 2151 // CHECK3: omp_offload.failed18: 2152 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP64]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP66]]) #[[ATTR4]] 2153 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT19]] 2154 // CHECK3: omp_offload.cont19: 2155 // CHECK3-NEXT: br label [[OMP_IF_END21:%.*]] 2156 // CHECK3: omp_if.else20: 2157 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP64]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP66]]) #[[ATTR4]] 2158 // CHECK3-NEXT: br label [[OMP_IF_END21]] 2159 // CHECK3: omp_if.end21: 2160 // CHECK3-NEXT: [[TMP119:%.*]] = load i32, ptr [[A]], align 4 2161 // CHECK3-NEXT: [[TMP120:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 2162 // CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP120]]) 2163 // CHECK3-NEXT: ret i32 [[TMP119]] 2164 // 2165 // 2166 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 2167 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] { 2168 // CHECK3-NEXT: entry: 2169 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @.omp_outlined.) 2170 // CHECK3-NEXT: ret void 2171 // 2172 // 2173 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 2174 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 2175 // CHECK3-NEXT: entry: 2176 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2177 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2178 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2179 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2180 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2181 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2182 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2183 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2184 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2185 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2186 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2187 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2188 // CHECK3-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 2189 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2190 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2191 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2192 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2193 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2194 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2195 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 2196 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2197 // CHECK3: cond.true: 2198 // CHECK3-NEXT: br label [[COND_END:%.*]] 2199 // CHECK3: cond.false: 2200 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2201 // CHECK3-NEXT: br label [[COND_END]] 2202 // CHECK3: cond.end: 2203 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2204 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2205 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2206 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2207 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2208 // CHECK3: omp.inner.for.cond: 2209 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 2210 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 2211 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2212 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2213 // CHECK3: omp.inner.for.body: 2214 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 2215 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 2216 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 2217 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 2218 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2219 // CHECK3: omp.body.continue: 2220 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2221 // CHECK3: omp.inner.for.inc: 2222 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 2223 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 2224 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 2225 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 2226 // CHECK3: omp.inner.for.end: 2227 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2228 // CHECK3: omp.loop.exit: 2229 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2230 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2231 // CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 2232 // CHECK3-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2233 // CHECK3: .omp.final.then: 2234 // CHECK3-NEXT: store i32 33, ptr [[I]], align 4 2235 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2236 // CHECK3: .omp.final.done: 2237 // CHECK3-NEXT: ret void 2238 // 2239 // 2240 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 2241 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 2242 // CHECK3-NEXT: entry: 2243 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 2244 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4 2245 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4 2246 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4 2247 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4 2248 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4 2249 // CHECK3-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2250 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 2251 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 2252 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 2253 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 2254 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 2255 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 2256 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 2257 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 2258 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 2259 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 2260 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 2261 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 2262 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 2263 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) 2264 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 2265 // CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias !26 2266 // CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26 2267 // CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26 2268 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias !26 2269 // CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !26 2270 // CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !26 2271 // CHECK3-NEXT: store i32 1, ptr [[KERNEL_ARGS_I]], align 4, !noalias !26 2272 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 2273 // CHECK3-NEXT: store i32 0, ptr [[TMP9]], align 4, !noalias !26 2274 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 2275 // CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 4, !noalias !26 2276 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 2277 // CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4, !noalias !26 2278 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 2279 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4, !noalias !26 2280 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 2281 // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4, !noalias !26 2282 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 2283 // CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4, !noalias !26 2284 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 2285 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4, !noalias !26 2286 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 2287 // CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8, !noalias !26 2288 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__tgt_target_kernel_nowait(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, ptr [[KERNEL_ARGS_I]], i32 0, ptr null, i32 0, ptr null) 2289 // CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 2290 // CHECK3-NEXT: br i1 [[TMP18]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 2291 // CHECK3: omp_offload.failed.i: 2292 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] 2293 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 2294 // CHECK3: .omp_outlined..1.exit: 2295 // CHECK3-NEXT: ret i32 0 2296 // 2297 // 2298 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 2299 // CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 2300 // CHECK3-NEXT: entry: 2301 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2302 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4 2303 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2304 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2305 // CHECK3-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4 2306 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4 2307 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 2308 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 2309 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 2310 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..2, i32 [[TMP2]], ptr [[TMP0]]) 2311 // CHECK3-NEXT: ret void 2312 // 2313 // 2314 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 2315 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 2316 // CHECK3-NEXT: entry: 2317 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2318 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2319 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2320 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4 2321 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2322 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2323 // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 2324 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2325 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2326 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2327 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2328 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2329 // CHECK3-NEXT: [[K1:%.*]] = alloca i64, align 8 2330 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2331 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2332 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2333 // CHECK3-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4 2334 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4 2335 // CHECK3-NEXT: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 8 2336 // CHECK3-NEXT: store i64 [[TMP1]], ptr [[DOTLINEAR_START]], align 8 2337 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2338 // CHECK3-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 4 2339 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2340 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2341 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2342 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 2343 // CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 2344 // CHECK3-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1) 2345 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2346 // CHECK3: omp.dispatch.cond: 2347 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]) 2348 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 2349 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2350 // CHECK3: omp.dispatch.body: 2351 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2352 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 2353 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2354 // CHECK3: omp.inner.for.cond: 2355 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] 2356 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] 2357 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 2358 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2359 // CHECK3: omp.inner.for.body: 2360 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 2361 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 2362 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 2363 // CHECK3-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] 2364 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP27]] 2365 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 2366 // CHECK3-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 2367 // CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 2368 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 2369 // CHECK3-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP27]] 2370 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 2371 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 2372 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 2373 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2374 // CHECK3: omp.body.continue: 2375 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2376 // CHECK3: omp.inner.for.inc: 2377 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 2378 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 2379 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 2380 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 2381 // CHECK3: omp.inner.for.end: 2382 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2383 // CHECK3: omp.dispatch.inc: 2384 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2385 // CHECK3: omp.dispatch.end: 2386 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2387 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 2388 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2389 // CHECK3: .omp.final.then: 2390 // CHECK3-NEXT: store i32 1, ptr [[I]], align 4 2391 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2392 // CHECK3: .omp.final.done: 2393 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2394 // CHECK3-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 2395 // CHECK3-NEXT: br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 2396 // CHECK3: .omp.linear.pu: 2397 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, ptr [[K1]], align 8 2398 // CHECK3-NEXT: store i64 [[TMP17]], ptr [[TMP0]], align 8 2399 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 2400 // CHECK3: .omp.linear.pu.done: 2401 // CHECK3-NEXT: ret void 2402 // 2403 // 2404 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 2405 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 2406 // CHECK3-NEXT: entry: 2407 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2408 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 2409 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2410 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2411 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 2412 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2413 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2414 // CHECK3-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 2415 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2416 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2417 // CHECK3-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 2418 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 2419 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 2420 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 2421 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 2422 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 2423 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 2424 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4 2425 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..3, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 2426 // CHECK3-NEXT: ret void 2427 // 2428 // 2429 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 2430 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 2431 // CHECK3-NEXT: entry: 2432 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2433 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2434 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2435 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 2436 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2437 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2438 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 2439 // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 2440 // CHECK3-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 2441 // CHECK3-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 2442 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2443 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2444 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2445 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2446 // CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8 2447 // CHECK3-NEXT: [[LIN2:%.*]] = alloca i32, align 4 2448 // CHECK3-NEXT: [[A3:%.*]] = alloca i32, align 4 2449 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2450 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2451 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2452 // CHECK3-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 2453 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2454 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 2455 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 2456 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 2457 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 2458 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 2459 // CHECK3-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 2460 // CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 2461 // CHECK3-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 2462 // CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 2463 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2464 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2465 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 2466 // CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]]) 2467 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 2468 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 2469 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 2470 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2471 // CHECK3: cond.true: 2472 // CHECK3-NEXT: br label [[COND_END:%.*]] 2473 // CHECK3: cond.false: 2474 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 2475 // CHECK3-NEXT: br label [[COND_END]] 2476 // CHECK3: cond.end: 2477 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2478 // CHECK3-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 2479 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 2480 // CHECK3-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 2481 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2482 // CHECK3: omp.inner.for.cond: 2483 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30:![0-9]+]] 2484 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP30]] 2485 // CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 2486 // CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2487 // CHECK3: omp.inner.for.body: 2488 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2489 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 2490 // CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 2491 // CHECK3-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP30]] 2492 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP30]] 2493 // CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 2494 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2495 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]] 2496 // CHECK3-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 2497 // CHECK3-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 2498 // CHECK3-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 2499 // CHECK3-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP30]] 2500 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP30]] 2501 // CHECK3-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 2502 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2503 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]] 2504 // CHECK3-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 2505 // CHECK3-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 2506 // CHECK3-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 2507 // CHECK3-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP30]] 2508 // CHECK3-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] 2509 // CHECK3-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 2510 // CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 2511 // CHECK3-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 2512 // CHECK3-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] 2513 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2514 // CHECK3: omp.body.continue: 2515 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2516 // CHECK3: omp.inner.for.inc: 2517 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2518 // CHECK3-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 2519 // CHECK3-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2520 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 2521 // CHECK3: omp.inner.for.end: 2522 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2523 // CHECK3: omp.loop.exit: 2524 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 2525 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2526 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 2527 // CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2528 // CHECK3: .omp.final.then: 2529 // CHECK3-NEXT: store i64 400, ptr [[IT]], align 8 2530 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2531 // CHECK3: .omp.final.done: 2532 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2533 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 2534 // CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 2535 // CHECK3: .omp.linear.pu: 2536 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 2537 // CHECK3-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 2538 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 2539 // CHECK3-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 2540 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 2541 // CHECK3: .omp.linear.pu.done: 2542 // CHECK3-NEXT: ret void 2543 // 2544 // 2545 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 2546 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2547 // CHECK3-NEXT: entry: 2548 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2549 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2550 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2551 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2552 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2553 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2554 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2555 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 2556 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 2557 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2558 // CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 2559 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 2560 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..4, i32 [[TMP1]], i32 [[TMP3]]) 2561 // CHECK3-NEXT: ret void 2562 // 2563 // 2564 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 2565 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 2566 // CHECK3-NEXT: entry: 2567 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2568 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2569 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2570 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2571 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2572 // CHECK3-NEXT: [[TMP:%.*]] = alloca i16, align 2 2573 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2574 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2575 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2576 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2577 // CHECK3-NEXT: [[IT:%.*]] = alloca i16, align 2 2578 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2579 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2580 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2581 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2582 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2583 // CHECK3-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 2584 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2585 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2586 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2587 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2588 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2589 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2590 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 2591 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2592 // CHECK3: cond.true: 2593 // CHECK3-NEXT: br label [[COND_END:%.*]] 2594 // CHECK3: cond.false: 2595 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2596 // CHECK3-NEXT: br label [[COND_END]] 2597 // CHECK3: cond.end: 2598 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2599 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2600 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2601 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2602 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2603 // CHECK3: omp.inner.for.cond: 2604 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] 2605 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] 2606 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2607 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2608 // CHECK3: omp.inner.for.body: 2609 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 2610 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 2611 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 2612 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 2613 // CHECK3-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP33]] 2614 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 2615 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 2616 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 2617 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] 2618 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 2619 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 2620 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 2621 // CHECK3-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] 2622 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2623 // CHECK3: omp.body.continue: 2624 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2625 // CHECK3: omp.inner.for.inc: 2626 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 2627 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 2628 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 2629 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 2630 // CHECK3: omp.inner.for.end: 2631 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2632 // CHECK3: omp.loop.exit: 2633 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2634 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2635 // CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 2636 // CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2637 // CHECK3: .omp.final.then: 2638 // CHECK3-NEXT: store i16 22, ptr [[IT]], align 2 2639 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2640 // CHECK3: .omp.final.done: 2641 // CHECK3-NEXT: ret void 2642 // 2643 // 2644 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 2645 // CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 2646 // CHECK3-NEXT: entry: 2647 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2648 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 2649 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2650 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 2651 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 2652 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2653 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2654 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 2655 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 2656 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2657 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2658 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 2659 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2660 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 2661 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 2662 // CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 2663 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 2664 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 2665 // CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 2666 // CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 2667 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 2668 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2669 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 2670 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 2671 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 2672 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 2673 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 2674 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 2675 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 2676 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 2677 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 2678 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 2679 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 2680 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2681 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 2682 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 2683 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @.omp_outlined..7, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]]) 2684 // CHECK3-NEXT: ret void 2685 // 2686 // 2687 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 2688 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 2689 // CHECK3-NEXT: entry: 2690 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2691 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2692 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2693 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 2694 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2695 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 2696 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 2697 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2698 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2699 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 2700 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 2701 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2702 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2703 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 2704 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2705 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2706 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2707 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2708 // CHECK3-NEXT: [[IT:%.*]] = alloca i8, align 1 2709 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2710 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2711 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2712 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 2713 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 2714 // CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 2715 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 2716 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 2717 // CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 2718 // CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 2719 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 2720 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2721 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 2722 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 2723 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 2724 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 2725 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 2726 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 2727 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 2728 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 2729 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2730 // CHECK3-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 2731 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2732 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2733 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2734 // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2735 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 2736 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 2737 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2738 // CHECK3: omp.dispatch.cond: 2739 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2740 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 2741 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2742 // CHECK3: cond.true: 2743 // CHECK3-NEXT: br label [[COND_END:%.*]] 2744 // CHECK3: cond.false: 2745 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2746 // CHECK3-NEXT: br label [[COND_END]] 2747 // CHECK3: cond.end: 2748 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 2749 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2750 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2751 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 2752 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2753 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2754 // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 2755 // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2756 // CHECK3: omp.dispatch.body: 2757 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2758 // CHECK3: omp.inner.for.cond: 2759 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] 2760 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]] 2761 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 2762 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2763 // CHECK3: omp.inner.for.body: 2764 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 2765 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 2766 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 2767 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 2768 // CHECK3-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP36]] 2769 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] 2770 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 2771 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] 2772 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 2773 // CHECK3-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] 2774 // CHECK3-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 2775 // CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 2776 // CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 2777 // CHECK3-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] 2778 // CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 2779 // CHECK3-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]] 2780 // CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 2781 // CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 2782 // CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 2783 // CHECK3-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]] 2784 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 2785 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 2786 // CHECK3-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] 2787 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 2788 // CHECK3-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] 2789 // CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 2790 // CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]] 2791 // CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3 2792 // CHECK3-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]] 2793 // CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 2794 // CHECK3-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]] 2795 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 2796 // CHECK3-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]] 2797 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 2798 // CHECK3-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]] 2799 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 2800 // CHECK3-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]] 2801 // CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 2802 // CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 2803 // CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 2804 // CHECK3-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]] 2805 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2806 // CHECK3: omp.body.continue: 2807 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2808 // CHECK3: omp.inner.for.inc: 2809 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 2810 // CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 2811 // CHECK3-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 2812 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] 2813 // CHECK3: omp.inner.for.end: 2814 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2815 // CHECK3: omp.dispatch.inc: 2816 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2817 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2818 // CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 2819 // CHECK3-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 2820 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2821 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2822 // CHECK3-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 2823 // CHECK3-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 2824 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2825 // CHECK3: omp.dispatch.end: 2826 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 2827 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2828 // CHECK3-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 2829 // CHECK3-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2830 // CHECK3: .omp.final.then: 2831 // CHECK3-NEXT: store i8 96, ptr [[IT]], align 1 2832 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2833 // CHECK3: .omp.final.done: 2834 // CHECK3-NEXT: ret void 2835 // 2836 // 2837 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 2838 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 2839 // CHECK3-NEXT: entry: 2840 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2841 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2842 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 2843 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2844 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 2845 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 2846 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 2847 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 2848 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2849 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A]], align 4 2850 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 2851 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 2852 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 2853 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2854 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 2855 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 2856 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 2857 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 2858 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2859 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 2860 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 2861 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 2862 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 2863 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 2864 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 2865 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 2866 // CHECK3-NEXT: ret i32 [[TMP8]] 2867 // 2868 // 2869 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2870 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2871 // CHECK3-NEXT: entry: 2872 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2873 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2874 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 2875 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 2876 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2877 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2878 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 2879 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 2880 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 2881 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 2882 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2883 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2884 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2885 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 2886 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2887 // CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4 2888 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 2889 // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() 2890 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 2891 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 2892 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 2893 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 2894 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 2895 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 2896 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 2897 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 2898 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 2899 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2900 // CHECK3: omp_if.then: 2901 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 2902 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 2903 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 2904 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 2905 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.11, i32 40, i1 false) 2906 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2907 // CHECK3-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 4 2908 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2909 // CHECK3-NEXT: store ptr [[A]], ptr [[TMP11]], align 4 2910 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2911 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 2912 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2913 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 4 2914 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2915 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 4 2916 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2917 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 2918 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2919 // CHECK3-NEXT: store i32 2, ptr [[TMP16]], align 4 2920 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2921 // CHECK3-NEXT: store i32 2, ptr [[TMP17]], align 4 2922 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2923 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 2924 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2925 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP19]], align 4 2926 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2927 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP20]], align 4 2928 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2929 // CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 4 2930 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2931 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 4 2932 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2933 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 4 2934 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 2935 // CHECK3-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 4 2936 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2937 // CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4 2938 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2939 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2940 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2941 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2942 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2943 // CHECK3-NEXT: store i32 1, ptr [[TMP29]], align 4 2944 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2945 // CHECK3-NEXT: store i32 5, ptr [[TMP30]], align 4 2946 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2947 // CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 4 2948 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2949 // CHECK3-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 4 2950 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2951 // CHECK3-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 4 2952 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2953 // CHECK3-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP34]], align 4 2954 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 2955 // CHECK3-NEXT: store ptr null, ptr [[TMP35]], align 4 2956 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 2957 // CHECK3-NEXT: store ptr null, ptr [[TMP36]], align 4 2958 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 2959 // CHECK3-NEXT: store i64 0, ptr [[TMP37]], align 8 2960 // CHECK3-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, ptr [[KERNEL_ARGS]]) 2961 // CHECK3-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 2962 // CHECK3-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2963 // CHECK3: omp_offload.failed: 2964 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4]] 2965 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2966 // CHECK3: omp_offload.cont: 2967 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2968 // CHECK3: omp_if.else: 2969 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4]] 2970 // CHECK3-NEXT: br label [[OMP_IF_END]] 2971 // CHECK3: omp_if.end: 2972 // CHECK3-NEXT: [[TMP40:%.*]] = mul nsw i32 1, [[TMP1]] 2973 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP40]] 2974 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 2975 // CHECK3-NEXT: [[TMP41:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 2976 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP41]] to i32 2977 // CHECK3-NEXT: [[TMP42:%.*]] = load i32, ptr [[B]], align 4 2978 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP42]] 2979 // CHECK3-NEXT: [[TMP43:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 2980 // CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP43]]) 2981 // CHECK3-NEXT: ret i32 [[ADD3]] 2982 // 2983 // 2984 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 2985 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 2986 // CHECK3-NEXT: entry: 2987 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2988 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2989 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 2990 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 2991 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 2992 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2993 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2994 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 2995 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 2996 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 2997 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 2998 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2999 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 3000 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 3001 // CHECK3-NEXT: store i8 0, ptr [[AAA]], align 1 3002 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 3003 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 3004 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 3005 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 3006 // CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 3007 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3008 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1 3009 // CHECK3-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1 3010 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 3011 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 3012 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 3013 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3014 // CHECK3: omp_if.then: 3015 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3016 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 4 3017 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3018 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 4 3019 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3020 // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 3021 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3022 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP10]], align 4 3023 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3024 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP11]], align 4 3025 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3026 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 3027 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3028 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 4 3029 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3030 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 4 3031 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3032 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 3033 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3034 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP16]], align 4 3035 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3036 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP17]], align 4 3037 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3038 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 3039 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3040 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3041 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3042 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3043 // CHECK3-NEXT: store i32 1, ptr [[TMP21]], align 4 3044 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3045 // CHECK3-NEXT: store i32 4, ptr [[TMP22]], align 4 3046 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3047 // CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4 3048 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3049 // CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4 3050 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3051 // CHECK3-NEXT: store ptr @.offload_sizes.14, ptr [[TMP25]], align 4 3052 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3053 // CHECK3-NEXT: store ptr @.offload_maptypes.15, ptr [[TMP26]], align 4 3054 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3055 // CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 4 3056 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3057 // CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 4 3058 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3059 // CHECK3-NEXT: store i64 0, ptr [[TMP29]], align 8 3060 // CHECK3-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, ptr [[KERNEL_ARGS]]) 3061 // CHECK3-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 3062 // CHECK3-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3063 // CHECK3: omp_offload.failed: 3064 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]] 3065 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3066 // CHECK3: omp_offload.cont: 3067 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3068 // CHECK3: omp_if.else: 3069 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]] 3070 // CHECK3-NEXT: br label [[OMP_IF_END]] 3071 // CHECK3: omp_if.end: 3072 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, ptr [[A]], align 4 3073 // CHECK3-NEXT: ret i32 [[TMP32]] 3074 // 3075 // 3076 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3077 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 3078 // CHECK3-NEXT: entry: 3079 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3080 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3081 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3082 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3083 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3084 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3085 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 3086 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 3087 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 3088 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 3089 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 3090 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 3091 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 3092 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 3093 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 3094 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 3095 // CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 3096 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3097 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 3098 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 3099 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3100 // CHECK3: omp_if.then: 3101 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3102 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 3103 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3104 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 4 3105 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3106 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 3107 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3108 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 4 3109 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3110 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP9]], align 4 3111 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3112 // CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 4 3113 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3114 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP11]], align 4 3115 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3116 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP12]], align 4 3117 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3118 // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4 3119 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3120 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3121 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3122 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3123 // CHECK3-NEXT: store i32 1, ptr [[TMP16]], align 4 3124 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3125 // CHECK3-NEXT: store i32 3, ptr [[TMP17]], align 4 3126 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3127 // CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4 3128 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3129 // CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 4 3130 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3131 // CHECK3-NEXT: store ptr @.offload_sizes.17, ptr [[TMP20]], align 4 3132 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3133 // CHECK3-NEXT: store ptr @.offload_maptypes.18, ptr [[TMP21]], align 4 3134 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3135 // CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 4 3136 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3137 // CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 4 3138 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3139 // CHECK3-NEXT: store i64 0, ptr [[TMP24]], align 8 3140 // CHECK3-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, ptr [[KERNEL_ARGS]]) 3141 // CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 3142 // CHECK3-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3143 // CHECK3: omp_offload.failed: 3144 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] 3145 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3146 // CHECK3: omp_offload.cont: 3147 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3148 // CHECK3: omp_if.else: 3149 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] 3150 // CHECK3-NEXT: br label [[OMP_IF_END]] 3151 // CHECK3: omp_if.end: 3152 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[A]], align 4 3153 // CHECK3-NEXT: ret i32 [[TMP27]] 3154 // 3155 // 3156 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 3157 // CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3158 // CHECK3-NEXT: entry: 3159 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3160 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3161 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3162 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3163 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3164 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3165 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3166 // CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 3167 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 3168 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 3169 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3170 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3171 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 3172 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 3173 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 3174 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 3175 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 3176 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 3177 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @.omp_outlined..10, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]]) 3178 // CHECK3-NEXT: ret void 3179 // 3180 // 3181 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 3182 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 3183 // CHECK3-NEXT: entry: 3184 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3185 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3186 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3187 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3188 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3189 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3190 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3191 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3192 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 3193 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3194 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3195 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3196 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3197 // CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8 3198 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3199 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3200 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3201 // CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 3202 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 3203 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 3204 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3205 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3206 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 3207 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 3208 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 3209 // CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 3210 // CHECK3-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 3211 // CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 3212 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3213 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3214 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 3215 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 3216 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 3217 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 3218 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3219 // CHECK3: cond.true: 3220 // CHECK3-NEXT: br label [[COND_END:%.*]] 3221 // CHECK3: cond.false: 3222 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 3223 // CHECK3-NEXT: br label [[COND_END]] 3224 // CHECK3: cond.end: 3225 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3226 // CHECK3-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 3227 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 3228 // CHECK3-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8 3229 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3230 // CHECK3: omp.inner.for.cond: 3231 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39:![0-9]+]] 3232 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP39]] 3233 // CHECK3-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 3234 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3235 // CHECK3: omp.inner.for.body: 3236 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 3237 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 3238 // CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 3239 // CHECK3-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP39]] 3240 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]] 3241 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 3242 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3243 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 3244 // CHECK3-NEXT: store double [[ADD]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP39]] 3245 // CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 3246 // CHECK3-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP39]] 3247 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 3248 // CHECK3-NEXT: store double [[INC]], ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP39]] 3249 // CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 3250 // CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 3251 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]] 3252 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 3253 // CHECK3-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP39]] 3254 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3255 // CHECK3: omp.body.continue: 3256 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3257 // CHECK3: omp.inner.for.inc: 3258 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 3259 // CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 3260 // CHECK3-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 3261 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] 3262 // CHECK3: omp.inner.for.end: 3263 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3264 // CHECK3: omp.loop.exit: 3265 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 3266 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3267 // CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 3268 // CHECK3-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3269 // CHECK3: .omp.final.then: 3270 // CHECK3-NEXT: store i64 400, ptr [[IT]], align 8 3271 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 3272 // CHECK3: .omp.final.done: 3273 // CHECK3-NEXT: ret void 3274 // 3275 // 3276 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 3277 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3278 // CHECK3-NEXT: entry: 3279 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3280 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3281 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3282 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3283 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3284 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3285 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3286 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3287 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3288 // CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 3289 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3290 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3291 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 3292 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 3293 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 3294 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3295 // CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 3296 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3297 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 3298 // CHECK3-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 3299 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 3300 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @.omp_outlined..13, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]]) 3301 // CHECK3-NEXT: ret void 3302 // 3303 // 3304 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 3305 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3306 // CHECK3-NEXT: entry: 3307 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3308 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3309 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3310 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3311 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3312 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3313 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3314 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3315 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3316 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3317 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3318 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3319 // CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 3320 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3321 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3322 // CHECK3-NEXT: ret void 3323 // 3324 // 3325 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 3326 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3327 // CHECK3-NEXT: entry: 3328 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3329 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3330 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3331 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3332 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3333 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3334 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3335 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3336 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3337 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 3338 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 3339 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 3340 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3341 // CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 3342 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3343 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..16, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) 3344 // CHECK3-NEXT: ret void 3345 // 3346 // 3347 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 3348 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3349 // CHECK3-NEXT: entry: 3350 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3351 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3352 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3353 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3354 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3355 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3356 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 3357 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3358 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3359 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3360 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3361 // CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 3362 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3363 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3364 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3365 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3366 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3367 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3368 // CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 3369 // CHECK3-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 3370 // CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 3371 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3372 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3373 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 3374 // CHECK3-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 3375 // CHECK3-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 3376 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 3377 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3378 // CHECK3: cond.true: 3379 // CHECK3-NEXT: br label [[COND_END:%.*]] 3380 // CHECK3: cond.false: 3381 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 3382 // CHECK3-NEXT: br label [[COND_END]] 3383 // CHECK3: cond.end: 3384 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 3385 // CHECK3-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 3386 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 3387 // CHECK3-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 3388 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3389 // CHECK3: omp.inner.for.cond: 3390 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42:![0-9]+]] 3391 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP42]] 3392 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 3393 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3394 // CHECK3: omp.inner.for.body: 3395 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42]] 3396 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 3397 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 3398 // CHECK3-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP42]] 3399 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]] 3400 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 3401 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]] 3402 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]] 3403 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 3404 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 3405 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 3406 // CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]] 3407 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 3408 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]] 3409 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 3410 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]] 3411 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3412 // CHECK3: omp.body.continue: 3413 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3414 // CHECK3: omp.inner.for.inc: 3415 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42]] 3416 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 3417 // CHECK3-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42]] 3418 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] 3419 // CHECK3: omp.inner.for.end: 3420 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3421 // CHECK3: omp.loop.exit: 3422 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 3423 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3424 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 3425 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3426 // CHECK3: .omp.final.then: 3427 // CHECK3-NEXT: store i64 11, ptr [[I]], align 8 3428 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 3429 // CHECK3: .omp.final.done: 3430 // CHECK3-NEXT: ret void 3431 // 3432 // 3433 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3434 // CHECK3-SAME: () #[[ATTR8:[0-9]+]] { 3435 // CHECK3-NEXT: entry: 3436 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 3437 // CHECK3-NEXT: ret void 3438 // 3439 // 3440 // CHECK5-LABEL: define {{[^@]+}}@_Z7get_valv 3441 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 3442 // CHECK5-NEXT: entry: 3443 // CHECK5-NEXT: ret i64 0 3444 // 3445 // 3446 // CHECK5-LABEL: define {{[^@]+}}@_Z3fooi 3447 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 3448 // CHECK5-NEXT: entry: 3449 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3450 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 3451 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 3452 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x float], align 4 3453 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 3454 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3455 // CHECK5-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 3456 // CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 3457 // CHECK5-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 3458 // CHECK5-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 3459 // CHECK5-NEXT: [[K:%.*]] = alloca i64, align 8 3460 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3461 // CHECK5-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 3462 // CHECK5-NEXT: [[LIN:%.*]] = alloca i32, align 4 3463 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3464 // CHECK5-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 3465 // CHECK5-NEXT: [[A_CASTED2:%.*]] = alloca i64, align 8 3466 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 3467 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 3468 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 3469 // CHECK5-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 3470 // CHECK5-NEXT: [[AA_CASTED4:%.*]] = alloca i64, align 8 3471 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 8 3472 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 8 3473 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 8 3474 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3475 // CHECK5-NEXT: [[A_CASTED11:%.*]] = alloca i64, align 8 3476 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 3477 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 8 3478 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 8 3479 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 8 3480 // CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 3481 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 3482 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 3483 // CHECK5-NEXT: store i32 0, ptr [[A]], align 4 3484 // CHECK5-NEXT: store i16 0, ptr [[AA]], align 2 3485 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 3486 // CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 3487 // CHECK5-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() 3488 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 3489 // CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 3490 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 3491 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 3492 // CHECK5-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 3493 // CHECK5-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 3494 // CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 3495 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 3496 // CHECK5-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, ptr @.omp_task_entry., i64 -1) 3497 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP7]], i32 0, i32 0 3498 // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP7]]) 3499 // CHECK5-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 3500 // CHECK5-NEXT: store i64 [[CALL]], ptr [[K]], align 8 3501 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4 3502 // CHECK5-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4 3503 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8 3504 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[K]], align 8 3505 // CHECK5-NEXT: store i64 [[TMP12]], ptr [[K_CASTED]], align 8 3506 // CHECK5-NEXT: [[TMP13:%.*]] = load i64, ptr [[K_CASTED]], align 8 3507 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR4:[0-9]+]] 3508 // CHECK5-NEXT: store i32 12, ptr [[LIN]], align 4 3509 // CHECK5-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2 3510 // CHECK5-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2 3511 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[AA_CASTED]], align 8 3512 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[LIN]], align 4 3513 // CHECK5-NEXT: store i32 [[TMP16]], ptr [[LIN_CASTED]], align 4 3514 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 3515 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[A]], align 4 3516 // CHECK5-NEXT: store i32 [[TMP18]], ptr [[A_CASTED2]], align 4 3517 // CHECK5-NEXT: [[TMP19:%.*]] = load i64, ptr [[A_CASTED2]], align 8 3518 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3519 // CHECK5-NEXT: store i64 [[TMP15]], ptr [[TMP20]], align 8 3520 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3521 // CHECK5-NEXT: store i64 [[TMP15]], ptr [[TMP21]], align 8 3522 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3523 // CHECK5-NEXT: store ptr null, ptr [[TMP22]], align 8 3524 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3525 // CHECK5-NEXT: store i64 [[TMP17]], ptr [[TMP23]], align 8 3526 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3527 // CHECK5-NEXT: store i64 [[TMP17]], ptr [[TMP24]], align 8 3528 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3529 // CHECK5-NEXT: store ptr null, ptr [[TMP25]], align 8 3530 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3531 // CHECK5-NEXT: store i64 [[TMP19]], ptr [[TMP26]], align 8 3532 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3533 // CHECK5-NEXT: store i64 [[TMP19]], ptr [[TMP27]], align 8 3534 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3535 // CHECK5-NEXT: store ptr null, ptr [[TMP28]], align 8 3536 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3537 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3538 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3539 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3540 // CHECK5-NEXT: store i32 1, ptr [[TMP31]], align 4 3541 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3542 // CHECK5-NEXT: store i32 3, ptr [[TMP32]], align 4 3543 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3544 // CHECK5-NEXT: store ptr [[TMP29]], ptr [[TMP33]], align 8 3545 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3546 // CHECK5-NEXT: store ptr [[TMP30]], ptr [[TMP34]], align 8 3547 // CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3548 // CHECK5-NEXT: store ptr @.offload_sizes, ptr [[TMP35]], align 8 3549 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3550 // CHECK5-NEXT: store ptr @.offload_maptypes, ptr [[TMP36]], align 8 3551 // CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3552 // CHECK5-NEXT: store ptr null, ptr [[TMP37]], align 8 3553 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3554 // CHECK5-NEXT: store ptr null, ptr [[TMP38]], align 8 3555 // CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3556 // CHECK5-NEXT: store i64 0, ptr [[TMP39]], align 8 3557 // CHECK5-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, ptr [[KERNEL_ARGS]]) 3558 // CHECK5-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 3559 // CHECK5-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3560 // CHECK5: omp_offload.failed: 3561 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]]) #[[ATTR4]] 3562 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 3563 // CHECK5: omp_offload.cont: 3564 // CHECK5-NEXT: [[TMP42:%.*]] = load i32, ptr [[A]], align 4 3565 // CHECK5-NEXT: store i32 [[TMP42]], ptr [[A_CASTED3]], align 4 3566 // CHECK5-NEXT: [[TMP43:%.*]] = load i64, ptr [[A_CASTED3]], align 8 3567 // CHECK5-NEXT: [[TMP44:%.*]] = load i16, ptr [[AA]], align 2 3568 // CHECK5-NEXT: store i16 [[TMP44]], ptr [[AA_CASTED4]], align 2 3569 // CHECK5-NEXT: [[TMP45:%.*]] = load i64, ptr [[AA_CASTED4]], align 8 3570 // CHECK5-NEXT: [[TMP46:%.*]] = load i32, ptr [[N_ADDR]], align 4 3571 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP46]], 10 3572 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3573 // CHECK5: omp_if.then: 3574 // CHECK5-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 3575 // CHECK5-NEXT: store i64 [[TMP43]], ptr [[TMP47]], align 8 3576 // CHECK5-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 3577 // CHECK5-NEXT: store i64 [[TMP43]], ptr [[TMP48]], align 8 3578 // CHECK5-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 3579 // CHECK5-NEXT: store ptr null, ptr [[TMP49]], align 8 3580 // CHECK5-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 3581 // CHECK5-NEXT: store i64 [[TMP45]], ptr [[TMP50]], align 8 3582 // CHECK5-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 3583 // CHECK5-NEXT: store i64 [[TMP45]], ptr [[TMP51]], align 8 3584 // CHECK5-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 3585 // CHECK5-NEXT: store ptr null, ptr [[TMP52]], align 8 3586 // CHECK5-NEXT: [[TMP53:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 3587 // CHECK5-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 3588 // CHECK5-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 3589 // CHECK5-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0 3590 // CHECK5-NEXT: store i32 1, ptr [[TMP55]], align 4 3591 // CHECK5-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1 3592 // CHECK5-NEXT: store i32 2, ptr [[TMP56]], align 4 3593 // CHECK5-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2 3594 // CHECK5-NEXT: store ptr [[TMP53]], ptr [[TMP57]], align 8 3595 // CHECK5-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3 3596 // CHECK5-NEXT: store ptr [[TMP54]], ptr [[TMP58]], align 8 3597 // CHECK5-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4 3598 // CHECK5-NEXT: store ptr @.offload_sizes.5, ptr [[TMP59]], align 8 3599 // CHECK5-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5 3600 // CHECK5-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP60]], align 8 3601 // CHECK5-NEXT: [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6 3602 // CHECK5-NEXT: store ptr null, ptr [[TMP61]], align 8 3603 // CHECK5-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7 3604 // CHECK5-NEXT: store ptr null, ptr [[TMP62]], align 8 3605 // CHECK5-NEXT: [[TMP63:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8 3606 // CHECK5-NEXT: store i64 0, ptr [[TMP63]], align 8 3607 // CHECK5-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, ptr [[KERNEL_ARGS8]]) 3608 // CHECK5-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 3609 // CHECK5-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 3610 // CHECK5: omp_offload.failed9: 3611 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP43]], i64 [[TMP45]]) #[[ATTR4]] 3612 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT10]] 3613 // CHECK5: omp_offload.cont10: 3614 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 3615 // CHECK5: omp_if.else: 3616 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP43]], i64 [[TMP45]]) #[[ATTR4]] 3617 // CHECK5-NEXT: br label [[OMP_IF_END]] 3618 // CHECK5: omp_if.end: 3619 // CHECK5-NEXT: [[TMP66:%.*]] = load i32, ptr [[A]], align 4 3620 // CHECK5-NEXT: store i32 [[TMP66]], ptr [[DOTCAPTURE_EXPR_]], align 4 3621 // CHECK5-NEXT: [[TMP67:%.*]] = load i32, ptr [[A]], align 4 3622 // CHECK5-NEXT: store i32 [[TMP67]], ptr [[A_CASTED11]], align 4 3623 // CHECK5-NEXT: [[TMP68:%.*]] = load i64, ptr [[A_CASTED11]], align 8 3624 // CHECK5-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 3625 // CHECK5-NEXT: store i32 [[TMP69]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 3626 // CHECK5-NEXT: [[TMP70:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 3627 // CHECK5-NEXT: [[TMP71:%.*]] = load i32, ptr [[N_ADDR]], align 4 3628 // CHECK5-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP71]], 20 3629 // CHECK5-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]] 3630 // CHECK5: omp_if.then13: 3631 // CHECK5-NEXT: [[TMP72:%.*]] = mul nuw i64 [[TMP2]], 4 3632 // CHECK5-NEXT: [[TMP73:%.*]] = mul nuw i64 5, [[TMP5]] 3633 // CHECK5-NEXT: [[TMP74:%.*]] = mul nuw i64 [[TMP73]], 8 3634 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.8, i64 80, i1 false) 3635 // CHECK5-NEXT: [[TMP75:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 3636 // CHECK5-NEXT: store i64 [[TMP68]], ptr [[TMP75]], align 8 3637 // CHECK5-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 3638 // CHECK5-NEXT: store i64 [[TMP68]], ptr [[TMP76]], align 8 3639 // CHECK5-NEXT: [[TMP77:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0 3640 // CHECK5-NEXT: store ptr null, ptr [[TMP77]], align 8 3641 // CHECK5-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 3642 // CHECK5-NEXT: store ptr [[B]], ptr [[TMP78]], align 8 3643 // CHECK5-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 3644 // CHECK5-NEXT: store ptr [[B]], ptr [[TMP79]], align 8 3645 // CHECK5-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1 3646 // CHECK5-NEXT: store ptr null, ptr [[TMP80]], align 8 3647 // CHECK5-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 3648 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP81]], align 8 3649 // CHECK5-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 3650 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP82]], align 8 3651 // CHECK5-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 2 3652 // CHECK5-NEXT: store ptr null, ptr [[TMP83]], align 8 3653 // CHECK5-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 3654 // CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP84]], align 8 3655 // CHECK5-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 3656 // CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP85]], align 8 3657 // CHECK5-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 3658 // CHECK5-NEXT: store i64 [[TMP72]], ptr [[TMP86]], align 8 3659 // CHECK5-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 3 3660 // CHECK5-NEXT: store ptr null, ptr [[TMP87]], align 8 3661 // CHECK5-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 3662 // CHECK5-NEXT: store ptr [[C]], ptr [[TMP88]], align 8 3663 // CHECK5-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 3664 // CHECK5-NEXT: store ptr [[C]], ptr [[TMP89]], align 8 3665 // CHECK5-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 4 3666 // CHECK5-NEXT: store ptr null, ptr [[TMP90]], align 8 3667 // CHECK5-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 3668 // CHECK5-NEXT: store i64 5, ptr [[TMP91]], align 8 3669 // CHECK5-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 3670 // CHECK5-NEXT: store i64 5, ptr [[TMP92]], align 8 3671 // CHECK5-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 5 3672 // CHECK5-NEXT: store ptr null, ptr [[TMP93]], align 8 3673 // CHECK5-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 3674 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP94]], align 8 3675 // CHECK5-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 3676 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP95]], align 8 3677 // CHECK5-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 6 3678 // CHECK5-NEXT: store ptr null, ptr [[TMP96]], align 8 3679 // CHECK5-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 3680 // CHECK5-NEXT: store ptr [[VLA1]], ptr [[TMP97]], align 8 3681 // CHECK5-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 3682 // CHECK5-NEXT: store ptr [[VLA1]], ptr [[TMP98]], align 8 3683 // CHECK5-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 3684 // CHECK5-NEXT: store i64 [[TMP74]], ptr [[TMP99]], align 8 3685 // CHECK5-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 7 3686 // CHECK5-NEXT: store ptr null, ptr [[TMP100]], align 8 3687 // CHECK5-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 3688 // CHECK5-NEXT: store ptr [[D]], ptr [[TMP101]], align 8 3689 // CHECK5-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 3690 // CHECK5-NEXT: store ptr [[D]], ptr [[TMP102]], align 8 3691 // CHECK5-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 8 3692 // CHECK5-NEXT: store ptr null, ptr [[TMP103]], align 8 3693 // CHECK5-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 3694 // CHECK5-NEXT: store i64 [[TMP70]], ptr [[TMP104]], align 8 3695 // CHECK5-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 3696 // CHECK5-NEXT: store i64 [[TMP70]], ptr [[TMP105]], align 8 3697 // CHECK5-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 9 3698 // CHECK5-NEXT: store ptr null, ptr [[TMP106]], align 8 3699 // CHECK5-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 3700 // CHECK5-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 3701 // CHECK5-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3702 // CHECK5-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 3703 // CHECK5-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0 3704 // CHECK5-NEXT: store i32 1, ptr [[TMP110]], align 4 3705 // CHECK5-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1 3706 // CHECK5-NEXT: store i32 10, ptr [[TMP111]], align 4 3707 // CHECK5-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2 3708 // CHECK5-NEXT: store ptr [[TMP107]], ptr [[TMP112]], align 8 3709 // CHECK5-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3 3710 // CHECK5-NEXT: store ptr [[TMP108]], ptr [[TMP113]], align 8 3711 // CHECK5-NEXT: [[TMP114:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4 3712 // CHECK5-NEXT: store ptr [[TMP109]], ptr [[TMP114]], align 8 3713 // CHECK5-NEXT: [[TMP115:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5 3714 // CHECK5-NEXT: store ptr @.offload_maptypes.9, ptr [[TMP115]], align 8 3715 // CHECK5-NEXT: [[TMP116:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6 3716 // CHECK5-NEXT: store ptr null, ptr [[TMP116]], align 8 3717 // CHECK5-NEXT: [[TMP117:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7 3718 // CHECK5-NEXT: store ptr null, ptr [[TMP117]], align 8 3719 // CHECK5-NEXT: [[TMP118:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8 3720 // CHECK5-NEXT: store i64 0, ptr [[TMP118]], align 8 3721 // CHECK5-NEXT: [[TMP119:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, ptr [[KERNEL_ARGS17]]) 3722 // CHECK5-NEXT: [[TMP120:%.*]] = icmp ne i32 [[TMP119]], 0 3723 // CHECK5-NEXT: br i1 [[TMP120]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] 3724 // CHECK5: omp_offload.failed18: 3725 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP68]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP70]]) #[[ATTR4]] 3726 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT19]] 3727 // CHECK5: omp_offload.cont19: 3728 // CHECK5-NEXT: br label [[OMP_IF_END21:%.*]] 3729 // CHECK5: omp_if.else20: 3730 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP68]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP70]]) #[[ATTR4]] 3731 // CHECK5-NEXT: br label [[OMP_IF_END21]] 3732 // CHECK5: omp_if.end21: 3733 // CHECK5-NEXT: [[TMP121:%.*]] = load i32, ptr [[A]], align 4 3734 // CHECK5-NEXT: [[TMP122:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 3735 // CHECK5-NEXT: call void @llvm.stackrestore(ptr [[TMP122]]) 3736 // CHECK5-NEXT: ret i32 [[TMP121]] 3737 // 3738 // 3739 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 3740 // CHECK5-SAME: () #[[ATTR2:[0-9]+]] { 3741 // CHECK5-NEXT: entry: 3742 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @.omp_outlined.) 3743 // CHECK5-NEXT: ret void 3744 // 3745 // 3746 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. 3747 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 3748 // CHECK5-NEXT: entry: 3749 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3750 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3751 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3752 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 3753 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3754 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3755 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3756 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3757 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3758 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3759 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3760 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3761 // CHECK5-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 3762 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3763 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3764 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3765 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 3766 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3767 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3768 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 3769 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3770 // CHECK5: cond.true: 3771 // CHECK5-NEXT: br label [[COND_END:%.*]] 3772 // CHECK5: cond.false: 3773 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3774 // CHECK5-NEXT: br label [[COND_END]] 3775 // CHECK5: cond.end: 3776 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3777 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3778 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3779 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 3780 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3781 // CHECK5: omp.inner.for.cond: 3782 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 3783 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 3784 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3785 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3786 // CHECK5: omp.inner.for.body: 3787 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 3788 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 3789 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 3790 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 3791 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3792 // CHECK5: omp.body.continue: 3793 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3794 // CHECK5: omp.inner.for.inc: 3795 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 3796 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 3797 // CHECK5-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 3798 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 3799 // CHECK5: omp.inner.for.end: 3800 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3801 // CHECK5: omp.loop.exit: 3802 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 3803 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3804 // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 3805 // CHECK5-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3806 // CHECK5: .omp.final.then: 3807 // CHECK5-NEXT: store i32 33, ptr [[I]], align 4 3808 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 3809 // CHECK5: .omp.final.done: 3810 // CHECK5-NEXT: ret void 3811 // 3812 // 3813 // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry. 3814 // CHECK5-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 3815 // CHECK5-NEXT: entry: 3816 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 3817 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 3818 // CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 3819 // CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 3820 // CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 3821 // CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 3822 // CHECK5-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3823 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 3824 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 3825 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 3826 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 3827 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 3828 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 3829 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 3830 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 3831 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 3832 // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 3833 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 3834 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 3835 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 3836 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 3837 // CHECK5-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 3838 // CHECK5-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !25 3839 // CHECK5-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25 3840 // CHECK5-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25 3841 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !25 3842 // CHECK5-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !25 3843 // CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !25 3844 // CHECK5-NEXT: store i32 1, ptr [[KERNEL_ARGS_I]], align 4, !noalias !25 3845 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 3846 // CHECK5-NEXT: store i32 0, ptr [[TMP9]], align 4, !noalias !25 3847 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 3848 // CHECK5-NEXT: store ptr null, ptr [[TMP10]], align 8, !noalias !25 3849 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 3850 // CHECK5-NEXT: store ptr null, ptr [[TMP11]], align 8, !noalias !25 3851 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 3852 // CHECK5-NEXT: store ptr null, ptr [[TMP12]], align 8, !noalias !25 3853 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 3854 // CHECK5-NEXT: store ptr null, ptr [[TMP13]], align 8, !noalias !25 3855 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 3856 // CHECK5-NEXT: store ptr null, ptr [[TMP14]], align 8, !noalias !25 3857 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 3858 // CHECK5-NEXT: store ptr null, ptr [[TMP15]], align 8, !noalias !25 3859 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 3860 // CHECK5-NEXT: store i64 0, ptr [[TMP16]], align 8, !noalias !25 3861 // CHECK5-NEXT: [[TMP17:%.*]] = call i32 @__tgt_target_kernel_nowait(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, ptr [[KERNEL_ARGS_I]], i32 0, ptr null, i32 0, ptr null) 3862 // CHECK5-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 3863 // CHECK5-NEXT: br i1 [[TMP18]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 3864 // CHECK5: omp_offload.failed.i: 3865 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] 3866 // CHECK5-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 3867 // CHECK5: .omp_outlined..1.exit: 3868 // CHECK5-NEXT: ret i32 0 3869 // 3870 // 3871 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 3872 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 3873 // CHECK5-NEXT: entry: 3874 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3875 // CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 3876 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3877 // CHECK5-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 3878 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 3879 // CHECK5-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8 3880 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3881 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 3882 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 3883 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[K_ADDR]], align 8 3884 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[K_CASTED]], align 8 3885 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[K_CASTED]], align 8 3886 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..2, i64 [[TMP1]], i64 [[TMP3]]) 3887 // CHECK5-NEXT: ret void 3888 // 3889 // 3890 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 3891 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 3892 // CHECK5-NEXT: entry: 3893 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3894 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3895 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3896 // CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 3897 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3898 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 3899 // CHECK5-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 3900 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3901 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3902 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3903 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3904 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3905 // CHECK5-NEXT: [[K1:%.*]] = alloca i64, align 8 3906 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3907 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3908 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 3909 // CHECK5-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8 3910 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[K_ADDR]], align 8 3911 // CHECK5-NEXT: store i64 [[TMP0]], ptr [[DOTLINEAR_START]], align 8 3912 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3913 // CHECK5-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 4 3914 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3915 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3916 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3917 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 3918 // CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 3919 // CHECK5-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 3920 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3921 // CHECK5: omp.dispatch.cond: 3922 // CHECK5-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP2]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]) 3923 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 3924 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3925 // CHECK5: omp.dispatch.body: 3926 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3927 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 3928 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3929 // CHECK5: omp.inner.for.cond: 3930 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] 3931 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] 3932 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3933 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3934 // CHECK5: omp.inner.for.body: 3935 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 3936 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 3937 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 3938 // CHECK5-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] 3939 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP26]] 3940 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 3941 // CHECK5-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 3942 // CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 3943 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV]] 3944 // CHECK5-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP26]] 3945 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] 3946 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 3947 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] 3948 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3949 // CHECK5: omp.body.continue: 3950 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3951 // CHECK5: omp.inner.for.inc: 3952 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 3953 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 3954 // CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 3955 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] 3956 // CHECK5: omp.inner.for.end: 3957 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3958 // CHECK5: omp.dispatch.inc: 3959 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] 3960 // CHECK5: omp.dispatch.end: 3961 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3962 // CHECK5-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 3963 // CHECK5-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3964 // CHECK5: .omp.final.then: 3965 // CHECK5-NEXT: store i32 1, ptr [[I]], align 4 3966 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 3967 // CHECK5: .omp.final.done: 3968 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3969 // CHECK5-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 3970 // CHECK5-NEXT: br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 3971 // CHECK5: .omp.linear.pu: 3972 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[K1]], align 8 3973 // CHECK5-NEXT: store i64 [[TMP16]], ptr [[K_ADDR]], align 8 3974 // CHECK5-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 3975 // CHECK5: .omp.linear.pu.done: 3976 // CHECK5-NEXT: ret void 3977 // 3978 // 3979 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 3980 // CHECK5-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 3981 // CHECK5-NEXT: entry: 3982 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3983 // CHECK5-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 3984 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3985 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3986 // CHECK5-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 3987 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3988 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 3989 // CHECK5-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 3990 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 3991 // CHECK5-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3992 // CHECK5-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 3993 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 3994 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 3995 // CHECK5-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 3996 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 3997 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 3998 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 3999 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8 4000 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..3, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 4001 // CHECK5-NEXT: ret void 4002 // 4003 // 4004 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 4005 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 4006 // CHECK5-NEXT: entry: 4007 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4008 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4009 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4010 // CHECK5-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 4011 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4012 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4013 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 4014 // CHECK5-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 4015 // CHECK5-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 4016 // CHECK5-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 4017 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4018 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4019 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4020 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4021 // CHECK5-NEXT: [[IT:%.*]] = alloca i64, align 8 4022 // CHECK5-NEXT: [[LIN2:%.*]] = alloca i32, align 4 4023 // CHECK5-NEXT: [[A3:%.*]] = alloca i32, align 4 4024 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4025 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4026 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4027 // CHECK5-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 4028 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4029 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 4030 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 4031 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 4032 // CHECK5-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 4033 // CHECK5-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 4034 // CHECK5-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 4035 // CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 4036 // CHECK5-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 4037 // CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 4038 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4039 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4040 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 4041 // CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]]) 4042 // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 4043 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 4044 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 4045 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4046 // CHECK5: cond.true: 4047 // CHECK5-NEXT: br label [[COND_END:%.*]] 4048 // CHECK5: cond.false: 4049 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 4050 // CHECK5-NEXT: br label [[COND_END]] 4051 // CHECK5: cond.end: 4052 // CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 4053 // CHECK5-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 4054 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 4055 // CHECK5-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 4056 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4057 // CHECK5: omp.inner.for.cond: 4058 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29:![0-9]+]] 4059 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP29]] 4060 // CHECK5-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 4061 // CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4062 // CHECK5: omp.inner.for.body: 4063 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4064 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 4065 // CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 4066 // CHECK5-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP29]] 4067 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP29]] 4068 // CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 4069 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4070 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]] 4071 // CHECK5-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 4072 // CHECK5-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 4073 // CHECK5-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 4074 // CHECK5-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP29]] 4075 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP29]] 4076 // CHECK5-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 4077 // CHECK5-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4078 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]] 4079 // CHECK5-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 4080 // CHECK5-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 4081 // CHECK5-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 4082 // CHECK5-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP29]] 4083 // CHECK5-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] 4084 // CHECK5-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 4085 // CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 4086 // CHECK5-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 4087 // CHECK5-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] 4088 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4089 // CHECK5: omp.body.continue: 4090 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4091 // CHECK5: omp.inner.for.inc: 4092 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4093 // CHECK5-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 4094 // CHECK5-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4095 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] 4096 // CHECK5: omp.inner.for.end: 4097 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4098 // CHECK5: omp.loop.exit: 4099 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 4100 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4101 // CHECK5-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 4102 // CHECK5-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4103 // CHECK5: .omp.final.then: 4104 // CHECK5-NEXT: store i64 400, ptr [[IT]], align 8 4105 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4106 // CHECK5: .omp.final.done: 4107 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4108 // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 4109 // CHECK5-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 4110 // CHECK5: .omp.linear.pu: 4111 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 4112 // CHECK5-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 4113 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 4114 // CHECK5-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 4115 // CHECK5-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 4116 // CHECK5: .omp.linear.pu.done: 4117 // CHECK5-NEXT: ret void 4118 // 4119 // 4120 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 4121 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 4122 // CHECK5-NEXT: entry: 4123 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4124 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4125 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4126 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4127 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4128 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4129 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4130 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 4131 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 4132 // CHECK5-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4133 // CHECK5-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 4134 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 4135 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..4, i64 [[TMP1]], i64 [[TMP3]]) 4136 // CHECK5-NEXT: ret void 4137 // 4138 // 4139 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 4140 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 4141 // CHECK5-NEXT: entry: 4142 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4143 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4144 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4145 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4146 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4147 // CHECK5-NEXT: [[TMP:%.*]] = alloca i16, align 2 4148 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4149 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4150 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4151 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4152 // CHECK5-NEXT: [[IT:%.*]] = alloca i16, align 2 4153 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4154 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4155 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4156 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4157 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4158 // CHECK5-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 4159 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4160 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4161 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4162 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 4163 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 4164 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4165 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 4166 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4167 // CHECK5: cond.true: 4168 // CHECK5-NEXT: br label [[COND_END:%.*]] 4169 // CHECK5: cond.false: 4170 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4171 // CHECK5-NEXT: br label [[COND_END]] 4172 // CHECK5: cond.end: 4173 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4174 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4175 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4176 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 4177 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4178 // CHECK5: omp.inner.for.cond: 4179 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]] 4180 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]] 4181 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4182 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4183 // CHECK5: omp.inner.for.body: 4184 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 4185 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 4186 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 4187 // CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 4188 // CHECK5-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP32]] 4189 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] 4190 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 4191 // CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] 4192 // CHECK5-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] 4193 // CHECK5-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 4194 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 4195 // CHECK5-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 4196 // CHECK5-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] 4197 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4198 // CHECK5: omp.body.continue: 4199 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4200 // CHECK5: omp.inner.for.inc: 4201 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 4202 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 4203 // CHECK5-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 4204 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] 4205 // CHECK5: omp.inner.for.end: 4206 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4207 // CHECK5: omp.loop.exit: 4208 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 4209 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4210 // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 4211 // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4212 // CHECK5: .omp.final.then: 4213 // CHECK5-NEXT: store i16 22, ptr [[IT]], align 2 4214 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4215 // CHECK5: .omp.final.done: 4216 // CHECK5-NEXT: ret void 4217 // 4218 // 4219 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 4220 // CHECK5-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 4221 // CHECK5-NEXT: entry: 4222 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4223 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4224 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4225 // CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 4226 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4227 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4228 // CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4229 // CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 4230 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 4231 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4232 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4233 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4234 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4235 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4236 // CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4237 // CHECK5-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 4238 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4239 // CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 4240 // CHECK5-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 4241 // CHECK5-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 4242 // CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 4243 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 4244 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 4245 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4246 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 4247 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4248 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 4249 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 4250 // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 4251 // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 4252 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 4253 // CHECK5-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 4254 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 4255 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 4256 // CHECK5-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 4257 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 4258 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @.omp_outlined..7, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]]) 4259 // CHECK5-NEXT: ret void 4260 // 4261 // 4262 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 4263 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 4264 // CHECK5-NEXT: entry: 4265 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4266 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4267 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4268 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4269 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4270 // CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 4271 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4272 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4273 // CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4274 // CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 4275 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 4276 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4277 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4278 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1 4279 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4280 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4281 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4282 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4283 // CHECK5-NEXT: [[IT:%.*]] = alloca i8, align 1 4284 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4285 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4286 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4287 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4288 // CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4289 // CHECK5-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 4290 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4291 // CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 4292 // CHECK5-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 4293 // CHECK5-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 4294 // CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 4295 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 4296 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 4297 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4298 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 4299 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4300 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 4301 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 4302 // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 4303 // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 4304 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4305 // CHECK5-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 4306 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4307 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4308 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 4309 // CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4310 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 4311 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 4312 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4313 // CHECK5: omp.dispatch.cond: 4314 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4315 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 4316 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4317 // CHECK5: cond.true: 4318 // CHECK5-NEXT: br label [[COND_END:%.*]] 4319 // CHECK5: cond.false: 4320 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4321 // CHECK5-NEXT: br label [[COND_END]] 4322 // CHECK5: cond.end: 4323 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 4324 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4325 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4326 // CHECK5-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 4327 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4328 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4329 // CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 4330 // CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4331 // CHECK5: omp.dispatch.body: 4332 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4333 // CHECK5: omp.inner.for.cond: 4334 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]] 4335 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]] 4336 // CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 4337 // CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4338 // CHECK5: omp.inner.for.body: 4339 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 4340 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 4341 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 4342 // CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 4343 // CHECK5-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP35]] 4344 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] 4345 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 4346 // CHECK5-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] 4347 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 4348 // CHECK5-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] 4349 // CHECK5-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 4350 // CHECK5-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 4351 // CHECK5-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 4352 // CHECK5-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] 4353 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 4354 // CHECK5-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP35]] 4355 // CHECK5-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 4356 // CHECK5-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 4357 // CHECK5-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 4358 // CHECK5-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP35]] 4359 // CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 4360 // CHECK5-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 4361 // CHECK5-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]] 4362 // CHECK5-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 4363 // CHECK5-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]] 4364 // CHECK5-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 4365 // CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]] 4366 // CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3 4367 // CHECK5-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP35]] 4368 // CHECK5-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 4369 // CHECK5-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP35]] 4370 // CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 4371 // CHECK5-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]] 4372 // CHECK5-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 4373 // CHECK5-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]] 4374 // CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 4375 // CHECK5-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]] 4376 // CHECK5-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 4377 // CHECK5-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 4378 // CHECK5-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 4379 // CHECK5-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]] 4380 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4381 // CHECK5: omp.body.continue: 4382 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4383 // CHECK5: omp.inner.for.inc: 4384 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 4385 // CHECK5-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 4386 // CHECK5-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 4387 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] 4388 // CHECK5: omp.inner.for.end: 4389 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4390 // CHECK5: omp.dispatch.inc: 4391 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4392 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 4393 // CHECK5-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 4394 // CHECK5-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 4395 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4396 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 4397 // CHECK5-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 4398 // CHECK5-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 4399 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] 4400 // CHECK5: omp.dispatch.end: 4401 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 4402 // CHECK5-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4403 // CHECK5-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 4404 // CHECK5-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4405 // CHECK5: .omp.final.then: 4406 // CHECK5-NEXT: store i8 96, ptr [[IT]], align 1 4407 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4408 // CHECK5: .omp.final.done: 4409 // CHECK5-NEXT: ret void 4410 // 4411 // 4412 // CHECK5-LABEL: define {{[^@]+}}@_Z3bari 4413 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 4414 // CHECK5-NEXT: entry: 4415 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4416 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 4417 // CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 4418 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 4419 // CHECK5-NEXT: store i32 0, ptr [[A]], align 4 4420 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 4421 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 4422 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 4423 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 4424 // CHECK5-NEXT: store i32 [[ADD]], ptr [[A]], align 4 4425 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 4426 // CHECK5-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 4427 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 4428 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 4429 // CHECK5-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 4430 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 4431 // CHECK5-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 4432 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 4433 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 4434 // CHECK5-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 4435 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 4436 // CHECK5-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 4437 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 4438 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 4439 // CHECK5-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 4440 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 4441 // CHECK5-NEXT: ret i32 [[TMP8]] 4442 // 4443 // 4444 // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 4445 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 4446 // CHECK5-NEXT: entry: 4447 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4448 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4449 // CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 4450 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 4451 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4452 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4453 // CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4454 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4455 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x ptr], align 8 4456 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x ptr], align 8 4457 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x ptr], align 8 4458 // CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 8 4459 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4460 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 4461 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4462 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 4463 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4464 // CHECK5-NEXT: store i32 [[ADD]], ptr [[B]], align 4 4465 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 4466 // CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 4467 // CHECK5-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() 4468 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 4469 // CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 4470 // CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 4471 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 4472 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 4473 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 4474 // CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 4475 // CHECK5-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 4476 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[B]], align 4 4477 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[B_CASTED]], align 4 4478 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[B_CASTED]], align 8 4479 // CHECK5-NEXT: [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4480 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1 4481 // CHECK5-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8 4482 // CHECK5-NEXT: store i8 [[FROMBOOL2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 4483 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 4484 // CHECK5-NEXT: [[TMP10:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4485 // CHECK5-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP10]] to i1 4486 // CHECK5-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4487 // CHECK5: omp_if.then: 4488 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 4489 // CHECK5-NEXT: [[TMP11:%.*]] = mul nuw i64 2, [[TMP2]] 4490 // CHECK5-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 2 4491 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.11, i64 48, i1 false) 4492 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4493 // CHECK5-NEXT: store ptr [[THIS1]], ptr [[TMP13]], align 8 4494 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4495 // CHECK5-NEXT: store ptr [[A]], ptr [[TMP14]], align 8 4496 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4497 // CHECK5-NEXT: store ptr null, ptr [[TMP15]], align 8 4498 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4499 // CHECK5-NEXT: store i64 [[TMP7]], ptr [[TMP16]], align 8 4500 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4501 // CHECK5-NEXT: store i64 [[TMP7]], ptr [[TMP17]], align 8 4502 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4503 // CHECK5-NEXT: store ptr null, ptr [[TMP18]], align 8 4504 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4505 // CHECK5-NEXT: store i64 2, ptr [[TMP19]], align 8 4506 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4507 // CHECK5-NEXT: store i64 2, ptr [[TMP20]], align 8 4508 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4509 // CHECK5-NEXT: store ptr null, ptr [[TMP21]], align 8 4510 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4511 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP22]], align 8 4512 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4513 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP23]], align 8 4514 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 4515 // CHECK5-NEXT: store ptr null, ptr [[TMP24]], align 8 4516 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 4517 // CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP25]], align 8 4518 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 4519 // CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP26]], align 8 4520 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 4521 // CHECK5-NEXT: store i64 [[TMP12]], ptr [[TMP27]], align 8 4522 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 4523 // CHECK5-NEXT: store ptr null, ptr [[TMP28]], align 8 4524 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 4525 // CHECK5-NEXT: store i64 [[TMP9]], ptr [[TMP29]], align 8 4526 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5 4527 // CHECK5-NEXT: store i64 [[TMP9]], ptr [[TMP30]], align 8 4528 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 4529 // CHECK5-NEXT: store ptr null, ptr [[TMP31]], align 8 4530 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4531 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4532 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4533 // CHECK5-NEXT: [[TMP35:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4534 // CHECK5-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP35]] to i1 4535 // CHECK5-NEXT: [[TMP36:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 4536 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 4537 // CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 4538 // CHECK5-NEXT: store i32 1, ptr [[TMP37]], align 4 4539 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 4540 // CHECK5-NEXT: store i32 6, ptr [[TMP38]], align 4 4541 // CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 4542 // CHECK5-NEXT: store ptr [[TMP32]], ptr [[TMP39]], align 8 4543 // CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 4544 // CHECK5-NEXT: store ptr [[TMP33]], ptr [[TMP40]], align 8 4545 // CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 4546 // CHECK5-NEXT: store ptr [[TMP34]], ptr [[TMP41]], align 8 4547 // CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 4548 // CHECK5-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP42]], align 8 4549 // CHECK5-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 4550 // CHECK5-NEXT: store ptr null, ptr [[TMP43]], align 8 4551 // CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 4552 // CHECK5-NEXT: store ptr null, ptr [[TMP44]], align 8 4553 // CHECK5-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 4554 // CHECK5-NEXT: store i64 0, ptr [[TMP45]], align 8 4555 // CHECK5-NEXT: [[TMP46:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 [[TMP36]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, ptr [[KERNEL_ARGS]]) 4556 // CHECK5-NEXT: [[TMP47:%.*]] = icmp ne i32 [[TMP46]], 0 4557 // CHECK5-NEXT: br i1 [[TMP47]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4558 // CHECK5: omp_offload.failed: 4559 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR4]] 4560 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 4561 // CHECK5: omp_offload.cont: 4562 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4563 // CHECK5: omp_if.else: 4564 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR4]] 4565 // CHECK5-NEXT: br label [[OMP_IF_END]] 4566 // CHECK5: omp_if.end: 4567 // CHECK5-NEXT: [[TMP48:%.*]] = mul nsw i64 1, [[TMP2]] 4568 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP48]] 4569 // CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 4570 // CHECK5-NEXT: [[TMP49:%.*]] = load i16, ptr [[ARRAYIDX5]], align 2 4571 // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP49]] to i32 4572 // CHECK5-NEXT: [[TMP50:%.*]] = load i32, ptr [[B]], align 4 4573 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV]], [[TMP50]] 4574 // CHECK5-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 4575 // CHECK5-NEXT: call void @llvm.stackrestore(ptr [[TMP51]]) 4576 // CHECK5-NEXT: ret i32 [[ADD6]] 4577 // 4578 // 4579 // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici 4580 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 4581 // CHECK5-NEXT: entry: 4582 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4583 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 4584 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 4585 // CHECK5-NEXT: [[AAA:%.*]] = alloca i8, align 1 4586 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4587 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4588 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4589 // CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 4590 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 4591 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 4592 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 4593 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 4594 // CHECK5-NEXT: store i32 0, ptr [[A]], align 4 4595 // CHECK5-NEXT: store i16 0, ptr [[AA]], align 2 4596 // CHECK5-NEXT: store i8 0, ptr [[AAA]], align 1 4597 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 4598 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 4599 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 4600 // CHECK5-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 4601 // CHECK5-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 4602 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 4603 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1 4604 // CHECK5-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1 4605 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 4606 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 4607 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 4608 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4609 // CHECK5: omp_if.then: 4610 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4611 // CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP7]], align 8 4612 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4613 // CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP8]], align 8 4614 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4615 // CHECK5-NEXT: store ptr null, ptr [[TMP9]], align 8 4616 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4617 // CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP10]], align 8 4618 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4619 // CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP11]], align 8 4620 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4621 // CHECK5-NEXT: store ptr null, ptr [[TMP12]], align 8 4622 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4623 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP13]], align 8 4624 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4625 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP14]], align 8 4626 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4627 // CHECK5-NEXT: store ptr null, ptr [[TMP15]], align 8 4628 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4629 // CHECK5-NEXT: store ptr [[B]], ptr [[TMP16]], align 8 4630 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4631 // CHECK5-NEXT: store ptr [[B]], ptr [[TMP17]], align 8 4632 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 4633 // CHECK5-NEXT: store ptr null, ptr [[TMP18]], align 8 4634 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4635 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4636 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 4637 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 4638 // CHECK5-NEXT: store i32 1, ptr [[TMP21]], align 4 4639 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 4640 // CHECK5-NEXT: store i32 4, ptr [[TMP22]], align 4 4641 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 4642 // CHECK5-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8 4643 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 4644 // CHECK5-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8 4645 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 4646 // CHECK5-NEXT: store ptr @.offload_sizes.14, ptr [[TMP25]], align 8 4647 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 4648 // CHECK5-NEXT: store ptr @.offload_maptypes.15, ptr [[TMP26]], align 8 4649 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 4650 // CHECK5-NEXT: store ptr null, ptr [[TMP27]], align 8 4651 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 4652 // CHECK5-NEXT: store ptr null, ptr [[TMP28]], align 8 4653 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 4654 // CHECK5-NEXT: store i64 0, ptr [[TMP29]], align 8 4655 // CHECK5-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, ptr [[KERNEL_ARGS]]) 4656 // CHECK5-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 4657 // CHECK5-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4658 // CHECK5: omp_offload.failed: 4659 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]] 4660 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 4661 // CHECK5: omp_offload.cont: 4662 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4663 // CHECK5: omp_if.else: 4664 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]] 4665 // CHECK5-NEXT: br label [[OMP_IF_END]] 4666 // CHECK5: omp_if.end: 4667 // CHECK5-NEXT: [[TMP32:%.*]] = load i32, ptr [[A]], align 4 4668 // CHECK5-NEXT: ret i32 [[TMP32]] 4669 // 4670 // 4671 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 4672 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 4673 // CHECK5-NEXT: entry: 4674 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4675 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 4676 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 4677 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4678 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4679 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4680 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 4681 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 4682 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 4683 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 4684 // CHECK5-NEXT: store i32 0, ptr [[A]], align 4 4685 // CHECK5-NEXT: store i16 0, ptr [[AA]], align 2 4686 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 4687 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 4688 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 4689 // CHECK5-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 4690 // CHECK5-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 4691 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 4692 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 4693 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 4694 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4695 // CHECK5: omp_if.then: 4696 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4697 // CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 4698 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4699 // CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 8 4700 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4701 // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 4702 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4703 // CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 8 4704 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4705 // CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP9]], align 8 4706 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4707 // CHECK5-NEXT: store ptr null, ptr [[TMP10]], align 8 4708 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4709 // CHECK5-NEXT: store ptr [[B]], ptr [[TMP11]], align 8 4710 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4711 // CHECK5-NEXT: store ptr [[B]], ptr [[TMP12]], align 8 4712 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4713 // CHECK5-NEXT: store ptr null, ptr [[TMP13]], align 8 4714 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4715 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4716 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 4717 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 4718 // CHECK5-NEXT: store i32 1, ptr [[TMP16]], align 4 4719 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 4720 // CHECK5-NEXT: store i32 3, ptr [[TMP17]], align 4 4721 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 4722 // CHECK5-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8 4723 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 4724 // CHECK5-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8 4725 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 4726 // CHECK5-NEXT: store ptr @.offload_sizes.17, ptr [[TMP20]], align 8 4727 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 4728 // CHECK5-NEXT: store ptr @.offload_maptypes.18, ptr [[TMP21]], align 8 4729 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 4730 // CHECK5-NEXT: store ptr null, ptr [[TMP22]], align 8 4731 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 4732 // CHECK5-NEXT: store ptr null, ptr [[TMP23]], align 8 4733 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 4734 // CHECK5-NEXT: store i64 0, ptr [[TMP24]], align 8 4735 // CHECK5-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, ptr [[KERNEL_ARGS]]) 4736 // CHECK5-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 4737 // CHECK5-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4738 // CHECK5: omp_offload.failed: 4739 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] 4740 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 4741 // CHECK5: omp_offload.cont: 4742 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4743 // CHECK5: omp_if.else: 4744 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] 4745 // CHECK5-NEXT: br label [[OMP_IF_END]] 4746 // CHECK5: omp_if.end: 4747 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, ptr [[A]], align 4 4748 // CHECK5-NEXT: ret i32 [[TMP27]] 4749 // 4750 // 4751 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 4752 // CHECK5-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 4753 // CHECK5-NEXT: entry: 4754 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4755 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4756 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4757 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4758 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4759 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4760 // CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4761 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4762 // CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 4763 // CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 4764 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 4765 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4766 // CHECK5-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 4767 // CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4768 // CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 4769 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4770 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 4771 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4772 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4773 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 4774 // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4775 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4 4776 // CHECK5-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 4777 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 4778 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 4779 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 4780 // CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 4781 // CHECK5-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 4782 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 4783 // CHECK5-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 4784 // CHECK5-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1 4785 // CHECK5-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4786 // CHECK5: omp_if.then: 4787 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @.omp_outlined..10, ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) 4788 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4789 // CHECK5: omp_if.else: 4790 // CHECK5-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 4791 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 4792 // CHECK5-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 4793 // CHECK5-NEXT: call void @.omp_outlined..10(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) #[[ATTR4]] 4794 // CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 4795 // CHECK5-NEXT: br label [[OMP_IF_END]] 4796 // CHECK5: omp_if.end: 4797 // CHECK5-NEXT: ret void 4798 // 4799 // 4800 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 4801 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 4802 // CHECK5-NEXT: entry: 4803 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4804 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4805 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4806 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4807 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4808 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4809 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4810 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4811 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4812 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 4813 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4814 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4815 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4816 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4817 // CHECK5-NEXT: [[IT:%.*]] = alloca i64, align 8 4818 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4819 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4820 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4821 // CHECK5-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 4822 // CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4823 // CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 4824 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4825 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 4826 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4827 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4828 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 4829 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4830 // CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 4831 // CHECK5-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 4832 // CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 4833 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4834 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 4835 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 4836 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4837 // CHECK5: omp_if.then: 4838 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4839 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 4840 // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 4841 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 4842 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 4843 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4844 // CHECK5: cond.true: 4845 // CHECK5-NEXT: br label [[COND_END:%.*]] 4846 // CHECK5: cond.false: 4847 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 4848 // CHECK5-NEXT: br label [[COND_END]] 4849 // CHECK5: cond.end: 4850 // CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 4851 // CHECK5-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 4852 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 4853 // CHECK5-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV]], align 8 4854 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4855 // CHECK5: omp.inner.for.cond: 4856 // CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38:![0-9]+]] 4857 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP38]] 4858 // CHECK5-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 4859 // CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4860 // CHECK5: omp.inner.for.body: 4861 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 4862 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 4863 // CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 4864 // CHECK5-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP38]] 4865 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]] 4866 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double 4867 // CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 4868 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 4869 // CHECK5-NEXT: store double [[ADD]], ptr [[A]], align 8, !nontemporal !39, !llvm.access.group [[ACC_GRP38]] 4870 // CHECK5-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 4871 // CHECK5-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 8, !nontemporal !39, !llvm.access.group [[ACC_GRP38]] 4872 // CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 4873 // CHECK5-NEXT: store double [[INC]], ptr [[A4]], align 8, !nontemporal !39, !llvm.access.group [[ACC_GRP38]] 4874 // CHECK5-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 4875 // CHECK5-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]] 4876 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP15]] 4877 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 4878 // CHECK5-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP38]] 4879 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4880 // CHECK5: omp.body.continue: 4881 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4882 // CHECK5: omp.inner.for.inc: 4883 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 4884 // CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1 4885 // CHECK5-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 4886 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] 4887 // CHECK5: omp.inner.for.end: 4888 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4889 // CHECK5: omp_if.else: 4890 // CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4891 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 4892 // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP18]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 4893 // CHECK5-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 4894 // CHECK5-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[TMP19]], 3 4895 // CHECK5-NEXT: br i1 [[CMP8]], label [[COND_TRUE9:%.*]], label [[COND_FALSE10:%.*]] 4896 // CHECK5: cond.true9: 4897 // CHECK5-NEXT: br label [[COND_END11:%.*]] 4898 // CHECK5: cond.false10: 4899 // CHECK5-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 4900 // CHECK5-NEXT: br label [[COND_END11]] 4901 // CHECK5: cond.end11: 4902 // CHECK5-NEXT: [[COND12:%.*]] = phi i64 [ 3, [[COND_TRUE9]] ], [ [[TMP20]], [[COND_FALSE10]] ] 4903 // CHECK5-NEXT: store i64 [[COND12]], ptr [[DOTOMP_UB]], align 8 4904 // CHECK5-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 4905 // CHECK5-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV]], align 8 4906 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 4907 // CHECK5: omp.inner.for.cond13: 4908 // CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4909 // CHECK5-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 4910 // CHECK5-NEXT: [[CMP14:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 4911 // CHECK5-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END29:%.*]] 4912 // CHECK5: omp.inner.for.body15: 4913 // CHECK5-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4914 // CHECK5-NEXT: [[MUL16:%.*]] = mul i64 [[TMP24]], 400 4915 // CHECK5-NEXT: [[SUB17:%.*]] = sub i64 2000, [[MUL16]] 4916 // CHECK5-NEXT: store i64 [[SUB17]], ptr [[IT]], align 8 4917 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[B_ADDR]], align 4 4918 // CHECK5-NEXT: [[CONV18:%.*]] = sitofp i32 [[TMP25]] to double 4919 // CHECK5-NEXT: [[ADD19:%.*]] = fadd double [[CONV18]], 1.500000e+00 4920 // CHECK5-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 4921 // CHECK5-NEXT: store double [[ADD19]], ptr [[A20]], align 8 4922 // CHECK5-NEXT: [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 4923 // CHECK5-NEXT: [[TMP26:%.*]] = load double, ptr [[A21]], align 8 4924 // CHECK5-NEXT: [[INC22:%.*]] = fadd double [[TMP26]], 1.000000e+00 4925 // CHECK5-NEXT: store double [[INC22]], ptr [[A21]], align 8 4926 // CHECK5-NEXT: [[CONV23:%.*]] = fptosi double [[INC22]] to i16 4927 // CHECK5-NEXT: [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]] 4928 // CHECK5-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP27]] 4929 // CHECK5-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX24]], i64 1 4930 // CHECK5-NEXT: store i16 [[CONV23]], ptr [[ARRAYIDX25]], align 2 4931 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] 4932 // CHECK5: omp.body.continue26: 4933 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] 4934 // CHECK5: omp.inner.for.inc27: 4935 // CHECK5-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4936 // CHECK5-NEXT: [[ADD28:%.*]] = add i64 [[TMP28]], 1 4937 // CHECK5-NEXT: store i64 [[ADD28]], ptr [[DOTOMP_IV]], align 8 4938 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP42:![0-9]+]] 4939 // CHECK5: omp.inner.for.end29: 4940 // CHECK5-NEXT: br label [[OMP_IF_END]] 4941 // CHECK5: omp_if.end: 4942 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4943 // CHECK5: omp.loop.exit: 4944 // CHECK5-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4945 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4 4946 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]]) 4947 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4948 // CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 4949 // CHECK5-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4950 // CHECK5: .omp.final.then: 4951 // CHECK5-NEXT: store i64 400, ptr [[IT]], align 8 4952 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4953 // CHECK5: .omp.final.done: 4954 // CHECK5-NEXT: ret void 4955 // 4956 // 4957 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 4958 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 4959 // CHECK5-NEXT: entry: 4960 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4961 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4962 // CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 4963 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4964 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4965 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4966 // CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 4967 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4968 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4969 // CHECK5-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 4970 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4971 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 4972 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 4973 // CHECK5-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 4974 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 4975 // CHECK5-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4976 // CHECK5-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 4977 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 4978 // CHECK5-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 4979 // CHECK5-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 4980 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 4981 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @.omp_outlined..13, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]]) 4982 // CHECK5-NEXT: ret void 4983 // 4984 // 4985 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..13 4986 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 4987 // CHECK5-NEXT: entry: 4988 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4989 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4990 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4991 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4992 // CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 4993 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4994 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4995 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 4996 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4997 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4998 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4999 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 5000 // CHECK5-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 5001 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 5002 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 5003 // CHECK5-NEXT: ret void 5004 // 5005 // 5006 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 5007 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5008 // CHECK5-NEXT: entry: 5009 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5010 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5011 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 5012 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5013 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 5014 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 5015 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 5016 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 5017 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 5018 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 5019 // CHECK5-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 5020 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 5021 // CHECK5-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 5022 // CHECK5-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 5023 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 5024 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..16, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) 5025 // CHECK5-NEXT: ret void 5026 // 5027 // 5028 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..16 5029 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 5030 // CHECK5-NEXT: entry: 5031 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 5032 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 5033 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5034 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5035 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 5036 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5037 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 5038 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5039 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5040 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5041 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5042 // CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8 5043 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 5044 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 5045 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 5046 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 5047 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 5048 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 5049 // CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 5050 // CHECK5-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 5051 // CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 5052 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5053 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 5054 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 5055 // CHECK5-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 5056 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5057 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 5058 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5059 // CHECK5: cond.true: 5060 // CHECK5-NEXT: br label [[COND_END:%.*]] 5061 // CHECK5: cond.false: 5062 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5063 // CHECK5-NEXT: br label [[COND_END]] 5064 // CHECK5: cond.end: 5065 // CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 5066 // CHECK5-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 5067 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 5068 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 5069 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5070 // CHECK5: omp.inner.for.cond: 5071 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44:![0-9]+]] 5072 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP44]] 5073 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 5074 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5075 // CHECK5: omp.inner.for.body: 5076 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44]] 5077 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 5078 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 5079 // CHECK5-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP44]] 5080 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]] 5081 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 5082 // CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]] 5083 // CHECK5-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]] 5084 // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 5085 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 5086 // CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 5087 // CHECK5-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]] 5088 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 5089 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] 5090 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 5091 // CHECK5-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] 5092 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5093 // CHECK5: omp.body.continue: 5094 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5095 // CHECK5: omp.inner.for.inc: 5096 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44]] 5097 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 5098 // CHECK5-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44]] 5099 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]] 5100 // CHECK5: omp.inner.for.end: 5101 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5102 // CHECK5: omp.loop.exit: 5103 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 5104 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5105 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 5106 // CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5107 // CHECK5: .omp.final.then: 5108 // CHECK5-NEXT: store i64 11, ptr [[I]], align 8 5109 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 5110 // CHECK5: .omp.final.done: 5111 // CHECK5-NEXT: ret void 5112 // 5113 // 5114 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 5115 // CHECK5-SAME: () #[[ATTR8:[0-9]+]] { 5116 // CHECK5-NEXT: entry: 5117 // CHECK5-NEXT: call void @__tgt_register_requires(i64 1) 5118 // CHECK5-NEXT: ret void 5119 // 5120 // 5121 // CHECK7-LABEL: define {{[^@]+}}@_Z7get_valv 5122 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 5123 // CHECK7-NEXT: entry: 5124 // CHECK7-NEXT: ret i64 0 5125 // 5126 // 5127 // CHECK7-LABEL: define {{[^@]+}}@_Z3fooi 5128 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 5129 // CHECK7-NEXT: entry: 5130 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5131 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 5132 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 5133 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x float], align 4 5134 // CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 5135 // CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 5136 // CHECK7-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 5137 // CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 5138 // CHECK7-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 5139 // CHECK7-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 5140 // CHECK7-NEXT: [[K:%.*]] = alloca i64, align 8 5141 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5142 // CHECK7-NEXT: [[LIN:%.*]] = alloca i32, align 4 5143 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5144 // CHECK7-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 5145 // CHECK7-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 5146 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 5147 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 5148 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 5149 // CHECK7-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 5150 // CHECK7-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 5151 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 4 5152 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 4 5153 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 4 5154 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5155 // CHECK7-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 5156 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 5157 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 4 5158 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 4 5159 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 4 5160 // CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 5161 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 5162 // CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 5163 // CHECK7-NEXT: store i32 0, ptr [[A]], align 4 5164 // CHECK7-NEXT: store i16 0, ptr [[AA]], align 2 5165 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 5166 // CHECK7-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() 5167 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 5168 // CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 5169 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 5170 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 5171 // CHECK7-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 5172 // CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 5173 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 5174 // CHECK7-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, ptr @.omp_task_entry., i64 -1) 5175 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP5]], i32 0, i32 0 5176 // CHECK7-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP5]]) 5177 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 5178 // CHECK7-NEXT: store i64 [[CALL]], ptr [[K]], align 8 5179 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 5180 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 5181 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 5182 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP9]], ptr [[K]]) #[[ATTR4:[0-9]+]] 5183 // CHECK7-NEXT: store i32 12, ptr [[LIN]], align 4 5184 // CHECK7-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2 5185 // CHECK7-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2 5186 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4 5187 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[LIN]], align 4 5188 // CHECK7-NEXT: store i32 [[TMP12]], ptr [[LIN_CASTED]], align 4 5189 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 5190 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4 5191 // CHECK7-NEXT: store i32 [[TMP14]], ptr [[A_CASTED2]], align 4 5192 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[A_CASTED2]], align 4 5193 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5194 // CHECK7-NEXT: store i32 [[TMP11]], ptr [[TMP16]], align 4 5195 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5196 // CHECK7-NEXT: store i32 [[TMP11]], ptr [[TMP17]], align 4 5197 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5198 // CHECK7-NEXT: store ptr null, ptr [[TMP18]], align 4 5199 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5200 // CHECK7-NEXT: store i32 [[TMP13]], ptr [[TMP19]], align 4 5201 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5202 // CHECK7-NEXT: store i32 [[TMP13]], ptr [[TMP20]], align 4 5203 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5204 // CHECK7-NEXT: store ptr null, ptr [[TMP21]], align 4 5205 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5206 // CHECK7-NEXT: store i32 [[TMP15]], ptr [[TMP22]], align 4 5207 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5208 // CHECK7-NEXT: store i32 [[TMP15]], ptr [[TMP23]], align 4 5209 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5210 // CHECK7-NEXT: store ptr null, ptr [[TMP24]], align 4 5211 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5212 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5213 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 5214 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 5215 // CHECK7-NEXT: store i32 1, ptr [[TMP27]], align 4 5216 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 5217 // CHECK7-NEXT: store i32 3, ptr [[TMP28]], align 4 5218 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 5219 // CHECK7-NEXT: store ptr [[TMP25]], ptr [[TMP29]], align 4 5220 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 5221 // CHECK7-NEXT: store ptr [[TMP26]], ptr [[TMP30]], align 4 5222 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 5223 // CHECK7-NEXT: store ptr @.offload_sizes, ptr [[TMP31]], align 4 5224 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 5225 // CHECK7-NEXT: store ptr @.offload_maptypes, ptr [[TMP32]], align 4 5226 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 5227 // CHECK7-NEXT: store ptr null, ptr [[TMP33]], align 4 5228 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 5229 // CHECK7-NEXT: store ptr null, ptr [[TMP34]], align 4 5230 // CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 5231 // CHECK7-NEXT: store i64 0, ptr [[TMP35]], align 8 5232 // CHECK7-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, ptr [[KERNEL_ARGS]]) 5233 // CHECK7-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 5234 // CHECK7-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5235 // CHECK7: omp_offload.failed: 5236 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP11]], i32 [[TMP13]], i32 [[TMP15]]) #[[ATTR4]] 5237 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 5238 // CHECK7: omp_offload.cont: 5239 // CHECK7-NEXT: [[TMP38:%.*]] = load i32, ptr [[A]], align 4 5240 // CHECK7-NEXT: store i32 [[TMP38]], ptr [[A_CASTED3]], align 4 5241 // CHECK7-NEXT: [[TMP39:%.*]] = load i32, ptr [[A_CASTED3]], align 4 5242 // CHECK7-NEXT: [[TMP40:%.*]] = load i16, ptr [[AA]], align 2 5243 // CHECK7-NEXT: store i16 [[TMP40]], ptr [[AA_CASTED4]], align 2 5244 // CHECK7-NEXT: [[TMP41:%.*]] = load i32, ptr [[AA_CASTED4]], align 4 5245 // CHECK7-NEXT: [[TMP42:%.*]] = load i32, ptr [[N_ADDR]], align 4 5246 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP42]], 10 5247 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5248 // CHECK7: omp_if.then: 5249 // CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 5250 // CHECK7-NEXT: store i32 [[TMP39]], ptr [[TMP43]], align 4 5251 // CHECK7-NEXT: [[TMP44:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 5252 // CHECK7-NEXT: store i32 [[TMP39]], ptr [[TMP44]], align 4 5253 // CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 5254 // CHECK7-NEXT: store ptr null, ptr [[TMP45]], align 4 5255 // CHECK7-NEXT: [[TMP46:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 5256 // CHECK7-NEXT: store i32 [[TMP41]], ptr [[TMP46]], align 4 5257 // CHECK7-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 5258 // CHECK7-NEXT: store i32 [[TMP41]], ptr [[TMP47]], align 4 5259 // CHECK7-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 5260 // CHECK7-NEXT: store ptr null, ptr [[TMP48]], align 4 5261 // CHECK7-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 5262 // CHECK7-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 5263 // CHECK7-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 5264 // CHECK7-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0 5265 // CHECK7-NEXT: store i32 1, ptr [[TMP51]], align 4 5266 // CHECK7-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1 5267 // CHECK7-NEXT: store i32 2, ptr [[TMP52]], align 4 5268 // CHECK7-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2 5269 // CHECK7-NEXT: store ptr [[TMP49]], ptr [[TMP53]], align 4 5270 // CHECK7-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3 5271 // CHECK7-NEXT: store ptr [[TMP50]], ptr [[TMP54]], align 4 5272 // CHECK7-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4 5273 // CHECK7-NEXT: store ptr @.offload_sizes.5, ptr [[TMP55]], align 4 5274 // CHECK7-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5 5275 // CHECK7-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP56]], align 4 5276 // CHECK7-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6 5277 // CHECK7-NEXT: store ptr null, ptr [[TMP57]], align 4 5278 // CHECK7-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7 5279 // CHECK7-NEXT: store ptr null, ptr [[TMP58]], align 4 5280 // CHECK7-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8 5281 // CHECK7-NEXT: store i64 0, ptr [[TMP59]], align 8 5282 // CHECK7-NEXT: [[TMP60:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, ptr [[KERNEL_ARGS8]]) 5283 // CHECK7-NEXT: [[TMP61:%.*]] = icmp ne i32 [[TMP60]], 0 5284 // CHECK7-NEXT: br i1 [[TMP61]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 5285 // CHECK7: omp_offload.failed9: 5286 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP39]], i32 [[TMP41]]) #[[ATTR4]] 5287 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT10]] 5288 // CHECK7: omp_offload.cont10: 5289 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 5290 // CHECK7: omp_if.else: 5291 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP39]], i32 [[TMP41]]) #[[ATTR4]] 5292 // CHECK7-NEXT: br label [[OMP_IF_END]] 5293 // CHECK7: omp_if.end: 5294 // CHECK7-NEXT: [[TMP62:%.*]] = load i32, ptr [[A]], align 4 5295 // CHECK7-NEXT: store i32 [[TMP62]], ptr [[DOTCAPTURE_EXPR_]], align 4 5296 // CHECK7-NEXT: [[TMP63:%.*]] = load i32, ptr [[A]], align 4 5297 // CHECK7-NEXT: store i32 [[TMP63]], ptr [[A_CASTED11]], align 4 5298 // CHECK7-NEXT: [[TMP64:%.*]] = load i32, ptr [[A_CASTED11]], align 4 5299 // CHECK7-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 5300 // CHECK7-NEXT: store i32 [[TMP65]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 5301 // CHECK7-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 5302 // CHECK7-NEXT: [[TMP67:%.*]] = load i32, ptr [[N_ADDR]], align 4 5303 // CHECK7-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP67]], 20 5304 // CHECK7-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]] 5305 // CHECK7: omp_if.then13: 5306 // CHECK7-NEXT: [[TMP68:%.*]] = mul nuw i32 [[TMP1]], 4 5307 // CHECK7-NEXT: [[TMP69:%.*]] = sext i32 [[TMP68]] to i64 5308 // CHECK7-NEXT: [[TMP70:%.*]] = mul nuw i32 5, [[TMP3]] 5309 // CHECK7-NEXT: [[TMP71:%.*]] = mul nuw i32 [[TMP70]], 8 5310 // CHECK7-NEXT: [[TMP72:%.*]] = sext i32 [[TMP71]] to i64 5311 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.8, i32 80, i1 false) 5312 // CHECK7-NEXT: [[TMP73:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 5313 // CHECK7-NEXT: store i32 [[TMP64]], ptr [[TMP73]], align 4 5314 // CHECK7-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 5315 // CHECK7-NEXT: store i32 [[TMP64]], ptr [[TMP74]], align 4 5316 // CHECK7-NEXT: [[TMP75:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 5317 // CHECK7-NEXT: store ptr null, ptr [[TMP75]], align 4 5318 // CHECK7-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 5319 // CHECK7-NEXT: store ptr [[B]], ptr [[TMP76]], align 4 5320 // CHECK7-NEXT: [[TMP77:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 5321 // CHECK7-NEXT: store ptr [[B]], ptr [[TMP77]], align 4 5322 // CHECK7-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 5323 // CHECK7-NEXT: store ptr null, ptr [[TMP78]], align 4 5324 // CHECK7-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 5325 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP79]], align 4 5326 // CHECK7-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 5327 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP80]], align 4 5328 // CHECK7-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 5329 // CHECK7-NEXT: store ptr null, ptr [[TMP81]], align 4 5330 // CHECK7-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 5331 // CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP82]], align 4 5332 // CHECK7-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 5333 // CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP83]], align 4 5334 // CHECK7-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 5335 // CHECK7-NEXT: store i64 [[TMP69]], ptr [[TMP84]], align 4 5336 // CHECK7-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 5337 // CHECK7-NEXT: store ptr null, ptr [[TMP85]], align 4 5338 // CHECK7-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 5339 // CHECK7-NEXT: store ptr [[C]], ptr [[TMP86]], align 4 5340 // CHECK7-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 5341 // CHECK7-NEXT: store ptr [[C]], ptr [[TMP87]], align 4 5342 // CHECK7-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 5343 // CHECK7-NEXT: store ptr null, ptr [[TMP88]], align 4 5344 // CHECK7-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 5345 // CHECK7-NEXT: store i32 5, ptr [[TMP89]], align 4 5346 // CHECK7-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 5347 // CHECK7-NEXT: store i32 5, ptr [[TMP90]], align 4 5348 // CHECK7-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 5349 // CHECK7-NEXT: store ptr null, ptr [[TMP91]], align 4 5350 // CHECK7-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 5351 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP92]], align 4 5352 // CHECK7-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 5353 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP93]], align 4 5354 // CHECK7-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 5355 // CHECK7-NEXT: store ptr null, ptr [[TMP94]], align 4 5356 // CHECK7-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 5357 // CHECK7-NEXT: store ptr [[VLA1]], ptr [[TMP95]], align 4 5358 // CHECK7-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 5359 // CHECK7-NEXT: store ptr [[VLA1]], ptr [[TMP96]], align 4 5360 // CHECK7-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 5361 // CHECK7-NEXT: store i64 [[TMP72]], ptr [[TMP97]], align 4 5362 // CHECK7-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 5363 // CHECK7-NEXT: store ptr null, ptr [[TMP98]], align 4 5364 // CHECK7-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 5365 // CHECK7-NEXT: store ptr [[D]], ptr [[TMP99]], align 4 5366 // CHECK7-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 5367 // CHECK7-NEXT: store ptr [[D]], ptr [[TMP100]], align 4 5368 // CHECK7-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 5369 // CHECK7-NEXT: store ptr null, ptr [[TMP101]], align 4 5370 // CHECK7-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 5371 // CHECK7-NEXT: store i32 [[TMP66]], ptr [[TMP102]], align 4 5372 // CHECK7-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 5373 // CHECK7-NEXT: store i32 [[TMP66]], ptr [[TMP103]], align 4 5374 // CHECK7-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 5375 // CHECK7-NEXT: store ptr null, ptr [[TMP104]], align 4 5376 // CHECK7-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 5377 // CHECK7-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 5378 // CHECK7-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5379 // CHECK7-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 5380 // CHECK7-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0 5381 // CHECK7-NEXT: store i32 1, ptr [[TMP108]], align 4 5382 // CHECK7-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1 5383 // CHECK7-NEXT: store i32 10, ptr [[TMP109]], align 4 5384 // CHECK7-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2 5385 // CHECK7-NEXT: store ptr [[TMP105]], ptr [[TMP110]], align 4 5386 // CHECK7-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3 5387 // CHECK7-NEXT: store ptr [[TMP106]], ptr [[TMP111]], align 4 5388 // CHECK7-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4 5389 // CHECK7-NEXT: store ptr [[TMP107]], ptr [[TMP112]], align 4 5390 // CHECK7-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5 5391 // CHECK7-NEXT: store ptr @.offload_maptypes.9, ptr [[TMP113]], align 4 5392 // CHECK7-NEXT: [[TMP114:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6 5393 // CHECK7-NEXT: store ptr null, ptr [[TMP114]], align 4 5394 // CHECK7-NEXT: [[TMP115:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7 5395 // CHECK7-NEXT: store ptr null, ptr [[TMP115]], align 4 5396 // CHECK7-NEXT: [[TMP116:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8 5397 // CHECK7-NEXT: store i64 0, ptr [[TMP116]], align 8 5398 // CHECK7-NEXT: [[TMP117:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, ptr [[KERNEL_ARGS17]]) 5399 // CHECK7-NEXT: [[TMP118:%.*]] = icmp ne i32 [[TMP117]], 0 5400 // CHECK7-NEXT: br i1 [[TMP118]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] 5401 // CHECK7: omp_offload.failed18: 5402 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP64]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP66]]) #[[ATTR4]] 5403 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT19]] 5404 // CHECK7: omp_offload.cont19: 5405 // CHECK7-NEXT: br label [[OMP_IF_END21:%.*]] 5406 // CHECK7: omp_if.else20: 5407 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP64]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP66]]) #[[ATTR4]] 5408 // CHECK7-NEXT: br label [[OMP_IF_END21]] 5409 // CHECK7: omp_if.end21: 5410 // CHECK7-NEXT: [[TMP119:%.*]] = load i32, ptr [[A]], align 4 5411 // CHECK7-NEXT: [[TMP120:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 5412 // CHECK7-NEXT: call void @llvm.stackrestore(ptr [[TMP120]]) 5413 // CHECK7-NEXT: ret i32 [[TMP119]] 5414 // 5415 // 5416 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 5417 // CHECK7-SAME: () #[[ATTR2:[0-9]+]] { 5418 // CHECK7-NEXT: entry: 5419 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @.omp_outlined.) 5420 // CHECK7-NEXT: ret void 5421 // 5422 // 5423 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. 5424 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 5425 // CHECK7-NEXT: entry: 5426 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 5427 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 5428 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5429 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5430 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5431 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5432 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5433 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5434 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 5435 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 5436 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 5437 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5438 // CHECK7-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 5439 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 5440 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5441 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 5442 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 5443 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 5444 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5445 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 5446 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5447 // CHECK7: cond.true: 5448 // CHECK7-NEXT: br label [[COND_END:%.*]] 5449 // CHECK7: cond.false: 5450 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5451 // CHECK7-NEXT: br label [[COND_END]] 5452 // CHECK7: cond.end: 5453 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 5454 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 5455 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5456 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 5457 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5458 // CHECK7: omp.inner.for.cond: 5459 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 5460 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 5461 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 5462 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5463 // CHECK7: omp.inner.for.body: 5464 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 5465 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 5466 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 5467 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 5468 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5469 // CHECK7: omp.body.continue: 5470 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5471 // CHECK7: omp.inner.for.inc: 5472 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 5473 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 5474 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 5475 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 5476 // CHECK7: omp.inner.for.end: 5477 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5478 // CHECK7: omp.loop.exit: 5479 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 5480 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5481 // CHECK7-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 5482 // CHECK7-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5483 // CHECK7: .omp.final.then: 5484 // CHECK7-NEXT: store i32 33, ptr [[I]], align 4 5485 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 5486 // CHECK7: .omp.final.done: 5487 // CHECK7-NEXT: ret void 5488 // 5489 // 5490 // CHECK7-LABEL: define {{[^@]+}}@.omp_task_entry. 5491 // CHECK7-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 5492 // CHECK7-NEXT: entry: 5493 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 5494 // CHECK7-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4 5495 // CHECK7-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4 5496 // CHECK7-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4 5497 // CHECK7-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4 5498 // CHECK7-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4 5499 // CHECK7-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 5500 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 5501 // CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 5502 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 5503 // CHECK7-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 5504 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 5505 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 5506 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 5507 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 5508 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 5509 // CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 5510 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 5511 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 5512 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 5513 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) 5514 // CHECK7-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 5515 // CHECK7-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias !26 5516 // CHECK7-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26 5517 // CHECK7-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26 5518 // CHECK7-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias !26 5519 // CHECK7-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !26 5520 // CHECK7-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !26 5521 // CHECK7-NEXT: store i32 1, ptr [[KERNEL_ARGS_I]], align 4, !noalias !26 5522 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 5523 // CHECK7-NEXT: store i32 0, ptr [[TMP9]], align 4, !noalias !26 5524 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 5525 // CHECK7-NEXT: store ptr null, ptr [[TMP10]], align 4, !noalias !26 5526 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 5527 // CHECK7-NEXT: store ptr null, ptr [[TMP11]], align 4, !noalias !26 5528 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 5529 // CHECK7-NEXT: store ptr null, ptr [[TMP12]], align 4, !noalias !26 5530 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 5531 // CHECK7-NEXT: store ptr null, ptr [[TMP13]], align 4, !noalias !26 5532 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 5533 // CHECK7-NEXT: store ptr null, ptr [[TMP14]], align 4, !noalias !26 5534 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 5535 // CHECK7-NEXT: store ptr null, ptr [[TMP15]], align 4, !noalias !26 5536 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 5537 // CHECK7-NEXT: store i64 0, ptr [[TMP16]], align 8, !noalias !26 5538 // CHECK7-NEXT: [[TMP17:%.*]] = call i32 @__tgt_target_kernel_nowait(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, ptr [[KERNEL_ARGS_I]], i32 0, ptr null, i32 0, ptr null) 5539 // CHECK7-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 5540 // CHECK7-NEXT: br i1 [[TMP18]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 5541 // CHECK7: omp_offload.failed.i: 5542 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] 5543 // CHECK7-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 5544 // CHECK7: .omp_outlined..1.exit: 5545 // CHECK7-NEXT: ret i32 0 5546 // 5547 // 5548 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 5549 // CHECK7-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 5550 // CHECK7-NEXT: entry: 5551 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5552 // CHECK7-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4 5553 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5554 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5555 // CHECK7-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4 5556 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4 5557 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 5558 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 5559 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 5560 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..2, i32 [[TMP2]], ptr [[TMP0]]) 5561 // CHECK7-NEXT: ret void 5562 // 5563 // 5564 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 5565 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 5566 // CHECK7-NEXT: entry: 5567 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 5568 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 5569 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5570 // CHECK7-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4 5571 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5572 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5573 // CHECK7-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 5574 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5575 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5576 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5577 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5578 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 5579 // CHECK7-NEXT: [[K1:%.*]] = alloca i64, align 8 5580 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 5581 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 5582 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5583 // CHECK7-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4 5584 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4 5585 // CHECK7-NEXT: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 8 5586 // CHECK7-NEXT: store i64 [[TMP1]], ptr [[DOTLINEAR_START]], align 8 5587 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5588 // CHECK7-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 4 5589 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 5590 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5591 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 5592 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 5593 // CHECK7-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 5594 // CHECK7-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 5595 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 5596 // CHECK7: omp.dispatch.cond: 5597 // CHECK7-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]) 5598 // CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 5599 // CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 5600 // CHECK7: omp.dispatch.body: 5601 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5602 // CHECK7-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 5603 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5604 // CHECK7: omp.inner.for.cond: 5605 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] 5606 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] 5607 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 5608 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5609 // CHECK7: omp.inner.for.body: 5610 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 5611 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 5612 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 5613 // CHECK7-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] 5614 // CHECK7-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP27]] 5615 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 5616 // CHECK7-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 5617 // CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 5618 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 5619 // CHECK7-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP27]] 5620 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 5621 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 5622 // CHECK7-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 5623 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5624 // CHECK7: omp.body.continue: 5625 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5626 // CHECK7: omp.inner.for.inc: 5627 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 5628 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 5629 // CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 5630 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 5631 // CHECK7: omp.inner.for.end: 5632 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 5633 // CHECK7: omp.dispatch.inc: 5634 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] 5635 // CHECK7: omp.dispatch.end: 5636 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5637 // CHECK7-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 5638 // CHECK7-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5639 // CHECK7: .omp.final.then: 5640 // CHECK7-NEXT: store i32 1, ptr [[I]], align 4 5641 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 5642 // CHECK7: .omp.final.done: 5643 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5644 // CHECK7-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 5645 // CHECK7-NEXT: br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 5646 // CHECK7: .omp.linear.pu: 5647 // CHECK7-NEXT: [[TMP17:%.*]] = load i64, ptr [[K1]], align 8 5648 // CHECK7-NEXT: store i64 [[TMP17]], ptr [[TMP0]], align 8 5649 // CHECK7-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 5650 // CHECK7: .omp.linear.pu.done: 5651 // CHECK7-NEXT: ret void 5652 // 5653 // 5654 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 5655 // CHECK7-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 5656 // CHECK7-NEXT: entry: 5657 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5658 // CHECK7-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 5659 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5660 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5661 // CHECK7-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 5662 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5663 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 5664 // CHECK7-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 5665 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5666 // CHECK7-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 5667 // CHECK7-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 5668 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 5669 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 5670 // CHECK7-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 5671 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 5672 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 5673 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 5674 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4 5675 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..3, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 5676 // CHECK7-NEXT: ret void 5677 // 5678 // 5679 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 5680 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 5681 // CHECK7-NEXT: entry: 5682 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 5683 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 5684 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5685 // CHECK7-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 5686 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5687 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5688 // CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 5689 // CHECK7-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 5690 // CHECK7-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 5691 // CHECK7-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 5692 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5693 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5694 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5695 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5696 // CHECK7-NEXT: [[IT:%.*]] = alloca i64, align 8 5697 // CHECK7-NEXT: [[LIN2:%.*]] = alloca i32, align 4 5698 // CHECK7-NEXT: [[A3:%.*]] = alloca i32, align 4 5699 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 5700 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 5701 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 5702 // CHECK7-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 5703 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5704 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 5705 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 5706 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 5707 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 5708 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 5709 // CHECK7-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 5710 // CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 5711 // CHECK7-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 5712 // CHECK7-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 5713 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5714 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 5715 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 5716 // CHECK7-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]]) 5717 // CHECK7-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 5718 // CHECK7-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5719 // CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 5720 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5721 // CHECK7: cond.true: 5722 // CHECK7-NEXT: br label [[COND_END:%.*]] 5723 // CHECK7: cond.false: 5724 // CHECK7-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5725 // CHECK7-NEXT: br label [[COND_END]] 5726 // CHECK7: cond.end: 5727 // CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 5728 // CHECK7-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 5729 // CHECK7-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 5730 // CHECK7-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 5731 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5732 // CHECK7: omp.inner.for.cond: 5733 // CHECK7-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30:![0-9]+]] 5734 // CHECK7-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP30]] 5735 // CHECK7-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 5736 // CHECK7-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5737 // CHECK7: omp.inner.for.body: 5738 // CHECK7-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 5739 // CHECK7-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 5740 // CHECK7-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 5741 // CHECK7-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP30]] 5742 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP30]] 5743 // CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 5744 // CHECK7-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 5745 // CHECK7-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]] 5746 // CHECK7-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 5747 // CHECK7-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 5748 // CHECK7-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 5749 // CHECK7-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP30]] 5750 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP30]] 5751 // CHECK7-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 5752 // CHECK7-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 5753 // CHECK7-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]] 5754 // CHECK7-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 5755 // CHECK7-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 5756 // CHECK7-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 5757 // CHECK7-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP30]] 5758 // CHECK7-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] 5759 // CHECK7-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 5760 // CHECK7-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 5761 // CHECK7-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 5762 // CHECK7-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] 5763 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5764 // CHECK7: omp.body.continue: 5765 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5766 // CHECK7: omp.inner.for.inc: 5767 // CHECK7-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 5768 // CHECK7-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 5769 // CHECK7-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 5770 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 5771 // CHECK7: omp.inner.for.end: 5772 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5773 // CHECK7: omp.loop.exit: 5774 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 5775 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5776 // CHECK7-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 5777 // CHECK7-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5778 // CHECK7: .omp.final.then: 5779 // CHECK7-NEXT: store i64 400, ptr [[IT]], align 8 5780 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 5781 // CHECK7: .omp.final.done: 5782 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5783 // CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 5784 // CHECK7-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 5785 // CHECK7: .omp.linear.pu: 5786 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 5787 // CHECK7-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 5788 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 5789 // CHECK7-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 5790 // CHECK7-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 5791 // CHECK7: .omp.linear.pu.done: 5792 // CHECK7-NEXT: ret void 5793 // 5794 // 5795 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 5796 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 5797 // CHECK7-NEXT: entry: 5798 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5799 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5800 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5801 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5802 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5803 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 5804 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 5805 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 5806 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 5807 // CHECK7-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 5808 // CHECK7-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 5809 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 5810 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..4, i32 [[TMP1]], i32 [[TMP3]]) 5811 // CHECK7-NEXT: ret void 5812 // 5813 // 5814 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 5815 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 5816 // CHECK7-NEXT: entry: 5817 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 5818 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 5819 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5820 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5821 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5822 // CHECK7-NEXT: [[TMP:%.*]] = alloca i16, align 2 5823 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5824 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5825 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5826 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5827 // CHECK7-NEXT: [[IT:%.*]] = alloca i16, align 2 5828 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 5829 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 5830 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5831 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 5832 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5833 // CHECK7-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 5834 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 5835 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5836 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 5837 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 5838 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 5839 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5840 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 5841 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5842 // CHECK7: cond.true: 5843 // CHECK7-NEXT: br label [[COND_END:%.*]] 5844 // CHECK7: cond.false: 5845 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5846 // CHECK7-NEXT: br label [[COND_END]] 5847 // CHECK7: cond.end: 5848 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 5849 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 5850 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5851 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 5852 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5853 // CHECK7: omp.inner.for.cond: 5854 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] 5855 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] 5856 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 5857 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5858 // CHECK7: omp.inner.for.body: 5859 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 5860 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 5861 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 5862 // CHECK7-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 5863 // CHECK7-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP33]] 5864 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 5865 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 5866 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 5867 // CHECK7-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] 5868 // CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 5869 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 5870 // CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 5871 // CHECK7-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] 5872 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5873 // CHECK7: omp.body.continue: 5874 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5875 // CHECK7: omp.inner.for.inc: 5876 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 5877 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 5878 // CHECK7-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 5879 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 5880 // CHECK7: omp.inner.for.end: 5881 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5882 // CHECK7: omp.loop.exit: 5883 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 5884 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5885 // CHECK7-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 5886 // CHECK7-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5887 // CHECK7: .omp.final.then: 5888 // CHECK7-NEXT: store i16 22, ptr [[IT]], align 2 5889 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 5890 // CHECK7: .omp.final.done: 5891 // CHECK7-NEXT: ret void 5892 // 5893 // 5894 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 5895 // CHECK7-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 5896 // CHECK7-NEXT: entry: 5897 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5898 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 5899 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5900 // CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 5901 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 5902 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5903 // CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 5904 // CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 5905 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 5906 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 5907 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5908 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 5909 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5910 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 5911 // CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 5912 // CHECK7-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 5913 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 5914 // CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 5915 // CHECK7-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 5916 // CHECK7-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 5917 // CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 5918 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 5919 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 5920 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 5921 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 5922 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 5923 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 5924 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 5925 // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 5926 // CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 5927 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 5928 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 5929 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 5930 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 5931 // CHECK7-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 5932 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 5933 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @.omp_outlined..7, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]]) 5934 // CHECK7-NEXT: ret void 5935 // 5936 // 5937 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 5938 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 5939 // CHECK7-NEXT: entry: 5940 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 5941 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 5942 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5943 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 5944 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5945 // CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 5946 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 5947 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5948 // CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 5949 // CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 5950 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 5951 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 5952 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5953 // CHECK7-NEXT: [[TMP:%.*]] = alloca i8, align 1 5954 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5955 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5956 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5957 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5958 // CHECK7-NEXT: [[IT:%.*]] = alloca i8, align 1 5959 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 5960 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 5961 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5962 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 5963 // CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 5964 // CHECK7-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 5965 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 5966 // CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 5967 // CHECK7-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 5968 // CHECK7-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 5969 // CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 5970 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 5971 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 5972 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 5973 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 5974 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 5975 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 5976 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 5977 // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 5978 // CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 5979 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5980 // CHECK7-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 5981 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 5982 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5983 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 5984 // CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 5985 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 5986 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 5987 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 5988 // CHECK7: omp.dispatch.cond: 5989 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5990 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 5991 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5992 // CHECK7: cond.true: 5993 // CHECK7-NEXT: br label [[COND_END:%.*]] 5994 // CHECK7: cond.false: 5995 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5996 // CHECK7-NEXT: br label [[COND_END]] 5997 // CHECK7: cond.end: 5998 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 5999 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 6000 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6001 // CHECK7-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 6002 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 6003 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6004 // CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 6005 // CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6006 // CHECK7: omp.dispatch.body: 6007 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6008 // CHECK7: omp.inner.for.cond: 6009 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] 6010 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]] 6011 // CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 6012 // CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6013 // CHECK7: omp.inner.for.body: 6014 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 6015 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 6016 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 6017 // CHECK7-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 6018 // CHECK7-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP36]] 6019 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] 6020 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 6021 // CHECK7-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] 6022 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 6023 // CHECK7-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] 6024 // CHECK7-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 6025 // CHECK7-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 6026 // CHECK7-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 6027 // CHECK7-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] 6028 // CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 6029 // CHECK7-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]] 6030 // CHECK7-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 6031 // CHECK7-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 6032 // CHECK7-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 6033 // CHECK7-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]] 6034 // CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 6035 // CHECK7-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 6036 // CHECK7-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] 6037 // CHECK7-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 6038 // CHECK7-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] 6039 // CHECK7-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 6040 // CHECK7-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]] 6041 // CHECK7-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3 6042 // CHECK7-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]] 6043 // CHECK7-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 6044 // CHECK7-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]] 6045 // CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 6046 // CHECK7-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]] 6047 // CHECK7-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 6048 // CHECK7-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]] 6049 // CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 6050 // CHECK7-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]] 6051 // CHECK7-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 6052 // CHECK7-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 6053 // CHECK7-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 6054 // CHECK7-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]] 6055 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6056 // CHECK7: omp.body.continue: 6057 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6058 // CHECK7: omp.inner.for.inc: 6059 // CHECK7-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 6060 // CHECK7-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 6061 // CHECK7-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 6062 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] 6063 // CHECK7: omp.inner.for.end: 6064 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6065 // CHECK7: omp.dispatch.inc: 6066 // CHECK7-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6067 // CHECK7-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 6068 // CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 6069 // CHECK7-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 6070 // CHECK7-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6071 // CHECK7-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 6072 // CHECK7-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 6073 // CHECK7-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 6074 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] 6075 // CHECK7: omp.dispatch.end: 6076 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 6077 // CHECK7-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 6078 // CHECK7-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 6079 // CHECK7-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6080 // CHECK7: .omp.final.then: 6081 // CHECK7-NEXT: store i8 96, ptr [[IT]], align 1 6082 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6083 // CHECK7: .omp.final.done: 6084 // CHECK7-NEXT: ret void 6085 // 6086 // 6087 // CHECK7-LABEL: define {{[^@]+}}@_Z3bari 6088 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 6089 // CHECK7-NEXT: entry: 6090 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6091 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6092 // CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 6093 // CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 6094 // CHECK7-NEXT: store i32 0, ptr [[A]], align 4 6095 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 6096 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 6097 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 6098 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6099 // CHECK7-NEXT: store i32 [[ADD]], ptr [[A]], align 4 6100 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 6101 // CHECK7-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 6102 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 6103 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6104 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 6105 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 6106 // CHECK7-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 6107 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 6108 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6109 // CHECK7-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 6110 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 6111 // CHECK7-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 6112 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 6113 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 6114 // CHECK7-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 6115 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 6116 // CHECK7-NEXT: ret i32 [[TMP8]] 6117 // 6118 // 6119 // CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6120 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6121 // CHECK7-NEXT: entry: 6122 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 6123 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6124 // CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 6125 // CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 6126 // CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 6127 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 6128 // CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6129 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 6130 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x ptr], align 4 6131 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x ptr], align 4 6132 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x ptr], align 4 6133 // CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 4 6134 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 6135 // CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 6136 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 6137 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 6138 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6139 // CHECK7-NEXT: store i32 [[ADD]], ptr [[B]], align 4 6140 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 6141 // CHECK7-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() 6142 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 6143 // CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 6144 // CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 6145 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 6146 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 6147 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 6148 // CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 6149 // CHECK7-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 6150 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 6151 // CHECK7-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 6152 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4 6153 // CHECK7-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 6154 // CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 6155 // CHECK7-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8 6156 // CHECK7-NEXT: store i8 [[FROMBOOL2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 6157 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 6158 // CHECK7-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 6159 // CHECK7-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1 6160 // CHECK7-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6161 // CHECK7: omp_if.then: 6162 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 6163 // CHECK7-NEXT: [[TMP10:%.*]] = mul nuw i32 2, [[TMP1]] 6164 // CHECK7-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 2 6165 // CHECK7-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 6166 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.11, i32 48, i1 false) 6167 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6168 // CHECK7-NEXT: store ptr [[THIS1]], ptr [[TMP13]], align 4 6169 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6170 // CHECK7-NEXT: store ptr [[A]], ptr [[TMP14]], align 4 6171 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6172 // CHECK7-NEXT: store ptr null, ptr [[TMP15]], align 4 6173 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6174 // CHECK7-NEXT: store i32 [[TMP6]], ptr [[TMP16]], align 4 6175 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6176 // CHECK7-NEXT: store i32 [[TMP6]], ptr [[TMP17]], align 4 6177 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6178 // CHECK7-NEXT: store ptr null, ptr [[TMP18]], align 4 6179 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6180 // CHECK7-NEXT: store i32 2, ptr [[TMP19]], align 4 6181 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6182 // CHECK7-NEXT: store i32 2, ptr [[TMP20]], align 4 6183 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6184 // CHECK7-NEXT: store ptr null, ptr [[TMP21]], align 4 6185 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6186 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP22]], align 4 6187 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6188 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP23]], align 4 6189 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 6190 // CHECK7-NEXT: store ptr null, ptr [[TMP24]], align 4 6191 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 6192 // CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP25]], align 4 6193 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 6194 // CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP26]], align 4 6195 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 6196 // CHECK7-NEXT: store i64 [[TMP12]], ptr [[TMP27]], align 4 6197 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 6198 // CHECK7-NEXT: store ptr null, ptr [[TMP28]], align 4 6199 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 6200 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[TMP29]], align 4 6201 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5 6202 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[TMP30]], align 4 6203 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 6204 // CHECK7-NEXT: store ptr null, ptr [[TMP31]], align 4 6205 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6206 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6207 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 6208 // CHECK7-NEXT: [[TMP35:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 6209 // CHECK7-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP35]] to i1 6210 // CHECK7-NEXT: [[TMP36:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 6211 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 6212 // CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 6213 // CHECK7-NEXT: store i32 1, ptr [[TMP37]], align 4 6214 // CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 6215 // CHECK7-NEXT: store i32 6, ptr [[TMP38]], align 4 6216 // CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 6217 // CHECK7-NEXT: store ptr [[TMP32]], ptr [[TMP39]], align 4 6218 // CHECK7-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 6219 // CHECK7-NEXT: store ptr [[TMP33]], ptr [[TMP40]], align 4 6220 // CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 6221 // CHECK7-NEXT: store ptr [[TMP34]], ptr [[TMP41]], align 4 6222 // CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 6223 // CHECK7-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP42]], align 4 6224 // CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 6225 // CHECK7-NEXT: store ptr null, ptr [[TMP43]], align 4 6226 // CHECK7-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 6227 // CHECK7-NEXT: store ptr null, ptr [[TMP44]], align 4 6228 // CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 6229 // CHECK7-NEXT: store i64 0, ptr [[TMP45]], align 8 6230 // CHECK7-NEXT: [[TMP46:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 [[TMP36]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, ptr [[KERNEL_ARGS]]) 6231 // CHECK7-NEXT: [[TMP47:%.*]] = icmp ne i32 [[TMP46]], 0 6232 // CHECK7-NEXT: br i1 [[TMP47]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6233 // CHECK7: omp_offload.failed: 6234 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR4]] 6235 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 6236 // CHECK7: omp_offload.cont: 6237 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6238 // CHECK7: omp_if.else: 6239 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR4]] 6240 // CHECK7-NEXT: br label [[OMP_IF_END]] 6241 // CHECK7: omp_if.end: 6242 // CHECK7-NEXT: [[TMP48:%.*]] = mul nsw i32 1, [[TMP1]] 6243 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP48]] 6244 // CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 6245 // CHECK7-NEXT: [[TMP49:%.*]] = load i16, ptr [[ARRAYIDX5]], align 2 6246 // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP49]] to i32 6247 // CHECK7-NEXT: [[TMP50:%.*]] = load i32, ptr [[B]], align 4 6248 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV]], [[TMP50]] 6249 // CHECK7-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 6250 // CHECK7-NEXT: call void @llvm.stackrestore(ptr [[TMP51]]) 6251 // CHECK7-NEXT: ret i32 [[ADD6]] 6252 // 6253 // 6254 // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici 6255 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 6256 // CHECK7-NEXT: entry: 6257 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6258 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6259 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 6260 // CHECK7-NEXT: [[AAA:%.*]] = alloca i8, align 1 6261 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6262 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6263 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6264 // CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 6265 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 6266 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 6267 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 6268 // CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 6269 // CHECK7-NEXT: store i32 0, ptr [[A]], align 4 6270 // CHECK7-NEXT: store i16 0, ptr [[AA]], align 2 6271 // CHECK7-NEXT: store i8 0, ptr [[AAA]], align 1 6272 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 6273 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 6274 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 6275 // CHECK7-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 6276 // CHECK7-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 6277 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 6278 // CHECK7-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1 6279 // CHECK7-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1 6280 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 6281 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 6282 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 6283 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6284 // CHECK7: omp_if.then: 6285 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6286 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 4 6287 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6288 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 4 6289 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6290 // CHECK7-NEXT: store ptr null, ptr [[TMP9]], align 4 6291 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6292 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP10]], align 4 6293 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6294 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP11]], align 4 6295 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6296 // CHECK7-NEXT: store ptr null, ptr [[TMP12]], align 4 6297 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6298 // CHECK7-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 4 6299 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6300 // CHECK7-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 4 6301 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6302 // CHECK7-NEXT: store ptr null, ptr [[TMP15]], align 4 6303 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6304 // CHECK7-NEXT: store ptr [[B]], ptr [[TMP16]], align 4 6305 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6306 // CHECK7-NEXT: store ptr [[B]], ptr [[TMP17]], align 4 6307 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 6308 // CHECK7-NEXT: store ptr null, ptr [[TMP18]], align 4 6309 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6310 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6311 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 6312 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 6313 // CHECK7-NEXT: store i32 1, ptr [[TMP21]], align 4 6314 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 6315 // CHECK7-NEXT: store i32 4, ptr [[TMP22]], align 4 6316 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 6317 // CHECK7-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4 6318 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 6319 // CHECK7-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4 6320 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 6321 // CHECK7-NEXT: store ptr @.offload_sizes.14, ptr [[TMP25]], align 4 6322 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 6323 // CHECK7-NEXT: store ptr @.offload_maptypes.15, ptr [[TMP26]], align 4 6324 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 6325 // CHECK7-NEXT: store ptr null, ptr [[TMP27]], align 4 6326 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 6327 // CHECK7-NEXT: store ptr null, ptr [[TMP28]], align 4 6328 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 6329 // CHECK7-NEXT: store i64 0, ptr [[TMP29]], align 8 6330 // CHECK7-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, ptr [[KERNEL_ARGS]]) 6331 // CHECK7-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 6332 // CHECK7-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6333 // CHECK7: omp_offload.failed: 6334 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]] 6335 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 6336 // CHECK7: omp_offload.cont: 6337 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6338 // CHECK7: omp_if.else: 6339 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]] 6340 // CHECK7-NEXT: br label [[OMP_IF_END]] 6341 // CHECK7: omp_if.end: 6342 // CHECK7-NEXT: [[TMP32:%.*]] = load i32, ptr [[A]], align 4 6343 // CHECK7-NEXT: ret i32 [[TMP32]] 6344 // 6345 // 6346 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6347 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 6348 // CHECK7-NEXT: entry: 6349 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6350 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6351 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 6352 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6353 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6354 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6355 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 6356 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 6357 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 6358 // CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 6359 // CHECK7-NEXT: store i32 0, ptr [[A]], align 4 6360 // CHECK7-NEXT: store i16 0, ptr [[AA]], align 2 6361 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 6362 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 6363 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 6364 // CHECK7-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 6365 // CHECK7-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 6366 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 6367 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 6368 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 6369 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6370 // CHECK7: omp_if.then: 6371 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6372 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 6373 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6374 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 4 6375 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6376 // CHECK7-NEXT: store ptr null, ptr [[TMP7]], align 4 6377 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6378 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 4 6379 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6380 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP9]], align 4 6381 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6382 // CHECK7-NEXT: store ptr null, ptr [[TMP10]], align 4 6383 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6384 // CHECK7-NEXT: store ptr [[B]], ptr [[TMP11]], align 4 6385 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6386 // CHECK7-NEXT: store ptr [[B]], ptr [[TMP12]], align 4 6387 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6388 // CHECK7-NEXT: store ptr null, ptr [[TMP13]], align 4 6389 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6390 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6391 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 6392 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 6393 // CHECK7-NEXT: store i32 1, ptr [[TMP16]], align 4 6394 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 6395 // CHECK7-NEXT: store i32 3, ptr [[TMP17]], align 4 6396 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 6397 // CHECK7-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4 6398 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 6399 // CHECK7-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 4 6400 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 6401 // CHECK7-NEXT: store ptr @.offload_sizes.17, ptr [[TMP20]], align 4 6402 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 6403 // CHECK7-NEXT: store ptr @.offload_maptypes.18, ptr [[TMP21]], align 4 6404 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 6405 // CHECK7-NEXT: store ptr null, ptr [[TMP22]], align 4 6406 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 6407 // CHECK7-NEXT: store ptr null, ptr [[TMP23]], align 4 6408 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 6409 // CHECK7-NEXT: store i64 0, ptr [[TMP24]], align 8 6410 // CHECK7-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, ptr [[KERNEL_ARGS]]) 6411 // CHECK7-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 6412 // CHECK7-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6413 // CHECK7: omp_offload.failed: 6414 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] 6415 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 6416 // CHECK7: omp_offload.cont: 6417 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6418 // CHECK7: omp_if.else: 6419 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] 6420 // CHECK7-NEXT: br label [[OMP_IF_END]] 6421 // CHECK7: omp_if.end: 6422 // CHECK7-NEXT: [[TMP27:%.*]] = load i32, ptr [[A]], align 4 6423 // CHECK7-NEXT: ret i32 [[TMP27]] 6424 // 6425 // 6426 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 6427 // CHECK7-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 6428 // CHECK7-NEXT: entry: 6429 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 6430 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6431 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6432 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6433 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 6434 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6435 // CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6436 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 6437 // CHECK7-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 6438 // CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 6439 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 6440 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 6441 // CHECK7-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 6442 // CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 6443 // CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 6444 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 6445 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 6446 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 6447 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 6448 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 6449 // CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 4 6450 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4 6451 // CHECK7-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 6452 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4 6453 // CHECK7-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 6454 // CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 6455 // CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 6456 // CHECK7-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 6457 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 6458 // CHECK7-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 6459 // CHECK7-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1 6460 // CHECK7-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6461 // CHECK7: omp_if.then: 6462 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @.omp_outlined..10, ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) 6463 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6464 // CHECK7: omp_if.else: 6465 // CHECK7-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 6466 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 6467 // CHECK7-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 6468 // CHECK7-NEXT: call void @.omp_outlined..10(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) #[[ATTR4]] 6469 // CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 6470 // CHECK7-NEXT: br label [[OMP_IF_END]] 6471 // CHECK7: omp_if.end: 6472 // CHECK7-NEXT: ret void 6473 // 6474 // 6475 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10 6476 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 6477 // CHECK7-NEXT: entry: 6478 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 6479 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 6480 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 6481 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6482 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6483 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6484 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 6485 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6486 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6487 // CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 6488 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6489 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6490 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6491 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6492 // CHECK7-NEXT: [[IT:%.*]] = alloca i64, align 8 6493 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 6494 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 6495 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 6496 // CHECK7-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 6497 // CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 6498 // CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 6499 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 6500 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 6501 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 6502 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 6503 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 6504 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 6505 // CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 6506 // CHECK7-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 6507 // CHECK7-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 6508 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 6509 // CHECK7-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 6510 // CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 6511 // CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6512 // CHECK7: omp_if.then: 6513 // CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6514 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 6515 // CHECK7-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 6516 // CHECK7-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6517 // CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 6518 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6519 // CHECK7: cond.true: 6520 // CHECK7-NEXT: br label [[COND_END:%.*]] 6521 // CHECK7: cond.false: 6522 // CHECK7-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6523 // CHECK7-NEXT: br label [[COND_END]] 6524 // CHECK7: cond.end: 6525 // CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 6526 // CHECK7-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 6527 // CHECK7-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 6528 // CHECK7-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV]], align 8 6529 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6530 // CHECK7: omp.inner.for.cond: 6531 // CHECK7-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39:![0-9]+]] 6532 // CHECK7-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP39]] 6533 // CHECK7-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 6534 // CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6535 // CHECK7: omp.inner.for.body: 6536 // CHECK7-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 6537 // CHECK7-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 6538 // CHECK7-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 6539 // CHECK7-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP39]] 6540 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]] 6541 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double 6542 // CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 6543 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 6544 // CHECK7-NEXT: store double [[ADD]], ptr [[A]], align 4, !nontemporal !40, !llvm.access.group [[ACC_GRP39]] 6545 // CHECK7-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 6546 // CHECK7-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 4, !nontemporal !40, !llvm.access.group [[ACC_GRP39]] 6547 // CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 6548 // CHECK7-NEXT: store double [[INC]], ptr [[A4]], align 4, !nontemporal !40, !llvm.access.group [[ACC_GRP39]] 6549 // CHECK7-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 6550 // CHECK7-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]] 6551 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP15]] 6552 // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 6553 // CHECK7-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP39]] 6554 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6555 // CHECK7: omp.body.continue: 6556 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6557 // CHECK7: omp.inner.for.inc: 6558 // CHECK7-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 6559 // CHECK7-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1 6560 // CHECK7-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 6561 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] 6562 // CHECK7: omp.inner.for.end: 6563 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6564 // CHECK7: omp_if.else: 6565 // CHECK7-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6566 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 6567 // CHECK7-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP18]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 6568 // CHECK7-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6569 // CHECK7-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[TMP19]], 3 6570 // CHECK7-NEXT: br i1 [[CMP8]], label [[COND_TRUE9:%.*]], label [[COND_FALSE10:%.*]] 6571 // CHECK7: cond.true9: 6572 // CHECK7-NEXT: br label [[COND_END11:%.*]] 6573 // CHECK7: cond.false10: 6574 // CHECK7-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6575 // CHECK7-NEXT: br label [[COND_END11]] 6576 // CHECK7: cond.end11: 6577 // CHECK7-NEXT: [[COND12:%.*]] = phi i64 [ 3, [[COND_TRUE9]] ], [ [[TMP20]], [[COND_FALSE10]] ] 6578 // CHECK7-NEXT: store i64 [[COND12]], ptr [[DOTOMP_UB]], align 8 6579 // CHECK7-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 6580 // CHECK7-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV]], align 8 6581 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 6582 // CHECK7: omp.inner.for.cond13: 6583 // CHECK7-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 6584 // CHECK7-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6585 // CHECK7-NEXT: [[CMP14:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 6586 // CHECK7-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END29:%.*]] 6587 // CHECK7: omp.inner.for.body15: 6588 // CHECK7-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 6589 // CHECK7-NEXT: [[MUL16:%.*]] = mul i64 [[TMP24]], 400 6590 // CHECK7-NEXT: [[SUB17:%.*]] = sub i64 2000, [[MUL16]] 6591 // CHECK7-NEXT: store i64 [[SUB17]], ptr [[IT]], align 8 6592 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, ptr [[B_ADDR]], align 4 6593 // CHECK7-NEXT: [[CONV18:%.*]] = sitofp i32 [[TMP25]] to double 6594 // CHECK7-NEXT: [[ADD19:%.*]] = fadd double [[CONV18]], 1.500000e+00 6595 // CHECK7-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 6596 // CHECK7-NEXT: store double [[ADD19]], ptr [[A20]], align 4 6597 // CHECK7-NEXT: [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 6598 // CHECK7-NEXT: [[TMP26:%.*]] = load double, ptr [[A21]], align 4 6599 // CHECK7-NEXT: [[INC22:%.*]] = fadd double [[TMP26]], 1.000000e+00 6600 // CHECK7-NEXT: store double [[INC22]], ptr [[A21]], align 4 6601 // CHECK7-NEXT: [[CONV23:%.*]] = fptosi double [[INC22]] to i16 6602 // CHECK7-NEXT: [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]] 6603 // CHECK7-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP27]] 6604 // CHECK7-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX24]], i32 1 6605 // CHECK7-NEXT: store i16 [[CONV23]], ptr [[ARRAYIDX25]], align 2 6606 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] 6607 // CHECK7: omp.body.continue26: 6608 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] 6609 // CHECK7: omp.inner.for.inc27: 6610 // CHECK7-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 6611 // CHECK7-NEXT: [[ADD28:%.*]] = add i64 [[TMP28]], 1 6612 // CHECK7-NEXT: store i64 [[ADD28]], ptr [[DOTOMP_IV]], align 8 6613 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP43:![0-9]+]] 6614 // CHECK7: omp.inner.for.end29: 6615 // CHECK7-NEXT: br label [[OMP_IF_END]] 6616 // CHECK7: omp_if.end: 6617 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6618 // CHECK7: omp.loop.exit: 6619 // CHECK7-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6620 // CHECK7-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4 6621 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]]) 6622 // CHECK7-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 6623 // CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 6624 // CHECK7-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6625 // CHECK7: .omp.final.then: 6626 // CHECK7-NEXT: store i64 400, ptr [[IT]], align 8 6627 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6628 // CHECK7: .omp.final.done: 6629 // CHECK7-NEXT: ret void 6630 // 6631 // 6632 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 6633 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6634 // CHECK7-NEXT: entry: 6635 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6636 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6637 // CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 6638 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6639 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6640 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6641 // CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 6642 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6643 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 6644 // CHECK7-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 6645 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6646 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 6647 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 6648 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 6649 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 6650 // CHECK7-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 6651 // CHECK7-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 6652 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 6653 // CHECK7-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 6654 // CHECK7-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 6655 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 6656 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @.omp_outlined..13, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]]) 6657 // CHECK7-NEXT: ret void 6658 // 6659 // 6660 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..13 6661 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 6662 // CHECK7-NEXT: entry: 6663 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 6664 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 6665 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6666 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6667 // CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 6668 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6669 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6670 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 6671 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 6672 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 6673 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6674 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 6675 // CHECK7-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 6676 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6677 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 6678 // CHECK7-NEXT: ret void 6679 // 6680 // 6681 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 6682 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6683 // CHECK7-NEXT: entry: 6684 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6685 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6686 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6687 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6688 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6689 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6690 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 6691 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6692 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 6693 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 6694 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 6695 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 6696 // CHECK7-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 6697 // CHECK7-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 6698 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 6699 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..16, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) 6700 // CHECK7-NEXT: ret void 6701 // 6702 // 6703 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..16 6704 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 6705 // CHECK7-NEXT: entry: 6706 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 6707 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 6708 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6709 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6710 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6711 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6712 // CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 6713 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6714 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6715 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6716 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6717 // CHECK7-NEXT: [[I:%.*]] = alloca i64, align 8 6718 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 6719 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 6720 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6721 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 6722 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6723 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 6724 // CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 6725 // CHECK7-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 6726 // CHECK7-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 6727 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 6728 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6729 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 6730 // CHECK7-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 6731 // CHECK7-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6732 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 6733 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6734 // CHECK7: cond.true: 6735 // CHECK7-NEXT: br label [[COND_END:%.*]] 6736 // CHECK7: cond.false: 6737 // CHECK7-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6738 // CHECK7-NEXT: br label [[COND_END]] 6739 // CHECK7: cond.end: 6740 // CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 6741 // CHECK7-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 6742 // CHECK7-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 6743 // CHECK7-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 6744 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6745 // CHECK7: omp.inner.for.cond: 6746 // CHECK7-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45:![0-9]+]] 6747 // CHECK7-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP45]] 6748 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 6749 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6750 // CHECK7: omp.inner.for.body: 6751 // CHECK7-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45]] 6752 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 6753 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 6754 // CHECK7-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP45]] 6755 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]] 6756 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 6757 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]] 6758 // CHECK7-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]] 6759 // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 6760 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 6761 // CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 6762 // CHECK7-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]] 6763 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 6764 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] 6765 // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 6766 // CHECK7-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] 6767 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6768 // CHECK7: omp.body.continue: 6769 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6770 // CHECK7: omp.inner.for.inc: 6771 // CHECK7-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45]] 6772 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 6773 // CHECK7-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45]] 6774 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] 6775 // CHECK7: omp.inner.for.end: 6776 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6777 // CHECK7: omp.loop.exit: 6778 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 6779 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 6780 // CHECK7-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 6781 // CHECK7-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6782 // CHECK7: .omp.final.then: 6783 // CHECK7-NEXT: store i64 11, ptr [[I]], align 8 6784 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6785 // CHECK7: .omp.final.done: 6786 // CHECK7-NEXT: ret void 6787 // 6788 // 6789 // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 6790 // CHECK7-SAME: () #[[ATTR8:[0-9]+]] { 6791 // CHECK7-NEXT: entry: 6792 // CHECK7-NEXT: call void @__tgt_register_requires(i64 1) 6793 // CHECK7-NEXT: ret void 6794 // 6795 // 6796 // CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv 6797 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 6798 // CHECK9-NEXT: entry: 6799 // CHECK9-NEXT: ret i64 0 6800 // 6801 // 6802 // CHECK9-LABEL: define {{[^@]+}}@_Z3fooi 6803 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 6804 // CHECK9-NEXT: entry: 6805 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6806 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 6807 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 6808 // CHECK9-NEXT: [[B:%.*]] = alloca [10 x float], align 4 6809 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 6810 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 6811 // CHECK9-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 6812 // CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 6813 // CHECK9-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 6814 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 6815 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6816 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6817 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6818 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 6819 // CHECK9-NEXT: [[K:%.*]] = alloca i64, align 8 6820 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 6821 // CHECK9-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 6822 // CHECK9-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 6823 // CHECK9-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 6824 // CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 6825 // CHECK9-NEXT: [[I7:%.*]] = alloca i32, align 4 6826 // CHECK9-NEXT: [[K8:%.*]] = alloca i64, align 8 6827 // CHECK9-NEXT: [[LIN:%.*]] = alloca i32, align 4 6828 // CHECK9-NEXT: [[_TMP20:%.*]] = alloca i64, align 8 6829 // CHECK9-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 6830 // CHECK9-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 6831 // CHECK9-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 6832 // CHECK9-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 6833 // CHECK9-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 6834 // CHECK9-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 6835 // CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8 6836 // CHECK9-NEXT: [[LIN27:%.*]] = alloca i32, align 4 6837 // CHECK9-NEXT: [[A28:%.*]] = alloca i32, align 4 6838 // CHECK9-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 6839 // CHECK9-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 6840 // CHECK9-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 6841 // CHECK9-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 6842 // CHECK9-NEXT: [[IT53:%.*]] = alloca i16, align 2 6843 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6844 // CHECK9-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 6845 // CHECK9-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 6846 // CHECK9-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 6847 // CHECK9-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 6848 // CHECK9-NEXT: [[IT72:%.*]] = alloca i8, align 1 6849 // CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 6850 // CHECK9-NEXT: store i32 0, ptr [[A]], align 4 6851 // CHECK9-NEXT: store i16 0, ptr [[AA]], align 2 6852 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 6853 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 6854 // CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() 6855 // CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 6856 // CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 6857 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 6858 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 6859 // CHECK9-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 6860 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 6861 // CHECK9-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 6862 // CHECK9-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 6863 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 6864 // CHECK9-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 6865 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6866 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 6867 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6868 // CHECK9: omp.inner.for.cond: 6869 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 6870 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 6871 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 6872 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6873 // CHECK9: omp.inner.for.body: 6874 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 6875 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5 6876 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 6877 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 6878 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6879 // CHECK9: omp.body.continue: 6880 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6881 // CHECK9: omp.inner.for.inc: 6882 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 6883 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 6884 // CHECK9-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 6885 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 6886 // CHECK9: omp.inner.for.end: 6887 // CHECK9-NEXT: store i32 33, ptr [[I]], align 4 6888 // CHECK9-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 6889 // CHECK9-NEXT: store i64 [[CALL]], ptr [[K]], align 8 6890 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 4 6891 // CHECK9-NEXT: store i32 8, ptr [[DOTOMP_UB5]], align 4 6892 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 4 6893 // CHECK9-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV6]], align 4 6894 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[K]], align 8 6895 // CHECK9-NEXT: store i64 [[TMP12]], ptr [[DOTLINEAR_START]], align 8 6896 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 6897 // CHECK9: omp.inner.for.cond9: 6898 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 6899 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP6]] 6900 // CHECK9-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 6901 // CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 6902 // CHECK9: omp.inner.for.body11: 6903 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 6904 // CHECK9-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1 6905 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 6906 // CHECK9-NEXT: store i32 [[SUB]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP6]] 6907 // CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP6]] 6908 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 6909 // CHECK9-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3 6910 // CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 6911 // CHECK9-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]] 6912 // CHECK9-NEXT: store i64 [[ADD14]], ptr [[K8]], align 8, !llvm.access.group [[ACC_GRP6]] 6913 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP6]] 6914 // CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 6915 // CHECK9-NEXT: store i32 [[ADD15]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP6]] 6916 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 6917 // CHECK9: omp.body.continue16: 6918 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 6919 // CHECK9: omp.inner.for.inc17: 6920 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 6921 // CHECK9-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 6922 // CHECK9-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 6923 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] 6924 // CHECK9: omp.inner.for.end19: 6925 // CHECK9-NEXT: store i32 1, ptr [[I7]], align 4 6926 // CHECK9-NEXT: [[TMP20:%.*]] = load i64, ptr [[K8]], align 8 6927 // CHECK9-NEXT: store i64 [[TMP20]], ptr [[K]], align 8 6928 // CHECK9-NEXT: store i32 12, ptr [[LIN]], align 4 6929 // CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB21]], align 8 6930 // CHECK9-NEXT: store i64 3, ptr [[DOTOMP_UB22]], align 8 6931 // CHECK9-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB21]], align 8 6932 // CHECK9-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV23]], align 8 6933 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN]], align 4 6934 // CHECK9-NEXT: store i32 [[TMP22]], ptr [[DOTLINEAR_START24]], align 4 6935 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[A]], align 4 6936 // CHECK9-NEXT: store i32 [[TMP23]], ptr [[DOTLINEAR_START25]], align 4 6937 // CHECK9-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 6938 // CHECK9-NEXT: store i64 [[CALL26]], ptr [[DOTLINEAR_STEP]], align 8 6939 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 6940 // CHECK9: omp.inner.for.cond29: 6941 // CHECK9-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9:![0-9]+]] 6942 // CHECK9-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP9]] 6943 // CHECK9-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]] 6944 // CHECK9-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 6945 // CHECK9: omp.inner.for.body31: 6946 // CHECK9-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 6947 // CHECK9-NEXT: [[MUL32:%.*]] = mul i64 [[TMP26]], 400 6948 // CHECK9-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 6949 // CHECK9-NEXT: store i64 [[SUB33]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP9]] 6950 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP9]] 6951 // CHECK9-NEXT: [[CONV34:%.*]] = sext i32 [[TMP27]] to i64 6952 // CHECK9-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 6953 // CHECK9-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]] 6954 // CHECK9-NEXT: [[MUL35:%.*]] = mul i64 [[TMP28]], [[TMP29]] 6955 // CHECK9-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 6956 // CHECK9-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 6957 // CHECK9-NEXT: store i32 [[CONV37]], ptr [[LIN27]], align 4, !llvm.access.group [[ACC_GRP9]] 6958 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP9]] 6959 // CHECK9-NEXT: [[CONV38:%.*]] = sext i32 [[TMP30]] to i64 6960 // CHECK9-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 6961 // CHECK9-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]] 6962 // CHECK9-NEXT: [[MUL39:%.*]] = mul i64 [[TMP31]], [[TMP32]] 6963 // CHECK9-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 6964 // CHECK9-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 6965 // CHECK9-NEXT: store i32 [[CONV41]], ptr [[A28]], align 4, !llvm.access.group [[ACC_GRP9]] 6966 // CHECK9-NEXT: [[TMP33:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]] 6967 // CHECK9-NEXT: [[CONV42:%.*]] = sext i16 [[TMP33]] to i32 6968 // CHECK9-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 6969 // CHECK9-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 6970 // CHECK9-NEXT: store i16 [[CONV44]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]] 6971 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 6972 // CHECK9: omp.body.continue45: 6973 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 6974 // CHECK9: omp.inner.for.inc46: 6975 // CHECK9-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 6976 // CHECK9-NEXT: [[ADD47:%.*]] = add i64 [[TMP34]], 1 6977 // CHECK9-NEXT: store i64 [[ADD47]], ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 6978 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP10:![0-9]+]] 6979 // CHECK9: omp.inner.for.end48: 6980 // CHECK9-NEXT: store i64 400, ptr [[IT]], align 8 6981 // CHECK9-NEXT: [[TMP35:%.*]] = load i32, ptr [[LIN27]], align 4 6982 // CHECK9-NEXT: store i32 [[TMP35]], ptr [[LIN]], align 4 6983 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[A28]], align 4 6984 // CHECK9-NEXT: store i32 [[TMP36]], ptr [[A]], align 4 6985 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB50]], align 4 6986 // CHECK9-NEXT: store i32 3, ptr [[DOTOMP_UB51]], align 4 6987 // CHECK9-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_LB50]], align 4 6988 // CHECK9-NEXT: store i32 [[TMP37]], ptr [[DOTOMP_IV52]], align 4 6989 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 6990 // CHECK9: omp.inner.for.cond54: 6991 // CHECK9-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 6992 // CHECK9-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP12]] 6993 // CHECK9-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]] 6994 // CHECK9-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 6995 // CHECK9: omp.inner.for.body56: 6996 // CHECK9-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 6997 // CHECK9-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP40]], 4 6998 // CHECK9-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 6999 // CHECK9-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 7000 // CHECK9-NEXT: store i16 [[CONV59]], ptr [[IT53]], align 2, !llvm.access.group [[ACC_GRP12]] 7001 // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]] 7002 // CHECK9-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP41]], 1 7003 // CHECK9-NEXT: store i32 [[ADD60]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]] 7004 // CHECK9-NEXT: [[TMP42:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]] 7005 // CHECK9-NEXT: [[CONV61:%.*]] = sext i16 [[TMP42]] to i32 7006 // CHECK9-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 7007 // CHECK9-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 7008 // CHECK9-NEXT: store i16 [[CONV63]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]] 7009 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 7010 // CHECK9: omp.body.continue64: 7011 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 7012 // CHECK9: omp.inner.for.inc65: 7013 // CHECK9-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 7014 // CHECK9-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP43]], 1 7015 // CHECK9-NEXT: store i32 [[ADD66]], ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 7016 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP13:![0-9]+]] 7017 // CHECK9: omp.inner.for.end67: 7018 // CHECK9-NEXT: store i16 22, ptr [[IT53]], align 2 7019 // CHECK9-NEXT: [[TMP44:%.*]] = load i32, ptr [[A]], align 4 7020 // CHECK9-NEXT: store i32 [[TMP44]], ptr [[DOTCAPTURE_EXPR_]], align 4 7021 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB69]], align 4 7022 // CHECK9-NEXT: store i32 25, ptr [[DOTOMP_UB70]], align 4 7023 // CHECK9-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_LB69]], align 4 7024 // CHECK9-NEXT: store i32 [[TMP45]], ptr [[DOTOMP_IV71]], align 4 7025 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 7026 // CHECK9: omp.inner.for.cond73: 7027 // CHECK9-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] 7028 // CHECK9-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP15]] 7029 // CHECK9-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]] 7030 // CHECK9-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 7031 // CHECK9: omp.inner.for.body75: 7032 // CHECK9-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 7033 // CHECK9-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP48]], 1 7034 // CHECK9-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 7035 // CHECK9-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 7036 // CHECK9-NEXT: store i8 [[CONV78]], ptr [[IT72]], align 1, !llvm.access.group [[ACC_GRP15]] 7037 // CHECK9-NEXT: [[TMP49:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]] 7038 // CHECK9-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP49]], 1 7039 // CHECK9-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]] 7040 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 2 7041 // CHECK9-NEXT: [[TMP50:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] 7042 // CHECK9-NEXT: [[CONV80:%.*]] = fpext float [[TMP50]] to double 7043 // CHECK9-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 7044 // CHECK9-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 7045 // CHECK9-NEXT: store float [[CONV82]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] 7046 // CHECK9-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 3 7047 // CHECK9-NEXT: [[TMP51:%.*]] = load float, ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]] 7048 // CHECK9-NEXT: [[CONV84:%.*]] = fpext float [[TMP51]] to double 7049 // CHECK9-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 7050 // CHECK9-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 7051 // CHECK9-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]] 7052 // CHECK9-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 1 7053 // CHECK9-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i64 0, i64 2 7054 // CHECK9-NEXT: [[TMP52:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] 7055 // CHECK9-NEXT: [[ADD89:%.*]] = fadd double [[TMP52]], 1.000000e+00 7056 // CHECK9-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] 7057 // CHECK9-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP4]] 7058 // CHECK9-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP53]] 7059 // CHECK9-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX90]], i64 3 7060 // CHECK9-NEXT: [[TMP54:%.*]] = load double, ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]] 7061 // CHECK9-NEXT: [[ADD92:%.*]] = fadd double [[TMP54]], 1.000000e+00 7062 // CHECK9-NEXT: store double [[ADD92]], ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]] 7063 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 7064 // CHECK9-NEXT: [[TMP55:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]] 7065 // CHECK9-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP55]], 1 7066 // CHECK9-NEXT: store i64 [[ADD93]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]] 7067 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 7068 // CHECK9-NEXT: [[TMP56:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]] 7069 // CHECK9-NEXT: [[CONV94:%.*]] = sext i8 [[TMP56]] to i32 7070 // CHECK9-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 7071 // CHECK9-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 7072 // CHECK9-NEXT: store i8 [[CONV96]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]] 7073 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 7074 // CHECK9: omp.body.continue97: 7075 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 7076 // CHECK9: omp.inner.for.inc98: 7077 // CHECK9-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 7078 // CHECK9-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 1 7079 // CHECK9-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 7080 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]] 7081 // CHECK9: omp.inner.for.end100: 7082 // CHECK9-NEXT: store i8 96, ptr [[IT72]], align 1 7083 // CHECK9-NEXT: [[TMP58:%.*]] = load i32, ptr [[A]], align 4 7084 // CHECK9-NEXT: [[TMP59:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 7085 // CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP59]]) 7086 // CHECK9-NEXT: ret i32 [[TMP58]] 7087 // 7088 // 7089 // CHECK9-LABEL: define {{[^@]+}}@_Z3bari 7090 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7091 // CHECK9-NEXT: entry: 7092 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7093 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7094 // CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 7095 // CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7096 // CHECK9-NEXT: store i32 0, ptr [[A]], align 4 7097 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 7098 // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 7099 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 7100 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 7101 // CHECK9-NEXT: store i32 [[ADD]], ptr [[A]], align 4 7102 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 7103 // CHECK9-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 7104 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 7105 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 7106 // CHECK9-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 7107 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 7108 // CHECK9-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 7109 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 7110 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 7111 // CHECK9-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 7112 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 7113 // CHECK9-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 7114 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 7115 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 7116 // CHECK9-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 7117 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 7118 // CHECK9-NEXT: ret i32 [[TMP8]] 7119 // 7120 // 7121 // CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 7122 // CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 7123 // CHECK9-NEXT: entry: 7124 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7125 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7126 // CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 7127 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 7128 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7129 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 7130 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7131 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7132 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7133 // CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8 7134 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7135 // CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7136 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7137 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 7138 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7139 // CHECK9-NEXT: store i32 [[ADD]], ptr [[B]], align 4 7140 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 7141 // CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 7142 // CHECK9-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() 7143 // CHECK9-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 7144 // CHECK9-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 7145 // CHECK9-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 7146 // CHECK9-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 7147 // CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 7148 // CHECK9-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 7149 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 7150 // CHECK9-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 7151 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7152 // CHECK9: omp.inner.for.cond: 7153 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]] 7154 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]] 7155 // CHECK9-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP6]], [[TMP7]] 7156 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7157 // CHECK9: omp.inner.for.body: 7158 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 7159 // CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP8]], 400 7160 // CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 7161 // CHECK9-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP18]] 7162 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP18]] 7163 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double 7164 // CHECK9-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 7165 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 7166 // CHECK9-NEXT: store double [[ADD2]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP18]] 7167 // CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 7168 // CHECK9-NEXT: [[TMP10:%.*]] = load double, ptr [[A3]], align 8, !llvm.access.group [[ACC_GRP18]] 7169 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00 7170 // CHECK9-NEXT: store double [[INC]], ptr [[A3]], align 8, !llvm.access.group [[ACC_GRP18]] 7171 // CHECK9-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 7172 // CHECK9-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]] 7173 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP11]] 7174 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 7175 // CHECK9-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2, !llvm.access.group [[ACC_GRP18]] 7176 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7177 // CHECK9: omp.body.continue: 7178 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7179 // CHECK9: omp.inner.for.inc: 7180 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 7181 // CHECK9-NEXT: [[ADD6:%.*]] = add i64 [[TMP12]], 1 7182 // CHECK9-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 7183 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 7184 // CHECK9: omp.inner.for.end: 7185 // CHECK9-NEXT: store i64 400, ptr [[IT]], align 8 7186 // CHECK9-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] 7187 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP13]] 7188 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX7]], i64 1 7189 // CHECK9-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX8]], align 2 7190 // CHECK9-NEXT: [[CONV9:%.*]] = sext i16 [[TMP14]] to i32 7191 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4 7192 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP15]] 7193 // CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 7194 // CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP16]]) 7195 // CHECK9-NEXT: ret i32 [[ADD10]] 7196 // 7197 // 7198 // CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici 7199 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7200 // CHECK9-NEXT: entry: 7201 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7202 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7203 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 7204 // CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 1 7205 // CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7206 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 7207 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7208 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7209 // CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7210 // CHECK9-NEXT: store i32 0, ptr [[A]], align 4 7211 // CHECK9-NEXT: store i16 0, ptr [[AA]], align 2 7212 // CHECK9-NEXT: store i8 0, ptr [[AAA]], align 1 7213 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 7214 // CHECK9-NEXT: store i32 429496720, ptr [[DOTOMP_UB]], align 4 7215 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 7216 // CHECK9-NEXT: ret i32 [[TMP0]] 7217 // 7218 // 7219 // CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 7220 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 7221 // CHECK9-NEXT: entry: 7222 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7223 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7224 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 7225 // CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7226 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 7227 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7228 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7229 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7230 // CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8 7231 // CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7232 // CHECK9-NEXT: store i32 0, ptr [[A]], align 4 7233 // CHECK9-NEXT: store i16 0, ptr [[AA]], align 2 7234 // CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 7235 // CHECK9-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 7236 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 7237 // CHECK9-NEXT: store i64 [[TMP0]], ptr [[DOTOMP_IV]], align 8 7238 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7239 // CHECK9: omp.inner.for.cond: 7240 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21:![0-9]+]] 7241 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP21]] 7242 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 7243 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7244 // CHECK9: omp.inner.for.body: 7245 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21]] 7246 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 7247 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 7248 // CHECK9-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP21]] 7249 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP21]] 7250 // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 7251 // CHECK9-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP21]] 7252 // CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP21]] 7253 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 7254 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 7255 // CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 7256 // CHECK9-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP21]] 7257 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 7258 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] 7259 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 7260 // CHECK9-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] 7261 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7262 // CHECK9: omp.body.continue: 7263 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7264 // CHECK9: omp.inner.for.inc: 7265 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21]] 7266 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 7267 // CHECK9-NEXT: store i64 [[ADD5]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21]] 7268 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 7269 // CHECK9: omp.inner.for.end: 7270 // CHECK9-NEXT: store i64 11, ptr [[I]], align 8 7271 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 7272 // CHECK9-NEXT: ret i32 [[TMP8]] 7273 // 7274 // 7275 // CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv 7276 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 7277 // CHECK11-NEXT: entry: 7278 // CHECK11-NEXT: ret i64 0 7279 // 7280 // 7281 // CHECK11-LABEL: define {{[^@]+}}@_Z3fooi 7282 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 7283 // CHECK11-NEXT: entry: 7284 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7285 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 7286 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 7287 // CHECK11-NEXT: [[B:%.*]] = alloca [10 x float], align 4 7288 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 7289 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 7290 // CHECK11-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 7291 // CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 7292 // CHECK11-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 7293 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 7294 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7295 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7296 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7297 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 7298 // CHECK11-NEXT: [[K:%.*]] = alloca i64, align 8 7299 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 7300 // CHECK11-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 7301 // CHECK11-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 7302 // CHECK11-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 7303 // CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 7304 // CHECK11-NEXT: [[I7:%.*]] = alloca i32, align 4 7305 // CHECK11-NEXT: [[K8:%.*]] = alloca i64, align 8 7306 // CHECK11-NEXT: [[LIN:%.*]] = alloca i32, align 4 7307 // CHECK11-NEXT: [[_TMP20:%.*]] = alloca i64, align 4 7308 // CHECK11-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 7309 // CHECK11-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 7310 // CHECK11-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 7311 // CHECK11-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 7312 // CHECK11-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 7313 // CHECK11-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 7314 // CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8 7315 // CHECK11-NEXT: [[LIN27:%.*]] = alloca i32, align 4 7316 // CHECK11-NEXT: [[A28:%.*]] = alloca i32, align 4 7317 // CHECK11-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 7318 // CHECK11-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 7319 // CHECK11-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 7320 // CHECK11-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 7321 // CHECK11-NEXT: [[IT53:%.*]] = alloca i16, align 2 7322 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 7323 // CHECK11-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 7324 // CHECK11-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 7325 // CHECK11-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 7326 // CHECK11-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 7327 // CHECK11-NEXT: [[IT72:%.*]] = alloca i8, align 1 7328 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7329 // CHECK11-NEXT: store i32 0, ptr [[A]], align 4 7330 // CHECK11-NEXT: store i16 0, ptr [[AA]], align 2 7331 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 7332 // CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() 7333 // CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 7334 // CHECK11-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 7335 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 7336 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 7337 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 7338 // CHECK11-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 7339 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 7340 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 7341 // CHECK11-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 7342 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 7343 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 7344 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7345 // CHECK11: omp.inner.for.cond: 7346 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 7347 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 7348 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 7349 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7350 // CHECK11: omp.inner.for.body: 7351 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 7352 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 7353 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 7354 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 7355 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7356 // CHECK11: omp.body.continue: 7357 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7358 // CHECK11: omp.inner.for.inc: 7359 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 7360 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 7361 // CHECK11-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 7362 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 7363 // CHECK11: omp.inner.for.end: 7364 // CHECK11-NEXT: store i32 33, ptr [[I]], align 4 7365 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 7366 // CHECK11-NEXT: store i64 [[CALL]], ptr [[K]], align 8 7367 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 4 7368 // CHECK11-NEXT: store i32 8, ptr [[DOTOMP_UB5]], align 4 7369 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 4 7370 // CHECK11-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV6]], align 4 7371 // CHECK11-NEXT: [[TMP10:%.*]] = load i64, ptr [[K]], align 8 7372 // CHECK11-NEXT: store i64 [[TMP10]], ptr [[DOTLINEAR_START]], align 8 7373 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 7374 // CHECK11: omp.inner.for.cond9: 7375 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 7376 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP7]] 7377 // CHECK11-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 7378 // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 7379 // CHECK11: omp.inner.for.body11: 7380 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 7381 // CHECK11-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1 7382 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 7383 // CHECK11-NEXT: store i32 [[SUB]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] 7384 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP7]] 7385 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 7386 // CHECK11-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3 7387 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 7388 // CHECK11-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]] 7389 // CHECK11-NEXT: store i64 [[ADD14]], ptr [[K8]], align 8, !llvm.access.group [[ACC_GRP7]] 7390 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP7]] 7391 // CHECK11-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 7392 // CHECK11-NEXT: store i32 [[ADD15]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP7]] 7393 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 7394 // CHECK11: omp.body.continue16: 7395 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 7396 // CHECK11: omp.inner.for.inc17: 7397 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 7398 // CHECK11-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 7399 // CHECK11-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 7400 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]] 7401 // CHECK11: omp.inner.for.end19: 7402 // CHECK11-NEXT: store i32 1, ptr [[I7]], align 4 7403 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, ptr [[K8]], align 8 7404 // CHECK11-NEXT: store i64 [[TMP18]], ptr [[K]], align 8 7405 // CHECK11-NEXT: store i32 12, ptr [[LIN]], align 4 7406 // CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB21]], align 8 7407 // CHECK11-NEXT: store i64 3, ptr [[DOTOMP_UB22]], align 8 7408 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_LB21]], align 8 7409 // CHECK11-NEXT: store i64 [[TMP19]], ptr [[DOTOMP_IV23]], align 8 7410 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN]], align 4 7411 // CHECK11-NEXT: store i32 [[TMP20]], ptr [[DOTLINEAR_START24]], align 4 7412 // CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 4 7413 // CHECK11-NEXT: store i32 [[TMP21]], ptr [[DOTLINEAR_START25]], align 4 7414 // CHECK11-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 7415 // CHECK11-NEXT: store i64 [[CALL26]], ptr [[DOTLINEAR_STEP]], align 8 7416 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 7417 // CHECK11: omp.inner.for.cond29: 7418 // CHECK11-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10:![0-9]+]] 7419 // CHECK11-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP10]] 7420 // CHECK11-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 7421 // CHECK11-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 7422 // CHECK11: omp.inner.for.body31: 7423 // CHECK11-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7424 // CHECK11-NEXT: [[MUL32:%.*]] = mul i64 [[TMP24]], 400 7425 // CHECK11-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 7426 // CHECK11-NEXT: store i64 [[SUB33]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP10]] 7427 // CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP10]] 7428 // CHECK11-NEXT: [[CONV34:%.*]] = sext i32 [[TMP25]] to i64 7429 // CHECK11-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7430 // CHECK11-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]] 7431 // CHECK11-NEXT: [[MUL35:%.*]] = mul i64 [[TMP26]], [[TMP27]] 7432 // CHECK11-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 7433 // CHECK11-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 7434 // CHECK11-NEXT: store i32 [[CONV37]], ptr [[LIN27]], align 4, !llvm.access.group [[ACC_GRP10]] 7435 // CHECK11-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP10]] 7436 // CHECK11-NEXT: [[CONV38:%.*]] = sext i32 [[TMP28]] to i64 7437 // CHECK11-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7438 // CHECK11-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]] 7439 // CHECK11-NEXT: [[MUL39:%.*]] = mul i64 [[TMP29]], [[TMP30]] 7440 // CHECK11-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 7441 // CHECK11-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 7442 // CHECK11-NEXT: store i32 [[CONV41]], ptr [[A28]], align 4, !llvm.access.group [[ACC_GRP10]] 7443 // CHECK11-NEXT: [[TMP31:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]] 7444 // CHECK11-NEXT: [[CONV42:%.*]] = sext i16 [[TMP31]] to i32 7445 // CHECK11-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 7446 // CHECK11-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 7447 // CHECK11-NEXT: store i16 [[CONV44]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]] 7448 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 7449 // CHECK11: omp.body.continue45: 7450 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 7451 // CHECK11: omp.inner.for.inc46: 7452 // CHECK11-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7453 // CHECK11-NEXT: [[ADD47:%.*]] = add i64 [[TMP32]], 1 7454 // CHECK11-NEXT: store i64 [[ADD47]], ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7455 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP11:![0-9]+]] 7456 // CHECK11: omp.inner.for.end48: 7457 // CHECK11-NEXT: store i64 400, ptr [[IT]], align 8 7458 // CHECK11-NEXT: [[TMP33:%.*]] = load i32, ptr [[LIN27]], align 4 7459 // CHECK11-NEXT: store i32 [[TMP33]], ptr [[LIN]], align 4 7460 // CHECK11-NEXT: [[TMP34:%.*]] = load i32, ptr [[A28]], align 4 7461 // CHECK11-NEXT: store i32 [[TMP34]], ptr [[A]], align 4 7462 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB50]], align 4 7463 // CHECK11-NEXT: store i32 3, ptr [[DOTOMP_UB51]], align 4 7464 // CHECK11-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_LB50]], align 4 7465 // CHECK11-NEXT: store i32 [[TMP35]], ptr [[DOTOMP_IV52]], align 4 7466 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 7467 // CHECK11: omp.inner.for.cond54: 7468 // CHECK11-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] 7469 // CHECK11-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP13]] 7470 // CHECK11-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP36]], [[TMP37]] 7471 // CHECK11-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 7472 // CHECK11: omp.inner.for.body56: 7473 // CHECK11-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 7474 // CHECK11-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP38]], 4 7475 // CHECK11-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 7476 // CHECK11-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 7477 // CHECK11-NEXT: store i16 [[CONV59]], ptr [[IT53]], align 2, !llvm.access.group [[ACC_GRP13]] 7478 // CHECK11-NEXT: [[TMP39:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]] 7479 // CHECK11-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP39]], 1 7480 // CHECK11-NEXT: store i32 [[ADD60]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]] 7481 // CHECK11-NEXT: [[TMP40:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]] 7482 // CHECK11-NEXT: [[CONV61:%.*]] = sext i16 [[TMP40]] to i32 7483 // CHECK11-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 7484 // CHECK11-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 7485 // CHECK11-NEXT: store i16 [[CONV63]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]] 7486 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 7487 // CHECK11: omp.body.continue64: 7488 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 7489 // CHECK11: omp.inner.for.inc65: 7490 // CHECK11-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 7491 // CHECK11-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP41]], 1 7492 // CHECK11-NEXT: store i32 [[ADD66]], ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 7493 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP14:![0-9]+]] 7494 // CHECK11: omp.inner.for.end67: 7495 // CHECK11-NEXT: store i16 22, ptr [[IT53]], align 2 7496 // CHECK11-NEXT: [[TMP42:%.*]] = load i32, ptr [[A]], align 4 7497 // CHECK11-NEXT: store i32 [[TMP42]], ptr [[DOTCAPTURE_EXPR_]], align 4 7498 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB69]], align 4 7499 // CHECK11-NEXT: store i32 25, ptr [[DOTOMP_UB70]], align 4 7500 // CHECK11-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_LB69]], align 4 7501 // CHECK11-NEXT: store i32 [[TMP43]], ptr [[DOTOMP_IV71]], align 4 7502 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 7503 // CHECK11: omp.inner.for.cond73: 7504 // CHECK11-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] 7505 // CHECK11-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP16]] 7506 // CHECK11-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP44]], [[TMP45]] 7507 // CHECK11-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 7508 // CHECK11: omp.inner.for.body75: 7509 // CHECK11-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 7510 // CHECK11-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP46]], 1 7511 // CHECK11-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 7512 // CHECK11-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 7513 // CHECK11-NEXT: store i8 [[CONV78]], ptr [[IT72]], align 1, !llvm.access.group [[ACC_GRP16]] 7514 // CHECK11-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] 7515 // CHECK11-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP47]], 1 7516 // CHECK11-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] 7517 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 2 7518 // CHECK11-NEXT: [[TMP48:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] 7519 // CHECK11-NEXT: [[CONV80:%.*]] = fpext float [[TMP48]] to double 7520 // CHECK11-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 7521 // CHECK11-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 7522 // CHECK11-NEXT: store float [[CONV82]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] 7523 // CHECK11-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 3 7524 // CHECK11-NEXT: [[TMP49:%.*]] = load float, ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]] 7525 // CHECK11-NEXT: [[CONV84:%.*]] = fpext float [[TMP49]] to double 7526 // CHECK11-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 7527 // CHECK11-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 7528 // CHECK11-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]] 7529 // CHECK11-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 1 7530 // CHECK11-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i32 0, i32 2 7531 // CHECK11-NEXT: [[TMP50:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] 7532 // CHECK11-NEXT: [[ADD89:%.*]] = fadd double [[TMP50]], 1.000000e+00 7533 // CHECK11-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] 7534 // CHECK11-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP2]] 7535 // CHECK11-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP51]] 7536 // CHECK11-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX90]], i32 3 7537 // CHECK11-NEXT: [[TMP52:%.*]] = load double, ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]] 7538 // CHECK11-NEXT: [[ADD92:%.*]] = fadd double [[TMP52]], 1.000000e+00 7539 // CHECK11-NEXT: store double [[ADD92]], ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]] 7540 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 7541 // CHECK11-NEXT: [[TMP53:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]] 7542 // CHECK11-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP53]], 1 7543 // CHECK11-NEXT: store i64 [[ADD93]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]] 7544 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 7545 // CHECK11-NEXT: [[TMP54:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]] 7546 // CHECK11-NEXT: [[CONV94:%.*]] = sext i8 [[TMP54]] to i32 7547 // CHECK11-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 7548 // CHECK11-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 7549 // CHECK11-NEXT: store i8 [[CONV96]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]] 7550 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 7551 // CHECK11: omp.body.continue97: 7552 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 7553 // CHECK11: omp.inner.for.inc98: 7554 // CHECK11-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 7555 // CHECK11-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 1 7556 // CHECK11-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 7557 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]] 7558 // CHECK11: omp.inner.for.end100: 7559 // CHECK11-NEXT: store i8 96, ptr [[IT72]], align 1 7560 // CHECK11-NEXT: [[TMP56:%.*]] = load i32, ptr [[A]], align 4 7561 // CHECK11-NEXT: [[TMP57:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 7562 // CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP57]]) 7563 // CHECK11-NEXT: ret i32 [[TMP56]] 7564 // 7565 // 7566 // CHECK11-LABEL: define {{[^@]+}}@_Z3bari 7567 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 7568 // CHECK11-NEXT: entry: 7569 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7570 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 7571 // CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 7572 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7573 // CHECK11-NEXT: store i32 0, ptr [[A]], align 4 7574 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 7575 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 7576 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 7577 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 7578 // CHECK11-NEXT: store i32 [[ADD]], ptr [[A]], align 4 7579 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 7580 // CHECK11-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 7581 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 7582 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 7583 // CHECK11-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 7584 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 7585 // CHECK11-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 7586 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 7587 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 7588 // CHECK11-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 7589 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 7590 // CHECK11-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 7591 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 7592 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 7593 // CHECK11-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 7594 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 7595 // CHECK11-NEXT: ret i32 [[TMP8]] 7596 // 7597 // 7598 // CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 7599 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 7600 // CHECK11-NEXT: entry: 7601 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 7602 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7603 // CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 7604 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 7605 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 7606 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4 7607 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7608 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7609 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7610 // CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8 7611 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 7612 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7613 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 7614 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 7615 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7616 // CHECK11-NEXT: store i32 [[ADD]], ptr [[B]], align 4 7617 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 7618 // CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() 7619 // CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 7620 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 7621 // CHECK11-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 7622 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 7623 // CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 7624 // CHECK11-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 7625 // CHECK11-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 7626 // CHECK11-NEXT: store i64 [[TMP4]], ptr [[DOTOMP_IV]], align 8 7627 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7628 // CHECK11: omp.inner.for.cond: 7629 // CHECK11-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19:![0-9]+]] 7630 // CHECK11-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP19]] 7631 // CHECK11-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP5]], [[TMP6]] 7632 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7633 // CHECK11: omp.inner.for.body: 7634 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 7635 // CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP7]], 400 7636 // CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 7637 // CHECK11-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP19]] 7638 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP19]] 7639 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double 7640 // CHECK11-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 7641 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 7642 // CHECK11-NEXT: store double [[ADD2]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP19]] 7643 // CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 7644 // CHECK11-NEXT: [[TMP9:%.*]] = load double, ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP19]] 7645 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 7646 // CHECK11-NEXT: store double [[INC]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP19]] 7647 // CHECK11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 7648 // CHECK11-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]] 7649 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP10]] 7650 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 7651 // CHECK11-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2, !llvm.access.group [[ACC_GRP19]] 7652 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7653 // CHECK11: omp.body.continue: 7654 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7655 // CHECK11: omp.inner.for.inc: 7656 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 7657 // CHECK11-NEXT: [[ADD6:%.*]] = add i64 [[TMP11]], 1 7658 // CHECK11-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 7659 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 7660 // CHECK11: omp.inner.for.end: 7661 // CHECK11-NEXT: store i64 400, ptr [[IT]], align 8 7662 // CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] 7663 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP12]] 7664 // CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX7]], i32 1 7665 // CHECK11-NEXT: [[TMP13:%.*]] = load i16, ptr [[ARRAYIDX8]], align 2 7666 // CHECK11-NEXT: [[CONV9:%.*]] = sext i16 [[TMP13]] to i32 7667 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[B]], align 4 7668 // CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP14]] 7669 // CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 7670 // CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) 7671 // CHECK11-NEXT: ret i32 [[ADD10]] 7672 // 7673 // 7674 // CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici 7675 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 7676 // CHECK11-NEXT: entry: 7677 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7678 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 7679 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 7680 // CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 1 7681 // CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7682 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 7683 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7684 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7685 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7686 // CHECK11-NEXT: store i32 0, ptr [[A]], align 4 7687 // CHECK11-NEXT: store i16 0, ptr [[AA]], align 2 7688 // CHECK11-NEXT: store i8 0, ptr [[AAA]], align 1 7689 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 7690 // CHECK11-NEXT: store i32 429496720, ptr [[DOTOMP_UB]], align 4 7691 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 7692 // CHECK11-NEXT: ret i32 [[TMP0]] 7693 // 7694 // 7695 // CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 7696 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 7697 // CHECK11-NEXT: entry: 7698 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7699 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 7700 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 7701 // CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7702 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4 7703 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7704 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7705 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7706 // CHECK11-NEXT: [[I:%.*]] = alloca i64, align 8 7707 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7708 // CHECK11-NEXT: store i32 0, ptr [[A]], align 4 7709 // CHECK11-NEXT: store i16 0, ptr [[AA]], align 2 7710 // CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 7711 // CHECK11-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 7712 // CHECK11-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 7713 // CHECK11-NEXT: store i64 [[TMP0]], ptr [[DOTOMP_IV]], align 8 7714 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7715 // CHECK11: omp.inner.for.cond: 7716 // CHECK11-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22:![0-9]+]] 7717 // CHECK11-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP22]] 7718 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 7719 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7720 // CHECK11: omp.inner.for.body: 7721 // CHECK11-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22]] 7722 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 7723 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 7724 // CHECK11-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP22]] 7725 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP22]] 7726 // CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 7727 // CHECK11-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP22]] 7728 // CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP22]] 7729 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 7730 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 7731 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 7732 // CHECK11-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP22]] 7733 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 7734 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] 7735 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 7736 // CHECK11-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] 7737 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7738 // CHECK11: omp.body.continue: 7739 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7740 // CHECK11: omp.inner.for.inc: 7741 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22]] 7742 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 7743 // CHECK11-NEXT: store i64 [[ADD5]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22]] 7744 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] 7745 // CHECK11: omp.inner.for.end: 7746 // CHECK11-NEXT: store i64 11, ptr [[I]], align 8 7747 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 7748 // CHECK11-NEXT: ret i32 [[TMP8]] 7749 // 7750 // 7751 // CHECK13-LABEL: define {{[^@]+}}@_Z7get_valv 7752 // CHECK13-SAME: () #[[ATTR0:[0-9]+]] { 7753 // CHECK13-NEXT: entry: 7754 // CHECK13-NEXT: ret i64 0 7755 // 7756 // 7757 // CHECK13-LABEL: define {{[^@]+}}@_Z3fooi 7758 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7759 // CHECK13-NEXT: entry: 7760 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7761 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 7762 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 7763 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x float], align 4 7764 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 7765 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7766 // CHECK13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 7767 // CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 7768 // CHECK13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 7769 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 7770 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7771 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7772 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7773 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 7774 // CHECK13-NEXT: [[K:%.*]] = alloca i64, align 8 7775 // CHECK13-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 7776 // CHECK13-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 7777 // CHECK13-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 7778 // CHECK13-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 7779 // CHECK13-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 7780 // CHECK13-NEXT: [[I7:%.*]] = alloca i32, align 4 7781 // CHECK13-NEXT: [[K8:%.*]] = alloca i64, align 8 7782 // CHECK13-NEXT: [[LIN:%.*]] = alloca i32, align 4 7783 // CHECK13-NEXT: [[_TMP20:%.*]] = alloca i64, align 8 7784 // CHECK13-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 7785 // CHECK13-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 7786 // CHECK13-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 7787 // CHECK13-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 7788 // CHECK13-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 7789 // CHECK13-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 7790 // CHECK13-NEXT: [[IT:%.*]] = alloca i64, align 8 7791 // CHECK13-NEXT: [[LIN27:%.*]] = alloca i32, align 4 7792 // CHECK13-NEXT: [[A28:%.*]] = alloca i32, align 4 7793 // CHECK13-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 7794 // CHECK13-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 7795 // CHECK13-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 7796 // CHECK13-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 7797 // CHECK13-NEXT: [[IT53:%.*]] = alloca i16, align 2 7798 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 7799 // CHECK13-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 7800 // CHECK13-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 7801 // CHECK13-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 7802 // CHECK13-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 7803 // CHECK13-NEXT: [[IT72:%.*]] = alloca i8, align 1 7804 // CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7805 // CHECK13-NEXT: store i32 0, ptr [[A]], align 4 7806 // CHECK13-NEXT: store i16 0, ptr [[AA]], align 2 7807 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 7808 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 7809 // CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() 7810 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 7811 // CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 7812 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 7813 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 7814 // CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 7815 // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 7816 // CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 7817 // CHECK13-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 7818 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 7819 // CHECK13-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 7820 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 7821 // CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 7822 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7823 // CHECK13: omp.inner.for.cond: 7824 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 7825 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 7826 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 7827 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7828 // CHECK13: omp.inner.for.body: 7829 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 7830 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5 7831 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 7832 // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 7833 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7834 // CHECK13: omp.body.continue: 7835 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7836 // CHECK13: omp.inner.for.inc: 7837 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 7838 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 7839 // CHECK13-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 7840 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 7841 // CHECK13: omp.inner.for.end: 7842 // CHECK13-NEXT: store i32 33, ptr [[I]], align 4 7843 // CHECK13-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 7844 // CHECK13-NEXT: store i64 [[CALL]], ptr [[K]], align 8 7845 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 4 7846 // CHECK13-NEXT: store i32 8, ptr [[DOTOMP_UB5]], align 4 7847 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 4 7848 // CHECK13-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV6]], align 4 7849 // CHECK13-NEXT: [[TMP12:%.*]] = load i64, ptr [[K]], align 8 7850 // CHECK13-NEXT: store i64 [[TMP12]], ptr [[DOTLINEAR_START]], align 8 7851 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 7852 // CHECK13: omp.inner.for.cond9: 7853 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 7854 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP6]] 7855 // CHECK13-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 7856 // CHECK13-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 7857 // CHECK13: omp.inner.for.body11: 7858 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 7859 // CHECK13-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1 7860 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 7861 // CHECK13-NEXT: store i32 [[SUB]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP6]] 7862 // CHECK13-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP6]] 7863 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 7864 // CHECK13-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3 7865 // CHECK13-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 7866 // CHECK13-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]] 7867 // CHECK13-NEXT: store i64 [[ADD14]], ptr [[K8]], align 8, !llvm.access.group [[ACC_GRP6]] 7868 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP6]] 7869 // CHECK13-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 7870 // CHECK13-NEXT: store i32 [[ADD15]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP6]] 7871 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 7872 // CHECK13: omp.body.continue16: 7873 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 7874 // CHECK13: omp.inner.for.inc17: 7875 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 7876 // CHECK13-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 7877 // CHECK13-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 7878 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] 7879 // CHECK13: omp.inner.for.end19: 7880 // CHECK13-NEXT: store i32 1, ptr [[I7]], align 4 7881 // CHECK13-NEXT: [[TMP20:%.*]] = load i64, ptr [[K8]], align 8 7882 // CHECK13-NEXT: store i64 [[TMP20]], ptr [[K]], align 8 7883 // CHECK13-NEXT: store i32 12, ptr [[LIN]], align 4 7884 // CHECK13-NEXT: store i64 0, ptr [[DOTOMP_LB21]], align 8 7885 // CHECK13-NEXT: store i64 3, ptr [[DOTOMP_UB22]], align 8 7886 // CHECK13-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB21]], align 8 7887 // CHECK13-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV23]], align 8 7888 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN]], align 4 7889 // CHECK13-NEXT: store i32 [[TMP22]], ptr [[DOTLINEAR_START24]], align 4 7890 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, ptr [[A]], align 4 7891 // CHECK13-NEXT: store i32 [[TMP23]], ptr [[DOTLINEAR_START25]], align 4 7892 // CHECK13-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 7893 // CHECK13-NEXT: store i64 [[CALL26]], ptr [[DOTLINEAR_STEP]], align 8 7894 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 7895 // CHECK13: omp.inner.for.cond29: 7896 // CHECK13-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9:![0-9]+]] 7897 // CHECK13-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP9]] 7898 // CHECK13-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]] 7899 // CHECK13-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 7900 // CHECK13: omp.inner.for.body31: 7901 // CHECK13-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7902 // CHECK13-NEXT: [[MUL32:%.*]] = mul i64 [[TMP26]], 400 7903 // CHECK13-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 7904 // CHECK13-NEXT: store i64 [[SUB33]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP9]] 7905 // CHECK13-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP9]] 7906 // CHECK13-NEXT: [[CONV34:%.*]] = sext i32 [[TMP27]] to i64 7907 // CHECK13-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7908 // CHECK13-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]] 7909 // CHECK13-NEXT: [[MUL35:%.*]] = mul i64 [[TMP28]], [[TMP29]] 7910 // CHECK13-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 7911 // CHECK13-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 7912 // CHECK13-NEXT: store i32 [[CONV37]], ptr [[LIN27]], align 4, !llvm.access.group [[ACC_GRP9]] 7913 // CHECK13-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP9]] 7914 // CHECK13-NEXT: [[CONV38:%.*]] = sext i32 [[TMP30]] to i64 7915 // CHECK13-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7916 // CHECK13-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]] 7917 // CHECK13-NEXT: [[MUL39:%.*]] = mul i64 [[TMP31]], [[TMP32]] 7918 // CHECK13-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 7919 // CHECK13-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 7920 // CHECK13-NEXT: store i32 [[CONV41]], ptr [[A28]], align 4, !llvm.access.group [[ACC_GRP9]] 7921 // CHECK13-NEXT: [[TMP33:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]] 7922 // CHECK13-NEXT: [[CONV42:%.*]] = sext i16 [[TMP33]] to i32 7923 // CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 7924 // CHECK13-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 7925 // CHECK13-NEXT: store i16 [[CONV44]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]] 7926 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 7927 // CHECK13: omp.body.continue45: 7928 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 7929 // CHECK13: omp.inner.for.inc46: 7930 // CHECK13-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7931 // CHECK13-NEXT: [[ADD47:%.*]] = add i64 [[TMP34]], 1 7932 // CHECK13-NEXT: store i64 [[ADD47]], ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7933 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP10:![0-9]+]] 7934 // CHECK13: omp.inner.for.end48: 7935 // CHECK13-NEXT: store i64 400, ptr [[IT]], align 8 7936 // CHECK13-NEXT: [[TMP35:%.*]] = load i32, ptr [[LIN27]], align 4 7937 // CHECK13-NEXT: store i32 [[TMP35]], ptr [[LIN]], align 4 7938 // CHECK13-NEXT: [[TMP36:%.*]] = load i32, ptr [[A28]], align 4 7939 // CHECK13-NEXT: store i32 [[TMP36]], ptr [[A]], align 4 7940 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB50]], align 4 7941 // CHECK13-NEXT: store i32 3, ptr [[DOTOMP_UB51]], align 4 7942 // CHECK13-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_LB50]], align 4 7943 // CHECK13-NEXT: store i32 [[TMP37]], ptr [[DOTOMP_IV52]], align 4 7944 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 7945 // CHECK13: omp.inner.for.cond54: 7946 // CHECK13-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 7947 // CHECK13-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP12]] 7948 // CHECK13-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]] 7949 // CHECK13-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 7950 // CHECK13: omp.inner.for.body56: 7951 // CHECK13-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 7952 // CHECK13-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP40]], 4 7953 // CHECK13-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 7954 // CHECK13-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 7955 // CHECK13-NEXT: store i16 [[CONV59]], ptr [[IT53]], align 2, !llvm.access.group [[ACC_GRP12]] 7956 // CHECK13-NEXT: [[TMP41:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]] 7957 // CHECK13-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP41]], 1 7958 // CHECK13-NEXT: store i32 [[ADD60]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]] 7959 // CHECK13-NEXT: [[TMP42:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]] 7960 // CHECK13-NEXT: [[CONV61:%.*]] = sext i16 [[TMP42]] to i32 7961 // CHECK13-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 7962 // CHECK13-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 7963 // CHECK13-NEXT: store i16 [[CONV63]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]] 7964 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 7965 // CHECK13: omp.body.continue64: 7966 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 7967 // CHECK13: omp.inner.for.inc65: 7968 // CHECK13-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 7969 // CHECK13-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP43]], 1 7970 // CHECK13-NEXT: store i32 [[ADD66]], ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 7971 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP13:![0-9]+]] 7972 // CHECK13: omp.inner.for.end67: 7973 // CHECK13-NEXT: store i16 22, ptr [[IT53]], align 2 7974 // CHECK13-NEXT: [[TMP44:%.*]] = load i32, ptr [[A]], align 4 7975 // CHECK13-NEXT: store i32 [[TMP44]], ptr [[DOTCAPTURE_EXPR_]], align 4 7976 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB69]], align 4 7977 // CHECK13-NEXT: store i32 25, ptr [[DOTOMP_UB70]], align 4 7978 // CHECK13-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_LB69]], align 4 7979 // CHECK13-NEXT: store i32 [[TMP45]], ptr [[DOTOMP_IV71]], align 4 7980 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 7981 // CHECK13: omp.inner.for.cond73: 7982 // CHECK13-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] 7983 // CHECK13-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP15]] 7984 // CHECK13-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]] 7985 // CHECK13-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 7986 // CHECK13: omp.inner.for.body75: 7987 // CHECK13-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 7988 // CHECK13-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP48]], 1 7989 // CHECK13-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 7990 // CHECK13-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 7991 // CHECK13-NEXT: store i8 [[CONV78]], ptr [[IT72]], align 1, !llvm.access.group [[ACC_GRP15]] 7992 // CHECK13-NEXT: [[TMP49:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]] 7993 // CHECK13-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP49]], 1 7994 // CHECK13-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]] 7995 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 2 7996 // CHECK13-NEXT: [[TMP50:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] 7997 // CHECK13-NEXT: [[CONV80:%.*]] = fpext float [[TMP50]] to double 7998 // CHECK13-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 7999 // CHECK13-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 8000 // CHECK13-NEXT: store float [[CONV82]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] 8001 // CHECK13-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 3 8002 // CHECK13-NEXT: [[TMP51:%.*]] = load float, ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]] 8003 // CHECK13-NEXT: [[CONV84:%.*]] = fpext float [[TMP51]] to double 8004 // CHECK13-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 8005 // CHECK13-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 8006 // CHECK13-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]] 8007 // CHECK13-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 1 8008 // CHECK13-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i64 0, i64 2 8009 // CHECK13-NEXT: [[TMP52:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] 8010 // CHECK13-NEXT: [[ADD89:%.*]] = fadd double [[TMP52]], 1.000000e+00 8011 // CHECK13-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] 8012 // CHECK13-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP4]] 8013 // CHECK13-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP53]] 8014 // CHECK13-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX90]], i64 3 8015 // CHECK13-NEXT: [[TMP54:%.*]] = load double, ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]] 8016 // CHECK13-NEXT: [[ADD92:%.*]] = fadd double [[TMP54]], 1.000000e+00 8017 // CHECK13-NEXT: store double [[ADD92]], ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]] 8018 // CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 8019 // CHECK13-NEXT: [[TMP55:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]] 8020 // CHECK13-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP55]], 1 8021 // CHECK13-NEXT: store i64 [[ADD93]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]] 8022 // CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 8023 // CHECK13-NEXT: [[TMP56:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]] 8024 // CHECK13-NEXT: [[CONV94:%.*]] = sext i8 [[TMP56]] to i32 8025 // CHECK13-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 8026 // CHECK13-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 8027 // CHECK13-NEXT: store i8 [[CONV96]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]] 8028 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 8029 // CHECK13: omp.body.continue97: 8030 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 8031 // CHECK13: omp.inner.for.inc98: 8032 // CHECK13-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 8033 // CHECK13-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 1 8034 // CHECK13-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 8035 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]] 8036 // CHECK13: omp.inner.for.end100: 8037 // CHECK13-NEXT: store i8 96, ptr [[IT72]], align 1 8038 // CHECK13-NEXT: [[TMP58:%.*]] = load i32, ptr [[A]], align 4 8039 // CHECK13-NEXT: [[TMP59:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 8040 // CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP59]]) 8041 // CHECK13-NEXT: ret i32 [[TMP58]] 8042 // 8043 // 8044 // CHECK13-LABEL: define {{[^@]+}}@_Z3bari 8045 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 8046 // CHECK13-NEXT: entry: 8047 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8048 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8049 // CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 8050 // CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8051 // CHECK13-NEXT: store i32 0, ptr [[A]], align 4 8052 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 8053 // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 8054 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 8055 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 8056 // CHECK13-NEXT: store i32 [[ADD]], ptr [[A]], align 4 8057 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 8058 // CHECK13-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 8059 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 8060 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 8061 // CHECK13-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 8062 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 8063 // CHECK13-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 8064 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 8065 // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 8066 // CHECK13-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 8067 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 8068 // CHECK13-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 8069 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 8070 // CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 8071 // CHECK13-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 8072 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 8073 // CHECK13-NEXT: ret i32 [[TMP8]] 8074 // 8075 // 8076 // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 8077 // CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 8078 // CHECK13-NEXT: entry: 8079 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 8080 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8081 // CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 8082 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 8083 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 8084 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 8085 // CHECK13-NEXT: [[TMP:%.*]] = alloca i64, align 8 8086 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8087 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8088 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8089 // CHECK13-NEXT: [[IT:%.*]] = alloca i64, align 8 8090 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 8091 // CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8092 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 8093 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 8094 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8095 // CHECK13-NEXT: store i32 [[ADD]], ptr [[B]], align 4 8096 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 8097 // CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 8098 // CHECK13-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() 8099 // CHECK13-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 8100 // CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 8101 // CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 8102 // CHECK13-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 8103 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 8104 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 8105 // CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 8106 // CHECK13-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 8107 // CHECK13-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 8108 // CHECK13-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 8109 // CHECK13-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 8110 // CHECK13-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 8111 // CHECK13-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 8112 // CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 8113 // CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8114 // CHECK13: omp_if.then: 8115 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8116 // CHECK13: omp.inner.for.cond: 8117 // CHECK13-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]] 8118 // CHECK13-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]] 8119 // CHECK13-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP8]], [[TMP9]] 8120 // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8121 // CHECK13: omp.inner.for.body: 8122 // CHECK13-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 8123 // CHECK13-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 400 8124 // CHECK13-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 8125 // CHECK13-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP18]] 8126 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP18]] 8127 // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP11]] to double 8128 // CHECK13-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 8129 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 8130 // CHECK13-NEXT: store double [[ADD3]], ptr [[A]], align 8, !nontemporal !19, !llvm.access.group [[ACC_GRP18]] 8131 // CHECK13-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 8132 // CHECK13-NEXT: [[TMP12:%.*]] = load double, ptr [[A4]], align 8, !nontemporal !19, !llvm.access.group [[ACC_GRP18]] 8133 // CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00 8134 // CHECK13-NEXT: store double [[INC]], ptr [[A4]], align 8, !nontemporal !19, !llvm.access.group [[ACC_GRP18]] 8135 // CHECK13-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 8136 // CHECK13-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] 8137 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP13]] 8138 // CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 8139 // CHECK13-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP18]] 8140 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8141 // CHECK13: omp.body.continue: 8142 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8143 // CHECK13: omp.inner.for.inc: 8144 // CHECK13-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 8145 // CHECK13-NEXT: [[ADD7:%.*]] = add i64 [[TMP14]], 1 8146 // CHECK13-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 8147 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 8148 // CHECK13: omp.inner.for.end: 8149 // CHECK13-NEXT: br label [[OMP_IF_END:%.*]] 8150 // CHECK13: omp_if.else: 8151 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]] 8152 // CHECK13: omp.inner.for.cond8: 8153 // CHECK13-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 8154 // CHECK13-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 8155 // CHECK13-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP15]], [[TMP16]] 8156 // CHECK13-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]] 8157 // CHECK13: omp.inner.for.body10: 8158 // CHECK13-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 8159 // CHECK13-NEXT: [[MUL11:%.*]] = mul i64 [[TMP17]], 400 8160 // CHECK13-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]] 8161 // CHECK13-NEXT: store i64 [[SUB12]], ptr [[IT]], align 8 8162 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[B]], align 4 8163 // CHECK13-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP18]] to double 8164 // CHECK13-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00 8165 // CHECK13-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 8166 // CHECK13-NEXT: store double [[ADD14]], ptr [[A15]], align 8 8167 // CHECK13-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 8168 // CHECK13-NEXT: [[TMP19:%.*]] = load double, ptr [[A16]], align 8 8169 // CHECK13-NEXT: [[INC17:%.*]] = fadd double [[TMP19]], 1.000000e+00 8170 // CHECK13-NEXT: store double [[INC17]], ptr [[A16]], align 8 8171 // CHECK13-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16 8172 // CHECK13-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]] 8173 // CHECK13-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP20]] 8174 // CHECK13-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX19]], i64 1 8175 // CHECK13-NEXT: store i16 [[CONV18]], ptr [[ARRAYIDX20]], align 2 8176 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]] 8177 // CHECK13: omp.body.continue21: 8178 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]] 8179 // CHECK13: omp.inner.for.inc22: 8180 // CHECK13-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 8181 // CHECK13-NEXT: [[ADD23:%.*]] = add i64 [[TMP21]], 1 8182 // CHECK13-NEXT: store i64 [[ADD23]], ptr [[DOTOMP_IV]], align 8 8183 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP22:![0-9]+]] 8184 // CHECK13: omp.inner.for.end24: 8185 // CHECK13-NEXT: br label [[OMP_IF_END]] 8186 // CHECK13: omp_if.end: 8187 // CHECK13-NEXT: store i64 400, ptr [[IT]], align 8 8188 // CHECK13-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]] 8189 // CHECK13-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP22]] 8190 // CHECK13-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX25]], i64 1 8191 // CHECK13-NEXT: [[TMP23:%.*]] = load i16, ptr [[ARRAYIDX26]], align 2 8192 // CHECK13-NEXT: [[CONV27:%.*]] = sext i16 [[TMP23]] to i32 8193 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, ptr [[B]], align 4 8194 // CHECK13-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP24]] 8195 // CHECK13-NEXT: [[TMP25:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 8196 // CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP25]]) 8197 // CHECK13-NEXT: ret i32 [[ADD28]] 8198 // 8199 // 8200 // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici 8201 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 8202 // CHECK13-NEXT: entry: 8203 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8204 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8205 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 8206 // CHECK13-NEXT: [[AAA:%.*]] = alloca i8, align 1 8207 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8208 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 8209 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8210 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8211 // CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8212 // CHECK13-NEXT: store i32 0, ptr [[A]], align 4 8213 // CHECK13-NEXT: store i16 0, ptr [[AA]], align 2 8214 // CHECK13-NEXT: store i8 0, ptr [[AAA]], align 1 8215 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 8216 // CHECK13-NEXT: store i32 429496720, ptr [[DOTOMP_UB]], align 4 8217 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 8218 // CHECK13-NEXT: ret i32 [[TMP0]] 8219 // 8220 // 8221 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 8222 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 8223 // CHECK13-NEXT: entry: 8224 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8225 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8226 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 8227 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8228 // CHECK13-NEXT: [[TMP:%.*]] = alloca i64, align 8 8229 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8230 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8231 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8232 // CHECK13-NEXT: [[I:%.*]] = alloca i64, align 8 8233 // CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8234 // CHECK13-NEXT: store i32 0, ptr [[A]], align 4 8235 // CHECK13-NEXT: store i16 0, ptr [[AA]], align 2 8236 // CHECK13-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 8237 // CHECK13-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 8238 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 8239 // CHECK13-NEXT: store i64 [[TMP0]], ptr [[DOTOMP_IV]], align 8 8240 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8241 // CHECK13: omp.inner.for.cond: 8242 // CHECK13-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24:![0-9]+]] 8243 // CHECK13-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP24]] 8244 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 8245 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8246 // CHECK13: omp.inner.for.body: 8247 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24]] 8248 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 8249 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 8250 // CHECK13-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP24]] 8251 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP24]] 8252 // CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 8253 // CHECK13-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP24]] 8254 // CHECK13-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP24]] 8255 // CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 8256 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 8257 // CHECK13-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 8258 // CHECK13-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP24]] 8259 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 8260 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 8261 // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 8262 // CHECK13-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 8263 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8264 // CHECK13: omp.body.continue: 8265 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8266 // CHECK13: omp.inner.for.inc: 8267 // CHECK13-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24]] 8268 // CHECK13-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 8269 // CHECK13-NEXT: store i64 [[ADD5]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24]] 8270 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 8271 // CHECK13: omp.inner.for.end: 8272 // CHECK13-NEXT: store i64 11, ptr [[I]], align 8 8273 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 8274 // CHECK13-NEXT: ret i32 [[TMP8]] 8275 // 8276 // 8277 // CHECK15-LABEL: define {{[^@]+}}@_Z7get_valv 8278 // CHECK15-SAME: () #[[ATTR0:[0-9]+]] { 8279 // CHECK15-NEXT: entry: 8280 // CHECK15-NEXT: ret i64 0 8281 // 8282 // 8283 // CHECK15-LABEL: define {{[^@]+}}@_Z3fooi 8284 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 8285 // CHECK15-NEXT: entry: 8286 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8287 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 8288 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 8289 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x float], align 4 8290 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 8291 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 8292 // CHECK15-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 8293 // CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 8294 // CHECK15-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 8295 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 8296 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8297 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8298 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8299 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 8300 // CHECK15-NEXT: [[K:%.*]] = alloca i64, align 8 8301 // CHECK15-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 8302 // CHECK15-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 8303 // CHECK15-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 8304 // CHECK15-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 8305 // CHECK15-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 8306 // CHECK15-NEXT: [[I7:%.*]] = alloca i32, align 4 8307 // CHECK15-NEXT: [[K8:%.*]] = alloca i64, align 8 8308 // CHECK15-NEXT: [[LIN:%.*]] = alloca i32, align 4 8309 // CHECK15-NEXT: [[_TMP20:%.*]] = alloca i64, align 4 8310 // CHECK15-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 8311 // CHECK15-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 8312 // CHECK15-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 8313 // CHECK15-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 8314 // CHECK15-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 8315 // CHECK15-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 8316 // CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 8 8317 // CHECK15-NEXT: [[LIN27:%.*]] = alloca i32, align 4 8318 // CHECK15-NEXT: [[A28:%.*]] = alloca i32, align 4 8319 // CHECK15-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 8320 // CHECK15-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 8321 // CHECK15-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 8322 // CHECK15-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 8323 // CHECK15-NEXT: [[IT53:%.*]] = alloca i16, align 2 8324 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 8325 // CHECK15-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 8326 // CHECK15-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 8327 // CHECK15-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 8328 // CHECK15-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 8329 // CHECK15-NEXT: [[IT72:%.*]] = alloca i8, align 1 8330 // CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8331 // CHECK15-NEXT: store i32 0, ptr [[A]], align 4 8332 // CHECK15-NEXT: store i16 0, ptr [[AA]], align 2 8333 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 8334 // CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() 8335 // CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 8336 // CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 8337 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 8338 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 8339 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 8340 // CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 8341 // CHECK15-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 8342 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 8343 // CHECK15-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 8344 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 8345 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 8346 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8347 // CHECK15: omp.inner.for.cond: 8348 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 8349 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 8350 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 8351 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8352 // CHECK15: omp.inner.for.body: 8353 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 8354 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 8355 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 8356 // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 8357 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8358 // CHECK15: omp.body.continue: 8359 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8360 // CHECK15: omp.inner.for.inc: 8361 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 8362 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 8363 // CHECK15-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 8364 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 8365 // CHECK15: omp.inner.for.end: 8366 // CHECK15-NEXT: store i32 33, ptr [[I]], align 4 8367 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 8368 // CHECK15-NEXT: store i64 [[CALL]], ptr [[K]], align 8 8369 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 4 8370 // CHECK15-NEXT: store i32 8, ptr [[DOTOMP_UB5]], align 4 8371 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 4 8372 // CHECK15-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV6]], align 4 8373 // CHECK15-NEXT: [[TMP10:%.*]] = load i64, ptr [[K]], align 8 8374 // CHECK15-NEXT: store i64 [[TMP10]], ptr [[DOTLINEAR_START]], align 8 8375 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 8376 // CHECK15: omp.inner.for.cond9: 8377 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 8378 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP7]] 8379 // CHECK15-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 8380 // CHECK15-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 8381 // CHECK15: omp.inner.for.body11: 8382 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 8383 // CHECK15-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1 8384 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 8385 // CHECK15-NEXT: store i32 [[SUB]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] 8386 // CHECK15-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP7]] 8387 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 8388 // CHECK15-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3 8389 // CHECK15-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 8390 // CHECK15-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]] 8391 // CHECK15-NEXT: store i64 [[ADD14]], ptr [[K8]], align 8, !llvm.access.group [[ACC_GRP7]] 8392 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP7]] 8393 // CHECK15-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 8394 // CHECK15-NEXT: store i32 [[ADD15]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP7]] 8395 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 8396 // CHECK15: omp.body.continue16: 8397 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 8398 // CHECK15: omp.inner.for.inc17: 8399 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 8400 // CHECK15-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 8401 // CHECK15-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 8402 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]] 8403 // CHECK15: omp.inner.for.end19: 8404 // CHECK15-NEXT: store i32 1, ptr [[I7]], align 4 8405 // CHECK15-NEXT: [[TMP18:%.*]] = load i64, ptr [[K8]], align 8 8406 // CHECK15-NEXT: store i64 [[TMP18]], ptr [[K]], align 8 8407 // CHECK15-NEXT: store i32 12, ptr [[LIN]], align 4 8408 // CHECK15-NEXT: store i64 0, ptr [[DOTOMP_LB21]], align 8 8409 // CHECK15-NEXT: store i64 3, ptr [[DOTOMP_UB22]], align 8 8410 // CHECK15-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_LB21]], align 8 8411 // CHECK15-NEXT: store i64 [[TMP19]], ptr [[DOTOMP_IV23]], align 8 8412 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN]], align 4 8413 // CHECK15-NEXT: store i32 [[TMP20]], ptr [[DOTLINEAR_START24]], align 4 8414 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 4 8415 // CHECK15-NEXT: store i32 [[TMP21]], ptr [[DOTLINEAR_START25]], align 4 8416 // CHECK15-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 8417 // CHECK15-NEXT: store i64 [[CALL26]], ptr [[DOTLINEAR_STEP]], align 8 8418 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 8419 // CHECK15: omp.inner.for.cond29: 8420 // CHECK15-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10:![0-9]+]] 8421 // CHECK15-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP10]] 8422 // CHECK15-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 8423 // CHECK15-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 8424 // CHECK15: omp.inner.for.body31: 8425 // CHECK15-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8426 // CHECK15-NEXT: [[MUL32:%.*]] = mul i64 [[TMP24]], 400 8427 // CHECK15-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 8428 // CHECK15-NEXT: store i64 [[SUB33]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP10]] 8429 // CHECK15-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP10]] 8430 // CHECK15-NEXT: [[CONV34:%.*]] = sext i32 [[TMP25]] to i64 8431 // CHECK15-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8432 // CHECK15-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]] 8433 // CHECK15-NEXT: [[MUL35:%.*]] = mul i64 [[TMP26]], [[TMP27]] 8434 // CHECK15-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 8435 // CHECK15-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 8436 // CHECK15-NEXT: store i32 [[CONV37]], ptr [[LIN27]], align 4, !llvm.access.group [[ACC_GRP10]] 8437 // CHECK15-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP10]] 8438 // CHECK15-NEXT: [[CONV38:%.*]] = sext i32 [[TMP28]] to i64 8439 // CHECK15-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8440 // CHECK15-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]] 8441 // CHECK15-NEXT: [[MUL39:%.*]] = mul i64 [[TMP29]], [[TMP30]] 8442 // CHECK15-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 8443 // CHECK15-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 8444 // CHECK15-NEXT: store i32 [[CONV41]], ptr [[A28]], align 4, !llvm.access.group [[ACC_GRP10]] 8445 // CHECK15-NEXT: [[TMP31:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]] 8446 // CHECK15-NEXT: [[CONV42:%.*]] = sext i16 [[TMP31]] to i32 8447 // CHECK15-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 8448 // CHECK15-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 8449 // CHECK15-NEXT: store i16 [[CONV44]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]] 8450 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 8451 // CHECK15: omp.body.continue45: 8452 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 8453 // CHECK15: omp.inner.for.inc46: 8454 // CHECK15-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8455 // CHECK15-NEXT: [[ADD47:%.*]] = add i64 [[TMP32]], 1 8456 // CHECK15-NEXT: store i64 [[ADD47]], ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8457 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP11:![0-9]+]] 8458 // CHECK15: omp.inner.for.end48: 8459 // CHECK15-NEXT: store i64 400, ptr [[IT]], align 8 8460 // CHECK15-NEXT: [[TMP33:%.*]] = load i32, ptr [[LIN27]], align 4 8461 // CHECK15-NEXT: store i32 [[TMP33]], ptr [[LIN]], align 4 8462 // CHECK15-NEXT: [[TMP34:%.*]] = load i32, ptr [[A28]], align 4 8463 // CHECK15-NEXT: store i32 [[TMP34]], ptr [[A]], align 4 8464 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB50]], align 4 8465 // CHECK15-NEXT: store i32 3, ptr [[DOTOMP_UB51]], align 4 8466 // CHECK15-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_LB50]], align 4 8467 // CHECK15-NEXT: store i32 [[TMP35]], ptr [[DOTOMP_IV52]], align 4 8468 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 8469 // CHECK15: omp.inner.for.cond54: 8470 // CHECK15-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] 8471 // CHECK15-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP13]] 8472 // CHECK15-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP36]], [[TMP37]] 8473 // CHECK15-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 8474 // CHECK15: omp.inner.for.body56: 8475 // CHECK15-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 8476 // CHECK15-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP38]], 4 8477 // CHECK15-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 8478 // CHECK15-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 8479 // CHECK15-NEXT: store i16 [[CONV59]], ptr [[IT53]], align 2, !llvm.access.group [[ACC_GRP13]] 8480 // CHECK15-NEXT: [[TMP39:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]] 8481 // CHECK15-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP39]], 1 8482 // CHECK15-NEXT: store i32 [[ADD60]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]] 8483 // CHECK15-NEXT: [[TMP40:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]] 8484 // CHECK15-NEXT: [[CONV61:%.*]] = sext i16 [[TMP40]] to i32 8485 // CHECK15-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 8486 // CHECK15-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 8487 // CHECK15-NEXT: store i16 [[CONV63]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]] 8488 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 8489 // CHECK15: omp.body.continue64: 8490 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 8491 // CHECK15: omp.inner.for.inc65: 8492 // CHECK15-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 8493 // CHECK15-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP41]], 1 8494 // CHECK15-NEXT: store i32 [[ADD66]], ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 8495 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP14:![0-9]+]] 8496 // CHECK15: omp.inner.for.end67: 8497 // CHECK15-NEXT: store i16 22, ptr [[IT53]], align 2 8498 // CHECK15-NEXT: [[TMP42:%.*]] = load i32, ptr [[A]], align 4 8499 // CHECK15-NEXT: store i32 [[TMP42]], ptr [[DOTCAPTURE_EXPR_]], align 4 8500 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB69]], align 4 8501 // CHECK15-NEXT: store i32 25, ptr [[DOTOMP_UB70]], align 4 8502 // CHECK15-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_LB69]], align 4 8503 // CHECK15-NEXT: store i32 [[TMP43]], ptr [[DOTOMP_IV71]], align 4 8504 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 8505 // CHECK15: omp.inner.for.cond73: 8506 // CHECK15-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] 8507 // CHECK15-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP16]] 8508 // CHECK15-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP44]], [[TMP45]] 8509 // CHECK15-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 8510 // CHECK15: omp.inner.for.body75: 8511 // CHECK15-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 8512 // CHECK15-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP46]], 1 8513 // CHECK15-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 8514 // CHECK15-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 8515 // CHECK15-NEXT: store i8 [[CONV78]], ptr [[IT72]], align 1, !llvm.access.group [[ACC_GRP16]] 8516 // CHECK15-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] 8517 // CHECK15-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP47]], 1 8518 // CHECK15-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] 8519 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 2 8520 // CHECK15-NEXT: [[TMP48:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] 8521 // CHECK15-NEXT: [[CONV80:%.*]] = fpext float [[TMP48]] to double 8522 // CHECK15-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 8523 // CHECK15-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 8524 // CHECK15-NEXT: store float [[CONV82]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] 8525 // CHECK15-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 3 8526 // CHECK15-NEXT: [[TMP49:%.*]] = load float, ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]] 8527 // CHECK15-NEXT: [[CONV84:%.*]] = fpext float [[TMP49]] to double 8528 // CHECK15-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 8529 // CHECK15-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 8530 // CHECK15-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]] 8531 // CHECK15-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 1 8532 // CHECK15-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i32 0, i32 2 8533 // CHECK15-NEXT: [[TMP50:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] 8534 // CHECK15-NEXT: [[ADD89:%.*]] = fadd double [[TMP50]], 1.000000e+00 8535 // CHECK15-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] 8536 // CHECK15-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP2]] 8537 // CHECK15-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP51]] 8538 // CHECK15-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX90]], i32 3 8539 // CHECK15-NEXT: [[TMP52:%.*]] = load double, ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]] 8540 // CHECK15-NEXT: [[ADD92:%.*]] = fadd double [[TMP52]], 1.000000e+00 8541 // CHECK15-NEXT: store double [[ADD92]], ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]] 8542 // CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 8543 // CHECK15-NEXT: [[TMP53:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]] 8544 // CHECK15-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP53]], 1 8545 // CHECK15-NEXT: store i64 [[ADD93]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]] 8546 // CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 8547 // CHECK15-NEXT: [[TMP54:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]] 8548 // CHECK15-NEXT: [[CONV94:%.*]] = sext i8 [[TMP54]] to i32 8549 // CHECK15-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 8550 // CHECK15-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 8551 // CHECK15-NEXT: store i8 [[CONV96]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]] 8552 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 8553 // CHECK15: omp.body.continue97: 8554 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 8555 // CHECK15: omp.inner.for.inc98: 8556 // CHECK15-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 8557 // CHECK15-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 1 8558 // CHECK15-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 8559 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]] 8560 // CHECK15: omp.inner.for.end100: 8561 // CHECK15-NEXT: store i8 96, ptr [[IT72]], align 1 8562 // CHECK15-NEXT: [[TMP56:%.*]] = load i32, ptr [[A]], align 4 8563 // CHECK15-NEXT: [[TMP57:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 8564 // CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP57]]) 8565 // CHECK15-NEXT: ret i32 [[TMP56]] 8566 // 8567 // 8568 // CHECK15-LABEL: define {{[^@]+}}@_Z3bari 8569 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 8570 // CHECK15-NEXT: entry: 8571 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8572 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 8573 // CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 8574 // CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8575 // CHECK15-NEXT: store i32 0, ptr [[A]], align 4 8576 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 8577 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 8578 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 8579 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 8580 // CHECK15-NEXT: store i32 [[ADD]], ptr [[A]], align 4 8581 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 8582 // CHECK15-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 8583 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 8584 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 8585 // CHECK15-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 8586 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 8587 // CHECK15-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 8588 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 8589 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 8590 // CHECK15-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 8591 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 8592 // CHECK15-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 8593 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 8594 // CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 8595 // CHECK15-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 8596 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 8597 // CHECK15-NEXT: ret i32 [[TMP8]] 8598 // 8599 // 8600 // CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 8601 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 8602 // CHECK15-NEXT: entry: 8603 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 8604 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8605 // CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 8606 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 8607 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 8608 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 8609 // CHECK15-NEXT: [[TMP:%.*]] = alloca i64, align 4 8610 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8611 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8612 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8613 // CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 8 8614 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 8615 // CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8616 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 8617 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 8618 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8619 // CHECK15-NEXT: store i32 [[ADD]], ptr [[B]], align 4 8620 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 8621 // CHECK15-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() 8622 // CHECK15-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 8623 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 8624 // CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 8625 // CHECK15-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 8626 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 8627 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 8628 // CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 8629 // CHECK15-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 8630 // CHECK15-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 8631 // CHECK15-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 8632 // CHECK15-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 8633 // CHECK15-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 8634 // CHECK15-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 8635 // CHECK15-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 8636 // CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8637 // CHECK15: omp_if.then: 8638 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8639 // CHECK15: omp.inner.for.cond: 8640 // CHECK15-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19:![0-9]+]] 8641 // CHECK15-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP19]] 8642 // CHECK15-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 8643 // CHECK15-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8644 // CHECK15: omp.inner.for.body: 8645 // CHECK15-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 8646 // CHECK15-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 8647 // CHECK15-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 8648 // CHECK15-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP19]] 8649 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP19]] 8650 // CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double 8651 // CHECK15-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 8652 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 8653 // CHECK15-NEXT: store double [[ADD3]], ptr [[A]], align 4, !nontemporal !20, !llvm.access.group [[ACC_GRP19]] 8654 // CHECK15-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 8655 // CHECK15-NEXT: [[TMP11:%.*]] = load double, ptr [[A4]], align 4, !nontemporal !20, !llvm.access.group [[ACC_GRP19]] 8656 // CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 8657 // CHECK15-NEXT: store double [[INC]], ptr [[A4]], align 4, !nontemporal !20, !llvm.access.group [[ACC_GRP19]] 8658 // CHECK15-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 8659 // CHECK15-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] 8660 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP12]] 8661 // CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 8662 // CHECK15-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP19]] 8663 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8664 // CHECK15: omp.body.continue: 8665 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8666 // CHECK15: omp.inner.for.inc: 8667 // CHECK15-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 8668 // CHECK15-NEXT: [[ADD7:%.*]] = add i64 [[TMP13]], 1 8669 // CHECK15-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 8670 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 8671 // CHECK15: omp.inner.for.end: 8672 // CHECK15-NEXT: br label [[OMP_IF_END:%.*]] 8673 // CHECK15: omp_if.else: 8674 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]] 8675 // CHECK15: omp.inner.for.cond8: 8676 // CHECK15-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 8677 // CHECK15-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 8678 // CHECK15-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP14]], [[TMP15]] 8679 // CHECK15-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]] 8680 // CHECK15: omp.inner.for.body10: 8681 // CHECK15-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 8682 // CHECK15-NEXT: [[MUL11:%.*]] = mul i64 [[TMP16]], 400 8683 // CHECK15-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]] 8684 // CHECK15-NEXT: store i64 [[SUB12]], ptr [[IT]], align 8 8685 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[B]], align 4 8686 // CHECK15-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP17]] to double 8687 // CHECK15-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00 8688 // CHECK15-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 8689 // CHECK15-NEXT: store double [[ADD14]], ptr [[A15]], align 4 8690 // CHECK15-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 8691 // CHECK15-NEXT: [[TMP18:%.*]] = load double, ptr [[A16]], align 4 8692 // CHECK15-NEXT: [[INC17:%.*]] = fadd double [[TMP18]], 1.000000e+00 8693 // CHECK15-NEXT: store double [[INC17]], ptr [[A16]], align 4 8694 // CHECK15-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16 8695 // CHECK15-NEXT: [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]] 8696 // CHECK15-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP19]] 8697 // CHECK15-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX19]], i32 1 8698 // CHECK15-NEXT: store i16 [[CONV18]], ptr [[ARRAYIDX20]], align 2 8699 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]] 8700 // CHECK15: omp.body.continue21: 8701 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]] 8702 // CHECK15: omp.inner.for.inc22: 8703 // CHECK15-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 8704 // CHECK15-NEXT: [[ADD23:%.*]] = add i64 [[TMP20]], 1 8705 // CHECK15-NEXT: store i64 [[ADD23]], ptr [[DOTOMP_IV]], align 8 8706 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP23:![0-9]+]] 8707 // CHECK15: omp.inner.for.end24: 8708 // CHECK15-NEXT: br label [[OMP_IF_END]] 8709 // CHECK15: omp_if.end: 8710 // CHECK15-NEXT: store i64 400, ptr [[IT]], align 8 8711 // CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]] 8712 // CHECK15-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP21]] 8713 // CHECK15-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX25]], i32 1 8714 // CHECK15-NEXT: [[TMP22:%.*]] = load i16, ptr [[ARRAYIDX26]], align 2 8715 // CHECK15-NEXT: [[CONV27:%.*]] = sext i16 [[TMP22]] to i32 8716 // CHECK15-NEXT: [[TMP23:%.*]] = load i32, ptr [[B]], align 4 8717 // CHECK15-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP23]] 8718 // CHECK15-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 8719 // CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP24]]) 8720 // CHECK15-NEXT: ret i32 [[ADD28]] 8721 // 8722 // 8723 // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici 8724 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 8725 // CHECK15-NEXT: entry: 8726 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8727 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 8728 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 8729 // CHECK15-NEXT: [[AAA:%.*]] = alloca i8, align 1 8730 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8731 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 8732 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8733 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8734 // CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8735 // CHECK15-NEXT: store i32 0, ptr [[A]], align 4 8736 // CHECK15-NEXT: store i16 0, ptr [[AA]], align 2 8737 // CHECK15-NEXT: store i8 0, ptr [[AAA]], align 1 8738 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 8739 // CHECK15-NEXT: store i32 429496720, ptr [[DOTOMP_UB]], align 4 8740 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 8741 // CHECK15-NEXT: ret i32 [[TMP0]] 8742 // 8743 // 8744 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 8745 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 8746 // CHECK15-NEXT: entry: 8747 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8748 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 8749 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 8750 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8751 // CHECK15-NEXT: [[TMP:%.*]] = alloca i64, align 4 8752 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8753 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8754 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8755 // CHECK15-NEXT: [[I:%.*]] = alloca i64, align 8 8756 // CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8757 // CHECK15-NEXT: store i32 0, ptr [[A]], align 4 8758 // CHECK15-NEXT: store i16 0, ptr [[AA]], align 2 8759 // CHECK15-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 8760 // CHECK15-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 8761 // CHECK15-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 8762 // CHECK15-NEXT: store i64 [[TMP0]], ptr [[DOTOMP_IV]], align 8 8763 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8764 // CHECK15: omp.inner.for.cond: 8765 // CHECK15-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25:![0-9]+]] 8766 // CHECK15-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP25]] 8767 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 8768 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8769 // CHECK15: omp.inner.for.body: 8770 // CHECK15-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25]] 8771 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 8772 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 8773 // CHECK15-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP25]] 8774 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP25]] 8775 // CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 8776 // CHECK15-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP25]] 8777 // CHECK15-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP25]] 8778 // CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 8779 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 8780 // CHECK15-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 8781 // CHECK15-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP25]] 8782 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 8783 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] 8784 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 8785 // CHECK15-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] 8786 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8787 // CHECK15: omp.body.continue: 8788 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8789 // CHECK15: omp.inner.for.inc: 8790 // CHECK15-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25]] 8791 // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 8792 // CHECK15-NEXT: store i64 [[ADD5]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25]] 8793 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] 8794 // CHECK15: omp.inner.for.end: 8795 // CHECK15-NEXT: store i64 11, ptr [[I]], align 8 8796 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 8797 // CHECK15-NEXT: ret i32 [[TMP8]] 8798 // 8799 // 8800 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 8801 // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { 8802 // CHECK17-NEXT: entry: 8803 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @.omp_outlined.) 8804 // CHECK17-NEXT: ret void 8805 // 8806 // 8807 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 8808 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 8809 // CHECK17-NEXT: entry: 8810 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 8811 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 8812 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8813 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 8814 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8815 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8816 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 8817 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8818 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 8819 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 8820 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 8821 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 8822 // CHECK17-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 8823 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 8824 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 8825 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 8826 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 8827 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 8828 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 8829 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 8830 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8831 // CHECK17: cond.true: 8832 // CHECK17-NEXT: br label [[COND_END:%.*]] 8833 // CHECK17: cond.false: 8834 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 8835 // CHECK17-NEXT: br label [[COND_END]] 8836 // CHECK17: cond.end: 8837 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 8838 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 8839 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 8840 // CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 8841 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8842 // CHECK17: omp.inner.for.cond: 8843 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 8844 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 8845 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 8846 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8847 // CHECK17: omp.inner.for.body: 8848 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 8849 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 8850 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 8851 // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 8852 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8853 // CHECK17: omp.body.continue: 8854 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8855 // CHECK17: omp.inner.for.inc: 8856 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 8857 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 8858 // CHECK17-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 8859 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 8860 // CHECK17: omp.inner.for.end: 8861 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8862 // CHECK17: omp.loop.exit: 8863 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 8864 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 8865 // CHECK17-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 8866 // CHECK17-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 8867 // CHECK17: .omp.final.then: 8868 // CHECK17-NEXT: store i32 33, ptr [[I]], align 4 8869 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 8870 // CHECK17: .omp.final.done: 8871 // CHECK17-NEXT: ret void 8872 // 8873 // 8874 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 8875 // CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 8876 // CHECK17-NEXT: entry: 8877 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8878 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 8879 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8880 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 8881 // CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 8882 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 8883 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 8884 // CHECK17-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 8885 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 8886 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 8887 // CHECK17-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 8888 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 8889 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 8890 // CHECK17-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 8891 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 8892 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 8893 // CHECK17-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 8894 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8 8895 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..1, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 8896 // CHECK17-NEXT: ret void 8897 // 8898 // 8899 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 8900 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 8901 // CHECK17-NEXT: entry: 8902 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 8903 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 8904 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8905 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 8906 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8907 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8908 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 8909 // CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 8910 // CHECK17-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 8911 // CHECK17-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 8912 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8913 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8914 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 8915 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8916 // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 8917 // CHECK17-NEXT: [[LIN2:%.*]] = alloca i32, align 4 8918 // CHECK17-NEXT: [[A3:%.*]] = alloca i32, align 4 8919 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 8920 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 8921 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 8922 // CHECK17-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 8923 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 8924 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 8925 // CHECK17-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 8926 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 8927 // CHECK17-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 8928 // CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 8929 // CHECK17-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 8930 // CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 8931 // CHECK17-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 8932 // CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 8933 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 8934 // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 8935 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 8936 // CHECK17-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 8937 // CHECK17-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 8938 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 8939 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 8940 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8941 // CHECK17: cond.true: 8942 // CHECK17-NEXT: br label [[COND_END:%.*]] 8943 // CHECK17: cond.false: 8944 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 8945 // CHECK17-NEXT: br label [[COND_END]] 8946 // CHECK17: cond.end: 8947 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 8948 // CHECK17-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 8949 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 8950 // CHECK17-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 8951 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8952 // CHECK17: omp.inner.for.cond: 8953 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17:![0-9]+]] 8954 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP17]] 8955 // CHECK17-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 8956 // CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8957 // CHECK17: omp.inner.for.body: 8958 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 8959 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 8960 // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 8961 // CHECK17-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP17]] 8962 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP17]] 8963 // CHECK17-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 8964 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 8965 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]] 8966 // CHECK17-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 8967 // CHECK17-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 8968 // CHECK17-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 8969 // CHECK17-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP17]] 8970 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP17]] 8971 // CHECK17-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 8972 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 8973 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]] 8974 // CHECK17-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 8975 // CHECK17-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 8976 // CHECK17-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 8977 // CHECK17-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP17]] 8978 // CHECK17-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP17]] 8979 // CHECK17-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 8980 // CHECK17-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 8981 // CHECK17-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 8982 // CHECK17-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP17]] 8983 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8984 // CHECK17: omp.body.continue: 8985 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8986 // CHECK17: omp.inner.for.inc: 8987 // CHECK17-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 8988 // CHECK17-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 8989 // CHECK17-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 8990 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 8991 // CHECK17: omp.inner.for.end: 8992 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8993 // CHECK17: omp.loop.exit: 8994 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 8995 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 8996 // CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 8997 // CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 8998 // CHECK17: .omp.final.then: 8999 // CHECK17-NEXT: store i64 400, ptr [[IT]], align 8 9000 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9001 // CHECK17: .omp.final.done: 9002 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9003 // CHECK17-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 9004 // CHECK17-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 9005 // CHECK17: .omp.linear.pu: 9006 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 9007 // CHECK17-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 9008 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 9009 // CHECK17-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 9010 // CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 9011 // CHECK17: .omp.linear.pu.done: 9012 // CHECK17-NEXT: ret void 9013 // 9014 // 9015 // CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv 9016 // CHECK17-SAME: () #[[ATTR3:[0-9]+]] { 9017 // CHECK17-NEXT: entry: 9018 // CHECK17-NEXT: ret i64 0 9019 // 9020 // 9021 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 9022 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 9023 // CHECK17-NEXT: entry: 9024 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9025 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9026 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9027 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9028 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9029 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9030 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 9031 // CHECK17-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 9032 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 9033 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 9034 // CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 9035 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 9036 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..2, i64 [[TMP1]], i64 [[TMP3]]) 9037 // CHECK17-NEXT: ret void 9038 // 9039 // 9040 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 9041 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 9042 // CHECK17-NEXT: entry: 9043 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 9044 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 9045 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9046 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9047 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9048 // CHECK17-NEXT: [[TMP:%.*]] = alloca i16, align 2 9049 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9050 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9051 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9052 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9053 // CHECK17-NEXT: [[IT:%.*]] = alloca i16, align 2 9054 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 9055 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 9056 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9057 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9058 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 9059 // CHECK17-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 9060 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 9061 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9062 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 9063 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 9064 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 9065 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9066 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 9067 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9068 // CHECK17: cond.true: 9069 // CHECK17-NEXT: br label [[COND_END:%.*]] 9070 // CHECK17: cond.false: 9071 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9072 // CHECK17-NEXT: br label [[COND_END]] 9073 // CHECK17: cond.end: 9074 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9075 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 9076 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 9077 // CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 9078 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9079 // CHECK17: omp.inner.for.cond: 9080 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] 9081 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] 9082 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9083 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9084 // CHECK17: omp.inner.for.body: 9085 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 9086 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 9087 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 9088 // CHECK17-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 9089 // CHECK17-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP20]] 9090 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]] 9091 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 9092 // CHECK17-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]] 9093 // CHECK17-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP20]] 9094 // CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 9095 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 9096 // CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 9097 // CHECK17-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP20]] 9098 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9099 // CHECK17: omp.body.continue: 9100 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9101 // CHECK17: omp.inner.for.inc: 9102 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 9103 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 9104 // CHECK17-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 9105 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 9106 // CHECK17: omp.inner.for.end: 9107 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9108 // CHECK17: omp.loop.exit: 9109 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 9110 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9111 // CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 9112 // CHECK17-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9113 // CHECK17: .omp.final.then: 9114 // CHECK17-NEXT: store i16 22, ptr [[IT]], align 2 9115 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9116 // CHECK17: .omp.final.done: 9117 // CHECK17-NEXT: ret void 9118 // 9119 // 9120 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 9121 // CHECK17-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 9122 // CHECK17-NEXT: entry: 9123 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9124 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 9125 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9126 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 9127 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 9128 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9129 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 9130 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 9131 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 9132 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 9133 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9134 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 9135 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9136 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 9137 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 9138 // CHECK17-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 9139 // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 9140 // CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 9141 // CHECK17-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 9142 // CHECK17-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 9143 // CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 9144 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 9145 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 9146 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 9147 // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 9148 // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 9149 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 9150 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 9151 // CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 9152 // CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 9153 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 9154 // CHECK17-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 9155 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 9156 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 9157 // CHECK17-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 9158 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 9159 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @.omp_outlined..3, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]]) 9160 // CHECK17-NEXT: ret void 9161 // 9162 // 9163 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 9164 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 9165 // CHECK17-NEXT: entry: 9166 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 9167 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 9168 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9169 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 9170 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9171 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 9172 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 9173 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9174 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 9175 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 9176 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 9177 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 9178 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9179 // CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1 9180 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9181 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9182 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9183 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9184 // CHECK17-NEXT: [[IT:%.*]] = alloca i8, align 1 9185 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 9186 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 9187 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9188 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 9189 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 9190 // CHECK17-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 9191 // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 9192 // CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 9193 // CHECK17-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 9194 // CHECK17-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 9195 // CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 9196 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 9197 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 9198 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 9199 // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 9200 // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 9201 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 9202 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 9203 // CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 9204 // CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 9205 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 9206 // CHECK17-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 9207 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 9208 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9209 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 9210 // CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 9211 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 9212 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 9213 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 9214 // CHECK17: omp.dispatch.cond: 9215 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9216 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 9217 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9218 // CHECK17: cond.true: 9219 // CHECK17-NEXT: br label [[COND_END:%.*]] 9220 // CHECK17: cond.false: 9221 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9222 // CHECK17-NEXT: br label [[COND_END]] 9223 // CHECK17: cond.end: 9224 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 9225 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 9226 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 9227 // CHECK17-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 9228 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 9229 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9230 // CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 9231 // CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 9232 // CHECK17: omp.dispatch.body: 9233 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9234 // CHECK17: omp.inner.for.cond: 9235 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] 9236 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] 9237 // CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 9238 // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9239 // CHECK17: omp.inner.for.body: 9240 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 9241 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 9242 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 9243 // CHECK17-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 9244 // CHECK17-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP23]] 9245 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] 9246 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 9247 // CHECK17-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] 9248 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 9249 // CHECK17-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] 9250 // CHECK17-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 9251 // CHECK17-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 9252 // CHECK17-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 9253 // CHECK17-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] 9254 // CHECK17-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 9255 // CHECK17-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]] 9256 // CHECK17-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 9257 // CHECK17-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 9258 // CHECK17-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 9259 // CHECK17-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]] 9260 // CHECK17-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 9261 // CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 9262 // CHECK17-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] 9263 // CHECK17-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 9264 // CHECK17-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] 9265 // CHECK17-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 9266 // CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]] 9267 // CHECK17-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3 9268 // CHECK17-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]] 9269 // CHECK17-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 9270 // CHECK17-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]] 9271 // CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 9272 // CHECK17-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP23]] 9273 // CHECK17-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 9274 // CHECK17-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP23]] 9275 // CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 9276 // CHECK17-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP23]] 9277 // CHECK17-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 9278 // CHECK17-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 9279 // CHECK17-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 9280 // CHECK17-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP23]] 9281 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9282 // CHECK17: omp.body.continue: 9283 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9284 // CHECK17: omp.inner.for.inc: 9285 // CHECK17-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 9286 // CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 9287 // CHECK17-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 9288 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] 9289 // CHECK17: omp.inner.for.end: 9290 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 9291 // CHECK17: omp.dispatch.inc: 9292 // CHECK17-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 9293 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 9294 // CHECK17-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 9295 // CHECK17-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 9296 // CHECK17-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9297 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 9298 // CHECK17-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 9299 // CHECK17-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 9300 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 9301 // CHECK17: omp.dispatch.end: 9302 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 9303 // CHECK17-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9304 // CHECK17-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 9305 // CHECK17-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9306 // CHECK17: .omp.final.then: 9307 // CHECK17-NEXT: store i8 96, ptr [[IT]], align 1 9308 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9309 // CHECK17: .omp.final.done: 9310 // CHECK17-NEXT: ret void 9311 // 9312 // 9313 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 9314 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 9315 // CHECK17-NEXT: entry: 9316 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9317 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9318 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 9319 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 9320 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9321 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9322 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 9323 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9324 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9325 // CHECK17-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 9326 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 9327 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 9328 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 9329 // CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 9330 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 9331 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 9332 // CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 9333 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 9334 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 9335 // CHECK17-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 9336 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 9337 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @.omp_outlined..4, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]]) 9338 // CHECK17-NEXT: ret void 9339 // 9340 // 9341 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 9342 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 9343 // CHECK17-NEXT: entry: 9344 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 9345 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 9346 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9347 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9348 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 9349 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 9350 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9351 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 9352 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 9353 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 9354 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9355 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9356 // CHECK17-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 9357 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 9358 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 9359 // CHECK17-NEXT: ret void 9360 // 9361 // 9362 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 9363 // CHECK17-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 9364 // CHECK17-NEXT: entry: 9365 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 9366 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 9367 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9368 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9369 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 9370 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 9371 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 9372 // CHECK17-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 9373 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 9374 // CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 9375 // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 9376 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 9377 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 9378 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 9379 // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 9380 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 9381 // CHECK17-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 9382 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8 9383 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @.omp_outlined..5, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) 9384 // CHECK17-NEXT: ret void 9385 // 9386 // 9387 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 9388 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 9389 // CHECK17-NEXT: entry: 9390 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 9391 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 9392 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 9393 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 9394 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9395 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9396 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 9397 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9398 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 9399 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9400 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9401 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9402 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9403 // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 9404 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 9405 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 9406 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 9407 // CHECK17-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 9408 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 9409 // CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 9410 // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 9411 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 9412 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 9413 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 9414 // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 9415 // CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 9416 // CHECK17-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 9417 // CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 9418 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9419 // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 9420 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 9421 // CHECK17-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 9422 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9423 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 9424 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9425 // CHECK17: cond.true: 9426 // CHECK17-NEXT: br label [[COND_END:%.*]] 9427 // CHECK17: cond.false: 9428 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9429 // CHECK17-NEXT: br label [[COND_END]] 9430 // CHECK17: cond.end: 9431 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 9432 // CHECK17-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 9433 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 9434 // CHECK17-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8 9435 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9436 // CHECK17: omp.inner.for.cond: 9437 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26:![0-9]+]] 9438 // CHECK17-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP26]] 9439 // CHECK17-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 9440 // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9441 // CHECK17: omp.inner.for.body: 9442 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 9443 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 9444 // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 9445 // CHECK17-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP26]] 9446 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] 9447 // CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 9448 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 9449 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 9450 // CHECK17-NEXT: store double [[ADD]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP26]] 9451 // CHECK17-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 9452 // CHECK17-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP26]] 9453 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 9454 // CHECK17-NEXT: store double [[INC]], ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP26]] 9455 // CHECK17-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 9456 // CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 9457 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]] 9458 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 9459 // CHECK17-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP26]] 9460 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9461 // CHECK17: omp.body.continue: 9462 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9463 // CHECK17: omp.inner.for.inc: 9464 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 9465 // CHECK17-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 9466 // CHECK17-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 9467 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] 9468 // CHECK17: omp.inner.for.end: 9469 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9470 // CHECK17: omp.loop.exit: 9471 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 9472 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9473 // CHECK17-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 9474 // CHECK17-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9475 // CHECK17: .omp.final.then: 9476 // CHECK17-NEXT: store i64 400, ptr [[IT]], align 8 9477 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9478 // CHECK17: .omp.final.done: 9479 // CHECK17-NEXT: ret void 9480 // 9481 // 9482 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 9483 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 9484 // CHECK17-NEXT: entry: 9485 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9486 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9487 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 9488 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9489 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9490 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9491 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9492 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 9493 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 9494 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 9495 // CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 9496 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 9497 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 9498 // CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 9499 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 9500 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..6, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) 9501 // CHECK17-NEXT: ret void 9502 // 9503 // 9504 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 9505 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 9506 // CHECK17-NEXT: entry: 9507 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 9508 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 9509 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9510 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9511 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 9512 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9513 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 9514 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9515 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9516 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9517 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9518 // CHECK17-NEXT: [[I:%.*]] = alloca i64, align 8 9519 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 9520 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 9521 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9522 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9523 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 9524 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 9525 // CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 9526 // CHECK17-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 9527 // CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 9528 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9529 // CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 9530 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 9531 // CHECK17-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 9532 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9533 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 9534 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9535 // CHECK17: cond.true: 9536 // CHECK17-NEXT: br label [[COND_END:%.*]] 9537 // CHECK17: cond.false: 9538 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9539 // CHECK17-NEXT: br label [[COND_END]] 9540 // CHECK17: cond.end: 9541 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 9542 // CHECK17-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 9543 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 9544 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 9545 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9546 // CHECK17: omp.inner.for.cond: 9547 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29:![0-9]+]] 9548 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP29]] 9549 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 9550 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9551 // CHECK17: omp.inner.for.body: 9552 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 9553 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 9554 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 9555 // CHECK17-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP29]] 9556 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP29]] 9557 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 9558 // CHECK17-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP29]] 9559 // CHECK17-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] 9560 // CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 9561 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 9562 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 9563 // CHECK17-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] 9564 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 9565 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP29]] 9566 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 9567 // CHECK17-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP29]] 9568 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9569 // CHECK17: omp.body.continue: 9570 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9571 // CHECK17: omp.inner.for.inc: 9572 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 9573 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 9574 // CHECK17-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 9575 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] 9576 // CHECK17: omp.inner.for.end: 9577 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9578 // CHECK17: omp.loop.exit: 9579 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 9580 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9581 // CHECK17-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 9582 // CHECK17-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9583 // CHECK17: .omp.final.then: 9584 // CHECK17-NEXT: store i64 11, ptr [[I]], align 8 9585 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9586 // CHECK17: .omp.final.done: 9587 // CHECK17-NEXT: ret void 9588 // 9589 // 9590 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 9591 // CHECK19-SAME: () #[[ATTR0:[0-9]+]] { 9592 // CHECK19-NEXT: entry: 9593 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @.omp_outlined.) 9594 // CHECK19-NEXT: ret void 9595 // 9596 // 9597 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 9598 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 9599 // CHECK19-NEXT: entry: 9600 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 9601 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 9602 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9603 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 9604 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9605 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9606 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9607 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9608 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 9609 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 9610 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 9611 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 9612 // CHECK19-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 9613 // CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 9614 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9615 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 9616 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 9617 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 9618 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9619 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 9620 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9621 // CHECK19: cond.true: 9622 // CHECK19-NEXT: br label [[COND_END:%.*]] 9623 // CHECK19: cond.false: 9624 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9625 // CHECK19-NEXT: br label [[COND_END]] 9626 // CHECK19: cond.end: 9627 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9628 // CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 9629 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 9630 // CHECK19-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 9631 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9632 // CHECK19: omp.inner.for.cond: 9633 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 9634 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] 9635 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9636 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9637 // CHECK19: omp.inner.for.body: 9638 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 9639 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 9640 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 9641 // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] 9642 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9643 // CHECK19: omp.body.continue: 9644 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9645 // CHECK19: omp.inner.for.inc: 9646 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 9647 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 9648 // CHECK19-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 9649 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 9650 // CHECK19: omp.inner.for.end: 9651 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9652 // CHECK19: omp.loop.exit: 9653 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 9654 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9655 // CHECK19-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 9656 // CHECK19-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9657 // CHECK19: .omp.final.then: 9658 // CHECK19-NEXT: store i32 33, ptr [[I]], align 4 9659 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 9660 // CHECK19: .omp.final.done: 9661 // CHECK19-NEXT: ret void 9662 // 9663 // 9664 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 9665 // CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 9666 // CHECK19-NEXT: entry: 9667 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9668 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 9669 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9670 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9671 // CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 9672 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9673 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 9674 // CHECK19-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 9675 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 9676 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 9677 // CHECK19-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 9678 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 9679 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 9680 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 9681 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 9682 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 9683 // CHECK19-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 9684 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4 9685 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..1, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 9686 // CHECK19-NEXT: ret void 9687 // 9688 // 9689 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 9690 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 9691 // CHECK19-NEXT: entry: 9692 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 9693 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 9694 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9695 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 9696 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9697 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9698 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 9699 // CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 9700 // CHECK19-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 9701 // CHECK19-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 9702 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9703 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9704 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9705 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9706 // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 9707 // CHECK19-NEXT: [[LIN2:%.*]] = alloca i32, align 4 9708 // CHECK19-NEXT: [[A3:%.*]] = alloca i32, align 4 9709 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 9710 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 9711 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 9712 // CHECK19-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 9713 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 9714 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 9715 // CHECK19-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 9716 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 9717 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 9718 // CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 9719 // CHECK19-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 9720 // CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 9721 // CHECK19-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 9722 // CHECK19-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 9723 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9724 // CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 9725 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 9726 // CHECK19-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 9727 // CHECK19-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 9728 // CHECK19-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9729 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 9730 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9731 // CHECK19: cond.true: 9732 // CHECK19-NEXT: br label [[COND_END:%.*]] 9733 // CHECK19: cond.false: 9734 // CHECK19-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9735 // CHECK19-NEXT: br label [[COND_END]] 9736 // CHECK19: cond.end: 9737 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 9738 // CHECK19-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 9739 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 9740 // CHECK19-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 9741 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9742 // CHECK19: omp.inner.for.cond: 9743 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]] 9744 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]] 9745 // CHECK19-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 9746 // CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9747 // CHECK19: omp.inner.for.body: 9748 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 9749 // CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 9750 // CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 9751 // CHECK19-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP18]] 9752 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP18]] 9753 // CHECK19-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 9754 // CHECK19-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 9755 // CHECK19-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]] 9756 // CHECK19-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 9757 // CHECK19-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 9758 // CHECK19-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 9759 // CHECK19-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP18]] 9760 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP18]] 9761 // CHECK19-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 9762 // CHECK19-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 9763 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]] 9764 // CHECK19-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 9765 // CHECK19-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 9766 // CHECK19-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 9767 // CHECK19-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP18]] 9768 // CHECK19-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]] 9769 // CHECK19-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 9770 // CHECK19-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 9771 // CHECK19-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 9772 // CHECK19-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]] 9773 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9774 // CHECK19: omp.body.continue: 9775 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9776 // CHECK19: omp.inner.for.inc: 9777 // CHECK19-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 9778 // CHECK19-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 9779 // CHECK19-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 9780 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 9781 // CHECK19: omp.inner.for.end: 9782 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9783 // CHECK19: omp.loop.exit: 9784 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 9785 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9786 // CHECK19-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 9787 // CHECK19-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9788 // CHECK19: .omp.final.then: 9789 // CHECK19-NEXT: store i64 400, ptr [[IT]], align 8 9790 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 9791 // CHECK19: .omp.final.done: 9792 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9793 // CHECK19-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 9794 // CHECK19-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 9795 // CHECK19: .omp.linear.pu: 9796 // CHECK19-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 9797 // CHECK19-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 9798 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 9799 // CHECK19-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 9800 // CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 9801 // CHECK19: .omp.linear.pu.done: 9802 // CHECK19-NEXT: ret void 9803 // 9804 // 9805 // CHECK19-LABEL: define {{[^@]+}}@_Z7get_valv 9806 // CHECK19-SAME: () #[[ATTR3:[0-9]+]] { 9807 // CHECK19-NEXT: entry: 9808 // CHECK19-NEXT: ret i64 0 9809 // 9810 // 9811 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 9812 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 9813 // CHECK19-NEXT: entry: 9814 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9815 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9816 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9817 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9818 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 9819 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 9820 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 9821 // CHECK19-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 9822 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 9823 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 9824 // CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 9825 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 9826 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..2, i32 [[TMP1]], i32 [[TMP3]]) 9827 // CHECK19-NEXT: ret void 9828 // 9829 // 9830 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 9831 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 9832 // CHECK19-NEXT: entry: 9833 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 9834 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 9835 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9836 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9837 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9838 // CHECK19-NEXT: [[TMP:%.*]] = alloca i16, align 2 9839 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9840 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9841 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9842 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9843 // CHECK19-NEXT: [[IT:%.*]] = alloca i16, align 2 9844 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 9845 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 9846 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 9847 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 9848 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 9849 // CHECK19-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 9850 // CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 9851 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9852 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 9853 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 9854 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 9855 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9856 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 9857 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9858 // CHECK19: cond.true: 9859 // CHECK19-NEXT: br label [[COND_END:%.*]] 9860 // CHECK19: cond.false: 9861 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9862 // CHECK19-NEXT: br label [[COND_END]] 9863 // CHECK19: cond.end: 9864 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9865 // CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 9866 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 9867 // CHECK19-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 9868 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9869 // CHECK19: omp.inner.for.cond: 9870 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] 9871 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] 9872 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9873 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9874 // CHECK19: omp.inner.for.body: 9875 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 9876 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 9877 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 9878 // CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 9879 // CHECK19-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP21]] 9880 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] 9881 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 9882 // CHECK19-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] 9883 // CHECK19-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]] 9884 // CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 9885 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 9886 // CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 9887 // CHECK19-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]] 9888 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9889 // CHECK19: omp.body.continue: 9890 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9891 // CHECK19: omp.inner.for.inc: 9892 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 9893 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 9894 // CHECK19-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 9895 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 9896 // CHECK19: omp.inner.for.end: 9897 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9898 // CHECK19: omp.loop.exit: 9899 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 9900 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9901 // CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 9902 // CHECK19-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9903 // CHECK19: .omp.final.then: 9904 // CHECK19-NEXT: store i16 22, ptr [[IT]], align 2 9905 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 9906 // CHECK19: .omp.final.done: 9907 // CHECK19-NEXT: ret void 9908 // 9909 // 9910 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 9911 // CHECK19-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 9912 // CHECK19-NEXT: entry: 9913 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9914 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 9915 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9916 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 9917 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 9918 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9919 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 9920 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 9921 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 9922 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 9923 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9924 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 9925 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 9926 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 9927 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 9928 // CHECK19-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 9929 // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 9930 // CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 9931 // CHECK19-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 9932 // CHECK19-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 9933 // CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 9934 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 9935 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 9936 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 9937 // CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 9938 // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 9939 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 9940 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 9941 // CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 9942 // CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 9943 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 9944 // CHECK19-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 9945 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 9946 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 9947 // CHECK19-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 9948 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 9949 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @.omp_outlined..3, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]]) 9950 // CHECK19-NEXT: ret void 9951 // 9952 // 9953 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 9954 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 9955 // CHECK19-NEXT: entry: 9956 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 9957 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 9958 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9959 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 9960 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9961 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 9962 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 9963 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9964 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 9965 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 9966 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 9967 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 9968 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9969 // CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1 9970 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9971 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9972 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9973 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9974 // CHECK19-NEXT: [[IT:%.*]] = alloca i8, align 1 9975 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 9976 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 9977 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 9978 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 9979 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 9980 // CHECK19-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 9981 // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 9982 // CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 9983 // CHECK19-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 9984 // CHECK19-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 9985 // CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 9986 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 9987 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 9988 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 9989 // CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 9990 // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 9991 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 9992 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 9993 // CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 9994 // CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 9995 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 9996 // CHECK19-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 9997 // CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 9998 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9999 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 10000 // CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 10001 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 10002 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 10003 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 10004 // CHECK19: omp.dispatch.cond: 10005 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10006 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 10007 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10008 // CHECK19: cond.true: 10009 // CHECK19-NEXT: br label [[COND_END:%.*]] 10010 // CHECK19: cond.false: 10011 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10012 // CHECK19-NEXT: br label [[COND_END]] 10013 // CHECK19: cond.end: 10014 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 10015 // CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 10016 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 10017 // CHECK19-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 10018 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 10019 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10020 // CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 10021 // CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 10022 // CHECK19: omp.dispatch.body: 10023 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10024 // CHECK19: omp.inner.for.cond: 10025 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] 10026 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]] 10027 // CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 10028 // CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10029 // CHECK19: omp.inner.for.body: 10030 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 10031 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 10032 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 10033 // CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 10034 // CHECK19-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP24]] 10035 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] 10036 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 10037 // CHECK19-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] 10038 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 10039 // CHECK19-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 10040 // CHECK19-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 10041 // CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 10042 // CHECK19-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 10043 // CHECK19-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 10044 // CHECK19-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 10045 // CHECK19-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]] 10046 // CHECK19-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 10047 // CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 10048 // CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 10049 // CHECK19-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]] 10050 // CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 10051 // CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 10052 // CHECK19-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] 10053 // CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 10054 // CHECK19-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] 10055 // CHECK19-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 10056 // CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]] 10057 // CHECK19-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3 10058 // CHECK19-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]] 10059 // CHECK19-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 10060 // CHECK19-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]] 10061 // CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 10062 // CHECK19-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP24]] 10063 // CHECK19-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 10064 // CHECK19-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP24]] 10065 // CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 10066 // CHECK19-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP24]] 10067 // CHECK19-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 10068 // CHECK19-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 10069 // CHECK19-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 10070 // CHECK19-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP24]] 10071 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10072 // CHECK19: omp.body.continue: 10073 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10074 // CHECK19: omp.inner.for.inc: 10075 // CHECK19-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 10076 // CHECK19-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 10077 // CHECK19-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 10078 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 10079 // CHECK19: omp.inner.for.end: 10080 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 10081 // CHECK19: omp.dispatch.inc: 10082 // CHECK19-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 10083 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 10084 // CHECK19-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 10085 // CHECK19-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 10086 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10087 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 10088 // CHECK19-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 10089 // CHECK19-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 10090 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 10091 // CHECK19: omp.dispatch.end: 10092 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 10093 // CHECK19-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10094 // CHECK19-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 10095 // CHECK19-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10096 // CHECK19: .omp.final.then: 10097 // CHECK19-NEXT: store i8 96, ptr [[IT]], align 1 10098 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10099 // CHECK19: .omp.final.done: 10100 // CHECK19-NEXT: ret void 10101 // 10102 // 10103 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 10104 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10105 // CHECK19-NEXT: entry: 10106 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10107 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10108 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 10109 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 10110 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10111 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10112 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 10113 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10114 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 10115 // CHECK19-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 10116 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 10117 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 10118 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 10119 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 10120 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 10121 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 10122 // CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 10123 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 10124 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 10125 // CHECK19-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 10126 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 10127 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @.omp_outlined..4, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]]) 10128 // CHECK19-NEXT: ret void 10129 // 10130 // 10131 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 10132 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10133 // CHECK19-NEXT: entry: 10134 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 10135 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 10136 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10137 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10138 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 10139 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 10140 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10141 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 10142 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 10143 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 10144 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10145 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 10146 // CHECK19-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 10147 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 10148 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 10149 // CHECK19-NEXT: ret void 10150 // 10151 // 10152 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 10153 // CHECK19-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 10154 // CHECK19-NEXT: entry: 10155 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 10156 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 10157 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10158 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10159 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 10160 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 10161 // CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 10162 // CHECK19-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 10163 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 10164 // CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 10165 // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 10166 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 10167 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 10168 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 10169 // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 10170 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 10171 // CHECK19-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 10172 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 10173 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @.omp_outlined..5, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]]) 10174 // CHECK19-NEXT: ret void 10175 // 10176 // 10177 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5 10178 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 10179 // CHECK19-NEXT: entry: 10180 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 10181 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 10182 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 10183 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 10184 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10185 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10186 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 10187 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 10188 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 10189 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 10190 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 10191 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 10192 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10193 // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 10194 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 10195 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 10196 // CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 10197 // CHECK19-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 10198 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 10199 // CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 10200 // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 10201 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 10202 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 10203 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 10204 // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 10205 // CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 10206 // CHECK19-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 10207 // CHECK19-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 10208 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10209 // CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 10210 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 10211 // CHECK19-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 10212 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 10213 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 10214 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10215 // CHECK19: cond.true: 10216 // CHECK19-NEXT: br label [[COND_END:%.*]] 10217 // CHECK19: cond.false: 10218 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 10219 // CHECK19-NEXT: br label [[COND_END]] 10220 // CHECK19: cond.end: 10221 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 10222 // CHECK19-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 10223 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 10224 // CHECK19-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8 10225 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10226 // CHECK19: omp.inner.for.cond: 10227 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27:![0-9]+]] 10228 // CHECK19-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP27]] 10229 // CHECK19-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 10230 // CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10231 // CHECK19: omp.inner.for.body: 10232 // CHECK19-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 10233 // CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 10234 // CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 10235 // CHECK19-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP27]] 10236 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 10237 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 10238 // CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 10239 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 10240 // CHECK19-NEXT: store double [[ADD]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP27]] 10241 // CHECK19-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 10242 // CHECK19-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP27]] 10243 // CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 10244 // CHECK19-NEXT: store double [[INC]], ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP27]] 10245 // CHECK19-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 10246 // CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 10247 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]] 10248 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 10249 // CHECK19-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP27]] 10250 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10251 // CHECK19: omp.body.continue: 10252 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10253 // CHECK19: omp.inner.for.inc: 10254 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 10255 // CHECK19-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 10256 // CHECK19-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 10257 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 10258 // CHECK19: omp.inner.for.end: 10259 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10260 // CHECK19: omp.loop.exit: 10261 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 10262 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10263 // CHECK19-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 10264 // CHECK19-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10265 // CHECK19: .omp.final.then: 10266 // CHECK19-NEXT: store i64 400, ptr [[IT]], align 8 10267 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10268 // CHECK19: .omp.final.done: 10269 // CHECK19-NEXT: ret void 10270 // 10271 // 10272 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 10273 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10274 // CHECK19-NEXT: entry: 10275 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10276 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10277 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 10278 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10279 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10280 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10281 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 10282 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 10283 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 10284 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 10285 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 10286 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 10287 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 10288 // CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 10289 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 10290 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..6, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) 10291 // CHECK19-NEXT: ret void 10292 // 10293 // 10294 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 10295 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10296 // CHECK19-NEXT: entry: 10297 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 10298 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 10299 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10300 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10301 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 10302 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 10303 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 10304 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 10305 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 10306 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 10307 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10308 // CHECK19-NEXT: [[I:%.*]] = alloca i64, align 8 10309 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 10310 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 10311 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10312 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 10313 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 10314 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 10315 // CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 10316 // CHECK19-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 10317 // CHECK19-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 10318 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10319 // CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 10320 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 10321 // CHECK19-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 10322 // CHECK19-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 10323 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 10324 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10325 // CHECK19: cond.true: 10326 // CHECK19-NEXT: br label [[COND_END:%.*]] 10327 // CHECK19: cond.false: 10328 // CHECK19-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 10329 // CHECK19-NEXT: br label [[COND_END]] 10330 // CHECK19: cond.end: 10331 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 10332 // CHECK19-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 10333 // CHECK19-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 10334 // CHECK19-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 10335 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10336 // CHECK19: omp.inner.for.cond: 10337 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30:![0-9]+]] 10338 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP30]] 10339 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 10340 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10341 // CHECK19: omp.inner.for.body: 10342 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 10343 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 10344 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 10345 // CHECK19-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP30]] 10346 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP30]] 10347 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 10348 // CHECK19-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP30]] 10349 // CHECK19-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] 10350 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 10351 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 10352 // CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 10353 // CHECK19-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] 10354 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 10355 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP30]] 10356 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 10357 // CHECK19-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP30]] 10358 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10359 // CHECK19: omp.body.continue: 10360 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10361 // CHECK19: omp.inner.for.inc: 10362 // CHECK19-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 10363 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 10364 // CHECK19-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 10365 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 10366 // CHECK19: omp.inner.for.end: 10367 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10368 // CHECK19: omp.loop.exit: 10369 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 10370 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10371 // CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 10372 // CHECK19-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10373 // CHECK19: .omp.final.then: 10374 // CHECK19-NEXT: store i64 11, ptr [[I]], align 8 10375 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10376 // CHECK19: .omp.final.done: 10377 // CHECK19-NEXT: ret void 10378 // 10379 // 10380 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 10381 // CHECK21-SAME: () #[[ATTR0:[0-9]+]] { 10382 // CHECK21-NEXT: entry: 10383 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @.omp_outlined.) 10384 // CHECK21-NEXT: ret void 10385 // 10386 // 10387 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined. 10388 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 10389 // CHECK21-NEXT: entry: 10390 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 10391 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 10392 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10393 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 10394 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10395 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10396 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10397 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10398 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 10399 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 10400 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 10401 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 10402 // CHECK21-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 10403 // CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 10404 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10405 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 10406 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 10407 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 10408 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10409 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 10410 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10411 // CHECK21: cond.true: 10412 // CHECK21-NEXT: br label [[COND_END:%.*]] 10413 // CHECK21: cond.false: 10414 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10415 // CHECK21-NEXT: br label [[COND_END]] 10416 // CHECK21: cond.end: 10417 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10418 // CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 10419 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 10420 // CHECK21-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 10421 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10422 // CHECK21: omp.inner.for.cond: 10423 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 10424 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 10425 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10426 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10427 // CHECK21: omp.inner.for.body: 10428 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 10429 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 10430 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 10431 // CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 10432 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10433 // CHECK21: omp.body.continue: 10434 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10435 // CHECK21: omp.inner.for.inc: 10436 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 10437 // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 10438 // CHECK21-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 10439 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 10440 // CHECK21: omp.inner.for.end: 10441 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10442 // CHECK21: omp.loop.exit: 10443 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 10444 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10445 // CHECK21-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 10446 // CHECK21-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10447 // CHECK21: .omp.final.then: 10448 // CHECK21-NEXT: store i32 33, ptr [[I]], align 4 10449 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 10450 // CHECK21: .omp.final.done: 10451 // CHECK21-NEXT: ret void 10452 // 10453 // 10454 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 10455 // CHECK21-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 10456 // CHECK21-NEXT: entry: 10457 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10458 // CHECK21-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 10459 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10460 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10461 // CHECK21-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 10462 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10463 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 10464 // CHECK21-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 10465 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 10466 // CHECK21-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 10467 // CHECK21-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 10468 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 10469 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 10470 // CHECK21-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 10471 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 10472 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 10473 // CHECK21-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 10474 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8 10475 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..1, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 10476 // CHECK21-NEXT: ret void 10477 // 10478 // 10479 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1 10480 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 10481 // CHECK21-NEXT: entry: 10482 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 10483 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 10484 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10485 // CHECK21-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 10486 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10487 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 10488 // CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8 10489 // CHECK21-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 10490 // CHECK21-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 10491 // CHECK21-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 10492 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 10493 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 10494 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 10495 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10496 // CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 8 10497 // CHECK21-NEXT: [[LIN2:%.*]] = alloca i32, align 4 10498 // CHECK21-NEXT: [[A3:%.*]] = alloca i32, align 4 10499 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 10500 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 10501 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 10502 // CHECK21-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 10503 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 10504 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 10505 // CHECK21-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 10506 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 10507 // CHECK21-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 10508 // CHECK21-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 10509 // CHECK21-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 10510 // CHECK21-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 10511 // CHECK21-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 10512 // CHECK21-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 10513 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10514 // CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 10515 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 10516 // CHECK21-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 10517 // CHECK21-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 10518 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 10519 // CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 10520 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10521 // CHECK21: cond.true: 10522 // CHECK21-NEXT: br label [[COND_END:%.*]] 10523 // CHECK21: cond.false: 10524 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 10525 // CHECK21-NEXT: br label [[COND_END]] 10526 // CHECK21: cond.end: 10527 // CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 10528 // CHECK21-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 10529 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 10530 // CHECK21-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 10531 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10532 // CHECK21: omp.inner.for.cond: 10533 // CHECK21-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17:![0-9]+]] 10534 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP17]] 10535 // CHECK21-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 10536 // CHECK21-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10537 // CHECK21: omp.inner.for.body: 10538 // CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 10539 // CHECK21-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 10540 // CHECK21-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 10541 // CHECK21-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP17]] 10542 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP17]] 10543 // CHECK21-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 10544 // CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 10545 // CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]] 10546 // CHECK21-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 10547 // CHECK21-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 10548 // CHECK21-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 10549 // CHECK21-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP17]] 10550 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP17]] 10551 // CHECK21-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 10552 // CHECK21-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 10553 // CHECK21-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]] 10554 // CHECK21-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 10555 // CHECK21-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 10556 // CHECK21-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 10557 // CHECK21-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP17]] 10558 // CHECK21-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP17]] 10559 // CHECK21-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 10560 // CHECK21-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 10561 // CHECK21-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 10562 // CHECK21-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP17]] 10563 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10564 // CHECK21: omp.body.continue: 10565 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10566 // CHECK21: omp.inner.for.inc: 10567 // CHECK21-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 10568 // CHECK21-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 10569 // CHECK21-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 10570 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 10571 // CHECK21: omp.inner.for.end: 10572 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10573 // CHECK21: omp.loop.exit: 10574 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 10575 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10576 // CHECK21-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 10577 // CHECK21-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10578 // CHECK21: .omp.final.then: 10579 // CHECK21-NEXT: store i64 400, ptr [[IT]], align 8 10580 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 10581 // CHECK21: .omp.final.done: 10582 // CHECK21-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10583 // CHECK21-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 10584 // CHECK21-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 10585 // CHECK21: .omp.linear.pu: 10586 // CHECK21-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 10587 // CHECK21-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 10588 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 10589 // CHECK21-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 10590 // CHECK21-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 10591 // CHECK21: .omp.linear.pu.done: 10592 // CHECK21-NEXT: ret void 10593 // 10594 // 10595 // CHECK21-LABEL: define {{[^@]+}}@_Z7get_valv 10596 // CHECK21-SAME: () #[[ATTR3:[0-9]+]] { 10597 // CHECK21-NEXT: entry: 10598 // CHECK21-NEXT: ret i64 0 10599 // 10600 // 10601 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 10602 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 10603 // CHECK21-NEXT: entry: 10604 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10605 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10606 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10607 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10608 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 10609 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 10610 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 10611 // CHECK21-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 10612 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 10613 // CHECK21-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 10614 // CHECK21-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 10615 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 10616 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..2, i64 [[TMP1]], i64 [[TMP3]]) 10617 // CHECK21-NEXT: ret void 10618 // 10619 // 10620 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2 10621 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 10622 // CHECK21-NEXT: entry: 10623 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 10624 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 10625 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10626 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10627 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10628 // CHECK21-NEXT: [[TMP:%.*]] = alloca i16, align 2 10629 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10630 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10631 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10632 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10633 // CHECK21-NEXT: [[IT:%.*]] = alloca i16, align 2 10634 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 10635 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 10636 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 10637 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 10638 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 10639 // CHECK21-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 10640 // CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 10641 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10642 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 10643 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 10644 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 10645 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10646 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 10647 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10648 // CHECK21: cond.true: 10649 // CHECK21-NEXT: br label [[COND_END:%.*]] 10650 // CHECK21: cond.false: 10651 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10652 // CHECK21-NEXT: br label [[COND_END]] 10653 // CHECK21: cond.end: 10654 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10655 // CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 10656 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 10657 // CHECK21-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 10658 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10659 // CHECK21: omp.inner.for.cond: 10660 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] 10661 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] 10662 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10663 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10664 // CHECK21: omp.inner.for.body: 10665 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 10666 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 10667 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 10668 // CHECK21-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 10669 // CHECK21-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP20]] 10670 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]] 10671 // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 10672 // CHECK21-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]] 10673 // CHECK21-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP20]] 10674 // CHECK21-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 10675 // CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 10676 // CHECK21-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 10677 // CHECK21-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP20]] 10678 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10679 // CHECK21: omp.body.continue: 10680 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10681 // CHECK21: omp.inner.for.inc: 10682 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 10683 // CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 10684 // CHECK21-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 10685 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 10686 // CHECK21: omp.inner.for.end: 10687 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10688 // CHECK21: omp.loop.exit: 10689 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 10690 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10691 // CHECK21-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 10692 // CHECK21-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10693 // CHECK21: .omp.final.then: 10694 // CHECK21-NEXT: store i16 22, ptr [[IT]], align 2 10695 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 10696 // CHECK21: .omp.final.done: 10697 // CHECK21-NEXT: ret void 10698 // 10699 // 10700 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 10701 // CHECK21-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 10702 // CHECK21-NEXT: entry: 10703 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10704 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 10705 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10706 // CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 10707 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 10708 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10709 // CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10710 // CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 10711 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 10712 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 10713 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10714 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 10715 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 10716 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 10717 // CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 10718 // CHECK21-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 10719 // CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 10720 // CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 10721 // CHECK21-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 10722 // CHECK21-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 10723 // CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 10724 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 10725 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 10726 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 10727 // CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 10728 // CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 10729 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 10730 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 10731 // CHECK21-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 10732 // CHECK21-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 10733 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 10734 // CHECK21-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 10735 // CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 10736 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 10737 // CHECK21-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 10738 // CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 10739 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @.omp_outlined..3, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]]) 10740 // CHECK21-NEXT: ret void 10741 // 10742 // 10743 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3 10744 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 10745 // CHECK21-NEXT: entry: 10746 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 10747 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 10748 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10749 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 10750 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10751 // CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 10752 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 10753 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10754 // CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10755 // CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 10756 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 10757 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 10758 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10759 // CHECK21-NEXT: [[TMP:%.*]] = alloca i8, align 1 10760 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10761 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10762 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10763 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10764 // CHECK21-NEXT: [[IT:%.*]] = alloca i8, align 1 10765 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 10766 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 10767 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 10768 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 10769 // CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 10770 // CHECK21-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 10771 // CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 10772 // CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 10773 // CHECK21-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 10774 // CHECK21-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 10775 // CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 10776 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 10777 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 10778 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 10779 // CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 10780 // CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 10781 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 10782 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 10783 // CHECK21-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 10784 // CHECK21-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 10785 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 10786 // CHECK21-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 10787 // CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 10788 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10789 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 10790 // CHECK21-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 10791 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 10792 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 10793 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 10794 // CHECK21: omp.dispatch.cond: 10795 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10796 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 10797 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10798 // CHECK21: cond.true: 10799 // CHECK21-NEXT: br label [[COND_END:%.*]] 10800 // CHECK21: cond.false: 10801 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10802 // CHECK21-NEXT: br label [[COND_END]] 10803 // CHECK21: cond.end: 10804 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 10805 // CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 10806 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 10807 // CHECK21-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 10808 // CHECK21-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 10809 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10810 // CHECK21-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 10811 // CHECK21-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 10812 // CHECK21: omp.dispatch.body: 10813 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10814 // CHECK21: omp.inner.for.cond: 10815 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] 10816 // CHECK21-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] 10817 // CHECK21-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 10818 // CHECK21-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10819 // CHECK21: omp.inner.for.body: 10820 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 10821 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 10822 // CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 10823 // CHECK21-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 10824 // CHECK21-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP23]] 10825 // CHECK21-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] 10826 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 10827 // CHECK21-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] 10828 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 10829 // CHECK21-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] 10830 // CHECK21-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 10831 // CHECK21-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 10832 // CHECK21-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 10833 // CHECK21-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] 10834 // CHECK21-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 10835 // CHECK21-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]] 10836 // CHECK21-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 10837 // CHECK21-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 10838 // CHECK21-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 10839 // CHECK21-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]] 10840 // CHECK21-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 10841 // CHECK21-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 10842 // CHECK21-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] 10843 // CHECK21-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 10844 // CHECK21-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] 10845 // CHECK21-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 10846 // CHECK21-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]] 10847 // CHECK21-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3 10848 // CHECK21-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]] 10849 // CHECK21-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 10850 // CHECK21-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]] 10851 // CHECK21-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 10852 // CHECK21-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP23]] 10853 // CHECK21-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 10854 // CHECK21-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP23]] 10855 // CHECK21-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 10856 // CHECK21-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP23]] 10857 // CHECK21-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 10858 // CHECK21-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 10859 // CHECK21-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 10860 // CHECK21-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP23]] 10861 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10862 // CHECK21: omp.body.continue: 10863 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10864 // CHECK21: omp.inner.for.inc: 10865 // CHECK21-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 10866 // CHECK21-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 10867 // CHECK21-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 10868 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] 10869 // CHECK21: omp.inner.for.end: 10870 // CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 10871 // CHECK21: omp.dispatch.inc: 10872 // CHECK21-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 10873 // CHECK21-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 10874 // CHECK21-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 10875 // CHECK21-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 10876 // CHECK21-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10877 // CHECK21-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 10878 // CHECK21-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 10879 // CHECK21-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 10880 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND]] 10881 // CHECK21: omp.dispatch.end: 10882 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 10883 // CHECK21-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10884 // CHECK21-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 10885 // CHECK21-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10886 // CHECK21: .omp.final.then: 10887 // CHECK21-NEXT: store i8 96, ptr [[IT]], align 1 10888 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 10889 // CHECK21: .omp.final.done: 10890 // CHECK21-NEXT: ret void 10891 // 10892 // 10893 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 10894 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10895 // CHECK21-NEXT: entry: 10896 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10897 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10898 // CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 10899 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 10900 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10901 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10902 // CHECK21-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 10903 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 10904 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 10905 // CHECK21-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 10906 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 10907 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 10908 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 10909 // CHECK21-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 10910 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 10911 // CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 10912 // CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 10913 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 10914 // CHECK21-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 10915 // CHECK21-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 10916 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 10917 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @.omp_outlined..4, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]]) 10918 // CHECK21-NEXT: ret void 10919 // 10920 // 10921 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4 10922 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10923 // CHECK21-NEXT: entry: 10924 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 10925 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 10926 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10927 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10928 // CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 10929 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 10930 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10931 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 10932 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 10933 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 10934 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 10935 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 10936 // CHECK21-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 10937 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 10938 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 10939 // CHECK21-NEXT: ret void 10940 // 10941 // 10942 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 10943 // CHECK21-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 10944 // CHECK21-NEXT: entry: 10945 // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 10946 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 10947 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10948 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10949 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 10950 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 10951 // CHECK21-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 10952 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 10953 // CHECK21-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 10954 // CHECK21-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 10955 // CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 10956 // CHECK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 10957 // CHECK21-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 10958 // CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 10959 // CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 10960 // CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 10961 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 10962 // CHECK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 10963 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 10964 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 10965 // CHECK21-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8 10966 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4 10967 // CHECK21-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 10968 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 10969 // CHECK21-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 10970 // CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 10971 // CHECK21-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 10972 // CHECK21-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 10973 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 10974 // CHECK21-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 10975 // CHECK21-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1 10976 // CHECK21-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 10977 // CHECK21: omp_if.then: 10978 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @.omp_outlined..5, ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) 10979 // CHECK21-NEXT: br label [[OMP_IF_END:%.*]] 10980 // CHECK21: omp_if.else: 10981 // CHECK21-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 10982 // CHECK21-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 10983 // CHECK21-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 10984 // CHECK21-NEXT: call void @.omp_outlined..5(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) #[[ATTR2:[0-9]+]] 10985 // CHECK21-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 10986 // CHECK21-NEXT: br label [[OMP_IF_END]] 10987 // CHECK21: omp_if.end: 10988 // CHECK21-NEXT: ret void 10989 // 10990 // 10991 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..5 10992 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 10993 // CHECK21-NEXT: entry: 10994 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 10995 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 10996 // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 10997 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 10998 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10999 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11000 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 11001 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 11002 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11003 // CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8 11004 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11005 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11006 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11007 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11008 // CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 8 11009 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 11010 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 11011 // CHECK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 11012 // CHECK21-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 11013 // CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 11014 // CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 11015 // CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 11016 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 11017 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 11018 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 11019 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 11020 // CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 11021 // CHECK21-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 11022 // CHECK21-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 11023 // CHECK21-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 11024 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11025 // CHECK21-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 11026 // CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 11027 // CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11028 // CHECK21: omp_if.then: 11029 // CHECK21-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 11030 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 11031 // CHECK21-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 11032 // CHECK21-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11033 // CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 11034 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11035 // CHECK21: cond.true: 11036 // CHECK21-NEXT: br label [[COND_END:%.*]] 11037 // CHECK21: cond.false: 11038 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11039 // CHECK21-NEXT: br label [[COND_END]] 11040 // CHECK21: cond.end: 11041 // CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 11042 // CHECK21-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 11043 // CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 11044 // CHECK21-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV]], align 8 11045 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11046 // CHECK21: omp.inner.for.cond: 11047 // CHECK21-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26:![0-9]+]] 11048 // CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP26]] 11049 // CHECK21-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 11050 // CHECK21-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11051 // CHECK21: omp.inner.for.body: 11052 // CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 11053 // CHECK21-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 11054 // CHECK21-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 11055 // CHECK21-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP26]] 11056 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] 11057 // CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double 11058 // CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 11059 // CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 11060 // CHECK21-NEXT: store double [[ADD]], ptr [[A]], align 8, !nontemporal !27, !llvm.access.group [[ACC_GRP26]] 11061 // CHECK21-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 11062 // CHECK21-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 8, !nontemporal !27, !llvm.access.group [[ACC_GRP26]] 11063 // CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 11064 // CHECK21-NEXT: store double [[INC]], ptr [[A4]], align 8, !nontemporal !27, !llvm.access.group [[ACC_GRP26]] 11065 // CHECK21-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 11066 // CHECK21-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]] 11067 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP15]] 11068 // CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 11069 // CHECK21-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP26]] 11070 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11071 // CHECK21: omp.body.continue: 11072 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11073 // CHECK21: omp.inner.for.inc: 11074 // CHECK21-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 11075 // CHECK21-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1 11076 // CHECK21-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 11077 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 11078 // CHECK21: omp.inner.for.end: 11079 // CHECK21-NEXT: br label [[OMP_IF_END:%.*]] 11080 // CHECK21: omp_if.else: 11081 // CHECK21-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 11082 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 11083 // CHECK21-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP18]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 11084 // CHECK21-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11085 // CHECK21-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[TMP19]], 3 11086 // CHECK21-NEXT: br i1 [[CMP8]], label [[COND_TRUE9:%.*]], label [[COND_FALSE10:%.*]] 11087 // CHECK21: cond.true9: 11088 // CHECK21-NEXT: br label [[COND_END11:%.*]] 11089 // CHECK21: cond.false10: 11090 // CHECK21-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11091 // CHECK21-NEXT: br label [[COND_END11]] 11092 // CHECK21: cond.end11: 11093 // CHECK21-NEXT: [[COND12:%.*]] = phi i64 [ 3, [[COND_TRUE9]] ], [ [[TMP20]], [[COND_FALSE10]] ] 11094 // CHECK21-NEXT: store i64 [[COND12]], ptr [[DOTOMP_UB]], align 8 11095 // CHECK21-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 11096 // CHECK21-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV]], align 8 11097 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 11098 // CHECK21: omp.inner.for.cond13: 11099 // CHECK21-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 11100 // CHECK21-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11101 // CHECK21-NEXT: [[CMP14:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 11102 // CHECK21-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END29:%.*]] 11103 // CHECK21: omp.inner.for.body15: 11104 // CHECK21-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 11105 // CHECK21-NEXT: [[MUL16:%.*]] = mul i64 [[TMP24]], 400 11106 // CHECK21-NEXT: [[SUB17:%.*]] = sub i64 2000, [[MUL16]] 11107 // CHECK21-NEXT: store i64 [[SUB17]], ptr [[IT]], align 8 11108 // CHECK21-NEXT: [[TMP25:%.*]] = load i32, ptr [[B_ADDR]], align 4 11109 // CHECK21-NEXT: [[CONV18:%.*]] = sitofp i32 [[TMP25]] to double 11110 // CHECK21-NEXT: [[ADD19:%.*]] = fadd double [[CONV18]], 1.500000e+00 11111 // CHECK21-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 11112 // CHECK21-NEXT: store double [[ADD19]], ptr [[A20]], align 8 11113 // CHECK21-NEXT: [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 11114 // CHECK21-NEXT: [[TMP26:%.*]] = load double, ptr [[A21]], align 8 11115 // CHECK21-NEXT: [[INC22:%.*]] = fadd double [[TMP26]], 1.000000e+00 11116 // CHECK21-NEXT: store double [[INC22]], ptr [[A21]], align 8 11117 // CHECK21-NEXT: [[CONV23:%.*]] = fptosi double [[INC22]] to i16 11118 // CHECK21-NEXT: [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]] 11119 // CHECK21-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP27]] 11120 // CHECK21-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX24]], i64 1 11121 // CHECK21-NEXT: store i16 [[CONV23]], ptr [[ARRAYIDX25]], align 2 11122 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] 11123 // CHECK21: omp.body.continue26: 11124 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] 11125 // CHECK21: omp.inner.for.inc27: 11126 // CHECK21-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 11127 // CHECK21-NEXT: [[ADD28:%.*]] = add i64 [[TMP28]], 1 11128 // CHECK21-NEXT: store i64 [[ADD28]], ptr [[DOTOMP_IV]], align 8 11129 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP30:![0-9]+]] 11130 // CHECK21: omp.inner.for.end29: 11131 // CHECK21-NEXT: br label [[OMP_IF_END]] 11132 // CHECK21: omp_if.end: 11133 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11134 // CHECK21: omp.loop.exit: 11135 // CHECK21-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 11136 // CHECK21-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4 11137 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]]) 11138 // CHECK21-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11139 // CHECK21-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 11140 // CHECK21-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11141 // CHECK21: .omp.final.then: 11142 // CHECK21-NEXT: store i64 400, ptr [[IT]], align 8 11143 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11144 // CHECK21: .omp.final.done: 11145 // CHECK21-NEXT: ret void 11146 // 11147 // 11148 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 11149 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11150 // CHECK21-NEXT: entry: 11151 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11152 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11153 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 11154 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11155 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11156 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 11157 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 11158 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 11159 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 11160 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 11161 // CHECK21-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 11162 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 11163 // CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 11164 // CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 11165 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 11166 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..6, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) 11167 // CHECK21-NEXT: ret void 11168 // 11169 // 11170 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..6 11171 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 11172 // CHECK21-NEXT: entry: 11173 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 11174 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 11175 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11176 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11177 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 11178 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11179 // CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8 11180 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11181 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11182 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11183 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11184 // CHECK21-NEXT: [[I:%.*]] = alloca i64, align 8 11185 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 11186 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 11187 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 11188 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 11189 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 11190 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 11191 // CHECK21-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 11192 // CHECK21-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 11193 // CHECK21-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 11194 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11195 // CHECK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 11196 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 11197 // CHECK21-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 11198 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11199 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 11200 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11201 // CHECK21: cond.true: 11202 // CHECK21-NEXT: br label [[COND_END:%.*]] 11203 // CHECK21: cond.false: 11204 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11205 // CHECK21-NEXT: br label [[COND_END]] 11206 // CHECK21: cond.end: 11207 // CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 11208 // CHECK21-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 11209 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 11210 // CHECK21-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 11211 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11212 // CHECK21: omp.inner.for.cond: 11213 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32:![0-9]+]] 11214 // CHECK21-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP32]] 11215 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 11216 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11217 // CHECK21: omp.inner.for.body: 11218 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32]] 11219 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 11220 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 11221 // CHECK21-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP32]] 11222 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] 11223 // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 11224 // CHECK21-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] 11225 // CHECK21-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] 11226 // CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 11227 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 11228 // CHECK21-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 11229 // CHECK21-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] 11230 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 11231 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] 11232 // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 11233 // CHECK21-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] 11234 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11235 // CHECK21: omp.body.continue: 11236 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11237 // CHECK21: omp.inner.for.inc: 11238 // CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32]] 11239 // CHECK21-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 11240 // CHECK21-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32]] 11241 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] 11242 // CHECK21: omp.inner.for.end: 11243 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11244 // CHECK21: omp.loop.exit: 11245 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 11246 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11247 // CHECK21-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 11248 // CHECK21-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11249 // CHECK21: .omp.final.then: 11250 // CHECK21-NEXT: store i64 11, ptr [[I]], align 8 11251 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11252 // CHECK21: .omp.final.done: 11253 // CHECK21-NEXT: ret void 11254 // 11255 // 11256 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 11257 // CHECK23-SAME: () #[[ATTR0:[0-9]+]] { 11258 // CHECK23-NEXT: entry: 11259 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @.omp_outlined.) 11260 // CHECK23-NEXT: ret void 11261 // 11262 // 11263 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined. 11264 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 11265 // CHECK23-NEXT: entry: 11266 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 11267 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 11268 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11269 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 11270 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11271 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11272 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11273 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11274 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 11275 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 11276 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 11277 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 11278 // CHECK23-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 11279 // CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 11280 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11281 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 11282 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 11283 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 11284 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11285 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 11286 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11287 // CHECK23: cond.true: 11288 // CHECK23-NEXT: br label [[COND_END:%.*]] 11289 // CHECK23: cond.false: 11290 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11291 // CHECK23-NEXT: br label [[COND_END]] 11292 // CHECK23: cond.end: 11293 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 11294 // CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 11295 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 11296 // CHECK23-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 11297 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11298 // CHECK23: omp.inner.for.cond: 11299 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 11300 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] 11301 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 11302 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11303 // CHECK23: omp.inner.for.body: 11304 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 11305 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 11306 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 11307 // CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] 11308 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11309 // CHECK23: omp.body.continue: 11310 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11311 // CHECK23: omp.inner.for.inc: 11312 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 11313 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 11314 // CHECK23-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 11315 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 11316 // CHECK23: omp.inner.for.end: 11317 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11318 // CHECK23: omp.loop.exit: 11319 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 11320 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11321 // CHECK23-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 11322 // CHECK23-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11323 // CHECK23: .omp.final.then: 11324 // CHECK23-NEXT: store i32 33, ptr [[I]], align 4 11325 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 11326 // CHECK23: .omp.final.done: 11327 // CHECK23-NEXT: ret void 11328 // 11329 // 11330 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 11331 // CHECK23-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 11332 // CHECK23-NEXT: entry: 11333 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11334 // CHECK23-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 11335 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11336 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11337 // CHECK23-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 11338 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11339 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 11340 // CHECK23-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 11341 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11342 // CHECK23-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 11343 // CHECK23-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 11344 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 11345 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 11346 // CHECK23-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 11347 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 11348 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 11349 // CHECK23-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 11350 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4 11351 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..1, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 11352 // CHECK23-NEXT: ret void 11353 // 11354 // 11355 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1 11356 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 11357 // CHECK23-NEXT: entry: 11358 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 11359 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 11360 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11361 // CHECK23-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 11362 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11363 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11364 // CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4 11365 // CHECK23-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 11366 // CHECK23-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 11367 // CHECK23-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 11368 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11369 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11370 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11371 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11372 // CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 8 11373 // CHECK23-NEXT: [[LIN2:%.*]] = alloca i32, align 4 11374 // CHECK23-NEXT: [[A3:%.*]] = alloca i32, align 4 11375 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 11376 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 11377 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 11378 // CHECK23-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 11379 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11380 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 11381 // CHECK23-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 11382 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 11383 // CHECK23-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 11384 // CHECK23-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 11385 // CHECK23-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 11386 // CHECK23-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 11387 // CHECK23-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 11388 // CHECK23-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 11389 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11390 // CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 11391 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 11392 // CHECK23-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 11393 // CHECK23-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 11394 // CHECK23-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11395 // CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 11396 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11397 // CHECK23: cond.true: 11398 // CHECK23-NEXT: br label [[COND_END:%.*]] 11399 // CHECK23: cond.false: 11400 // CHECK23-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11401 // CHECK23-NEXT: br label [[COND_END]] 11402 // CHECK23: cond.end: 11403 // CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 11404 // CHECK23-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 11405 // CHECK23-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 11406 // CHECK23-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 11407 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11408 // CHECK23: omp.inner.for.cond: 11409 // CHECK23-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]] 11410 // CHECK23-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]] 11411 // CHECK23-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 11412 // CHECK23-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11413 // CHECK23: omp.inner.for.body: 11414 // CHECK23-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11415 // CHECK23-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 11416 // CHECK23-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 11417 // CHECK23-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP18]] 11418 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP18]] 11419 // CHECK23-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 11420 // CHECK23-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11421 // CHECK23-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]] 11422 // CHECK23-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 11423 // CHECK23-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 11424 // CHECK23-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 11425 // CHECK23-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP18]] 11426 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP18]] 11427 // CHECK23-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 11428 // CHECK23-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11429 // CHECK23-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]] 11430 // CHECK23-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 11431 // CHECK23-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 11432 // CHECK23-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 11433 // CHECK23-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP18]] 11434 // CHECK23-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]] 11435 // CHECK23-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 11436 // CHECK23-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 11437 // CHECK23-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 11438 // CHECK23-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]] 11439 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11440 // CHECK23: omp.body.continue: 11441 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11442 // CHECK23: omp.inner.for.inc: 11443 // CHECK23-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11444 // CHECK23-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 11445 // CHECK23-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11446 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 11447 // CHECK23: omp.inner.for.end: 11448 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11449 // CHECK23: omp.loop.exit: 11450 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 11451 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11452 // CHECK23-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 11453 // CHECK23-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11454 // CHECK23: .omp.final.then: 11455 // CHECK23-NEXT: store i64 400, ptr [[IT]], align 8 11456 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 11457 // CHECK23: .omp.final.done: 11458 // CHECK23-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11459 // CHECK23-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 11460 // CHECK23-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 11461 // CHECK23: .omp.linear.pu: 11462 // CHECK23-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 11463 // CHECK23-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 11464 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 11465 // CHECK23-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 11466 // CHECK23-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 11467 // CHECK23: .omp.linear.pu.done: 11468 // CHECK23-NEXT: ret void 11469 // 11470 // 11471 // CHECK23-LABEL: define {{[^@]+}}@_Z7get_valv 11472 // CHECK23-SAME: () #[[ATTR3:[0-9]+]] { 11473 // CHECK23-NEXT: entry: 11474 // CHECK23-NEXT: ret i64 0 11475 // 11476 // 11477 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 11478 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 11479 // CHECK23-NEXT: entry: 11480 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11481 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11482 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11483 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11484 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11485 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 11486 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 11487 // CHECK23-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 11488 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 11489 // CHECK23-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 11490 // CHECK23-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 11491 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 11492 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..2, i32 [[TMP1]], i32 [[TMP3]]) 11493 // CHECK23-NEXT: ret void 11494 // 11495 // 11496 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2 11497 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 11498 // CHECK23-NEXT: entry: 11499 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 11500 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 11501 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11502 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11503 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11504 // CHECK23-NEXT: [[TMP:%.*]] = alloca i16, align 2 11505 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11506 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11507 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11508 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11509 // CHECK23-NEXT: [[IT:%.*]] = alloca i16, align 2 11510 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 11511 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 11512 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11513 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 11514 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 11515 // CHECK23-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 11516 // CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 11517 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11518 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 11519 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 11520 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 11521 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11522 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 11523 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11524 // CHECK23: cond.true: 11525 // CHECK23-NEXT: br label [[COND_END:%.*]] 11526 // CHECK23: cond.false: 11527 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11528 // CHECK23-NEXT: br label [[COND_END]] 11529 // CHECK23: cond.end: 11530 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 11531 // CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 11532 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 11533 // CHECK23-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 11534 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11535 // CHECK23: omp.inner.for.cond: 11536 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] 11537 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] 11538 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 11539 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11540 // CHECK23: omp.inner.for.body: 11541 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 11542 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 11543 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 11544 // CHECK23-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 11545 // CHECK23-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP21]] 11546 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] 11547 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 11548 // CHECK23-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] 11549 // CHECK23-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]] 11550 // CHECK23-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 11551 // CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 11552 // CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 11553 // CHECK23-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]] 11554 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11555 // CHECK23: omp.body.continue: 11556 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11557 // CHECK23: omp.inner.for.inc: 11558 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 11559 // CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 11560 // CHECK23-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 11561 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 11562 // CHECK23: omp.inner.for.end: 11563 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11564 // CHECK23: omp.loop.exit: 11565 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 11566 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11567 // CHECK23-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 11568 // CHECK23-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11569 // CHECK23: .omp.final.then: 11570 // CHECK23-NEXT: store i16 22, ptr [[IT]], align 2 11571 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 11572 // CHECK23: .omp.final.done: 11573 // CHECK23-NEXT: ret void 11574 // 11575 // 11576 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 11577 // CHECK23-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 11578 // CHECK23-NEXT: entry: 11579 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11580 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 11581 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11582 // CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 11583 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 11584 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11585 // CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 11586 // CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 11587 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 11588 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 11589 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11590 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 11591 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11592 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 11593 // CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 11594 // CHECK23-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 11595 // CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 11596 // CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 11597 // CHECK23-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 11598 // CHECK23-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 11599 // CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 11600 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 11601 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 11602 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 11603 // CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 11604 // CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 11605 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 11606 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 11607 // CHECK23-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 11608 // CHECK23-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 11609 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 11610 // CHECK23-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 11611 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 11612 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 11613 // CHECK23-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 11614 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 11615 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @.omp_outlined..3, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]]) 11616 // CHECK23-NEXT: ret void 11617 // 11618 // 11619 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..3 11620 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 11621 // CHECK23-NEXT: entry: 11622 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 11623 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 11624 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11625 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 11626 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11627 // CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 11628 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 11629 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11630 // CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 11631 // CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 11632 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 11633 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 11634 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11635 // CHECK23-NEXT: [[TMP:%.*]] = alloca i8, align 1 11636 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11637 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11638 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11639 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11640 // CHECK23-NEXT: [[IT:%.*]] = alloca i8, align 1 11641 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 11642 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 11643 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11644 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 11645 // CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 11646 // CHECK23-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 11647 // CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 11648 // CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 11649 // CHECK23-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 11650 // CHECK23-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 11651 // CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 11652 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 11653 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 11654 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 11655 // CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 11656 // CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 11657 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 11658 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 11659 // CHECK23-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 11660 // CHECK23-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 11661 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 11662 // CHECK23-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 11663 // CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 11664 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11665 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 11666 // CHECK23-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 11667 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 11668 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 11669 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 11670 // CHECK23: omp.dispatch.cond: 11671 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11672 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 11673 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11674 // CHECK23: cond.true: 11675 // CHECK23-NEXT: br label [[COND_END:%.*]] 11676 // CHECK23: cond.false: 11677 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11678 // CHECK23-NEXT: br label [[COND_END]] 11679 // CHECK23: cond.end: 11680 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 11681 // CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 11682 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 11683 // CHECK23-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 11684 // CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 11685 // CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11686 // CHECK23-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 11687 // CHECK23-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 11688 // CHECK23: omp.dispatch.body: 11689 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11690 // CHECK23: omp.inner.for.cond: 11691 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] 11692 // CHECK23-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]] 11693 // CHECK23-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 11694 // CHECK23-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11695 // CHECK23: omp.inner.for.body: 11696 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 11697 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 11698 // CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 11699 // CHECK23-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 11700 // CHECK23-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP24]] 11701 // CHECK23-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] 11702 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 11703 // CHECK23-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] 11704 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 11705 // CHECK23-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 11706 // CHECK23-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 11707 // CHECK23-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 11708 // CHECK23-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 11709 // CHECK23-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 11710 // CHECK23-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 11711 // CHECK23-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]] 11712 // CHECK23-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 11713 // CHECK23-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 11714 // CHECK23-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 11715 // CHECK23-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]] 11716 // CHECK23-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 11717 // CHECK23-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 11718 // CHECK23-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] 11719 // CHECK23-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 11720 // CHECK23-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] 11721 // CHECK23-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 11722 // CHECK23-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]] 11723 // CHECK23-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3 11724 // CHECK23-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]] 11725 // CHECK23-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 11726 // CHECK23-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]] 11727 // CHECK23-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 11728 // CHECK23-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP24]] 11729 // CHECK23-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 11730 // CHECK23-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP24]] 11731 // CHECK23-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 11732 // CHECK23-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP24]] 11733 // CHECK23-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 11734 // CHECK23-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 11735 // CHECK23-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 11736 // CHECK23-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP24]] 11737 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11738 // CHECK23: omp.body.continue: 11739 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11740 // CHECK23: omp.inner.for.inc: 11741 // CHECK23-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 11742 // CHECK23-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 11743 // CHECK23-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 11744 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 11745 // CHECK23: omp.inner.for.end: 11746 // CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 11747 // CHECK23: omp.dispatch.inc: 11748 // CHECK23-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 11749 // CHECK23-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 11750 // CHECK23-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 11751 // CHECK23-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 11752 // CHECK23-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11753 // CHECK23-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 11754 // CHECK23-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 11755 // CHECK23-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 11756 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND]] 11757 // CHECK23: omp.dispatch.end: 11758 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 11759 // CHECK23-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11760 // CHECK23-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 11761 // CHECK23-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11762 // CHECK23: .omp.final.then: 11763 // CHECK23-NEXT: store i8 96, ptr [[IT]], align 1 11764 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 11765 // CHECK23: .omp.final.done: 11766 // CHECK23-NEXT: ret void 11767 // 11768 // 11769 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 11770 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11771 // CHECK23-NEXT: entry: 11772 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11773 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11774 // CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 11775 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 11776 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11777 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11778 // CHECK23-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 11779 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11780 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 11781 // CHECK23-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 11782 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 11783 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 11784 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 11785 // CHECK23-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 11786 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 11787 // CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 11788 // CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 11789 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 11790 // CHECK23-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 11791 // CHECK23-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 11792 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 11793 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @.omp_outlined..4, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]]) 11794 // CHECK23-NEXT: ret void 11795 // 11796 // 11797 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4 11798 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 11799 // CHECK23-NEXT: entry: 11800 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 11801 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 11802 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11803 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11804 // CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 11805 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 11806 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11807 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 11808 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 11809 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 11810 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11811 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 11812 // CHECK23-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 11813 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 11814 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 11815 // CHECK23-NEXT: ret void 11816 // 11817 // 11818 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 11819 // CHECK23-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 11820 // CHECK23-NEXT: entry: 11821 // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 11822 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 11823 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11824 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11825 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 11826 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 11827 // CHECK23-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 11828 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 11829 // CHECK23-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 11830 // CHECK23-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 11831 // CHECK23-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 11832 // CHECK23-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 11833 // CHECK23-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 11834 // CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 11835 // CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 11836 // CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 11837 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 11838 // CHECK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 11839 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 11840 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 11841 // CHECK23-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 4 11842 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4 11843 // CHECK23-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 11844 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4 11845 // CHECK23-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 11846 // CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 11847 // CHECK23-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 11848 // CHECK23-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 11849 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 11850 // CHECK23-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 11851 // CHECK23-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1 11852 // CHECK23-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11853 // CHECK23: omp_if.then: 11854 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @.omp_outlined..5, ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) 11855 // CHECK23-NEXT: br label [[OMP_IF_END:%.*]] 11856 // CHECK23: omp_if.else: 11857 // CHECK23-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 11858 // CHECK23-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 11859 // CHECK23-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 11860 // CHECK23-NEXT: call void @.omp_outlined..5(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) #[[ATTR2:[0-9]+]] 11861 // CHECK23-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 11862 // CHECK23-NEXT: br label [[OMP_IF_END]] 11863 // CHECK23: omp_if.end: 11864 // CHECK23-NEXT: ret void 11865 // 11866 // 11867 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..5 11868 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 11869 // CHECK23-NEXT: entry: 11870 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 11871 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 11872 // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 11873 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 11874 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11875 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11876 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 11877 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 11878 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11879 // CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4 11880 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11881 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11882 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11883 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11884 // CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 8 11885 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 11886 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 11887 // CHECK23-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 11888 // CHECK23-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 11889 // CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 11890 // CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 11891 // CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 11892 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 11893 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 11894 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 11895 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 11896 // CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 11897 // CHECK23-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 11898 // CHECK23-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 11899 // CHECK23-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 11900 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11901 // CHECK23-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 11902 // CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 11903 // CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11904 // CHECK23: omp_if.then: 11905 // CHECK23-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 11906 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 11907 // CHECK23-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 11908 // CHECK23-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11909 // CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 11910 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11911 // CHECK23: cond.true: 11912 // CHECK23-NEXT: br label [[COND_END:%.*]] 11913 // CHECK23: cond.false: 11914 // CHECK23-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11915 // CHECK23-NEXT: br label [[COND_END]] 11916 // CHECK23: cond.end: 11917 // CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 11918 // CHECK23-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 11919 // CHECK23-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 11920 // CHECK23-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV]], align 8 11921 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11922 // CHECK23: omp.inner.for.cond: 11923 // CHECK23-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27:![0-9]+]] 11924 // CHECK23-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP27]] 11925 // CHECK23-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 11926 // CHECK23-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11927 // CHECK23: omp.inner.for.body: 11928 // CHECK23-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 11929 // CHECK23-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 11930 // CHECK23-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 11931 // CHECK23-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP27]] 11932 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 11933 // CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double 11934 // CHECK23-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 11935 // CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 11936 // CHECK23-NEXT: store double [[ADD]], ptr [[A]], align 4, !nontemporal !28, !llvm.access.group [[ACC_GRP27]] 11937 // CHECK23-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 11938 // CHECK23-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 4, !nontemporal !28, !llvm.access.group [[ACC_GRP27]] 11939 // CHECK23-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 11940 // CHECK23-NEXT: store double [[INC]], ptr [[A4]], align 4, !nontemporal !28, !llvm.access.group [[ACC_GRP27]] 11941 // CHECK23-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 11942 // CHECK23-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]] 11943 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP15]] 11944 // CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 11945 // CHECK23-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP27]] 11946 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11947 // CHECK23: omp.body.continue: 11948 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11949 // CHECK23: omp.inner.for.inc: 11950 // CHECK23-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 11951 // CHECK23-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1 11952 // CHECK23-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 11953 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] 11954 // CHECK23: omp.inner.for.end: 11955 // CHECK23-NEXT: br label [[OMP_IF_END:%.*]] 11956 // CHECK23: omp_if.else: 11957 // CHECK23-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 11958 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 11959 // CHECK23-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP18]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 11960 // CHECK23-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11961 // CHECK23-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[TMP19]], 3 11962 // CHECK23-NEXT: br i1 [[CMP8]], label [[COND_TRUE9:%.*]], label [[COND_FALSE10:%.*]] 11963 // CHECK23: cond.true9: 11964 // CHECK23-NEXT: br label [[COND_END11:%.*]] 11965 // CHECK23: cond.false10: 11966 // CHECK23-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11967 // CHECK23-NEXT: br label [[COND_END11]] 11968 // CHECK23: cond.end11: 11969 // CHECK23-NEXT: [[COND12:%.*]] = phi i64 [ 3, [[COND_TRUE9]] ], [ [[TMP20]], [[COND_FALSE10]] ] 11970 // CHECK23-NEXT: store i64 [[COND12]], ptr [[DOTOMP_UB]], align 8 11971 // CHECK23-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 11972 // CHECK23-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV]], align 8 11973 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 11974 // CHECK23: omp.inner.for.cond13: 11975 // CHECK23-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 11976 // CHECK23-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11977 // CHECK23-NEXT: [[CMP14:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 11978 // CHECK23-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END29:%.*]] 11979 // CHECK23: omp.inner.for.body15: 11980 // CHECK23-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 11981 // CHECK23-NEXT: [[MUL16:%.*]] = mul i64 [[TMP24]], 400 11982 // CHECK23-NEXT: [[SUB17:%.*]] = sub i64 2000, [[MUL16]] 11983 // CHECK23-NEXT: store i64 [[SUB17]], ptr [[IT]], align 8 11984 // CHECK23-NEXT: [[TMP25:%.*]] = load i32, ptr [[B_ADDR]], align 4 11985 // CHECK23-NEXT: [[CONV18:%.*]] = sitofp i32 [[TMP25]] to double 11986 // CHECK23-NEXT: [[ADD19:%.*]] = fadd double [[CONV18]], 1.500000e+00 11987 // CHECK23-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 11988 // CHECK23-NEXT: store double [[ADD19]], ptr [[A20]], align 4 11989 // CHECK23-NEXT: [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 11990 // CHECK23-NEXT: [[TMP26:%.*]] = load double, ptr [[A21]], align 4 11991 // CHECK23-NEXT: [[INC22:%.*]] = fadd double [[TMP26]], 1.000000e+00 11992 // CHECK23-NEXT: store double [[INC22]], ptr [[A21]], align 4 11993 // CHECK23-NEXT: [[CONV23:%.*]] = fptosi double [[INC22]] to i16 11994 // CHECK23-NEXT: [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]] 11995 // CHECK23-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP27]] 11996 // CHECK23-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX24]], i32 1 11997 // CHECK23-NEXT: store i16 [[CONV23]], ptr [[ARRAYIDX25]], align 2 11998 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] 11999 // CHECK23: omp.body.continue26: 12000 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] 12001 // CHECK23: omp.inner.for.inc27: 12002 // CHECK23-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 12003 // CHECK23-NEXT: [[ADD28:%.*]] = add i64 [[TMP28]], 1 12004 // CHECK23-NEXT: store i64 [[ADD28]], ptr [[DOTOMP_IV]], align 8 12005 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP31:![0-9]+]] 12006 // CHECK23: omp.inner.for.end29: 12007 // CHECK23-NEXT: br label [[OMP_IF_END]] 12008 // CHECK23: omp_if.end: 12009 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12010 // CHECK23: omp.loop.exit: 12011 // CHECK23-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 12012 // CHECK23-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4 12013 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]]) 12014 // CHECK23-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 12015 // CHECK23-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 12016 // CHECK23-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12017 // CHECK23: .omp.final.then: 12018 // CHECK23-NEXT: store i64 400, ptr [[IT]], align 8 12019 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12020 // CHECK23: .omp.final.done: 12021 // CHECK23-NEXT: ret void 12022 // 12023 // 12024 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 12025 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 12026 // CHECK23-NEXT: entry: 12027 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12028 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12029 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 12030 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 12031 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12032 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 12033 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 12034 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 12035 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 12036 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 12037 // CHECK23-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 12038 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 12039 // CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 12040 // CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 12041 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 12042 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..6, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) 12043 // CHECK23-NEXT: ret void 12044 // 12045 // 12046 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..6 12047 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 12048 // CHECK23-NEXT: entry: 12049 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 12050 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 12051 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12052 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12053 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 12054 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 12055 // CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4 12056 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 12057 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 12058 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 12059 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12060 // CHECK23-NEXT: [[I:%.*]] = alloca i64, align 8 12061 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 12062 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 12063 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 12064 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 12065 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 12066 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 12067 // CHECK23-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 12068 // CHECK23-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 12069 // CHECK23-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 12070 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 12071 // CHECK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 12072 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 12073 // CHECK23-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 12074 // CHECK23-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 12075 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 12076 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12077 // CHECK23: cond.true: 12078 // CHECK23-NEXT: br label [[COND_END:%.*]] 12079 // CHECK23: cond.false: 12080 // CHECK23-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 12081 // CHECK23-NEXT: br label [[COND_END]] 12082 // CHECK23: cond.end: 12083 // CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 12084 // CHECK23-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 12085 // CHECK23-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 12086 // CHECK23-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 12087 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12088 // CHECK23: omp.inner.for.cond: 12089 // CHECK23-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33:![0-9]+]] 12090 // CHECK23-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP33]] 12091 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 12092 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12093 // CHECK23: omp.inner.for.body: 12094 // CHECK23-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33]] 12095 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 12096 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 12097 // CHECK23-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP33]] 12098 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 12099 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 12100 // CHECK23-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 12101 // CHECK23-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] 12102 // CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 12103 // CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 12104 // CHECK23-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 12105 // CHECK23-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] 12106 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 12107 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] 12108 // CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 12109 // CHECK23-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] 12110 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12111 // CHECK23: omp.body.continue: 12112 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12113 // CHECK23: omp.inner.for.inc: 12114 // CHECK23-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33]] 12115 // CHECK23-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 12116 // CHECK23-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33]] 12117 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 12118 // CHECK23: omp.inner.for.end: 12119 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12120 // CHECK23: omp.loop.exit: 12121 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 12122 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 12123 // CHECK23-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 12124 // CHECK23-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12125 // CHECK23: .omp.final.then: 12126 // CHECK23-NEXT: store i64 11, ptr [[I]], align 8 12127 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12128 // CHECK23: .omp.final.done: 12129 // CHECK23-NEXT: ret void 12130 // 12131