1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 9 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 20 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 21 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 22 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 23 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 24 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 25 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 26 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 27 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 28 29 // Test target codegen - host bc file has to be created first. 30 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 31 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 33 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 34 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 35 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 36 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 37 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 38 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 39 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 40 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 41 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 42 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 43 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 44 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 45 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 46 47 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 48 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 49 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 50 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 51 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 52 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 53 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 54 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 55 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 56 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 57 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 58 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 59 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 60 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 61 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 62 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 63 64 // expected-no-diagnostics 65 #ifndef HEADER 66 #define HEADER 67 68 69 70 // We have 8 target regions, but only 7 that actually will generate offloading 71 // code, only 6 will have mapped arguments, and only 4 have all-constant map 72 // sizes. 73 74 75 76 // Check target registration is registered as a Ctor. 77 78 79 template<typename tx, typename ty> 80 struct TT{ 81 tx X; 82 ty Y; 83 }; 84 85 long long get_val() { return 0; } 86 87 int foo(int n) { 88 int a = 0; 89 short aa = 0; 90 float b[10]; 91 float bn[n]; 92 double c[5][10]; 93 double cn[5][n]; 94 TT<long long, char> d; 95 96 #pragma omp target parallel for simd nowait 97 for (int i = 3; i < 32; i += 5) { 98 } 99 100 long long k = get_val(); 101 #pragma omp target parallel for simd if(target: 0) linear(k : 3) schedule(dynamic) 102 for (int i = 10; i > 1; i--) { 103 a += 1; 104 } 105 106 107 int lin = 12; 108 #pragma omp target parallel for simd if(target: 1) linear(lin, a : get_val()) 109 for (unsigned long long it = 2000; it >= 600; it-=400) { 110 aa += 1; 111 } 112 113 114 115 116 #pragma omp target parallel for simd if(target: n>10) 117 for (short it = 6; it <= 20; it-=-4) { 118 a += 1; 119 aa += 1; 120 } 121 122 // We capture 3 VLA sizes in this target region 123 124 125 126 127 128 // The names below are not necessarily consistent with the names used for the 129 // addresses above as some are repeated. 130 131 132 133 134 135 136 137 138 139 140 #pragma omp target parallel for simd if(target: n>20) schedule(static, a) 141 for (unsigned char it = 'z'; it >= 'a'; it+=-1) { 142 a += 1; 143 b[2] += 1.0; 144 bn[3] += 1.0; 145 c[1][2] += 1.0; 146 cn[1][3] += 1.0; 147 d.X += 1; 148 d.Y += 1; 149 } 150 151 return a; 152 } 153 154 // Check that the offloading functions are emitted and that the arguments are 155 // correct and loaded correctly for the target regions in foo(). 156 157 158 159 160 // Create stack storage and store argument in there. 161 162 // Create stack storage and store argument in there. 163 164 // Create stack storage and store argument in there. 165 166 // Create local storage for each capture. 167 168 169 170 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 171 172 template<typename tx> 173 tx ftemplate(int n) { 174 tx a = 0; 175 short aa = 0; 176 tx b[10]; 177 178 #pragma omp target parallel for simd if(target: n>40) 179 for (long long i = -10; i < 10; i += 3) { 180 a += 1; 181 aa += 1; 182 b[2] += 1; 183 } 184 185 return a; 186 } 187 188 static 189 int fstatic(int n) { 190 int a = 0; 191 short aa = 0; 192 char aaa = 0; 193 int b[10]; 194 195 #pragma omp target parallel for simd if(target: n>50) 196 for (unsigned i=100; i<10; i+=10) { 197 a += 1; 198 aa += 1; 199 aaa += 1; 200 b[2] += 1; 201 } 202 203 return a; 204 } 205 206 struct S1 { 207 double a; 208 209 int r1(int n){ 210 int b = n+1; 211 short int c[2][n]; 212 213 #ifdef OMP5 214 #pragma omp target parallel for simd if(n>60) nontemporal(a) 215 #else 216 #pragma omp target parallel for simd if(target: n>60) 217 #endif // OMP5 218 for (unsigned long long it = 2000; it >= 600; it -= 400) { 219 this->a = (double)b + 1.5; 220 c[1][1] = ++a; 221 } 222 223 return c[1][1] + (int)b; 224 } 225 }; 226 227 int bar(int n){ 228 int a = 0; 229 230 a += foo(n); 231 232 S1 S; 233 a += S.r1(n); 234 235 a += fstatic(n); 236 237 a += ftemplate<int>(n); 238 239 return a; 240 } 241 242 243 244 // We capture 2 VLA sizes in this target region 245 246 247 // The names below are not necessarily consistent with the names used for the 248 // addresses above as some are repeated. 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 // Check that the offloading functions are emitted and that the arguments are 269 // correct and loaded correctly for the target regions of the callees of bar(). 270 271 // Create local storage for each capture. 272 // Store captures in the context. 273 274 275 276 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 277 278 279 // Create local storage for each capture. 280 // Store captures in the context. 281 282 283 284 285 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 286 287 // Create local storage for each capture. 288 // Store captures in the context. 289 290 291 292 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 293 294 295 #endif 296 // CHECK1-LABEL: define {{[^@]+}}@_Z7get_valv 297 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 298 // CHECK1-NEXT: entry: 299 // CHECK1-NEXT: ret i64 0 300 // 301 // 302 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 303 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 304 // CHECK1-NEXT: entry: 305 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 306 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 307 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 308 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 309 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 310 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 311 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 312 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 313 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 314 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 315 // CHECK1-NEXT: [[K:%.*]] = alloca i64, align 8 316 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 317 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 318 // CHECK1-NEXT: [[LIN:%.*]] = alloca i32, align 4 319 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 320 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 321 // CHECK1-NEXT: [[A_CASTED2:%.*]] = alloca i64, align 8 322 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 323 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 324 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 325 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 326 // CHECK1-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 327 // CHECK1-NEXT: [[AA_CASTED4:%.*]] = alloca i64, align 8 328 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 8 329 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 8 330 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 8 331 // CHECK1-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 332 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 333 // CHECK1-NEXT: [[A_CASTED11:%.*]] = alloca i64, align 8 334 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 335 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 8 336 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 8 337 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 8 338 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 339 // CHECK1-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 340 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 341 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 342 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 343 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 344 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 345 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 346 // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0() 347 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 348 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 349 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 350 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 351 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 352 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 353 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 354 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 355 // CHECK1-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, ptr @.omp_task_entry., i64 -1) 356 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP7]], i32 0, i32 0 357 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP7]]) 358 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 359 // CHECK1-NEXT: store i64 [[CALL]], ptr [[K]], align 8 360 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4 361 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4 362 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8 363 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[K]], align 8 364 // CHECK1-NEXT: store i64 [[TMP12]], ptr [[K_CASTED]], align 8 365 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, ptr [[K_CASTED]], align 8 366 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR3:[0-9]+]] 367 // CHECK1-NEXT: store i32 12, ptr [[LIN]], align 4 368 // CHECK1-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2 369 // CHECK1-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2 370 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[AA_CASTED]], align 8 371 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[LIN]], align 4 372 // CHECK1-NEXT: store i32 [[TMP16]], ptr [[LIN_CASTED]], align 4 373 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 374 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A]], align 4 375 // CHECK1-NEXT: store i32 [[TMP18]], ptr [[A_CASTED2]], align 4 376 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[A_CASTED2]], align 8 377 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 378 // CHECK1-NEXT: store i64 [[TMP15]], ptr [[TMP20]], align 8 379 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 380 // CHECK1-NEXT: store i64 [[TMP15]], ptr [[TMP21]], align 8 381 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 382 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 383 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 384 // CHECK1-NEXT: store i64 [[TMP17]], ptr [[TMP23]], align 8 385 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 386 // CHECK1-NEXT: store i64 [[TMP17]], ptr [[TMP24]], align 8 387 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 388 // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 389 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 390 // CHECK1-NEXT: store i64 [[TMP19]], ptr [[TMP26]], align 8 391 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 392 // CHECK1-NEXT: store i64 [[TMP19]], ptr [[TMP27]], align 8 393 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 394 // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8 395 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 396 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 397 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 398 // CHECK1-NEXT: store i32 3, ptr [[TMP31]], align 4 399 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 400 // CHECK1-NEXT: store i32 3, ptr [[TMP32]], align 4 401 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 402 // CHECK1-NEXT: store ptr [[TMP29]], ptr [[TMP33]], align 8 403 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 404 // CHECK1-NEXT: store ptr [[TMP30]], ptr [[TMP34]], align 8 405 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 406 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP35]], align 8 407 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 408 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP36]], align 8 409 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 410 // CHECK1-NEXT: store ptr null, ptr [[TMP37]], align 8 411 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 412 // CHECK1-NEXT: store ptr null, ptr [[TMP38]], align 8 413 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 414 // CHECK1-NEXT: store i64 0, ptr [[TMP39]], align 8 415 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 416 // CHECK1-NEXT: store i64 0, ptr [[TMP40]], align 8 417 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 418 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP41]], align 4 419 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 420 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP42]], align 4 421 // CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 422 // CHECK1-NEXT: store i32 0, ptr [[TMP43]], align 4 423 // CHECK1-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, ptr [[KERNEL_ARGS]]) 424 // CHECK1-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 425 // CHECK1-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 426 // CHECK1: omp_offload.failed: 427 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]]) #[[ATTR3]] 428 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 429 // CHECK1: omp_offload.cont: 430 // CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 431 // CHECK1-NEXT: store i32 [[TMP46]], ptr [[A_CASTED3]], align 4 432 // CHECK1-NEXT: [[TMP47:%.*]] = load i64, ptr [[A_CASTED3]], align 8 433 // CHECK1-NEXT: [[TMP48:%.*]] = load i16, ptr [[AA]], align 2 434 // CHECK1-NEXT: store i16 [[TMP48]], ptr [[AA_CASTED4]], align 2 435 // CHECK1-NEXT: [[TMP49:%.*]] = load i64, ptr [[AA_CASTED4]], align 8 436 // CHECK1-NEXT: [[TMP50:%.*]] = load i32, ptr [[N_ADDR]], align 4 437 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP50]], 10 438 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 439 // CHECK1: omp_if.then: 440 // CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 441 // CHECK1-NEXT: store i64 [[TMP47]], ptr [[TMP51]], align 8 442 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 443 // CHECK1-NEXT: store i64 [[TMP47]], ptr [[TMP52]], align 8 444 // CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 445 // CHECK1-NEXT: store ptr null, ptr [[TMP53]], align 8 446 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 447 // CHECK1-NEXT: store i64 [[TMP49]], ptr [[TMP54]], align 8 448 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 449 // CHECK1-NEXT: store i64 [[TMP49]], ptr [[TMP55]], align 8 450 // CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 451 // CHECK1-NEXT: store ptr null, ptr [[TMP56]], align 8 452 // CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 453 // CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 454 // CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0 455 // CHECK1-NEXT: store i32 3, ptr [[TMP59]], align 4 456 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1 457 // CHECK1-NEXT: store i32 2, ptr [[TMP60]], align 4 458 // CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2 459 // CHECK1-NEXT: store ptr [[TMP57]], ptr [[TMP61]], align 8 460 // CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3 461 // CHECK1-NEXT: store ptr [[TMP58]], ptr [[TMP62]], align 8 462 // CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4 463 // CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP63]], align 8 464 // CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5 465 // CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP64]], align 8 466 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6 467 // CHECK1-NEXT: store ptr null, ptr [[TMP65]], align 8 468 // CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7 469 // CHECK1-NEXT: store ptr null, ptr [[TMP66]], align 8 470 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8 471 // CHECK1-NEXT: store i64 0, ptr [[TMP67]], align 8 472 // CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 9 473 // CHECK1-NEXT: store i64 0, ptr [[TMP68]], align 8 474 // CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 10 475 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP69]], align 4 476 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 11 477 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP70]], align 4 478 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12 479 // CHECK1-NEXT: store i32 0, ptr [[TMP71]], align 4 480 // CHECK1-NEXT: [[TMP72:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, ptr [[KERNEL_ARGS8]]) 481 // CHECK1-NEXT: [[TMP73:%.*]] = icmp ne i32 [[TMP72]], 0 482 // CHECK1-NEXT: br i1 [[TMP73]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 483 // CHECK1: omp_offload.failed9: 484 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR3]] 485 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT10]] 486 // CHECK1: omp_offload.cont10: 487 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 488 // CHECK1: omp_if.else: 489 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR3]] 490 // CHECK1-NEXT: br label [[OMP_IF_END]] 491 // CHECK1: omp_if.end: 492 // CHECK1-NEXT: [[TMP74:%.*]] = load i32, ptr [[A]], align 4 493 // CHECK1-NEXT: store i32 [[TMP74]], ptr [[DOTCAPTURE_EXPR_]], align 4 494 // CHECK1-NEXT: [[TMP75:%.*]] = load i32, ptr [[A]], align 4 495 // CHECK1-NEXT: store i32 [[TMP75]], ptr [[A_CASTED11]], align 4 496 // CHECK1-NEXT: [[TMP76:%.*]] = load i64, ptr [[A_CASTED11]], align 8 497 // CHECK1-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 498 // CHECK1-NEXT: store i32 [[TMP77]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 499 // CHECK1-NEXT: [[TMP78:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 500 // CHECK1-NEXT: [[TMP79:%.*]] = load i32, ptr [[N_ADDR]], align 4 501 // CHECK1-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP79]], 20 502 // CHECK1-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]] 503 // CHECK1: omp_if.then13: 504 // CHECK1-NEXT: [[TMP80:%.*]] = mul nuw i64 [[TMP2]], 4 505 // CHECK1-NEXT: [[TMP81:%.*]] = mul nuw i64 5, [[TMP5]] 506 // CHECK1-NEXT: [[TMP82:%.*]] = mul nuw i64 [[TMP81]], 8 507 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.3, i64 80, i1 false) 508 // CHECK1-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 509 // CHECK1-NEXT: store i64 [[TMP76]], ptr [[TMP83]], align 8 510 // CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 511 // CHECK1-NEXT: store i64 [[TMP76]], ptr [[TMP84]], align 8 512 // CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0 513 // CHECK1-NEXT: store ptr null, ptr [[TMP85]], align 8 514 // CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 515 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP86]], align 8 516 // CHECK1-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 517 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP87]], align 8 518 // CHECK1-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1 519 // CHECK1-NEXT: store ptr null, ptr [[TMP88]], align 8 520 // CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 521 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP89]], align 8 522 // CHECK1-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 523 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP90]], align 8 524 // CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 2 525 // CHECK1-NEXT: store ptr null, ptr [[TMP91]], align 8 526 // CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 527 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP92]], align 8 528 // CHECK1-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 529 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP93]], align 8 530 // CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 531 // CHECK1-NEXT: store i64 [[TMP80]], ptr [[TMP94]], align 8 532 // CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 3 533 // CHECK1-NEXT: store ptr null, ptr [[TMP95]], align 8 534 // CHECK1-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 535 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP96]], align 8 536 // CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 537 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP97]], align 8 538 // CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 4 539 // CHECK1-NEXT: store ptr null, ptr [[TMP98]], align 8 540 // CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 541 // CHECK1-NEXT: store i64 5, ptr [[TMP99]], align 8 542 // CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 543 // CHECK1-NEXT: store i64 5, ptr [[TMP100]], align 8 544 // CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 5 545 // CHECK1-NEXT: store ptr null, ptr [[TMP101]], align 8 546 // CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 547 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP102]], align 8 548 // CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 549 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP103]], align 8 550 // CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 6 551 // CHECK1-NEXT: store ptr null, ptr [[TMP104]], align 8 552 // CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 553 // CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP105]], align 8 554 // CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 555 // CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP106]], align 8 556 // CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 557 // CHECK1-NEXT: store i64 [[TMP82]], ptr [[TMP107]], align 8 558 // CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 7 559 // CHECK1-NEXT: store ptr null, ptr [[TMP108]], align 8 560 // CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 561 // CHECK1-NEXT: store ptr [[D]], ptr [[TMP109]], align 8 562 // CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 563 // CHECK1-NEXT: store ptr [[D]], ptr [[TMP110]], align 8 564 // CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 8 565 // CHECK1-NEXT: store ptr null, ptr [[TMP111]], align 8 566 // CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 567 // CHECK1-NEXT: store i64 [[TMP78]], ptr [[TMP112]], align 8 568 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 569 // CHECK1-NEXT: store i64 [[TMP78]], ptr [[TMP113]], align 8 570 // CHECK1-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 9 571 // CHECK1-NEXT: store ptr null, ptr [[TMP114]], align 8 572 // CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 573 // CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 574 // CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 575 // CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0 576 // CHECK1-NEXT: store i32 3, ptr [[TMP118]], align 4 577 // CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1 578 // CHECK1-NEXT: store i32 10, ptr [[TMP119]], align 4 579 // CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2 580 // CHECK1-NEXT: store ptr [[TMP115]], ptr [[TMP120]], align 8 581 // CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3 582 // CHECK1-NEXT: store ptr [[TMP116]], ptr [[TMP121]], align 8 583 // CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4 584 // CHECK1-NEXT: store ptr [[TMP117]], ptr [[TMP122]], align 8 585 // CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5 586 // CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP123]], align 8 587 // CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6 588 // CHECK1-NEXT: store ptr null, ptr [[TMP124]], align 8 589 // CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7 590 // CHECK1-NEXT: store ptr null, ptr [[TMP125]], align 8 591 // CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8 592 // CHECK1-NEXT: store i64 0, ptr [[TMP126]], align 8 593 // CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 9 594 // CHECK1-NEXT: store i64 0, ptr [[TMP127]], align 8 595 // CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 10 596 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP128]], align 4 597 // CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 11 598 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP129]], align 4 599 // CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12 600 // CHECK1-NEXT: store i32 0, ptr [[TMP130]], align 4 601 // CHECK1-NEXT: [[TMP131:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, ptr [[KERNEL_ARGS17]]) 602 // CHECK1-NEXT: [[TMP132:%.*]] = icmp ne i32 [[TMP131]], 0 603 // CHECK1-NEXT: br i1 [[TMP132]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] 604 // CHECK1: omp_offload.failed18: 605 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR3]] 606 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT19]] 607 // CHECK1: omp_offload.cont19: 608 // CHECK1-NEXT: br label [[OMP_IF_END21:%.*]] 609 // CHECK1: omp_if.else20: 610 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR3]] 611 // CHECK1-NEXT: br label [[OMP_IF_END21]] 612 // CHECK1: omp_if.end21: 613 // CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[A]], align 4 614 // CHECK1-NEXT: [[TMP134:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 615 // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP134]]) 616 // CHECK1-NEXT: ret i32 [[TMP133]] 617 // 618 // 619 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 620 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] { 621 // CHECK1-NEXT: entry: 622 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) 623 // CHECK1-NEXT: ret void 624 // 625 // 626 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined 627 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { 628 // CHECK1-NEXT: entry: 629 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 630 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 631 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 632 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 633 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 634 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 635 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 636 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 637 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 638 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 639 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 640 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 641 // CHECK1-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 642 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 643 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 644 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 645 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 646 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 647 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 648 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 649 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 650 // CHECK1: cond.true: 651 // CHECK1-NEXT: br label [[COND_END:%.*]] 652 // CHECK1: cond.false: 653 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 654 // CHECK1-NEXT: br label [[COND_END]] 655 // CHECK1: cond.end: 656 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 657 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 658 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 659 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 660 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 661 // CHECK1: omp.inner.for.cond: 662 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 663 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 664 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 665 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 666 // CHECK1: omp.inner.for.body: 667 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 668 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 669 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 670 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 671 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 672 // CHECK1: omp.body.continue: 673 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 674 // CHECK1: omp.inner.for.inc: 675 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 676 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 677 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 678 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 679 // CHECK1: omp.inner.for.end: 680 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 681 // CHECK1: omp.loop.exit: 682 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 683 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 684 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 685 // CHECK1-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 686 // CHECK1: .omp.final.then: 687 // CHECK1-NEXT: store i32 33, ptr [[I]], align 4 688 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 689 // CHECK1: .omp.final.done: 690 // CHECK1-NEXT: ret void 691 // 692 // 693 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 694 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { 695 // CHECK1-NEXT: entry: 696 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 697 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 698 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 699 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 700 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 701 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 702 // CHECK1-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 703 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 704 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 705 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 706 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 707 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 708 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 709 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 710 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 711 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 712 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 713 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 714 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 715 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 716 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 717 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META25:![0-9]+]] 718 // CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META25]] 719 // CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META25]] 720 // CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META25]] 721 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META25]] 722 // CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META25]] 723 // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META25]] 724 // CHECK1-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META25]] 725 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 726 // CHECK1-NEXT: store i32 0, ptr [[TMP9]], align 4, !noalias [[META25]] 727 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 728 // CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8, !noalias [[META25]] 729 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 730 // CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8, !noalias [[META25]] 731 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 732 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8, !noalias [[META25]] 733 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 734 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8, !noalias [[META25]] 735 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 736 // CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8, !noalias [[META25]] 737 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 738 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8, !noalias [[META25]] 739 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 740 // CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8, !noalias [[META25]] 741 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9 742 // CHECK1-NEXT: store i64 1, ptr [[TMP17]], align 8, !noalias [[META25]] 743 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10 744 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4, !noalias [[META25]] 745 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11 746 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4, !noalias [[META25]] 747 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12 748 // CHECK1-NEXT: store i32 0, ptr [[TMP20]], align 4, !noalias [[META25]] 749 // CHECK1-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, ptr [[KERNEL_ARGS_I]]) 750 // CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 751 // CHECK1-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] 752 // CHECK1: omp_offload.failed.i: 753 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR3]] 754 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] 755 // CHECK1: .omp_outlined..exit: 756 // CHECK1-NEXT: ret i32 0 757 // 758 // 759 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 760 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] { 761 // CHECK1-NEXT: entry: 762 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 763 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 764 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 765 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 766 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 767 // CHECK1-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8 768 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 769 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 770 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 771 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[K_ADDR]], align 8 772 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[K_CASTED]], align 8 773 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[K_CASTED]], align 8 774 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) 775 // CHECK1-NEXT: ret void 776 // 777 // 778 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined 779 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] { 780 // CHECK1-NEXT: entry: 781 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 782 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 783 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 784 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 785 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 786 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 787 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 788 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 789 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 790 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 791 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 792 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 793 // CHECK1-NEXT: [[K1:%.*]] = alloca i64, align 8 794 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 795 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 796 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 797 // CHECK1-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8 798 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[K_ADDR]], align 8 799 // CHECK1-NEXT: store i64 [[TMP0]], ptr [[DOTLINEAR_START]], align 8 800 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 801 // CHECK1-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 4 802 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 803 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 804 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 805 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 806 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 807 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1) 808 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 809 // CHECK1: omp.dispatch.cond: 810 // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP2]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]) 811 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 812 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 813 // CHECK1: omp.dispatch.body: 814 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 815 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 816 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 817 // CHECK1: omp.inner.for.cond: 818 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] 819 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] 820 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 821 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 822 // CHECK1: omp.inner.for.body: 823 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 824 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 825 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 826 // CHECK1-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] 827 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP26]] 828 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 829 // CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 830 // CHECK1-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 831 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV]] 832 // CHECK1-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP26]] 833 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] 834 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 835 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] 836 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 837 // CHECK1: omp.body.continue: 838 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 839 // CHECK1: omp.inner.for.inc: 840 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 841 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 842 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 843 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] 844 // CHECK1: omp.inner.for.end: 845 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 846 // CHECK1: omp.dispatch.inc: 847 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 848 // CHECK1: omp.dispatch.end: 849 // CHECK1-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP2]]) 850 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 851 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 852 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 853 // CHECK1: .omp.final.then: 854 // CHECK1-NEXT: store i32 1, ptr [[I]], align 4 855 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 856 // CHECK1: .omp.final.done: 857 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 858 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 859 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 860 // CHECK1: .omp.linear.pu: 861 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, ptr [[K1]], align 8 862 // CHECK1-NEXT: store i64 [[TMP16]], ptr [[K_ADDR]], align 8 863 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 864 // CHECK1: .omp.linear.pu.done: 865 // CHECK1-NEXT: ret void 866 // 867 // 868 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 869 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 870 // CHECK1-NEXT: entry: 871 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 872 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 873 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 874 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 875 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 876 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 877 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 878 // CHECK1-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 879 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 880 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 881 // CHECK1-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 882 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 883 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 884 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 885 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 886 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 887 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 888 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8 889 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 890 // CHECK1-NEXT: ret void 891 // 892 // 893 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined 894 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 895 // CHECK1-NEXT: entry: 896 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 897 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 898 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 899 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 900 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 901 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 902 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 903 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 904 // CHECK1-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 905 // CHECK1-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 906 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 907 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 908 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 909 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 910 // CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8 911 // CHECK1-NEXT: [[LIN2:%.*]] = alloca i32, align 4 912 // CHECK1-NEXT: [[A3:%.*]] = alloca i32, align 4 913 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 914 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 915 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 916 // CHECK1-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 917 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 918 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 919 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 920 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 921 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 922 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 923 // CHECK1-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 924 // CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 925 // CHECK1-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 926 // CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 927 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 928 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 929 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 930 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]]) 931 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 932 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 933 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 934 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 935 // CHECK1: cond.true: 936 // CHECK1-NEXT: br label [[COND_END:%.*]] 937 // CHECK1: cond.false: 938 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 939 // CHECK1-NEXT: br label [[COND_END]] 940 // CHECK1: cond.end: 941 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 942 // CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 943 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 944 // CHECK1-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 945 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 946 // CHECK1: omp.inner.for.cond: 947 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29:![0-9]+]] 948 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP29]] 949 // CHECK1-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 950 // CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 951 // CHECK1: omp.inner.for.body: 952 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 953 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 954 // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 955 // CHECK1-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP29]] 956 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP29]] 957 // CHECK1-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 958 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 959 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]] 960 // CHECK1-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 961 // CHECK1-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 962 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 963 // CHECK1-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP29]] 964 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP29]] 965 // CHECK1-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 966 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 967 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]] 968 // CHECK1-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 969 // CHECK1-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 970 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 971 // CHECK1-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP29]] 972 // CHECK1-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] 973 // CHECK1-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 974 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 975 // CHECK1-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 976 // CHECK1-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] 977 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 978 // CHECK1: omp.body.continue: 979 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 980 // CHECK1: omp.inner.for.inc: 981 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 982 // CHECK1-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 983 // CHECK1-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 984 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] 985 // CHECK1: omp.inner.for.end: 986 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 987 // CHECK1: omp.loop.exit: 988 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 989 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 990 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 991 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 992 // CHECK1: .omp.final.then: 993 // CHECK1-NEXT: store i64 400, ptr [[IT]], align 8 994 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 995 // CHECK1: .omp.final.done: 996 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 997 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 998 // CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 999 // CHECK1: .omp.linear.pu: 1000 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 1001 // CHECK1-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 1002 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 1003 // CHECK1-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 1004 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 1005 // CHECK1: .omp.linear.pu.done: 1006 // CHECK1-NEXT: ret void 1007 // 1008 // 1009 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 1010 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1011 // CHECK1-NEXT: entry: 1012 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1013 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1014 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1015 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1016 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1017 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1018 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1019 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 1020 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 1021 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1022 // CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 1023 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1024 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) 1025 // CHECK1-NEXT: ret void 1026 // 1027 // 1028 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined 1029 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1030 // CHECK1-NEXT: entry: 1031 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1032 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1033 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1034 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1035 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1036 // CHECK1-NEXT: [[TMP:%.*]] = alloca i16, align 2 1037 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1038 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1039 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1040 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1041 // CHECK1-NEXT: [[IT:%.*]] = alloca i16, align 2 1042 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1043 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1044 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1045 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1046 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1047 // CHECK1-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 1048 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1049 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1050 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1051 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1052 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1053 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1054 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 1055 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1056 // CHECK1: cond.true: 1057 // CHECK1-NEXT: br label [[COND_END:%.*]] 1058 // CHECK1: cond.false: 1059 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1060 // CHECK1-NEXT: br label [[COND_END]] 1061 // CHECK1: cond.end: 1062 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1063 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1064 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1065 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1066 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1067 // CHECK1: omp.inner.for.cond: 1068 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]] 1069 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]] 1070 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1071 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1072 // CHECK1: omp.inner.for.body: 1073 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 1074 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 1075 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 1076 // CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 1077 // CHECK1-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP32]] 1078 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] 1079 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 1080 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] 1081 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] 1082 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 1083 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 1084 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 1085 // CHECK1-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] 1086 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1087 // CHECK1: omp.body.continue: 1088 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1089 // CHECK1: omp.inner.for.inc: 1090 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 1091 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 1092 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 1093 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] 1094 // CHECK1: omp.inner.for.end: 1095 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1096 // CHECK1: omp.loop.exit: 1097 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1098 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1099 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 1100 // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1101 // CHECK1: .omp.final.then: 1102 // CHECK1-NEXT: store i16 22, ptr [[IT]], align 2 1103 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1104 // CHECK1: .omp.final.done: 1105 // CHECK1-NEXT: ret void 1106 // 1107 // 1108 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 1109 // CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 1110 // CHECK1-NEXT: entry: 1111 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1112 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1113 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1114 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 1115 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1116 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1117 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1118 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 1119 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 1120 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1121 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1122 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1123 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1124 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1125 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1126 // CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 1127 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1128 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1129 // CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 1130 // CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 1131 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 1132 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 1133 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1134 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1135 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 1136 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1137 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1138 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 1139 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 1140 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 1141 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 1142 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 1143 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 1144 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 1145 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 1146 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 1147 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]]) 1148 // CHECK1-NEXT: ret void 1149 // 1150 // 1151 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined 1152 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 1153 // CHECK1-NEXT: entry: 1154 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1155 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1156 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1157 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1158 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1159 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 1160 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1161 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1162 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1163 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 1164 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 1165 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1166 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1167 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 1168 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1169 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1170 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1171 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1172 // CHECK1-NEXT: [[IT:%.*]] = alloca i8, align 1 1173 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1174 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1175 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1176 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1177 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1178 // CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 1179 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1180 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1181 // CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 1182 // CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 1183 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 1184 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 1185 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1186 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1187 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 1188 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1189 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1190 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 1191 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 1192 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 1193 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1194 // CHECK1-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 1195 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1196 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1197 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 1198 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1199 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 1200 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 1201 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1202 // CHECK1: omp.dispatch.cond: 1203 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1204 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 1205 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1206 // CHECK1: cond.true: 1207 // CHECK1-NEXT: br label [[COND_END:%.*]] 1208 // CHECK1: cond.false: 1209 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1210 // CHECK1-NEXT: br label [[COND_END]] 1211 // CHECK1: cond.end: 1212 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 1213 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1214 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1215 // CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 1216 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1217 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1218 // CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 1219 // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1220 // CHECK1: omp.dispatch.body: 1221 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1222 // CHECK1: omp.inner.for.cond: 1223 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]] 1224 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]] 1225 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 1226 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1227 // CHECK1: omp.inner.for.body: 1228 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 1229 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 1230 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 1231 // CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 1232 // CHECK1-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP35]] 1233 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] 1234 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 1235 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] 1236 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 1237 // CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] 1238 // CHECK1-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 1239 // CHECK1-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 1240 // CHECK1-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 1241 // CHECK1-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] 1242 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 1243 // CHECK1-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP35]] 1244 // CHECK1-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 1245 // CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 1246 // CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 1247 // CHECK1-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP35]] 1248 // CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 1249 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 1250 // CHECK1-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]] 1251 // CHECK1-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 1252 // CHECK1-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]] 1253 // CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 1254 // CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]] 1255 // CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3 1256 // CHECK1-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP35]] 1257 // CHECK1-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 1258 // CHECK1-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP35]] 1259 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 1260 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]] 1261 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 1262 // CHECK1-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]] 1263 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 1264 // CHECK1-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]] 1265 // CHECK1-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 1266 // CHECK1-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 1267 // CHECK1-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 1268 // CHECK1-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]] 1269 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1270 // CHECK1: omp.body.continue: 1271 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1272 // CHECK1: omp.inner.for.inc: 1273 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 1274 // CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 1275 // CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 1276 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] 1277 // CHECK1: omp.inner.for.end: 1278 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1279 // CHECK1: omp.dispatch.inc: 1280 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1281 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1282 // CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 1283 // CHECK1-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 1284 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1285 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1286 // CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 1287 // CHECK1-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 1288 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1289 // CHECK1: omp.dispatch.end: 1290 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 1291 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1292 // CHECK1-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 1293 // CHECK1-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1294 // CHECK1: .omp.final.then: 1295 // CHECK1-NEXT: store i8 96, ptr [[IT]], align 1 1296 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1297 // CHECK1: .omp.final.done: 1298 // CHECK1-NEXT: ret void 1299 // 1300 // 1301 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 1302 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1303 // CHECK1-NEXT: entry: 1304 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1305 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1306 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1307 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1308 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 1309 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 1310 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 1311 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 1312 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1313 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A]], align 4 1314 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 1315 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 1316 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 1317 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1318 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 1319 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 1320 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 1321 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 1322 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1323 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 1324 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 1325 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 1326 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 1327 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 1328 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 1329 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 1330 // CHECK1-NEXT: ret i32 [[TMP8]] 1331 // 1332 // 1333 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1334 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1335 // CHECK1-NEXT: entry: 1336 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1337 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1338 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 1339 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 1340 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1341 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1342 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 1343 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 1344 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 1345 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1346 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1347 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1348 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1349 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1350 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 1351 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1352 // CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4 1353 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 1354 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1355 // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0() 1356 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 1357 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 1358 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 1359 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 1360 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 1361 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 1362 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 1363 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 1364 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 1365 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1366 // CHECK1: omp_if.then: 1367 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 1368 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 1369 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 1370 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 40, i1 false) 1371 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1372 // CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 8 1373 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1374 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP11]], align 8 1375 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1376 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 1377 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1378 // CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP13]], align 8 1379 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1380 // CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP14]], align 8 1381 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1382 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 1383 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1384 // CHECK1-NEXT: store i64 2, ptr [[TMP16]], align 8 1385 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1386 // CHECK1-NEXT: store i64 2, ptr [[TMP17]], align 8 1387 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1388 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 1389 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1390 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP19]], align 8 1391 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1392 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP20]], align 8 1393 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1394 // CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8 1395 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1396 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 8 1397 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1398 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 8 1399 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1400 // CHECK1-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 8 1401 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1402 // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 1403 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1404 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1405 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1406 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1407 // CHECK1-NEXT: store i32 3, ptr [[TMP29]], align 4 1408 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1409 // CHECK1-NEXT: store i32 5, ptr [[TMP30]], align 4 1410 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1411 // CHECK1-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 8 1412 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1413 // CHECK1-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 8 1414 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1415 // CHECK1-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 8 1416 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1417 // CHECK1-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP34]], align 8 1418 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1419 // CHECK1-NEXT: store ptr null, ptr [[TMP35]], align 8 1420 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1421 // CHECK1-NEXT: store ptr null, ptr [[TMP36]], align 8 1422 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1423 // CHECK1-NEXT: store i64 0, ptr [[TMP37]], align 8 1424 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1425 // CHECK1-NEXT: store i64 0, ptr [[TMP38]], align 8 1426 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1427 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 4 1428 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1429 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4 1430 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1431 // CHECK1-NEXT: store i32 0, ptr [[TMP41]], align 4 1432 // CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, ptr [[KERNEL_ARGS]]) 1433 // CHECK1-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 1434 // CHECK1-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1435 // CHECK1: omp_offload.failed: 1436 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]] 1437 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1438 // CHECK1: omp_offload.cont: 1439 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1440 // CHECK1: omp_if.else: 1441 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]] 1442 // CHECK1-NEXT: br label [[OMP_IF_END]] 1443 // CHECK1: omp_if.end: 1444 // CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]] 1445 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]] 1446 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 1447 // CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 1448 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 1449 // CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 1450 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] 1451 // CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 1452 // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]]) 1453 // CHECK1-NEXT: ret i32 [[ADD3]] 1454 // 1455 // 1456 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 1457 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1458 // CHECK1-NEXT: entry: 1459 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1460 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1461 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1462 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 1463 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1464 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1465 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1466 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1467 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 1468 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 1469 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 1470 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1471 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1472 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 1473 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 1474 // CHECK1-NEXT: store i8 0, ptr [[AAA]], align 1 1475 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 1476 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 1477 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 1478 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 1479 // CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 1480 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1481 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1 1482 // CHECK1-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1 1483 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 1484 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 1485 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 1486 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1487 // CHECK1: omp_if.then: 1488 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1489 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP7]], align 8 1490 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1491 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP8]], align 8 1492 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1493 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 1494 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1495 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP10]], align 8 1496 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1497 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP11]], align 8 1498 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1499 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 1500 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1501 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP13]], align 8 1502 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1503 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP14]], align 8 1504 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1505 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 1506 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1507 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP16]], align 8 1508 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1509 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP17]], align 8 1510 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1511 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 1512 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1513 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1514 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1515 // CHECK1-NEXT: store i32 3, ptr [[TMP21]], align 4 1516 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1517 // CHECK1-NEXT: store i32 4, ptr [[TMP22]], align 4 1518 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1519 // CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8 1520 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1521 // CHECK1-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8 1522 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1523 // CHECK1-NEXT: store ptr @.offload_sizes.7, ptr [[TMP25]], align 8 1524 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1525 // CHECK1-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP26]], align 8 1526 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1527 // CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8 1528 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1529 // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8 1530 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1531 // CHECK1-NEXT: store i64 0, ptr [[TMP29]], align 8 1532 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1533 // CHECK1-NEXT: store i64 0, ptr [[TMP30]], align 8 1534 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1535 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4 1536 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1537 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 1538 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1539 // CHECK1-NEXT: store i32 0, ptr [[TMP33]], align 4 1540 // CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, ptr [[KERNEL_ARGS]]) 1541 // CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 1542 // CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1543 // CHECK1: omp_offload.failed: 1544 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]] 1545 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1546 // CHECK1: omp_offload.cont: 1547 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1548 // CHECK1: omp_if.else: 1549 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]] 1550 // CHECK1-NEXT: br label [[OMP_IF_END]] 1551 // CHECK1: omp_if.end: 1552 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 1553 // CHECK1-NEXT: ret i32 [[TMP36]] 1554 // 1555 // 1556 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1557 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1558 // CHECK1-NEXT: entry: 1559 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1560 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1561 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1562 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1563 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1564 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1565 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 1566 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 1567 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 1568 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1569 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1570 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 1571 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 1572 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 1573 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 1574 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 1575 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 1576 // CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 1577 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1578 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 1579 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1580 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1581 // CHECK1: omp_if.then: 1582 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1583 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 1584 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1585 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 8 1586 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1587 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 1588 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1589 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 8 1590 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1591 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP9]], align 8 1592 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1593 // CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8 1594 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1595 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP11]], align 8 1596 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1597 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP12]], align 8 1598 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1599 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8 1600 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1601 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1602 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1603 // CHECK1-NEXT: store i32 3, ptr [[TMP16]], align 4 1604 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1605 // CHECK1-NEXT: store i32 3, ptr [[TMP17]], align 4 1606 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1607 // CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8 1608 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1609 // CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8 1610 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1611 // CHECK1-NEXT: store ptr @.offload_sizes.9, ptr [[TMP20]], align 8 1612 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1613 // CHECK1-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP21]], align 8 1614 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1615 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 1616 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1617 // CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8 1618 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1619 // CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 8 1620 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1621 // CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 8 1622 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1623 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4 1624 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1625 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 1626 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1627 // CHECK1-NEXT: store i32 0, ptr [[TMP28]], align 4 1628 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, ptr [[KERNEL_ARGS]]) 1629 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 1630 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1631 // CHECK1: omp_offload.failed: 1632 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] 1633 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1634 // CHECK1: omp_offload.cont: 1635 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1636 // CHECK1: omp_if.else: 1637 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] 1638 // CHECK1-NEXT: br label [[OMP_IF_END]] 1639 // CHECK1: omp_if.end: 1640 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 1641 // CHECK1-NEXT: ret i32 [[TMP31]] 1642 // 1643 // 1644 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 1645 // CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1646 // CHECK1-NEXT: entry: 1647 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1648 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1649 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1650 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1651 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1652 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1653 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1654 // CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 1655 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1656 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1657 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1658 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1659 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1660 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1661 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1662 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 1663 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 1664 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8 1665 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) 1666 // CHECK1-NEXT: ret void 1667 // 1668 // 1669 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined 1670 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1671 // CHECK1-NEXT: entry: 1672 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1673 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1674 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1675 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1676 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1677 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1678 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1679 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1680 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 1681 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1682 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1683 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1684 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1685 // CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8 1686 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1687 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1688 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1689 // CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 1690 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1691 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1692 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1693 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1694 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1695 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1696 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1697 // CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 1698 // CHECK1-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 1699 // CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 1700 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1701 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1702 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 1703 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 1704 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 1705 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 1706 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1707 // CHECK1: cond.true: 1708 // CHECK1-NEXT: br label [[COND_END:%.*]] 1709 // CHECK1: cond.false: 1710 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 1711 // CHECK1-NEXT: br label [[COND_END]] 1712 // CHECK1: cond.end: 1713 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1714 // CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 1715 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 1716 // CHECK1-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8 1717 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1718 // CHECK1: omp.inner.for.cond: 1719 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38:![0-9]+]] 1720 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP38]] 1721 // CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 1722 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1723 // CHECK1: omp.inner.for.body: 1724 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 1725 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 1726 // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 1727 // CHECK1-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP38]] 1728 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]] 1729 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 1730 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 1731 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 1732 // CHECK1-NEXT: store double [[ADD]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP38]] 1733 // CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 1734 // CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP38]] 1735 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 1736 // CHECK1-NEXT: store double [[INC]], ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP38]] 1737 // CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 1738 // CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 1739 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]] 1740 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 1741 // CHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP38]] 1742 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1743 // CHECK1: omp.body.continue: 1744 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1745 // CHECK1: omp.inner.for.inc: 1746 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 1747 // CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 1748 // CHECK1-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 1749 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]] 1750 // CHECK1: omp.inner.for.end: 1751 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1752 // CHECK1: omp.loop.exit: 1753 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 1754 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1755 // CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 1756 // CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1757 // CHECK1: .omp.final.then: 1758 // CHECK1-NEXT: store i64 400, ptr [[IT]], align 8 1759 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1760 // CHECK1: .omp.final.done: 1761 // CHECK1-NEXT: ret void 1762 // 1763 // 1764 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 1765 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1766 // CHECK1-NEXT: entry: 1767 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1768 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1769 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1770 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1771 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1772 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1773 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1774 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1775 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1776 // CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 1777 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1778 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1779 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 1780 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 1781 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 1782 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1783 // CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 1784 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1785 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 1786 // CHECK1-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 1787 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 1788 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]]) 1789 // CHECK1-NEXT: ret void 1790 // 1791 // 1792 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined 1793 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1794 // CHECK1-NEXT: entry: 1795 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1796 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1797 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1798 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1799 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1800 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1801 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1802 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1803 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1804 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1805 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1806 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1807 // CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 1808 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1809 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1810 // CHECK1-NEXT: ret void 1811 // 1812 // 1813 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 1814 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1815 // CHECK1-NEXT: entry: 1816 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1817 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1818 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1819 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1820 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1821 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1822 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1823 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1824 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1825 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 1826 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 1827 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 1828 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1829 // CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 1830 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1831 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) 1832 // CHECK1-NEXT: ret void 1833 // 1834 // 1835 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined 1836 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1837 // CHECK1-NEXT: entry: 1838 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1839 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1840 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1841 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1842 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1843 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1844 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 1845 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1846 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1847 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1848 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1849 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 1850 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1851 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1852 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1853 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1854 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1855 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1856 // CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 1857 // CHECK1-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 1858 // CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 1859 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1860 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1861 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 1862 // CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 1863 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 1864 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 1865 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1866 // CHECK1: cond.true: 1867 // CHECK1-NEXT: br label [[COND_END:%.*]] 1868 // CHECK1: cond.false: 1869 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 1870 // CHECK1-NEXT: br label [[COND_END]] 1871 // CHECK1: cond.end: 1872 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1873 // CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 1874 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 1875 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 1876 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1877 // CHECK1: omp.inner.for.cond: 1878 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41:![0-9]+]] 1879 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP41]] 1880 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 1881 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1882 // CHECK1: omp.inner.for.body: 1883 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41]] 1884 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 1885 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 1886 // CHECK1-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP41]] 1887 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]] 1888 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 1889 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]] 1890 // CHECK1-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]] 1891 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 1892 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 1893 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 1894 // CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]] 1895 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 1896 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]] 1897 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 1898 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]] 1899 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1900 // CHECK1: omp.body.continue: 1901 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1902 // CHECK1: omp.inner.for.inc: 1903 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41]] 1904 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 1905 // CHECK1-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41]] 1906 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]] 1907 // CHECK1: omp.inner.for.end: 1908 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1909 // CHECK1: omp.loop.exit: 1910 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 1911 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1912 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1913 // CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1914 // CHECK1: .omp.final.then: 1915 // CHECK1-NEXT: store i64 11, ptr [[I]], align 8 1916 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1917 // CHECK1: .omp.final.done: 1918 // CHECK1-NEXT: ret void 1919 // 1920 // 1921 // CHECK3-LABEL: define {{[^@]+}}@_Z7get_valv 1922 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 1923 // CHECK3-NEXT: entry: 1924 // CHECK3-NEXT: ret i64 0 1925 // 1926 // 1927 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 1928 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 1929 // CHECK3-NEXT: entry: 1930 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1931 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 1932 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 1933 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 1934 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 1935 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1936 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 1937 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1938 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 1939 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 1940 // CHECK3-NEXT: [[K:%.*]] = alloca i64, align 8 1941 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1942 // CHECK3-NEXT: [[LIN:%.*]] = alloca i32, align 4 1943 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 1944 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 1945 // CHECK3-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 1946 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 1947 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 1948 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 1949 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1950 // CHECK3-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 1951 // CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 1952 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 4 1953 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 4 1954 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 4 1955 // CHECK3-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 1956 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1957 // CHECK3-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 1958 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 1959 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 4 1960 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 4 1961 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 4 1962 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 1963 // CHECK3-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 1964 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 1965 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1966 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 1967 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 1968 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 1969 // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0() 1970 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 1971 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 1972 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 1973 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 1974 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 1975 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 1976 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 1977 // CHECK3-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, ptr @.omp_task_entry., i64 -1) 1978 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP5]], i32 0, i32 0 1979 // CHECK3-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP5]]) 1980 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 1981 // CHECK3-NEXT: store i64 [[CALL]], ptr [[K]], align 8 1982 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 1983 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 1984 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 1985 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP9]], ptr [[K]]) #[[ATTR3:[0-9]+]] 1986 // CHECK3-NEXT: store i32 12, ptr [[LIN]], align 4 1987 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2 1988 // CHECK3-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2 1989 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4 1990 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[LIN]], align 4 1991 // CHECK3-NEXT: store i32 [[TMP12]], ptr [[LIN_CASTED]], align 4 1992 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 1993 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4 1994 // CHECK3-NEXT: store i32 [[TMP14]], ptr [[A_CASTED2]], align 4 1995 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[A_CASTED2]], align 4 1996 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1997 // CHECK3-NEXT: store i32 [[TMP11]], ptr [[TMP16]], align 4 1998 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1999 // CHECK3-NEXT: store i32 [[TMP11]], ptr [[TMP17]], align 4 2000 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2001 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 2002 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2003 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[TMP19]], align 4 2004 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2005 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[TMP20]], align 4 2006 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2007 // CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 4 2008 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2009 // CHECK3-NEXT: store i32 [[TMP15]], ptr [[TMP22]], align 4 2010 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2011 // CHECK3-NEXT: store i32 [[TMP15]], ptr [[TMP23]], align 4 2012 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2013 // CHECK3-NEXT: store ptr null, ptr [[TMP24]], align 4 2014 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2015 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2016 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2017 // CHECK3-NEXT: store i32 3, ptr [[TMP27]], align 4 2018 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2019 // CHECK3-NEXT: store i32 3, ptr [[TMP28]], align 4 2020 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2021 // CHECK3-NEXT: store ptr [[TMP25]], ptr [[TMP29]], align 4 2022 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2023 // CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP30]], align 4 2024 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2025 // CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP31]], align 4 2026 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2027 // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP32]], align 4 2028 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 2029 // CHECK3-NEXT: store ptr null, ptr [[TMP33]], align 4 2030 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 2031 // CHECK3-NEXT: store ptr null, ptr [[TMP34]], align 4 2032 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 2033 // CHECK3-NEXT: store i64 0, ptr [[TMP35]], align 8 2034 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 2035 // CHECK3-NEXT: store i64 0, ptr [[TMP36]], align 8 2036 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 2037 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP37]], align 4 2038 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 2039 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP38]], align 4 2040 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 2041 // CHECK3-NEXT: store i32 0, ptr [[TMP39]], align 4 2042 // CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, ptr [[KERNEL_ARGS]]) 2043 // CHECK3-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 2044 // CHECK3-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2045 // CHECK3: omp_offload.failed: 2046 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP11]], i32 [[TMP13]], i32 [[TMP15]]) #[[ATTR3]] 2047 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2048 // CHECK3: omp_offload.cont: 2049 // CHECK3-NEXT: [[TMP42:%.*]] = load i32, ptr [[A]], align 4 2050 // CHECK3-NEXT: store i32 [[TMP42]], ptr [[A_CASTED3]], align 4 2051 // CHECK3-NEXT: [[TMP43:%.*]] = load i32, ptr [[A_CASTED3]], align 4 2052 // CHECK3-NEXT: [[TMP44:%.*]] = load i16, ptr [[AA]], align 2 2053 // CHECK3-NEXT: store i16 [[TMP44]], ptr [[AA_CASTED4]], align 2 2054 // CHECK3-NEXT: [[TMP45:%.*]] = load i32, ptr [[AA_CASTED4]], align 4 2055 // CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[N_ADDR]], align 4 2056 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP46]], 10 2057 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2058 // CHECK3: omp_if.then: 2059 // CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 2060 // CHECK3-NEXT: store i32 [[TMP43]], ptr [[TMP47]], align 4 2061 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 2062 // CHECK3-NEXT: store i32 [[TMP43]], ptr [[TMP48]], align 4 2063 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 2064 // CHECK3-NEXT: store ptr null, ptr [[TMP49]], align 4 2065 // CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 2066 // CHECK3-NEXT: store i32 [[TMP45]], ptr [[TMP50]], align 4 2067 // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 2068 // CHECK3-NEXT: store i32 [[TMP45]], ptr [[TMP51]], align 4 2069 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 2070 // CHECK3-NEXT: store ptr null, ptr [[TMP52]], align 4 2071 // CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 2072 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 2073 // CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0 2074 // CHECK3-NEXT: store i32 3, ptr [[TMP55]], align 4 2075 // CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1 2076 // CHECK3-NEXT: store i32 2, ptr [[TMP56]], align 4 2077 // CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2 2078 // CHECK3-NEXT: store ptr [[TMP53]], ptr [[TMP57]], align 4 2079 // CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3 2080 // CHECK3-NEXT: store ptr [[TMP54]], ptr [[TMP58]], align 4 2081 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4 2082 // CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP59]], align 4 2083 // CHECK3-NEXT: [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5 2084 // CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP60]], align 4 2085 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6 2086 // CHECK3-NEXT: store ptr null, ptr [[TMP61]], align 4 2087 // CHECK3-NEXT: [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7 2088 // CHECK3-NEXT: store ptr null, ptr [[TMP62]], align 4 2089 // CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8 2090 // CHECK3-NEXT: store i64 0, ptr [[TMP63]], align 8 2091 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 9 2092 // CHECK3-NEXT: store i64 0, ptr [[TMP64]], align 8 2093 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 10 2094 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP65]], align 4 2095 // CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 11 2096 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP66]], align 4 2097 // CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12 2098 // CHECK3-NEXT: store i32 0, ptr [[TMP67]], align 4 2099 // CHECK3-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, ptr [[KERNEL_ARGS8]]) 2100 // CHECK3-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 2101 // CHECK3-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 2102 // CHECK3: omp_offload.failed9: 2103 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR3]] 2104 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT10]] 2105 // CHECK3: omp_offload.cont10: 2106 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2107 // CHECK3: omp_if.else: 2108 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR3]] 2109 // CHECK3-NEXT: br label [[OMP_IF_END]] 2110 // CHECK3: omp_if.end: 2111 // CHECK3-NEXT: [[TMP70:%.*]] = load i32, ptr [[A]], align 4 2112 // CHECK3-NEXT: store i32 [[TMP70]], ptr [[DOTCAPTURE_EXPR_]], align 4 2113 // CHECK3-NEXT: [[TMP71:%.*]] = load i32, ptr [[A]], align 4 2114 // CHECK3-NEXT: store i32 [[TMP71]], ptr [[A_CASTED11]], align 4 2115 // CHECK3-NEXT: [[TMP72:%.*]] = load i32, ptr [[A_CASTED11]], align 4 2116 // CHECK3-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 2117 // CHECK3-NEXT: store i32 [[TMP73]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 2118 // CHECK3-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 2119 // CHECK3-NEXT: [[TMP75:%.*]] = load i32, ptr [[N_ADDR]], align 4 2120 // CHECK3-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP75]], 20 2121 // CHECK3-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]] 2122 // CHECK3: omp_if.then13: 2123 // CHECK3-NEXT: [[TMP76:%.*]] = mul nuw i32 [[TMP1]], 4 2124 // CHECK3-NEXT: [[TMP77:%.*]] = sext i32 [[TMP76]] to i64 2125 // CHECK3-NEXT: [[TMP78:%.*]] = mul nuw i32 5, [[TMP3]] 2126 // CHECK3-NEXT: [[TMP79:%.*]] = mul nuw i32 [[TMP78]], 8 2127 // CHECK3-NEXT: [[TMP80:%.*]] = sext i32 [[TMP79]] to i64 2128 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.3, i32 80, i1 false) 2129 // CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 2130 // CHECK3-NEXT: store i32 [[TMP72]], ptr [[TMP81]], align 4 2131 // CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 2132 // CHECK3-NEXT: store i32 [[TMP72]], ptr [[TMP82]], align 4 2133 // CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 2134 // CHECK3-NEXT: store ptr null, ptr [[TMP83]], align 4 2135 // CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 2136 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP84]], align 4 2137 // CHECK3-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 2138 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP85]], align 4 2139 // CHECK3-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 2140 // CHECK3-NEXT: store ptr null, ptr [[TMP86]], align 4 2141 // CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 2142 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP87]], align 4 2143 // CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 2144 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP88]], align 4 2145 // CHECK3-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 2146 // CHECK3-NEXT: store ptr null, ptr [[TMP89]], align 4 2147 // CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 2148 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP90]], align 4 2149 // CHECK3-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 2150 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP91]], align 4 2151 // CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 2152 // CHECK3-NEXT: store i64 [[TMP77]], ptr [[TMP92]], align 4 2153 // CHECK3-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 2154 // CHECK3-NEXT: store ptr null, ptr [[TMP93]], align 4 2155 // CHECK3-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 2156 // CHECK3-NEXT: store ptr [[C]], ptr [[TMP94]], align 4 2157 // CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 2158 // CHECK3-NEXT: store ptr [[C]], ptr [[TMP95]], align 4 2159 // CHECK3-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 2160 // CHECK3-NEXT: store ptr null, ptr [[TMP96]], align 4 2161 // CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 2162 // CHECK3-NEXT: store i32 5, ptr [[TMP97]], align 4 2163 // CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 2164 // CHECK3-NEXT: store i32 5, ptr [[TMP98]], align 4 2165 // CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 2166 // CHECK3-NEXT: store ptr null, ptr [[TMP99]], align 4 2167 // CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 2168 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP100]], align 4 2169 // CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 2170 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP101]], align 4 2171 // CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 2172 // CHECK3-NEXT: store ptr null, ptr [[TMP102]], align 4 2173 // CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 2174 // CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP103]], align 4 2175 // CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 2176 // CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP104]], align 4 2177 // CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 2178 // CHECK3-NEXT: store i64 [[TMP80]], ptr [[TMP105]], align 4 2179 // CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 2180 // CHECK3-NEXT: store ptr null, ptr [[TMP106]], align 4 2181 // CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 2182 // CHECK3-NEXT: store ptr [[D]], ptr [[TMP107]], align 4 2183 // CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 2184 // CHECK3-NEXT: store ptr [[D]], ptr [[TMP108]], align 4 2185 // CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 2186 // CHECK3-NEXT: store ptr null, ptr [[TMP109]], align 4 2187 // CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 2188 // CHECK3-NEXT: store i32 [[TMP74]], ptr [[TMP110]], align 4 2189 // CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 2190 // CHECK3-NEXT: store i32 [[TMP74]], ptr [[TMP111]], align 4 2191 // CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 2192 // CHECK3-NEXT: store ptr null, ptr [[TMP112]], align 4 2193 // CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 2194 // CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 2195 // CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2196 // CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0 2197 // CHECK3-NEXT: store i32 3, ptr [[TMP116]], align 4 2198 // CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1 2199 // CHECK3-NEXT: store i32 10, ptr [[TMP117]], align 4 2200 // CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2 2201 // CHECK3-NEXT: store ptr [[TMP113]], ptr [[TMP118]], align 4 2202 // CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3 2203 // CHECK3-NEXT: store ptr [[TMP114]], ptr [[TMP119]], align 4 2204 // CHECK3-NEXT: [[TMP120:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4 2205 // CHECK3-NEXT: store ptr [[TMP115]], ptr [[TMP120]], align 4 2206 // CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5 2207 // CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP121]], align 4 2208 // CHECK3-NEXT: [[TMP122:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6 2209 // CHECK3-NEXT: store ptr null, ptr [[TMP122]], align 4 2210 // CHECK3-NEXT: [[TMP123:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7 2211 // CHECK3-NEXT: store ptr null, ptr [[TMP123]], align 4 2212 // CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8 2213 // CHECK3-NEXT: store i64 0, ptr [[TMP124]], align 8 2214 // CHECK3-NEXT: [[TMP125:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 9 2215 // CHECK3-NEXT: store i64 0, ptr [[TMP125]], align 8 2216 // CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 10 2217 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP126]], align 4 2218 // CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 11 2219 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP127]], align 4 2220 // CHECK3-NEXT: [[TMP128:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12 2221 // CHECK3-NEXT: store i32 0, ptr [[TMP128]], align 4 2222 // CHECK3-NEXT: [[TMP129:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, ptr [[KERNEL_ARGS17]]) 2223 // CHECK3-NEXT: [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 0 2224 // CHECK3-NEXT: br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] 2225 // CHECK3: omp_offload.failed18: 2226 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR3]] 2227 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT19]] 2228 // CHECK3: omp_offload.cont19: 2229 // CHECK3-NEXT: br label [[OMP_IF_END21:%.*]] 2230 // CHECK3: omp_if.else20: 2231 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR3]] 2232 // CHECK3-NEXT: br label [[OMP_IF_END21]] 2233 // CHECK3: omp_if.end21: 2234 // CHECK3-NEXT: [[TMP131:%.*]] = load i32, ptr [[A]], align 4 2235 // CHECK3-NEXT: [[TMP132:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 2236 // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP132]]) 2237 // CHECK3-NEXT: ret i32 [[TMP131]] 2238 // 2239 // 2240 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 2241 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] { 2242 // CHECK3-NEXT: entry: 2243 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) 2244 // CHECK3-NEXT: ret void 2245 // 2246 // 2247 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined 2248 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { 2249 // CHECK3-NEXT: entry: 2250 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2251 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2252 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2253 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2254 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2255 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2256 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2257 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2258 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2259 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2260 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2261 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2262 // CHECK3-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 2263 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2264 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2265 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2266 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2267 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2268 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2269 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 2270 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2271 // CHECK3: cond.true: 2272 // CHECK3-NEXT: br label [[COND_END:%.*]] 2273 // CHECK3: cond.false: 2274 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2275 // CHECK3-NEXT: br label [[COND_END]] 2276 // CHECK3: cond.end: 2277 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2278 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2279 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2280 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2281 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2282 // CHECK3: omp.inner.for.cond: 2283 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 2284 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 2285 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2286 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2287 // CHECK3: omp.inner.for.body: 2288 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 2289 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 2290 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 2291 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 2292 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2293 // CHECK3: omp.body.continue: 2294 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2295 // CHECK3: omp.inner.for.inc: 2296 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 2297 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 2298 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 2299 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 2300 // CHECK3: omp.inner.for.end: 2301 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2302 // CHECK3: omp.loop.exit: 2303 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2304 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2305 // CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 2306 // CHECK3-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2307 // CHECK3: .omp.final.then: 2308 // CHECK3-NEXT: store i32 33, ptr [[I]], align 4 2309 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2310 // CHECK3: .omp.final.done: 2311 // CHECK3-NEXT: ret void 2312 // 2313 // 2314 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 2315 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { 2316 // CHECK3-NEXT: entry: 2317 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 2318 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4 2319 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4 2320 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4 2321 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4 2322 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4 2323 // CHECK3-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2324 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 2325 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 2326 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 2327 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 2328 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 2329 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 2330 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 2331 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 2332 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 2333 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 2334 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 2335 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 2336 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 2337 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) 2338 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META26:![0-9]+]] 2339 // CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias [[META26]] 2340 // CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META26]] 2341 // CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META26]] 2342 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias [[META26]] 2343 // CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META26]] 2344 // CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META26]] 2345 // CHECK3-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META26]] 2346 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 2347 // CHECK3-NEXT: store i32 0, ptr [[TMP9]], align 4, !noalias [[META26]] 2348 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 2349 // CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 4, !noalias [[META26]] 2350 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 2351 // CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4, !noalias [[META26]] 2352 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 2353 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4, !noalias [[META26]] 2354 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 2355 // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4, !noalias [[META26]] 2356 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 2357 // CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4, !noalias [[META26]] 2358 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 2359 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4, !noalias [[META26]] 2360 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 2361 // CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8, !noalias [[META26]] 2362 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9 2363 // CHECK3-NEXT: store i64 1, ptr [[TMP17]], align 8, !noalias [[META26]] 2364 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10 2365 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4, !noalias [[META26]] 2366 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11 2367 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4, !noalias [[META26]] 2368 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12 2369 // CHECK3-NEXT: store i32 0, ptr [[TMP20]], align 4, !noalias [[META26]] 2370 // CHECK3-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, ptr [[KERNEL_ARGS_I]]) 2371 // CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 2372 // CHECK3-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] 2373 // CHECK3: omp_offload.failed.i: 2374 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR3]] 2375 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] 2376 // CHECK3: .omp_outlined..exit: 2377 // CHECK3-NEXT: ret i32 0 2378 // 2379 // 2380 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 2381 // CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { 2382 // CHECK3-NEXT: entry: 2383 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2384 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4 2385 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2386 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2387 // CHECK3-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4 2388 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4 2389 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 2390 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 2391 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 2392 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i32 [[TMP2]], ptr [[TMP0]]) 2393 // CHECK3-NEXT: ret void 2394 // 2395 // 2396 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined 2397 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { 2398 // CHECK3-NEXT: entry: 2399 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2400 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2401 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2402 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4 2403 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2404 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2405 // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 2406 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2407 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2408 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2409 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2410 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2411 // CHECK3-NEXT: [[K1:%.*]] = alloca i64, align 8 2412 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2413 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2414 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2415 // CHECK3-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4 2416 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4 2417 // CHECK3-NEXT: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 8 2418 // CHECK3-NEXT: store i64 [[TMP1]], ptr [[DOTLINEAR_START]], align 8 2419 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2420 // CHECK3-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 4 2421 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2422 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2423 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2424 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 2425 // CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 2426 // CHECK3-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1) 2427 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2428 // CHECK3: omp.dispatch.cond: 2429 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]) 2430 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 2431 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2432 // CHECK3: omp.dispatch.body: 2433 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2434 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 2435 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2436 // CHECK3: omp.inner.for.cond: 2437 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] 2438 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] 2439 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 2440 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2441 // CHECK3: omp.inner.for.body: 2442 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 2443 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 2444 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 2445 // CHECK3-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] 2446 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP27]] 2447 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 2448 // CHECK3-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 2449 // CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 2450 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 2451 // CHECK3-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP27]] 2452 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 2453 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 2454 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 2455 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2456 // CHECK3: omp.body.continue: 2457 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2458 // CHECK3: omp.inner.for.inc: 2459 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 2460 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 2461 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 2462 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 2463 // CHECK3: omp.inner.for.end: 2464 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2465 // CHECK3: omp.dispatch.inc: 2466 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2467 // CHECK3: omp.dispatch.end: 2468 // CHECK3-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP3]]) 2469 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2470 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 2471 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2472 // CHECK3: .omp.final.then: 2473 // CHECK3-NEXT: store i32 1, ptr [[I]], align 4 2474 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2475 // CHECK3: .omp.final.done: 2476 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2477 // CHECK3-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 2478 // CHECK3-NEXT: br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 2479 // CHECK3: .omp.linear.pu: 2480 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, ptr [[K1]], align 8 2481 // CHECK3-NEXT: store i64 [[TMP17]], ptr [[TMP0]], align 8 2482 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 2483 // CHECK3: .omp.linear.pu.done: 2484 // CHECK3-NEXT: ret void 2485 // 2486 // 2487 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 2488 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 2489 // CHECK3-NEXT: entry: 2490 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2491 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 2492 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2493 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2494 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 2495 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2496 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2497 // CHECK3-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 2498 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2499 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2500 // CHECK3-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 2501 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 2502 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 2503 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 2504 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 2505 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 2506 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 2507 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4 2508 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 2509 // CHECK3-NEXT: ret void 2510 // 2511 // 2512 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined 2513 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 2514 // CHECK3-NEXT: entry: 2515 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2516 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2517 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2518 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 2519 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2520 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2521 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 2522 // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 2523 // CHECK3-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 2524 // CHECK3-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 2525 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2526 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2527 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2528 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2529 // CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8 2530 // CHECK3-NEXT: [[LIN2:%.*]] = alloca i32, align 4 2531 // CHECK3-NEXT: [[A3:%.*]] = alloca i32, align 4 2532 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2533 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2534 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2535 // CHECK3-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 2536 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2537 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 2538 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 2539 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 2540 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 2541 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 2542 // CHECK3-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 2543 // CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 2544 // CHECK3-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 2545 // CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 2546 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2547 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2548 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 2549 // CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]]) 2550 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 2551 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 2552 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 2553 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2554 // CHECK3: cond.true: 2555 // CHECK3-NEXT: br label [[COND_END:%.*]] 2556 // CHECK3: cond.false: 2557 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 2558 // CHECK3-NEXT: br label [[COND_END]] 2559 // CHECK3: cond.end: 2560 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2561 // CHECK3-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 2562 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 2563 // CHECK3-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 2564 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2565 // CHECK3: omp.inner.for.cond: 2566 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30:![0-9]+]] 2567 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP30]] 2568 // CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 2569 // CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2570 // CHECK3: omp.inner.for.body: 2571 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2572 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 2573 // CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 2574 // CHECK3-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP30]] 2575 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP30]] 2576 // CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 2577 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2578 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]] 2579 // CHECK3-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 2580 // CHECK3-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 2581 // CHECK3-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 2582 // CHECK3-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP30]] 2583 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP30]] 2584 // CHECK3-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 2585 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2586 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]] 2587 // CHECK3-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 2588 // CHECK3-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 2589 // CHECK3-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 2590 // CHECK3-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP30]] 2591 // CHECK3-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] 2592 // CHECK3-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 2593 // CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 2594 // CHECK3-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 2595 // CHECK3-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] 2596 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2597 // CHECK3: omp.body.continue: 2598 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2599 // CHECK3: omp.inner.for.inc: 2600 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2601 // CHECK3-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 2602 // CHECK3-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2603 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 2604 // CHECK3: omp.inner.for.end: 2605 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2606 // CHECK3: omp.loop.exit: 2607 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 2608 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2609 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 2610 // CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2611 // CHECK3: .omp.final.then: 2612 // CHECK3-NEXT: store i64 400, ptr [[IT]], align 8 2613 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2614 // CHECK3: .omp.final.done: 2615 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2616 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 2617 // CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 2618 // CHECK3: .omp.linear.pu: 2619 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 2620 // CHECK3-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 2621 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 2622 // CHECK3-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 2623 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 2624 // CHECK3: .omp.linear.pu.done: 2625 // CHECK3-NEXT: ret void 2626 // 2627 // 2628 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 2629 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2630 // CHECK3-NEXT: entry: 2631 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2632 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2633 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2634 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2635 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2636 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2637 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2638 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 2639 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 2640 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2641 // CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 2642 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 2643 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) 2644 // CHECK3-NEXT: ret void 2645 // 2646 // 2647 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined 2648 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2649 // CHECK3-NEXT: entry: 2650 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2651 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2652 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2653 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2654 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2655 // CHECK3-NEXT: [[TMP:%.*]] = alloca i16, align 2 2656 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2657 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2658 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2659 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2660 // CHECK3-NEXT: [[IT:%.*]] = alloca i16, align 2 2661 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2662 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2663 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2664 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2665 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2666 // CHECK3-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 2667 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2668 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2669 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2670 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2671 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2672 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2673 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 2674 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2675 // CHECK3: cond.true: 2676 // CHECK3-NEXT: br label [[COND_END:%.*]] 2677 // CHECK3: cond.false: 2678 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2679 // CHECK3-NEXT: br label [[COND_END]] 2680 // CHECK3: cond.end: 2681 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2682 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2683 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2684 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2685 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2686 // CHECK3: omp.inner.for.cond: 2687 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] 2688 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] 2689 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2690 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2691 // CHECK3: omp.inner.for.body: 2692 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 2693 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 2694 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 2695 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 2696 // CHECK3-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP33]] 2697 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 2698 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 2699 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 2700 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] 2701 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 2702 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 2703 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 2704 // CHECK3-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] 2705 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2706 // CHECK3: omp.body.continue: 2707 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2708 // CHECK3: omp.inner.for.inc: 2709 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 2710 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 2711 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 2712 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 2713 // CHECK3: omp.inner.for.end: 2714 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2715 // CHECK3: omp.loop.exit: 2716 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2717 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2718 // CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 2719 // CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2720 // CHECK3: .omp.final.then: 2721 // CHECK3-NEXT: store i16 22, ptr [[IT]], align 2 2722 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2723 // CHECK3: .omp.final.done: 2724 // CHECK3-NEXT: ret void 2725 // 2726 // 2727 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 2728 // CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 2729 // CHECK3-NEXT: entry: 2730 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2731 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 2732 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2733 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 2734 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 2735 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2736 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2737 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 2738 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 2739 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2740 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2741 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 2742 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2743 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 2744 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 2745 // CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 2746 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 2747 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 2748 // CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 2749 // CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 2750 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 2751 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2752 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 2753 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 2754 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 2755 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 2756 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 2757 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 2758 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 2759 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 2760 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 2761 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 2762 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 2763 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2764 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 2765 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 2766 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]]) 2767 // CHECK3-NEXT: ret void 2768 // 2769 // 2770 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined 2771 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 2772 // CHECK3-NEXT: entry: 2773 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2774 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2775 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2776 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 2777 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2778 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 2779 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 2780 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2781 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2782 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 2783 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 2784 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2785 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2786 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 2787 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2788 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2789 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2790 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2791 // CHECK3-NEXT: [[IT:%.*]] = alloca i8, align 1 2792 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2793 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2794 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2795 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 2796 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 2797 // CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 2798 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 2799 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 2800 // CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 2801 // CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 2802 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 2803 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2804 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 2805 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 2806 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 2807 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 2808 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 2809 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 2810 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 2811 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 2812 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2813 // CHECK3-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 2814 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2815 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2816 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2817 // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2818 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 2819 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 2820 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2821 // CHECK3: omp.dispatch.cond: 2822 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2823 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 2824 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2825 // CHECK3: cond.true: 2826 // CHECK3-NEXT: br label [[COND_END:%.*]] 2827 // CHECK3: cond.false: 2828 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2829 // CHECK3-NEXT: br label [[COND_END]] 2830 // CHECK3: cond.end: 2831 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 2832 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2833 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2834 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 2835 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2836 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2837 // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 2838 // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2839 // CHECK3: omp.dispatch.body: 2840 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2841 // CHECK3: omp.inner.for.cond: 2842 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] 2843 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]] 2844 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 2845 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2846 // CHECK3: omp.inner.for.body: 2847 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 2848 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 2849 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 2850 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 2851 // CHECK3-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP36]] 2852 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] 2853 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 2854 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] 2855 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 2856 // CHECK3-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] 2857 // CHECK3-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 2858 // CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 2859 // CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 2860 // CHECK3-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] 2861 // CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 2862 // CHECK3-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]] 2863 // CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 2864 // CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 2865 // CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 2866 // CHECK3-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]] 2867 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 2868 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 2869 // CHECK3-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] 2870 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 2871 // CHECK3-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] 2872 // CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 2873 // CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]] 2874 // CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3 2875 // CHECK3-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]] 2876 // CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 2877 // CHECK3-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]] 2878 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 2879 // CHECK3-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]] 2880 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 2881 // CHECK3-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]] 2882 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 2883 // CHECK3-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]] 2884 // CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 2885 // CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 2886 // CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 2887 // CHECK3-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]] 2888 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2889 // CHECK3: omp.body.continue: 2890 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2891 // CHECK3: omp.inner.for.inc: 2892 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 2893 // CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 2894 // CHECK3-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 2895 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] 2896 // CHECK3: omp.inner.for.end: 2897 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2898 // CHECK3: omp.dispatch.inc: 2899 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2900 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2901 // CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 2902 // CHECK3-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 2903 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2904 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2905 // CHECK3-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 2906 // CHECK3-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 2907 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2908 // CHECK3: omp.dispatch.end: 2909 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 2910 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2911 // CHECK3-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 2912 // CHECK3-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2913 // CHECK3: .omp.final.then: 2914 // CHECK3-NEXT: store i8 96, ptr [[IT]], align 1 2915 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2916 // CHECK3: .omp.final.done: 2917 // CHECK3-NEXT: ret void 2918 // 2919 // 2920 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 2921 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 2922 // CHECK3-NEXT: entry: 2923 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2924 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2925 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 2926 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2927 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 2928 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 2929 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 2930 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 2931 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2932 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A]], align 4 2933 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 2934 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 2935 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 2936 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2937 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 2938 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 2939 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 2940 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 2941 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2942 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 2943 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 2944 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 2945 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 2946 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 2947 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 2948 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 2949 // CHECK3-NEXT: ret i32 [[TMP8]] 2950 // 2951 // 2952 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2953 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2954 // CHECK3-NEXT: entry: 2955 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2956 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2957 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 2958 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 2959 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2960 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2961 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 2962 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 2963 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 2964 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 2965 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2966 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2967 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2968 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2969 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 2970 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2971 // CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4 2972 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 2973 // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0() 2974 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 2975 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 2976 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 2977 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 2978 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 2979 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 2980 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 2981 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 2982 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 2983 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2984 // CHECK3: omp_if.then: 2985 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 2986 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 2987 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 2988 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 2989 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 40, i1 false) 2990 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2991 // CHECK3-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 4 2992 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2993 // CHECK3-NEXT: store ptr [[A]], ptr [[TMP11]], align 4 2994 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2995 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 2996 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2997 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 4 2998 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2999 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 4 3000 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3001 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 3002 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3003 // CHECK3-NEXT: store i32 2, ptr [[TMP16]], align 4 3004 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3005 // CHECK3-NEXT: store i32 2, ptr [[TMP17]], align 4 3006 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3007 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 3008 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3009 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP19]], align 4 3010 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3011 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP20]], align 4 3012 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3013 // CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 4 3014 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3015 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 4 3016 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3017 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 4 3018 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 3019 // CHECK3-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 4 3020 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 3021 // CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4 3022 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3023 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3024 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3025 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3026 // CHECK3-NEXT: store i32 3, ptr [[TMP29]], align 4 3027 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3028 // CHECK3-NEXT: store i32 5, ptr [[TMP30]], align 4 3029 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3030 // CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 4 3031 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3032 // CHECK3-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 4 3033 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3034 // CHECK3-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 4 3035 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3036 // CHECK3-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP34]], align 4 3037 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3038 // CHECK3-NEXT: store ptr null, ptr [[TMP35]], align 4 3039 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3040 // CHECK3-NEXT: store ptr null, ptr [[TMP36]], align 4 3041 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3042 // CHECK3-NEXT: store i64 0, ptr [[TMP37]], align 8 3043 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 3044 // CHECK3-NEXT: store i64 0, ptr [[TMP38]], align 8 3045 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 3046 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 4 3047 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 3048 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4 3049 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 3050 // CHECK3-NEXT: store i32 0, ptr [[TMP41]], align 4 3051 // CHECK3-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, ptr [[KERNEL_ARGS]]) 3052 // CHECK3-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 3053 // CHECK3-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3054 // CHECK3: omp_offload.failed: 3055 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] 3056 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3057 // CHECK3: omp_offload.cont: 3058 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3059 // CHECK3: omp_if.else: 3060 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] 3061 // CHECK3-NEXT: br label [[OMP_IF_END]] 3062 // CHECK3: omp_if.end: 3063 // CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]] 3064 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]] 3065 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 3066 // CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 3067 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 3068 // CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 3069 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] 3070 // CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 3071 // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]]) 3072 // CHECK3-NEXT: ret i32 [[ADD3]] 3073 // 3074 // 3075 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 3076 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 3077 // CHECK3-NEXT: entry: 3078 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3079 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3080 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3081 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 3082 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3083 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3084 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3085 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3086 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 3087 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 3088 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 3089 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3090 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 3091 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 3092 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 3093 // CHECK3-NEXT: store i8 0, ptr [[AAA]], align 1 3094 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 3095 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 3096 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 3097 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 3098 // CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 3099 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3100 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1 3101 // CHECK3-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1 3102 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 3103 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 3104 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 3105 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3106 // CHECK3: omp_if.then: 3107 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3108 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 4 3109 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3110 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 4 3111 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3112 // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 3113 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3114 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP10]], align 4 3115 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3116 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP11]], align 4 3117 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3118 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 3119 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3120 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 4 3121 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3122 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 4 3123 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3124 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 3125 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3126 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP16]], align 4 3127 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3128 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP17]], align 4 3129 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3130 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 3131 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3132 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3133 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3134 // CHECK3-NEXT: store i32 3, ptr [[TMP21]], align 4 3135 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3136 // CHECK3-NEXT: store i32 4, ptr [[TMP22]], align 4 3137 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3138 // CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4 3139 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3140 // CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4 3141 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3142 // CHECK3-NEXT: store ptr @.offload_sizes.7, ptr [[TMP25]], align 4 3143 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3144 // CHECK3-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP26]], align 4 3145 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3146 // CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 4 3147 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3148 // CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 4 3149 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3150 // CHECK3-NEXT: store i64 0, ptr [[TMP29]], align 8 3151 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 3152 // CHECK3-NEXT: store i64 0, ptr [[TMP30]], align 8 3153 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 3154 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4 3155 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 3156 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 3157 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 3158 // CHECK3-NEXT: store i32 0, ptr [[TMP33]], align 4 3159 // CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, ptr [[KERNEL_ARGS]]) 3160 // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 3161 // CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3162 // CHECK3: omp_offload.failed: 3163 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]] 3164 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3165 // CHECK3: omp_offload.cont: 3166 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3167 // CHECK3: omp_if.else: 3168 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]] 3169 // CHECK3-NEXT: br label [[OMP_IF_END]] 3170 // CHECK3: omp_if.end: 3171 // CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 3172 // CHECK3-NEXT: ret i32 [[TMP36]] 3173 // 3174 // 3175 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3176 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 3177 // CHECK3-NEXT: entry: 3178 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3179 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3180 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3181 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3182 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3183 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3184 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 3185 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 3186 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 3187 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3188 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 3189 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 3190 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 3191 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 3192 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 3193 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 3194 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 3195 // CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 3196 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3197 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 3198 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 3199 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3200 // CHECK3: omp_if.then: 3201 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3202 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 3203 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3204 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 4 3205 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3206 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 3207 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3208 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 4 3209 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3210 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP9]], align 4 3211 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3212 // CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 4 3213 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3214 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP11]], align 4 3215 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3216 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP12]], align 4 3217 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3218 // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4 3219 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3220 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3221 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3222 // CHECK3-NEXT: store i32 3, ptr [[TMP16]], align 4 3223 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3224 // CHECK3-NEXT: store i32 3, ptr [[TMP17]], align 4 3225 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3226 // CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4 3227 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3228 // CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 4 3229 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3230 // CHECK3-NEXT: store ptr @.offload_sizes.9, ptr [[TMP20]], align 4 3231 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3232 // CHECK3-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP21]], align 4 3233 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3234 // CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 4 3235 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3236 // CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 4 3237 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3238 // CHECK3-NEXT: store i64 0, ptr [[TMP24]], align 8 3239 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 3240 // CHECK3-NEXT: store i64 0, ptr [[TMP25]], align 8 3241 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 3242 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4 3243 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 3244 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 3245 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 3246 // CHECK3-NEXT: store i32 0, ptr [[TMP28]], align 4 3247 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, ptr [[KERNEL_ARGS]]) 3248 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 3249 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3250 // CHECK3: omp_offload.failed: 3251 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] 3252 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3253 // CHECK3: omp_offload.cont: 3254 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3255 // CHECK3: omp_if.else: 3256 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] 3257 // CHECK3-NEXT: br label [[OMP_IF_END]] 3258 // CHECK3: omp_if.end: 3259 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 3260 // CHECK3-NEXT: ret i32 [[TMP31]] 3261 // 3262 // 3263 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 3264 // CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3265 // CHECK3-NEXT: entry: 3266 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3267 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3268 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3269 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3270 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3271 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3272 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3273 // CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 3274 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 3275 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 3276 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3277 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3278 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 3279 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 3280 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 3281 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 3282 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 3283 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 3284 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]]) 3285 // CHECK3-NEXT: ret void 3286 // 3287 // 3288 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined 3289 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3290 // CHECK3-NEXT: entry: 3291 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3292 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3293 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3294 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3295 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3296 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3297 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3298 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3299 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 3300 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3301 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3302 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3303 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3304 // CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8 3305 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3306 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3307 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3308 // CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 3309 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 3310 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 3311 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3312 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3313 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 3314 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 3315 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 3316 // CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 3317 // CHECK3-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 3318 // CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 3319 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3320 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3321 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 3322 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 3323 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 3324 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 3325 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3326 // CHECK3: cond.true: 3327 // CHECK3-NEXT: br label [[COND_END:%.*]] 3328 // CHECK3: cond.false: 3329 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 3330 // CHECK3-NEXT: br label [[COND_END]] 3331 // CHECK3: cond.end: 3332 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3333 // CHECK3-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 3334 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 3335 // CHECK3-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8 3336 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3337 // CHECK3: omp.inner.for.cond: 3338 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39:![0-9]+]] 3339 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP39]] 3340 // CHECK3-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 3341 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3342 // CHECK3: omp.inner.for.body: 3343 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 3344 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 3345 // CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 3346 // CHECK3-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP39]] 3347 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]] 3348 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 3349 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3350 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 3351 // CHECK3-NEXT: store double [[ADD]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP39]] 3352 // CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 3353 // CHECK3-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP39]] 3354 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 3355 // CHECK3-NEXT: store double [[INC]], ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP39]] 3356 // CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 3357 // CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 3358 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]] 3359 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 3360 // CHECK3-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP39]] 3361 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3362 // CHECK3: omp.body.continue: 3363 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3364 // CHECK3: omp.inner.for.inc: 3365 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 3366 // CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 3367 // CHECK3-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 3368 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] 3369 // CHECK3: omp.inner.for.end: 3370 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3371 // CHECK3: omp.loop.exit: 3372 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 3373 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3374 // CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 3375 // CHECK3-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3376 // CHECK3: .omp.final.then: 3377 // CHECK3-NEXT: store i64 400, ptr [[IT]], align 8 3378 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 3379 // CHECK3: .omp.final.done: 3380 // CHECK3-NEXT: ret void 3381 // 3382 // 3383 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 3384 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3385 // CHECK3-NEXT: entry: 3386 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3387 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3388 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3389 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3390 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3391 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3392 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3393 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3394 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3395 // CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 3396 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3397 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3398 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 3399 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 3400 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 3401 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3402 // CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 3403 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3404 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 3405 // CHECK3-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 3406 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 3407 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]]) 3408 // CHECK3-NEXT: ret void 3409 // 3410 // 3411 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined 3412 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3413 // CHECK3-NEXT: entry: 3414 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3415 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3416 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3417 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3418 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3419 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3420 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3421 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3422 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3423 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3424 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3425 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3426 // CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 3427 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3428 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3429 // CHECK3-NEXT: ret void 3430 // 3431 // 3432 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 3433 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3434 // CHECK3-NEXT: entry: 3435 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3436 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3437 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3438 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3439 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3440 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3441 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3442 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3443 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3444 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 3445 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 3446 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 3447 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3448 // CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 3449 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3450 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) 3451 // CHECK3-NEXT: ret void 3452 // 3453 // 3454 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined 3455 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3456 // CHECK3-NEXT: entry: 3457 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3458 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3459 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3460 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3461 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3462 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3463 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 3464 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3465 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3466 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3467 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3468 // CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 3469 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3470 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3471 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3472 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3473 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3474 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3475 // CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 3476 // CHECK3-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 3477 // CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 3478 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3479 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3480 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 3481 // CHECK3-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 3482 // CHECK3-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 3483 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 3484 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3485 // CHECK3: cond.true: 3486 // CHECK3-NEXT: br label [[COND_END:%.*]] 3487 // CHECK3: cond.false: 3488 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 3489 // CHECK3-NEXT: br label [[COND_END]] 3490 // CHECK3: cond.end: 3491 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 3492 // CHECK3-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 3493 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 3494 // CHECK3-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 3495 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3496 // CHECK3: omp.inner.for.cond: 3497 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42:![0-9]+]] 3498 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP42]] 3499 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 3500 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3501 // CHECK3: omp.inner.for.body: 3502 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42]] 3503 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 3504 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 3505 // CHECK3-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP42]] 3506 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]] 3507 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 3508 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]] 3509 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]] 3510 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 3511 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 3512 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 3513 // CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]] 3514 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 3515 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]] 3516 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 3517 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]] 3518 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3519 // CHECK3: omp.body.continue: 3520 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3521 // CHECK3: omp.inner.for.inc: 3522 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42]] 3523 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 3524 // CHECK3-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42]] 3525 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] 3526 // CHECK3: omp.inner.for.end: 3527 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3528 // CHECK3: omp.loop.exit: 3529 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 3530 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3531 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 3532 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3533 // CHECK3: .omp.final.then: 3534 // CHECK3-NEXT: store i64 11, ptr [[I]], align 8 3535 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 3536 // CHECK3: .omp.final.done: 3537 // CHECK3-NEXT: ret void 3538 // 3539 // 3540 // CHECK5-LABEL: define {{[^@]+}}@_Z7get_valv 3541 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 3542 // CHECK5-NEXT: entry: 3543 // CHECK5-NEXT: ret i64 0 3544 // 3545 // 3546 // CHECK5-LABEL: define {{[^@]+}}@_Z3fooi 3547 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 3548 // CHECK5-NEXT: entry: 3549 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3550 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 3551 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 3552 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x float], align 4 3553 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 3554 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3555 // CHECK5-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 3556 // CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 3557 // CHECK5-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 3558 // CHECK5-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 3559 // CHECK5-NEXT: [[K:%.*]] = alloca i64, align 8 3560 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3561 // CHECK5-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 3562 // CHECK5-NEXT: [[LIN:%.*]] = alloca i32, align 4 3563 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3564 // CHECK5-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 3565 // CHECK5-NEXT: [[A_CASTED2:%.*]] = alloca i64, align 8 3566 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 3567 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 3568 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 3569 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3570 // CHECK5-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 3571 // CHECK5-NEXT: [[AA_CASTED4:%.*]] = alloca i64, align 8 3572 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 8 3573 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 8 3574 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 8 3575 // CHECK5-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 3576 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3577 // CHECK5-NEXT: [[A_CASTED11:%.*]] = alloca i64, align 8 3578 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 3579 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 8 3580 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 8 3581 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 8 3582 // CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 3583 // CHECK5-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 3584 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 3585 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 3586 // CHECK5-NEXT: store i32 0, ptr [[A]], align 4 3587 // CHECK5-NEXT: store i16 0, ptr [[AA]], align 2 3588 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 3589 // CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 3590 // CHECK5-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0() 3591 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 3592 // CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 3593 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 3594 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 3595 // CHECK5-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 3596 // CHECK5-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 3597 // CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 3598 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 3599 // CHECK5-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, ptr @.omp_task_entry., i64 -1) 3600 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP7]], i32 0, i32 0 3601 // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP7]]) 3602 // CHECK5-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 3603 // CHECK5-NEXT: store i64 [[CALL]], ptr [[K]], align 8 3604 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4 3605 // CHECK5-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4 3606 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8 3607 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[K]], align 8 3608 // CHECK5-NEXT: store i64 [[TMP12]], ptr [[K_CASTED]], align 8 3609 // CHECK5-NEXT: [[TMP13:%.*]] = load i64, ptr [[K_CASTED]], align 8 3610 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR3:[0-9]+]] 3611 // CHECK5-NEXT: store i32 12, ptr [[LIN]], align 4 3612 // CHECK5-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2 3613 // CHECK5-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2 3614 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[AA_CASTED]], align 8 3615 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[LIN]], align 4 3616 // CHECK5-NEXT: store i32 [[TMP16]], ptr [[LIN_CASTED]], align 4 3617 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 3618 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[A]], align 4 3619 // CHECK5-NEXT: store i32 [[TMP18]], ptr [[A_CASTED2]], align 4 3620 // CHECK5-NEXT: [[TMP19:%.*]] = load i64, ptr [[A_CASTED2]], align 8 3621 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3622 // CHECK5-NEXT: store i64 [[TMP15]], ptr [[TMP20]], align 8 3623 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3624 // CHECK5-NEXT: store i64 [[TMP15]], ptr [[TMP21]], align 8 3625 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3626 // CHECK5-NEXT: store ptr null, ptr [[TMP22]], align 8 3627 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3628 // CHECK5-NEXT: store i64 [[TMP17]], ptr [[TMP23]], align 8 3629 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3630 // CHECK5-NEXT: store i64 [[TMP17]], ptr [[TMP24]], align 8 3631 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3632 // CHECK5-NEXT: store ptr null, ptr [[TMP25]], align 8 3633 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3634 // CHECK5-NEXT: store i64 [[TMP19]], ptr [[TMP26]], align 8 3635 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3636 // CHECK5-NEXT: store i64 [[TMP19]], ptr [[TMP27]], align 8 3637 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3638 // CHECK5-NEXT: store ptr null, ptr [[TMP28]], align 8 3639 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3640 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3641 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3642 // CHECK5-NEXT: store i32 3, ptr [[TMP31]], align 4 3643 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3644 // CHECK5-NEXT: store i32 3, ptr [[TMP32]], align 4 3645 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3646 // CHECK5-NEXT: store ptr [[TMP29]], ptr [[TMP33]], align 8 3647 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3648 // CHECK5-NEXT: store ptr [[TMP30]], ptr [[TMP34]], align 8 3649 // CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3650 // CHECK5-NEXT: store ptr @.offload_sizes, ptr [[TMP35]], align 8 3651 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3652 // CHECK5-NEXT: store ptr @.offload_maptypes, ptr [[TMP36]], align 8 3653 // CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3654 // CHECK5-NEXT: store ptr null, ptr [[TMP37]], align 8 3655 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3656 // CHECK5-NEXT: store ptr null, ptr [[TMP38]], align 8 3657 // CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3658 // CHECK5-NEXT: store i64 0, ptr [[TMP39]], align 8 3659 // CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 3660 // CHECK5-NEXT: store i64 0, ptr [[TMP40]], align 8 3661 // CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 3662 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP41]], align 4 3663 // CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 3664 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP42]], align 4 3665 // CHECK5-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 3666 // CHECK5-NEXT: store i32 0, ptr [[TMP43]], align 4 3667 // CHECK5-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, ptr [[KERNEL_ARGS]]) 3668 // CHECK5-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 3669 // CHECK5-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3670 // CHECK5: omp_offload.failed: 3671 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]]) #[[ATTR3]] 3672 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 3673 // CHECK5: omp_offload.cont: 3674 // CHECK5-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 3675 // CHECK5-NEXT: store i32 [[TMP46]], ptr [[A_CASTED3]], align 4 3676 // CHECK5-NEXT: [[TMP47:%.*]] = load i64, ptr [[A_CASTED3]], align 8 3677 // CHECK5-NEXT: [[TMP48:%.*]] = load i16, ptr [[AA]], align 2 3678 // CHECK5-NEXT: store i16 [[TMP48]], ptr [[AA_CASTED4]], align 2 3679 // CHECK5-NEXT: [[TMP49:%.*]] = load i64, ptr [[AA_CASTED4]], align 8 3680 // CHECK5-NEXT: [[TMP50:%.*]] = load i32, ptr [[N_ADDR]], align 4 3681 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP50]], 10 3682 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3683 // CHECK5: omp_if.then: 3684 // CHECK5-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 3685 // CHECK5-NEXT: store i64 [[TMP47]], ptr [[TMP51]], align 8 3686 // CHECK5-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 3687 // CHECK5-NEXT: store i64 [[TMP47]], ptr [[TMP52]], align 8 3688 // CHECK5-NEXT: [[TMP53:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 3689 // CHECK5-NEXT: store ptr null, ptr [[TMP53]], align 8 3690 // CHECK5-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 3691 // CHECK5-NEXT: store i64 [[TMP49]], ptr [[TMP54]], align 8 3692 // CHECK5-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 3693 // CHECK5-NEXT: store i64 [[TMP49]], ptr [[TMP55]], align 8 3694 // CHECK5-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 3695 // CHECK5-NEXT: store ptr null, ptr [[TMP56]], align 8 3696 // CHECK5-NEXT: [[TMP57:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 3697 // CHECK5-NEXT: [[TMP58:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 3698 // CHECK5-NEXT: [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0 3699 // CHECK5-NEXT: store i32 3, ptr [[TMP59]], align 4 3700 // CHECK5-NEXT: [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1 3701 // CHECK5-NEXT: store i32 2, ptr [[TMP60]], align 4 3702 // CHECK5-NEXT: [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2 3703 // CHECK5-NEXT: store ptr [[TMP57]], ptr [[TMP61]], align 8 3704 // CHECK5-NEXT: [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3 3705 // CHECK5-NEXT: store ptr [[TMP58]], ptr [[TMP62]], align 8 3706 // CHECK5-NEXT: [[TMP63:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4 3707 // CHECK5-NEXT: store ptr @.offload_sizes.1, ptr [[TMP63]], align 8 3708 // CHECK5-NEXT: [[TMP64:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5 3709 // CHECK5-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP64]], align 8 3710 // CHECK5-NEXT: [[TMP65:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6 3711 // CHECK5-NEXT: store ptr null, ptr [[TMP65]], align 8 3712 // CHECK5-NEXT: [[TMP66:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7 3713 // CHECK5-NEXT: store ptr null, ptr [[TMP66]], align 8 3714 // CHECK5-NEXT: [[TMP67:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8 3715 // CHECK5-NEXT: store i64 0, ptr [[TMP67]], align 8 3716 // CHECK5-NEXT: [[TMP68:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 9 3717 // CHECK5-NEXT: store i64 0, ptr [[TMP68]], align 8 3718 // CHECK5-NEXT: [[TMP69:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 10 3719 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP69]], align 4 3720 // CHECK5-NEXT: [[TMP70:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 11 3721 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP70]], align 4 3722 // CHECK5-NEXT: [[TMP71:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12 3723 // CHECK5-NEXT: store i32 0, ptr [[TMP71]], align 4 3724 // CHECK5-NEXT: [[TMP72:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, ptr [[KERNEL_ARGS8]]) 3725 // CHECK5-NEXT: [[TMP73:%.*]] = icmp ne i32 [[TMP72]], 0 3726 // CHECK5-NEXT: br i1 [[TMP73]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 3727 // CHECK5: omp_offload.failed9: 3728 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR3]] 3729 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT10]] 3730 // CHECK5: omp_offload.cont10: 3731 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 3732 // CHECK5: omp_if.else: 3733 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR3]] 3734 // CHECK5-NEXT: br label [[OMP_IF_END]] 3735 // CHECK5: omp_if.end: 3736 // CHECK5-NEXT: [[TMP74:%.*]] = load i32, ptr [[A]], align 4 3737 // CHECK5-NEXT: store i32 [[TMP74]], ptr [[DOTCAPTURE_EXPR_]], align 4 3738 // CHECK5-NEXT: [[TMP75:%.*]] = load i32, ptr [[A]], align 4 3739 // CHECK5-NEXT: store i32 [[TMP75]], ptr [[A_CASTED11]], align 4 3740 // CHECK5-NEXT: [[TMP76:%.*]] = load i64, ptr [[A_CASTED11]], align 8 3741 // CHECK5-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 3742 // CHECK5-NEXT: store i32 [[TMP77]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 3743 // CHECK5-NEXT: [[TMP78:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 3744 // CHECK5-NEXT: [[TMP79:%.*]] = load i32, ptr [[N_ADDR]], align 4 3745 // CHECK5-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP79]], 20 3746 // CHECK5-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]] 3747 // CHECK5: omp_if.then13: 3748 // CHECK5-NEXT: [[TMP80:%.*]] = mul nuw i64 [[TMP2]], 4 3749 // CHECK5-NEXT: [[TMP81:%.*]] = mul nuw i64 5, [[TMP5]] 3750 // CHECK5-NEXT: [[TMP82:%.*]] = mul nuw i64 [[TMP81]], 8 3751 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.3, i64 80, i1 false) 3752 // CHECK5-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 3753 // CHECK5-NEXT: store i64 [[TMP76]], ptr [[TMP83]], align 8 3754 // CHECK5-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 3755 // CHECK5-NEXT: store i64 [[TMP76]], ptr [[TMP84]], align 8 3756 // CHECK5-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0 3757 // CHECK5-NEXT: store ptr null, ptr [[TMP85]], align 8 3758 // CHECK5-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 3759 // CHECK5-NEXT: store ptr [[B]], ptr [[TMP86]], align 8 3760 // CHECK5-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 3761 // CHECK5-NEXT: store ptr [[B]], ptr [[TMP87]], align 8 3762 // CHECK5-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1 3763 // CHECK5-NEXT: store ptr null, ptr [[TMP88]], align 8 3764 // CHECK5-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 3765 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP89]], align 8 3766 // CHECK5-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 3767 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP90]], align 8 3768 // CHECK5-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 2 3769 // CHECK5-NEXT: store ptr null, ptr [[TMP91]], align 8 3770 // CHECK5-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 3771 // CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP92]], align 8 3772 // CHECK5-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 3773 // CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP93]], align 8 3774 // CHECK5-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 3775 // CHECK5-NEXT: store i64 [[TMP80]], ptr [[TMP94]], align 8 3776 // CHECK5-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 3 3777 // CHECK5-NEXT: store ptr null, ptr [[TMP95]], align 8 3778 // CHECK5-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 3779 // CHECK5-NEXT: store ptr [[C]], ptr [[TMP96]], align 8 3780 // CHECK5-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 3781 // CHECK5-NEXT: store ptr [[C]], ptr [[TMP97]], align 8 3782 // CHECK5-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 4 3783 // CHECK5-NEXT: store ptr null, ptr [[TMP98]], align 8 3784 // CHECK5-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 3785 // CHECK5-NEXT: store i64 5, ptr [[TMP99]], align 8 3786 // CHECK5-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 3787 // CHECK5-NEXT: store i64 5, ptr [[TMP100]], align 8 3788 // CHECK5-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 5 3789 // CHECK5-NEXT: store ptr null, ptr [[TMP101]], align 8 3790 // CHECK5-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 3791 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP102]], align 8 3792 // CHECK5-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 3793 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP103]], align 8 3794 // CHECK5-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 6 3795 // CHECK5-NEXT: store ptr null, ptr [[TMP104]], align 8 3796 // CHECK5-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 3797 // CHECK5-NEXT: store ptr [[VLA1]], ptr [[TMP105]], align 8 3798 // CHECK5-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 3799 // CHECK5-NEXT: store ptr [[VLA1]], ptr [[TMP106]], align 8 3800 // CHECK5-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 3801 // CHECK5-NEXT: store i64 [[TMP82]], ptr [[TMP107]], align 8 3802 // CHECK5-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 7 3803 // CHECK5-NEXT: store ptr null, ptr [[TMP108]], align 8 3804 // CHECK5-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 3805 // CHECK5-NEXT: store ptr [[D]], ptr [[TMP109]], align 8 3806 // CHECK5-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 3807 // CHECK5-NEXT: store ptr [[D]], ptr [[TMP110]], align 8 3808 // CHECK5-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 8 3809 // CHECK5-NEXT: store ptr null, ptr [[TMP111]], align 8 3810 // CHECK5-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 3811 // CHECK5-NEXT: store i64 [[TMP78]], ptr [[TMP112]], align 8 3812 // CHECK5-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 3813 // CHECK5-NEXT: store i64 [[TMP78]], ptr [[TMP113]], align 8 3814 // CHECK5-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 9 3815 // CHECK5-NEXT: store ptr null, ptr [[TMP114]], align 8 3816 // CHECK5-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 3817 // CHECK5-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 3818 // CHECK5-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3819 // CHECK5-NEXT: [[TMP118:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0 3820 // CHECK5-NEXT: store i32 3, ptr [[TMP118]], align 4 3821 // CHECK5-NEXT: [[TMP119:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1 3822 // CHECK5-NEXT: store i32 10, ptr [[TMP119]], align 4 3823 // CHECK5-NEXT: [[TMP120:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2 3824 // CHECK5-NEXT: store ptr [[TMP115]], ptr [[TMP120]], align 8 3825 // CHECK5-NEXT: [[TMP121:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3 3826 // CHECK5-NEXT: store ptr [[TMP116]], ptr [[TMP121]], align 8 3827 // CHECK5-NEXT: [[TMP122:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4 3828 // CHECK5-NEXT: store ptr [[TMP117]], ptr [[TMP122]], align 8 3829 // CHECK5-NEXT: [[TMP123:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5 3830 // CHECK5-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP123]], align 8 3831 // CHECK5-NEXT: [[TMP124:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6 3832 // CHECK5-NEXT: store ptr null, ptr [[TMP124]], align 8 3833 // CHECK5-NEXT: [[TMP125:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7 3834 // CHECK5-NEXT: store ptr null, ptr [[TMP125]], align 8 3835 // CHECK5-NEXT: [[TMP126:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8 3836 // CHECK5-NEXT: store i64 0, ptr [[TMP126]], align 8 3837 // CHECK5-NEXT: [[TMP127:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 9 3838 // CHECK5-NEXT: store i64 0, ptr [[TMP127]], align 8 3839 // CHECK5-NEXT: [[TMP128:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 10 3840 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP128]], align 4 3841 // CHECK5-NEXT: [[TMP129:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 11 3842 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP129]], align 4 3843 // CHECK5-NEXT: [[TMP130:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12 3844 // CHECK5-NEXT: store i32 0, ptr [[TMP130]], align 4 3845 // CHECK5-NEXT: [[TMP131:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, ptr [[KERNEL_ARGS17]]) 3846 // CHECK5-NEXT: [[TMP132:%.*]] = icmp ne i32 [[TMP131]], 0 3847 // CHECK5-NEXT: br i1 [[TMP132]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] 3848 // CHECK5: omp_offload.failed18: 3849 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR3]] 3850 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT19]] 3851 // CHECK5: omp_offload.cont19: 3852 // CHECK5-NEXT: br label [[OMP_IF_END21:%.*]] 3853 // CHECK5: omp_if.else20: 3854 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR3]] 3855 // CHECK5-NEXT: br label [[OMP_IF_END21]] 3856 // CHECK5: omp_if.end21: 3857 // CHECK5-NEXT: [[TMP133:%.*]] = load i32, ptr [[A]], align 4 3858 // CHECK5-NEXT: [[TMP134:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 3859 // CHECK5-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP134]]) 3860 // CHECK5-NEXT: ret i32 [[TMP133]] 3861 // 3862 // 3863 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 3864 // CHECK5-SAME: () #[[ATTR2:[0-9]+]] { 3865 // CHECK5-NEXT: entry: 3866 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) 3867 // CHECK5-NEXT: ret void 3868 // 3869 // 3870 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined 3871 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { 3872 // CHECK5-NEXT: entry: 3873 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3874 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3875 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3876 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 3877 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3878 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3879 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3880 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3881 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3882 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3883 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3884 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3885 // CHECK5-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 3886 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3887 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3888 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3889 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 3890 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3891 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3892 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 3893 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3894 // CHECK5: cond.true: 3895 // CHECK5-NEXT: br label [[COND_END:%.*]] 3896 // CHECK5: cond.false: 3897 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3898 // CHECK5-NEXT: br label [[COND_END]] 3899 // CHECK5: cond.end: 3900 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3901 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3902 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3903 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 3904 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3905 // CHECK5: omp.inner.for.cond: 3906 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 3907 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 3908 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3909 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3910 // CHECK5: omp.inner.for.body: 3911 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 3912 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 3913 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 3914 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 3915 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3916 // CHECK5: omp.body.continue: 3917 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3918 // CHECK5: omp.inner.for.inc: 3919 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 3920 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 3921 // CHECK5-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 3922 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 3923 // CHECK5: omp.inner.for.end: 3924 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3925 // CHECK5: omp.loop.exit: 3926 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 3927 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3928 // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 3929 // CHECK5-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3930 // CHECK5: .omp.final.then: 3931 // CHECK5-NEXT: store i32 33, ptr [[I]], align 4 3932 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 3933 // CHECK5: .omp.final.done: 3934 // CHECK5-NEXT: ret void 3935 // 3936 // 3937 // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry. 3938 // CHECK5-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { 3939 // CHECK5-NEXT: entry: 3940 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 3941 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 3942 // CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 3943 // CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 3944 // CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 3945 // CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 3946 // CHECK5-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3947 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 3948 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 3949 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 3950 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 3951 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 3952 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 3953 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 3954 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 3955 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 3956 // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 3957 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 3958 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 3959 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 3960 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 3961 // CHECK5-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META25:![0-9]+]] 3962 // CHECK5-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META25]] 3963 // CHECK5-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META25]] 3964 // CHECK5-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META25]] 3965 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META25]] 3966 // CHECK5-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META25]] 3967 // CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META25]] 3968 // CHECK5-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META25]] 3969 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 3970 // CHECK5-NEXT: store i32 0, ptr [[TMP9]], align 4, !noalias [[META25]] 3971 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 3972 // CHECK5-NEXT: store ptr null, ptr [[TMP10]], align 8, !noalias [[META25]] 3973 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 3974 // CHECK5-NEXT: store ptr null, ptr [[TMP11]], align 8, !noalias [[META25]] 3975 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 3976 // CHECK5-NEXT: store ptr null, ptr [[TMP12]], align 8, !noalias [[META25]] 3977 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 3978 // CHECK5-NEXT: store ptr null, ptr [[TMP13]], align 8, !noalias [[META25]] 3979 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 3980 // CHECK5-NEXT: store ptr null, ptr [[TMP14]], align 8, !noalias [[META25]] 3981 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 3982 // CHECK5-NEXT: store ptr null, ptr [[TMP15]], align 8, !noalias [[META25]] 3983 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 3984 // CHECK5-NEXT: store i64 0, ptr [[TMP16]], align 8, !noalias [[META25]] 3985 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9 3986 // CHECK5-NEXT: store i64 1, ptr [[TMP17]], align 8, !noalias [[META25]] 3987 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10 3988 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4, !noalias [[META25]] 3989 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11 3990 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4, !noalias [[META25]] 3991 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12 3992 // CHECK5-NEXT: store i32 0, ptr [[TMP20]], align 4, !noalias [[META25]] 3993 // CHECK5-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, ptr [[KERNEL_ARGS_I]]) 3994 // CHECK5-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 3995 // CHECK5-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] 3996 // CHECK5: omp_offload.failed.i: 3997 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR3]] 3998 // CHECK5-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] 3999 // CHECK5: .omp_outlined..exit: 4000 // CHECK5-NEXT: ret i32 0 4001 // 4002 // 4003 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 4004 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] { 4005 // CHECK5-NEXT: entry: 4006 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4007 // CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 4008 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4009 // CHECK5-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 4010 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4011 // CHECK5-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8 4012 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4013 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 4014 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 4015 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[K_ADDR]], align 8 4016 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[K_CASTED]], align 8 4017 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[K_CASTED]], align 8 4018 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) 4019 // CHECK5-NEXT: ret void 4020 // 4021 // 4022 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined 4023 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] { 4024 // CHECK5-NEXT: entry: 4025 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4026 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4027 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4028 // CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 4029 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4030 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 4031 // CHECK5-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 4032 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4033 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4034 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4035 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4036 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 4037 // CHECK5-NEXT: [[K1:%.*]] = alloca i64, align 8 4038 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4039 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4040 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4041 // CHECK5-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8 4042 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[K_ADDR]], align 8 4043 // CHECK5-NEXT: store i64 [[TMP0]], ptr [[DOTLINEAR_START]], align 8 4044 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4045 // CHECK5-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 4 4046 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4047 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4048 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4049 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 4050 // CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 4051 // CHECK5-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 4052 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4053 // CHECK5: omp.dispatch.cond: 4054 // CHECK5-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP2]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]) 4055 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 4056 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4057 // CHECK5: omp.dispatch.body: 4058 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4059 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 4060 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4061 // CHECK5: omp.inner.for.cond: 4062 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] 4063 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] 4064 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4065 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4066 // CHECK5: omp.inner.for.body: 4067 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 4068 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4069 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 4070 // CHECK5-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] 4071 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP26]] 4072 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 4073 // CHECK5-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 4074 // CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 4075 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV]] 4076 // CHECK5-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP26]] 4077 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] 4078 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 4079 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] 4080 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4081 // CHECK5: omp.body.continue: 4082 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4083 // CHECK5: omp.inner.for.inc: 4084 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 4085 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 4086 // CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 4087 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] 4088 // CHECK5: omp.inner.for.end: 4089 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4090 // CHECK5: omp.dispatch.inc: 4091 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] 4092 // CHECK5: omp.dispatch.end: 4093 // CHECK5-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP2]]) 4094 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4095 // CHECK5-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 4096 // CHECK5-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4097 // CHECK5: .omp.final.then: 4098 // CHECK5-NEXT: store i32 1, ptr [[I]], align 4 4099 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4100 // CHECK5: .omp.final.done: 4101 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4102 // CHECK5-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 4103 // CHECK5-NEXT: br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 4104 // CHECK5: .omp.linear.pu: 4105 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[K1]], align 8 4106 // CHECK5-NEXT: store i64 [[TMP16]], ptr [[K_ADDR]], align 8 4107 // CHECK5-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 4108 // CHECK5: .omp.linear.pu.done: 4109 // CHECK5-NEXT: ret void 4110 // 4111 // 4112 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 4113 // CHECK5-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 4114 // CHECK5-NEXT: entry: 4115 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4116 // CHECK5-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 4117 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4118 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4119 // CHECK5-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 4120 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4121 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4122 // CHECK5-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 4123 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4124 // CHECK5-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4125 // CHECK5-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 4126 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 4127 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 4128 // CHECK5-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 4129 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 4130 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 4131 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 4132 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8 4133 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 4134 // CHECK5-NEXT: ret void 4135 // 4136 // 4137 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined 4138 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 4139 // CHECK5-NEXT: entry: 4140 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4141 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4142 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4143 // CHECK5-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 4144 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4145 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4146 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 4147 // CHECK5-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 4148 // CHECK5-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 4149 // CHECK5-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 4150 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4151 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4152 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4153 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4154 // CHECK5-NEXT: [[IT:%.*]] = alloca i64, align 8 4155 // CHECK5-NEXT: [[LIN2:%.*]] = alloca i32, align 4 4156 // CHECK5-NEXT: [[A3:%.*]] = alloca i32, align 4 4157 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4158 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4159 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4160 // CHECK5-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 4161 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4162 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 4163 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 4164 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 4165 // CHECK5-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 4166 // CHECK5-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 4167 // CHECK5-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 4168 // CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 4169 // CHECK5-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 4170 // CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 4171 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4172 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4173 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 4174 // CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]]) 4175 // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 4176 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 4177 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 4178 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4179 // CHECK5: cond.true: 4180 // CHECK5-NEXT: br label [[COND_END:%.*]] 4181 // CHECK5: cond.false: 4182 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 4183 // CHECK5-NEXT: br label [[COND_END]] 4184 // CHECK5: cond.end: 4185 // CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 4186 // CHECK5-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 4187 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 4188 // CHECK5-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 4189 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4190 // CHECK5: omp.inner.for.cond: 4191 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29:![0-9]+]] 4192 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP29]] 4193 // CHECK5-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 4194 // CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4195 // CHECK5: omp.inner.for.body: 4196 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4197 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 4198 // CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 4199 // CHECK5-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP29]] 4200 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP29]] 4201 // CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 4202 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4203 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]] 4204 // CHECK5-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 4205 // CHECK5-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 4206 // CHECK5-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 4207 // CHECK5-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP29]] 4208 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP29]] 4209 // CHECK5-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 4210 // CHECK5-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4211 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]] 4212 // CHECK5-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 4213 // CHECK5-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 4214 // CHECK5-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 4215 // CHECK5-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP29]] 4216 // CHECK5-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] 4217 // CHECK5-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 4218 // CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 4219 // CHECK5-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 4220 // CHECK5-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] 4221 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4222 // CHECK5: omp.body.continue: 4223 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4224 // CHECK5: omp.inner.for.inc: 4225 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4226 // CHECK5-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 4227 // CHECK5-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4228 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] 4229 // CHECK5: omp.inner.for.end: 4230 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4231 // CHECK5: omp.loop.exit: 4232 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 4233 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4234 // CHECK5-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 4235 // CHECK5-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4236 // CHECK5: .omp.final.then: 4237 // CHECK5-NEXT: store i64 400, ptr [[IT]], align 8 4238 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4239 // CHECK5: .omp.final.done: 4240 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4241 // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 4242 // CHECK5-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 4243 // CHECK5: .omp.linear.pu: 4244 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 4245 // CHECK5-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 4246 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 4247 // CHECK5-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 4248 // CHECK5-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 4249 // CHECK5: .omp.linear.pu.done: 4250 // CHECK5-NEXT: ret void 4251 // 4252 // 4253 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 4254 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 4255 // CHECK5-NEXT: entry: 4256 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4257 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4258 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4259 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4260 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4261 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4262 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4263 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 4264 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 4265 // CHECK5-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4266 // CHECK5-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 4267 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 4268 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) 4269 // CHECK5-NEXT: ret void 4270 // 4271 // 4272 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined 4273 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 4274 // CHECK5-NEXT: entry: 4275 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4276 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4277 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4278 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4279 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4280 // CHECK5-NEXT: [[TMP:%.*]] = alloca i16, align 2 4281 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4282 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4283 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4284 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4285 // CHECK5-NEXT: [[IT:%.*]] = alloca i16, align 2 4286 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4287 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4288 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4289 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4290 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4291 // CHECK5-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 4292 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4293 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4294 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4295 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 4296 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 4297 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4298 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 4299 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4300 // CHECK5: cond.true: 4301 // CHECK5-NEXT: br label [[COND_END:%.*]] 4302 // CHECK5: cond.false: 4303 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4304 // CHECK5-NEXT: br label [[COND_END]] 4305 // CHECK5: cond.end: 4306 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4307 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4308 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4309 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 4310 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4311 // CHECK5: omp.inner.for.cond: 4312 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]] 4313 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]] 4314 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4315 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4316 // CHECK5: omp.inner.for.body: 4317 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 4318 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 4319 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 4320 // CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 4321 // CHECK5-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP32]] 4322 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] 4323 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 4324 // CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] 4325 // CHECK5-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] 4326 // CHECK5-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 4327 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 4328 // CHECK5-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 4329 // CHECK5-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] 4330 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4331 // CHECK5: omp.body.continue: 4332 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4333 // CHECK5: omp.inner.for.inc: 4334 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 4335 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 4336 // CHECK5-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 4337 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] 4338 // CHECK5: omp.inner.for.end: 4339 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4340 // CHECK5: omp.loop.exit: 4341 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 4342 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4343 // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 4344 // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4345 // CHECK5: .omp.final.then: 4346 // CHECK5-NEXT: store i16 22, ptr [[IT]], align 2 4347 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4348 // CHECK5: .omp.final.done: 4349 // CHECK5-NEXT: ret void 4350 // 4351 // 4352 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 4353 // CHECK5-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 4354 // CHECK5-NEXT: entry: 4355 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4356 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4357 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4358 // CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 4359 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4360 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4361 // CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4362 // CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 4363 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 4364 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4365 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4366 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4367 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4368 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4369 // CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4370 // CHECK5-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 4371 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4372 // CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 4373 // CHECK5-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 4374 // CHECK5-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 4375 // CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 4376 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 4377 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 4378 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4379 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 4380 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4381 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 4382 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 4383 // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 4384 // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 4385 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 4386 // CHECK5-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 4387 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 4388 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 4389 // CHECK5-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 4390 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 4391 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]]) 4392 // CHECK5-NEXT: ret void 4393 // 4394 // 4395 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined 4396 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 4397 // CHECK5-NEXT: entry: 4398 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4399 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4400 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4401 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4402 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4403 // CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 4404 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4405 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4406 // CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4407 // CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 4408 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 4409 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4410 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4411 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1 4412 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4413 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4414 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4415 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4416 // CHECK5-NEXT: [[IT:%.*]] = alloca i8, align 1 4417 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4418 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4419 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4420 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4421 // CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4422 // CHECK5-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 4423 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4424 // CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 4425 // CHECK5-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 4426 // CHECK5-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 4427 // CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 4428 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 4429 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 4430 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4431 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 4432 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4433 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 4434 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 4435 // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 4436 // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 4437 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4438 // CHECK5-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 4439 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4440 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4441 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 4442 // CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4443 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 4444 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 4445 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4446 // CHECK5: omp.dispatch.cond: 4447 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4448 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 4449 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4450 // CHECK5: cond.true: 4451 // CHECK5-NEXT: br label [[COND_END:%.*]] 4452 // CHECK5: cond.false: 4453 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4454 // CHECK5-NEXT: br label [[COND_END]] 4455 // CHECK5: cond.end: 4456 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 4457 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4458 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4459 // CHECK5-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 4460 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4461 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4462 // CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 4463 // CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4464 // CHECK5: omp.dispatch.body: 4465 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4466 // CHECK5: omp.inner.for.cond: 4467 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]] 4468 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]] 4469 // CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 4470 // CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4471 // CHECK5: omp.inner.for.body: 4472 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 4473 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 4474 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 4475 // CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 4476 // CHECK5-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP35]] 4477 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] 4478 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 4479 // CHECK5-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] 4480 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 4481 // CHECK5-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] 4482 // CHECK5-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 4483 // CHECK5-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 4484 // CHECK5-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 4485 // CHECK5-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] 4486 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 4487 // CHECK5-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP35]] 4488 // CHECK5-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 4489 // CHECK5-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 4490 // CHECK5-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 4491 // CHECK5-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP35]] 4492 // CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 4493 // CHECK5-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 4494 // CHECK5-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]] 4495 // CHECK5-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 4496 // CHECK5-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]] 4497 // CHECK5-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 4498 // CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]] 4499 // CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3 4500 // CHECK5-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP35]] 4501 // CHECK5-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 4502 // CHECK5-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP35]] 4503 // CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 4504 // CHECK5-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]] 4505 // CHECK5-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 4506 // CHECK5-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]] 4507 // CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 4508 // CHECK5-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]] 4509 // CHECK5-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 4510 // CHECK5-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 4511 // CHECK5-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 4512 // CHECK5-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]] 4513 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4514 // CHECK5: omp.body.continue: 4515 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4516 // CHECK5: omp.inner.for.inc: 4517 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 4518 // CHECK5-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 4519 // CHECK5-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 4520 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] 4521 // CHECK5: omp.inner.for.end: 4522 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4523 // CHECK5: omp.dispatch.inc: 4524 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4525 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 4526 // CHECK5-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 4527 // CHECK5-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 4528 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4529 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 4530 // CHECK5-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 4531 // CHECK5-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 4532 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] 4533 // CHECK5: omp.dispatch.end: 4534 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 4535 // CHECK5-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4536 // CHECK5-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 4537 // CHECK5-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4538 // CHECK5: .omp.final.then: 4539 // CHECK5-NEXT: store i8 96, ptr [[IT]], align 1 4540 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4541 // CHECK5: .omp.final.done: 4542 // CHECK5-NEXT: ret void 4543 // 4544 // 4545 // CHECK5-LABEL: define {{[^@]+}}@_Z3bari 4546 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 4547 // CHECK5-NEXT: entry: 4548 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4549 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 4550 // CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 4551 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 4552 // CHECK5-NEXT: store i32 0, ptr [[A]], align 4 4553 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 4554 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 4555 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 4556 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 4557 // CHECK5-NEXT: store i32 [[ADD]], ptr [[A]], align 4 4558 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 4559 // CHECK5-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 4560 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 4561 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 4562 // CHECK5-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 4563 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 4564 // CHECK5-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 4565 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 4566 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 4567 // CHECK5-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 4568 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 4569 // CHECK5-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 4570 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 4571 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 4572 // CHECK5-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 4573 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 4574 // CHECK5-NEXT: ret i32 [[TMP8]] 4575 // 4576 // 4577 // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 4578 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 4579 // CHECK5-NEXT: entry: 4580 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4581 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4582 // CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 4583 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 4584 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4585 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4586 // CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4587 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4588 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x ptr], align 8 4589 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x ptr], align 8 4590 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x ptr], align 8 4591 // CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 8 4592 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 4593 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4594 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 4595 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4596 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 4597 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4598 // CHECK5-NEXT: store i32 [[ADD]], ptr [[B]], align 4 4599 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 4600 // CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 4601 // CHECK5-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0() 4602 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 4603 // CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 4604 // CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 4605 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 4606 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 4607 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 4608 // CHECK5-NEXT: [[STOREDV:%.*]] = zext i1 [[CMP]] to i8 4609 // CHECK5-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1 4610 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[B]], align 4 4611 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[B_CASTED]], align 4 4612 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[B_CASTED]], align 8 4613 // CHECK5-NEXT: [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4614 // CHECK5-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP8]] to i1 4615 // CHECK5-NEXT: [[STOREDV2:%.*]] = zext i1 [[LOADEDV]] to i8 4616 // CHECK5-NEXT: store i8 [[STOREDV2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 4617 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 4618 // CHECK5-NEXT: [[TMP10:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4619 // CHECK5-NEXT: [[LOADEDV3:%.*]] = trunc i8 [[TMP10]] to i1 4620 // CHECK5-NEXT: br i1 [[LOADEDV3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4621 // CHECK5: omp_if.then: 4622 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 4623 // CHECK5-NEXT: [[TMP11:%.*]] = mul nuw i64 2, [[TMP2]] 4624 // CHECK5-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 2 4625 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 48, i1 false) 4626 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4627 // CHECK5-NEXT: store ptr [[THIS1]], ptr [[TMP13]], align 8 4628 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4629 // CHECK5-NEXT: store ptr [[A]], ptr [[TMP14]], align 8 4630 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4631 // CHECK5-NEXT: store ptr null, ptr [[TMP15]], align 8 4632 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4633 // CHECK5-NEXT: store i64 [[TMP7]], ptr [[TMP16]], align 8 4634 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4635 // CHECK5-NEXT: store i64 [[TMP7]], ptr [[TMP17]], align 8 4636 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4637 // CHECK5-NEXT: store ptr null, ptr [[TMP18]], align 8 4638 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4639 // CHECK5-NEXT: store i64 2, ptr [[TMP19]], align 8 4640 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4641 // CHECK5-NEXT: store i64 2, ptr [[TMP20]], align 8 4642 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4643 // CHECK5-NEXT: store ptr null, ptr [[TMP21]], align 8 4644 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4645 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP22]], align 8 4646 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4647 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP23]], align 8 4648 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 4649 // CHECK5-NEXT: store ptr null, ptr [[TMP24]], align 8 4650 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 4651 // CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP25]], align 8 4652 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 4653 // CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP26]], align 8 4654 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 4655 // CHECK5-NEXT: store i64 [[TMP12]], ptr [[TMP27]], align 8 4656 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 4657 // CHECK5-NEXT: store ptr null, ptr [[TMP28]], align 8 4658 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 4659 // CHECK5-NEXT: store i64 [[TMP9]], ptr [[TMP29]], align 8 4660 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5 4661 // CHECK5-NEXT: store i64 [[TMP9]], ptr [[TMP30]], align 8 4662 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 4663 // CHECK5-NEXT: store ptr null, ptr [[TMP31]], align 8 4664 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4665 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4666 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4667 // CHECK5-NEXT: [[TMP35:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4668 // CHECK5-NEXT: [[LOADEDV4:%.*]] = trunc i8 [[TMP35]] to i1 4669 // CHECK5-NEXT: [[TMP36:%.*]] = select i1 [[LOADEDV4]], i32 0, i32 1 4670 // CHECK5-NEXT: [[TMP37:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP36]], 0 4671 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 4672 // CHECK5-NEXT: store i32 3, ptr [[TMP38]], align 4 4673 // CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 4674 // CHECK5-NEXT: store i32 6, ptr [[TMP39]], align 4 4675 // CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 4676 // CHECK5-NEXT: store ptr [[TMP32]], ptr [[TMP40]], align 8 4677 // CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 4678 // CHECK5-NEXT: store ptr [[TMP33]], ptr [[TMP41]], align 8 4679 // CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 4680 // CHECK5-NEXT: store ptr [[TMP34]], ptr [[TMP42]], align 8 4681 // CHECK5-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 4682 // CHECK5-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP43]], align 8 4683 // CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 4684 // CHECK5-NEXT: store ptr null, ptr [[TMP44]], align 8 4685 // CHECK5-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 4686 // CHECK5-NEXT: store ptr null, ptr [[TMP45]], align 8 4687 // CHECK5-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 4688 // CHECK5-NEXT: store i64 0, ptr [[TMP46]], align 8 4689 // CHECK5-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 4690 // CHECK5-NEXT: store i64 0, ptr [[TMP47]], align 8 4691 // CHECK5-NEXT: [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 4692 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP48]], align 4 4693 // CHECK5-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 4694 // CHECK5-NEXT: store [3 x i32] [[TMP37]], ptr [[TMP49]], align 4 4695 // CHECK5-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 4696 // CHECK5-NEXT: store i32 0, ptr [[TMP50]], align 4 4697 // CHECK5-NEXT: [[TMP51:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 [[TMP36]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, ptr [[KERNEL_ARGS]]) 4698 // CHECK5-NEXT: [[TMP52:%.*]] = icmp ne i32 [[TMP51]], 0 4699 // CHECK5-NEXT: br i1 [[TMP52]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4700 // CHECK5: omp_offload.failed: 4701 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR3]] 4702 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 4703 // CHECK5: omp_offload.cont: 4704 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4705 // CHECK5: omp_if.else: 4706 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR3]] 4707 // CHECK5-NEXT: br label [[OMP_IF_END]] 4708 // CHECK5: omp_if.end: 4709 // CHECK5-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP2]] 4710 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP53]] 4711 // CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 4712 // CHECK5-NEXT: [[TMP54:%.*]] = load i16, ptr [[ARRAYIDX5]], align 2 4713 // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP54]] to i32 4714 // CHECK5-NEXT: [[TMP55:%.*]] = load i32, ptr [[B]], align 4 4715 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV]], [[TMP55]] 4716 // CHECK5-NEXT: [[TMP56:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 4717 // CHECK5-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP56]]) 4718 // CHECK5-NEXT: ret i32 [[ADD6]] 4719 // 4720 // 4721 // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici 4722 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 4723 // CHECK5-NEXT: entry: 4724 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4725 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 4726 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 4727 // CHECK5-NEXT: [[AAA:%.*]] = alloca i8, align 1 4728 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4729 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4730 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4731 // CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 4732 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 4733 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 4734 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 4735 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 4736 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 4737 // CHECK5-NEXT: store i32 0, ptr [[A]], align 4 4738 // CHECK5-NEXT: store i16 0, ptr [[AA]], align 2 4739 // CHECK5-NEXT: store i8 0, ptr [[AAA]], align 1 4740 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 4741 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 4742 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 4743 // CHECK5-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 4744 // CHECK5-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 4745 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 4746 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1 4747 // CHECK5-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1 4748 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 4749 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 4750 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 4751 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4752 // CHECK5: omp_if.then: 4753 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4754 // CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP7]], align 8 4755 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4756 // CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP8]], align 8 4757 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4758 // CHECK5-NEXT: store ptr null, ptr [[TMP9]], align 8 4759 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4760 // CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP10]], align 8 4761 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4762 // CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP11]], align 8 4763 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4764 // CHECK5-NEXT: store ptr null, ptr [[TMP12]], align 8 4765 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4766 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP13]], align 8 4767 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4768 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP14]], align 8 4769 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4770 // CHECK5-NEXT: store ptr null, ptr [[TMP15]], align 8 4771 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4772 // CHECK5-NEXT: store ptr [[B]], ptr [[TMP16]], align 8 4773 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4774 // CHECK5-NEXT: store ptr [[B]], ptr [[TMP17]], align 8 4775 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 4776 // CHECK5-NEXT: store ptr null, ptr [[TMP18]], align 8 4777 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4778 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4779 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 4780 // CHECK5-NEXT: store i32 3, ptr [[TMP21]], align 4 4781 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 4782 // CHECK5-NEXT: store i32 4, ptr [[TMP22]], align 4 4783 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 4784 // CHECK5-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8 4785 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 4786 // CHECK5-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8 4787 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 4788 // CHECK5-NEXT: store ptr @.offload_sizes.7, ptr [[TMP25]], align 8 4789 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 4790 // CHECK5-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP26]], align 8 4791 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 4792 // CHECK5-NEXT: store ptr null, ptr [[TMP27]], align 8 4793 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 4794 // CHECK5-NEXT: store ptr null, ptr [[TMP28]], align 8 4795 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 4796 // CHECK5-NEXT: store i64 0, ptr [[TMP29]], align 8 4797 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 4798 // CHECK5-NEXT: store i64 0, ptr [[TMP30]], align 8 4799 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 4800 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4 4801 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 4802 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 4803 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 4804 // CHECK5-NEXT: store i32 0, ptr [[TMP33]], align 4 4805 // CHECK5-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, ptr [[KERNEL_ARGS]]) 4806 // CHECK5-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 4807 // CHECK5-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4808 // CHECK5: omp_offload.failed: 4809 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]] 4810 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 4811 // CHECK5: omp_offload.cont: 4812 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4813 // CHECK5: omp_if.else: 4814 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]] 4815 // CHECK5-NEXT: br label [[OMP_IF_END]] 4816 // CHECK5: omp_if.end: 4817 // CHECK5-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 4818 // CHECK5-NEXT: ret i32 [[TMP36]] 4819 // 4820 // 4821 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 4822 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 4823 // CHECK5-NEXT: entry: 4824 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4825 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 4826 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 4827 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4828 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4829 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4830 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 4831 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 4832 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 4833 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 4834 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 4835 // CHECK5-NEXT: store i32 0, ptr [[A]], align 4 4836 // CHECK5-NEXT: store i16 0, ptr [[AA]], align 2 4837 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 4838 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 4839 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 4840 // CHECK5-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 4841 // CHECK5-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 4842 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 4843 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 4844 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 4845 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4846 // CHECK5: omp_if.then: 4847 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4848 // CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 4849 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4850 // CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 8 4851 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4852 // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 4853 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4854 // CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 8 4855 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4856 // CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP9]], align 8 4857 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4858 // CHECK5-NEXT: store ptr null, ptr [[TMP10]], align 8 4859 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4860 // CHECK5-NEXT: store ptr [[B]], ptr [[TMP11]], align 8 4861 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4862 // CHECK5-NEXT: store ptr [[B]], ptr [[TMP12]], align 8 4863 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4864 // CHECK5-NEXT: store ptr null, ptr [[TMP13]], align 8 4865 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4866 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4867 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 4868 // CHECK5-NEXT: store i32 3, ptr [[TMP16]], align 4 4869 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 4870 // CHECK5-NEXT: store i32 3, ptr [[TMP17]], align 4 4871 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 4872 // CHECK5-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8 4873 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 4874 // CHECK5-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8 4875 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 4876 // CHECK5-NEXT: store ptr @.offload_sizes.9, ptr [[TMP20]], align 8 4877 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 4878 // CHECK5-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP21]], align 8 4879 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 4880 // CHECK5-NEXT: store ptr null, ptr [[TMP22]], align 8 4881 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 4882 // CHECK5-NEXT: store ptr null, ptr [[TMP23]], align 8 4883 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 4884 // CHECK5-NEXT: store i64 0, ptr [[TMP24]], align 8 4885 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 4886 // CHECK5-NEXT: store i64 0, ptr [[TMP25]], align 8 4887 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 4888 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4 4889 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 4890 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 4891 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 4892 // CHECK5-NEXT: store i32 0, ptr [[TMP28]], align 4 4893 // CHECK5-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, ptr [[KERNEL_ARGS]]) 4894 // CHECK5-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 4895 // CHECK5-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4896 // CHECK5: omp_offload.failed: 4897 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] 4898 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 4899 // CHECK5: omp_offload.cont: 4900 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4901 // CHECK5: omp_if.else: 4902 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] 4903 // CHECK5-NEXT: br label [[OMP_IF_END]] 4904 // CHECK5: omp_if.end: 4905 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 4906 // CHECK5-NEXT: ret i32 [[TMP31]] 4907 // 4908 // 4909 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 4910 // CHECK5-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 4911 // CHECK5-NEXT: entry: 4912 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4913 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4914 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4915 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4916 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4917 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4918 // CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4919 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4920 // CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 4921 // CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 4922 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 4923 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4924 // CHECK5-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 4925 // CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4926 // CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 4927 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4928 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 4929 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4930 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4931 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 4932 // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4933 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4 4934 // CHECK5-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 4935 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 4936 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 4937 // CHECK5-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i1 4938 // CHECK5-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8 4939 // CHECK5-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 4940 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 4941 // CHECK5-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 4942 // CHECK5-NEXT: [[LOADEDV3:%.*]] = trunc i8 [[TMP9]] to i1 4943 // CHECK5-NEXT: br i1 [[LOADEDV3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4944 // CHECK5: omp_if.then: 4945 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) 4946 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4947 // CHECK5: omp_if.else: 4948 // CHECK5-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 4949 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 4950 // CHECK5-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 4951 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) #[[ATTR3]] 4952 // CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 4953 // CHECK5-NEXT: br label [[OMP_IF_END]] 4954 // CHECK5: omp_if.end: 4955 // CHECK5-NEXT: ret void 4956 // 4957 // 4958 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined 4959 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 4960 // CHECK5-NEXT: entry: 4961 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4962 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4963 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4964 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4965 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4966 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4967 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4968 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4969 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4970 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 4971 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4972 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4973 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4974 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4975 // CHECK5-NEXT: [[IT:%.*]] = alloca i64, align 8 4976 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4977 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4978 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4979 // CHECK5-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 4980 // CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4981 // CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 4982 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4983 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 4984 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4985 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4986 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 4987 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4988 // CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 4989 // CHECK5-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 4990 // CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 4991 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4992 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 4993 // CHECK5-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP4]] to i1 4994 // CHECK5-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4995 // CHECK5: omp_if.then: 4996 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4997 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 4998 // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 4999 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5000 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 5001 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5002 // CHECK5: cond.true: 5003 // CHECK5-NEXT: br label [[COND_END:%.*]] 5004 // CHECK5: cond.false: 5005 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5006 // CHECK5-NEXT: br label [[COND_END]] 5007 // CHECK5: cond.end: 5008 // CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 5009 // CHECK5-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 5010 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 5011 // CHECK5-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV]], align 8 5012 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5013 // CHECK5: omp.inner.for.cond: 5014 // CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38:![0-9]+]] 5015 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP38]] 5016 // CHECK5-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 5017 // CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5018 // CHECK5: omp.inner.for.body: 5019 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 5020 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 5021 // CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 5022 // CHECK5-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP38]] 5023 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]] 5024 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double 5025 // CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 5026 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 5027 // CHECK5-NEXT: store double [[ADD]], ptr [[A]], align 8, !nontemporal [[META39:![0-9]+]], !llvm.access.group [[ACC_GRP38]] 5028 // CHECK5-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 5029 // CHECK5-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 8, !nontemporal [[META39]], !llvm.access.group [[ACC_GRP38]] 5030 // CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 5031 // CHECK5-NEXT: store double [[INC]], ptr [[A4]], align 8, !nontemporal [[META39]], !llvm.access.group [[ACC_GRP38]] 5032 // CHECK5-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 5033 // CHECK5-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]] 5034 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP15]] 5035 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 5036 // CHECK5-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP38]] 5037 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5038 // CHECK5: omp.body.continue: 5039 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5040 // CHECK5: omp.inner.for.inc: 5041 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 5042 // CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1 5043 // CHECK5-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 5044 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] 5045 // CHECK5: omp.inner.for.end: 5046 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 5047 // CHECK5: omp_if.else: 5048 // CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 5049 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 5050 // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP18]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 5051 // CHECK5-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5052 // CHECK5-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[TMP19]], 3 5053 // CHECK5-NEXT: br i1 [[CMP8]], label [[COND_TRUE9:%.*]], label [[COND_FALSE10:%.*]] 5054 // CHECK5: cond.true9: 5055 // CHECK5-NEXT: br label [[COND_END11:%.*]] 5056 // CHECK5: cond.false10: 5057 // CHECK5-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5058 // CHECK5-NEXT: br label [[COND_END11]] 5059 // CHECK5: cond.end11: 5060 // CHECK5-NEXT: [[COND12:%.*]] = phi i64 [ 3, [[COND_TRUE9]] ], [ [[TMP20]], [[COND_FALSE10]] ] 5061 // CHECK5-NEXT: store i64 [[COND12]], ptr [[DOTOMP_UB]], align 8 5062 // CHECK5-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 5063 // CHECK5-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV]], align 8 5064 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 5065 // CHECK5: omp.inner.for.cond13: 5066 // CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 5067 // CHECK5-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5068 // CHECK5-NEXT: [[CMP14:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 5069 // CHECK5-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END29:%.*]] 5070 // CHECK5: omp.inner.for.body15: 5071 // CHECK5-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 5072 // CHECK5-NEXT: [[MUL16:%.*]] = mul i64 [[TMP24]], 400 5073 // CHECK5-NEXT: [[SUB17:%.*]] = sub i64 2000, [[MUL16]] 5074 // CHECK5-NEXT: store i64 [[SUB17]], ptr [[IT]], align 8 5075 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[B_ADDR]], align 4 5076 // CHECK5-NEXT: [[CONV18:%.*]] = sitofp i32 [[TMP25]] to double 5077 // CHECK5-NEXT: [[ADD19:%.*]] = fadd double [[CONV18]], 1.500000e+00 5078 // CHECK5-NEXT: [[A20:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 5079 // CHECK5-NEXT: store double [[ADD19]], ptr [[A20]], align 8 5080 // CHECK5-NEXT: [[A21:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 5081 // CHECK5-NEXT: [[TMP26:%.*]] = load double, ptr [[A21]], align 8 5082 // CHECK5-NEXT: [[INC22:%.*]] = fadd double [[TMP26]], 1.000000e+00 5083 // CHECK5-NEXT: store double [[INC22]], ptr [[A21]], align 8 5084 // CHECK5-NEXT: [[CONV23:%.*]] = fptosi double [[INC22]] to i16 5085 // CHECK5-NEXT: [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]] 5086 // CHECK5-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP27]] 5087 // CHECK5-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX24]], i64 1 5088 // CHECK5-NEXT: store i16 [[CONV23]], ptr [[ARRAYIDX25]], align 2 5089 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] 5090 // CHECK5: omp.body.continue26: 5091 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] 5092 // CHECK5: omp.inner.for.inc27: 5093 // CHECK5-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 5094 // CHECK5-NEXT: [[ADD28:%.*]] = add i64 [[TMP28]], 1 5095 // CHECK5-NEXT: store i64 [[ADD28]], ptr [[DOTOMP_IV]], align 8 5096 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP42:![0-9]+]] 5097 // CHECK5: omp.inner.for.end29: 5098 // CHECK5-NEXT: br label [[OMP_IF_END]] 5099 // CHECK5: omp_if.end: 5100 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5101 // CHECK5: omp.loop.exit: 5102 // CHECK5-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 5103 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4 5104 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]]) 5105 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5106 // CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 5107 // CHECK5-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5108 // CHECK5: .omp.final.then: 5109 // CHECK5-NEXT: store i64 400, ptr [[IT]], align 8 5110 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 5111 // CHECK5: .omp.final.done: 5112 // CHECK5-NEXT: ret void 5113 // 5114 // 5115 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 5116 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5117 // CHECK5-NEXT: entry: 5118 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5119 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5120 // CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 5121 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 5122 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5123 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 5124 // CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 5125 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 5126 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 5127 // CHECK5-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 5128 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 5129 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 5130 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 5131 // CHECK5-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 5132 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 5133 // CHECK5-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 5134 // CHECK5-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 5135 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 5136 // CHECK5-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 5137 // CHECK5-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 5138 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 5139 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]]) 5140 // CHECK5-NEXT: ret void 5141 // 5142 // 5143 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined 5144 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5145 // CHECK5-NEXT: entry: 5146 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 5147 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 5148 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5149 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5150 // CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 5151 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 5152 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5153 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 5154 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 5155 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 5156 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 5157 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 5158 // CHECK5-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 5159 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 5160 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 5161 // CHECK5-NEXT: ret void 5162 // 5163 // 5164 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 5165 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5166 // CHECK5-NEXT: entry: 5167 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5168 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5169 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 5170 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5171 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 5172 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 5173 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 5174 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 5175 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 5176 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 5177 // CHECK5-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 5178 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 5179 // CHECK5-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 5180 // CHECK5-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 5181 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 5182 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) 5183 // CHECK5-NEXT: ret void 5184 // 5185 // 5186 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined 5187 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5188 // CHECK5-NEXT: entry: 5189 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 5190 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 5191 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5192 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5193 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 5194 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5195 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 5196 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5197 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5198 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5199 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5200 // CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8 5201 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 5202 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 5203 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 5204 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 5205 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 5206 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 5207 // CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 5208 // CHECK5-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 5209 // CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 5210 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5211 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 5212 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 5213 // CHECK5-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 5214 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5215 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 5216 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5217 // CHECK5: cond.true: 5218 // CHECK5-NEXT: br label [[COND_END:%.*]] 5219 // CHECK5: cond.false: 5220 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5221 // CHECK5-NEXT: br label [[COND_END]] 5222 // CHECK5: cond.end: 5223 // CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 5224 // CHECK5-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 5225 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 5226 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 5227 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5228 // CHECK5: omp.inner.for.cond: 5229 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44:![0-9]+]] 5230 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP44]] 5231 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 5232 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5233 // CHECK5: omp.inner.for.body: 5234 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44]] 5235 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 5236 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 5237 // CHECK5-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP44]] 5238 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]] 5239 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 5240 // CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]] 5241 // CHECK5-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]] 5242 // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 5243 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 5244 // CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 5245 // CHECK5-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]] 5246 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 5247 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] 5248 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 5249 // CHECK5-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] 5250 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5251 // CHECK5: omp.body.continue: 5252 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5253 // CHECK5: omp.inner.for.inc: 5254 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44]] 5255 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 5256 // CHECK5-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44]] 5257 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]] 5258 // CHECK5: omp.inner.for.end: 5259 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5260 // CHECK5: omp.loop.exit: 5261 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 5262 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5263 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 5264 // CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5265 // CHECK5: .omp.final.then: 5266 // CHECK5-NEXT: store i64 11, ptr [[I]], align 8 5267 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 5268 // CHECK5: .omp.final.done: 5269 // CHECK5-NEXT: ret void 5270 // 5271 // 5272 // CHECK7-LABEL: define {{[^@]+}}@_Z7get_valv 5273 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 5274 // CHECK7-NEXT: entry: 5275 // CHECK7-NEXT: ret i64 0 5276 // 5277 // 5278 // CHECK7-LABEL: define {{[^@]+}}@_Z3fooi 5279 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 5280 // CHECK7-NEXT: entry: 5281 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5282 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 5283 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 5284 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x float], align 4 5285 // CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 5286 // CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 5287 // CHECK7-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 5288 // CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 5289 // CHECK7-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 5290 // CHECK7-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 5291 // CHECK7-NEXT: [[K:%.*]] = alloca i64, align 8 5292 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5293 // CHECK7-NEXT: [[LIN:%.*]] = alloca i32, align 4 5294 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5295 // CHECK7-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 5296 // CHECK7-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 5297 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 5298 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 5299 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 5300 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 5301 // CHECK7-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 5302 // CHECK7-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 5303 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 4 5304 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 4 5305 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 4 5306 // CHECK7-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 5307 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5308 // CHECK7-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 5309 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 5310 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 4 5311 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 4 5312 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 4 5313 // CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 5314 // CHECK7-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 5315 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 5316 // CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 5317 // CHECK7-NEXT: store i32 0, ptr [[A]], align 4 5318 // CHECK7-NEXT: store i16 0, ptr [[AA]], align 2 5319 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 5320 // CHECK7-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0() 5321 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 5322 // CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 5323 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 5324 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 5325 // CHECK7-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 5326 // CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 5327 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 5328 // CHECK7-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, ptr @.omp_task_entry., i64 -1) 5329 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP5]], i32 0, i32 0 5330 // CHECK7-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP5]]) 5331 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 5332 // CHECK7-NEXT: store i64 [[CALL]], ptr [[K]], align 8 5333 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 5334 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 5335 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 5336 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP9]], ptr [[K]]) #[[ATTR3:[0-9]+]] 5337 // CHECK7-NEXT: store i32 12, ptr [[LIN]], align 4 5338 // CHECK7-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2 5339 // CHECK7-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2 5340 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4 5341 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[LIN]], align 4 5342 // CHECK7-NEXT: store i32 [[TMP12]], ptr [[LIN_CASTED]], align 4 5343 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 5344 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4 5345 // CHECK7-NEXT: store i32 [[TMP14]], ptr [[A_CASTED2]], align 4 5346 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[A_CASTED2]], align 4 5347 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5348 // CHECK7-NEXT: store i32 [[TMP11]], ptr [[TMP16]], align 4 5349 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5350 // CHECK7-NEXT: store i32 [[TMP11]], ptr [[TMP17]], align 4 5351 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5352 // CHECK7-NEXT: store ptr null, ptr [[TMP18]], align 4 5353 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5354 // CHECK7-NEXT: store i32 [[TMP13]], ptr [[TMP19]], align 4 5355 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5356 // CHECK7-NEXT: store i32 [[TMP13]], ptr [[TMP20]], align 4 5357 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5358 // CHECK7-NEXT: store ptr null, ptr [[TMP21]], align 4 5359 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5360 // CHECK7-NEXT: store i32 [[TMP15]], ptr [[TMP22]], align 4 5361 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5362 // CHECK7-NEXT: store i32 [[TMP15]], ptr [[TMP23]], align 4 5363 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5364 // CHECK7-NEXT: store ptr null, ptr [[TMP24]], align 4 5365 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5366 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5367 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 5368 // CHECK7-NEXT: store i32 3, ptr [[TMP27]], align 4 5369 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 5370 // CHECK7-NEXT: store i32 3, ptr [[TMP28]], align 4 5371 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 5372 // CHECK7-NEXT: store ptr [[TMP25]], ptr [[TMP29]], align 4 5373 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 5374 // CHECK7-NEXT: store ptr [[TMP26]], ptr [[TMP30]], align 4 5375 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 5376 // CHECK7-NEXT: store ptr @.offload_sizes, ptr [[TMP31]], align 4 5377 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 5378 // CHECK7-NEXT: store ptr @.offload_maptypes, ptr [[TMP32]], align 4 5379 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 5380 // CHECK7-NEXT: store ptr null, ptr [[TMP33]], align 4 5381 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 5382 // CHECK7-NEXT: store ptr null, ptr [[TMP34]], align 4 5383 // CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 5384 // CHECK7-NEXT: store i64 0, ptr [[TMP35]], align 8 5385 // CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 5386 // CHECK7-NEXT: store i64 0, ptr [[TMP36]], align 8 5387 // CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 5388 // CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP37]], align 4 5389 // CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 5390 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP38]], align 4 5391 // CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 5392 // CHECK7-NEXT: store i32 0, ptr [[TMP39]], align 4 5393 // CHECK7-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, ptr [[KERNEL_ARGS]]) 5394 // CHECK7-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 5395 // CHECK7-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5396 // CHECK7: omp_offload.failed: 5397 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP11]], i32 [[TMP13]], i32 [[TMP15]]) #[[ATTR3]] 5398 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 5399 // CHECK7: omp_offload.cont: 5400 // CHECK7-NEXT: [[TMP42:%.*]] = load i32, ptr [[A]], align 4 5401 // CHECK7-NEXT: store i32 [[TMP42]], ptr [[A_CASTED3]], align 4 5402 // CHECK7-NEXT: [[TMP43:%.*]] = load i32, ptr [[A_CASTED3]], align 4 5403 // CHECK7-NEXT: [[TMP44:%.*]] = load i16, ptr [[AA]], align 2 5404 // CHECK7-NEXT: store i16 [[TMP44]], ptr [[AA_CASTED4]], align 2 5405 // CHECK7-NEXT: [[TMP45:%.*]] = load i32, ptr [[AA_CASTED4]], align 4 5406 // CHECK7-NEXT: [[TMP46:%.*]] = load i32, ptr [[N_ADDR]], align 4 5407 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP46]], 10 5408 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5409 // CHECK7: omp_if.then: 5410 // CHECK7-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 5411 // CHECK7-NEXT: store i32 [[TMP43]], ptr [[TMP47]], align 4 5412 // CHECK7-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 5413 // CHECK7-NEXT: store i32 [[TMP43]], ptr [[TMP48]], align 4 5414 // CHECK7-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 5415 // CHECK7-NEXT: store ptr null, ptr [[TMP49]], align 4 5416 // CHECK7-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 5417 // CHECK7-NEXT: store i32 [[TMP45]], ptr [[TMP50]], align 4 5418 // CHECK7-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 5419 // CHECK7-NEXT: store i32 [[TMP45]], ptr [[TMP51]], align 4 5420 // CHECK7-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 5421 // CHECK7-NEXT: store ptr null, ptr [[TMP52]], align 4 5422 // CHECK7-NEXT: [[TMP53:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 5423 // CHECK7-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 5424 // CHECK7-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0 5425 // CHECK7-NEXT: store i32 3, ptr [[TMP55]], align 4 5426 // CHECK7-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1 5427 // CHECK7-NEXT: store i32 2, ptr [[TMP56]], align 4 5428 // CHECK7-NEXT: [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2 5429 // CHECK7-NEXT: store ptr [[TMP53]], ptr [[TMP57]], align 4 5430 // CHECK7-NEXT: [[TMP58:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3 5431 // CHECK7-NEXT: store ptr [[TMP54]], ptr [[TMP58]], align 4 5432 // CHECK7-NEXT: [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4 5433 // CHECK7-NEXT: store ptr @.offload_sizes.1, ptr [[TMP59]], align 4 5434 // CHECK7-NEXT: [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5 5435 // CHECK7-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP60]], align 4 5436 // CHECK7-NEXT: [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6 5437 // CHECK7-NEXT: store ptr null, ptr [[TMP61]], align 4 5438 // CHECK7-NEXT: [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7 5439 // CHECK7-NEXT: store ptr null, ptr [[TMP62]], align 4 5440 // CHECK7-NEXT: [[TMP63:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8 5441 // CHECK7-NEXT: store i64 0, ptr [[TMP63]], align 8 5442 // CHECK7-NEXT: [[TMP64:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 9 5443 // CHECK7-NEXT: store i64 0, ptr [[TMP64]], align 8 5444 // CHECK7-NEXT: [[TMP65:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 10 5445 // CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP65]], align 4 5446 // CHECK7-NEXT: [[TMP66:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 11 5447 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP66]], align 4 5448 // CHECK7-NEXT: [[TMP67:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12 5449 // CHECK7-NEXT: store i32 0, ptr [[TMP67]], align 4 5450 // CHECK7-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, ptr [[KERNEL_ARGS8]]) 5451 // CHECK7-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 5452 // CHECK7-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 5453 // CHECK7: omp_offload.failed9: 5454 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR3]] 5455 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT10]] 5456 // CHECK7: omp_offload.cont10: 5457 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 5458 // CHECK7: omp_if.else: 5459 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR3]] 5460 // CHECK7-NEXT: br label [[OMP_IF_END]] 5461 // CHECK7: omp_if.end: 5462 // CHECK7-NEXT: [[TMP70:%.*]] = load i32, ptr [[A]], align 4 5463 // CHECK7-NEXT: store i32 [[TMP70]], ptr [[DOTCAPTURE_EXPR_]], align 4 5464 // CHECK7-NEXT: [[TMP71:%.*]] = load i32, ptr [[A]], align 4 5465 // CHECK7-NEXT: store i32 [[TMP71]], ptr [[A_CASTED11]], align 4 5466 // CHECK7-NEXT: [[TMP72:%.*]] = load i32, ptr [[A_CASTED11]], align 4 5467 // CHECK7-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 5468 // CHECK7-NEXT: store i32 [[TMP73]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 5469 // CHECK7-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 5470 // CHECK7-NEXT: [[TMP75:%.*]] = load i32, ptr [[N_ADDR]], align 4 5471 // CHECK7-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP75]], 20 5472 // CHECK7-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]] 5473 // CHECK7: omp_if.then13: 5474 // CHECK7-NEXT: [[TMP76:%.*]] = mul nuw i32 [[TMP1]], 4 5475 // CHECK7-NEXT: [[TMP77:%.*]] = sext i32 [[TMP76]] to i64 5476 // CHECK7-NEXT: [[TMP78:%.*]] = mul nuw i32 5, [[TMP3]] 5477 // CHECK7-NEXT: [[TMP79:%.*]] = mul nuw i32 [[TMP78]], 8 5478 // CHECK7-NEXT: [[TMP80:%.*]] = sext i32 [[TMP79]] to i64 5479 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.3, i32 80, i1 false) 5480 // CHECK7-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 5481 // CHECK7-NEXT: store i32 [[TMP72]], ptr [[TMP81]], align 4 5482 // CHECK7-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 5483 // CHECK7-NEXT: store i32 [[TMP72]], ptr [[TMP82]], align 4 5484 // CHECK7-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 5485 // CHECK7-NEXT: store ptr null, ptr [[TMP83]], align 4 5486 // CHECK7-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 5487 // CHECK7-NEXT: store ptr [[B]], ptr [[TMP84]], align 4 5488 // CHECK7-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 5489 // CHECK7-NEXT: store ptr [[B]], ptr [[TMP85]], align 4 5490 // CHECK7-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 5491 // CHECK7-NEXT: store ptr null, ptr [[TMP86]], align 4 5492 // CHECK7-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 5493 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP87]], align 4 5494 // CHECK7-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 5495 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP88]], align 4 5496 // CHECK7-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 5497 // CHECK7-NEXT: store ptr null, ptr [[TMP89]], align 4 5498 // CHECK7-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 5499 // CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP90]], align 4 5500 // CHECK7-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 5501 // CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP91]], align 4 5502 // CHECK7-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 5503 // CHECK7-NEXT: store i64 [[TMP77]], ptr [[TMP92]], align 4 5504 // CHECK7-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 5505 // CHECK7-NEXT: store ptr null, ptr [[TMP93]], align 4 5506 // CHECK7-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 5507 // CHECK7-NEXT: store ptr [[C]], ptr [[TMP94]], align 4 5508 // CHECK7-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 5509 // CHECK7-NEXT: store ptr [[C]], ptr [[TMP95]], align 4 5510 // CHECK7-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 5511 // CHECK7-NEXT: store ptr null, ptr [[TMP96]], align 4 5512 // CHECK7-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 5513 // CHECK7-NEXT: store i32 5, ptr [[TMP97]], align 4 5514 // CHECK7-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 5515 // CHECK7-NEXT: store i32 5, ptr [[TMP98]], align 4 5516 // CHECK7-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 5517 // CHECK7-NEXT: store ptr null, ptr [[TMP99]], align 4 5518 // CHECK7-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 5519 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP100]], align 4 5520 // CHECK7-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 5521 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP101]], align 4 5522 // CHECK7-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 5523 // CHECK7-NEXT: store ptr null, ptr [[TMP102]], align 4 5524 // CHECK7-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 5525 // CHECK7-NEXT: store ptr [[VLA1]], ptr [[TMP103]], align 4 5526 // CHECK7-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 5527 // CHECK7-NEXT: store ptr [[VLA1]], ptr [[TMP104]], align 4 5528 // CHECK7-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 5529 // CHECK7-NEXT: store i64 [[TMP80]], ptr [[TMP105]], align 4 5530 // CHECK7-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 5531 // CHECK7-NEXT: store ptr null, ptr [[TMP106]], align 4 5532 // CHECK7-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 5533 // CHECK7-NEXT: store ptr [[D]], ptr [[TMP107]], align 4 5534 // CHECK7-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 5535 // CHECK7-NEXT: store ptr [[D]], ptr [[TMP108]], align 4 5536 // CHECK7-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 5537 // CHECK7-NEXT: store ptr null, ptr [[TMP109]], align 4 5538 // CHECK7-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 5539 // CHECK7-NEXT: store i32 [[TMP74]], ptr [[TMP110]], align 4 5540 // CHECK7-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 5541 // CHECK7-NEXT: store i32 [[TMP74]], ptr [[TMP111]], align 4 5542 // CHECK7-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 5543 // CHECK7-NEXT: store ptr null, ptr [[TMP112]], align 4 5544 // CHECK7-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 5545 // CHECK7-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 5546 // CHECK7-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5547 // CHECK7-NEXT: [[TMP116:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0 5548 // CHECK7-NEXT: store i32 3, ptr [[TMP116]], align 4 5549 // CHECK7-NEXT: [[TMP117:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1 5550 // CHECK7-NEXT: store i32 10, ptr [[TMP117]], align 4 5551 // CHECK7-NEXT: [[TMP118:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2 5552 // CHECK7-NEXT: store ptr [[TMP113]], ptr [[TMP118]], align 4 5553 // CHECK7-NEXT: [[TMP119:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3 5554 // CHECK7-NEXT: store ptr [[TMP114]], ptr [[TMP119]], align 4 5555 // CHECK7-NEXT: [[TMP120:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4 5556 // CHECK7-NEXT: store ptr [[TMP115]], ptr [[TMP120]], align 4 5557 // CHECK7-NEXT: [[TMP121:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5 5558 // CHECK7-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP121]], align 4 5559 // CHECK7-NEXT: [[TMP122:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6 5560 // CHECK7-NEXT: store ptr null, ptr [[TMP122]], align 4 5561 // CHECK7-NEXT: [[TMP123:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7 5562 // CHECK7-NEXT: store ptr null, ptr [[TMP123]], align 4 5563 // CHECK7-NEXT: [[TMP124:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8 5564 // CHECK7-NEXT: store i64 0, ptr [[TMP124]], align 8 5565 // CHECK7-NEXT: [[TMP125:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 9 5566 // CHECK7-NEXT: store i64 0, ptr [[TMP125]], align 8 5567 // CHECK7-NEXT: [[TMP126:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 10 5568 // CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP126]], align 4 5569 // CHECK7-NEXT: [[TMP127:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 11 5570 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP127]], align 4 5571 // CHECK7-NEXT: [[TMP128:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12 5572 // CHECK7-NEXT: store i32 0, ptr [[TMP128]], align 4 5573 // CHECK7-NEXT: [[TMP129:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, ptr [[KERNEL_ARGS17]]) 5574 // CHECK7-NEXT: [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 0 5575 // CHECK7-NEXT: br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] 5576 // CHECK7: omp_offload.failed18: 5577 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR3]] 5578 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT19]] 5579 // CHECK7: omp_offload.cont19: 5580 // CHECK7-NEXT: br label [[OMP_IF_END21:%.*]] 5581 // CHECK7: omp_if.else20: 5582 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR3]] 5583 // CHECK7-NEXT: br label [[OMP_IF_END21]] 5584 // CHECK7: omp_if.end21: 5585 // CHECK7-NEXT: [[TMP131:%.*]] = load i32, ptr [[A]], align 4 5586 // CHECK7-NEXT: [[TMP132:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 5587 // CHECK7-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP132]]) 5588 // CHECK7-NEXT: ret i32 [[TMP131]] 5589 // 5590 // 5591 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 5592 // CHECK7-SAME: () #[[ATTR2:[0-9]+]] { 5593 // CHECK7-NEXT: entry: 5594 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) 5595 // CHECK7-NEXT: ret void 5596 // 5597 // 5598 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined 5599 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { 5600 // CHECK7-NEXT: entry: 5601 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 5602 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 5603 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5604 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5605 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5606 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5607 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5608 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5609 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 5610 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 5611 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 5612 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5613 // CHECK7-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 5614 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 5615 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5616 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 5617 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 5618 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 5619 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5620 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 5621 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5622 // CHECK7: cond.true: 5623 // CHECK7-NEXT: br label [[COND_END:%.*]] 5624 // CHECK7: cond.false: 5625 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5626 // CHECK7-NEXT: br label [[COND_END]] 5627 // CHECK7: cond.end: 5628 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 5629 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 5630 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5631 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 5632 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5633 // CHECK7: omp.inner.for.cond: 5634 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 5635 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 5636 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 5637 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5638 // CHECK7: omp.inner.for.body: 5639 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 5640 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 5641 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 5642 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 5643 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5644 // CHECK7: omp.body.continue: 5645 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5646 // CHECK7: omp.inner.for.inc: 5647 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 5648 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 5649 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 5650 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 5651 // CHECK7: omp.inner.for.end: 5652 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5653 // CHECK7: omp.loop.exit: 5654 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 5655 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5656 // CHECK7-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 5657 // CHECK7-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5658 // CHECK7: .omp.final.then: 5659 // CHECK7-NEXT: store i32 33, ptr [[I]], align 4 5660 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 5661 // CHECK7: .omp.final.done: 5662 // CHECK7-NEXT: ret void 5663 // 5664 // 5665 // CHECK7-LABEL: define {{[^@]+}}@.omp_task_entry. 5666 // CHECK7-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { 5667 // CHECK7-NEXT: entry: 5668 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 5669 // CHECK7-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4 5670 // CHECK7-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4 5671 // CHECK7-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4 5672 // CHECK7-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4 5673 // CHECK7-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4 5674 // CHECK7-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 5675 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 5676 // CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 5677 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 5678 // CHECK7-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 5679 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 5680 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 5681 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 5682 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 5683 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 5684 // CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 5685 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 5686 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 5687 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 5688 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) 5689 // CHECK7-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META26:![0-9]+]] 5690 // CHECK7-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias [[META26]] 5691 // CHECK7-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META26]] 5692 // CHECK7-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META26]] 5693 // CHECK7-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias [[META26]] 5694 // CHECK7-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META26]] 5695 // CHECK7-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META26]] 5696 // CHECK7-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META26]] 5697 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 5698 // CHECK7-NEXT: store i32 0, ptr [[TMP9]], align 4, !noalias [[META26]] 5699 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 5700 // CHECK7-NEXT: store ptr null, ptr [[TMP10]], align 4, !noalias [[META26]] 5701 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 5702 // CHECK7-NEXT: store ptr null, ptr [[TMP11]], align 4, !noalias [[META26]] 5703 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 5704 // CHECK7-NEXT: store ptr null, ptr [[TMP12]], align 4, !noalias [[META26]] 5705 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 5706 // CHECK7-NEXT: store ptr null, ptr [[TMP13]], align 4, !noalias [[META26]] 5707 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 5708 // CHECK7-NEXT: store ptr null, ptr [[TMP14]], align 4, !noalias [[META26]] 5709 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 5710 // CHECK7-NEXT: store ptr null, ptr [[TMP15]], align 4, !noalias [[META26]] 5711 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 5712 // CHECK7-NEXT: store i64 0, ptr [[TMP16]], align 8, !noalias [[META26]] 5713 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9 5714 // CHECK7-NEXT: store i64 1, ptr [[TMP17]], align 8, !noalias [[META26]] 5715 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10 5716 // CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4, !noalias [[META26]] 5717 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11 5718 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4, !noalias [[META26]] 5719 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12 5720 // CHECK7-NEXT: store i32 0, ptr [[TMP20]], align 4, !noalias [[META26]] 5721 // CHECK7-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, ptr [[KERNEL_ARGS_I]]) 5722 // CHECK7-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 5723 // CHECK7-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] 5724 // CHECK7: omp_offload.failed.i: 5725 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR3]] 5726 // CHECK7-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] 5727 // CHECK7: .omp_outlined..exit: 5728 // CHECK7-NEXT: ret i32 0 5729 // 5730 // 5731 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 5732 // CHECK7-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { 5733 // CHECK7-NEXT: entry: 5734 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5735 // CHECK7-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4 5736 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5737 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5738 // CHECK7-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4 5739 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4 5740 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 5741 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 5742 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 5743 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i32 [[TMP2]], ptr [[TMP0]]) 5744 // CHECK7-NEXT: ret void 5745 // 5746 // 5747 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined 5748 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { 5749 // CHECK7-NEXT: entry: 5750 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 5751 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 5752 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5753 // CHECK7-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4 5754 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5755 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5756 // CHECK7-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 5757 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5758 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5759 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5760 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5761 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 5762 // CHECK7-NEXT: [[K1:%.*]] = alloca i64, align 8 5763 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 5764 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 5765 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5766 // CHECK7-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4 5767 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4 5768 // CHECK7-NEXT: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 8 5769 // CHECK7-NEXT: store i64 [[TMP1]], ptr [[DOTLINEAR_START]], align 8 5770 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5771 // CHECK7-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 4 5772 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 5773 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5774 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 5775 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 5776 // CHECK7-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 5777 // CHECK7-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 5778 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 5779 // CHECK7: omp.dispatch.cond: 5780 // CHECK7-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]) 5781 // CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 5782 // CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 5783 // CHECK7: omp.dispatch.body: 5784 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5785 // CHECK7-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 5786 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5787 // CHECK7: omp.inner.for.cond: 5788 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] 5789 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] 5790 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 5791 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5792 // CHECK7: omp.inner.for.body: 5793 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 5794 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 5795 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 5796 // CHECK7-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] 5797 // CHECK7-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP27]] 5798 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 5799 // CHECK7-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 5800 // CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 5801 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 5802 // CHECK7-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP27]] 5803 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 5804 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 5805 // CHECK7-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 5806 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5807 // CHECK7: omp.body.continue: 5808 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5809 // CHECK7: omp.inner.for.inc: 5810 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 5811 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 5812 // CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 5813 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 5814 // CHECK7: omp.inner.for.end: 5815 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 5816 // CHECK7: omp.dispatch.inc: 5817 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] 5818 // CHECK7: omp.dispatch.end: 5819 // CHECK7-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP3]]) 5820 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5821 // CHECK7-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 5822 // CHECK7-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5823 // CHECK7: .omp.final.then: 5824 // CHECK7-NEXT: store i32 1, ptr [[I]], align 4 5825 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 5826 // CHECK7: .omp.final.done: 5827 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5828 // CHECK7-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 5829 // CHECK7-NEXT: br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 5830 // CHECK7: .omp.linear.pu: 5831 // CHECK7-NEXT: [[TMP17:%.*]] = load i64, ptr [[K1]], align 8 5832 // CHECK7-NEXT: store i64 [[TMP17]], ptr [[TMP0]], align 8 5833 // CHECK7-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 5834 // CHECK7: .omp.linear.pu.done: 5835 // CHECK7-NEXT: ret void 5836 // 5837 // 5838 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 5839 // CHECK7-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 5840 // CHECK7-NEXT: entry: 5841 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5842 // CHECK7-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 5843 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5844 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5845 // CHECK7-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 5846 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5847 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 5848 // CHECK7-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 5849 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5850 // CHECK7-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 5851 // CHECK7-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 5852 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 5853 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 5854 // CHECK7-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 5855 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 5856 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 5857 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 5858 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4 5859 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 5860 // CHECK7-NEXT: ret void 5861 // 5862 // 5863 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined 5864 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 5865 // CHECK7-NEXT: entry: 5866 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 5867 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 5868 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5869 // CHECK7-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 5870 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5871 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5872 // CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 5873 // CHECK7-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 5874 // CHECK7-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 5875 // CHECK7-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 5876 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5877 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5878 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5879 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5880 // CHECK7-NEXT: [[IT:%.*]] = alloca i64, align 8 5881 // CHECK7-NEXT: [[LIN2:%.*]] = alloca i32, align 4 5882 // CHECK7-NEXT: [[A3:%.*]] = alloca i32, align 4 5883 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 5884 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 5885 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 5886 // CHECK7-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 5887 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5888 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 5889 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 5890 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 5891 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 5892 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 5893 // CHECK7-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 5894 // CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 5895 // CHECK7-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 5896 // CHECK7-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 5897 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5898 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 5899 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 5900 // CHECK7-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]]) 5901 // CHECK7-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 5902 // CHECK7-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5903 // CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 5904 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5905 // CHECK7: cond.true: 5906 // CHECK7-NEXT: br label [[COND_END:%.*]] 5907 // CHECK7: cond.false: 5908 // CHECK7-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5909 // CHECK7-NEXT: br label [[COND_END]] 5910 // CHECK7: cond.end: 5911 // CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 5912 // CHECK7-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 5913 // CHECK7-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 5914 // CHECK7-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 5915 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5916 // CHECK7: omp.inner.for.cond: 5917 // CHECK7-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30:![0-9]+]] 5918 // CHECK7-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP30]] 5919 // CHECK7-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 5920 // CHECK7-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5921 // CHECK7: omp.inner.for.body: 5922 // CHECK7-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 5923 // CHECK7-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 5924 // CHECK7-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 5925 // CHECK7-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP30]] 5926 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP30]] 5927 // CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 5928 // CHECK7-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 5929 // CHECK7-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]] 5930 // CHECK7-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 5931 // CHECK7-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 5932 // CHECK7-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 5933 // CHECK7-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP30]] 5934 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP30]] 5935 // CHECK7-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 5936 // CHECK7-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 5937 // CHECK7-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]] 5938 // CHECK7-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 5939 // CHECK7-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 5940 // CHECK7-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 5941 // CHECK7-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP30]] 5942 // CHECK7-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] 5943 // CHECK7-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 5944 // CHECK7-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 5945 // CHECK7-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 5946 // CHECK7-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] 5947 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5948 // CHECK7: omp.body.continue: 5949 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5950 // CHECK7: omp.inner.for.inc: 5951 // CHECK7-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 5952 // CHECK7-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 5953 // CHECK7-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 5954 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 5955 // CHECK7: omp.inner.for.end: 5956 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5957 // CHECK7: omp.loop.exit: 5958 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 5959 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5960 // CHECK7-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 5961 // CHECK7-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5962 // CHECK7: .omp.final.then: 5963 // CHECK7-NEXT: store i64 400, ptr [[IT]], align 8 5964 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 5965 // CHECK7: .omp.final.done: 5966 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5967 // CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 5968 // CHECK7-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 5969 // CHECK7: .omp.linear.pu: 5970 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 5971 // CHECK7-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 5972 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 5973 // CHECK7-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 5974 // CHECK7-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 5975 // CHECK7: .omp.linear.pu.done: 5976 // CHECK7-NEXT: ret void 5977 // 5978 // 5979 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 5980 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 5981 // CHECK7-NEXT: entry: 5982 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5983 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5984 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5985 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5986 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5987 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 5988 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 5989 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 5990 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 5991 // CHECK7-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 5992 // CHECK7-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 5993 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 5994 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) 5995 // CHECK7-NEXT: ret void 5996 // 5997 // 5998 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined 5999 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 6000 // CHECK7-NEXT: entry: 6001 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 6002 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 6003 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6004 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6005 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6006 // CHECK7-NEXT: [[TMP:%.*]] = alloca i16, align 2 6007 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6008 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6009 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6010 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6011 // CHECK7-NEXT: [[IT:%.*]] = alloca i16, align 2 6012 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 6013 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 6014 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6015 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 6016 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 6017 // CHECK7-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 6018 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 6019 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 6020 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6021 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 6022 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 6023 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6024 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 6025 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6026 // CHECK7: cond.true: 6027 // CHECK7-NEXT: br label [[COND_END:%.*]] 6028 // CHECK7: cond.false: 6029 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6030 // CHECK7-NEXT: br label [[COND_END]] 6031 // CHECK7: cond.end: 6032 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 6033 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 6034 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6035 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 6036 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6037 // CHECK7: omp.inner.for.cond: 6038 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] 6039 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] 6040 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 6041 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6042 // CHECK7: omp.inner.for.body: 6043 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 6044 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 6045 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 6046 // CHECK7-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 6047 // CHECK7-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP33]] 6048 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 6049 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 6050 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 6051 // CHECK7-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] 6052 // CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 6053 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 6054 // CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 6055 // CHECK7-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] 6056 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6057 // CHECK7: omp.body.continue: 6058 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6059 // CHECK7: omp.inner.for.inc: 6060 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 6061 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 6062 // CHECK7-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 6063 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 6064 // CHECK7: omp.inner.for.end: 6065 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6066 // CHECK7: omp.loop.exit: 6067 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 6068 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 6069 // CHECK7-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 6070 // CHECK7-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6071 // CHECK7: .omp.final.then: 6072 // CHECK7-NEXT: store i16 22, ptr [[IT]], align 2 6073 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6074 // CHECK7: .omp.final.done: 6075 // CHECK7-NEXT: ret void 6076 // 6077 // 6078 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 6079 // CHECK7-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 6080 // CHECK7-NEXT: entry: 6081 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6082 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6083 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6084 // CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 6085 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 6086 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6087 // CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 6088 // CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 6089 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 6090 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6091 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6092 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 6093 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6094 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6095 // CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 6096 // CHECK7-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 6097 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 6098 // CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 6099 // CHECK7-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 6100 // CHECK7-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 6101 // CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 6102 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 6103 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 6104 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 6105 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 6106 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 6107 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 6108 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 6109 // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 6110 // CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 6111 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 6112 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 6113 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 6114 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 6115 // CHECK7-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 6116 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 6117 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]]) 6118 // CHECK7-NEXT: ret void 6119 // 6120 // 6121 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined 6122 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 6123 // CHECK7-NEXT: entry: 6124 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 6125 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 6126 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6127 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6128 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6129 // CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 6130 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 6131 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6132 // CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 6133 // CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 6134 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 6135 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6136 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6137 // CHECK7-NEXT: [[TMP:%.*]] = alloca i8, align 1 6138 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6139 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6140 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6141 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6142 // CHECK7-NEXT: [[IT:%.*]] = alloca i8, align 1 6143 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 6144 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 6145 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6146 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6147 // CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 6148 // CHECK7-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 6149 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 6150 // CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 6151 // CHECK7-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 6152 // CHECK7-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 6153 // CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 6154 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 6155 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 6156 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 6157 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 6158 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 6159 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 6160 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 6161 // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 6162 // CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 6163 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 6164 // CHECK7-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 6165 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 6166 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 6167 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 6168 // CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6169 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 6170 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 6171 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6172 // CHECK7: omp.dispatch.cond: 6173 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6174 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 6175 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6176 // CHECK7: cond.true: 6177 // CHECK7-NEXT: br label [[COND_END:%.*]] 6178 // CHECK7: cond.false: 6179 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6180 // CHECK7-NEXT: br label [[COND_END]] 6181 // CHECK7: cond.end: 6182 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 6183 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 6184 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6185 // CHECK7-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 6186 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 6187 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6188 // CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 6189 // CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6190 // CHECK7: omp.dispatch.body: 6191 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6192 // CHECK7: omp.inner.for.cond: 6193 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] 6194 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]] 6195 // CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 6196 // CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6197 // CHECK7: omp.inner.for.body: 6198 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 6199 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 6200 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 6201 // CHECK7-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 6202 // CHECK7-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP36]] 6203 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] 6204 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 6205 // CHECK7-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] 6206 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 6207 // CHECK7-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] 6208 // CHECK7-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 6209 // CHECK7-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 6210 // CHECK7-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 6211 // CHECK7-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] 6212 // CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 6213 // CHECK7-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]] 6214 // CHECK7-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 6215 // CHECK7-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 6216 // CHECK7-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 6217 // CHECK7-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]] 6218 // CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 6219 // CHECK7-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 6220 // CHECK7-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] 6221 // CHECK7-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 6222 // CHECK7-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] 6223 // CHECK7-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 6224 // CHECK7-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]] 6225 // CHECK7-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3 6226 // CHECK7-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]] 6227 // CHECK7-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 6228 // CHECK7-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]] 6229 // CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 6230 // CHECK7-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]] 6231 // CHECK7-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 6232 // CHECK7-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]] 6233 // CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 6234 // CHECK7-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]] 6235 // CHECK7-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 6236 // CHECK7-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 6237 // CHECK7-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 6238 // CHECK7-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]] 6239 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6240 // CHECK7: omp.body.continue: 6241 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6242 // CHECK7: omp.inner.for.inc: 6243 // CHECK7-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 6244 // CHECK7-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 6245 // CHECK7-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 6246 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] 6247 // CHECK7: omp.inner.for.end: 6248 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6249 // CHECK7: omp.dispatch.inc: 6250 // CHECK7-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6251 // CHECK7-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 6252 // CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 6253 // CHECK7-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 6254 // CHECK7-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6255 // CHECK7-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 6256 // CHECK7-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 6257 // CHECK7-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 6258 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] 6259 // CHECK7: omp.dispatch.end: 6260 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 6261 // CHECK7-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 6262 // CHECK7-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 6263 // CHECK7-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6264 // CHECK7: .omp.final.then: 6265 // CHECK7-NEXT: store i8 96, ptr [[IT]], align 1 6266 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6267 // CHECK7: .omp.final.done: 6268 // CHECK7-NEXT: ret void 6269 // 6270 // 6271 // CHECK7-LABEL: define {{[^@]+}}@_Z3bari 6272 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 6273 // CHECK7-NEXT: entry: 6274 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6275 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6276 // CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 6277 // CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 6278 // CHECK7-NEXT: store i32 0, ptr [[A]], align 4 6279 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 6280 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 6281 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 6282 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6283 // CHECK7-NEXT: store i32 [[ADD]], ptr [[A]], align 4 6284 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 6285 // CHECK7-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 6286 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 6287 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6288 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 6289 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 6290 // CHECK7-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 6291 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 6292 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6293 // CHECK7-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 6294 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 6295 // CHECK7-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 6296 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 6297 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 6298 // CHECK7-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 6299 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 6300 // CHECK7-NEXT: ret i32 [[TMP8]] 6301 // 6302 // 6303 // CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6304 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6305 // CHECK7-NEXT: entry: 6306 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 6307 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6308 // CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 6309 // CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 6310 // CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 6311 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 6312 // CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6313 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 6314 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x ptr], align 4 6315 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x ptr], align 4 6316 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x ptr], align 4 6317 // CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 4 6318 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 6319 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 6320 // CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 6321 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 6322 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 6323 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6324 // CHECK7-NEXT: store i32 [[ADD]], ptr [[B]], align 4 6325 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 6326 // CHECK7-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0() 6327 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 6328 // CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 6329 // CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 6330 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 6331 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 6332 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 6333 // CHECK7-NEXT: [[STOREDV:%.*]] = zext i1 [[CMP]] to i8 6334 // CHECK7-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1 6335 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 6336 // CHECK7-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 6337 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4 6338 // CHECK7-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 6339 // CHECK7-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i1 6340 // CHECK7-NEXT: [[STOREDV2:%.*]] = zext i1 [[LOADEDV]] to i8 6341 // CHECK7-NEXT: store i8 [[STOREDV2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 6342 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 6343 // CHECK7-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 6344 // CHECK7-NEXT: [[LOADEDV3:%.*]] = trunc i8 [[TMP9]] to i1 6345 // CHECK7-NEXT: br i1 [[LOADEDV3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6346 // CHECK7: omp_if.then: 6347 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 6348 // CHECK7-NEXT: [[TMP10:%.*]] = mul nuw i32 2, [[TMP1]] 6349 // CHECK7-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 2 6350 // CHECK7-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 6351 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 48, i1 false) 6352 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6353 // CHECK7-NEXT: store ptr [[THIS1]], ptr [[TMP13]], align 4 6354 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6355 // CHECK7-NEXT: store ptr [[A]], ptr [[TMP14]], align 4 6356 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6357 // CHECK7-NEXT: store ptr null, ptr [[TMP15]], align 4 6358 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6359 // CHECK7-NEXT: store i32 [[TMP6]], ptr [[TMP16]], align 4 6360 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6361 // CHECK7-NEXT: store i32 [[TMP6]], ptr [[TMP17]], align 4 6362 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6363 // CHECK7-NEXT: store ptr null, ptr [[TMP18]], align 4 6364 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6365 // CHECK7-NEXT: store i32 2, ptr [[TMP19]], align 4 6366 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6367 // CHECK7-NEXT: store i32 2, ptr [[TMP20]], align 4 6368 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6369 // CHECK7-NEXT: store ptr null, ptr [[TMP21]], align 4 6370 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6371 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP22]], align 4 6372 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6373 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP23]], align 4 6374 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 6375 // CHECK7-NEXT: store ptr null, ptr [[TMP24]], align 4 6376 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 6377 // CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP25]], align 4 6378 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 6379 // CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP26]], align 4 6380 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 6381 // CHECK7-NEXT: store i64 [[TMP12]], ptr [[TMP27]], align 4 6382 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 6383 // CHECK7-NEXT: store ptr null, ptr [[TMP28]], align 4 6384 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 6385 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[TMP29]], align 4 6386 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5 6387 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[TMP30]], align 4 6388 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 6389 // CHECK7-NEXT: store ptr null, ptr [[TMP31]], align 4 6390 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6391 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6392 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 6393 // CHECK7-NEXT: [[TMP35:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 6394 // CHECK7-NEXT: [[LOADEDV4:%.*]] = trunc i8 [[TMP35]] to i1 6395 // CHECK7-NEXT: [[TMP36:%.*]] = select i1 [[LOADEDV4]], i32 0, i32 1 6396 // CHECK7-NEXT: [[TMP37:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP36]], 0 6397 // CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 6398 // CHECK7-NEXT: store i32 3, ptr [[TMP38]], align 4 6399 // CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 6400 // CHECK7-NEXT: store i32 6, ptr [[TMP39]], align 4 6401 // CHECK7-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 6402 // CHECK7-NEXT: store ptr [[TMP32]], ptr [[TMP40]], align 4 6403 // CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 6404 // CHECK7-NEXT: store ptr [[TMP33]], ptr [[TMP41]], align 4 6405 // CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 6406 // CHECK7-NEXT: store ptr [[TMP34]], ptr [[TMP42]], align 4 6407 // CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 6408 // CHECK7-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP43]], align 4 6409 // CHECK7-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 6410 // CHECK7-NEXT: store ptr null, ptr [[TMP44]], align 4 6411 // CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 6412 // CHECK7-NEXT: store ptr null, ptr [[TMP45]], align 4 6413 // CHECK7-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 6414 // CHECK7-NEXT: store i64 0, ptr [[TMP46]], align 8 6415 // CHECK7-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 6416 // CHECK7-NEXT: store i64 0, ptr [[TMP47]], align 8 6417 // CHECK7-NEXT: [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 6418 // CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP48]], align 4 6419 // CHECK7-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 6420 // CHECK7-NEXT: store [3 x i32] [[TMP37]], ptr [[TMP49]], align 4 6421 // CHECK7-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 6422 // CHECK7-NEXT: store i32 0, ptr [[TMP50]], align 4 6423 // CHECK7-NEXT: [[TMP51:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 [[TMP36]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, ptr [[KERNEL_ARGS]]) 6424 // CHECK7-NEXT: [[TMP52:%.*]] = icmp ne i32 [[TMP51]], 0 6425 // CHECK7-NEXT: br i1 [[TMP52]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6426 // CHECK7: omp_offload.failed: 6427 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR3]] 6428 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 6429 // CHECK7: omp_offload.cont: 6430 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6431 // CHECK7: omp_if.else: 6432 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR3]] 6433 // CHECK7-NEXT: br label [[OMP_IF_END]] 6434 // CHECK7: omp_if.end: 6435 // CHECK7-NEXT: [[TMP53:%.*]] = mul nsw i32 1, [[TMP1]] 6436 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP53]] 6437 // CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 6438 // CHECK7-NEXT: [[TMP54:%.*]] = load i16, ptr [[ARRAYIDX5]], align 2 6439 // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP54]] to i32 6440 // CHECK7-NEXT: [[TMP55:%.*]] = load i32, ptr [[B]], align 4 6441 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV]], [[TMP55]] 6442 // CHECK7-NEXT: [[TMP56:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 6443 // CHECK7-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP56]]) 6444 // CHECK7-NEXT: ret i32 [[ADD6]] 6445 // 6446 // 6447 // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici 6448 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 6449 // CHECK7-NEXT: entry: 6450 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6451 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6452 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 6453 // CHECK7-NEXT: [[AAA:%.*]] = alloca i8, align 1 6454 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6455 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6456 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6457 // CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 6458 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 6459 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 6460 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 6461 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 6462 // CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 6463 // CHECK7-NEXT: store i32 0, ptr [[A]], align 4 6464 // CHECK7-NEXT: store i16 0, ptr [[AA]], align 2 6465 // CHECK7-NEXT: store i8 0, ptr [[AAA]], align 1 6466 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 6467 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 6468 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 6469 // CHECK7-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 6470 // CHECK7-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 6471 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 6472 // CHECK7-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1 6473 // CHECK7-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1 6474 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 6475 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 6476 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 6477 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6478 // CHECK7: omp_if.then: 6479 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6480 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 4 6481 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6482 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 4 6483 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6484 // CHECK7-NEXT: store ptr null, ptr [[TMP9]], align 4 6485 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6486 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP10]], align 4 6487 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6488 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP11]], align 4 6489 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6490 // CHECK7-NEXT: store ptr null, ptr [[TMP12]], align 4 6491 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6492 // CHECK7-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 4 6493 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6494 // CHECK7-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 4 6495 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6496 // CHECK7-NEXT: store ptr null, ptr [[TMP15]], align 4 6497 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6498 // CHECK7-NEXT: store ptr [[B]], ptr [[TMP16]], align 4 6499 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6500 // CHECK7-NEXT: store ptr [[B]], ptr [[TMP17]], align 4 6501 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 6502 // CHECK7-NEXT: store ptr null, ptr [[TMP18]], align 4 6503 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6504 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6505 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 6506 // CHECK7-NEXT: store i32 3, ptr [[TMP21]], align 4 6507 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 6508 // CHECK7-NEXT: store i32 4, ptr [[TMP22]], align 4 6509 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 6510 // CHECK7-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4 6511 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 6512 // CHECK7-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4 6513 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 6514 // CHECK7-NEXT: store ptr @.offload_sizes.7, ptr [[TMP25]], align 4 6515 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 6516 // CHECK7-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP26]], align 4 6517 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 6518 // CHECK7-NEXT: store ptr null, ptr [[TMP27]], align 4 6519 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 6520 // CHECK7-NEXT: store ptr null, ptr [[TMP28]], align 4 6521 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 6522 // CHECK7-NEXT: store i64 0, ptr [[TMP29]], align 8 6523 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 6524 // CHECK7-NEXT: store i64 0, ptr [[TMP30]], align 8 6525 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 6526 // CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4 6527 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 6528 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 6529 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 6530 // CHECK7-NEXT: store i32 0, ptr [[TMP33]], align 4 6531 // CHECK7-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, ptr [[KERNEL_ARGS]]) 6532 // CHECK7-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 6533 // CHECK7-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6534 // CHECK7: omp_offload.failed: 6535 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]] 6536 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 6537 // CHECK7: omp_offload.cont: 6538 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6539 // CHECK7: omp_if.else: 6540 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]] 6541 // CHECK7-NEXT: br label [[OMP_IF_END]] 6542 // CHECK7: omp_if.end: 6543 // CHECK7-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 6544 // CHECK7-NEXT: ret i32 [[TMP36]] 6545 // 6546 // 6547 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6548 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 6549 // CHECK7-NEXT: entry: 6550 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6551 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6552 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 6553 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6554 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6555 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6556 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 6557 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 6558 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 6559 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 6560 // CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 6561 // CHECK7-NEXT: store i32 0, ptr [[A]], align 4 6562 // CHECK7-NEXT: store i16 0, ptr [[AA]], align 2 6563 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 6564 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 6565 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 6566 // CHECK7-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 6567 // CHECK7-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 6568 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 6569 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 6570 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 6571 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6572 // CHECK7: omp_if.then: 6573 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6574 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 6575 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6576 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 4 6577 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6578 // CHECK7-NEXT: store ptr null, ptr [[TMP7]], align 4 6579 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6580 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 4 6581 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6582 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP9]], align 4 6583 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6584 // CHECK7-NEXT: store ptr null, ptr [[TMP10]], align 4 6585 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6586 // CHECK7-NEXT: store ptr [[B]], ptr [[TMP11]], align 4 6587 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6588 // CHECK7-NEXT: store ptr [[B]], ptr [[TMP12]], align 4 6589 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6590 // CHECK7-NEXT: store ptr null, ptr [[TMP13]], align 4 6591 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6592 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6593 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 6594 // CHECK7-NEXT: store i32 3, ptr [[TMP16]], align 4 6595 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 6596 // CHECK7-NEXT: store i32 3, ptr [[TMP17]], align 4 6597 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 6598 // CHECK7-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4 6599 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 6600 // CHECK7-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 4 6601 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 6602 // CHECK7-NEXT: store ptr @.offload_sizes.9, ptr [[TMP20]], align 4 6603 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 6604 // CHECK7-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP21]], align 4 6605 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 6606 // CHECK7-NEXT: store ptr null, ptr [[TMP22]], align 4 6607 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 6608 // CHECK7-NEXT: store ptr null, ptr [[TMP23]], align 4 6609 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 6610 // CHECK7-NEXT: store i64 0, ptr [[TMP24]], align 8 6611 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 6612 // CHECK7-NEXT: store i64 0, ptr [[TMP25]], align 8 6613 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 6614 // CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4 6615 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 6616 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 6617 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 6618 // CHECK7-NEXT: store i32 0, ptr [[TMP28]], align 4 6619 // CHECK7-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, ptr [[KERNEL_ARGS]]) 6620 // CHECK7-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 6621 // CHECK7-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6622 // CHECK7: omp_offload.failed: 6623 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] 6624 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 6625 // CHECK7: omp_offload.cont: 6626 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6627 // CHECK7: omp_if.else: 6628 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] 6629 // CHECK7-NEXT: br label [[OMP_IF_END]] 6630 // CHECK7: omp_if.end: 6631 // CHECK7-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 6632 // CHECK7-NEXT: ret i32 [[TMP31]] 6633 // 6634 // 6635 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 6636 // CHECK7-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 6637 // CHECK7-NEXT: entry: 6638 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 6639 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6640 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6641 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6642 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 6643 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6644 // CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6645 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 6646 // CHECK7-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 6647 // CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 6648 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 6649 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 6650 // CHECK7-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 6651 // CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 6652 // CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 6653 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 6654 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 6655 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 6656 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 6657 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 6658 // CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 4 6659 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4 6660 // CHECK7-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 6661 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4 6662 // CHECK7-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 6663 // CHECK7-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i1 6664 // CHECK7-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8 6665 // CHECK7-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 6666 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 6667 // CHECK7-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 6668 // CHECK7-NEXT: [[LOADEDV3:%.*]] = trunc i8 [[TMP9]] to i1 6669 // CHECK7-NEXT: br i1 [[LOADEDV3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6670 // CHECK7: omp_if.then: 6671 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) 6672 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6673 // CHECK7: omp_if.else: 6674 // CHECK7-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 6675 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 6676 // CHECK7-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 6677 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) #[[ATTR3]] 6678 // CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 6679 // CHECK7-NEXT: br label [[OMP_IF_END]] 6680 // CHECK7: omp_if.end: 6681 // CHECK7-NEXT: ret void 6682 // 6683 // 6684 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined 6685 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 6686 // CHECK7-NEXT: entry: 6687 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 6688 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 6689 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 6690 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6691 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6692 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6693 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 6694 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6695 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6696 // CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 6697 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6698 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6699 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6700 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6701 // CHECK7-NEXT: [[IT:%.*]] = alloca i64, align 8 6702 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 6703 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 6704 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 6705 // CHECK7-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 6706 // CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 6707 // CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 6708 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 6709 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 6710 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 6711 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 6712 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 6713 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 6714 // CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 6715 // CHECK7-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 6716 // CHECK7-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 6717 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 6718 // CHECK7-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 6719 // CHECK7-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP4]] to i1 6720 // CHECK7-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6721 // CHECK7: omp_if.then: 6722 // CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6723 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 6724 // CHECK7-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 6725 // CHECK7-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6726 // CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 6727 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6728 // CHECK7: cond.true: 6729 // CHECK7-NEXT: br label [[COND_END:%.*]] 6730 // CHECK7: cond.false: 6731 // CHECK7-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6732 // CHECK7-NEXT: br label [[COND_END]] 6733 // CHECK7: cond.end: 6734 // CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 6735 // CHECK7-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 6736 // CHECK7-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 6737 // CHECK7-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV]], align 8 6738 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6739 // CHECK7: omp.inner.for.cond: 6740 // CHECK7-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39:![0-9]+]] 6741 // CHECK7-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP39]] 6742 // CHECK7-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 6743 // CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6744 // CHECK7: omp.inner.for.body: 6745 // CHECK7-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 6746 // CHECK7-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 6747 // CHECK7-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 6748 // CHECK7-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP39]] 6749 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]] 6750 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double 6751 // CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 6752 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 6753 // CHECK7-NEXT: store double [[ADD]], ptr [[A]], align 4, !nontemporal [[META40:![0-9]+]], !llvm.access.group [[ACC_GRP39]] 6754 // CHECK7-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 6755 // CHECK7-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 4, !nontemporal [[META40]], !llvm.access.group [[ACC_GRP39]] 6756 // CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 6757 // CHECK7-NEXT: store double [[INC]], ptr [[A4]], align 4, !nontemporal [[META40]], !llvm.access.group [[ACC_GRP39]] 6758 // CHECK7-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 6759 // CHECK7-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]] 6760 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP15]] 6761 // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 6762 // CHECK7-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP39]] 6763 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6764 // CHECK7: omp.body.continue: 6765 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6766 // CHECK7: omp.inner.for.inc: 6767 // CHECK7-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 6768 // CHECK7-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1 6769 // CHECK7-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 6770 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] 6771 // CHECK7: omp.inner.for.end: 6772 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6773 // CHECK7: omp_if.else: 6774 // CHECK7-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6775 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 6776 // CHECK7-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP18]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 6777 // CHECK7-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6778 // CHECK7-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[TMP19]], 3 6779 // CHECK7-NEXT: br i1 [[CMP8]], label [[COND_TRUE9:%.*]], label [[COND_FALSE10:%.*]] 6780 // CHECK7: cond.true9: 6781 // CHECK7-NEXT: br label [[COND_END11:%.*]] 6782 // CHECK7: cond.false10: 6783 // CHECK7-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6784 // CHECK7-NEXT: br label [[COND_END11]] 6785 // CHECK7: cond.end11: 6786 // CHECK7-NEXT: [[COND12:%.*]] = phi i64 [ 3, [[COND_TRUE9]] ], [ [[TMP20]], [[COND_FALSE10]] ] 6787 // CHECK7-NEXT: store i64 [[COND12]], ptr [[DOTOMP_UB]], align 8 6788 // CHECK7-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 6789 // CHECK7-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV]], align 8 6790 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 6791 // CHECK7: omp.inner.for.cond13: 6792 // CHECK7-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 6793 // CHECK7-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6794 // CHECK7-NEXT: [[CMP14:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 6795 // CHECK7-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END29:%.*]] 6796 // CHECK7: omp.inner.for.body15: 6797 // CHECK7-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 6798 // CHECK7-NEXT: [[MUL16:%.*]] = mul i64 [[TMP24]], 400 6799 // CHECK7-NEXT: [[SUB17:%.*]] = sub i64 2000, [[MUL16]] 6800 // CHECK7-NEXT: store i64 [[SUB17]], ptr [[IT]], align 8 6801 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, ptr [[B_ADDR]], align 4 6802 // CHECK7-NEXT: [[CONV18:%.*]] = sitofp i32 [[TMP25]] to double 6803 // CHECK7-NEXT: [[ADD19:%.*]] = fadd double [[CONV18]], 1.500000e+00 6804 // CHECK7-NEXT: [[A20:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 6805 // CHECK7-NEXT: store double [[ADD19]], ptr [[A20]], align 4 6806 // CHECK7-NEXT: [[A21:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 6807 // CHECK7-NEXT: [[TMP26:%.*]] = load double, ptr [[A21]], align 4 6808 // CHECK7-NEXT: [[INC22:%.*]] = fadd double [[TMP26]], 1.000000e+00 6809 // CHECK7-NEXT: store double [[INC22]], ptr [[A21]], align 4 6810 // CHECK7-NEXT: [[CONV23:%.*]] = fptosi double [[INC22]] to i16 6811 // CHECK7-NEXT: [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]] 6812 // CHECK7-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP27]] 6813 // CHECK7-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX24]], i32 1 6814 // CHECK7-NEXT: store i16 [[CONV23]], ptr [[ARRAYIDX25]], align 2 6815 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] 6816 // CHECK7: omp.body.continue26: 6817 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] 6818 // CHECK7: omp.inner.for.inc27: 6819 // CHECK7-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 6820 // CHECK7-NEXT: [[ADD28:%.*]] = add i64 [[TMP28]], 1 6821 // CHECK7-NEXT: store i64 [[ADD28]], ptr [[DOTOMP_IV]], align 8 6822 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP43:![0-9]+]] 6823 // CHECK7: omp.inner.for.end29: 6824 // CHECK7-NEXT: br label [[OMP_IF_END]] 6825 // CHECK7: omp_if.end: 6826 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6827 // CHECK7: omp.loop.exit: 6828 // CHECK7-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6829 // CHECK7-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4 6830 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]]) 6831 // CHECK7-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 6832 // CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 6833 // CHECK7-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6834 // CHECK7: .omp.final.then: 6835 // CHECK7-NEXT: store i64 400, ptr [[IT]], align 8 6836 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6837 // CHECK7: .omp.final.done: 6838 // CHECK7-NEXT: ret void 6839 // 6840 // 6841 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 6842 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6843 // CHECK7-NEXT: entry: 6844 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6845 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6846 // CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 6847 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6848 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6849 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6850 // CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 6851 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6852 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 6853 // CHECK7-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 6854 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6855 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 6856 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 6857 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 6858 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 6859 // CHECK7-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 6860 // CHECK7-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 6861 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 6862 // CHECK7-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 6863 // CHECK7-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 6864 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 6865 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]]) 6866 // CHECK7-NEXT: ret void 6867 // 6868 // 6869 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined 6870 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6871 // CHECK7-NEXT: entry: 6872 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 6873 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 6874 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6875 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6876 // CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 6877 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6878 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6879 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 6880 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 6881 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 6882 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6883 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 6884 // CHECK7-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 6885 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6886 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 6887 // CHECK7-NEXT: ret void 6888 // 6889 // 6890 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 6891 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6892 // CHECK7-NEXT: entry: 6893 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6894 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6895 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6896 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6897 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6898 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6899 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 6900 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6901 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 6902 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 6903 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 6904 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 6905 // CHECK7-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 6906 // CHECK7-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 6907 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 6908 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) 6909 // CHECK7-NEXT: ret void 6910 // 6911 // 6912 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined 6913 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6914 // CHECK7-NEXT: entry: 6915 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 6916 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 6917 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6918 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6919 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6920 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6921 // CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 6922 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6923 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6924 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6925 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6926 // CHECK7-NEXT: [[I:%.*]] = alloca i64, align 8 6927 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 6928 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 6929 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6930 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 6931 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6932 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 6933 // CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 6934 // CHECK7-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 6935 // CHECK7-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 6936 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 6937 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6938 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 6939 // CHECK7-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 6940 // CHECK7-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6941 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 6942 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6943 // CHECK7: cond.true: 6944 // CHECK7-NEXT: br label [[COND_END:%.*]] 6945 // CHECK7: cond.false: 6946 // CHECK7-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6947 // CHECK7-NEXT: br label [[COND_END]] 6948 // CHECK7: cond.end: 6949 // CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 6950 // CHECK7-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 6951 // CHECK7-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 6952 // CHECK7-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 6953 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6954 // CHECK7: omp.inner.for.cond: 6955 // CHECK7-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45:![0-9]+]] 6956 // CHECK7-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP45]] 6957 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 6958 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6959 // CHECK7: omp.inner.for.body: 6960 // CHECK7-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45]] 6961 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 6962 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 6963 // CHECK7-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP45]] 6964 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]] 6965 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 6966 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]] 6967 // CHECK7-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]] 6968 // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 6969 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 6970 // CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 6971 // CHECK7-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]] 6972 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 6973 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] 6974 // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 6975 // CHECK7-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] 6976 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6977 // CHECK7: omp.body.continue: 6978 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6979 // CHECK7: omp.inner.for.inc: 6980 // CHECK7-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45]] 6981 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 6982 // CHECK7-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45]] 6983 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] 6984 // CHECK7: omp.inner.for.end: 6985 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6986 // CHECK7: omp.loop.exit: 6987 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 6988 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 6989 // CHECK7-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 6990 // CHECK7-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6991 // CHECK7: .omp.final.then: 6992 // CHECK7-NEXT: store i64 11, ptr [[I]], align 8 6993 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6994 // CHECK7: .omp.final.done: 6995 // CHECK7-NEXT: ret void 6996 // 6997 // 6998 // CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv 6999 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 7000 // CHECK9-NEXT: entry: 7001 // CHECK9-NEXT: ret i64 0 7002 // 7003 // 7004 // CHECK9-LABEL: define {{[^@]+}}@_Z3fooi 7005 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7006 // CHECK9-NEXT: entry: 7007 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7008 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7009 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 7010 // CHECK9-NEXT: [[B:%.*]] = alloca [10 x float], align 4 7011 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 7012 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7013 // CHECK9-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 7014 // CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 7015 // CHECK9-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 7016 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 7017 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7018 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7019 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7020 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 7021 // CHECK9-NEXT: [[K:%.*]] = alloca i64, align 8 7022 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 7023 // CHECK9-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 7024 // CHECK9-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 7025 // CHECK9-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 7026 // CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 7027 // CHECK9-NEXT: [[I7:%.*]] = alloca i32, align 4 7028 // CHECK9-NEXT: [[K8:%.*]] = alloca i64, align 8 7029 // CHECK9-NEXT: [[LIN:%.*]] = alloca i32, align 4 7030 // CHECK9-NEXT: [[_TMP20:%.*]] = alloca i64, align 8 7031 // CHECK9-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 7032 // CHECK9-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 7033 // CHECK9-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 7034 // CHECK9-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 7035 // CHECK9-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 7036 // CHECK9-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 7037 // CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8 7038 // CHECK9-NEXT: [[LIN27:%.*]] = alloca i32, align 4 7039 // CHECK9-NEXT: [[A28:%.*]] = alloca i32, align 4 7040 // CHECK9-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 7041 // CHECK9-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 7042 // CHECK9-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 7043 // CHECK9-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 7044 // CHECK9-NEXT: [[IT53:%.*]] = alloca i16, align 2 7045 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 7046 // CHECK9-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 7047 // CHECK9-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 7048 // CHECK9-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 7049 // CHECK9-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 7050 // CHECK9-NEXT: [[IT72:%.*]] = alloca i8, align 1 7051 // CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7052 // CHECK9-NEXT: store i32 0, ptr [[A]], align 4 7053 // CHECK9-NEXT: store i16 0, ptr [[AA]], align 2 7054 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 7055 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 7056 // CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0() 7057 // CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 7058 // CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 7059 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 7060 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 7061 // CHECK9-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 7062 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 7063 // CHECK9-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 7064 // CHECK9-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 7065 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 7066 // CHECK9-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 7067 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 7068 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 7069 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7070 // CHECK9: omp.inner.for.cond: 7071 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 7072 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 7073 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 7074 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7075 // CHECK9: omp.inner.for.body: 7076 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 7077 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5 7078 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 7079 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 7080 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7081 // CHECK9: omp.body.continue: 7082 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7083 // CHECK9: omp.inner.for.inc: 7084 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 7085 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 7086 // CHECK9-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 7087 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 7088 // CHECK9: omp.inner.for.end: 7089 // CHECK9-NEXT: store i32 33, ptr [[I]], align 4 7090 // CHECK9-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 7091 // CHECK9-NEXT: store i64 [[CALL]], ptr [[K]], align 8 7092 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 4 7093 // CHECK9-NEXT: store i32 8, ptr [[DOTOMP_UB5]], align 4 7094 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 4 7095 // CHECK9-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV6]], align 4 7096 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[K]], align 8 7097 // CHECK9-NEXT: store i64 [[TMP12]], ptr [[DOTLINEAR_START]], align 8 7098 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 7099 // CHECK9: omp.inner.for.cond9: 7100 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 7101 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP6]] 7102 // CHECK9-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 7103 // CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 7104 // CHECK9: omp.inner.for.body11: 7105 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 7106 // CHECK9-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1 7107 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 7108 // CHECK9-NEXT: store i32 [[SUB]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP6]] 7109 // CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP6]] 7110 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 7111 // CHECK9-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3 7112 // CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 7113 // CHECK9-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]] 7114 // CHECK9-NEXT: store i64 [[ADD14]], ptr [[K8]], align 8, !llvm.access.group [[ACC_GRP6]] 7115 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP6]] 7116 // CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 7117 // CHECK9-NEXT: store i32 [[ADD15]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP6]] 7118 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 7119 // CHECK9: omp.body.continue16: 7120 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 7121 // CHECK9: omp.inner.for.inc17: 7122 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 7123 // CHECK9-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 7124 // CHECK9-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 7125 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] 7126 // CHECK9: omp.inner.for.end19: 7127 // CHECK9-NEXT: store i32 1, ptr [[I7]], align 4 7128 // CHECK9-NEXT: [[TMP20:%.*]] = load i64, ptr [[K8]], align 8 7129 // CHECK9-NEXT: store i64 [[TMP20]], ptr [[K]], align 8 7130 // CHECK9-NEXT: store i32 12, ptr [[LIN]], align 4 7131 // CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB21]], align 8 7132 // CHECK9-NEXT: store i64 3, ptr [[DOTOMP_UB22]], align 8 7133 // CHECK9-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB21]], align 8 7134 // CHECK9-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV23]], align 8 7135 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN]], align 4 7136 // CHECK9-NEXT: store i32 [[TMP22]], ptr [[DOTLINEAR_START24]], align 4 7137 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[A]], align 4 7138 // CHECK9-NEXT: store i32 [[TMP23]], ptr [[DOTLINEAR_START25]], align 4 7139 // CHECK9-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 7140 // CHECK9-NEXT: store i64 [[CALL26]], ptr [[DOTLINEAR_STEP]], align 8 7141 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 7142 // CHECK9: omp.inner.for.cond29: 7143 // CHECK9-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9:![0-9]+]] 7144 // CHECK9-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP9]] 7145 // CHECK9-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]] 7146 // CHECK9-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 7147 // CHECK9: omp.inner.for.body31: 7148 // CHECK9-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7149 // CHECK9-NEXT: [[MUL32:%.*]] = mul i64 [[TMP26]], 400 7150 // CHECK9-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 7151 // CHECK9-NEXT: store i64 [[SUB33]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP9]] 7152 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP9]] 7153 // CHECK9-NEXT: [[CONV34:%.*]] = sext i32 [[TMP27]] to i64 7154 // CHECK9-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7155 // CHECK9-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]] 7156 // CHECK9-NEXT: [[MUL35:%.*]] = mul i64 [[TMP28]], [[TMP29]] 7157 // CHECK9-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 7158 // CHECK9-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 7159 // CHECK9-NEXT: store i32 [[CONV37]], ptr [[LIN27]], align 4, !llvm.access.group [[ACC_GRP9]] 7160 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP9]] 7161 // CHECK9-NEXT: [[CONV38:%.*]] = sext i32 [[TMP30]] to i64 7162 // CHECK9-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7163 // CHECK9-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]] 7164 // CHECK9-NEXT: [[MUL39:%.*]] = mul i64 [[TMP31]], [[TMP32]] 7165 // CHECK9-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 7166 // CHECK9-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 7167 // CHECK9-NEXT: store i32 [[CONV41]], ptr [[A28]], align 4, !llvm.access.group [[ACC_GRP9]] 7168 // CHECK9-NEXT: [[TMP33:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]] 7169 // CHECK9-NEXT: [[CONV42:%.*]] = sext i16 [[TMP33]] to i32 7170 // CHECK9-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 7171 // CHECK9-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 7172 // CHECK9-NEXT: store i16 [[CONV44]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]] 7173 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 7174 // CHECK9: omp.body.continue45: 7175 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 7176 // CHECK9: omp.inner.for.inc46: 7177 // CHECK9-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7178 // CHECK9-NEXT: [[ADD47:%.*]] = add i64 [[TMP34]], 1 7179 // CHECK9-NEXT: store i64 [[ADD47]], ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7180 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP10:![0-9]+]] 7181 // CHECK9: omp.inner.for.end48: 7182 // CHECK9-NEXT: store i64 400, ptr [[IT]], align 8 7183 // CHECK9-NEXT: [[TMP35:%.*]] = load i32, ptr [[LIN27]], align 4 7184 // CHECK9-NEXT: store i32 [[TMP35]], ptr [[LIN]], align 4 7185 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[A28]], align 4 7186 // CHECK9-NEXT: store i32 [[TMP36]], ptr [[A]], align 4 7187 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB50]], align 4 7188 // CHECK9-NEXT: store i32 3, ptr [[DOTOMP_UB51]], align 4 7189 // CHECK9-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_LB50]], align 4 7190 // CHECK9-NEXT: store i32 [[TMP37]], ptr [[DOTOMP_IV52]], align 4 7191 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 7192 // CHECK9: omp.inner.for.cond54: 7193 // CHECK9-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 7194 // CHECK9-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP12]] 7195 // CHECK9-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]] 7196 // CHECK9-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 7197 // CHECK9: omp.inner.for.body56: 7198 // CHECK9-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 7199 // CHECK9-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP40]], 4 7200 // CHECK9-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 7201 // CHECK9-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 7202 // CHECK9-NEXT: store i16 [[CONV59]], ptr [[IT53]], align 2, !llvm.access.group [[ACC_GRP12]] 7203 // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]] 7204 // CHECK9-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP41]], 1 7205 // CHECK9-NEXT: store i32 [[ADD60]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]] 7206 // CHECK9-NEXT: [[TMP42:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]] 7207 // CHECK9-NEXT: [[CONV61:%.*]] = sext i16 [[TMP42]] to i32 7208 // CHECK9-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 7209 // CHECK9-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 7210 // CHECK9-NEXT: store i16 [[CONV63]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]] 7211 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 7212 // CHECK9: omp.body.continue64: 7213 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 7214 // CHECK9: omp.inner.for.inc65: 7215 // CHECK9-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 7216 // CHECK9-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP43]], 1 7217 // CHECK9-NEXT: store i32 [[ADD66]], ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 7218 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP13:![0-9]+]] 7219 // CHECK9: omp.inner.for.end67: 7220 // CHECK9-NEXT: store i16 22, ptr [[IT53]], align 2 7221 // CHECK9-NEXT: [[TMP44:%.*]] = load i32, ptr [[A]], align 4 7222 // CHECK9-NEXT: store i32 [[TMP44]], ptr [[DOTCAPTURE_EXPR_]], align 4 7223 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB69]], align 4 7224 // CHECK9-NEXT: store i32 25, ptr [[DOTOMP_UB70]], align 4 7225 // CHECK9-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_LB69]], align 4 7226 // CHECK9-NEXT: store i32 [[TMP45]], ptr [[DOTOMP_IV71]], align 4 7227 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 7228 // CHECK9: omp.inner.for.cond73: 7229 // CHECK9-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] 7230 // CHECK9-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP15]] 7231 // CHECK9-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]] 7232 // CHECK9-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 7233 // CHECK9: omp.inner.for.body75: 7234 // CHECK9-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 7235 // CHECK9-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP48]], 1 7236 // CHECK9-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 7237 // CHECK9-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 7238 // CHECK9-NEXT: store i8 [[CONV78]], ptr [[IT72]], align 1, !llvm.access.group [[ACC_GRP15]] 7239 // CHECK9-NEXT: [[TMP49:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]] 7240 // CHECK9-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP49]], 1 7241 // CHECK9-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]] 7242 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 2 7243 // CHECK9-NEXT: [[TMP50:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] 7244 // CHECK9-NEXT: [[CONV80:%.*]] = fpext float [[TMP50]] to double 7245 // CHECK9-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 7246 // CHECK9-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 7247 // CHECK9-NEXT: store float [[CONV82]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] 7248 // CHECK9-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 3 7249 // CHECK9-NEXT: [[TMP51:%.*]] = load float, ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]] 7250 // CHECK9-NEXT: [[CONV84:%.*]] = fpext float [[TMP51]] to double 7251 // CHECK9-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 7252 // CHECK9-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 7253 // CHECK9-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]] 7254 // CHECK9-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 1 7255 // CHECK9-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i64 0, i64 2 7256 // CHECK9-NEXT: [[TMP52:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] 7257 // CHECK9-NEXT: [[ADD89:%.*]] = fadd double [[TMP52]], 1.000000e+00 7258 // CHECK9-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] 7259 // CHECK9-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP4]] 7260 // CHECK9-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP53]] 7261 // CHECK9-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX90]], i64 3 7262 // CHECK9-NEXT: [[TMP54:%.*]] = load double, ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]] 7263 // CHECK9-NEXT: [[ADD92:%.*]] = fadd double [[TMP54]], 1.000000e+00 7264 // CHECK9-NEXT: store double [[ADD92]], ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]] 7265 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 7266 // CHECK9-NEXT: [[TMP55:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]] 7267 // CHECK9-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP55]], 1 7268 // CHECK9-NEXT: store i64 [[ADD93]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]] 7269 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 7270 // CHECK9-NEXT: [[TMP56:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]] 7271 // CHECK9-NEXT: [[CONV94:%.*]] = sext i8 [[TMP56]] to i32 7272 // CHECK9-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 7273 // CHECK9-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 7274 // CHECK9-NEXT: store i8 [[CONV96]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]] 7275 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 7276 // CHECK9: omp.body.continue97: 7277 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 7278 // CHECK9: omp.inner.for.inc98: 7279 // CHECK9-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 7280 // CHECK9-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 1 7281 // CHECK9-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 7282 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]] 7283 // CHECK9: omp.inner.for.end100: 7284 // CHECK9-NEXT: store i8 96, ptr [[IT72]], align 1 7285 // CHECK9-NEXT: [[TMP58:%.*]] = load i32, ptr [[A]], align 4 7286 // CHECK9-NEXT: [[TMP59:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 7287 // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP59]]) 7288 // CHECK9-NEXT: ret i32 [[TMP58]] 7289 // 7290 // 7291 // CHECK9-LABEL: define {{[^@]+}}@_Z3bari 7292 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7293 // CHECK9-NEXT: entry: 7294 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7295 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7296 // CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 7297 // CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7298 // CHECK9-NEXT: store i32 0, ptr [[A]], align 4 7299 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 7300 // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 7301 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 7302 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 7303 // CHECK9-NEXT: store i32 [[ADD]], ptr [[A]], align 4 7304 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 7305 // CHECK9-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 7306 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 7307 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 7308 // CHECK9-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 7309 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 7310 // CHECK9-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 7311 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 7312 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 7313 // CHECK9-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 7314 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 7315 // CHECK9-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 7316 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 7317 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 7318 // CHECK9-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 7319 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 7320 // CHECK9-NEXT: ret i32 [[TMP8]] 7321 // 7322 // 7323 // CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 7324 // CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 7325 // CHECK9-NEXT: entry: 7326 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7327 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7328 // CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 7329 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 7330 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7331 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 7332 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7333 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7334 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7335 // CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8 7336 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7337 // CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7338 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7339 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 7340 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7341 // CHECK9-NEXT: store i32 [[ADD]], ptr [[B]], align 4 7342 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 7343 // CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 7344 // CHECK9-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0() 7345 // CHECK9-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 7346 // CHECK9-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 7347 // CHECK9-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 7348 // CHECK9-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 7349 // CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 7350 // CHECK9-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 7351 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 7352 // CHECK9-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 7353 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7354 // CHECK9: omp.inner.for.cond: 7355 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]] 7356 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]] 7357 // CHECK9-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP6]], [[TMP7]] 7358 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7359 // CHECK9: omp.inner.for.body: 7360 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 7361 // CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP8]], 400 7362 // CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 7363 // CHECK9-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP18]] 7364 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP18]] 7365 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double 7366 // CHECK9-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 7367 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 7368 // CHECK9-NEXT: store double [[ADD2]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP18]] 7369 // CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 7370 // CHECK9-NEXT: [[TMP10:%.*]] = load double, ptr [[A3]], align 8, !llvm.access.group [[ACC_GRP18]] 7371 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00 7372 // CHECK9-NEXT: store double [[INC]], ptr [[A3]], align 8, !llvm.access.group [[ACC_GRP18]] 7373 // CHECK9-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 7374 // CHECK9-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]] 7375 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP11]] 7376 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 7377 // CHECK9-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2, !llvm.access.group [[ACC_GRP18]] 7378 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7379 // CHECK9: omp.body.continue: 7380 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7381 // CHECK9: omp.inner.for.inc: 7382 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 7383 // CHECK9-NEXT: [[ADD6:%.*]] = add i64 [[TMP12]], 1 7384 // CHECK9-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 7385 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 7386 // CHECK9: omp.inner.for.end: 7387 // CHECK9-NEXT: store i64 400, ptr [[IT]], align 8 7388 // CHECK9-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] 7389 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP13]] 7390 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX7]], i64 1 7391 // CHECK9-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX8]], align 2 7392 // CHECK9-NEXT: [[CONV9:%.*]] = sext i16 [[TMP14]] to i32 7393 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4 7394 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP15]] 7395 // CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 7396 // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP16]]) 7397 // CHECK9-NEXT: ret i32 [[ADD10]] 7398 // 7399 // 7400 // CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici 7401 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7402 // CHECK9-NEXT: entry: 7403 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7404 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7405 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 7406 // CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 1 7407 // CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7408 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 7409 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7410 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7411 // CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7412 // CHECK9-NEXT: store i32 0, ptr [[A]], align 4 7413 // CHECK9-NEXT: store i16 0, ptr [[AA]], align 2 7414 // CHECK9-NEXT: store i8 0, ptr [[AAA]], align 1 7415 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 7416 // CHECK9-NEXT: store i32 429496720, ptr [[DOTOMP_UB]], align 4 7417 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 7418 // CHECK9-NEXT: ret i32 [[TMP0]] 7419 // 7420 // 7421 // CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 7422 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 7423 // CHECK9-NEXT: entry: 7424 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7425 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7426 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 7427 // CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7428 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 7429 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7430 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7431 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7432 // CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8 7433 // CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7434 // CHECK9-NEXT: store i32 0, ptr [[A]], align 4 7435 // CHECK9-NEXT: store i16 0, ptr [[AA]], align 2 7436 // CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 7437 // CHECK9-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 7438 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 7439 // CHECK9-NEXT: store i64 [[TMP0]], ptr [[DOTOMP_IV]], align 8 7440 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7441 // CHECK9: omp.inner.for.cond: 7442 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21:![0-9]+]] 7443 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP21]] 7444 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 7445 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7446 // CHECK9: omp.inner.for.body: 7447 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21]] 7448 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 7449 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 7450 // CHECK9-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP21]] 7451 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP21]] 7452 // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 7453 // CHECK9-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP21]] 7454 // CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP21]] 7455 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 7456 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 7457 // CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 7458 // CHECK9-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP21]] 7459 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 7460 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] 7461 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 7462 // CHECK9-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] 7463 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7464 // CHECK9: omp.body.continue: 7465 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7466 // CHECK9: omp.inner.for.inc: 7467 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21]] 7468 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 7469 // CHECK9-NEXT: store i64 [[ADD5]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21]] 7470 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 7471 // CHECK9: omp.inner.for.end: 7472 // CHECK9-NEXT: store i64 11, ptr [[I]], align 8 7473 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 7474 // CHECK9-NEXT: ret i32 [[TMP8]] 7475 // 7476 // 7477 // CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv 7478 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 7479 // CHECK11-NEXT: entry: 7480 // CHECK11-NEXT: ret i64 0 7481 // 7482 // 7483 // CHECK11-LABEL: define {{[^@]+}}@_Z3fooi 7484 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 7485 // CHECK11-NEXT: entry: 7486 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7487 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 7488 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 7489 // CHECK11-NEXT: [[B:%.*]] = alloca [10 x float], align 4 7490 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 7491 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 7492 // CHECK11-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 7493 // CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 7494 // CHECK11-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 7495 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 7496 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7497 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7498 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7499 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 7500 // CHECK11-NEXT: [[K:%.*]] = alloca i64, align 8 7501 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 7502 // CHECK11-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 7503 // CHECK11-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 7504 // CHECK11-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 7505 // CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 7506 // CHECK11-NEXT: [[I7:%.*]] = alloca i32, align 4 7507 // CHECK11-NEXT: [[K8:%.*]] = alloca i64, align 8 7508 // CHECK11-NEXT: [[LIN:%.*]] = alloca i32, align 4 7509 // CHECK11-NEXT: [[_TMP20:%.*]] = alloca i64, align 4 7510 // CHECK11-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 7511 // CHECK11-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 7512 // CHECK11-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 7513 // CHECK11-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 7514 // CHECK11-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 7515 // CHECK11-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 7516 // CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8 7517 // CHECK11-NEXT: [[LIN27:%.*]] = alloca i32, align 4 7518 // CHECK11-NEXT: [[A28:%.*]] = alloca i32, align 4 7519 // CHECK11-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 7520 // CHECK11-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 7521 // CHECK11-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 7522 // CHECK11-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 7523 // CHECK11-NEXT: [[IT53:%.*]] = alloca i16, align 2 7524 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 7525 // CHECK11-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 7526 // CHECK11-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 7527 // CHECK11-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 7528 // CHECK11-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 7529 // CHECK11-NEXT: [[IT72:%.*]] = alloca i8, align 1 7530 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7531 // CHECK11-NEXT: store i32 0, ptr [[A]], align 4 7532 // CHECK11-NEXT: store i16 0, ptr [[AA]], align 2 7533 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 7534 // CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0() 7535 // CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 7536 // CHECK11-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 7537 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 7538 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 7539 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 7540 // CHECK11-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 7541 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 7542 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 7543 // CHECK11-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 7544 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 7545 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 7546 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7547 // CHECK11: omp.inner.for.cond: 7548 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 7549 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 7550 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 7551 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7552 // CHECK11: omp.inner.for.body: 7553 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 7554 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 7555 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 7556 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 7557 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7558 // CHECK11: omp.body.continue: 7559 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7560 // CHECK11: omp.inner.for.inc: 7561 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 7562 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 7563 // CHECK11-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 7564 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 7565 // CHECK11: omp.inner.for.end: 7566 // CHECK11-NEXT: store i32 33, ptr [[I]], align 4 7567 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 7568 // CHECK11-NEXT: store i64 [[CALL]], ptr [[K]], align 8 7569 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 4 7570 // CHECK11-NEXT: store i32 8, ptr [[DOTOMP_UB5]], align 4 7571 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 4 7572 // CHECK11-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV6]], align 4 7573 // CHECK11-NEXT: [[TMP10:%.*]] = load i64, ptr [[K]], align 8 7574 // CHECK11-NEXT: store i64 [[TMP10]], ptr [[DOTLINEAR_START]], align 8 7575 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 7576 // CHECK11: omp.inner.for.cond9: 7577 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 7578 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP7]] 7579 // CHECK11-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 7580 // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 7581 // CHECK11: omp.inner.for.body11: 7582 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 7583 // CHECK11-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1 7584 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 7585 // CHECK11-NEXT: store i32 [[SUB]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] 7586 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP7]] 7587 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 7588 // CHECK11-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3 7589 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 7590 // CHECK11-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]] 7591 // CHECK11-NEXT: store i64 [[ADD14]], ptr [[K8]], align 8, !llvm.access.group [[ACC_GRP7]] 7592 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP7]] 7593 // CHECK11-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 7594 // CHECK11-NEXT: store i32 [[ADD15]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP7]] 7595 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 7596 // CHECK11: omp.body.continue16: 7597 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 7598 // CHECK11: omp.inner.for.inc17: 7599 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 7600 // CHECK11-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 7601 // CHECK11-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 7602 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]] 7603 // CHECK11: omp.inner.for.end19: 7604 // CHECK11-NEXT: store i32 1, ptr [[I7]], align 4 7605 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, ptr [[K8]], align 8 7606 // CHECK11-NEXT: store i64 [[TMP18]], ptr [[K]], align 8 7607 // CHECK11-NEXT: store i32 12, ptr [[LIN]], align 4 7608 // CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB21]], align 8 7609 // CHECK11-NEXT: store i64 3, ptr [[DOTOMP_UB22]], align 8 7610 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_LB21]], align 8 7611 // CHECK11-NEXT: store i64 [[TMP19]], ptr [[DOTOMP_IV23]], align 8 7612 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN]], align 4 7613 // CHECK11-NEXT: store i32 [[TMP20]], ptr [[DOTLINEAR_START24]], align 4 7614 // CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 4 7615 // CHECK11-NEXT: store i32 [[TMP21]], ptr [[DOTLINEAR_START25]], align 4 7616 // CHECK11-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 7617 // CHECK11-NEXT: store i64 [[CALL26]], ptr [[DOTLINEAR_STEP]], align 8 7618 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 7619 // CHECK11: omp.inner.for.cond29: 7620 // CHECK11-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10:![0-9]+]] 7621 // CHECK11-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP10]] 7622 // CHECK11-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 7623 // CHECK11-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 7624 // CHECK11: omp.inner.for.body31: 7625 // CHECK11-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7626 // CHECK11-NEXT: [[MUL32:%.*]] = mul i64 [[TMP24]], 400 7627 // CHECK11-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 7628 // CHECK11-NEXT: store i64 [[SUB33]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP10]] 7629 // CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP10]] 7630 // CHECK11-NEXT: [[CONV34:%.*]] = sext i32 [[TMP25]] to i64 7631 // CHECK11-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7632 // CHECK11-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]] 7633 // CHECK11-NEXT: [[MUL35:%.*]] = mul i64 [[TMP26]], [[TMP27]] 7634 // CHECK11-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 7635 // CHECK11-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 7636 // CHECK11-NEXT: store i32 [[CONV37]], ptr [[LIN27]], align 4, !llvm.access.group [[ACC_GRP10]] 7637 // CHECK11-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP10]] 7638 // CHECK11-NEXT: [[CONV38:%.*]] = sext i32 [[TMP28]] to i64 7639 // CHECK11-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7640 // CHECK11-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]] 7641 // CHECK11-NEXT: [[MUL39:%.*]] = mul i64 [[TMP29]], [[TMP30]] 7642 // CHECK11-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 7643 // CHECK11-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 7644 // CHECK11-NEXT: store i32 [[CONV41]], ptr [[A28]], align 4, !llvm.access.group [[ACC_GRP10]] 7645 // CHECK11-NEXT: [[TMP31:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]] 7646 // CHECK11-NEXT: [[CONV42:%.*]] = sext i16 [[TMP31]] to i32 7647 // CHECK11-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 7648 // CHECK11-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 7649 // CHECK11-NEXT: store i16 [[CONV44]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]] 7650 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 7651 // CHECK11: omp.body.continue45: 7652 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 7653 // CHECK11: omp.inner.for.inc46: 7654 // CHECK11-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7655 // CHECK11-NEXT: [[ADD47:%.*]] = add i64 [[TMP32]], 1 7656 // CHECK11-NEXT: store i64 [[ADD47]], ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7657 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP11:![0-9]+]] 7658 // CHECK11: omp.inner.for.end48: 7659 // CHECK11-NEXT: store i64 400, ptr [[IT]], align 8 7660 // CHECK11-NEXT: [[TMP33:%.*]] = load i32, ptr [[LIN27]], align 4 7661 // CHECK11-NEXT: store i32 [[TMP33]], ptr [[LIN]], align 4 7662 // CHECK11-NEXT: [[TMP34:%.*]] = load i32, ptr [[A28]], align 4 7663 // CHECK11-NEXT: store i32 [[TMP34]], ptr [[A]], align 4 7664 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB50]], align 4 7665 // CHECK11-NEXT: store i32 3, ptr [[DOTOMP_UB51]], align 4 7666 // CHECK11-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_LB50]], align 4 7667 // CHECK11-NEXT: store i32 [[TMP35]], ptr [[DOTOMP_IV52]], align 4 7668 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 7669 // CHECK11: omp.inner.for.cond54: 7670 // CHECK11-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] 7671 // CHECK11-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP13]] 7672 // CHECK11-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP36]], [[TMP37]] 7673 // CHECK11-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 7674 // CHECK11: omp.inner.for.body56: 7675 // CHECK11-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 7676 // CHECK11-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP38]], 4 7677 // CHECK11-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 7678 // CHECK11-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 7679 // CHECK11-NEXT: store i16 [[CONV59]], ptr [[IT53]], align 2, !llvm.access.group [[ACC_GRP13]] 7680 // CHECK11-NEXT: [[TMP39:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]] 7681 // CHECK11-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP39]], 1 7682 // CHECK11-NEXT: store i32 [[ADD60]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]] 7683 // CHECK11-NEXT: [[TMP40:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]] 7684 // CHECK11-NEXT: [[CONV61:%.*]] = sext i16 [[TMP40]] to i32 7685 // CHECK11-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 7686 // CHECK11-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 7687 // CHECK11-NEXT: store i16 [[CONV63]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]] 7688 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 7689 // CHECK11: omp.body.continue64: 7690 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 7691 // CHECK11: omp.inner.for.inc65: 7692 // CHECK11-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 7693 // CHECK11-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP41]], 1 7694 // CHECK11-NEXT: store i32 [[ADD66]], ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 7695 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP14:![0-9]+]] 7696 // CHECK11: omp.inner.for.end67: 7697 // CHECK11-NEXT: store i16 22, ptr [[IT53]], align 2 7698 // CHECK11-NEXT: [[TMP42:%.*]] = load i32, ptr [[A]], align 4 7699 // CHECK11-NEXT: store i32 [[TMP42]], ptr [[DOTCAPTURE_EXPR_]], align 4 7700 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB69]], align 4 7701 // CHECK11-NEXT: store i32 25, ptr [[DOTOMP_UB70]], align 4 7702 // CHECK11-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_LB69]], align 4 7703 // CHECK11-NEXT: store i32 [[TMP43]], ptr [[DOTOMP_IV71]], align 4 7704 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 7705 // CHECK11: omp.inner.for.cond73: 7706 // CHECK11-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] 7707 // CHECK11-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP16]] 7708 // CHECK11-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP44]], [[TMP45]] 7709 // CHECK11-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 7710 // CHECK11: omp.inner.for.body75: 7711 // CHECK11-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 7712 // CHECK11-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP46]], 1 7713 // CHECK11-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 7714 // CHECK11-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 7715 // CHECK11-NEXT: store i8 [[CONV78]], ptr [[IT72]], align 1, !llvm.access.group [[ACC_GRP16]] 7716 // CHECK11-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] 7717 // CHECK11-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP47]], 1 7718 // CHECK11-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] 7719 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 2 7720 // CHECK11-NEXT: [[TMP48:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] 7721 // CHECK11-NEXT: [[CONV80:%.*]] = fpext float [[TMP48]] to double 7722 // CHECK11-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 7723 // CHECK11-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 7724 // CHECK11-NEXT: store float [[CONV82]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] 7725 // CHECK11-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 3 7726 // CHECK11-NEXT: [[TMP49:%.*]] = load float, ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]] 7727 // CHECK11-NEXT: [[CONV84:%.*]] = fpext float [[TMP49]] to double 7728 // CHECK11-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 7729 // CHECK11-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 7730 // CHECK11-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]] 7731 // CHECK11-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 1 7732 // CHECK11-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i32 0, i32 2 7733 // CHECK11-NEXT: [[TMP50:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] 7734 // CHECK11-NEXT: [[ADD89:%.*]] = fadd double [[TMP50]], 1.000000e+00 7735 // CHECK11-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] 7736 // CHECK11-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP2]] 7737 // CHECK11-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP51]] 7738 // CHECK11-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX90]], i32 3 7739 // CHECK11-NEXT: [[TMP52:%.*]] = load double, ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]] 7740 // CHECK11-NEXT: [[ADD92:%.*]] = fadd double [[TMP52]], 1.000000e+00 7741 // CHECK11-NEXT: store double [[ADD92]], ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]] 7742 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 7743 // CHECK11-NEXT: [[TMP53:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]] 7744 // CHECK11-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP53]], 1 7745 // CHECK11-NEXT: store i64 [[ADD93]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]] 7746 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 7747 // CHECK11-NEXT: [[TMP54:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]] 7748 // CHECK11-NEXT: [[CONV94:%.*]] = sext i8 [[TMP54]] to i32 7749 // CHECK11-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 7750 // CHECK11-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 7751 // CHECK11-NEXT: store i8 [[CONV96]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]] 7752 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 7753 // CHECK11: omp.body.continue97: 7754 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 7755 // CHECK11: omp.inner.for.inc98: 7756 // CHECK11-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 7757 // CHECK11-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 1 7758 // CHECK11-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 7759 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]] 7760 // CHECK11: omp.inner.for.end100: 7761 // CHECK11-NEXT: store i8 96, ptr [[IT72]], align 1 7762 // CHECK11-NEXT: [[TMP56:%.*]] = load i32, ptr [[A]], align 4 7763 // CHECK11-NEXT: [[TMP57:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 7764 // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP57]]) 7765 // CHECK11-NEXT: ret i32 [[TMP56]] 7766 // 7767 // 7768 // CHECK11-LABEL: define {{[^@]+}}@_Z3bari 7769 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 7770 // CHECK11-NEXT: entry: 7771 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7772 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 7773 // CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 7774 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7775 // CHECK11-NEXT: store i32 0, ptr [[A]], align 4 7776 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 7777 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 7778 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 7779 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 7780 // CHECK11-NEXT: store i32 [[ADD]], ptr [[A]], align 4 7781 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 7782 // CHECK11-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 7783 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 7784 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 7785 // CHECK11-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 7786 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 7787 // CHECK11-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 7788 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 7789 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 7790 // CHECK11-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 7791 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 7792 // CHECK11-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 7793 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 7794 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 7795 // CHECK11-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 7796 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 7797 // CHECK11-NEXT: ret i32 [[TMP8]] 7798 // 7799 // 7800 // CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 7801 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 7802 // CHECK11-NEXT: entry: 7803 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 7804 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7805 // CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 7806 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 7807 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 7808 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4 7809 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7810 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7811 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7812 // CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8 7813 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 7814 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7815 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 7816 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 7817 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7818 // CHECK11-NEXT: store i32 [[ADD]], ptr [[B]], align 4 7819 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 7820 // CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0() 7821 // CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 7822 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 7823 // CHECK11-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 7824 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 7825 // CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 7826 // CHECK11-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 7827 // CHECK11-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 7828 // CHECK11-NEXT: store i64 [[TMP4]], ptr [[DOTOMP_IV]], align 8 7829 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7830 // CHECK11: omp.inner.for.cond: 7831 // CHECK11-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19:![0-9]+]] 7832 // CHECK11-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP19]] 7833 // CHECK11-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP5]], [[TMP6]] 7834 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7835 // CHECK11: omp.inner.for.body: 7836 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 7837 // CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP7]], 400 7838 // CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 7839 // CHECK11-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP19]] 7840 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP19]] 7841 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double 7842 // CHECK11-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 7843 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 7844 // CHECK11-NEXT: store double [[ADD2]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP19]] 7845 // CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 7846 // CHECK11-NEXT: [[TMP9:%.*]] = load double, ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP19]] 7847 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 7848 // CHECK11-NEXT: store double [[INC]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP19]] 7849 // CHECK11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 7850 // CHECK11-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]] 7851 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP10]] 7852 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 7853 // CHECK11-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2, !llvm.access.group [[ACC_GRP19]] 7854 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7855 // CHECK11: omp.body.continue: 7856 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7857 // CHECK11: omp.inner.for.inc: 7858 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 7859 // CHECK11-NEXT: [[ADD6:%.*]] = add i64 [[TMP11]], 1 7860 // CHECK11-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 7861 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 7862 // CHECK11: omp.inner.for.end: 7863 // CHECK11-NEXT: store i64 400, ptr [[IT]], align 8 7864 // CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] 7865 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP12]] 7866 // CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX7]], i32 1 7867 // CHECK11-NEXT: [[TMP13:%.*]] = load i16, ptr [[ARRAYIDX8]], align 2 7868 // CHECK11-NEXT: [[CONV9:%.*]] = sext i16 [[TMP13]] to i32 7869 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[B]], align 4 7870 // CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP14]] 7871 // CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 7872 // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]]) 7873 // CHECK11-NEXT: ret i32 [[ADD10]] 7874 // 7875 // 7876 // CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici 7877 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 7878 // CHECK11-NEXT: entry: 7879 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7880 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 7881 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 7882 // CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 1 7883 // CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7884 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 7885 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7886 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7887 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7888 // CHECK11-NEXT: store i32 0, ptr [[A]], align 4 7889 // CHECK11-NEXT: store i16 0, ptr [[AA]], align 2 7890 // CHECK11-NEXT: store i8 0, ptr [[AAA]], align 1 7891 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 7892 // CHECK11-NEXT: store i32 429496720, ptr [[DOTOMP_UB]], align 4 7893 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 7894 // CHECK11-NEXT: ret i32 [[TMP0]] 7895 // 7896 // 7897 // CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 7898 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 7899 // CHECK11-NEXT: entry: 7900 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7901 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 7902 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 7903 // CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7904 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4 7905 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7906 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7907 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7908 // CHECK11-NEXT: [[I:%.*]] = alloca i64, align 8 7909 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7910 // CHECK11-NEXT: store i32 0, ptr [[A]], align 4 7911 // CHECK11-NEXT: store i16 0, ptr [[AA]], align 2 7912 // CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 7913 // CHECK11-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 7914 // CHECK11-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 7915 // CHECK11-NEXT: store i64 [[TMP0]], ptr [[DOTOMP_IV]], align 8 7916 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7917 // CHECK11: omp.inner.for.cond: 7918 // CHECK11-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22:![0-9]+]] 7919 // CHECK11-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP22]] 7920 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 7921 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7922 // CHECK11: omp.inner.for.body: 7923 // CHECK11-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22]] 7924 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 7925 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 7926 // CHECK11-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP22]] 7927 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP22]] 7928 // CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 7929 // CHECK11-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP22]] 7930 // CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP22]] 7931 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 7932 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 7933 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 7934 // CHECK11-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP22]] 7935 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 7936 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] 7937 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 7938 // CHECK11-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] 7939 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7940 // CHECK11: omp.body.continue: 7941 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7942 // CHECK11: omp.inner.for.inc: 7943 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22]] 7944 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 7945 // CHECK11-NEXT: store i64 [[ADD5]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22]] 7946 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] 7947 // CHECK11: omp.inner.for.end: 7948 // CHECK11-NEXT: store i64 11, ptr [[I]], align 8 7949 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 7950 // CHECK11-NEXT: ret i32 [[TMP8]] 7951 // 7952 // 7953 // CHECK13-LABEL: define {{[^@]+}}@_Z7get_valv 7954 // CHECK13-SAME: () #[[ATTR0:[0-9]+]] { 7955 // CHECK13-NEXT: entry: 7956 // CHECK13-NEXT: ret i64 0 7957 // 7958 // 7959 // CHECK13-LABEL: define {{[^@]+}}@_Z3fooi 7960 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7961 // CHECK13-NEXT: entry: 7962 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7963 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 7964 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 7965 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x float], align 4 7966 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 7967 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7968 // CHECK13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 7969 // CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 7970 // CHECK13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 7971 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 7972 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7973 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7974 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7975 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 7976 // CHECK13-NEXT: [[K:%.*]] = alloca i64, align 8 7977 // CHECK13-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 7978 // CHECK13-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 7979 // CHECK13-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 7980 // CHECK13-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 7981 // CHECK13-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 7982 // CHECK13-NEXT: [[I7:%.*]] = alloca i32, align 4 7983 // CHECK13-NEXT: [[K8:%.*]] = alloca i64, align 8 7984 // CHECK13-NEXT: [[LIN:%.*]] = alloca i32, align 4 7985 // CHECK13-NEXT: [[_TMP20:%.*]] = alloca i64, align 8 7986 // CHECK13-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 7987 // CHECK13-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 7988 // CHECK13-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 7989 // CHECK13-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 7990 // CHECK13-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 7991 // CHECK13-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 7992 // CHECK13-NEXT: [[IT:%.*]] = alloca i64, align 8 7993 // CHECK13-NEXT: [[LIN27:%.*]] = alloca i32, align 4 7994 // CHECK13-NEXT: [[A28:%.*]] = alloca i32, align 4 7995 // CHECK13-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 7996 // CHECK13-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 7997 // CHECK13-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 7998 // CHECK13-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 7999 // CHECK13-NEXT: [[IT53:%.*]] = alloca i16, align 2 8000 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 8001 // CHECK13-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 8002 // CHECK13-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 8003 // CHECK13-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 8004 // CHECK13-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 8005 // CHECK13-NEXT: [[IT72:%.*]] = alloca i8, align 1 8006 // CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8007 // CHECK13-NEXT: store i32 0, ptr [[A]], align 4 8008 // CHECK13-NEXT: store i16 0, ptr [[AA]], align 2 8009 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 8010 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 8011 // CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0() 8012 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 8013 // CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 8014 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 8015 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 8016 // CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 8017 // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 8018 // CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 8019 // CHECK13-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 8020 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 8021 // CHECK13-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 8022 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 8023 // CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 8024 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8025 // CHECK13: omp.inner.for.cond: 8026 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 8027 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 8028 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 8029 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8030 // CHECK13: omp.inner.for.body: 8031 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 8032 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5 8033 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 8034 // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 8035 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8036 // CHECK13: omp.body.continue: 8037 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8038 // CHECK13: omp.inner.for.inc: 8039 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 8040 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 8041 // CHECK13-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 8042 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 8043 // CHECK13: omp.inner.for.end: 8044 // CHECK13-NEXT: store i32 33, ptr [[I]], align 4 8045 // CHECK13-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 8046 // CHECK13-NEXT: store i64 [[CALL]], ptr [[K]], align 8 8047 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 4 8048 // CHECK13-NEXT: store i32 8, ptr [[DOTOMP_UB5]], align 4 8049 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 4 8050 // CHECK13-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV6]], align 4 8051 // CHECK13-NEXT: [[TMP12:%.*]] = load i64, ptr [[K]], align 8 8052 // CHECK13-NEXT: store i64 [[TMP12]], ptr [[DOTLINEAR_START]], align 8 8053 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 8054 // CHECK13: omp.inner.for.cond9: 8055 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 8056 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP6]] 8057 // CHECK13-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 8058 // CHECK13-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 8059 // CHECK13: omp.inner.for.body11: 8060 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 8061 // CHECK13-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1 8062 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 8063 // CHECK13-NEXT: store i32 [[SUB]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP6]] 8064 // CHECK13-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP6]] 8065 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 8066 // CHECK13-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3 8067 // CHECK13-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 8068 // CHECK13-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]] 8069 // CHECK13-NEXT: store i64 [[ADD14]], ptr [[K8]], align 8, !llvm.access.group [[ACC_GRP6]] 8070 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP6]] 8071 // CHECK13-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 8072 // CHECK13-NEXT: store i32 [[ADD15]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP6]] 8073 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 8074 // CHECK13: omp.body.continue16: 8075 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 8076 // CHECK13: omp.inner.for.inc17: 8077 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 8078 // CHECK13-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 8079 // CHECK13-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 8080 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] 8081 // CHECK13: omp.inner.for.end19: 8082 // CHECK13-NEXT: store i32 1, ptr [[I7]], align 4 8083 // CHECK13-NEXT: [[TMP20:%.*]] = load i64, ptr [[K8]], align 8 8084 // CHECK13-NEXT: store i64 [[TMP20]], ptr [[K]], align 8 8085 // CHECK13-NEXT: store i32 12, ptr [[LIN]], align 4 8086 // CHECK13-NEXT: store i64 0, ptr [[DOTOMP_LB21]], align 8 8087 // CHECK13-NEXT: store i64 3, ptr [[DOTOMP_UB22]], align 8 8088 // CHECK13-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB21]], align 8 8089 // CHECK13-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV23]], align 8 8090 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN]], align 4 8091 // CHECK13-NEXT: store i32 [[TMP22]], ptr [[DOTLINEAR_START24]], align 4 8092 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, ptr [[A]], align 4 8093 // CHECK13-NEXT: store i32 [[TMP23]], ptr [[DOTLINEAR_START25]], align 4 8094 // CHECK13-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 8095 // CHECK13-NEXT: store i64 [[CALL26]], ptr [[DOTLINEAR_STEP]], align 8 8096 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 8097 // CHECK13: omp.inner.for.cond29: 8098 // CHECK13-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9:![0-9]+]] 8099 // CHECK13-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP9]] 8100 // CHECK13-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]] 8101 // CHECK13-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 8102 // CHECK13: omp.inner.for.body31: 8103 // CHECK13-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 8104 // CHECK13-NEXT: [[MUL32:%.*]] = mul i64 [[TMP26]], 400 8105 // CHECK13-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 8106 // CHECK13-NEXT: store i64 [[SUB33]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP9]] 8107 // CHECK13-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP9]] 8108 // CHECK13-NEXT: [[CONV34:%.*]] = sext i32 [[TMP27]] to i64 8109 // CHECK13-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 8110 // CHECK13-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]] 8111 // CHECK13-NEXT: [[MUL35:%.*]] = mul i64 [[TMP28]], [[TMP29]] 8112 // CHECK13-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 8113 // CHECK13-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 8114 // CHECK13-NEXT: store i32 [[CONV37]], ptr [[LIN27]], align 4, !llvm.access.group [[ACC_GRP9]] 8115 // CHECK13-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP9]] 8116 // CHECK13-NEXT: [[CONV38:%.*]] = sext i32 [[TMP30]] to i64 8117 // CHECK13-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 8118 // CHECK13-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]] 8119 // CHECK13-NEXT: [[MUL39:%.*]] = mul i64 [[TMP31]], [[TMP32]] 8120 // CHECK13-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 8121 // CHECK13-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 8122 // CHECK13-NEXT: store i32 [[CONV41]], ptr [[A28]], align 4, !llvm.access.group [[ACC_GRP9]] 8123 // CHECK13-NEXT: [[TMP33:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]] 8124 // CHECK13-NEXT: [[CONV42:%.*]] = sext i16 [[TMP33]] to i32 8125 // CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 8126 // CHECK13-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 8127 // CHECK13-NEXT: store i16 [[CONV44]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]] 8128 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 8129 // CHECK13: omp.body.continue45: 8130 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 8131 // CHECK13: omp.inner.for.inc46: 8132 // CHECK13-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 8133 // CHECK13-NEXT: [[ADD47:%.*]] = add i64 [[TMP34]], 1 8134 // CHECK13-NEXT: store i64 [[ADD47]], ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 8135 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP10:![0-9]+]] 8136 // CHECK13: omp.inner.for.end48: 8137 // CHECK13-NEXT: store i64 400, ptr [[IT]], align 8 8138 // CHECK13-NEXT: [[TMP35:%.*]] = load i32, ptr [[LIN27]], align 4 8139 // CHECK13-NEXT: store i32 [[TMP35]], ptr [[LIN]], align 4 8140 // CHECK13-NEXT: [[TMP36:%.*]] = load i32, ptr [[A28]], align 4 8141 // CHECK13-NEXT: store i32 [[TMP36]], ptr [[A]], align 4 8142 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB50]], align 4 8143 // CHECK13-NEXT: store i32 3, ptr [[DOTOMP_UB51]], align 4 8144 // CHECK13-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_LB50]], align 4 8145 // CHECK13-NEXT: store i32 [[TMP37]], ptr [[DOTOMP_IV52]], align 4 8146 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 8147 // CHECK13: omp.inner.for.cond54: 8148 // CHECK13-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 8149 // CHECK13-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP12]] 8150 // CHECK13-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]] 8151 // CHECK13-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 8152 // CHECK13: omp.inner.for.body56: 8153 // CHECK13-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 8154 // CHECK13-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP40]], 4 8155 // CHECK13-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 8156 // CHECK13-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 8157 // CHECK13-NEXT: store i16 [[CONV59]], ptr [[IT53]], align 2, !llvm.access.group [[ACC_GRP12]] 8158 // CHECK13-NEXT: [[TMP41:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]] 8159 // CHECK13-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP41]], 1 8160 // CHECK13-NEXT: store i32 [[ADD60]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]] 8161 // CHECK13-NEXT: [[TMP42:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]] 8162 // CHECK13-NEXT: [[CONV61:%.*]] = sext i16 [[TMP42]] to i32 8163 // CHECK13-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 8164 // CHECK13-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 8165 // CHECK13-NEXT: store i16 [[CONV63]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]] 8166 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 8167 // CHECK13: omp.body.continue64: 8168 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 8169 // CHECK13: omp.inner.for.inc65: 8170 // CHECK13-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 8171 // CHECK13-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP43]], 1 8172 // CHECK13-NEXT: store i32 [[ADD66]], ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 8173 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP13:![0-9]+]] 8174 // CHECK13: omp.inner.for.end67: 8175 // CHECK13-NEXT: store i16 22, ptr [[IT53]], align 2 8176 // CHECK13-NEXT: [[TMP44:%.*]] = load i32, ptr [[A]], align 4 8177 // CHECK13-NEXT: store i32 [[TMP44]], ptr [[DOTCAPTURE_EXPR_]], align 4 8178 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB69]], align 4 8179 // CHECK13-NEXT: store i32 25, ptr [[DOTOMP_UB70]], align 4 8180 // CHECK13-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_LB69]], align 4 8181 // CHECK13-NEXT: store i32 [[TMP45]], ptr [[DOTOMP_IV71]], align 4 8182 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 8183 // CHECK13: omp.inner.for.cond73: 8184 // CHECK13-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] 8185 // CHECK13-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP15]] 8186 // CHECK13-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]] 8187 // CHECK13-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 8188 // CHECK13: omp.inner.for.body75: 8189 // CHECK13-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 8190 // CHECK13-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP48]], 1 8191 // CHECK13-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 8192 // CHECK13-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 8193 // CHECK13-NEXT: store i8 [[CONV78]], ptr [[IT72]], align 1, !llvm.access.group [[ACC_GRP15]] 8194 // CHECK13-NEXT: [[TMP49:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]] 8195 // CHECK13-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP49]], 1 8196 // CHECK13-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]] 8197 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 2 8198 // CHECK13-NEXT: [[TMP50:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] 8199 // CHECK13-NEXT: [[CONV80:%.*]] = fpext float [[TMP50]] to double 8200 // CHECK13-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 8201 // CHECK13-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 8202 // CHECK13-NEXT: store float [[CONV82]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] 8203 // CHECK13-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 3 8204 // CHECK13-NEXT: [[TMP51:%.*]] = load float, ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]] 8205 // CHECK13-NEXT: [[CONV84:%.*]] = fpext float [[TMP51]] to double 8206 // CHECK13-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 8207 // CHECK13-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 8208 // CHECK13-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]] 8209 // CHECK13-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 1 8210 // CHECK13-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i64 0, i64 2 8211 // CHECK13-NEXT: [[TMP52:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] 8212 // CHECK13-NEXT: [[ADD89:%.*]] = fadd double [[TMP52]], 1.000000e+00 8213 // CHECK13-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] 8214 // CHECK13-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP4]] 8215 // CHECK13-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP53]] 8216 // CHECK13-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX90]], i64 3 8217 // CHECK13-NEXT: [[TMP54:%.*]] = load double, ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]] 8218 // CHECK13-NEXT: [[ADD92:%.*]] = fadd double [[TMP54]], 1.000000e+00 8219 // CHECK13-NEXT: store double [[ADD92]], ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]] 8220 // CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 8221 // CHECK13-NEXT: [[TMP55:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]] 8222 // CHECK13-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP55]], 1 8223 // CHECK13-NEXT: store i64 [[ADD93]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]] 8224 // CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 8225 // CHECK13-NEXT: [[TMP56:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]] 8226 // CHECK13-NEXT: [[CONV94:%.*]] = sext i8 [[TMP56]] to i32 8227 // CHECK13-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 8228 // CHECK13-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 8229 // CHECK13-NEXT: store i8 [[CONV96]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]] 8230 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 8231 // CHECK13: omp.body.continue97: 8232 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 8233 // CHECK13: omp.inner.for.inc98: 8234 // CHECK13-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 8235 // CHECK13-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 1 8236 // CHECK13-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 8237 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]] 8238 // CHECK13: omp.inner.for.end100: 8239 // CHECK13-NEXT: store i8 96, ptr [[IT72]], align 1 8240 // CHECK13-NEXT: [[TMP58:%.*]] = load i32, ptr [[A]], align 4 8241 // CHECK13-NEXT: [[TMP59:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 8242 // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP59]]) 8243 // CHECK13-NEXT: ret i32 [[TMP58]] 8244 // 8245 // 8246 // CHECK13-LABEL: define {{[^@]+}}@_Z3bari 8247 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 8248 // CHECK13-NEXT: entry: 8249 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8250 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8251 // CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 8252 // CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8253 // CHECK13-NEXT: store i32 0, ptr [[A]], align 4 8254 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 8255 // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 8256 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 8257 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 8258 // CHECK13-NEXT: store i32 [[ADD]], ptr [[A]], align 4 8259 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 8260 // CHECK13-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 8261 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 8262 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 8263 // CHECK13-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 8264 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 8265 // CHECK13-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 8266 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 8267 // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 8268 // CHECK13-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 8269 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 8270 // CHECK13-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 8271 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 8272 // CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 8273 // CHECK13-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 8274 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 8275 // CHECK13-NEXT: ret i32 [[TMP8]] 8276 // 8277 // 8278 // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 8279 // CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 8280 // CHECK13-NEXT: entry: 8281 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 8282 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8283 // CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 8284 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 8285 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 8286 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 8287 // CHECK13-NEXT: [[TMP:%.*]] = alloca i64, align 8 8288 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8289 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8290 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8291 // CHECK13-NEXT: [[IT:%.*]] = alloca i64, align 8 8292 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 8293 // CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8294 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 8295 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 8296 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8297 // CHECK13-NEXT: store i32 [[ADD]], ptr [[B]], align 4 8298 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 8299 // CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 8300 // CHECK13-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0() 8301 // CHECK13-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 8302 // CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 8303 // CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 8304 // CHECK13-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 8305 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 8306 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 8307 // CHECK13-NEXT: [[STOREDV:%.*]] = zext i1 [[CMP]] to i8 8308 // CHECK13-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1 8309 // CHECK13-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 8310 // CHECK13-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 8311 // CHECK13-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 8312 // CHECK13-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 8313 // CHECK13-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 8314 // CHECK13-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i1 8315 // CHECK13-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8316 // CHECK13: omp_if.then: 8317 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8318 // CHECK13: omp.inner.for.cond: 8319 // CHECK13-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]] 8320 // CHECK13-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]] 8321 // CHECK13-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP8]], [[TMP9]] 8322 // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8323 // CHECK13: omp.inner.for.body: 8324 // CHECK13-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 8325 // CHECK13-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 400 8326 // CHECK13-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 8327 // CHECK13-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP18]] 8328 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP18]] 8329 // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP11]] to double 8330 // CHECK13-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 8331 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 8332 // CHECK13-NEXT: store double [[ADD3]], ptr [[A]], align 8, !nontemporal [[META19:![0-9]+]], !llvm.access.group [[ACC_GRP18]] 8333 // CHECK13-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 8334 // CHECK13-NEXT: [[TMP12:%.*]] = load double, ptr [[A4]], align 8, !nontemporal [[META19]], !llvm.access.group [[ACC_GRP18]] 8335 // CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00 8336 // CHECK13-NEXT: store double [[INC]], ptr [[A4]], align 8, !nontemporal [[META19]], !llvm.access.group [[ACC_GRP18]] 8337 // CHECK13-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 8338 // CHECK13-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] 8339 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP13]] 8340 // CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 8341 // CHECK13-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP18]] 8342 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8343 // CHECK13: omp.body.continue: 8344 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8345 // CHECK13: omp.inner.for.inc: 8346 // CHECK13-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 8347 // CHECK13-NEXT: [[ADD7:%.*]] = add i64 [[TMP14]], 1 8348 // CHECK13-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 8349 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 8350 // CHECK13: omp.inner.for.end: 8351 // CHECK13-NEXT: br label [[OMP_IF_END:%.*]] 8352 // CHECK13: omp_if.else: 8353 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]] 8354 // CHECK13: omp.inner.for.cond8: 8355 // CHECK13-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 8356 // CHECK13-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 8357 // CHECK13-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP15]], [[TMP16]] 8358 // CHECK13-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]] 8359 // CHECK13: omp.inner.for.body10: 8360 // CHECK13-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 8361 // CHECK13-NEXT: [[MUL11:%.*]] = mul i64 [[TMP17]], 400 8362 // CHECK13-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]] 8363 // CHECK13-NEXT: store i64 [[SUB12]], ptr [[IT]], align 8 8364 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[B]], align 4 8365 // CHECK13-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP18]] to double 8366 // CHECK13-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00 8367 // CHECK13-NEXT: [[A15:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 8368 // CHECK13-NEXT: store double [[ADD14]], ptr [[A15]], align 8 8369 // CHECK13-NEXT: [[A16:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 8370 // CHECK13-NEXT: [[TMP19:%.*]] = load double, ptr [[A16]], align 8 8371 // CHECK13-NEXT: [[INC17:%.*]] = fadd double [[TMP19]], 1.000000e+00 8372 // CHECK13-NEXT: store double [[INC17]], ptr [[A16]], align 8 8373 // CHECK13-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16 8374 // CHECK13-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]] 8375 // CHECK13-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP20]] 8376 // CHECK13-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX19]], i64 1 8377 // CHECK13-NEXT: store i16 [[CONV18]], ptr [[ARRAYIDX20]], align 2 8378 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]] 8379 // CHECK13: omp.body.continue21: 8380 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]] 8381 // CHECK13: omp.inner.for.inc22: 8382 // CHECK13-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 8383 // CHECK13-NEXT: [[ADD23:%.*]] = add i64 [[TMP21]], 1 8384 // CHECK13-NEXT: store i64 [[ADD23]], ptr [[DOTOMP_IV]], align 8 8385 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP22:![0-9]+]] 8386 // CHECK13: omp.inner.for.end24: 8387 // CHECK13-NEXT: br label [[OMP_IF_END]] 8388 // CHECK13: omp_if.end: 8389 // CHECK13-NEXT: store i64 400, ptr [[IT]], align 8 8390 // CHECK13-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]] 8391 // CHECK13-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP22]] 8392 // CHECK13-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX25]], i64 1 8393 // CHECK13-NEXT: [[TMP23:%.*]] = load i16, ptr [[ARRAYIDX26]], align 2 8394 // CHECK13-NEXT: [[CONV27:%.*]] = sext i16 [[TMP23]] to i32 8395 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, ptr [[B]], align 4 8396 // CHECK13-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP24]] 8397 // CHECK13-NEXT: [[TMP25:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 8398 // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP25]]) 8399 // CHECK13-NEXT: ret i32 [[ADD28]] 8400 // 8401 // 8402 // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici 8403 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 8404 // CHECK13-NEXT: entry: 8405 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8406 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8407 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 8408 // CHECK13-NEXT: [[AAA:%.*]] = alloca i8, align 1 8409 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8410 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 8411 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8412 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8413 // CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8414 // CHECK13-NEXT: store i32 0, ptr [[A]], align 4 8415 // CHECK13-NEXT: store i16 0, ptr [[AA]], align 2 8416 // CHECK13-NEXT: store i8 0, ptr [[AAA]], align 1 8417 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 8418 // CHECK13-NEXT: store i32 429496720, ptr [[DOTOMP_UB]], align 4 8419 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 8420 // CHECK13-NEXT: ret i32 [[TMP0]] 8421 // 8422 // 8423 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 8424 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 8425 // CHECK13-NEXT: entry: 8426 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8427 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8428 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 8429 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8430 // CHECK13-NEXT: [[TMP:%.*]] = alloca i64, align 8 8431 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8432 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8433 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8434 // CHECK13-NEXT: [[I:%.*]] = alloca i64, align 8 8435 // CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8436 // CHECK13-NEXT: store i32 0, ptr [[A]], align 4 8437 // CHECK13-NEXT: store i16 0, ptr [[AA]], align 2 8438 // CHECK13-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 8439 // CHECK13-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 8440 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 8441 // CHECK13-NEXT: store i64 [[TMP0]], ptr [[DOTOMP_IV]], align 8 8442 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8443 // CHECK13: omp.inner.for.cond: 8444 // CHECK13-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24:![0-9]+]] 8445 // CHECK13-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP24]] 8446 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 8447 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8448 // CHECK13: omp.inner.for.body: 8449 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24]] 8450 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 8451 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 8452 // CHECK13-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP24]] 8453 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP24]] 8454 // CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 8455 // CHECK13-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP24]] 8456 // CHECK13-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP24]] 8457 // CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 8458 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 8459 // CHECK13-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 8460 // CHECK13-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP24]] 8461 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 8462 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 8463 // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 8464 // CHECK13-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 8465 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8466 // CHECK13: omp.body.continue: 8467 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8468 // CHECK13: omp.inner.for.inc: 8469 // CHECK13-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24]] 8470 // CHECK13-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 8471 // CHECK13-NEXT: store i64 [[ADD5]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24]] 8472 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 8473 // CHECK13: omp.inner.for.end: 8474 // CHECK13-NEXT: store i64 11, ptr [[I]], align 8 8475 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 8476 // CHECK13-NEXT: ret i32 [[TMP8]] 8477 // 8478 // 8479 // CHECK15-LABEL: define {{[^@]+}}@_Z7get_valv 8480 // CHECK15-SAME: () #[[ATTR0:[0-9]+]] { 8481 // CHECK15-NEXT: entry: 8482 // CHECK15-NEXT: ret i64 0 8483 // 8484 // 8485 // CHECK15-LABEL: define {{[^@]+}}@_Z3fooi 8486 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 8487 // CHECK15-NEXT: entry: 8488 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8489 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 8490 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 8491 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x float], align 4 8492 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 8493 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 8494 // CHECK15-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 8495 // CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 8496 // CHECK15-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 8497 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 8498 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8499 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8500 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8501 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 8502 // CHECK15-NEXT: [[K:%.*]] = alloca i64, align 8 8503 // CHECK15-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 8504 // CHECK15-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 8505 // CHECK15-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 8506 // CHECK15-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 8507 // CHECK15-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 8508 // CHECK15-NEXT: [[I7:%.*]] = alloca i32, align 4 8509 // CHECK15-NEXT: [[K8:%.*]] = alloca i64, align 8 8510 // CHECK15-NEXT: [[LIN:%.*]] = alloca i32, align 4 8511 // CHECK15-NEXT: [[_TMP20:%.*]] = alloca i64, align 4 8512 // CHECK15-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 8513 // CHECK15-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 8514 // CHECK15-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 8515 // CHECK15-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 8516 // CHECK15-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 8517 // CHECK15-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 8518 // CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 8 8519 // CHECK15-NEXT: [[LIN27:%.*]] = alloca i32, align 4 8520 // CHECK15-NEXT: [[A28:%.*]] = alloca i32, align 4 8521 // CHECK15-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 8522 // CHECK15-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 8523 // CHECK15-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 8524 // CHECK15-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 8525 // CHECK15-NEXT: [[IT53:%.*]] = alloca i16, align 2 8526 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 8527 // CHECK15-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 8528 // CHECK15-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 8529 // CHECK15-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 8530 // CHECK15-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 8531 // CHECK15-NEXT: [[IT72:%.*]] = alloca i8, align 1 8532 // CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8533 // CHECK15-NEXT: store i32 0, ptr [[A]], align 4 8534 // CHECK15-NEXT: store i16 0, ptr [[AA]], align 2 8535 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 8536 // CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0() 8537 // CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 8538 // CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 8539 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 8540 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 8541 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 8542 // CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 8543 // CHECK15-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 8544 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 8545 // CHECK15-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 8546 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 8547 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 8548 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8549 // CHECK15: omp.inner.for.cond: 8550 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 8551 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 8552 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 8553 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8554 // CHECK15: omp.inner.for.body: 8555 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 8556 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 8557 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 8558 // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 8559 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8560 // CHECK15: omp.body.continue: 8561 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8562 // CHECK15: omp.inner.for.inc: 8563 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 8564 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 8565 // CHECK15-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 8566 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 8567 // CHECK15: omp.inner.for.end: 8568 // CHECK15-NEXT: store i32 33, ptr [[I]], align 4 8569 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 8570 // CHECK15-NEXT: store i64 [[CALL]], ptr [[K]], align 8 8571 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 4 8572 // CHECK15-NEXT: store i32 8, ptr [[DOTOMP_UB5]], align 4 8573 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 4 8574 // CHECK15-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV6]], align 4 8575 // CHECK15-NEXT: [[TMP10:%.*]] = load i64, ptr [[K]], align 8 8576 // CHECK15-NEXT: store i64 [[TMP10]], ptr [[DOTLINEAR_START]], align 8 8577 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 8578 // CHECK15: omp.inner.for.cond9: 8579 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 8580 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP7]] 8581 // CHECK15-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 8582 // CHECK15-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 8583 // CHECK15: omp.inner.for.body11: 8584 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 8585 // CHECK15-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1 8586 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 8587 // CHECK15-NEXT: store i32 [[SUB]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] 8588 // CHECK15-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP7]] 8589 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 8590 // CHECK15-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3 8591 // CHECK15-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 8592 // CHECK15-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]] 8593 // CHECK15-NEXT: store i64 [[ADD14]], ptr [[K8]], align 8, !llvm.access.group [[ACC_GRP7]] 8594 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP7]] 8595 // CHECK15-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 8596 // CHECK15-NEXT: store i32 [[ADD15]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP7]] 8597 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 8598 // CHECK15: omp.body.continue16: 8599 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 8600 // CHECK15: omp.inner.for.inc17: 8601 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 8602 // CHECK15-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 8603 // CHECK15-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 8604 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]] 8605 // CHECK15: omp.inner.for.end19: 8606 // CHECK15-NEXT: store i32 1, ptr [[I7]], align 4 8607 // CHECK15-NEXT: [[TMP18:%.*]] = load i64, ptr [[K8]], align 8 8608 // CHECK15-NEXT: store i64 [[TMP18]], ptr [[K]], align 8 8609 // CHECK15-NEXT: store i32 12, ptr [[LIN]], align 4 8610 // CHECK15-NEXT: store i64 0, ptr [[DOTOMP_LB21]], align 8 8611 // CHECK15-NEXT: store i64 3, ptr [[DOTOMP_UB22]], align 8 8612 // CHECK15-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_LB21]], align 8 8613 // CHECK15-NEXT: store i64 [[TMP19]], ptr [[DOTOMP_IV23]], align 8 8614 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN]], align 4 8615 // CHECK15-NEXT: store i32 [[TMP20]], ptr [[DOTLINEAR_START24]], align 4 8616 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 4 8617 // CHECK15-NEXT: store i32 [[TMP21]], ptr [[DOTLINEAR_START25]], align 4 8618 // CHECK15-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 8619 // CHECK15-NEXT: store i64 [[CALL26]], ptr [[DOTLINEAR_STEP]], align 8 8620 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 8621 // CHECK15: omp.inner.for.cond29: 8622 // CHECK15-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10:![0-9]+]] 8623 // CHECK15-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP10]] 8624 // CHECK15-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 8625 // CHECK15-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 8626 // CHECK15: omp.inner.for.body31: 8627 // CHECK15-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8628 // CHECK15-NEXT: [[MUL32:%.*]] = mul i64 [[TMP24]], 400 8629 // CHECK15-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 8630 // CHECK15-NEXT: store i64 [[SUB33]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP10]] 8631 // CHECK15-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP10]] 8632 // CHECK15-NEXT: [[CONV34:%.*]] = sext i32 [[TMP25]] to i64 8633 // CHECK15-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8634 // CHECK15-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]] 8635 // CHECK15-NEXT: [[MUL35:%.*]] = mul i64 [[TMP26]], [[TMP27]] 8636 // CHECK15-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 8637 // CHECK15-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 8638 // CHECK15-NEXT: store i32 [[CONV37]], ptr [[LIN27]], align 4, !llvm.access.group [[ACC_GRP10]] 8639 // CHECK15-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP10]] 8640 // CHECK15-NEXT: [[CONV38:%.*]] = sext i32 [[TMP28]] to i64 8641 // CHECK15-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8642 // CHECK15-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]] 8643 // CHECK15-NEXT: [[MUL39:%.*]] = mul i64 [[TMP29]], [[TMP30]] 8644 // CHECK15-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 8645 // CHECK15-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 8646 // CHECK15-NEXT: store i32 [[CONV41]], ptr [[A28]], align 4, !llvm.access.group [[ACC_GRP10]] 8647 // CHECK15-NEXT: [[TMP31:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]] 8648 // CHECK15-NEXT: [[CONV42:%.*]] = sext i16 [[TMP31]] to i32 8649 // CHECK15-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 8650 // CHECK15-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 8651 // CHECK15-NEXT: store i16 [[CONV44]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]] 8652 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 8653 // CHECK15: omp.body.continue45: 8654 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 8655 // CHECK15: omp.inner.for.inc46: 8656 // CHECK15-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8657 // CHECK15-NEXT: [[ADD47:%.*]] = add i64 [[TMP32]], 1 8658 // CHECK15-NEXT: store i64 [[ADD47]], ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8659 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP11:![0-9]+]] 8660 // CHECK15: omp.inner.for.end48: 8661 // CHECK15-NEXT: store i64 400, ptr [[IT]], align 8 8662 // CHECK15-NEXT: [[TMP33:%.*]] = load i32, ptr [[LIN27]], align 4 8663 // CHECK15-NEXT: store i32 [[TMP33]], ptr [[LIN]], align 4 8664 // CHECK15-NEXT: [[TMP34:%.*]] = load i32, ptr [[A28]], align 4 8665 // CHECK15-NEXT: store i32 [[TMP34]], ptr [[A]], align 4 8666 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB50]], align 4 8667 // CHECK15-NEXT: store i32 3, ptr [[DOTOMP_UB51]], align 4 8668 // CHECK15-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_LB50]], align 4 8669 // CHECK15-NEXT: store i32 [[TMP35]], ptr [[DOTOMP_IV52]], align 4 8670 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 8671 // CHECK15: omp.inner.for.cond54: 8672 // CHECK15-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] 8673 // CHECK15-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP13]] 8674 // CHECK15-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP36]], [[TMP37]] 8675 // CHECK15-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 8676 // CHECK15: omp.inner.for.body56: 8677 // CHECK15-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 8678 // CHECK15-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP38]], 4 8679 // CHECK15-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 8680 // CHECK15-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 8681 // CHECK15-NEXT: store i16 [[CONV59]], ptr [[IT53]], align 2, !llvm.access.group [[ACC_GRP13]] 8682 // CHECK15-NEXT: [[TMP39:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]] 8683 // CHECK15-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP39]], 1 8684 // CHECK15-NEXT: store i32 [[ADD60]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]] 8685 // CHECK15-NEXT: [[TMP40:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]] 8686 // CHECK15-NEXT: [[CONV61:%.*]] = sext i16 [[TMP40]] to i32 8687 // CHECK15-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 8688 // CHECK15-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 8689 // CHECK15-NEXT: store i16 [[CONV63]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]] 8690 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 8691 // CHECK15: omp.body.continue64: 8692 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 8693 // CHECK15: omp.inner.for.inc65: 8694 // CHECK15-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 8695 // CHECK15-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP41]], 1 8696 // CHECK15-NEXT: store i32 [[ADD66]], ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 8697 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP14:![0-9]+]] 8698 // CHECK15: omp.inner.for.end67: 8699 // CHECK15-NEXT: store i16 22, ptr [[IT53]], align 2 8700 // CHECK15-NEXT: [[TMP42:%.*]] = load i32, ptr [[A]], align 4 8701 // CHECK15-NEXT: store i32 [[TMP42]], ptr [[DOTCAPTURE_EXPR_]], align 4 8702 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB69]], align 4 8703 // CHECK15-NEXT: store i32 25, ptr [[DOTOMP_UB70]], align 4 8704 // CHECK15-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_LB69]], align 4 8705 // CHECK15-NEXT: store i32 [[TMP43]], ptr [[DOTOMP_IV71]], align 4 8706 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 8707 // CHECK15: omp.inner.for.cond73: 8708 // CHECK15-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] 8709 // CHECK15-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP16]] 8710 // CHECK15-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP44]], [[TMP45]] 8711 // CHECK15-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 8712 // CHECK15: omp.inner.for.body75: 8713 // CHECK15-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 8714 // CHECK15-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP46]], 1 8715 // CHECK15-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 8716 // CHECK15-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 8717 // CHECK15-NEXT: store i8 [[CONV78]], ptr [[IT72]], align 1, !llvm.access.group [[ACC_GRP16]] 8718 // CHECK15-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] 8719 // CHECK15-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP47]], 1 8720 // CHECK15-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] 8721 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 2 8722 // CHECK15-NEXT: [[TMP48:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] 8723 // CHECK15-NEXT: [[CONV80:%.*]] = fpext float [[TMP48]] to double 8724 // CHECK15-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 8725 // CHECK15-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 8726 // CHECK15-NEXT: store float [[CONV82]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] 8727 // CHECK15-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 3 8728 // CHECK15-NEXT: [[TMP49:%.*]] = load float, ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]] 8729 // CHECK15-NEXT: [[CONV84:%.*]] = fpext float [[TMP49]] to double 8730 // CHECK15-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 8731 // CHECK15-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 8732 // CHECK15-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]] 8733 // CHECK15-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 1 8734 // CHECK15-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i32 0, i32 2 8735 // CHECK15-NEXT: [[TMP50:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] 8736 // CHECK15-NEXT: [[ADD89:%.*]] = fadd double [[TMP50]], 1.000000e+00 8737 // CHECK15-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] 8738 // CHECK15-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP2]] 8739 // CHECK15-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP51]] 8740 // CHECK15-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX90]], i32 3 8741 // CHECK15-NEXT: [[TMP52:%.*]] = load double, ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]] 8742 // CHECK15-NEXT: [[ADD92:%.*]] = fadd double [[TMP52]], 1.000000e+00 8743 // CHECK15-NEXT: store double [[ADD92]], ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]] 8744 // CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 8745 // CHECK15-NEXT: [[TMP53:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]] 8746 // CHECK15-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP53]], 1 8747 // CHECK15-NEXT: store i64 [[ADD93]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]] 8748 // CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 8749 // CHECK15-NEXT: [[TMP54:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]] 8750 // CHECK15-NEXT: [[CONV94:%.*]] = sext i8 [[TMP54]] to i32 8751 // CHECK15-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 8752 // CHECK15-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 8753 // CHECK15-NEXT: store i8 [[CONV96]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]] 8754 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 8755 // CHECK15: omp.body.continue97: 8756 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 8757 // CHECK15: omp.inner.for.inc98: 8758 // CHECK15-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 8759 // CHECK15-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 1 8760 // CHECK15-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 8761 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]] 8762 // CHECK15: omp.inner.for.end100: 8763 // CHECK15-NEXT: store i8 96, ptr [[IT72]], align 1 8764 // CHECK15-NEXT: [[TMP56:%.*]] = load i32, ptr [[A]], align 4 8765 // CHECK15-NEXT: [[TMP57:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 8766 // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP57]]) 8767 // CHECK15-NEXT: ret i32 [[TMP56]] 8768 // 8769 // 8770 // CHECK15-LABEL: define {{[^@]+}}@_Z3bari 8771 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 8772 // CHECK15-NEXT: entry: 8773 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8774 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 8775 // CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 8776 // CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8777 // CHECK15-NEXT: store i32 0, ptr [[A]], align 4 8778 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 8779 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 8780 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 8781 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 8782 // CHECK15-NEXT: store i32 [[ADD]], ptr [[A]], align 4 8783 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 8784 // CHECK15-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 8785 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 8786 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 8787 // CHECK15-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 8788 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 8789 // CHECK15-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 8790 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 8791 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 8792 // CHECK15-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 8793 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 8794 // CHECK15-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 8795 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 8796 // CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 8797 // CHECK15-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 8798 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 8799 // CHECK15-NEXT: ret i32 [[TMP8]] 8800 // 8801 // 8802 // CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 8803 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 8804 // CHECK15-NEXT: entry: 8805 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 8806 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8807 // CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 8808 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 8809 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 8810 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 8811 // CHECK15-NEXT: [[TMP:%.*]] = alloca i64, align 4 8812 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8813 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8814 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8815 // CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 8 8816 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 8817 // CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8818 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 8819 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 8820 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8821 // CHECK15-NEXT: store i32 [[ADD]], ptr [[B]], align 4 8822 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 8823 // CHECK15-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0() 8824 // CHECK15-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 8825 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 8826 // CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 8827 // CHECK15-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 8828 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 8829 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 8830 // CHECK15-NEXT: [[STOREDV:%.*]] = zext i1 [[CMP]] to i8 8831 // CHECK15-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1 8832 // CHECK15-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 8833 // CHECK15-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 8834 // CHECK15-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 8835 // CHECK15-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 8836 // CHECK15-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 8837 // CHECK15-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP6]] to i1 8838 // CHECK15-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8839 // CHECK15: omp_if.then: 8840 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8841 // CHECK15: omp.inner.for.cond: 8842 // CHECK15-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19:![0-9]+]] 8843 // CHECK15-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP19]] 8844 // CHECK15-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 8845 // CHECK15-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8846 // CHECK15: omp.inner.for.body: 8847 // CHECK15-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 8848 // CHECK15-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 8849 // CHECK15-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 8850 // CHECK15-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP19]] 8851 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP19]] 8852 // CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double 8853 // CHECK15-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 8854 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 8855 // CHECK15-NEXT: store double [[ADD3]], ptr [[A]], align 4, !nontemporal [[META20:![0-9]+]], !llvm.access.group [[ACC_GRP19]] 8856 // CHECK15-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 8857 // CHECK15-NEXT: [[TMP11:%.*]] = load double, ptr [[A4]], align 4, !nontemporal [[META20]], !llvm.access.group [[ACC_GRP19]] 8858 // CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 8859 // CHECK15-NEXT: store double [[INC]], ptr [[A4]], align 4, !nontemporal [[META20]], !llvm.access.group [[ACC_GRP19]] 8860 // CHECK15-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 8861 // CHECK15-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] 8862 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP12]] 8863 // CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 8864 // CHECK15-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP19]] 8865 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8866 // CHECK15: omp.body.continue: 8867 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8868 // CHECK15: omp.inner.for.inc: 8869 // CHECK15-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 8870 // CHECK15-NEXT: [[ADD7:%.*]] = add i64 [[TMP13]], 1 8871 // CHECK15-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 8872 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 8873 // CHECK15: omp.inner.for.end: 8874 // CHECK15-NEXT: br label [[OMP_IF_END:%.*]] 8875 // CHECK15: omp_if.else: 8876 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]] 8877 // CHECK15: omp.inner.for.cond8: 8878 // CHECK15-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 8879 // CHECK15-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 8880 // CHECK15-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP14]], [[TMP15]] 8881 // CHECK15-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]] 8882 // CHECK15: omp.inner.for.body10: 8883 // CHECK15-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 8884 // CHECK15-NEXT: [[MUL11:%.*]] = mul i64 [[TMP16]], 400 8885 // CHECK15-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]] 8886 // CHECK15-NEXT: store i64 [[SUB12]], ptr [[IT]], align 8 8887 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[B]], align 4 8888 // CHECK15-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP17]] to double 8889 // CHECK15-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00 8890 // CHECK15-NEXT: [[A15:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 8891 // CHECK15-NEXT: store double [[ADD14]], ptr [[A15]], align 4 8892 // CHECK15-NEXT: [[A16:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 8893 // CHECK15-NEXT: [[TMP18:%.*]] = load double, ptr [[A16]], align 4 8894 // CHECK15-NEXT: [[INC17:%.*]] = fadd double [[TMP18]], 1.000000e+00 8895 // CHECK15-NEXT: store double [[INC17]], ptr [[A16]], align 4 8896 // CHECK15-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16 8897 // CHECK15-NEXT: [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]] 8898 // CHECK15-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP19]] 8899 // CHECK15-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX19]], i32 1 8900 // CHECK15-NEXT: store i16 [[CONV18]], ptr [[ARRAYIDX20]], align 2 8901 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]] 8902 // CHECK15: omp.body.continue21: 8903 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]] 8904 // CHECK15: omp.inner.for.inc22: 8905 // CHECK15-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 8906 // CHECK15-NEXT: [[ADD23:%.*]] = add i64 [[TMP20]], 1 8907 // CHECK15-NEXT: store i64 [[ADD23]], ptr [[DOTOMP_IV]], align 8 8908 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP23:![0-9]+]] 8909 // CHECK15: omp.inner.for.end24: 8910 // CHECK15-NEXT: br label [[OMP_IF_END]] 8911 // CHECK15: omp_if.end: 8912 // CHECK15-NEXT: store i64 400, ptr [[IT]], align 8 8913 // CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]] 8914 // CHECK15-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP21]] 8915 // CHECK15-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX25]], i32 1 8916 // CHECK15-NEXT: [[TMP22:%.*]] = load i16, ptr [[ARRAYIDX26]], align 2 8917 // CHECK15-NEXT: [[CONV27:%.*]] = sext i16 [[TMP22]] to i32 8918 // CHECK15-NEXT: [[TMP23:%.*]] = load i32, ptr [[B]], align 4 8919 // CHECK15-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP23]] 8920 // CHECK15-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 8921 // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP24]]) 8922 // CHECK15-NEXT: ret i32 [[ADD28]] 8923 // 8924 // 8925 // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici 8926 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 8927 // CHECK15-NEXT: entry: 8928 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8929 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 8930 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 8931 // CHECK15-NEXT: [[AAA:%.*]] = alloca i8, align 1 8932 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8933 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 8934 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8935 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8936 // CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8937 // CHECK15-NEXT: store i32 0, ptr [[A]], align 4 8938 // CHECK15-NEXT: store i16 0, ptr [[AA]], align 2 8939 // CHECK15-NEXT: store i8 0, ptr [[AAA]], align 1 8940 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 8941 // CHECK15-NEXT: store i32 429496720, ptr [[DOTOMP_UB]], align 4 8942 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 8943 // CHECK15-NEXT: ret i32 [[TMP0]] 8944 // 8945 // 8946 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 8947 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 8948 // CHECK15-NEXT: entry: 8949 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8950 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 8951 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 8952 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8953 // CHECK15-NEXT: [[TMP:%.*]] = alloca i64, align 4 8954 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8955 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8956 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8957 // CHECK15-NEXT: [[I:%.*]] = alloca i64, align 8 8958 // CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8959 // CHECK15-NEXT: store i32 0, ptr [[A]], align 4 8960 // CHECK15-NEXT: store i16 0, ptr [[AA]], align 2 8961 // CHECK15-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 8962 // CHECK15-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 8963 // CHECK15-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 8964 // CHECK15-NEXT: store i64 [[TMP0]], ptr [[DOTOMP_IV]], align 8 8965 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8966 // CHECK15: omp.inner.for.cond: 8967 // CHECK15-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25:![0-9]+]] 8968 // CHECK15-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP25]] 8969 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 8970 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8971 // CHECK15: omp.inner.for.body: 8972 // CHECK15-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25]] 8973 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 8974 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 8975 // CHECK15-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP25]] 8976 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP25]] 8977 // CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 8978 // CHECK15-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP25]] 8979 // CHECK15-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP25]] 8980 // CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 8981 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 8982 // CHECK15-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 8983 // CHECK15-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP25]] 8984 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 8985 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] 8986 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 8987 // CHECK15-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] 8988 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8989 // CHECK15: omp.body.continue: 8990 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8991 // CHECK15: omp.inner.for.inc: 8992 // CHECK15-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25]] 8993 // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 8994 // CHECK15-NEXT: store i64 [[ADD5]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25]] 8995 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] 8996 // CHECK15: omp.inner.for.end: 8997 // CHECK15-NEXT: store i64 11, ptr [[I]], align 8 8998 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 8999 // CHECK15-NEXT: ret i32 [[TMP8]] 9000 // 9001 // 9002 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 9003 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { 9004 // CHECK17-NEXT: entry: 9005 // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 9006 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 9007 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) 9008 // CHECK17-NEXT: ret void 9009 // 9010 // 9011 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined 9012 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 9013 // CHECK17-NEXT: entry: 9014 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 9015 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 9016 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9017 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 9018 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9019 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9020 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9021 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9022 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 9023 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 9024 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 9025 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 9026 // CHECK17-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 9027 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 9028 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9029 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 9030 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 9031 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 9032 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9033 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 9034 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9035 // CHECK17: cond.true: 9036 // CHECK17-NEXT: br label [[COND_END:%.*]] 9037 // CHECK17: cond.false: 9038 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9039 // CHECK17-NEXT: br label [[COND_END]] 9040 // CHECK17: cond.end: 9041 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9042 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 9043 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 9044 // CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 9045 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9046 // CHECK17: omp.inner.for.cond: 9047 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 9048 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 9049 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9050 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9051 // CHECK17: omp.inner.for.body: 9052 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 9053 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 9054 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 9055 // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 9056 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9057 // CHECK17: omp.body.continue: 9058 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9059 // CHECK17: omp.inner.for.inc: 9060 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 9061 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 9062 // CHECK17-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 9063 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 9064 // CHECK17: omp.inner.for.end: 9065 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9066 // CHECK17: omp.loop.exit: 9067 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 9068 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9069 // CHECK17-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 9070 // CHECK17-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9071 // CHECK17: .omp.final.then: 9072 // CHECK17-NEXT: store i32 33, ptr [[I]], align 4 9073 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9074 // CHECK17: .omp.final.done: 9075 // CHECK17-NEXT: ret void 9076 // 9077 // 9078 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 9079 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 9080 // CHECK17-NEXT: entry: 9081 // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 9082 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9083 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 9084 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9085 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9086 // CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 9087 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9088 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 9089 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9090 // CHECK17-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 9091 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9092 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 9093 // CHECK17-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 9094 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 9095 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 9096 // CHECK17-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 9097 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 9098 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 9099 // CHECK17-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 9100 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8 9101 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 9102 // CHECK17-NEXT: ret void 9103 // 9104 // 9105 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined 9106 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 9107 // CHECK17-NEXT: entry: 9108 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 9109 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 9110 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9111 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 9112 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9113 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9114 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 9115 // CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 9116 // CHECK17-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 9117 // CHECK17-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 9118 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9119 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9120 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9121 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9122 // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 9123 // CHECK17-NEXT: [[LIN2:%.*]] = alloca i32, align 4 9124 // CHECK17-NEXT: [[A3:%.*]] = alloca i32, align 4 9125 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 9126 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 9127 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9128 // CHECK17-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 9129 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9130 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 9131 // CHECK17-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 9132 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 9133 // CHECK17-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 9134 // CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 9135 // CHECK17-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 9136 // CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 9137 // CHECK17-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 9138 // CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 9139 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9140 // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 9141 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 9142 // CHECK17-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 9143 // CHECK17-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 9144 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9145 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 9146 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9147 // CHECK17: cond.true: 9148 // CHECK17-NEXT: br label [[COND_END:%.*]] 9149 // CHECK17: cond.false: 9150 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9151 // CHECK17-NEXT: br label [[COND_END]] 9152 // CHECK17: cond.end: 9153 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 9154 // CHECK17-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 9155 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 9156 // CHECK17-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 9157 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9158 // CHECK17: omp.inner.for.cond: 9159 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17:![0-9]+]] 9160 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP17]] 9161 // CHECK17-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 9162 // CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9163 // CHECK17: omp.inner.for.body: 9164 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 9165 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 9166 // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 9167 // CHECK17-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP17]] 9168 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP17]] 9169 // CHECK17-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 9170 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 9171 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]] 9172 // CHECK17-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 9173 // CHECK17-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 9174 // CHECK17-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 9175 // CHECK17-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP17]] 9176 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP17]] 9177 // CHECK17-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 9178 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 9179 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]] 9180 // CHECK17-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 9181 // CHECK17-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 9182 // CHECK17-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 9183 // CHECK17-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP17]] 9184 // CHECK17-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP17]] 9185 // CHECK17-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 9186 // CHECK17-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 9187 // CHECK17-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 9188 // CHECK17-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP17]] 9189 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9190 // CHECK17: omp.body.continue: 9191 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9192 // CHECK17: omp.inner.for.inc: 9193 // CHECK17-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 9194 // CHECK17-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 9195 // CHECK17-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 9196 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 9197 // CHECK17: omp.inner.for.end: 9198 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9199 // CHECK17: omp.loop.exit: 9200 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 9201 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9202 // CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 9203 // CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9204 // CHECK17: .omp.final.then: 9205 // CHECK17-NEXT: store i64 400, ptr [[IT]], align 8 9206 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9207 // CHECK17: .omp.final.done: 9208 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9209 // CHECK17-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 9210 // CHECK17-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 9211 // CHECK17: .omp.linear.pu: 9212 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 9213 // CHECK17-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 9214 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 9215 // CHECK17-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 9216 // CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 9217 // CHECK17: .omp.linear.pu.done: 9218 // CHECK17-NEXT: ret void 9219 // 9220 // 9221 // CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv 9222 // CHECK17-SAME: () #[[ATTR2:[0-9]+]] { 9223 // CHECK17-NEXT: entry: 9224 // CHECK17-NEXT: ret i64 0 9225 // 9226 // 9227 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 9228 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 9229 // CHECK17-NEXT: entry: 9230 // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 9231 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9232 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9233 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9234 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9235 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 9236 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9237 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9238 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 9239 // CHECK17-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 9240 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 9241 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 9242 // CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 9243 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 9244 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) 9245 // CHECK17-NEXT: ret void 9246 // 9247 // 9248 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined 9249 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 9250 // CHECK17-NEXT: entry: 9251 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 9252 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 9253 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9254 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9255 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9256 // CHECK17-NEXT: [[TMP:%.*]] = alloca i16, align 2 9257 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9258 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9259 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9260 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9261 // CHECK17-NEXT: [[IT:%.*]] = alloca i16, align 2 9262 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 9263 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 9264 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9265 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9266 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 9267 // CHECK17-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 9268 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 9269 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9270 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 9271 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 9272 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 9273 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9274 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 9275 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9276 // CHECK17: cond.true: 9277 // CHECK17-NEXT: br label [[COND_END:%.*]] 9278 // CHECK17: cond.false: 9279 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9280 // CHECK17-NEXT: br label [[COND_END]] 9281 // CHECK17: cond.end: 9282 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9283 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 9284 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 9285 // CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 9286 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9287 // CHECK17: omp.inner.for.cond: 9288 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] 9289 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] 9290 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9291 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9292 // CHECK17: omp.inner.for.body: 9293 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 9294 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 9295 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 9296 // CHECK17-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 9297 // CHECK17-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP20]] 9298 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]] 9299 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 9300 // CHECK17-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]] 9301 // CHECK17-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP20]] 9302 // CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 9303 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 9304 // CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 9305 // CHECK17-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP20]] 9306 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9307 // CHECK17: omp.body.continue: 9308 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9309 // CHECK17: omp.inner.for.inc: 9310 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 9311 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 9312 // CHECK17-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 9313 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 9314 // CHECK17: omp.inner.for.end: 9315 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9316 // CHECK17: omp.loop.exit: 9317 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 9318 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9319 // CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 9320 // CHECK17-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9321 // CHECK17: .omp.final.then: 9322 // CHECK17-NEXT: store i16 22, ptr [[IT]], align 2 9323 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9324 // CHECK17: .omp.final.done: 9325 // CHECK17-NEXT: ret void 9326 // 9327 // 9328 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 9329 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 9330 // CHECK17-NEXT: entry: 9331 // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 9332 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9333 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 9334 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9335 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 9336 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 9337 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9338 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 9339 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 9340 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 9341 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 9342 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9343 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 9344 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 9345 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9346 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 9347 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 9348 // CHECK17-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 9349 // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 9350 // CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 9351 // CHECK17-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 9352 // CHECK17-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 9353 // CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 9354 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 9355 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 9356 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 9357 // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 9358 // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 9359 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 9360 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 9361 // CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 9362 // CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 9363 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 9364 // CHECK17-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 9365 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 9366 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 9367 // CHECK17-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 9368 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 9369 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]]) 9370 // CHECK17-NEXT: ret void 9371 // 9372 // 9373 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined 9374 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 9375 // CHECK17-NEXT: entry: 9376 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 9377 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 9378 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9379 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 9380 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9381 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 9382 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 9383 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9384 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 9385 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 9386 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 9387 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 9388 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9389 // CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1 9390 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9391 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9392 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9393 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9394 // CHECK17-NEXT: [[IT:%.*]] = alloca i8, align 1 9395 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 9396 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 9397 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9398 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 9399 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 9400 // CHECK17-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 9401 // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 9402 // CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 9403 // CHECK17-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 9404 // CHECK17-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 9405 // CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 9406 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 9407 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 9408 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 9409 // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 9410 // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 9411 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 9412 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 9413 // CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 9414 // CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 9415 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 9416 // CHECK17-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 9417 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 9418 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9419 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 9420 // CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 9421 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 9422 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 9423 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 9424 // CHECK17: omp.dispatch.cond: 9425 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9426 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 9427 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9428 // CHECK17: cond.true: 9429 // CHECK17-NEXT: br label [[COND_END:%.*]] 9430 // CHECK17: cond.false: 9431 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9432 // CHECK17-NEXT: br label [[COND_END]] 9433 // CHECK17: cond.end: 9434 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 9435 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 9436 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 9437 // CHECK17-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 9438 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 9439 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9440 // CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 9441 // CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 9442 // CHECK17: omp.dispatch.body: 9443 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9444 // CHECK17: omp.inner.for.cond: 9445 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] 9446 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] 9447 // CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 9448 // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9449 // CHECK17: omp.inner.for.body: 9450 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 9451 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 9452 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 9453 // CHECK17-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 9454 // CHECK17-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP23]] 9455 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] 9456 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 9457 // CHECK17-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] 9458 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 9459 // CHECK17-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] 9460 // CHECK17-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 9461 // CHECK17-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 9462 // CHECK17-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 9463 // CHECK17-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] 9464 // CHECK17-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 9465 // CHECK17-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]] 9466 // CHECK17-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 9467 // CHECK17-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 9468 // CHECK17-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 9469 // CHECK17-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]] 9470 // CHECK17-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 9471 // CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 9472 // CHECK17-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] 9473 // CHECK17-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 9474 // CHECK17-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] 9475 // CHECK17-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 9476 // CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]] 9477 // CHECK17-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3 9478 // CHECK17-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]] 9479 // CHECK17-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 9480 // CHECK17-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]] 9481 // CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 9482 // CHECK17-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP23]] 9483 // CHECK17-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 9484 // CHECK17-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP23]] 9485 // CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 9486 // CHECK17-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP23]] 9487 // CHECK17-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 9488 // CHECK17-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 9489 // CHECK17-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 9490 // CHECK17-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP23]] 9491 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9492 // CHECK17: omp.body.continue: 9493 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9494 // CHECK17: omp.inner.for.inc: 9495 // CHECK17-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 9496 // CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 9497 // CHECK17-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 9498 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] 9499 // CHECK17: omp.inner.for.end: 9500 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 9501 // CHECK17: omp.dispatch.inc: 9502 // CHECK17-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 9503 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 9504 // CHECK17-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 9505 // CHECK17-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 9506 // CHECK17-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9507 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 9508 // CHECK17-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 9509 // CHECK17-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 9510 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 9511 // CHECK17: omp.dispatch.end: 9512 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 9513 // CHECK17-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9514 // CHECK17-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 9515 // CHECK17-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9516 // CHECK17: .omp.final.then: 9517 // CHECK17-NEXT: store i8 96, ptr [[IT]], align 1 9518 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9519 // CHECK17: .omp.final.done: 9520 // CHECK17-NEXT: ret void 9521 // 9522 // 9523 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 9524 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 9525 // CHECK17-NEXT: entry: 9526 // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 9527 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9528 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9529 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 9530 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 9531 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9532 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9533 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 9534 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 9535 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9536 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9537 // CHECK17-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 9538 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 9539 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 9540 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 9541 // CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 9542 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 9543 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 9544 // CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 9545 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 9546 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 9547 // CHECK17-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 9548 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 9549 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]]) 9550 // CHECK17-NEXT: ret void 9551 // 9552 // 9553 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined 9554 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 9555 // CHECK17-NEXT: entry: 9556 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 9557 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 9558 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9559 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9560 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 9561 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 9562 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9563 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 9564 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 9565 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 9566 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9567 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9568 // CHECK17-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 9569 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 9570 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 9571 // CHECK17-NEXT: ret void 9572 // 9573 // 9574 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 9575 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 9576 // CHECK17-NEXT: entry: 9577 // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 9578 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 9579 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 9580 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9581 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9582 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 9583 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 9584 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 9585 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 9586 // CHECK17-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 9587 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 9588 // CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 9589 // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 9590 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 9591 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 9592 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 9593 // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 9594 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 9595 // CHECK17-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 9596 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8 9597 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) 9598 // CHECK17-NEXT: ret void 9599 // 9600 // 9601 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined 9602 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 9603 // CHECK17-NEXT: entry: 9604 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 9605 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 9606 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 9607 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 9608 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9609 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9610 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 9611 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9612 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 9613 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9614 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9615 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9616 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9617 // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 9618 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 9619 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 9620 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 9621 // CHECK17-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 9622 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 9623 // CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 9624 // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 9625 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 9626 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 9627 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 9628 // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 9629 // CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 9630 // CHECK17-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 9631 // CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 9632 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9633 // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 9634 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 9635 // CHECK17-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 9636 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9637 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 9638 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9639 // CHECK17: cond.true: 9640 // CHECK17-NEXT: br label [[COND_END:%.*]] 9641 // CHECK17: cond.false: 9642 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9643 // CHECK17-NEXT: br label [[COND_END]] 9644 // CHECK17: cond.end: 9645 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 9646 // CHECK17-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 9647 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 9648 // CHECK17-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8 9649 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9650 // CHECK17: omp.inner.for.cond: 9651 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26:![0-9]+]] 9652 // CHECK17-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP26]] 9653 // CHECK17-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 9654 // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9655 // CHECK17: omp.inner.for.body: 9656 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 9657 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 9658 // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 9659 // CHECK17-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP26]] 9660 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] 9661 // CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 9662 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 9663 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 9664 // CHECK17-NEXT: store double [[ADD]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP26]] 9665 // CHECK17-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 9666 // CHECK17-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP26]] 9667 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 9668 // CHECK17-NEXT: store double [[INC]], ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP26]] 9669 // CHECK17-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 9670 // CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 9671 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]] 9672 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 9673 // CHECK17-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP26]] 9674 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9675 // CHECK17: omp.body.continue: 9676 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9677 // CHECK17: omp.inner.for.inc: 9678 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 9679 // CHECK17-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 9680 // CHECK17-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 9681 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] 9682 // CHECK17: omp.inner.for.end: 9683 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9684 // CHECK17: omp.loop.exit: 9685 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 9686 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9687 // CHECK17-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 9688 // CHECK17-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9689 // CHECK17: .omp.final.then: 9690 // CHECK17-NEXT: store i64 400, ptr [[IT]], align 8 9691 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9692 // CHECK17: .omp.final.done: 9693 // CHECK17-NEXT: ret void 9694 // 9695 // 9696 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 9697 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 9698 // CHECK17-NEXT: entry: 9699 // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 9700 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9701 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9702 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 9703 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9704 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9705 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 9706 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9707 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9708 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 9709 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 9710 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 9711 // CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 9712 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 9713 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 9714 // CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 9715 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 9716 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) 9717 // CHECK17-NEXT: ret void 9718 // 9719 // 9720 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined 9721 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 9722 // CHECK17-NEXT: entry: 9723 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 9724 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 9725 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9726 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9727 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 9728 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9729 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 9730 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9731 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9732 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9733 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9734 // CHECK17-NEXT: [[I:%.*]] = alloca i64, align 8 9735 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 9736 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 9737 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9738 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9739 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 9740 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 9741 // CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 9742 // CHECK17-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 9743 // CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 9744 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9745 // CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 9746 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 9747 // CHECK17-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 9748 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9749 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 9750 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9751 // CHECK17: cond.true: 9752 // CHECK17-NEXT: br label [[COND_END:%.*]] 9753 // CHECK17: cond.false: 9754 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9755 // CHECK17-NEXT: br label [[COND_END]] 9756 // CHECK17: cond.end: 9757 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 9758 // CHECK17-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 9759 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 9760 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 9761 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9762 // CHECK17: omp.inner.for.cond: 9763 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29:![0-9]+]] 9764 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP29]] 9765 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 9766 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9767 // CHECK17: omp.inner.for.body: 9768 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 9769 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 9770 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 9771 // CHECK17-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP29]] 9772 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP29]] 9773 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 9774 // CHECK17-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP29]] 9775 // CHECK17-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] 9776 // CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 9777 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 9778 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 9779 // CHECK17-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] 9780 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 9781 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP29]] 9782 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 9783 // CHECK17-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP29]] 9784 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9785 // CHECK17: omp.body.continue: 9786 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9787 // CHECK17: omp.inner.for.inc: 9788 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 9789 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 9790 // CHECK17-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 9791 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] 9792 // CHECK17: omp.inner.for.end: 9793 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9794 // CHECK17: omp.loop.exit: 9795 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 9796 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9797 // CHECK17-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 9798 // CHECK17-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9799 // CHECK17: .omp.final.then: 9800 // CHECK17-NEXT: store i64 11, ptr [[I]], align 8 9801 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9802 // CHECK17: .omp.final.done: 9803 // CHECK17-NEXT: ret void 9804 // 9805 // 9806 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 9807 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { 9808 // CHECK19-NEXT: entry: 9809 // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 9810 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 9811 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) 9812 // CHECK19-NEXT: ret void 9813 // 9814 // 9815 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined 9816 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 9817 // CHECK19-NEXT: entry: 9818 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 9819 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 9820 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9821 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 9822 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9823 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9824 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9825 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9826 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 9827 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 9828 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 9829 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 9830 // CHECK19-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 9831 // CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 9832 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9833 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 9834 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 9835 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 9836 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9837 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 9838 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9839 // CHECK19: cond.true: 9840 // CHECK19-NEXT: br label [[COND_END:%.*]] 9841 // CHECK19: cond.false: 9842 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9843 // CHECK19-NEXT: br label [[COND_END]] 9844 // CHECK19: cond.end: 9845 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9846 // CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 9847 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 9848 // CHECK19-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 9849 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9850 // CHECK19: omp.inner.for.cond: 9851 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 9852 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] 9853 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9854 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9855 // CHECK19: omp.inner.for.body: 9856 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 9857 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 9858 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 9859 // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] 9860 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9861 // CHECK19: omp.body.continue: 9862 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9863 // CHECK19: omp.inner.for.inc: 9864 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 9865 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 9866 // CHECK19-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 9867 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 9868 // CHECK19: omp.inner.for.end: 9869 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9870 // CHECK19: omp.loop.exit: 9871 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 9872 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9873 // CHECK19-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 9874 // CHECK19-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9875 // CHECK19: .omp.final.then: 9876 // CHECK19-NEXT: store i32 33, ptr [[I]], align 4 9877 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 9878 // CHECK19: .omp.final.done: 9879 // CHECK19-NEXT: ret void 9880 // 9881 // 9882 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 9883 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 9884 // CHECK19-NEXT: entry: 9885 // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 9886 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9887 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 9888 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9889 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9890 // CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 9891 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9892 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 9893 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 9894 // CHECK19-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 9895 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 9896 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 9897 // CHECK19-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 9898 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 9899 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 9900 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 9901 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 9902 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 9903 // CHECK19-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 9904 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4 9905 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 9906 // CHECK19-NEXT: ret void 9907 // 9908 // 9909 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined 9910 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 9911 // CHECK19-NEXT: entry: 9912 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 9913 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 9914 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9915 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 9916 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9917 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9918 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 9919 // CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 9920 // CHECK19-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 9921 // CHECK19-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 9922 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9923 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9924 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9925 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9926 // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 9927 // CHECK19-NEXT: [[LIN2:%.*]] = alloca i32, align 4 9928 // CHECK19-NEXT: [[A3:%.*]] = alloca i32, align 4 9929 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 9930 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 9931 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 9932 // CHECK19-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 9933 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 9934 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 9935 // CHECK19-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 9936 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 9937 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 9938 // CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 9939 // CHECK19-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 9940 // CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 9941 // CHECK19-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 9942 // CHECK19-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 9943 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9944 // CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 9945 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 9946 // CHECK19-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 9947 // CHECK19-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 9948 // CHECK19-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9949 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 9950 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9951 // CHECK19: cond.true: 9952 // CHECK19-NEXT: br label [[COND_END:%.*]] 9953 // CHECK19: cond.false: 9954 // CHECK19-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9955 // CHECK19-NEXT: br label [[COND_END]] 9956 // CHECK19: cond.end: 9957 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 9958 // CHECK19-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 9959 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 9960 // CHECK19-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 9961 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9962 // CHECK19: omp.inner.for.cond: 9963 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]] 9964 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]] 9965 // CHECK19-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 9966 // CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9967 // CHECK19: omp.inner.for.body: 9968 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 9969 // CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 9970 // CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 9971 // CHECK19-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP18]] 9972 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP18]] 9973 // CHECK19-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 9974 // CHECK19-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 9975 // CHECK19-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]] 9976 // CHECK19-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 9977 // CHECK19-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 9978 // CHECK19-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 9979 // CHECK19-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP18]] 9980 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP18]] 9981 // CHECK19-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 9982 // CHECK19-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 9983 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]] 9984 // CHECK19-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 9985 // CHECK19-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 9986 // CHECK19-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 9987 // CHECK19-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP18]] 9988 // CHECK19-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]] 9989 // CHECK19-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 9990 // CHECK19-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 9991 // CHECK19-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 9992 // CHECK19-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]] 9993 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9994 // CHECK19: omp.body.continue: 9995 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9996 // CHECK19: omp.inner.for.inc: 9997 // CHECK19-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 9998 // CHECK19-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 9999 // CHECK19-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 10000 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 10001 // CHECK19: omp.inner.for.end: 10002 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10003 // CHECK19: omp.loop.exit: 10004 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 10005 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10006 // CHECK19-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 10007 // CHECK19-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10008 // CHECK19: .omp.final.then: 10009 // CHECK19-NEXT: store i64 400, ptr [[IT]], align 8 10010 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10011 // CHECK19: .omp.final.done: 10012 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10013 // CHECK19-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 10014 // CHECK19-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 10015 // CHECK19: .omp.linear.pu: 10016 // CHECK19-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 10017 // CHECK19-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 10018 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 10019 // CHECK19-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 10020 // CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 10021 // CHECK19: .omp.linear.pu.done: 10022 // CHECK19-NEXT: ret void 10023 // 10024 // 10025 // CHECK19-LABEL: define {{[^@]+}}@_Z7get_valv 10026 // CHECK19-SAME: () #[[ATTR2:[0-9]+]] { 10027 // CHECK19-NEXT: entry: 10028 // CHECK19-NEXT: ret i64 0 10029 // 10030 // 10031 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 10032 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 10033 // CHECK19-NEXT: entry: 10034 // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 10035 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10036 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10037 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10038 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10039 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 10040 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10041 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 10042 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 10043 // CHECK19-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 10044 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 10045 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 10046 // CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 10047 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 10048 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) 10049 // CHECK19-NEXT: ret void 10050 // 10051 // 10052 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined 10053 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 10054 // CHECK19-NEXT: entry: 10055 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 10056 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 10057 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10058 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10059 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10060 // CHECK19-NEXT: [[TMP:%.*]] = alloca i16, align 2 10061 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10062 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10063 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10064 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10065 // CHECK19-NEXT: [[IT:%.*]] = alloca i16, align 2 10066 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 10067 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 10068 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10069 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 10070 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 10071 // CHECK19-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 10072 // CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 10073 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10074 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 10075 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 10076 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 10077 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10078 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 10079 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10080 // CHECK19: cond.true: 10081 // CHECK19-NEXT: br label [[COND_END:%.*]] 10082 // CHECK19: cond.false: 10083 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10084 // CHECK19-NEXT: br label [[COND_END]] 10085 // CHECK19: cond.end: 10086 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10087 // CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 10088 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 10089 // CHECK19-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 10090 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10091 // CHECK19: omp.inner.for.cond: 10092 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] 10093 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] 10094 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10095 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10096 // CHECK19: omp.inner.for.body: 10097 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 10098 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 10099 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 10100 // CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 10101 // CHECK19-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP21]] 10102 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] 10103 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 10104 // CHECK19-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] 10105 // CHECK19-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]] 10106 // CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 10107 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 10108 // CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 10109 // CHECK19-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]] 10110 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10111 // CHECK19: omp.body.continue: 10112 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10113 // CHECK19: omp.inner.for.inc: 10114 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 10115 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 10116 // CHECK19-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 10117 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 10118 // CHECK19: omp.inner.for.end: 10119 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10120 // CHECK19: omp.loop.exit: 10121 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 10122 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10123 // CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 10124 // CHECK19-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10125 // CHECK19: .omp.final.then: 10126 // CHECK19-NEXT: store i16 22, ptr [[IT]], align 2 10127 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10128 // CHECK19: .omp.final.done: 10129 // CHECK19-NEXT: ret void 10130 // 10131 // 10132 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 10133 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 10134 // CHECK19-NEXT: entry: 10135 // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 10136 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10137 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 10138 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10139 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 10140 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 10141 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10142 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 10143 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 10144 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 10145 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 10146 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10147 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 10148 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 10149 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10150 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 10151 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 10152 // CHECK19-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 10153 // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 10154 // CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 10155 // CHECK19-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 10156 // CHECK19-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 10157 // CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 10158 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 10159 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 10160 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 10161 // CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 10162 // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 10163 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 10164 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 10165 // CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 10166 // CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 10167 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 10168 // CHECK19-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 10169 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 10170 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 10171 // CHECK19-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 10172 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 10173 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]]) 10174 // CHECK19-NEXT: ret void 10175 // 10176 // 10177 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined 10178 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 10179 // CHECK19-NEXT: entry: 10180 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 10181 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 10182 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10183 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 10184 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10185 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 10186 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 10187 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10188 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 10189 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 10190 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 10191 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 10192 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10193 // CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1 10194 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10195 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10196 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10197 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10198 // CHECK19-NEXT: [[IT:%.*]] = alloca i8, align 1 10199 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 10200 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 10201 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10202 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 10203 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 10204 // CHECK19-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 10205 // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 10206 // CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 10207 // CHECK19-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 10208 // CHECK19-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 10209 // CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 10210 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 10211 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 10212 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 10213 // CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 10214 // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 10215 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 10216 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 10217 // CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 10218 // CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 10219 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 10220 // CHECK19-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 10221 // CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 10222 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10223 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 10224 // CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 10225 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 10226 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 10227 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 10228 // CHECK19: omp.dispatch.cond: 10229 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10230 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 10231 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10232 // CHECK19: cond.true: 10233 // CHECK19-NEXT: br label [[COND_END:%.*]] 10234 // CHECK19: cond.false: 10235 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10236 // CHECK19-NEXT: br label [[COND_END]] 10237 // CHECK19: cond.end: 10238 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 10239 // CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 10240 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 10241 // CHECK19-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 10242 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 10243 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10244 // CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 10245 // CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 10246 // CHECK19: omp.dispatch.body: 10247 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10248 // CHECK19: omp.inner.for.cond: 10249 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] 10250 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]] 10251 // CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 10252 // CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10253 // CHECK19: omp.inner.for.body: 10254 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 10255 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 10256 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 10257 // CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 10258 // CHECK19-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP24]] 10259 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] 10260 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 10261 // CHECK19-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] 10262 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 10263 // CHECK19-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 10264 // CHECK19-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 10265 // CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 10266 // CHECK19-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 10267 // CHECK19-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 10268 // CHECK19-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 10269 // CHECK19-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]] 10270 // CHECK19-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 10271 // CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 10272 // CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 10273 // CHECK19-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]] 10274 // CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 10275 // CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 10276 // CHECK19-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] 10277 // CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 10278 // CHECK19-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] 10279 // CHECK19-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 10280 // CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]] 10281 // CHECK19-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3 10282 // CHECK19-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]] 10283 // CHECK19-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 10284 // CHECK19-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]] 10285 // CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 10286 // CHECK19-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP24]] 10287 // CHECK19-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 10288 // CHECK19-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP24]] 10289 // CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 10290 // CHECK19-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP24]] 10291 // CHECK19-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 10292 // CHECK19-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 10293 // CHECK19-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 10294 // CHECK19-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP24]] 10295 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10296 // CHECK19: omp.body.continue: 10297 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10298 // CHECK19: omp.inner.for.inc: 10299 // CHECK19-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 10300 // CHECK19-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 10301 // CHECK19-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 10302 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 10303 // CHECK19: omp.inner.for.end: 10304 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 10305 // CHECK19: omp.dispatch.inc: 10306 // CHECK19-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 10307 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 10308 // CHECK19-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 10309 // CHECK19-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 10310 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10311 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 10312 // CHECK19-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 10313 // CHECK19-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 10314 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 10315 // CHECK19: omp.dispatch.end: 10316 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 10317 // CHECK19-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10318 // CHECK19-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 10319 // CHECK19-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10320 // CHECK19: .omp.final.then: 10321 // CHECK19-NEXT: store i8 96, ptr [[IT]], align 1 10322 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10323 // CHECK19: .omp.final.done: 10324 // CHECK19-NEXT: ret void 10325 // 10326 // 10327 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 10328 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10329 // CHECK19-NEXT: entry: 10330 // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 10331 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10332 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10333 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 10334 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 10335 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10336 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10337 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 10338 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 10339 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10340 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 10341 // CHECK19-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 10342 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 10343 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 10344 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 10345 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 10346 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 10347 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 10348 // CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 10349 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 10350 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 10351 // CHECK19-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 10352 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 10353 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]]) 10354 // CHECK19-NEXT: ret void 10355 // 10356 // 10357 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined 10358 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10359 // CHECK19-NEXT: entry: 10360 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 10361 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 10362 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10363 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10364 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 10365 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 10366 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10367 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 10368 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 10369 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 10370 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10371 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 10372 // CHECK19-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 10373 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 10374 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 10375 // CHECK19-NEXT: ret void 10376 // 10377 // 10378 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 10379 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 10380 // CHECK19-NEXT: entry: 10381 // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 10382 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 10383 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 10384 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10385 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10386 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 10387 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 10388 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 10389 // CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 10390 // CHECK19-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 10391 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 10392 // CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 10393 // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 10394 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 10395 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 10396 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 10397 // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 10398 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 10399 // CHECK19-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 10400 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 10401 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]]) 10402 // CHECK19-NEXT: ret void 10403 // 10404 // 10405 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined 10406 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 10407 // CHECK19-NEXT: entry: 10408 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 10409 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 10410 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 10411 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 10412 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10413 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10414 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 10415 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 10416 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 10417 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 10418 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 10419 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 10420 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10421 // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 10422 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 10423 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 10424 // CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 10425 // CHECK19-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 10426 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 10427 // CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 10428 // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 10429 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 10430 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 10431 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 10432 // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 10433 // CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 10434 // CHECK19-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 10435 // CHECK19-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 10436 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10437 // CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 10438 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 10439 // CHECK19-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 10440 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 10441 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 10442 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10443 // CHECK19: cond.true: 10444 // CHECK19-NEXT: br label [[COND_END:%.*]] 10445 // CHECK19: cond.false: 10446 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 10447 // CHECK19-NEXT: br label [[COND_END]] 10448 // CHECK19: cond.end: 10449 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 10450 // CHECK19-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 10451 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 10452 // CHECK19-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8 10453 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10454 // CHECK19: omp.inner.for.cond: 10455 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27:![0-9]+]] 10456 // CHECK19-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP27]] 10457 // CHECK19-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 10458 // CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10459 // CHECK19: omp.inner.for.body: 10460 // CHECK19-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 10461 // CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 10462 // CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 10463 // CHECK19-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP27]] 10464 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 10465 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 10466 // CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 10467 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 10468 // CHECK19-NEXT: store double [[ADD]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP27]] 10469 // CHECK19-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 10470 // CHECK19-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP27]] 10471 // CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 10472 // CHECK19-NEXT: store double [[INC]], ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP27]] 10473 // CHECK19-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 10474 // CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 10475 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]] 10476 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 10477 // CHECK19-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP27]] 10478 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10479 // CHECK19: omp.body.continue: 10480 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10481 // CHECK19: omp.inner.for.inc: 10482 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 10483 // CHECK19-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 10484 // CHECK19-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 10485 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 10486 // CHECK19: omp.inner.for.end: 10487 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10488 // CHECK19: omp.loop.exit: 10489 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 10490 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10491 // CHECK19-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 10492 // CHECK19-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10493 // CHECK19: .omp.final.then: 10494 // CHECK19-NEXT: store i64 400, ptr [[IT]], align 8 10495 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10496 // CHECK19: .omp.final.done: 10497 // CHECK19-NEXT: ret void 10498 // 10499 // 10500 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 10501 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10502 // CHECK19-NEXT: entry: 10503 // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 10504 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10505 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10506 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 10507 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10508 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10509 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 10510 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10511 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 10512 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 10513 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 10514 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 10515 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 10516 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 10517 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 10518 // CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 10519 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 10520 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) 10521 // CHECK19-NEXT: ret void 10522 // 10523 // 10524 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined 10525 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10526 // CHECK19-NEXT: entry: 10527 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 10528 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 10529 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10530 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10531 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 10532 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 10533 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 10534 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 10535 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 10536 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 10537 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10538 // CHECK19-NEXT: [[I:%.*]] = alloca i64, align 8 10539 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 10540 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 10541 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10542 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 10543 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 10544 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 10545 // CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 10546 // CHECK19-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 10547 // CHECK19-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 10548 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10549 // CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 10550 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 10551 // CHECK19-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 10552 // CHECK19-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 10553 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 10554 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10555 // CHECK19: cond.true: 10556 // CHECK19-NEXT: br label [[COND_END:%.*]] 10557 // CHECK19: cond.false: 10558 // CHECK19-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 10559 // CHECK19-NEXT: br label [[COND_END]] 10560 // CHECK19: cond.end: 10561 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 10562 // CHECK19-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 10563 // CHECK19-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 10564 // CHECK19-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 10565 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10566 // CHECK19: omp.inner.for.cond: 10567 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30:![0-9]+]] 10568 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP30]] 10569 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 10570 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10571 // CHECK19: omp.inner.for.body: 10572 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 10573 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 10574 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 10575 // CHECK19-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP30]] 10576 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP30]] 10577 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 10578 // CHECK19-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP30]] 10579 // CHECK19-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] 10580 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 10581 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 10582 // CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 10583 // CHECK19-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] 10584 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 10585 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP30]] 10586 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 10587 // CHECK19-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP30]] 10588 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10589 // CHECK19: omp.body.continue: 10590 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10591 // CHECK19: omp.inner.for.inc: 10592 // CHECK19-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 10593 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 10594 // CHECK19-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 10595 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 10596 // CHECK19: omp.inner.for.end: 10597 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10598 // CHECK19: omp.loop.exit: 10599 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 10600 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10601 // CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 10602 // CHECK19-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10603 // CHECK19: .omp.final.then: 10604 // CHECK19-NEXT: store i64 11, ptr [[I]], align 8 10605 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10606 // CHECK19: .omp.final.done: 10607 // CHECK19-NEXT: ret void 10608 // 10609 // 10610 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 10611 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { 10612 // CHECK21-NEXT: entry: 10613 // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 10614 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 10615 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) 10616 // CHECK21-NEXT: ret void 10617 // 10618 // 10619 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined 10620 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 10621 // CHECK21-NEXT: entry: 10622 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 10623 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 10624 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10625 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 10626 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10627 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10628 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10629 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10630 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 10631 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 10632 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 10633 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 10634 // CHECK21-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 10635 // CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 10636 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10637 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 10638 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 10639 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 10640 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10641 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 10642 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10643 // CHECK21: cond.true: 10644 // CHECK21-NEXT: br label [[COND_END:%.*]] 10645 // CHECK21: cond.false: 10646 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10647 // CHECK21-NEXT: br label [[COND_END]] 10648 // CHECK21: cond.end: 10649 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10650 // CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 10651 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 10652 // CHECK21-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 10653 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10654 // CHECK21: omp.inner.for.cond: 10655 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 10656 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 10657 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10658 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10659 // CHECK21: omp.inner.for.body: 10660 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 10661 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 10662 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 10663 // CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 10664 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10665 // CHECK21: omp.body.continue: 10666 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10667 // CHECK21: omp.inner.for.inc: 10668 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 10669 // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 10670 // CHECK21-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 10671 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 10672 // CHECK21: omp.inner.for.end: 10673 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10674 // CHECK21: omp.loop.exit: 10675 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 10676 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10677 // CHECK21-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 10678 // CHECK21-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10679 // CHECK21: .omp.final.then: 10680 // CHECK21-NEXT: store i32 33, ptr [[I]], align 4 10681 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 10682 // CHECK21: .omp.final.done: 10683 // CHECK21-NEXT: ret void 10684 // 10685 // 10686 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 10687 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 10688 // CHECK21-NEXT: entry: 10689 // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 10690 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10691 // CHECK21-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 10692 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10693 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10694 // CHECK21-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 10695 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10696 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 10697 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 10698 // CHECK21-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 10699 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 10700 // CHECK21-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 10701 // CHECK21-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 10702 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 10703 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 10704 // CHECK21-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 10705 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 10706 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 10707 // CHECK21-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 10708 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8 10709 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 10710 // CHECK21-NEXT: ret void 10711 // 10712 // 10713 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined 10714 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 10715 // CHECK21-NEXT: entry: 10716 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 10717 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 10718 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10719 // CHECK21-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 10720 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10721 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 10722 // CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8 10723 // CHECK21-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 10724 // CHECK21-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 10725 // CHECK21-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 10726 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 10727 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 10728 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 10729 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10730 // CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 8 10731 // CHECK21-NEXT: [[LIN2:%.*]] = alloca i32, align 4 10732 // CHECK21-NEXT: [[A3:%.*]] = alloca i32, align 4 10733 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 10734 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 10735 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 10736 // CHECK21-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 10737 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 10738 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 10739 // CHECK21-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 10740 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 10741 // CHECK21-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 10742 // CHECK21-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 10743 // CHECK21-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 10744 // CHECK21-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 10745 // CHECK21-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 10746 // CHECK21-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 10747 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10748 // CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 10749 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 10750 // CHECK21-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 10751 // CHECK21-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 10752 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 10753 // CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 10754 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10755 // CHECK21: cond.true: 10756 // CHECK21-NEXT: br label [[COND_END:%.*]] 10757 // CHECK21: cond.false: 10758 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 10759 // CHECK21-NEXT: br label [[COND_END]] 10760 // CHECK21: cond.end: 10761 // CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 10762 // CHECK21-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 10763 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 10764 // CHECK21-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 10765 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10766 // CHECK21: omp.inner.for.cond: 10767 // CHECK21-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17:![0-9]+]] 10768 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP17]] 10769 // CHECK21-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 10770 // CHECK21-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10771 // CHECK21: omp.inner.for.body: 10772 // CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 10773 // CHECK21-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 10774 // CHECK21-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 10775 // CHECK21-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP17]] 10776 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP17]] 10777 // CHECK21-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 10778 // CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 10779 // CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]] 10780 // CHECK21-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 10781 // CHECK21-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 10782 // CHECK21-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 10783 // CHECK21-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP17]] 10784 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP17]] 10785 // CHECK21-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 10786 // CHECK21-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 10787 // CHECK21-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]] 10788 // CHECK21-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 10789 // CHECK21-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 10790 // CHECK21-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 10791 // CHECK21-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP17]] 10792 // CHECK21-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP17]] 10793 // CHECK21-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 10794 // CHECK21-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 10795 // CHECK21-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 10796 // CHECK21-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP17]] 10797 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10798 // CHECK21: omp.body.continue: 10799 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10800 // CHECK21: omp.inner.for.inc: 10801 // CHECK21-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 10802 // CHECK21-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 10803 // CHECK21-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 10804 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 10805 // CHECK21: omp.inner.for.end: 10806 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10807 // CHECK21: omp.loop.exit: 10808 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 10809 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10810 // CHECK21-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 10811 // CHECK21-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10812 // CHECK21: .omp.final.then: 10813 // CHECK21-NEXT: store i64 400, ptr [[IT]], align 8 10814 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 10815 // CHECK21: .omp.final.done: 10816 // CHECK21-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10817 // CHECK21-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 10818 // CHECK21-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 10819 // CHECK21: .omp.linear.pu: 10820 // CHECK21-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 10821 // CHECK21-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 10822 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 10823 // CHECK21-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 10824 // CHECK21-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 10825 // CHECK21: .omp.linear.pu.done: 10826 // CHECK21-NEXT: ret void 10827 // 10828 // 10829 // CHECK21-LABEL: define {{[^@]+}}@_Z7get_valv 10830 // CHECK21-SAME: () #[[ATTR2:[0-9]+]] { 10831 // CHECK21-NEXT: entry: 10832 // CHECK21-NEXT: ret i64 0 10833 // 10834 // 10835 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 10836 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 10837 // CHECK21-NEXT: entry: 10838 // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 10839 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10840 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10841 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10842 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10843 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 10844 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 10845 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 10846 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 10847 // CHECK21-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 10848 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 10849 // CHECK21-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 10850 // CHECK21-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 10851 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 10852 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) 10853 // CHECK21-NEXT: ret void 10854 // 10855 // 10856 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined 10857 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 10858 // CHECK21-NEXT: entry: 10859 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 10860 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 10861 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10862 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10863 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10864 // CHECK21-NEXT: [[TMP:%.*]] = alloca i16, align 2 10865 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10866 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10867 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10868 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10869 // CHECK21-NEXT: [[IT:%.*]] = alloca i16, align 2 10870 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 10871 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 10872 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 10873 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 10874 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 10875 // CHECK21-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 10876 // CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 10877 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10878 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 10879 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 10880 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 10881 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10882 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 10883 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10884 // CHECK21: cond.true: 10885 // CHECK21-NEXT: br label [[COND_END:%.*]] 10886 // CHECK21: cond.false: 10887 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10888 // CHECK21-NEXT: br label [[COND_END]] 10889 // CHECK21: cond.end: 10890 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10891 // CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 10892 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 10893 // CHECK21-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 10894 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10895 // CHECK21: omp.inner.for.cond: 10896 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] 10897 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] 10898 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10899 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10900 // CHECK21: omp.inner.for.body: 10901 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 10902 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 10903 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 10904 // CHECK21-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 10905 // CHECK21-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP20]] 10906 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]] 10907 // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 10908 // CHECK21-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]] 10909 // CHECK21-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP20]] 10910 // CHECK21-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 10911 // CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 10912 // CHECK21-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 10913 // CHECK21-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP20]] 10914 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10915 // CHECK21: omp.body.continue: 10916 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10917 // CHECK21: omp.inner.for.inc: 10918 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 10919 // CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 10920 // CHECK21-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 10921 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 10922 // CHECK21: omp.inner.for.end: 10923 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10924 // CHECK21: omp.loop.exit: 10925 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 10926 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10927 // CHECK21-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 10928 // CHECK21-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10929 // CHECK21: .omp.final.then: 10930 // CHECK21-NEXT: store i16 22, ptr [[IT]], align 2 10931 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 10932 // CHECK21: .omp.final.done: 10933 // CHECK21-NEXT: ret void 10934 // 10935 // 10936 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 10937 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 10938 // CHECK21-NEXT: entry: 10939 // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 10940 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10941 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 10942 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10943 // CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 10944 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 10945 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10946 // CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10947 // CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 10948 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 10949 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 10950 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10951 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 10952 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 10953 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 10954 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 10955 // CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 10956 // CHECK21-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 10957 // CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 10958 // CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 10959 // CHECK21-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 10960 // CHECK21-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 10961 // CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 10962 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 10963 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 10964 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 10965 // CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 10966 // CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 10967 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 10968 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 10969 // CHECK21-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 10970 // CHECK21-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 10971 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 10972 // CHECK21-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 10973 // CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 10974 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 10975 // CHECK21-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 10976 // CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 10977 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]]) 10978 // CHECK21-NEXT: ret void 10979 // 10980 // 10981 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined 10982 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 10983 // CHECK21-NEXT: entry: 10984 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 10985 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 10986 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10987 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 10988 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10989 // CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 10990 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 10991 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10992 // CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10993 // CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 10994 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 10995 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 10996 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10997 // CHECK21-NEXT: [[TMP:%.*]] = alloca i8, align 1 10998 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10999 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11000 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11001 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11002 // CHECK21-NEXT: [[IT:%.*]] = alloca i8, align 1 11003 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 11004 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 11005 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 11006 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 11007 // CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 11008 // CHECK21-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 11009 // CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 11010 // CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 11011 // CHECK21-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 11012 // CHECK21-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 11013 // CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 11014 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 11015 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 11016 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 11017 // CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 11018 // CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 11019 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 11020 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 11021 // CHECK21-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 11022 // CHECK21-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 11023 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 11024 // CHECK21-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 11025 // CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 11026 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11027 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 11028 // CHECK21-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 11029 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 11030 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 11031 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 11032 // CHECK21: omp.dispatch.cond: 11033 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11034 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 11035 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11036 // CHECK21: cond.true: 11037 // CHECK21-NEXT: br label [[COND_END:%.*]] 11038 // CHECK21: cond.false: 11039 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11040 // CHECK21-NEXT: br label [[COND_END]] 11041 // CHECK21: cond.end: 11042 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 11043 // CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 11044 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 11045 // CHECK21-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 11046 // CHECK21-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 11047 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11048 // CHECK21-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 11049 // CHECK21-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 11050 // CHECK21: omp.dispatch.body: 11051 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11052 // CHECK21: omp.inner.for.cond: 11053 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] 11054 // CHECK21-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] 11055 // CHECK21-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 11056 // CHECK21-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11057 // CHECK21: omp.inner.for.body: 11058 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 11059 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 11060 // CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 11061 // CHECK21-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 11062 // CHECK21-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP23]] 11063 // CHECK21-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] 11064 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 11065 // CHECK21-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] 11066 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 11067 // CHECK21-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] 11068 // CHECK21-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 11069 // CHECK21-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 11070 // CHECK21-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 11071 // CHECK21-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] 11072 // CHECK21-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 11073 // CHECK21-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]] 11074 // CHECK21-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 11075 // CHECK21-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 11076 // CHECK21-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 11077 // CHECK21-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]] 11078 // CHECK21-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 11079 // CHECK21-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 11080 // CHECK21-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] 11081 // CHECK21-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 11082 // CHECK21-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] 11083 // CHECK21-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 11084 // CHECK21-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]] 11085 // CHECK21-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3 11086 // CHECK21-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]] 11087 // CHECK21-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 11088 // CHECK21-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]] 11089 // CHECK21-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 11090 // CHECK21-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP23]] 11091 // CHECK21-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 11092 // CHECK21-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP23]] 11093 // CHECK21-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 11094 // CHECK21-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP23]] 11095 // CHECK21-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 11096 // CHECK21-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 11097 // CHECK21-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 11098 // CHECK21-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP23]] 11099 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11100 // CHECK21: omp.body.continue: 11101 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11102 // CHECK21: omp.inner.for.inc: 11103 // CHECK21-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 11104 // CHECK21-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 11105 // CHECK21-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 11106 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] 11107 // CHECK21: omp.inner.for.end: 11108 // CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 11109 // CHECK21: omp.dispatch.inc: 11110 // CHECK21-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 11111 // CHECK21-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 11112 // CHECK21-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 11113 // CHECK21-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 11114 // CHECK21-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11115 // CHECK21-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 11116 // CHECK21-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 11117 // CHECK21-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 11118 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND]] 11119 // CHECK21: omp.dispatch.end: 11120 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 11121 // CHECK21-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11122 // CHECK21-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 11123 // CHECK21-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11124 // CHECK21: .omp.final.then: 11125 // CHECK21-NEXT: store i8 96, ptr [[IT]], align 1 11126 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11127 // CHECK21: .omp.final.done: 11128 // CHECK21-NEXT: ret void 11129 // 11130 // 11131 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 11132 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11133 // CHECK21-NEXT: entry: 11134 // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 11135 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11136 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11137 // CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 11138 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 11139 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11140 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11141 // CHECK21-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 11142 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 11143 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 11144 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 11145 // CHECK21-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 11146 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 11147 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 11148 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 11149 // CHECK21-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 11150 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 11151 // CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 11152 // CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 11153 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 11154 // CHECK21-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 11155 // CHECK21-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 11156 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 11157 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]]) 11158 // CHECK21-NEXT: ret void 11159 // 11160 // 11161 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined 11162 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11163 // CHECK21-NEXT: entry: 11164 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 11165 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 11166 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11167 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11168 // CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 11169 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 11170 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11171 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 11172 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 11173 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 11174 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 11175 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 11176 // CHECK21-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 11177 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 11178 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 11179 // CHECK21-NEXT: ret void 11180 // 11181 // 11182 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 11183 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 11184 // CHECK21-NEXT: entry: 11185 // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 11186 // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 11187 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 11188 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 11189 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11190 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 11191 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 11192 // CHECK21-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 11193 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 11194 // CHECK21-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 11195 // CHECK21-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 11196 // CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 11197 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 11198 // CHECK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 11199 // CHECK21-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 11200 // CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 11201 // CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 11202 // CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 11203 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 11204 // CHECK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 11205 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 11206 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 11207 // CHECK21-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8 11208 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4 11209 // CHECK21-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 11210 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 11211 // CHECK21-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 11212 // CHECK21-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i1 11213 // CHECK21-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8 11214 // CHECK21-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 11215 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 11216 // CHECK21-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 11217 // CHECK21-NEXT: [[LOADEDV3:%.*]] = trunc i8 [[TMP9]] to i1 11218 // CHECK21-NEXT: br i1 [[LOADEDV3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11219 // CHECK21: omp_if.then: 11220 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) 11221 // CHECK21-NEXT: br label [[OMP_IF_END:%.*]] 11222 // CHECK21: omp_if.else: 11223 // CHECK21-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 11224 // CHECK21-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 11225 // CHECK21-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 11226 // CHECK21-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) #[[ATTR1:[0-9]+]] 11227 // CHECK21-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 11228 // CHECK21-NEXT: br label [[OMP_IF_END]] 11229 // CHECK21: omp_if.end: 11230 // CHECK21-NEXT: ret void 11231 // 11232 // 11233 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined 11234 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 11235 // CHECK21-NEXT: entry: 11236 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 11237 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 11238 // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 11239 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 11240 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 11241 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11242 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 11243 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 11244 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11245 // CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8 11246 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11247 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11248 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11249 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11250 // CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 8 11251 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 11252 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 11253 // CHECK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 11254 // CHECK21-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 11255 // CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 11256 // CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 11257 // CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 11258 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 11259 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 11260 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 11261 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 11262 // CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 11263 // CHECK21-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 11264 // CHECK21-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 11265 // CHECK21-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 11266 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11267 // CHECK21-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 11268 // CHECK21-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP4]] to i1 11269 // CHECK21-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11270 // CHECK21: omp_if.then: 11271 // CHECK21-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 11272 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 11273 // CHECK21-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 11274 // CHECK21-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11275 // CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 11276 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11277 // CHECK21: cond.true: 11278 // CHECK21-NEXT: br label [[COND_END:%.*]] 11279 // CHECK21: cond.false: 11280 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11281 // CHECK21-NEXT: br label [[COND_END]] 11282 // CHECK21: cond.end: 11283 // CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 11284 // CHECK21-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 11285 // CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 11286 // CHECK21-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV]], align 8 11287 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11288 // CHECK21: omp.inner.for.cond: 11289 // CHECK21-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26:![0-9]+]] 11290 // CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP26]] 11291 // CHECK21-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 11292 // CHECK21-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11293 // CHECK21: omp.inner.for.body: 11294 // CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 11295 // CHECK21-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 11296 // CHECK21-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 11297 // CHECK21-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP26]] 11298 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] 11299 // CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double 11300 // CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 11301 // CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 11302 // CHECK21-NEXT: store double [[ADD]], ptr [[A]], align 8, !nontemporal [[META27:![0-9]+]], !llvm.access.group [[ACC_GRP26]] 11303 // CHECK21-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 11304 // CHECK21-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 8, !nontemporal [[META27]], !llvm.access.group [[ACC_GRP26]] 11305 // CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 11306 // CHECK21-NEXT: store double [[INC]], ptr [[A4]], align 8, !nontemporal [[META27]], !llvm.access.group [[ACC_GRP26]] 11307 // CHECK21-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 11308 // CHECK21-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]] 11309 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP15]] 11310 // CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 11311 // CHECK21-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP26]] 11312 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11313 // CHECK21: omp.body.continue: 11314 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11315 // CHECK21: omp.inner.for.inc: 11316 // CHECK21-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 11317 // CHECK21-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1 11318 // CHECK21-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 11319 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 11320 // CHECK21: omp.inner.for.end: 11321 // CHECK21-NEXT: br label [[OMP_IF_END:%.*]] 11322 // CHECK21: omp_if.else: 11323 // CHECK21-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 11324 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 11325 // CHECK21-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP18]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 11326 // CHECK21-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11327 // CHECK21-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[TMP19]], 3 11328 // CHECK21-NEXT: br i1 [[CMP8]], label [[COND_TRUE9:%.*]], label [[COND_FALSE10:%.*]] 11329 // CHECK21: cond.true9: 11330 // CHECK21-NEXT: br label [[COND_END11:%.*]] 11331 // CHECK21: cond.false10: 11332 // CHECK21-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11333 // CHECK21-NEXT: br label [[COND_END11]] 11334 // CHECK21: cond.end11: 11335 // CHECK21-NEXT: [[COND12:%.*]] = phi i64 [ 3, [[COND_TRUE9]] ], [ [[TMP20]], [[COND_FALSE10]] ] 11336 // CHECK21-NEXT: store i64 [[COND12]], ptr [[DOTOMP_UB]], align 8 11337 // CHECK21-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 11338 // CHECK21-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV]], align 8 11339 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 11340 // CHECK21: omp.inner.for.cond13: 11341 // CHECK21-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 11342 // CHECK21-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11343 // CHECK21-NEXT: [[CMP14:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 11344 // CHECK21-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END29:%.*]] 11345 // CHECK21: omp.inner.for.body15: 11346 // CHECK21-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 11347 // CHECK21-NEXT: [[MUL16:%.*]] = mul i64 [[TMP24]], 400 11348 // CHECK21-NEXT: [[SUB17:%.*]] = sub i64 2000, [[MUL16]] 11349 // CHECK21-NEXT: store i64 [[SUB17]], ptr [[IT]], align 8 11350 // CHECK21-NEXT: [[TMP25:%.*]] = load i32, ptr [[B_ADDR]], align 4 11351 // CHECK21-NEXT: [[CONV18:%.*]] = sitofp i32 [[TMP25]] to double 11352 // CHECK21-NEXT: [[ADD19:%.*]] = fadd double [[CONV18]], 1.500000e+00 11353 // CHECK21-NEXT: [[A20:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 11354 // CHECK21-NEXT: store double [[ADD19]], ptr [[A20]], align 8 11355 // CHECK21-NEXT: [[A21:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 11356 // CHECK21-NEXT: [[TMP26:%.*]] = load double, ptr [[A21]], align 8 11357 // CHECK21-NEXT: [[INC22:%.*]] = fadd double [[TMP26]], 1.000000e+00 11358 // CHECK21-NEXT: store double [[INC22]], ptr [[A21]], align 8 11359 // CHECK21-NEXT: [[CONV23:%.*]] = fptosi double [[INC22]] to i16 11360 // CHECK21-NEXT: [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]] 11361 // CHECK21-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP27]] 11362 // CHECK21-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX24]], i64 1 11363 // CHECK21-NEXT: store i16 [[CONV23]], ptr [[ARRAYIDX25]], align 2 11364 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] 11365 // CHECK21: omp.body.continue26: 11366 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] 11367 // CHECK21: omp.inner.for.inc27: 11368 // CHECK21-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 11369 // CHECK21-NEXT: [[ADD28:%.*]] = add i64 [[TMP28]], 1 11370 // CHECK21-NEXT: store i64 [[ADD28]], ptr [[DOTOMP_IV]], align 8 11371 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP30:![0-9]+]] 11372 // CHECK21: omp.inner.for.end29: 11373 // CHECK21-NEXT: br label [[OMP_IF_END]] 11374 // CHECK21: omp_if.end: 11375 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11376 // CHECK21: omp.loop.exit: 11377 // CHECK21-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 11378 // CHECK21-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4 11379 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]]) 11380 // CHECK21-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11381 // CHECK21-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 11382 // CHECK21-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11383 // CHECK21: .omp.final.then: 11384 // CHECK21-NEXT: store i64 400, ptr [[IT]], align 8 11385 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11386 // CHECK21: .omp.final.done: 11387 // CHECK21-NEXT: ret void 11388 // 11389 // 11390 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 11391 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11392 // CHECK21-NEXT: entry: 11393 // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 11394 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11395 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11396 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 11397 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11398 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11399 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 11400 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 11401 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 11402 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 11403 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 11404 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 11405 // CHECK21-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 11406 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 11407 // CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 11408 // CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 11409 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 11410 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) 11411 // CHECK21-NEXT: ret void 11412 // 11413 // 11414 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined 11415 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11416 // CHECK21-NEXT: entry: 11417 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 11418 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 11419 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11420 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11421 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 11422 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11423 // CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8 11424 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11425 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11426 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11427 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11428 // CHECK21-NEXT: [[I:%.*]] = alloca i64, align 8 11429 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 11430 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 11431 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 11432 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 11433 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 11434 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 11435 // CHECK21-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 11436 // CHECK21-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 11437 // CHECK21-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 11438 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11439 // CHECK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 11440 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 11441 // CHECK21-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 11442 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11443 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 11444 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11445 // CHECK21: cond.true: 11446 // CHECK21-NEXT: br label [[COND_END:%.*]] 11447 // CHECK21: cond.false: 11448 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11449 // CHECK21-NEXT: br label [[COND_END]] 11450 // CHECK21: cond.end: 11451 // CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 11452 // CHECK21-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 11453 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 11454 // CHECK21-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 11455 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11456 // CHECK21: omp.inner.for.cond: 11457 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32:![0-9]+]] 11458 // CHECK21-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP32]] 11459 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 11460 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11461 // CHECK21: omp.inner.for.body: 11462 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32]] 11463 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 11464 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 11465 // CHECK21-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP32]] 11466 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] 11467 // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 11468 // CHECK21-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] 11469 // CHECK21-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] 11470 // CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 11471 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 11472 // CHECK21-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 11473 // CHECK21-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] 11474 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 11475 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] 11476 // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 11477 // CHECK21-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] 11478 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11479 // CHECK21: omp.body.continue: 11480 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11481 // CHECK21: omp.inner.for.inc: 11482 // CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32]] 11483 // CHECK21-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 11484 // CHECK21-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32]] 11485 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] 11486 // CHECK21: omp.inner.for.end: 11487 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11488 // CHECK21: omp.loop.exit: 11489 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 11490 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11491 // CHECK21-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 11492 // CHECK21-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11493 // CHECK21: .omp.final.then: 11494 // CHECK21-NEXT: store i64 11, ptr [[I]], align 8 11495 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11496 // CHECK21: .omp.final.done: 11497 // CHECK21-NEXT: ret void 11498 // 11499 // 11500 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 11501 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { 11502 // CHECK23-NEXT: entry: 11503 // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 11504 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 11505 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) 11506 // CHECK23-NEXT: ret void 11507 // 11508 // 11509 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined 11510 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 11511 // CHECK23-NEXT: entry: 11512 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 11513 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 11514 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11515 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 11516 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11517 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11518 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11519 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11520 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 11521 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 11522 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 11523 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 11524 // CHECK23-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 11525 // CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 11526 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11527 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 11528 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 11529 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 11530 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11531 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 11532 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11533 // CHECK23: cond.true: 11534 // CHECK23-NEXT: br label [[COND_END:%.*]] 11535 // CHECK23: cond.false: 11536 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11537 // CHECK23-NEXT: br label [[COND_END]] 11538 // CHECK23: cond.end: 11539 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 11540 // CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 11541 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 11542 // CHECK23-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 11543 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11544 // CHECK23: omp.inner.for.cond: 11545 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 11546 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] 11547 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 11548 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11549 // CHECK23: omp.inner.for.body: 11550 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 11551 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 11552 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 11553 // CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] 11554 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11555 // CHECK23: omp.body.continue: 11556 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11557 // CHECK23: omp.inner.for.inc: 11558 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 11559 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 11560 // CHECK23-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 11561 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 11562 // CHECK23: omp.inner.for.end: 11563 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11564 // CHECK23: omp.loop.exit: 11565 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 11566 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11567 // CHECK23-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 11568 // CHECK23-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11569 // CHECK23: .omp.final.then: 11570 // CHECK23-NEXT: store i32 33, ptr [[I]], align 4 11571 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 11572 // CHECK23: .omp.final.done: 11573 // CHECK23-NEXT: ret void 11574 // 11575 // 11576 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 11577 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 11578 // CHECK23-NEXT: entry: 11579 // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 11580 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11581 // CHECK23-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 11582 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11583 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11584 // CHECK23-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 11585 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11586 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 11587 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 11588 // CHECK23-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 11589 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11590 // CHECK23-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 11591 // CHECK23-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 11592 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 11593 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 11594 // CHECK23-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 11595 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 11596 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 11597 // CHECK23-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 11598 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4 11599 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 11600 // CHECK23-NEXT: ret void 11601 // 11602 // 11603 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined 11604 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 11605 // CHECK23-NEXT: entry: 11606 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 11607 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 11608 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11609 // CHECK23-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 11610 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11611 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11612 // CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4 11613 // CHECK23-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 11614 // CHECK23-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 11615 // CHECK23-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 11616 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11617 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11618 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11619 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11620 // CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 8 11621 // CHECK23-NEXT: [[LIN2:%.*]] = alloca i32, align 4 11622 // CHECK23-NEXT: [[A3:%.*]] = alloca i32, align 4 11623 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 11624 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 11625 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 11626 // CHECK23-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 11627 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11628 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 11629 // CHECK23-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 11630 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 11631 // CHECK23-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 11632 // CHECK23-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 11633 // CHECK23-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 11634 // CHECK23-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 11635 // CHECK23-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 11636 // CHECK23-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 11637 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11638 // CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 11639 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 11640 // CHECK23-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 11641 // CHECK23-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 11642 // CHECK23-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11643 // CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 11644 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11645 // CHECK23: cond.true: 11646 // CHECK23-NEXT: br label [[COND_END:%.*]] 11647 // CHECK23: cond.false: 11648 // CHECK23-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11649 // CHECK23-NEXT: br label [[COND_END]] 11650 // CHECK23: cond.end: 11651 // CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 11652 // CHECK23-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 11653 // CHECK23-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 11654 // CHECK23-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 11655 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11656 // CHECK23: omp.inner.for.cond: 11657 // CHECK23-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]] 11658 // CHECK23-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]] 11659 // CHECK23-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 11660 // CHECK23-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11661 // CHECK23: omp.inner.for.body: 11662 // CHECK23-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11663 // CHECK23-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 11664 // CHECK23-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 11665 // CHECK23-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP18]] 11666 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP18]] 11667 // CHECK23-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 11668 // CHECK23-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11669 // CHECK23-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]] 11670 // CHECK23-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 11671 // CHECK23-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 11672 // CHECK23-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 11673 // CHECK23-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP18]] 11674 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP18]] 11675 // CHECK23-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 11676 // CHECK23-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11677 // CHECK23-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]] 11678 // CHECK23-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 11679 // CHECK23-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 11680 // CHECK23-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 11681 // CHECK23-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP18]] 11682 // CHECK23-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]] 11683 // CHECK23-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 11684 // CHECK23-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 11685 // CHECK23-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 11686 // CHECK23-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]] 11687 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11688 // CHECK23: omp.body.continue: 11689 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11690 // CHECK23: omp.inner.for.inc: 11691 // CHECK23-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11692 // CHECK23-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 11693 // CHECK23-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11694 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 11695 // CHECK23: omp.inner.for.end: 11696 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11697 // CHECK23: omp.loop.exit: 11698 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 11699 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11700 // CHECK23-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 11701 // CHECK23-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11702 // CHECK23: .omp.final.then: 11703 // CHECK23-NEXT: store i64 400, ptr [[IT]], align 8 11704 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 11705 // CHECK23: .omp.final.done: 11706 // CHECK23-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11707 // CHECK23-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 11708 // CHECK23-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 11709 // CHECK23: .omp.linear.pu: 11710 // CHECK23-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 11711 // CHECK23-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 11712 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 11713 // CHECK23-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 11714 // CHECK23-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 11715 // CHECK23: .omp.linear.pu.done: 11716 // CHECK23-NEXT: ret void 11717 // 11718 // 11719 // CHECK23-LABEL: define {{[^@]+}}@_Z7get_valv 11720 // CHECK23-SAME: () #[[ATTR2:[0-9]+]] { 11721 // CHECK23-NEXT: entry: 11722 // CHECK23-NEXT: ret i64 0 11723 // 11724 // 11725 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 11726 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 11727 // CHECK23-NEXT: entry: 11728 // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 11729 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11730 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11731 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11732 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11733 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 11734 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11735 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 11736 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 11737 // CHECK23-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 11738 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 11739 // CHECK23-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 11740 // CHECK23-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 11741 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 11742 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) 11743 // CHECK23-NEXT: ret void 11744 // 11745 // 11746 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined 11747 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 11748 // CHECK23-NEXT: entry: 11749 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 11750 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 11751 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11752 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11753 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11754 // CHECK23-NEXT: [[TMP:%.*]] = alloca i16, align 2 11755 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11756 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11757 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11758 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11759 // CHECK23-NEXT: [[IT:%.*]] = alloca i16, align 2 11760 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 11761 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 11762 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11763 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 11764 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 11765 // CHECK23-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 11766 // CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 11767 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11768 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 11769 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 11770 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 11771 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11772 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 11773 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11774 // CHECK23: cond.true: 11775 // CHECK23-NEXT: br label [[COND_END:%.*]] 11776 // CHECK23: cond.false: 11777 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11778 // CHECK23-NEXT: br label [[COND_END]] 11779 // CHECK23: cond.end: 11780 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 11781 // CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 11782 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 11783 // CHECK23-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 11784 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11785 // CHECK23: omp.inner.for.cond: 11786 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] 11787 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] 11788 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 11789 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11790 // CHECK23: omp.inner.for.body: 11791 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 11792 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 11793 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 11794 // CHECK23-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 11795 // CHECK23-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP21]] 11796 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] 11797 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 11798 // CHECK23-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] 11799 // CHECK23-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]] 11800 // CHECK23-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 11801 // CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 11802 // CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 11803 // CHECK23-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]] 11804 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11805 // CHECK23: omp.body.continue: 11806 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11807 // CHECK23: omp.inner.for.inc: 11808 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 11809 // CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 11810 // CHECK23-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 11811 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 11812 // CHECK23: omp.inner.for.end: 11813 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11814 // CHECK23: omp.loop.exit: 11815 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 11816 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11817 // CHECK23-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 11818 // CHECK23-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11819 // CHECK23: .omp.final.then: 11820 // CHECK23-NEXT: store i16 22, ptr [[IT]], align 2 11821 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 11822 // CHECK23: .omp.final.done: 11823 // CHECK23-NEXT: ret void 11824 // 11825 // 11826 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 11827 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 11828 // CHECK23-NEXT: entry: 11829 // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 11830 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11831 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 11832 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11833 // CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 11834 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 11835 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11836 // CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 11837 // CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 11838 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 11839 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 11840 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11841 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 11842 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 11843 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11844 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 11845 // CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 11846 // CHECK23-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 11847 // CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 11848 // CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 11849 // CHECK23-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 11850 // CHECK23-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 11851 // CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 11852 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 11853 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 11854 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 11855 // CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 11856 // CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 11857 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 11858 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 11859 // CHECK23-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 11860 // CHECK23-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 11861 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 11862 // CHECK23-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 11863 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 11864 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 11865 // CHECK23-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 11866 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 11867 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]]) 11868 // CHECK23-NEXT: ret void 11869 // 11870 // 11871 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined 11872 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 11873 // CHECK23-NEXT: entry: 11874 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 11875 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 11876 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11877 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 11878 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11879 // CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 11880 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 11881 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11882 // CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 11883 // CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 11884 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 11885 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 11886 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11887 // CHECK23-NEXT: [[TMP:%.*]] = alloca i8, align 1 11888 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11889 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11890 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11891 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11892 // CHECK23-NEXT: [[IT:%.*]] = alloca i8, align 1 11893 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 11894 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 11895 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11896 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 11897 // CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 11898 // CHECK23-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 11899 // CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 11900 // CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 11901 // CHECK23-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 11902 // CHECK23-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 11903 // CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 11904 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 11905 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 11906 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 11907 // CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 11908 // CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 11909 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 11910 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 11911 // CHECK23-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 11912 // CHECK23-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 11913 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 11914 // CHECK23-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 11915 // CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 11916 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11917 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 11918 // CHECK23-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 11919 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 11920 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 11921 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 11922 // CHECK23: omp.dispatch.cond: 11923 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11924 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 11925 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11926 // CHECK23: cond.true: 11927 // CHECK23-NEXT: br label [[COND_END:%.*]] 11928 // CHECK23: cond.false: 11929 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11930 // CHECK23-NEXT: br label [[COND_END]] 11931 // CHECK23: cond.end: 11932 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 11933 // CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 11934 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 11935 // CHECK23-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 11936 // CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 11937 // CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11938 // CHECK23-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 11939 // CHECK23-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 11940 // CHECK23: omp.dispatch.body: 11941 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11942 // CHECK23: omp.inner.for.cond: 11943 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] 11944 // CHECK23-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]] 11945 // CHECK23-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 11946 // CHECK23-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11947 // CHECK23: omp.inner.for.body: 11948 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 11949 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 11950 // CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 11951 // CHECK23-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 11952 // CHECK23-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP24]] 11953 // CHECK23-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] 11954 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 11955 // CHECK23-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] 11956 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 11957 // CHECK23-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 11958 // CHECK23-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 11959 // CHECK23-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 11960 // CHECK23-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 11961 // CHECK23-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 11962 // CHECK23-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 11963 // CHECK23-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]] 11964 // CHECK23-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 11965 // CHECK23-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 11966 // CHECK23-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 11967 // CHECK23-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]] 11968 // CHECK23-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 11969 // CHECK23-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 11970 // CHECK23-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] 11971 // CHECK23-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 11972 // CHECK23-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] 11973 // CHECK23-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 11974 // CHECK23-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]] 11975 // CHECK23-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3 11976 // CHECK23-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]] 11977 // CHECK23-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 11978 // CHECK23-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]] 11979 // CHECK23-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 11980 // CHECK23-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP24]] 11981 // CHECK23-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 11982 // CHECK23-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP24]] 11983 // CHECK23-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 11984 // CHECK23-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP24]] 11985 // CHECK23-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 11986 // CHECK23-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 11987 // CHECK23-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 11988 // CHECK23-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP24]] 11989 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11990 // CHECK23: omp.body.continue: 11991 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11992 // CHECK23: omp.inner.for.inc: 11993 // CHECK23-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 11994 // CHECK23-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 11995 // CHECK23-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 11996 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 11997 // CHECK23: omp.inner.for.end: 11998 // CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 11999 // CHECK23: omp.dispatch.inc: 12000 // CHECK23-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 12001 // CHECK23-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 12002 // CHECK23-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 12003 // CHECK23-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 12004 // CHECK23-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 12005 // CHECK23-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 12006 // CHECK23-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 12007 // CHECK23-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 12008 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND]] 12009 // CHECK23: omp.dispatch.end: 12010 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 12011 // CHECK23-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 12012 // CHECK23-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 12013 // CHECK23-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12014 // CHECK23: .omp.final.then: 12015 // CHECK23-NEXT: store i8 96, ptr [[IT]], align 1 12016 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12017 // CHECK23: .omp.final.done: 12018 // CHECK23-NEXT: ret void 12019 // 12020 // 12021 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 12022 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 12023 // CHECK23-NEXT: entry: 12024 // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 12025 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12026 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12027 // CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 12028 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 12029 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 12030 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12031 // CHECK23-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 12032 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 12033 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 12034 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 12035 // CHECK23-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 12036 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 12037 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 12038 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 12039 // CHECK23-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 12040 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 12041 // CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 12042 // CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 12043 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 12044 // CHECK23-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 12045 // CHECK23-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 12046 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 12047 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]]) 12048 // CHECK23-NEXT: ret void 12049 // 12050 // 12051 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined 12052 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 12053 // CHECK23-NEXT: entry: 12054 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 12055 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 12056 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12057 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12058 // CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 12059 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 12060 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 12061 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 12062 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 12063 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 12064 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 12065 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 12066 // CHECK23-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 12067 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 12068 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 12069 // CHECK23-NEXT: ret void 12070 // 12071 // 12072 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 12073 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 12074 // CHECK23-NEXT: entry: 12075 // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 12076 // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 12077 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 12078 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 12079 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 12080 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 12081 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 12082 // CHECK23-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 12083 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 12084 // CHECK23-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 12085 // CHECK23-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 12086 // CHECK23-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 12087 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 12088 // CHECK23-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 12089 // CHECK23-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 12090 // CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 12091 // CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 12092 // CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 12093 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 12094 // CHECK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 12095 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 12096 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 12097 // CHECK23-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 4 12098 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4 12099 // CHECK23-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 12100 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4 12101 // CHECK23-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 12102 // CHECK23-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i1 12103 // CHECK23-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8 12104 // CHECK23-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 12105 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 12106 // CHECK23-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 12107 // CHECK23-NEXT: [[LOADEDV3:%.*]] = trunc i8 [[TMP9]] to i1 12108 // CHECK23-NEXT: br i1 [[LOADEDV3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12109 // CHECK23: omp_if.then: 12110 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) 12111 // CHECK23-NEXT: br label [[OMP_IF_END:%.*]] 12112 // CHECK23: omp_if.else: 12113 // CHECK23-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 12114 // CHECK23-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 12115 // CHECK23-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 12116 // CHECK23-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) #[[ATTR1:[0-9]+]] 12117 // CHECK23-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 12118 // CHECK23-NEXT: br label [[OMP_IF_END]] 12119 // CHECK23: omp_if.end: 12120 // CHECK23-NEXT: ret void 12121 // 12122 // 12123 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined 12124 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 12125 // CHECK23-NEXT: entry: 12126 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 12127 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 12128 // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 12129 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 12130 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 12131 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 12132 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 12133 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 12134 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 12135 // CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4 12136 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 12137 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 12138 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 12139 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12140 // CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 8 12141 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 12142 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 12143 // CHECK23-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 12144 // CHECK23-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 12145 // CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 12146 // CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 12147 // CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 12148 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 12149 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 12150 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 12151 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 12152 // CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 12153 // CHECK23-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 12154 // CHECK23-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 12155 // CHECK23-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 12156 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 12157 // CHECK23-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 12158 // CHECK23-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP4]] to i1 12159 // CHECK23-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12160 // CHECK23: omp_if.then: 12161 // CHECK23-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 12162 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 12163 // CHECK23-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 12164 // CHECK23-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 12165 // CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 12166 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12167 // CHECK23: cond.true: 12168 // CHECK23-NEXT: br label [[COND_END:%.*]] 12169 // CHECK23: cond.false: 12170 // CHECK23-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 12171 // CHECK23-NEXT: br label [[COND_END]] 12172 // CHECK23: cond.end: 12173 // CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 12174 // CHECK23-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 12175 // CHECK23-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 12176 // CHECK23-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV]], align 8 12177 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12178 // CHECK23: omp.inner.for.cond: 12179 // CHECK23-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27:![0-9]+]] 12180 // CHECK23-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP27]] 12181 // CHECK23-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 12182 // CHECK23-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12183 // CHECK23: omp.inner.for.body: 12184 // CHECK23-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 12185 // CHECK23-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 12186 // CHECK23-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 12187 // CHECK23-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP27]] 12188 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 12189 // CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double 12190 // CHECK23-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 12191 // CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 12192 // CHECK23-NEXT: store double [[ADD]], ptr [[A]], align 4, !nontemporal [[META28:![0-9]+]], !llvm.access.group [[ACC_GRP27]] 12193 // CHECK23-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 12194 // CHECK23-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 4, !nontemporal [[META28]], !llvm.access.group [[ACC_GRP27]] 12195 // CHECK23-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 12196 // CHECK23-NEXT: store double [[INC]], ptr [[A4]], align 4, !nontemporal [[META28]], !llvm.access.group [[ACC_GRP27]] 12197 // CHECK23-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 12198 // CHECK23-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]] 12199 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP15]] 12200 // CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 12201 // CHECK23-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP27]] 12202 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12203 // CHECK23: omp.body.continue: 12204 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12205 // CHECK23: omp.inner.for.inc: 12206 // CHECK23-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 12207 // CHECK23-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1 12208 // CHECK23-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 12209 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] 12210 // CHECK23: omp.inner.for.end: 12211 // CHECK23-NEXT: br label [[OMP_IF_END:%.*]] 12212 // CHECK23: omp_if.else: 12213 // CHECK23-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 12214 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 12215 // CHECK23-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP18]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 12216 // CHECK23-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 12217 // CHECK23-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[TMP19]], 3 12218 // CHECK23-NEXT: br i1 [[CMP8]], label [[COND_TRUE9:%.*]], label [[COND_FALSE10:%.*]] 12219 // CHECK23: cond.true9: 12220 // CHECK23-NEXT: br label [[COND_END11:%.*]] 12221 // CHECK23: cond.false10: 12222 // CHECK23-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 12223 // CHECK23-NEXT: br label [[COND_END11]] 12224 // CHECK23: cond.end11: 12225 // CHECK23-NEXT: [[COND12:%.*]] = phi i64 [ 3, [[COND_TRUE9]] ], [ [[TMP20]], [[COND_FALSE10]] ] 12226 // CHECK23-NEXT: store i64 [[COND12]], ptr [[DOTOMP_UB]], align 8 12227 // CHECK23-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 12228 // CHECK23-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV]], align 8 12229 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 12230 // CHECK23: omp.inner.for.cond13: 12231 // CHECK23-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 12232 // CHECK23-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 12233 // CHECK23-NEXT: [[CMP14:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 12234 // CHECK23-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END29:%.*]] 12235 // CHECK23: omp.inner.for.body15: 12236 // CHECK23-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 12237 // CHECK23-NEXT: [[MUL16:%.*]] = mul i64 [[TMP24]], 400 12238 // CHECK23-NEXT: [[SUB17:%.*]] = sub i64 2000, [[MUL16]] 12239 // CHECK23-NEXT: store i64 [[SUB17]], ptr [[IT]], align 8 12240 // CHECK23-NEXT: [[TMP25:%.*]] = load i32, ptr [[B_ADDR]], align 4 12241 // CHECK23-NEXT: [[CONV18:%.*]] = sitofp i32 [[TMP25]] to double 12242 // CHECK23-NEXT: [[ADD19:%.*]] = fadd double [[CONV18]], 1.500000e+00 12243 // CHECK23-NEXT: [[A20:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 12244 // CHECK23-NEXT: store double [[ADD19]], ptr [[A20]], align 4 12245 // CHECK23-NEXT: [[A21:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 12246 // CHECK23-NEXT: [[TMP26:%.*]] = load double, ptr [[A21]], align 4 12247 // CHECK23-NEXT: [[INC22:%.*]] = fadd double [[TMP26]], 1.000000e+00 12248 // CHECK23-NEXT: store double [[INC22]], ptr [[A21]], align 4 12249 // CHECK23-NEXT: [[CONV23:%.*]] = fptosi double [[INC22]] to i16 12250 // CHECK23-NEXT: [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]] 12251 // CHECK23-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP27]] 12252 // CHECK23-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX24]], i32 1 12253 // CHECK23-NEXT: store i16 [[CONV23]], ptr [[ARRAYIDX25]], align 2 12254 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] 12255 // CHECK23: omp.body.continue26: 12256 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] 12257 // CHECK23: omp.inner.for.inc27: 12258 // CHECK23-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 12259 // CHECK23-NEXT: [[ADD28:%.*]] = add i64 [[TMP28]], 1 12260 // CHECK23-NEXT: store i64 [[ADD28]], ptr [[DOTOMP_IV]], align 8 12261 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP31:![0-9]+]] 12262 // CHECK23: omp.inner.for.end29: 12263 // CHECK23-NEXT: br label [[OMP_IF_END]] 12264 // CHECK23: omp_if.end: 12265 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12266 // CHECK23: omp.loop.exit: 12267 // CHECK23-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 12268 // CHECK23-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4 12269 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]]) 12270 // CHECK23-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 12271 // CHECK23-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 12272 // CHECK23-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12273 // CHECK23: .omp.final.then: 12274 // CHECK23-NEXT: store i64 400, ptr [[IT]], align 8 12275 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12276 // CHECK23: .omp.final.done: 12277 // CHECK23-NEXT: ret void 12278 // 12279 // 12280 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 12281 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 12282 // CHECK23-NEXT: entry: 12283 // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 12284 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12285 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12286 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 12287 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 12288 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12289 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 12290 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 12291 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 12292 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 12293 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 12294 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 12295 // CHECK23-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 12296 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 12297 // CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 12298 // CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 12299 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 12300 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) 12301 // CHECK23-NEXT: ret void 12302 // 12303 // 12304 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined 12305 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 12306 // CHECK23-NEXT: entry: 12307 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 12308 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 12309 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12310 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12311 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 12312 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 12313 // CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4 12314 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 12315 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 12316 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 12317 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12318 // CHECK23-NEXT: [[I:%.*]] = alloca i64, align 8 12319 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 12320 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 12321 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 12322 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 12323 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 12324 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 12325 // CHECK23-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 12326 // CHECK23-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 12327 // CHECK23-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 12328 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 12329 // CHECK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 12330 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 12331 // CHECK23-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 12332 // CHECK23-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 12333 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 12334 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12335 // CHECK23: cond.true: 12336 // CHECK23-NEXT: br label [[COND_END:%.*]] 12337 // CHECK23: cond.false: 12338 // CHECK23-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 12339 // CHECK23-NEXT: br label [[COND_END]] 12340 // CHECK23: cond.end: 12341 // CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 12342 // CHECK23-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 12343 // CHECK23-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 12344 // CHECK23-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 12345 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12346 // CHECK23: omp.inner.for.cond: 12347 // CHECK23-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33:![0-9]+]] 12348 // CHECK23-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP33]] 12349 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 12350 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12351 // CHECK23: omp.inner.for.body: 12352 // CHECK23-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33]] 12353 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 12354 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 12355 // CHECK23-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP33]] 12356 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 12357 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 12358 // CHECK23-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 12359 // CHECK23-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] 12360 // CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 12361 // CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 12362 // CHECK23-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 12363 // CHECK23-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] 12364 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 12365 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] 12366 // CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 12367 // CHECK23-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] 12368 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12369 // CHECK23: omp.body.continue: 12370 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12371 // CHECK23: omp.inner.for.inc: 12372 // CHECK23-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33]] 12373 // CHECK23-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 12374 // CHECK23-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33]] 12375 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 12376 // CHECK23: omp.inner.for.end: 12377 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12378 // CHECK23: omp.loop.exit: 12379 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 12380 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 12381 // CHECK23-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 12382 // CHECK23-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12383 // CHECK23: .omp.final.then: 12384 // CHECK23-NEXT: store i64 11, ptr [[I]], align 8 12385 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12386 // CHECK23: .omp.final.done: 12387 // CHECK23-NEXT: ret void 12388 // 12389