1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 9 // RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 20 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 21 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 22 // RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 23 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 24 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 25 // RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 26 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 27 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 28 29 // Test target codegen - host bc file has to be created first. 30 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 31 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 33 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 34 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 35 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 36 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 37 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 38 // RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 39 // RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 40 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 41 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 42 // RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 43 // RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 44 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 45 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 46 47 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 48 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 49 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 50 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 51 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 52 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 53 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 54 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 55 // RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 56 // RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 57 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 58 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 59 // RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 60 // RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 61 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 62 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 63 64 // expected-no-diagnostics 65 #ifndef HEADER 66 #define HEADER 67 68 69 70 // We have 8 target regions, but only 7 that actually will generate offloading 71 // code, only 6 will have mapped arguments, and only 4 have all-constant map 72 // sizes. 73 74 75 76 // Check target registration is registered as a Ctor. 77 78 79 template<typename tx, typename ty> 80 struct TT{ 81 tx X; 82 ty Y; 83 }; 84 85 long long get_val() { return 0; } 86 87 int foo(int n) { 88 int a = 0; 89 short aa = 0; 90 float b[10]; 91 float bn[n]; 92 double c[5][10]; 93 double cn[5][n]; 94 TT<long long, char> d; 95 96 #pragma omp target parallel for simd nowait 97 for (int i = 3; i < 32; i += 5) { 98 } 99 100 long long k = get_val(); 101 #pragma omp target parallel for simd if(target: 0) linear(k : 3) schedule(dynamic) 102 for (int i = 10; i > 1; i--) { 103 a += 1; 104 } 105 106 107 int lin = 12; 108 #pragma omp target parallel for simd if(target: 1) linear(lin, a : get_val()) 109 for (unsigned long long it = 2000; it >= 600; it-=400) { 110 aa += 1; 111 } 112 113 114 115 116 #pragma omp target parallel for simd if(target: n>10) 117 for (short it = 6; it <= 20; it-=-4) { 118 a += 1; 119 aa += 1; 120 } 121 122 // We capture 3 VLA sizes in this target region 123 124 125 126 127 128 // The names below are not necessarily consistent with the names used for the 129 // addresses above as some are repeated. 130 131 132 133 134 135 136 137 138 139 140 #pragma omp target parallel for simd if(target: n>20) schedule(static, a) 141 for (unsigned char it = 'z'; it >= 'a'; it+=-1) { 142 a += 1; 143 b[2] += 1.0; 144 bn[3] += 1.0; 145 c[1][2] += 1.0; 146 cn[1][3] += 1.0; 147 d.X += 1; 148 d.Y += 1; 149 } 150 151 return a; 152 } 153 154 // Check that the offloading functions are emitted and that the arguments are 155 // correct and loaded correctly for the target regions in foo(). 156 157 158 159 160 // Create stack storage and store argument in there. 161 162 // Create stack storage and store argument in there. 163 164 // Create stack storage and store argument in there. 165 166 // Create local storage for each capture. 167 168 169 170 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 171 172 template<typename tx> 173 tx ftemplate(int n) { 174 tx a = 0; 175 short aa = 0; 176 tx b[10]; 177 178 #pragma omp target parallel for simd if(target: n>40) 179 for (long long i = -10; i < 10; i += 3) { 180 a += 1; 181 aa += 1; 182 b[2] += 1; 183 } 184 185 return a; 186 } 187 188 static 189 int fstatic(int n) { 190 int a = 0; 191 short aa = 0; 192 char aaa = 0; 193 int b[10]; 194 195 #pragma omp target parallel for simd if(target: n>50) 196 for (unsigned i=100; i<10; i+=10) { 197 a += 1; 198 aa += 1; 199 aaa += 1; 200 b[2] += 1; 201 } 202 203 return a; 204 } 205 206 struct S1 { 207 double a; 208 209 int r1(int n){ 210 int b = n+1; 211 short int c[2][n]; 212 213 #ifdef OMP5 214 #pragma omp target parallel for simd if(n>60) nontemporal(a) 215 #else 216 #pragma omp target parallel for simd if(target: n>60) 217 #endif // OMP5 218 for (unsigned long long it = 2000; it >= 600; it -= 400) { 219 this->a = (double)b + 1.5; 220 c[1][1] = ++a; 221 } 222 223 return c[1][1] + (int)b; 224 } 225 }; 226 227 int bar(int n){ 228 int a = 0; 229 230 a += foo(n); 231 232 S1 S; 233 a += S.r1(n); 234 235 a += fstatic(n); 236 237 a += ftemplate<int>(n); 238 239 return a; 240 } 241 242 243 244 // We capture 2 VLA sizes in this target region 245 246 247 // The names below are not necessarily consistent with the names used for the 248 // addresses above as some are repeated. 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 // Check that the offloading functions are emitted and that the arguments are 269 // correct and loaded correctly for the target regions of the callees of bar(). 270 271 // Create local storage for each capture. 272 // Store captures in the context. 273 274 275 276 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 277 278 279 // Create local storage for each capture. 280 // Store captures in the context. 281 282 283 284 285 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 286 287 // Create local storage for each capture. 288 // Store captures in the context. 289 290 291 292 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 293 294 295 #endif 296 // CHECK1-LABEL: define {{[^@]+}}@_Z7get_valv 297 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 298 // CHECK1-NEXT: entry: 299 // CHECK1-NEXT: ret i64 0 300 // 301 // 302 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 303 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 304 // CHECK1-NEXT: entry: 305 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 306 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 307 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 308 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 309 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 310 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 311 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 312 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 313 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 314 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 315 // CHECK1-NEXT: [[K:%.*]] = alloca i64, align 8 316 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 317 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 318 // CHECK1-NEXT: [[LIN:%.*]] = alloca i32, align 4 319 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 320 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 321 // CHECK1-NEXT: [[A_CASTED2:%.*]] = alloca i64, align 8 322 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 323 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 324 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 325 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 326 // CHECK1-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 327 // CHECK1-NEXT: [[AA_CASTED4:%.*]] = alloca i64, align 8 328 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 8 329 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 8 330 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 8 331 // CHECK1-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 332 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 333 // CHECK1-NEXT: [[A_CASTED11:%.*]] = alloca i64, align 8 334 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 335 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 8 336 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 8 337 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 8 338 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 339 // CHECK1-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 340 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 341 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 342 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 343 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 344 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 345 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 346 // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() 347 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 348 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 349 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 350 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 351 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 352 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 353 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 354 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 355 // CHECK1-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, ptr @.omp_task_entry., i64 -1) 356 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP7]], i32 0, i32 0 357 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP7]]) 358 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 359 // CHECK1-NEXT: store i64 [[CALL]], ptr [[K]], align 8 360 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4 361 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4 362 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8 363 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[K]], align 8 364 // CHECK1-NEXT: store i64 [[TMP12]], ptr [[K_CASTED]], align 8 365 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, ptr [[K_CASTED]], align 8 366 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR4:[0-9]+]] 367 // CHECK1-NEXT: store i32 12, ptr [[LIN]], align 4 368 // CHECK1-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2 369 // CHECK1-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2 370 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[AA_CASTED]], align 8 371 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[LIN]], align 4 372 // CHECK1-NEXT: store i32 [[TMP16]], ptr [[LIN_CASTED]], align 4 373 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 374 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A]], align 4 375 // CHECK1-NEXT: store i32 [[TMP18]], ptr [[A_CASTED2]], align 4 376 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[A_CASTED2]], align 8 377 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 378 // CHECK1-NEXT: store i64 [[TMP15]], ptr [[TMP20]], align 8 379 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 380 // CHECK1-NEXT: store i64 [[TMP15]], ptr [[TMP21]], align 8 381 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 382 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 383 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 384 // CHECK1-NEXT: store i64 [[TMP17]], ptr [[TMP23]], align 8 385 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 386 // CHECK1-NEXT: store i64 [[TMP17]], ptr [[TMP24]], align 8 387 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 388 // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 389 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 390 // CHECK1-NEXT: store i64 [[TMP19]], ptr [[TMP26]], align 8 391 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 392 // CHECK1-NEXT: store i64 [[TMP19]], ptr [[TMP27]], align 8 393 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 394 // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8 395 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 396 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 397 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 398 // CHECK1-NEXT: store i32 2, ptr [[TMP31]], align 4 399 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 400 // CHECK1-NEXT: store i32 3, ptr [[TMP32]], align 4 401 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 402 // CHECK1-NEXT: store ptr [[TMP29]], ptr [[TMP33]], align 8 403 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 404 // CHECK1-NEXT: store ptr [[TMP30]], ptr [[TMP34]], align 8 405 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 406 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP35]], align 8 407 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 408 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP36]], align 8 409 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 410 // CHECK1-NEXT: store ptr null, ptr [[TMP37]], align 8 411 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 412 // CHECK1-NEXT: store ptr null, ptr [[TMP38]], align 8 413 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 414 // CHECK1-NEXT: store i64 0, ptr [[TMP39]], align 8 415 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 416 // CHECK1-NEXT: store i64 0, ptr [[TMP40]], align 8 417 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 418 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP41]], align 4 419 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 420 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP42]], align 4 421 // CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 422 // CHECK1-NEXT: store i32 0, ptr [[TMP43]], align 4 423 // CHECK1-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, ptr [[KERNEL_ARGS]]) 424 // CHECK1-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 425 // CHECK1-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 426 // CHECK1: omp_offload.failed: 427 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]]) #[[ATTR4]] 428 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 429 // CHECK1: omp_offload.cont: 430 // CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 431 // CHECK1-NEXT: store i32 [[TMP46]], ptr [[A_CASTED3]], align 4 432 // CHECK1-NEXT: [[TMP47:%.*]] = load i64, ptr [[A_CASTED3]], align 8 433 // CHECK1-NEXT: [[TMP48:%.*]] = load i16, ptr [[AA]], align 2 434 // CHECK1-NEXT: store i16 [[TMP48]], ptr [[AA_CASTED4]], align 2 435 // CHECK1-NEXT: [[TMP49:%.*]] = load i64, ptr [[AA_CASTED4]], align 8 436 // CHECK1-NEXT: [[TMP50:%.*]] = load i32, ptr [[N_ADDR]], align 4 437 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP50]], 10 438 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 439 // CHECK1: omp_if.then: 440 // CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 441 // CHECK1-NEXT: store i64 [[TMP47]], ptr [[TMP51]], align 8 442 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 443 // CHECK1-NEXT: store i64 [[TMP47]], ptr [[TMP52]], align 8 444 // CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 445 // CHECK1-NEXT: store ptr null, ptr [[TMP53]], align 8 446 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 447 // CHECK1-NEXT: store i64 [[TMP49]], ptr [[TMP54]], align 8 448 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 449 // CHECK1-NEXT: store i64 [[TMP49]], ptr [[TMP55]], align 8 450 // CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 451 // CHECK1-NEXT: store ptr null, ptr [[TMP56]], align 8 452 // CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 453 // CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 454 // CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0 455 // CHECK1-NEXT: store i32 2, ptr [[TMP59]], align 4 456 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1 457 // CHECK1-NEXT: store i32 2, ptr [[TMP60]], align 4 458 // CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2 459 // CHECK1-NEXT: store ptr [[TMP57]], ptr [[TMP61]], align 8 460 // CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3 461 // CHECK1-NEXT: store ptr [[TMP58]], ptr [[TMP62]], align 8 462 // CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4 463 // CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP63]], align 8 464 // CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5 465 // CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP64]], align 8 466 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6 467 // CHECK1-NEXT: store ptr null, ptr [[TMP65]], align 8 468 // CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7 469 // CHECK1-NEXT: store ptr null, ptr [[TMP66]], align 8 470 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8 471 // CHECK1-NEXT: store i64 0, ptr [[TMP67]], align 8 472 // CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 9 473 // CHECK1-NEXT: store i64 0, ptr [[TMP68]], align 8 474 // CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 10 475 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP69]], align 4 476 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 11 477 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP70]], align 4 478 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12 479 // CHECK1-NEXT: store i32 0, ptr [[TMP71]], align 4 480 // CHECK1-NEXT: [[TMP72:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, ptr [[KERNEL_ARGS8]]) 481 // CHECK1-NEXT: [[TMP73:%.*]] = icmp ne i32 [[TMP72]], 0 482 // CHECK1-NEXT: br i1 [[TMP73]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 483 // CHECK1: omp_offload.failed9: 484 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR4]] 485 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT10]] 486 // CHECK1: omp_offload.cont10: 487 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 488 // CHECK1: omp_if.else: 489 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR4]] 490 // CHECK1-NEXT: br label [[OMP_IF_END]] 491 // CHECK1: omp_if.end: 492 // CHECK1-NEXT: [[TMP74:%.*]] = load i32, ptr [[A]], align 4 493 // CHECK1-NEXT: store i32 [[TMP74]], ptr [[DOTCAPTURE_EXPR_]], align 4 494 // CHECK1-NEXT: [[TMP75:%.*]] = load i32, ptr [[A]], align 4 495 // CHECK1-NEXT: store i32 [[TMP75]], ptr [[A_CASTED11]], align 4 496 // CHECK1-NEXT: [[TMP76:%.*]] = load i64, ptr [[A_CASTED11]], align 8 497 // CHECK1-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 498 // CHECK1-NEXT: store i32 [[TMP77]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 499 // CHECK1-NEXT: [[TMP78:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 500 // CHECK1-NEXT: [[TMP79:%.*]] = load i32, ptr [[N_ADDR]], align 4 501 // CHECK1-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP79]], 20 502 // CHECK1-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]] 503 // CHECK1: omp_if.then13: 504 // CHECK1-NEXT: [[TMP80:%.*]] = mul nuw i64 [[TMP2]], 4 505 // CHECK1-NEXT: [[TMP81:%.*]] = mul nuw i64 5, [[TMP5]] 506 // CHECK1-NEXT: [[TMP82:%.*]] = mul nuw i64 [[TMP81]], 8 507 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.3, i64 80, i1 false) 508 // CHECK1-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 509 // CHECK1-NEXT: store i64 [[TMP76]], ptr [[TMP83]], align 8 510 // CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 511 // CHECK1-NEXT: store i64 [[TMP76]], ptr [[TMP84]], align 8 512 // CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0 513 // CHECK1-NEXT: store ptr null, ptr [[TMP85]], align 8 514 // CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 515 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP86]], align 8 516 // CHECK1-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 517 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP87]], align 8 518 // CHECK1-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1 519 // CHECK1-NEXT: store ptr null, ptr [[TMP88]], align 8 520 // CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 521 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP89]], align 8 522 // CHECK1-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 523 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP90]], align 8 524 // CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 2 525 // CHECK1-NEXT: store ptr null, ptr [[TMP91]], align 8 526 // CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 527 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP92]], align 8 528 // CHECK1-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 529 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP93]], align 8 530 // CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 531 // CHECK1-NEXT: store i64 [[TMP80]], ptr [[TMP94]], align 8 532 // CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 3 533 // CHECK1-NEXT: store ptr null, ptr [[TMP95]], align 8 534 // CHECK1-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 535 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP96]], align 8 536 // CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 537 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP97]], align 8 538 // CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 4 539 // CHECK1-NEXT: store ptr null, ptr [[TMP98]], align 8 540 // CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 541 // CHECK1-NEXT: store i64 5, ptr [[TMP99]], align 8 542 // CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 543 // CHECK1-NEXT: store i64 5, ptr [[TMP100]], align 8 544 // CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 5 545 // CHECK1-NEXT: store ptr null, ptr [[TMP101]], align 8 546 // CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 547 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP102]], align 8 548 // CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 549 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP103]], align 8 550 // CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 6 551 // CHECK1-NEXT: store ptr null, ptr [[TMP104]], align 8 552 // CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 553 // CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP105]], align 8 554 // CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 555 // CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP106]], align 8 556 // CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 557 // CHECK1-NEXT: store i64 [[TMP82]], ptr [[TMP107]], align 8 558 // CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 7 559 // CHECK1-NEXT: store ptr null, ptr [[TMP108]], align 8 560 // CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 561 // CHECK1-NEXT: store ptr [[D]], ptr [[TMP109]], align 8 562 // CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 563 // CHECK1-NEXT: store ptr [[D]], ptr [[TMP110]], align 8 564 // CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 8 565 // CHECK1-NEXT: store ptr null, ptr [[TMP111]], align 8 566 // CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 567 // CHECK1-NEXT: store i64 [[TMP78]], ptr [[TMP112]], align 8 568 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 569 // CHECK1-NEXT: store i64 [[TMP78]], ptr [[TMP113]], align 8 570 // CHECK1-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 9 571 // CHECK1-NEXT: store ptr null, ptr [[TMP114]], align 8 572 // CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 573 // CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 574 // CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 575 // CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0 576 // CHECK1-NEXT: store i32 2, ptr [[TMP118]], align 4 577 // CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1 578 // CHECK1-NEXT: store i32 10, ptr [[TMP119]], align 4 579 // CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2 580 // CHECK1-NEXT: store ptr [[TMP115]], ptr [[TMP120]], align 8 581 // CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3 582 // CHECK1-NEXT: store ptr [[TMP116]], ptr [[TMP121]], align 8 583 // CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4 584 // CHECK1-NEXT: store ptr [[TMP117]], ptr [[TMP122]], align 8 585 // CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5 586 // CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP123]], align 8 587 // CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6 588 // CHECK1-NEXT: store ptr null, ptr [[TMP124]], align 8 589 // CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7 590 // CHECK1-NEXT: store ptr null, ptr [[TMP125]], align 8 591 // CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8 592 // CHECK1-NEXT: store i64 0, ptr [[TMP126]], align 8 593 // CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 9 594 // CHECK1-NEXT: store i64 0, ptr [[TMP127]], align 8 595 // CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 10 596 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP128]], align 4 597 // CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 11 598 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP129]], align 4 599 // CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12 600 // CHECK1-NEXT: store i32 0, ptr [[TMP130]], align 4 601 // CHECK1-NEXT: [[TMP131:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, ptr [[KERNEL_ARGS17]]) 602 // CHECK1-NEXT: [[TMP132:%.*]] = icmp ne i32 [[TMP131]], 0 603 // CHECK1-NEXT: br i1 [[TMP132]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] 604 // CHECK1: omp_offload.failed18: 605 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR4]] 606 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT19]] 607 // CHECK1: omp_offload.cont19: 608 // CHECK1-NEXT: br label [[OMP_IF_END21:%.*]] 609 // CHECK1: omp_if.else20: 610 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR4]] 611 // CHECK1-NEXT: br label [[OMP_IF_END21]] 612 // CHECK1: omp_if.end21: 613 // CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[A]], align 4 614 // CHECK1-NEXT: [[TMP134:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 615 // CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP134]]) 616 // CHECK1-NEXT: ret i32 [[TMP133]] 617 // 618 // 619 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 620 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] { 621 // CHECK1-NEXT: entry: 622 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) 623 // CHECK1-NEXT: ret void 624 // 625 // 626 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined 627 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 628 // CHECK1-NEXT: entry: 629 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 630 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 631 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 632 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 633 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 634 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 635 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 636 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 637 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 638 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 639 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 640 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 641 // CHECK1-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 642 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 643 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 644 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 645 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 646 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 647 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 648 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 649 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 650 // CHECK1: cond.true: 651 // CHECK1-NEXT: br label [[COND_END:%.*]] 652 // CHECK1: cond.false: 653 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 654 // CHECK1-NEXT: br label [[COND_END]] 655 // CHECK1: cond.end: 656 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 657 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 658 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 659 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 660 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 661 // CHECK1: omp.inner.for.cond: 662 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 663 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 664 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 665 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 666 // CHECK1: omp.inner.for.body: 667 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 668 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 669 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 670 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 671 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 672 // CHECK1: omp.body.continue: 673 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 674 // CHECK1: omp.inner.for.inc: 675 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 676 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 677 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 678 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 679 // CHECK1: omp.inner.for.end: 680 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 681 // CHECK1: omp.loop.exit: 682 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 683 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 684 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 685 // CHECK1-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 686 // CHECK1: .omp.final.then: 687 // CHECK1-NEXT: store i32 33, ptr [[I]], align 4 688 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 689 // CHECK1: .omp.final.done: 690 // CHECK1-NEXT: ret void 691 // 692 // 693 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 694 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 695 // CHECK1-NEXT: entry: 696 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 697 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 698 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 699 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 700 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 701 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 702 // CHECK1-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 703 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 704 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 705 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 706 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 707 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 708 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 709 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 710 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 711 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 712 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 713 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 714 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 715 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 716 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 717 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 718 // CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !25 719 // CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25 720 // CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25 721 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !25 722 // CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !25 723 // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !25 724 // CHECK1-NEXT: store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !25 725 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 726 // CHECK1-NEXT: store i32 0, ptr [[TMP9]], align 4, !noalias !25 727 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 728 // CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8, !noalias !25 729 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 730 // CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8, !noalias !25 731 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 732 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8, !noalias !25 733 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 734 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8, !noalias !25 735 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 736 // CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8, !noalias !25 737 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 738 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8, !noalias !25 739 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 740 // CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8, !noalias !25 741 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9 742 // CHECK1-NEXT: store i64 1, ptr [[TMP17]], align 8, !noalias !25 743 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10 744 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4, !noalias !25 745 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11 746 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4, !noalias !25 747 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12 748 // CHECK1-NEXT: store i32 0, ptr [[TMP20]], align 4, !noalias !25 749 // CHECK1-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, ptr [[KERNEL_ARGS_I]]) 750 // CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 751 // CHECK1-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] 752 // CHECK1: omp_offload.failed.i: 753 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] 754 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] 755 // CHECK1: .omp_outlined..exit: 756 // CHECK1-NEXT: ret i32 0 757 // 758 // 759 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 760 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 761 // CHECK1-NEXT: entry: 762 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 763 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 764 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 765 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 766 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 767 // CHECK1-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8 768 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 769 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 770 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 771 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[K_ADDR]], align 8 772 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[K_CASTED]], align 8 773 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[K_CASTED]], align 8 774 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) 775 // CHECK1-NEXT: ret void 776 // 777 // 778 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined 779 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 780 // CHECK1-NEXT: entry: 781 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 782 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 783 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 784 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 785 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 786 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 787 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 788 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 789 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 790 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 791 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 792 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 793 // CHECK1-NEXT: [[K1:%.*]] = alloca i64, align 8 794 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 795 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 796 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 797 // CHECK1-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8 798 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[K_ADDR]], align 8 799 // CHECK1-NEXT: store i64 [[TMP0]], ptr [[DOTLINEAR_START]], align 8 800 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 801 // CHECK1-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 4 802 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 803 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 804 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 805 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 806 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 807 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1) 808 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 809 // CHECK1: omp.dispatch.cond: 810 // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP2]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]) 811 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 812 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 813 // CHECK1: omp.dispatch.body: 814 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 815 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 816 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 817 // CHECK1: omp.inner.for.cond: 818 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] 819 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] 820 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 821 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 822 // CHECK1: omp.inner.for.body: 823 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 824 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 825 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 826 // CHECK1-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] 827 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP26]] 828 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 829 // CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 830 // CHECK1-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 831 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV]] 832 // CHECK1-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP26]] 833 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] 834 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 835 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] 836 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 837 // CHECK1: omp.body.continue: 838 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 839 // CHECK1: omp.inner.for.inc: 840 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 841 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 842 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 843 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] 844 // CHECK1: omp.inner.for.end: 845 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 846 // CHECK1: omp.dispatch.inc: 847 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 848 // CHECK1: omp.dispatch.end: 849 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 850 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 851 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 852 // CHECK1: .omp.final.then: 853 // CHECK1-NEXT: store i32 1, ptr [[I]], align 4 854 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 855 // CHECK1: .omp.final.done: 856 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 857 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 858 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 859 // CHECK1: .omp.linear.pu: 860 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, ptr [[K1]], align 8 861 // CHECK1-NEXT: store i64 [[TMP16]], ptr [[K_ADDR]], align 8 862 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 863 // CHECK1: .omp.linear.pu.done: 864 // CHECK1-NEXT: ret void 865 // 866 // 867 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 868 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 869 // CHECK1-NEXT: entry: 870 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 871 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 872 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 873 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 874 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 875 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 876 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 877 // CHECK1-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 878 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 879 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 880 // CHECK1-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 881 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 882 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 883 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 884 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 885 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 886 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 887 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8 888 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 889 // CHECK1-NEXT: ret void 890 // 891 // 892 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined 893 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 894 // CHECK1-NEXT: entry: 895 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 896 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 897 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 898 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 899 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 900 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 901 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 902 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 903 // CHECK1-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 904 // CHECK1-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 905 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 906 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 907 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 908 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 909 // CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8 910 // CHECK1-NEXT: [[LIN2:%.*]] = alloca i32, align 4 911 // CHECK1-NEXT: [[A3:%.*]] = alloca i32, align 4 912 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 913 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 914 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 915 // CHECK1-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 916 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 917 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 918 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 919 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 920 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 921 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 922 // CHECK1-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 923 // CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 924 // CHECK1-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 925 // CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 926 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 927 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 928 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 929 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]]) 930 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 931 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 932 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 933 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 934 // CHECK1: cond.true: 935 // CHECK1-NEXT: br label [[COND_END:%.*]] 936 // CHECK1: cond.false: 937 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 938 // CHECK1-NEXT: br label [[COND_END]] 939 // CHECK1: cond.end: 940 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 941 // CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 942 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 943 // CHECK1-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 944 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 945 // CHECK1: omp.inner.for.cond: 946 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29:![0-9]+]] 947 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP29]] 948 // CHECK1-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 949 // CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 950 // CHECK1: omp.inner.for.body: 951 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 952 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 953 // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 954 // CHECK1-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP29]] 955 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP29]] 956 // CHECK1-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 957 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 958 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]] 959 // CHECK1-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 960 // CHECK1-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 961 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 962 // CHECK1-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP29]] 963 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP29]] 964 // CHECK1-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 965 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 966 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]] 967 // CHECK1-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 968 // CHECK1-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 969 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 970 // CHECK1-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP29]] 971 // CHECK1-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] 972 // CHECK1-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 973 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 974 // CHECK1-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 975 // CHECK1-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] 976 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 977 // CHECK1: omp.body.continue: 978 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 979 // CHECK1: omp.inner.for.inc: 980 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 981 // CHECK1-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 982 // CHECK1-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 983 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] 984 // CHECK1: omp.inner.for.end: 985 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 986 // CHECK1: omp.loop.exit: 987 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 988 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 989 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 990 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 991 // CHECK1: .omp.final.then: 992 // CHECK1-NEXT: store i64 400, ptr [[IT]], align 8 993 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 994 // CHECK1: .omp.final.done: 995 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 996 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 997 // CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 998 // CHECK1: .omp.linear.pu: 999 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 1000 // CHECK1-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 1001 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 1002 // CHECK1-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 1003 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 1004 // CHECK1: .omp.linear.pu.done: 1005 // CHECK1-NEXT: ret void 1006 // 1007 // 1008 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 1009 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1010 // CHECK1-NEXT: entry: 1011 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1012 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1013 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1014 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1015 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1016 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1017 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1018 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 1019 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 1020 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1021 // CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 1022 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1023 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) 1024 // CHECK1-NEXT: ret void 1025 // 1026 // 1027 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined 1028 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 1029 // CHECK1-NEXT: entry: 1030 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1031 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1032 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1033 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1034 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1035 // CHECK1-NEXT: [[TMP:%.*]] = alloca i16, align 2 1036 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1037 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1038 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1039 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1040 // CHECK1-NEXT: [[IT:%.*]] = alloca i16, align 2 1041 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1042 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1043 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1044 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1045 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1046 // CHECK1-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 1047 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1048 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1049 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1050 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1051 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1052 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1053 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 1054 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1055 // CHECK1: cond.true: 1056 // CHECK1-NEXT: br label [[COND_END:%.*]] 1057 // CHECK1: cond.false: 1058 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1059 // CHECK1-NEXT: br label [[COND_END]] 1060 // CHECK1: cond.end: 1061 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1062 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1063 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1064 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1065 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1066 // CHECK1: omp.inner.for.cond: 1067 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]] 1068 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]] 1069 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1070 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1071 // CHECK1: omp.inner.for.body: 1072 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 1073 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 1074 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 1075 // CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 1076 // CHECK1-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP32]] 1077 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] 1078 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 1079 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] 1080 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] 1081 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 1082 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 1083 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 1084 // CHECK1-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] 1085 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1086 // CHECK1: omp.body.continue: 1087 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1088 // CHECK1: omp.inner.for.inc: 1089 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 1090 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 1091 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 1092 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] 1093 // CHECK1: omp.inner.for.end: 1094 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1095 // CHECK1: omp.loop.exit: 1096 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1097 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1098 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 1099 // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1100 // CHECK1: .omp.final.then: 1101 // CHECK1-NEXT: store i16 22, ptr [[IT]], align 2 1102 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1103 // CHECK1: .omp.final.done: 1104 // CHECK1-NEXT: ret void 1105 // 1106 // 1107 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 1108 // CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 1109 // CHECK1-NEXT: entry: 1110 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1111 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1112 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1113 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 1114 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1115 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1116 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1117 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 1118 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 1119 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1120 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1121 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1122 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1123 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1124 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1125 // CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 1126 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1127 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1128 // CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 1129 // CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 1130 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 1131 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 1132 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1133 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1134 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 1135 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1136 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1137 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 1138 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 1139 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 1140 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 1141 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 1142 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 1143 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 1144 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 1145 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 1146 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]]) 1147 // CHECK1-NEXT: ret void 1148 // 1149 // 1150 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined 1151 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 1152 // CHECK1-NEXT: entry: 1153 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1154 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1155 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1156 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1157 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1158 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 1159 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1160 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1161 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1162 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 1163 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 1164 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1165 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1166 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 1167 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1168 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1169 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1170 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1171 // CHECK1-NEXT: [[IT:%.*]] = alloca i8, align 1 1172 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1173 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1174 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1175 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1176 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1177 // CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 1178 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1179 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1180 // CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 1181 // CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 1182 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 1183 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 1184 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1185 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1186 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 1187 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1188 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1189 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 1190 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 1191 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 1192 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1193 // CHECK1-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 1194 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1195 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1196 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 1197 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1198 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 1199 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 1200 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1201 // CHECK1: omp.dispatch.cond: 1202 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1203 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 1204 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1205 // CHECK1: cond.true: 1206 // CHECK1-NEXT: br label [[COND_END:%.*]] 1207 // CHECK1: cond.false: 1208 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1209 // CHECK1-NEXT: br label [[COND_END]] 1210 // CHECK1: cond.end: 1211 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 1212 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1213 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1214 // CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 1215 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1216 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1217 // CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 1218 // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1219 // CHECK1: omp.dispatch.body: 1220 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1221 // CHECK1: omp.inner.for.cond: 1222 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]] 1223 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]] 1224 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 1225 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1226 // CHECK1: omp.inner.for.body: 1227 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 1228 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 1229 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 1230 // CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 1231 // CHECK1-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP35]] 1232 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] 1233 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 1234 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] 1235 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 1236 // CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] 1237 // CHECK1-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 1238 // CHECK1-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 1239 // CHECK1-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 1240 // CHECK1-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] 1241 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 1242 // CHECK1-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP35]] 1243 // CHECK1-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 1244 // CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 1245 // CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 1246 // CHECK1-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP35]] 1247 // CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 1248 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 1249 // CHECK1-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]] 1250 // CHECK1-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 1251 // CHECK1-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]] 1252 // CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 1253 // CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]] 1254 // CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3 1255 // CHECK1-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP35]] 1256 // CHECK1-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 1257 // CHECK1-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP35]] 1258 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 1259 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]] 1260 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 1261 // CHECK1-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]] 1262 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 1263 // CHECK1-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]] 1264 // CHECK1-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 1265 // CHECK1-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 1266 // CHECK1-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 1267 // CHECK1-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]] 1268 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1269 // CHECK1: omp.body.continue: 1270 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1271 // CHECK1: omp.inner.for.inc: 1272 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 1273 // CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 1274 // CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 1275 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] 1276 // CHECK1: omp.inner.for.end: 1277 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1278 // CHECK1: omp.dispatch.inc: 1279 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1280 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1281 // CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 1282 // CHECK1-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 1283 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1284 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1285 // CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 1286 // CHECK1-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 1287 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1288 // CHECK1: omp.dispatch.end: 1289 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 1290 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1291 // CHECK1-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 1292 // CHECK1-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1293 // CHECK1: .omp.final.then: 1294 // CHECK1-NEXT: store i8 96, ptr [[IT]], align 1 1295 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1296 // CHECK1: .omp.final.done: 1297 // CHECK1-NEXT: ret void 1298 // 1299 // 1300 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 1301 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1302 // CHECK1-NEXT: entry: 1303 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1304 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1305 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1306 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1307 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 1308 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 1309 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 1310 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 1311 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1312 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A]], align 4 1313 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 1314 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 1315 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 1316 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1317 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 1318 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 1319 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 1320 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 1321 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1322 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 1323 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 1324 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 1325 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 1326 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 1327 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 1328 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 1329 // CHECK1-NEXT: ret i32 [[TMP8]] 1330 // 1331 // 1332 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1333 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1334 // CHECK1-NEXT: entry: 1335 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1336 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1337 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 1338 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 1339 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1340 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1341 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 1342 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 1343 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 1344 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1345 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1346 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1347 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1348 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1349 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 1350 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1351 // CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4 1352 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 1353 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1354 // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() 1355 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 1356 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 1357 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 1358 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 1359 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 1360 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 1361 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 1362 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 1363 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 1364 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1365 // CHECK1: omp_if.then: 1366 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 1367 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 1368 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 1369 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 40, i1 false) 1370 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1371 // CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 8 1372 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1373 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP11]], align 8 1374 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1375 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 1376 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1377 // CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP13]], align 8 1378 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1379 // CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP14]], align 8 1380 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1381 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 1382 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1383 // CHECK1-NEXT: store i64 2, ptr [[TMP16]], align 8 1384 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1385 // CHECK1-NEXT: store i64 2, ptr [[TMP17]], align 8 1386 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1387 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 1388 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1389 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP19]], align 8 1390 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1391 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP20]], align 8 1392 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1393 // CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8 1394 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1395 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 8 1396 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1397 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 8 1398 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1399 // CHECK1-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 8 1400 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1401 // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 1402 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1403 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1404 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1405 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1406 // CHECK1-NEXT: store i32 2, ptr [[TMP29]], align 4 1407 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1408 // CHECK1-NEXT: store i32 5, ptr [[TMP30]], align 4 1409 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1410 // CHECK1-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 8 1411 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1412 // CHECK1-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 8 1413 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1414 // CHECK1-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 8 1415 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1416 // CHECK1-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP34]], align 8 1417 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1418 // CHECK1-NEXT: store ptr null, ptr [[TMP35]], align 8 1419 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1420 // CHECK1-NEXT: store ptr null, ptr [[TMP36]], align 8 1421 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1422 // CHECK1-NEXT: store i64 0, ptr [[TMP37]], align 8 1423 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1424 // CHECK1-NEXT: store i64 0, ptr [[TMP38]], align 8 1425 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1426 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 4 1427 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1428 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4 1429 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1430 // CHECK1-NEXT: store i32 0, ptr [[TMP41]], align 4 1431 // CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, ptr [[KERNEL_ARGS]]) 1432 // CHECK1-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 1433 // CHECK1-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1434 // CHECK1: omp_offload.failed: 1435 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR4]] 1436 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1437 // CHECK1: omp_offload.cont: 1438 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1439 // CHECK1: omp_if.else: 1440 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR4]] 1441 // CHECK1-NEXT: br label [[OMP_IF_END]] 1442 // CHECK1: omp_if.end: 1443 // CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]] 1444 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]] 1445 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 1446 // CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 1447 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 1448 // CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 1449 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] 1450 // CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 1451 // CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP47]]) 1452 // CHECK1-NEXT: ret i32 [[ADD3]] 1453 // 1454 // 1455 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 1456 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1457 // CHECK1-NEXT: entry: 1458 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1459 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1460 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1461 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 1462 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1463 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1464 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1465 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1466 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 1467 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 1468 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 1469 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1470 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1471 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 1472 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 1473 // CHECK1-NEXT: store i8 0, ptr [[AAA]], align 1 1474 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 1475 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 1476 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 1477 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 1478 // CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 1479 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1480 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1 1481 // CHECK1-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1 1482 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 1483 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 1484 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 1485 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1486 // CHECK1: omp_if.then: 1487 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1488 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP7]], align 8 1489 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1490 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP8]], align 8 1491 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1492 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 1493 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1494 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP10]], align 8 1495 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1496 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP11]], align 8 1497 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1498 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 1499 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1500 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP13]], align 8 1501 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1502 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP14]], align 8 1503 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1504 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 1505 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1506 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP16]], align 8 1507 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1508 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP17]], align 8 1509 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1510 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 1511 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1512 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1513 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1514 // CHECK1-NEXT: store i32 2, ptr [[TMP21]], align 4 1515 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1516 // CHECK1-NEXT: store i32 4, ptr [[TMP22]], align 4 1517 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1518 // CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8 1519 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1520 // CHECK1-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8 1521 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1522 // CHECK1-NEXT: store ptr @.offload_sizes.7, ptr [[TMP25]], align 8 1523 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1524 // CHECK1-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP26]], align 8 1525 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1526 // CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8 1527 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1528 // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8 1529 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1530 // CHECK1-NEXT: store i64 0, ptr [[TMP29]], align 8 1531 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1532 // CHECK1-NEXT: store i64 0, ptr [[TMP30]], align 8 1533 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1534 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4 1535 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1536 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 1537 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1538 // CHECK1-NEXT: store i32 0, ptr [[TMP33]], align 4 1539 // CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, ptr [[KERNEL_ARGS]]) 1540 // CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 1541 // CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1542 // CHECK1: omp_offload.failed: 1543 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]] 1544 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1545 // CHECK1: omp_offload.cont: 1546 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1547 // CHECK1: omp_if.else: 1548 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]] 1549 // CHECK1-NEXT: br label [[OMP_IF_END]] 1550 // CHECK1: omp_if.end: 1551 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 1552 // CHECK1-NEXT: ret i32 [[TMP36]] 1553 // 1554 // 1555 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1556 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1557 // CHECK1-NEXT: entry: 1558 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1559 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1560 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1561 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1562 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1563 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1564 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 1565 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 1566 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 1567 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1568 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1569 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 1570 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 1571 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 1572 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 1573 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 1574 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 1575 // CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 1576 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1577 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 1578 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1579 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1580 // CHECK1: omp_if.then: 1581 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1582 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 1583 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1584 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 8 1585 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1586 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 1587 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1588 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 8 1589 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1590 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP9]], align 8 1591 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1592 // CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8 1593 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1594 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP11]], align 8 1595 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1596 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP12]], align 8 1597 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1598 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8 1599 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1600 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1601 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1602 // CHECK1-NEXT: store i32 2, ptr [[TMP16]], align 4 1603 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1604 // CHECK1-NEXT: store i32 3, ptr [[TMP17]], align 4 1605 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1606 // CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8 1607 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1608 // CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8 1609 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1610 // CHECK1-NEXT: store ptr @.offload_sizes.9, ptr [[TMP20]], align 8 1611 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1612 // CHECK1-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP21]], align 8 1613 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1614 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 1615 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1616 // CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8 1617 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1618 // CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 8 1619 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1620 // CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 8 1621 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1622 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4 1623 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1624 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 1625 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1626 // CHECK1-NEXT: store i32 0, ptr [[TMP28]], align 4 1627 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, ptr [[KERNEL_ARGS]]) 1628 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 1629 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1630 // CHECK1: omp_offload.failed: 1631 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] 1632 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1633 // CHECK1: omp_offload.cont: 1634 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1635 // CHECK1: omp_if.else: 1636 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] 1637 // CHECK1-NEXT: br label [[OMP_IF_END]] 1638 // CHECK1: omp_if.end: 1639 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 1640 // CHECK1-NEXT: ret i32 [[TMP31]] 1641 // 1642 // 1643 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 1644 // CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1645 // CHECK1-NEXT: entry: 1646 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1647 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1648 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1649 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1650 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1651 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1652 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1653 // CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 1654 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1655 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1656 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1657 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1658 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1659 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1660 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1661 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 1662 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 1663 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8 1664 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) 1665 // CHECK1-NEXT: ret void 1666 // 1667 // 1668 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined 1669 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 1670 // CHECK1-NEXT: entry: 1671 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1672 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1673 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1674 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1675 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1676 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1677 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1678 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1679 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 1680 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1681 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1682 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1683 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1684 // CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8 1685 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1686 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1687 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1688 // CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 1689 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1690 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1691 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1692 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1693 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1694 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1695 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1696 // CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 1697 // CHECK1-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 1698 // CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 1699 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1700 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1701 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 1702 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 1703 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 1704 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 1705 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1706 // CHECK1: cond.true: 1707 // CHECK1-NEXT: br label [[COND_END:%.*]] 1708 // CHECK1: cond.false: 1709 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 1710 // CHECK1-NEXT: br label [[COND_END]] 1711 // CHECK1: cond.end: 1712 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1713 // CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 1714 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 1715 // CHECK1-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8 1716 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1717 // CHECK1: omp.inner.for.cond: 1718 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38:![0-9]+]] 1719 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP38]] 1720 // CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 1721 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1722 // CHECK1: omp.inner.for.body: 1723 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 1724 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 1725 // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 1726 // CHECK1-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP38]] 1727 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]] 1728 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 1729 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 1730 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 1731 // CHECK1-NEXT: store double [[ADD]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP38]] 1732 // CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 1733 // CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP38]] 1734 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 1735 // CHECK1-NEXT: store double [[INC]], ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP38]] 1736 // CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 1737 // CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 1738 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]] 1739 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 1740 // CHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP38]] 1741 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1742 // CHECK1: omp.body.continue: 1743 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1744 // CHECK1: omp.inner.for.inc: 1745 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 1746 // CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 1747 // CHECK1-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 1748 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]] 1749 // CHECK1: omp.inner.for.end: 1750 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1751 // CHECK1: omp.loop.exit: 1752 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 1753 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1754 // CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 1755 // CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1756 // CHECK1: .omp.final.then: 1757 // CHECK1-NEXT: store i64 400, ptr [[IT]], align 8 1758 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1759 // CHECK1: .omp.final.done: 1760 // CHECK1-NEXT: ret void 1761 // 1762 // 1763 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 1764 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1765 // CHECK1-NEXT: entry: 1766 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1767 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1768 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1769 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1770 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1771 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1772 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1773 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1774 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1775 // CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 1776 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1777 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1778 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 1779 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 1780 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 1781 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1782 // CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 1783 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1784 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 1785 // CHECK1-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 1786 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 1787 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]]) 1788 // CHECK1-NEXT: ret void 1789 // 1790 // 1791 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined 1792 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1793 // CHECK1-NEXT: entry: 1794 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1795 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1796 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1797 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1798 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1799 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1800 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1801 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1802 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1803 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1804 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1805 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1806 // CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 1807 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1808 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1809 // CHECK1-NEXT: ret void 1810 // 1811 // 1812 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 1813 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1814 // CHECK1-NEXT: entry: 1815 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1816 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1817 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1818 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1819 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1820 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1821 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1822 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1823 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1824 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 1825 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 1826 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 1827 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1828 // CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 1829 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1830 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) 1831 // CHECK1-NEXT: ret void 1832 // 1833 // 1834 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined 1835 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1836 // CHECK1-NEXT: entry: 1837 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1838 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1839 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1840 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1841 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1842 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1843 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 1844 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1845 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1846 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1847 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1848 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 1849 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1850 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1851 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1852 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1853 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1854 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1855 // CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 1856 // CHECK1-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 1857 // CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 1858 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1859 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1860 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 1861 // CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 1862 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 1863 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 1864 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1865 // CHECK1: cond.true: 1866 // CHECK1-NEXT: br label [[COND_END:%.*]] 1867 // CHECK1: cond.false: 1868 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 1869 // CHECK1-NEXT: br label [[COND_END]] 1870 // CHECK1: cond.end: 1871 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1872 // CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 1873 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 1874 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 1875 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1876 // CHECK1: omp.inner.for.cond: 1877 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41:![0-9]+]] 1878 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP41]] 1879 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 1880 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1881 // CHECK1: omp.inner.for.body: 1882 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41]] 1883 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 1884 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 1885 // CHECK1-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP41]] 1886 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]] 1887 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 1888 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]] 1889 // CHECK1-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]] 1890 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 1891 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 1892 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 1893 // CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]] 1894 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 1895 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]] 1896 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 1897 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]] 1898 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1899 // CHECK1: omp.body.continue: 1900 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1901 // CHECK1: omp.inner.for.inc: 1902 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41]] 1903 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 1904 // CHECK1-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41]] 1905 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]] 1906 // CHECK1: omp.inner.for.end: 1907 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1908 // CHECK1: omp.loop.exit: 1909 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 1910 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1911 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1912 // CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1913 // CHECK1: .omp.final.then: 1914 // CHECK1-NEXT: store i64 11, ptr [[I]], align 8 1915 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1916 // CHECK1: .omp.final.done: 1917 // CHECK1-NEXT: ret void 1918 // 1919 // 1920 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1921 // CHECK1-SAME: () #[[ATTR8:[0-9]+]] { 1922 // CHECK1-NEXT: entry: 1923 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1924 // CHECK1-NEXT: ret void 1925 // 1926 // 1927 // CHECK3-LABEL: define {{[^@]+}}@_Z7get_valv 1928 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 1929 // CHECK3-NEXT: entry: 1930 // CHECK3-NEXT: ret i64 0 1931 // 1932 // 1933 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 1934 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 1935 // CHECK3-NEXT: entry: 1936 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1937 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 1938 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 1939 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 1940 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 1941 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1942 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 1943 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1944 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 1945 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 1946 // CHECK3-NEXT: [[K:%.*]] = alloca i64, align 8 1947 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1948 // CHECK3-NEXT: [[LIN:%.*]] = alloca i32, align 4 1949 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 1950 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 1951 // CHECK3-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 1952 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 1953 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 1954 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 1955 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1956 // CHECK3-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 1957 // CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 1958 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 4 1959 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 4 1960 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 4 1961 // CHECK3-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 1962 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1963 // CHECK3-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 1964 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 1965 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 4 1966 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 4 1967 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 4 1968 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 1969 // CHECK3-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 1970 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 1971 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1972 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 1973 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 1974 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 1975 // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() 1976 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 1977 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 1978 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 1979 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 1980 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 1981 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 1982 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 1983 // CHECK3-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, ptr @.omp_task_entry., i64 -1) 1984 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP5]], i32 0, i32 0 1985 // CHECK3-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP5]]) 1986 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 1987 // CHECK3-NEXT: store i64 [[CALL]], ptr [[K]], align 8 1988 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 1989 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 1990 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 1991 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP9]], ptr [[K]]) #[[ATTR4:[0-9]+]] 1992 // CHECK3-NEXT: store i32 12, ptr [[LIN]], align 4 1993 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2 1994 // CHECK3-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2 1995 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4 1996 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[LIN]], align 4 1997 // CHECK3-NEXT: store i32 [[TMP12]], ptr [[LIN_CASTED]], align 4 1998 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 1999 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4 2000 // CHECK3-NEXT: store i32 [[TMP14]], ptr [[A_CASTED2]], align 4 2001 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[A_CASTED2]], align 4 2002 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2003 // CHECK3-NEXT: store i32 [[TMP11]], ptr [[TMP16]], align 4 2004 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2005 // CHECK3-NEXT: store i32 [[TMP11]], ptr [[TMP17]], align 4 2006 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2007 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 2008 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2009 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[TMP19]], align 4 2010 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2011 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[TMP20]], align 4 2012 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2013 // CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 4 2014 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2015 // CHECK3-NEXT: store i32 [[TMP15]], ptr [[TMP22]], align 4 2016 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2017 // CHECK3-NEXT: store i32 [[TMP15]], ptr [[TMP23]], align 4 2018 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2019 // CHECK3-NEXT: store ptr null, ptr [[TMP24]], align 4 2020 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2021 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2022 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2023 // CHECK3-NEXT: store i32 2, ptr [[TMP27]], align 4 2024 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2025 // CHECK3-NEXT: store i32 3, ptr [[TMP28]], align 4 2026 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2027 // CHECK3-NEXT: store ptr [[TMP25]], ptr [[TMP29]], align 4 2028 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2029 // CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP30]], align 4 2030 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2031 // CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP31]], align 4 2032 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2033 // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP32]], align 4 2034 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 2035 // CHECK3-NEXT: store ptr null, ptr [[TMP33]], align 4 2036 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 2037 // CHECK3-NEXT: store ptr null, ptr [[TMP34]], align 4 2038 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 2039 // CHECK3-NEXT: store i64 0, ptr [[TMP35]], align 8 2040 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 2041 // CHECK3-NEXT: store i64 0, ptr [[TMP36]], align 8 2042 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 2043 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP37]], align 4 2044 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 2045 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP38]], align 4 2046 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 2047 // CHECK3-NEXT: store i32 0, ptr [[TMP39]], align 4 2048 // CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, ptr [[KERNEL_ARGS]]) 2049 // CHECK3-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 2050 // CHECK3-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2051 // CHECK3: omp_offload.failed: 2052 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP11]], i32 [[TMP13]], i32 [[TMP15]]) #[[ATTR4]] 2053 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2054 // CHECK3: omp_offload.cont: 2055 // CHECK3-NEXT: [[TMP42:%.*]] = load i32, ptr [[A]], align 4 2056 // CHECK3-NEXT: store i32 [[TMP42]], ptr [[A_CASTED3]], align 4 2057 // CHECK3-NEXT: [[TMP43:%.*]] = load i32, ptr [[A_CASTED3]], align 4 2058 // CHECK3-NEXT: [[TMP44:%.*]] = load i16, ptr [[AA]], align 2 2059 // CHECK3-NEXT: store i16 [[TMP44]], ptr [[AA_CASTED4]], align 2 2060 // CHECK3-NEXT: [[TMP45:%.*]] = load i32, ptr [[AA_CASTED4]], align 4 2061 // CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[N_ADDR]], align 4 2062 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP46]], 10 2063 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2064 // CHECK3: omp_if.then: 2065 // CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 2066 // CHECK3-NEXT: store i32 [[TMP43]], ptr [[TMP47]], align 4 2067 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 2068 // CHECK3-NEXT: store i32 [[TMP43]], ptr [[TMP48]], align 4 2069 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 2070 // CHECK3-NEXT: store ptr null, ptr [[TMP49]], align 4 2071 // CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 2072 // CHECK3-NEXT: store i32 [[TMP45]], ptr [[TMP50]], align 4 2073 // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 2074 // CHECK3-NEXT: store i32 [[TMP45]], ptr [[TMP51]], align 4 2075 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 2076 // CHECK3-NEXT: store ptr null, ptr [[TMP52]], align 4 2077 // CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 2078 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 2079 // CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0 2080 // CHECK3-NEXT: store i32 2, ptr [[TMP55]], align 4 2081 // CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1 2082 // CHECK3-NEXT: store i32 2, ptr [[TMP56]], align 4 2083 // CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2 2084 // CHECK3-NEXT: store ptr [[TMP53]], ptr [[TMP57]], align 4 2085 // CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3 2086 // CHECK3-NEXT: store ptr [[TMP54]], ptr [[TMP58]], align 4 2087 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4 2088 // CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP59]], align 4 2089 // CHECK3-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5 2090 // CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP60]], align 4 2091 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6 2092 // CHECK3-NEXT: store ptr null, ptr [[TMP61]], align 4 2093 // CHECK3-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7 2094 // CHECK3-NEXT: store ptr null, ptr [[TMP62]], align 4 2095 // CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8 2096 // CHECK3-NEXT: store i64 0, ptr [[TMP63]], align 8 2097 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 9 2098 // CHECK3-NEXT: store i64 0, ptr [[TMP64]], align 8 2099 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 10 2100 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP65]], align 4 2101 // CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 11 2102 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP66]], align 4 2103 // CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12 2104 // CHECK3-NEXT: store i32 0, ptr [[TMP67]], align 4 2105 // CHECK3-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, ptr [[KERNEL_ARGS8]]) 2106 // CHECK3-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 2107 // CHECK3-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 2108 // CHECK3: omp_offload.failed9: 2109 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR4]] 2110 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT10]] 2111 // CHECK3: omp_offload.cont10: 2112 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2113 // CHECK3: omp_if.else: 2114 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR4]] 2115 // CHECK3-NEXT: br label [[OMP_IF_END]] 2116 // CHECK3: omp_if.end: 2117 // CHECK3-NEXT: [[TMP70:%.*]] = load i32, ptr [[A]], align 4 2118 // CHECK3-NEXT: store i32 [[TMP70]], ptr [[DOTCAPTURE_EXPR_]], align 4 2119 // CHECK3-NEXT: [[TMP71:%.*]] = load i32, ptr [[A]], align 4 2120 // CHECK3-NEXT: store i32 [[TMP71]], ptr [[A_CASTED11]], align 4 2121 // CHECK3-NEXT: [[TMP72:%.*]] = load i32, ptr [[A_CASTED11]], align 4 2122 // CHECK3-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 2123 // CHECK3-NEXT: store i32 [[TMP73]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 2124 // CHECK3-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 2125 // CHECK3-NEXT: [[TMP75:%.*]] = load i32, ptr [[N_ADDR]], align 4 2126 // CHECK3-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP75]], 20 2127 // CHECK3-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]] 2128 // CHECK3: omp_if.then13: 2129 // CHECK3-NEXT: [[TMP76:%.*]] = mul nuw i32 [[TMP1]], 4 2130 // CHECK3-NEXT: [[TMP77:%.*]] = sext i32 [[TMP76]] to i64 2131 // CHECK3-NEXT: [[TMP78:%.*]] = mul nuw i32 5, [[TMP3]] 2132 // CHECK3-NEXT: [[TMP79:%.*]] = mul nuw i32 [[TMP78]], 8 2133 // CHECK3-NEXT: [[TMP80:%.*]] = sext i32 [[TMP79]] to i64 2134 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.3, i32 80, i1 false) 2135 // CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 2136 // CHECK3-NEXT: store i32 [[TMP72]], ptr [[TMP81]], align 4 2137 // CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 2138 // CHECK3-NEXT: store i32 [[TMP72]], ptr [[TMP82]], align 4 2139 // CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 2140 // CHECK3-NEXT: store ptr null, ptr [[TMP83]], align 4 2141 // CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 2142 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP84]], align 4 2143 // CHECK3-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 2144 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP85]], align 4 2145 // CHECK3-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 2146 // CHECK3-NEXT: store ptr null, ptr [[TMP86]], align 4 2147 // CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 2148 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP87]], align 4 2149 // CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 2150 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP88]], align 4 2151 // CHECK3-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 2152 // CHECK3-NEXT: store ptr null, ptr [[TMP89]], align 4 2153 // CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 2154 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP90]], align 4 2155 // CHECK3-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 2156 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP91]], align 4 2157 // CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 2158 // CHECK3-NEXT: store i64 [[TMP77]], ptr [[TMP92]], align 4 2159 // CHECK3-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 2160 // CHECK3-NEXT: store ptr null, ptr [[TMP93]], align 4 2161 // CHECK3-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 2162 // CHECK3-NEXT: store ptr [[C]], ptr [[TMP94]], align 4 2163 // CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 2164 // CHECK3-NEXT: store ptr [[C]], ptr [[TMP95]], align 4 2165 // CHECK3-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 2166 // CHECK3-NEXT: store ptr null, ptr [[TMP96]], align 4 2167 // CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 2168 // CHECK3-NEXT: store i32 5, ptr [[TMP97]], align 4 2169 // CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 2170 // CHECK3-NEXT: store i32 5, ptr [[TMP98]], align 4 2171 // CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 2172 // CHECK3-NEXT: store ptr null, ptr [[TMP99]], align 4 2173 // CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 2174 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP100]], align 4 2175 // CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 2176 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP101]], align 4 2177 // CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 2178 // CHECK3-NEXT: store ptr null, ptr [[TMP102]], align 4 2179 // CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 2180 // CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP103]], align 4 2181 // CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 2182 // CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP104]], align 4 2183 // CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 2184 // CHECK3-NEXT: store i64 [[TMP80]], ptr [[TMP105]], align 4 2185 // CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 2186 // CHECK3-NEXT: store ptr null, ptr [[TMP106]], align 4 2187 // CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 2188 // CHECK3-NEXT: store ptr [[D]], ptr [[TMP107]], align 4 2189 // CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 2190 // CHECK3-NEXT: store ptr [[D]], ptr [[TMP108]], align 4 2191 // CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 2192 // CHECK3-NEXT: store ptr null, ptr [[TMP109]], align 4 2193 // CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 2194 // CHECK3-NEXT: store i32 [[TMP74]], ptr [[TMP110]], align 4 2195 // CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 2196 // CHECK3-NEXT: store i32 [[TMP74]], ptr [[TMP111]], align 4 2197 // CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 2198 // CHECK3-NEXT: store ptr null, ptr [[TMP112]], align 4 2199 // CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 2200 // CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 2201 // CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2202 // CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0 2203 // CHECK3-NEXT: store i32 2, ptr [[TMP116]], align 4 2204 // CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1 2205 // CHECK3-NEXT: store i32 10, ptr [[TMP117]], align 4 2206 // CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2 2207 // CHECK3-NEXT: store ptr [[TMP113]], ptr [[TMP118]], align 4 2208 // CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3 2209 // CHECK3-NEXT: store ptr [[TMP114]], ptr [[TMP119]], align 4 2210 // CHECK3-NEXT: [[TMP120:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4 2211 // CHECK3-NEXT: store ptr [[TMP115]], ptr [[TMP120]], align 4 2212 // CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5 2213 // CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP121]], align 4 2214 // CHECK3-NEXT: [[TMP122:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6 2215 // CHECK3-NEXT: store ptr null, ptr [[TMP122]], align 4 2216 // CHECK3-NEXT: [[TMP123:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7 2217 // CHECK3-NEXT: store ptr null, ptr [[TMP123]], align 4 2218 // CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8 2219 // CHECK3-NEXT: store i64 0, ptr [[TMP124]], align 8 2220 // CHECK3-NEXT: [[TMP125:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 9 2221 // CHECK3-NEXT: store i64 0, ptr [[TMP125]], align 8 2222 // CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 10 2223 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP126]], align 4 2224 // CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 11 2225 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP127]], align 4 2226 // CHECK3-NEXT: [[TMP128:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12 2227 // CHECK3-NEXT: store i32 0, ptr [[TMP128]], align 4 2228 // CHECK3-NEXT: [[TMP129:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, ptr [[KERNEL_ARGS17]]) 2229 // CHECK3-NEXT: [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 0 2230 // CHECK3-NEXT: br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] 2231 // CHECK3: omp_offload.failed18: 2232 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR4]] 2233 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT19]] 2234 // CHECK3: omp_offload.cont19: 2235 // CHECK3-NEXT: br label [[OMP_IF_END21:%.*]] 2236 // CHECK3: omp_if.else20: 2237 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR4]] 2238 // CHECK3-NEXT: br label [[OMP_IF_END21]] 2239 // CHECK3: omp_if.end21: 2240 // CHECK3-NEXT: [[TMP131:%.*]] = load i32, ptr [[A]], align 4 2241 // CHECK3-NEXT: [[TMP132:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 2242 // CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP132]]) 2243 // CHECK3-NEXT: ret i32 [[TMP131]] 2244 // 2245 // 2246 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 2247 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] { 2248 // CHECK3-NEXT: entry: 2249 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) 2250 // CHECK3-NEXT: ret void 2251 // 2252 // 2253 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined 2254 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 2255 // CHECK3-NEXT: entry: 2256 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2257 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2258 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2259 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2260 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2261 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2262 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2263 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2264 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2265 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2266 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2267 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2268 // CHECK3-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 2269 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2270 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2271 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2272 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2273 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2274 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2275 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 2276 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2277 // CHECK3: cond.true: 2278 // CHECK3-NEXT: br label [[COND_END:%.*]] 2279 // CHECK3: cond.false: 2280 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2281 // CHECK3-NEXT: br label [[COND_END]] 2282 // CHECK3: cond.end: 2283 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2284 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2285 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2286 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2287 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2288 // CHECK3: omp.inner.for.cond: 2289 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 2290 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 2291 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2292 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2293 // CHECK3: omp.inner.for.body: 2294 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 2295 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 2296 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 2297 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 2298 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2299 // CHECK3: omp.body.continue: 2300 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2301 // CHECK3: omp.inner.for.inc: 2302 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 2303 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 2304 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 2305 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 2306 // CHECK3: omp.inner.for.end: 2307 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2308 // CHECK3: omp.loop.exit: 2309 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2310 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2311 // CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 2312 // CHECK3-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2313 // CHECK3: .omp.final.then: 2314 // CHECK3-NEXT: store i32 33, ptr [[I]], align 4 2315 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2316 // CHECK3: .omp.final.done: 2317 // CHECK3-NEXT: ret void 2318 // 2319 // 2320 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 2321 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 2322 // CHECK3-NEXT: entry: 2323 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 2324 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4 2325 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4 2326 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4 2327 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4 2328 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4 2329 // CHECK3-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2330 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 2331 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 2332 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 2333 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 2334 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 2335 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 2336 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 2337 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 2338 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 2339 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 2340 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 2341 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 2342 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 2343 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) 2344 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 2345 // CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias !26 2346 // CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26 2347 // CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26 2348 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias !26 2349 // CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !26 2350 // CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !26 2351 // CHECK3-NEXT: store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !26 2352 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 2353 // CHECK3-NEXT: store i32 0, ptr [[TMP9]], align 4, !noalias !26 2354 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 2355 // CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 4, !noalias !26 2356 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 2357 // CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4, !noalias !26 2358 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 2359 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4, !noalias !26 2360 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 2361 // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4, !noalias !26 2362 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 2363 // CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4, !noalias !26 2364 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 2365 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4, !noalias !26 2366 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 2367 // CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8, !noalias !26 2368 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9 2369 // CHECK3-NEXT: store i64 1, ptr [[TMP17]], align 8, !noalias !26 2370 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10 2371 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4, !noalias !26 2372 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11 2373 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4, !noalias !26 2374 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12 2375 // CHECK3-NEXT: store i32 0, ptr [[TMP20]], align 4, !noalias !26 2376 // CHECK3-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, ptr [[KERNEL_ARGS_I]]) 2377 // CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 2378 // CHECK3-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] 2379 // CHECK3: omp_offload.failed.i: 2380 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] 2381 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] 2382 // CHECK3: .omp_outlined..exit: 2383 // CHECK3-NEXT: ret i32 0 2384 // 2385 // 2386 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 2387 // CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 2388 // CHECK3-NEXT: entry: 2389 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2390 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4 2391 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2392 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2393 // CHECK3-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4 2394 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4 2395 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 2396 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 2397 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 2398 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i32 [[TMP2]], ptr [[TMP0]]) 2399 // CHECK3-NEXT: ret void 2400 // 2401 // 2402 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined 2403 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 2404 // CHECK3-NEXT: entry: 2405 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2406 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2407 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2408 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4 2409 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2410 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2411 // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 2412 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2413 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2414 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2415 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2416 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2417 // CHECK3-NEXT: [[K1:%.*]] = alloca i64, align 8 2418 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2419 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2420 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2421 // CHECK3-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4 2422 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4 2423 // CHECK3-NEXT: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 8 2424 // CHECK3-NEXT: store i64 [[TMP1]], ptr [[DOTLINEAR_START]], align 8 2425 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2426 // CHECK3-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 4 2427 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2428 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2429 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2430 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 2431 // CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 2432 // CHECK3-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1) 2433 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2434 // CHECK3: omp.dispatch.cond: 2435 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]) 2436 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 2437 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2438 // CHECK3: omp.dispatch.body: 2439 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2440 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 2441 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2442 // CHECK3: omp.inner.for.cond: 2443 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] 2444 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] 2445 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 2446 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2447 // CHECK3: omp.inner.for.body: 2448 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 2449 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 2450 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 2451 // CHECK3-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] 2452 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP27]] 2453 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 2454 // CHECK3-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 2455 // CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 2456 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 2457 // CHECK3-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP27]] 2458 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 2459 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 2460 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 2461 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2462 // CHECK3: omp.body.continue: 2463 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2464 // CHECK3: omp.inner.for.inc: 2465 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 2466 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 2467 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 2468 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 2469 // CHECK3: omp.inner.for.end: 2470 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2471 // CHECK3: omp.dispatch.inc: 2472 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2473 // CHECK3: omp.dispatch.end: 2474 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2475 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 2476 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2477 // CHECK3: .omp.final.then: 2478 // CHECK3-NEXT: store i32 1, ptr [[I]], align 4 2479 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2480 // CHECK3: .omp.final.done: 2481 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2482 // CHECK3-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 2483 // CHECK3-NEXT: br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 2484 // CHECK3: .omp.linear.pu: 2485 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, ptr [[K1]], align 8 2486 // CHECK3-NEXT: store i64 [[TMP17]], ptr [[TMP0]], align 8 2487 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 2488 // CHECK3: .omp.linear.pu.done: 2489 // CHECK3-NEXT: ret void 2490 // 2491 // 2492 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 2493 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 2494 // CHECK3-NEXT: entry: 2495 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2496 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 2497 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2498 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2499 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 2500 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2501 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2502 // CHECK3-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 2503 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2504 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2505 // CHECK3-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 2506 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 2507 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 2508 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 2509 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 2510 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 2511 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 2512 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4 2513 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 2514 // CHECK3-NEXT: ret void 2515 // 2516 // 2517 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined 2518 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 2519 // CHECK3-NEXT: entry: 2520 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2521 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2522 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2523 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 2524 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2525 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2526 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 2527 // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 2528 // CHECK3-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 2529 // CHECK3-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 2530 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2531 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2532 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2533 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2534 // CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8 2535 // CHECK3-NEXT: [[LIN2:%.*]] = alloca i32, align 4 2536 // CHECK3-NEXT: [[A3:%.*]] = alloca i32, align 4 2537 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2538 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2539 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2540 // CHECK3-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 2541 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2542 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 2543 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 2544 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 2545 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 2546 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 2547 // CHECK3-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 2548 // CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 2549 // CHECK3-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 2550 // CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 2551 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2552 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2553 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 2554 // CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]]) 2555 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 2556 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 2557 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 2558 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2559 // CHECK3: cond.true: 2560 // CHECK3-NEXT: br label [[COND_END:%.*]] 2561 // CHECK3: cond.false: 2562 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 2563 // CHECK3-NEXT: br label [[COND_END]] 2564 // CHECK3: cond.end: 2565 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2566 // CHECK3-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 2567 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 2568 // CHECK3-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 2569 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2570 // CHECK3: omp.inner.for.cond: 2571 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30:![0-9]+]] 2572 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP30]] 2573 // CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 2574 // CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2575 // CHECK3: omp.inner.for.body: 2576 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2577 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 2578 // CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 2579 // CHECK3-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP30]] 2580 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP30]] 2581 // CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 2582 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2583 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]] 2584 // CHECK3-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 2585 // CHECK3-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 2586 // CHECK3-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 2587 // CHECK3-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP30]] 2588 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP30]] 2589 // CHECK3-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 2590 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2591 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]] 2592 // CHECK3-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 2593 // CHECK3-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 2594 // CHECK3-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 2595 // CHECK3-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP30]] 2596 // CHECK3-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] 2597 // CHECK3-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 2598 // CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 2599 // CHECK3-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 2600 // CHECK3-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] 2601 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2602 // CHECK3: omp.body.continue: 2603 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2604 // CHECK3: omp.inner.for.inc: 2605 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2606 // CHECK3-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 2607 // CHECK3-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2608 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 2609 // CHECK3: omp.inner.for.end: 2610 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2611 // CHECK3: omp.loop.exit: 2612 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 2613 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2614 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 2615 // CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2616 // CHECK3: .omp.final.then: 2617 // CHECK3-NEXT: store i64 400, ptr [[IT]], align 8 2618 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2619 // CHECK3: .omp.final.done: 2620 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2621 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 2622 // CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 2623 // CHECK3: .omp.linear.pu: 2624 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 2625 // CHECK3-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 2626 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 2627 // CHECK3-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 2628 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 2629 // CHECK3: .omp.linear.pu.done: 2630 // CHECK3-NEXT: ret void 2631 // 2632 // 2633 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 2634 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2635 // CHECK3-NEXT: entry: 2636 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2637 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2638 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2639 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2640 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2641 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2642 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2643 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 2644 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 2645 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2646 // CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 2647 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 2648 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) 2649 // CHECK3-NEXT: ret void 2650 // 2651 // 2652 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined 2653 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 2654 // CHECK3-NEXT: entry: 2655 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2656 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2657 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2658 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2659 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2660 // CHECK3-NEXT: [[TMP:%.*]] = alloca i16, align 2 2661 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2662 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2663 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2664 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2665 // CHECK3-NEXT: [[IT:%.*]] = alloca i16, align 2 2666 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2667 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2668 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2669 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2670 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2671 // CHECK3-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 2672 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2673 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2674 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2675 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2676 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2677 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2678 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 2679 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2680 // CHECK3: cond.true: 2681 // CHECK3-NEXT: br label [[COND_END:%.*]] 2682 // CHECK3: cond.false: 2683 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2684 // CHECK3-NEXT: br label [[COND_END]] 2685 // CHECK3: cond.end: 2686 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2687 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2688 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2689 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2690 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2691 // CHECK3: omp.inner.for.cond: 2692 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] 2693 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] 2694 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2695 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2696 // CHECK3: omp.inner.for.body: 2697 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 2698 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 2699 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 2700 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 2701 // CHECK3-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP33]] 2702 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 2703 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 2704 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 2705 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] 2706 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 2707 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 2708 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 2709 // CHECK3-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] 2710 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2711 // CHECK3: omp.body.continue: 2712 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2713 // CHECK3: omp.inner.for.inc: 2714 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 2715 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 2716 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 2717 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 2718 // CHECK3: omp.inner.for.end: 2719 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2720 // CHECK3: omp.loop.exit: 2721 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2722 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2723 // CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 2724 // CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2725 // CHECK3: .omp.final.then: 2726 // CHECK3-NEXT: store i16 22, ptr [[IT]], align 2 2727 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2728 // CHECK3: .omp.final.done: 2729 // CHECK3-NEXT: ret void 2730 // 2731 // 2732 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 2733 // CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 2734 // CHECK3-NEXT: entry: 2735 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2736 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 2737 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2738 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 2739 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 2740 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2741 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2742 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 2743 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 2744 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2745 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2746 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 2747 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2748 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 2749 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 2750 // CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 2751 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 2752 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 2753 // CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 2754 // CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 2755 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 2756 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2757 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 2758 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 2759 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 2760 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 2761 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 2762 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 2763 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 2764 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 2765 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 2766 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 2767 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 2768 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2769 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 2770 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 2771 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]]) 2772 // CHECK3-NEXT: ret void 2773 // 2774 // 2775 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined 2776 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 2777 // CHECK3-NEXT: entry: 2778 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2779 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2780 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2781 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 2782 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2783 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 2784 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 2785 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2786 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2787 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 2788 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 2789 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2790 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2791 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 2792 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2793 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2794 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2795 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2796 // CHECK3-NEXT: [[IT:%.*]] = alloca i8, align 1 2797 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2798 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2799 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2800 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 2801 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 2802 // CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 2803 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 2804 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 2805 // CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 2806 // CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 2807 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 2808 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2809 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 2810 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 2811 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 2812 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 2813 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 2814 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 2815 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 2816 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 2817 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2818 // CHECK3-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 2819 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2820 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2821 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2822 // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2823 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 2824 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 2825 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2826 // CHECK3: omp.dispatch.cond: 2827 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2828 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 2829 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2830 // CHECK3: cond.true: 2831 // CHECK3-NEXT: br label [[COND_END:%.*]] 2832 // CHECK3: cond.false: 2833 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2834 // CHECK3-NEXT: br label [[COND_END]] 2835 // CHECK3: cond.end: 2836 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 2837 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2838 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2839 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 2840 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2841 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2842 // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 2843 // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2844 // CHECK3: omp.dispatch.body: 2845 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2846 // CHECK3: omp.inner.for.cond: 2847 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] 2848 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]] 2849 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 2850 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2851 // CHECK3: omp.inner.for.body: 2852 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 2853 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 2854 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 2855 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 2856 // CHECK3-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP36]] 2857 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] 2858 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 2859 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] 2860 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 2861 // CHECK3-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] 2862 // CHECK3-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 2863 // CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 2864 // CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 2865 // CHECK3-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] 2866 // CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 2867 // CHECK3-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]] 2868 // CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 2869 // CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 2870 // CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 2871 // CHECK3-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]] 2872 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 2873 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 2874 // CHECK3-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] 2875 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 2876 // CHECK3-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] 2877 // CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 2878 // CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]] 2879 // CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3 2880 // CHECK3-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]] 2881 // CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 2882 // CHECK3-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]] 2883 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 2884 // CHECK3-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]] 2885 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 2886 // CHECK3-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]] 2887 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 2888 // CHECK3-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]] 2889 // CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 2890 // CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 2891 // CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 2892 // CHECK3-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]] 2893 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2894 // CHECK3: omp.body.continue: 2895 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2896 // CHECK3: omp.inner.for.inc: 2897 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 2898 // CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 2899 // CHECK3-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 2900 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] 2901 // CHECK3: omp.inner.for.end: 2902 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2903 // CHECK3: omp.dispatch.inc: 2904 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2905 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2906 // CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 2907 // CHECK3-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 2908 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2909 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2910 // CHECK3-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 2911 // CHECK3-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 2912 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2913 // CHECK3: omp.dispatch.end: 2914 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 2915 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2916 // CHECK3-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 2917 // CHECK3-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2918 // CHECK3: .omp.final.then: 2919 // CHECK3-NEXT: store i8 96, ptr [[IT]], align 1 2920 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2921 // CHECK3: .omp.final.done: 2922 // CHECK3-NEXT: ret void 2923 // 2924 // 2925 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 2926 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 2927 // CHECK3-NEXT: entry: 2928 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2929 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2930 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 2931 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2932 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 2933 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 2934 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 2935 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 2936 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2937 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A]], align 4 2938 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 2939 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 2940 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 2941 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2942 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 2943 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 2944 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 2945 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 2946 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2947 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 2948 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 2949 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 2950 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 2951 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 2952 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 2953 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 2954 // CHECK3-NEXT: ret i32 [[TMP8]] 2955 // 2956 // 2957 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2958 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2959 // CHECK3-NEXT: entry: 2960 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2961 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2962 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 2963 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 2964 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2965 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2966 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 2967 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 2968 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 2969 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 2970 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2971 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2972 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2973 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2974 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 2975 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2976 // CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4 2977 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 2978 // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() 2979 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 2980 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 2981 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 2982 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 2983 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 2984 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 2985 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 2986 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 2987 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 2988 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2989 // CHECK3: omp_if.then: 2990 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 2991 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 2992 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 2993 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 2994 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 40, i1 false) 2995 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2996 // CHECK3-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 4 2997 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2998 // CHECK3-NEXT: store ptr [[A]], ptr [[TMP11]], align 4 2999 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3000 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 3001 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3002 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 4 3003 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3004 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 4 3005 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3006 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 3007 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3008 // CHECK3-NEXT: store i32 2, ptr [[TMP16]], align 4 3009 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3010 // CHECK3-NEXT: store i32 2, ptr [[TMP17]], align 4 3011 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3012 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 3013 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3014 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP19]], align 4 3015 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3016 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP20]], align 4 3017 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3018 // CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 4 3019 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3020 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 4 3021 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3022 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 4 3023 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 3024 // CHECK3-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 4 3025 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 3026 // CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4 3027 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3028 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3029 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3030 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3031 // CHECK3-NEXT: store i32 2, ptr [[TMP29]], align 4 3032 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3033 // CHECK3-NEXT: store i32 5, ptr [[TMP30]], align 4 3034 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3035 // CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 4 3036 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3037 // CHECK3-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 4 3038 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3039 // CHECK3-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 4 3040 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3041 // CHECK3-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP34]], align 4 3042 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3043 // CHECK3-NEXT: store ptr null, ptr [[TMP35]], align 4 3044 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3045 // CHECK3-NEXT: store ptr null, ptr [[TMP36]], align 4 3046 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3047 // CHECK3-NEXT: store i64 0, ptr [[TMP37]], align 8 3048 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 3049 // CHECK3-NEXT: store i64 0, ptr [[TMP38]], align 8 3050 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 3051 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 4 3052 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 3053 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4 3054 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 3055 // CHECK3-NEXT: store i32 0, ptr [[TMP41]], align 4 3056 // CHECK3-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, ptr [[KERNEL_ARGS]]) 3057 // CHECK3-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 3058 // CHECK3-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3059 // CHECK3: omp_offload.failed: 3060 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4]] 3061 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3062 // CHECK3: omp_offload.cont: 3063 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3064 // CHECK3: omp_if.else: 3065 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4]] 3066 // CHECK3-NEXT: br label [[OMP_IF_END]] 3067 // CHECK3: omp_if.end: 3068 // CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]] 3069 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]] 3070 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 3071 // CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 3072 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 3073 // CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 3074 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] 3075 // CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 3076 // CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP47]]) 3077 // CHECK3-NEXT: ret i32 [[ADD3]] 3078 // 3079 // 3080 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 3081 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 3082 // CHECK3-NEXT: entry: 3083 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3084 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3085 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3086 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 3087 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3088 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3089 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3090 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3091 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 3092 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 3093 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 3094 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3095 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 3096 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 3097 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 3098 // CHECK3-NEXT: store i8 0, ptr [[AAA]], align 1 3099 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 3100 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 3101 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 3102 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 3103 // CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 3104 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3105 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1 3106 // CHECK3-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1 3107 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 3108 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 3109 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 3110 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3111 // CHECK3: omp_if.then: 3112 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3113 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 4 3114 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3115 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 4 3116 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3117 // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 3118 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3119 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP10]], align 4 3120 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3121 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP11]], align 4 3122 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3123 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 3124 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3125 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 4 3126 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3127 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 4 3128 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3129 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 3130 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3131 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP16]], align 4 3132 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3133 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP17]], align 4 3134 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3135 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 3136 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3137 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3138 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3139 // CHECK3-NEXT: store i32 2, ptr [[TMP21]], align 4 3140 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3141 // CHECK3-NEXT: store i32 4, ptr [[TMP22]], align 4 3142 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3143 // CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4 3144 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3145 // CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4 3146 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3147 // CHECK3-NEXT: store ptr @.offload_sizes.7, ptr [[TMP25]], align 4 3148 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3149 // CHECK3-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP26]], align 4 3150 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3151 // CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 4 3152 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3153 // CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 4 3154 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3155 // CHECK3-NEXT: store i64 0, ptr [[TMP29]], align 8 3156 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 3157 // CHECK3-NEXT: store i64 0, ptr [[TMP30]], align 8 3158 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 3159 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4 3160 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 3161 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 3162 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 3163 // CHECK3-NEXT: store i32 0, ptr [[TMP33]], align 4 3164 // CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, ptr [[KERNEL_ARGS]]) 3165 // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 3166 // CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3167 // CHECK3: omp_offload.failed: 3168 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]] 3169 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3170 // CHECK3: omp_offload.cont: 3171 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3172 // CHECK3: omp_if.else: 3173 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]] 3174 // CHECK3-NEXT: br label [[OMP_IF_END]] 3175 // CHECK3: omp_if.end: 3176 // CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 3177 // CHECK3-NEXT: ret i32 [[TMP36]] 3178 // 3179 // 3180 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3181 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 3182 // CHECK3-NEXT: entry: 3183 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3184 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3185 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3186 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3187 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3188 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3189 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 3190 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 3191 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 3192 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3193 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 3194 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 3195 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 3196 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 3197 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 3198 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 3199 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 3200 // CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 3201 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3202 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 3203 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 3204 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3205 // CHECK3: omp_if.then: 3206 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3207 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 3208 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3209 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 4 3210 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3211 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 3212 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3213 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 4 3214 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3215 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP9]], align 4 3216 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3217 // CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 4 3218 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3219 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP11]], align 4 3220 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3221 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP12]], align 4 3222 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3223 // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4 3224 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3225 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3226 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3227 // CHECK3-NEXT: store i32 2, ptr [[TMP16]], align 4 3228 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3229 // CHECK3-NEXT: store i32 3, ptr [[TMP17]], align 4 3230 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3231 // CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4 3232 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3233 // CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 4 3234 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3235 // CHECK3-NEXT: store ptr @.offload_sizes.9, ptr [[TMP20]], align 4 3236 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3237 // CHECK3-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP21]], align 4 3238 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3239 // CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 4 3240 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3241 // CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 4 3242 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3243 // CHECK3-NEXT: store i64 0, ptr [[TMP24]], align 8 3244 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 3245 // CHECK3-NEXT: store i64 0, ptr [[TMP25]], align 8 3246 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 3247 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4 3248 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 3249 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 3250 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 3251 // CHECK3-NEXT: store i32 0, ptr [[TMP28]], align 4 3252 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, ptr [[KERNEL_ARGS]]) 3253 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 3254 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3255 // CHECK3: omp_offload.failed: 3256 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] 3257 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3258 // CHECK3: omp_offload.cont: 3259 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3260 // CHECK3: omp_if.else: 3261 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] 3262 // CHECK3-NEXT: br label [[OMP_IF_END]] 3263 // CHECK3: omp_if.end: 3264 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 3265 // CHECK3-NEXT: ret i32 [[TMP31]] 3266 // 3267 // 3268 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 3269 // CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3270 // CHECK3-NEXT: entry: 3271 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3272 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3273 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3274 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3275 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3276 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3277 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3278 // CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 3279 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 3280 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 3281 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3282 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3283 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 3284 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 3285 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 3286 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 3287 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 3288 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 3289 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]]) 3290 // CHECK3-NEXT: ret void 3291 // 3292 // 3293 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined 3294 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 3295 // CHECK3-NEXT: entry: 3296 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3297 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3298 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3299 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3300 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3301 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3302 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3303 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3304 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 3305 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3306 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3307 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3308 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3309 // CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8 3310 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3311 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3312 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3313 // CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 3314 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 3315 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 3316 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3317 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3318 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 3319 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 3320 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 3321 // CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 3322 // CHECK3-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 3323 // CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 3324 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3325 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3326 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 3327 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 3328 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 3329 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 3330 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3331 // CHECK3: cond.true: 3332 // CHECK3-NEXT: br label [[COND_END:%.*]] 3333 // CHECK3: cond.false: 3334 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 3335 // CHECK3-NEXT: br label [[COND_END]] 3336 // CHECK3: cond.end: 3337 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3338 // CHECK3-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 3339 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 3340 // CHECK3-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8 3341 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3342 // CHECK3: omp.inner.for.cond: 3343 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39:![0-9]+]] 3344 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP39]] 3345 // CHECK3-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 3346 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3347 // CHECK3: omp.inner.for.body: 3348 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 3349 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 3350 // CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 3351 // CHECK3-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP39]] 3352 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]] 3353 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 3354 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3355 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 3356 // CHECK3-NEXT: store double [[ADD]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP39]] 3357 // CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 3358 // CHECK3-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP39]] 3359 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 3360 // CHECK3-NEXT: store double [[INC]], ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP39]] 3361 // CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 3362 // CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 3363 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]] 3364 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 3365 // CHECK3-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP39]] 3366 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3367 // CHECK3: omp.body.continue: 3368 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3369 // CHECK3: omp.inner.for.inc: 3370 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 3371 // CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 3372 // CHECK3-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 3373 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] 3374 // CHECK3: omp.inner.for.end: 3375 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3376 // CHECK3: omp.loop.exit: 3377 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 3378 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3379 // CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 3380 // CHECK3-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3381 // CHECK3: .omp.final.then: 3382 // CHECK3-NEXT: store i64 400, ptr [[IT]], align 8 3383 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 3384 // CHECK3: .omp.final.done: 3385 // CHECK3-NEXT: ret void 3386 // 3387 // 3388 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 3389 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3390 // CHECK3-NEXT: entry: 3391 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3392 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3393 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3394 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3395 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3396 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3397 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3398 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3399 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3400 // CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 3401 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3402 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3403 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 3404 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 3405 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 3406 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3407 // CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 3408 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3409 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 3410 // CHECK3-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 3411 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 3412 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]]) 3413 // CHECK3-NEXT: ret void 3414 // 3415 // 3416 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined 3417 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3418 // CHECK3-NEXT: entry: 3419 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3420 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3421 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3422 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3423 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3424 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3425 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3426 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3427 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3428 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3429 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3430 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3431 // CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 3432 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3433 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3434 // CHECK3-NEXT: ret void 3435 // 3436 // 3437 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 3438 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3439 // CHECK3-NEXT: entry: 3440 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3441 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3442 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3443 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3444 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3445 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3446 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3447 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3448 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3449 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 3450 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 3451 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 3452 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3453 // CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 3454 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3455 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) 3456 // CHECK3-NEXT: ret void 3457 // 3458 // 3459 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined 3460 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3461 // CHECK3-NEXT: entry: 3462 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3463 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3464 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3465 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3466 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3467 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3468 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 3469 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3470 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3471 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3472 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3473 // CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 3474 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3475 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3476 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3477 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3478 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3479 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3480 // CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 3481 // CHECK3-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 3482 // CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 3483 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3484 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3485 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 3486 // CHECK3-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 3487 // CHECK3-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 3488 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 3489 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3490 // CHECK3: cond.true: 3491 // CHECK3-NEXT: br label [[COND_END:%.*]] 3492 // CHECK3: cond.false: 3493 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 3494 // CHECK3-NEXT: br label [[COND_END]] 3495 // CHECK3: cond.end: 3496 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 3497 // CHECK3-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 3498 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 3499 // CHECK3-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 3500 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3501 // CHECK3: omp.inner.for.cond: 3502 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42:![0-9]+]] 3503 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP42]] 3504 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 3505 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3506 // CHECK3: omp.inner.for.body: 3507 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42]] 3508 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 3509 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 3510 // CHECK3-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP42]] 3511 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]] 3512 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 3513 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]] 3514 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]] 3515 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 3516 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 3517 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 3518 // CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]] 3519 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 3520 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]] 3521 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 3522 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]] 3523 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3524 // CHECK3: omp.body.continue: 3525 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3526 // CHECK3: omp.inner.for.inc: 3527 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42]] 3528 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 3529 // CHECK3-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42]] 3530 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] 3531 // CHECK3: omp.inner.for.end: 3532 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3533 // CHECK3: omp.loop.exit: 3534 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 3535 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3536 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 3537 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3538 // CHECK3: .omp.final.then: 3539 // CHECK3-NEXT: store i64 11, ptr [[I]], align 8 3540 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 3541 // CHECK3: .omp.final.done: 3542 // CHECK3-NEXT: ret void 3543 // 3544 // 3545 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3546 // CHECK3-SAME: () #[[ATTR8:[0-9]+]] { 3547 // CHECK3-NEXT: entry: 3548 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 3549 // CHECK3-NEXT: ret void 3550 // 3551 // 3552 // CHECK5-LABEL: define {{[^@]+}}@_Z7get_valv 3553 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 3554 // CHECK5-NEXT: entry: 3555 // CHECK5-NEXT: ret i64 0 3556 // 3557 // 3558 // CHECK5-LABEL: define {{[^@]+}}@_Z3fooi 3559 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 3560 // CHECK5-NEXT: entry: 3561 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3562 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 3563 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 3564 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x float], align 4 3565 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 3566 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3567 // CHECK5-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 3568 // CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 3569 // CHECK5-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 3570 // CHECK5-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 3571 // CHECK5-NEXT: [[K:%.*]] = alloca i64, align 8 3572 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3573 // CHECK5-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 3574 // CHECK5-NEXT: [[LIN:%.*]] = alloca i32, align 4 3575 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3576 // CHECK5-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 3577 // CHECK5-NEXT: [[A_CASTED2:%.*]] = alloca i64, align 8 3578 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 3579 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 3580 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 3581 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3582 // CHECK5-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 3583 // CHECK5-NEXT: [[AA_CASTED4:%.*]] = alloca i64, align 8 3584 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 8 3585 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 8 3586 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 8 3587 // CHECK5-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 3588 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3589 // CHECK5-NEXT: [[A_CASTED11:%.*]] = alloca i64, align 8 3590 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 3591 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 8 3592 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 8 3593 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 8 3594 // CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 3595 // CHECK5-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 3596 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 3597 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 3598 // CHECK5-NEXT: store i32 0, ptr [[A]], align 4 3599 // CHECK5-NEXT: store i16 0, ptr [[AA]], align 2 3600 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 3601 // CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 3602 // CHECK5-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() 3603 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 3604 // CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 3605 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 3606 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 3607 // CHECK5-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 3608 // CHECK5-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 3609 // CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 3610 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 3611 // CHECK5-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, ptr @.omp_task_entry., i64 -1) 3612 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP7]], i32 0, i32 0 3613 // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP7]]) 3614 // CHECK5-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 3615 // CHECK5-NEXT: store i64 [[CALL]], ptr [[K]], align 8 3616 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4 3617 // CHECK5-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4 3618 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8 3619 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[K]], align 8 3620 // CHECK5-NEXT: store i64 [[TMP12]], ptr [[K_CASTED]], align 8 3621 // CHECK5-NEXT: [[TMP13:%.*]] = load i64, ptr [[K_CASTED]], align 8 3622 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR4:[0-9]+]] 3623 // CHECK5-NEXT: store i32 12, ptr [[LIN]], align 4 3624 // CHECK5-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2 3625 // CHECK5-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2 3626 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[AA_CASTED]], align 8 3627 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[LIN]], align 4 3628 // CHECK5-NEXT: store i32 [[TMP16]], ptr [[LIN_CASTED]], align 4 3629 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 3630 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[A]], align 4 3631 // CHECK5-NEXT: store i32 [[TMP18]], ptr [[A_CASTED2]], align 4 3632 // CHECK5-NEXT: [[TMP19:%.*]] = load i64, ptr [[A_CASTED2]], align 8 3633 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3634 // CHECK5-NEXT: store i64 [[TMP15]], ptr [[TMP20]], align 8 3635 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3636 // CHECK5-NEXT: store i64 [[TMP15]], ptr [[TMP21]], align 8 3637 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3638 // CHECK5-NEXT: store ptr null, ptr [[TMP22]], align 8 3639 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3640 // CHECK5-NEXT: store i64 [[TMP17]], ptr [[TMP23]], align 8 3641 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3642 // CHECK5-NEXT: store i64 [[TMP17]], ptr [[TMP24]], align 8 3643 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3644 // CHECK5-NEXT: store ptr null, ptr [[TMP25]], align 8 3645 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3646 // CHECK5-NEXT: store i64 [[TMP19]], ptr [[TMP26]], align 8 3647 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3648 // CHECK5-NEXT: store i64 [[TMP19]], ptr [[TMP27]], align 8 3649 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3650 // CHECK5-NEXT: store ptr null, ptr [[TMP28]], align 8 3651 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3652 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3653 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3654 // CHECK5-NEXT: store i32 2, ptr [[TMP31]], align 4 3655 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3656 // CHECK5-NEXT: store i32 3, ptr [[TMP32]], align 4 3657 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3658 // CHECK5-NEXT: store ptr [[TMP29]], ptr [[TMP33]], align 8 3659 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3660 // CHECK5-NEXT: store ptr [[TMP30]], ptr [[TMP34]], align 8 3661 // CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3662 // CHECK5-NEXT: store ptr @.offload_sizes, ptr [[TMP35]], align 8 3663 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3664 // CHECK5-NEXT: store ptr @.offload_maptypes, ptr [[TMP36]], align 8 3665 // CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3666 // CHECK5-NEXT: store ptr null, ptr [[TMP37]], align 8 3667 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3668 // CHECK5-NEXT: store ptr null, ptr [[TMP38]], align 8 3669 // CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3670 // CHECK5-NEXT: store i64 0, ptr [[TMP39]], align 8 3671 // CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 3672 // CHECK5-NEXT: store i64 0, ptr [[TMP40]], align 8 3673 // CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 3674 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP41]], align 4 3675 // CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 3676 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP42]], align 4 3677 // CHECK5-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 3678 // CHECK5-NEXT: store i32 0, ptr [[TMP43]], align 4 3679 // CHECK5-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, ptr [[KERNEL_ARGS]]) 3680 // CHECK5-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 3681 // CHECK5-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3682 // CHECK5: omp_offload.failed: 3683 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]]) #[[ATTR4]] 3684 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 3685 // CHECK5: omp_offload.cont: 3686 // CHECK5-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 3687 // CHECK5-NEXT: store i32 [[TMP46]], ptr [[A_CASTED3]], align 4 3688 // CHECK5-NEXT: [[TMP47:%.*]] = load i64, ptr [[A_CASTED3]], align 8 3689 // CHECK5-NEXT: [[TMP48:%.*]] = load i16, ptr [[AA]], align 2 3690 // CHECK5-NEXT: store i16 [[TMP48]], ptr [[AA_CASTED4]], align 2 3691 // CHECK5-NEXT: [[TMP49:%.*]] = load i64, ptr [[AA_CASTED4]], align 8 3692 // CHECK5-NEXT: [[TMP50:%.*]] = load i32, ptr [[N_ADDR]], align 4 3693 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP50]], 10 3694 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3695 // CHECK5: omp_if.then: 3696 // CHECK5-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 3697 // CHECK5-NEXT: store i64 [[TMP47]], ptr [[TMP51]], align 8 3698 // CHECK5-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 3699 // CHECK5-NEXT: store i64 [[TMP47]], ptr [[TMP52]], align 8 3700 // CHECK5-NEXT: [[TMP53:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 3701 // CHECK5-NEXT: store ptr null, ptr [[TMP53]], align 8 3702 // CHECK5-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 3703 // CHECK5-NEXT: store i64 [[TMP49]], ptr [[TMP54]], align 8 3704 // CHECK5-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 3705 // CHECK5-NEXT: store i64 [[TMP49]], ptr [[TMP55]], align 8 3706 // CHECK5-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 3707 // CHECK5-NEXT: store ptr null, ptr [[TMP56]], align 8 3708 // CHECK5-NEXT: [[TMP57:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 3709 // CHECK5-NEXT: [[TMP58:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 3710 // CHECK5-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0 3711 // CHECK5-NEXT: store i32 2, ptr [[TMP59]], align 4 3712 // CHECK5-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1 3713 // CHECK5-NEXT: store i32 2, ptr [[TMP60]], align 4 3714 // CHECK5-NEXT: [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2 3715 // CHECK5-NEXT: store ptr [[TMP57]], ptr [[TMP61]], align 8 3716 // CHECK5-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3 3717 // CHECK5-NEXT: store ptr [[TMP58]], ptr [[TMP62]], align 8 3718 // CHECK5-NEXT: [[TMP63:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4 3719 // CHECK5-NEXT: store ptr @.offload_sizes.1, ptr [[TMP63]], align 8 3720 // CHECK5-NEXT: [[TMP64:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5 3721 // CHECK5-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP64]], align 8 3722 // CHECK5-NEXT: [[TMP65:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6 3723 // CHECK5-NEXT: store ptr null, ptr [[TMP65]], align 8 3724 // CHECK5-NEXT: [[TMP66:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7 3725 // CHECK5-NEXT: store ptr null, ptr [[TMP66]], align 8 3726 // CHECK5-NEXT: [[TMP67:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8 3727 // CHECK5-NEXT: store i64 0, ptr [[TMP67]], align 8 3728 // CHECK5-NEXT: [[TMP68:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 9 3729 // CHECK5-NEXT: store i64 0, ptr [[TMP68]], align 8 3730 // CHECK5-NEXT: [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 10 3731 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP69]], align 4 3732 // CHECK5-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 11 3733 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP70]], align 4 3734 // CHECK5-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12 3735 // CHECK5-NEXT: store i32 0, ptr [[TMP71]], align 4 3736 // CHECK5-NEXT: [[TMP72:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, ptr [[KERNEL_ARGS8]]) 3737 // CHECK5-NEXT: [[TMP73:%.*]] = icmp ne i32 [[TMP72]], 0 3738 // CHECK5-NEXT: br i1 [[TMP73]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 3739 // CHECK5: omp_offload.failed9: 3740 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR4]] 3741 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT10]] 3742 // CHECK5: omp_offload.cont10: 3743 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 3744 // CHECK5: omp_if.else: 3745 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR4]] 3746 // CHECK5-NEXT: br label [[OMP_IF_END]] 3747 // CHECK5: omp_if.end: 3748 // CHECK5-NEXT: [[TMP74:%.*]] = load i32, ptr [[A]], align 4 3749 // CHECK5-NEXT: store i32 [[TMP74]], ptr [[DOTCAPTURE_EXPR_]], align 4 3750 // CHECK5-NEXT: [[TMP75:%.*]] = load i32, ptr [[A]], align 4 3751 // CHECK5-NEXT: store i32 [[TMP75]], ptr [[A_CASTED11]], align 4 3752 // CHECK5-NEXT: [[TMP76:%.*]] = load i64, ptr [[A_CASTED11]], align 8 3753 // CHECK5-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 3754 // CHECK5-NEXT: store i32 [[TMP77]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 3755 // CHECK5-NEXT: [[TMP78:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 3756 // CHECK5-NEXT: [[TMP79:%.*]] = load i32, ptr [[N_ADDR]], align 4 3757 // CHECK5-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP79]], 20 3758 // CHECK5-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]] 3759 // CHECK5: omp_if.then13: 3760 // CHECK5-NEXT: [[TMP80:%.*]] = mul nuw i64 [[TMP2]], 4 3761 // CHECK5-NEXT: [[TMP81:%.*]] = mul nuw i64 5, [[TMP5]] 3762 // CHECK5-NEXT: [[TMP82:%.*]] = mul nuw i64 [[TMP81]], 8 3763 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.3, i64 80, i1 false) 3764 // CHECK5-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 3765 // CHECK5-NEXT: store i64 [[TMP76]], ptr [[TMP83]], align 8 3766 // CHECK5-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 3767 // CHECK5-NEXT: store i64 [[TMP76]], ptr [[TMP84]], align 8 3768 // CHECK5-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0 3769 // CHECK5-NEXT: store ptr null, ptr [[TMP85]], align 8 3770 // CHECK5-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 3771 // CHECK5-NEXT: store ptr [[B]], ptr [[TMP86]], align 8 3772 // CHECK5-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 3773 // CHECK5-NEXT: store ptr [[B]], ptr [[TMP87]], align 8 3774 // CHECK5-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1 3775 // CHECK5-NEXT: store ptr null, ptr [[TMP88]], align 8 3776 // CHECK5-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 3777 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP89]], align 8 3778 // CHECK5-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 3779 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP90]], align 8 3780 // CHECK5-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 2 3781 // CHECK5-NEXT: store ptr null, ptr [[TMP91]], align 8 3782 // CHECK5-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 3783 // CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP92]], align 8 3784 // CHECK5-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 3785 // CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP93]], align 8 3786 // CHECK5-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 3787 // CHECK5-NEXT: store i64 [[TMP80]], ptr [[TMP94]], align 8 3788 // CHECK5-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 3 3789 // CHECK5-NEXT: store ptr null, ptr [[TMP95]], align 8 3790 // CHECK5-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 3791 // CHECK5-NEXT: store ptr [[C]], ptr [[TMP96]], align 8 3792 // CHECK5-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 3793 // CHECK5-NEXT: store ptr [[C]], ptr [[TMP97]], align 8 3794 // CHECK5-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 4 3795 // CHECK5-NEXT: store ptr null, ptr [[TMP98]], align 8 3796 // CHECK5-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 3797 // CHECK5-NEXT: store i64 5, ptr [[TMP99]], align 8 3798 // CHECK5-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 3799 // CHECK5-NEXT: store i64 5, ptr [[TMP100]], align 8 3800 // CHECK5-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 5 3801 // CHECK5-NEXT: store ptr null, ptr [[TMP101]], align 8 3802 // CHECK5-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 3803 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP102]], align 8 3804 // CHECK5-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 3805 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP103]], align 8 3806 // CHECK5-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 6 3807 // CHECK5-NEXT: store ptr null, ptr [[TMP104]], align 8 3808 // CHECK5-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 3809 // CHECK5-NEXT: store ptr [[VLA1]], ptr [[TMP105]], align 8 3810 // CHECK5-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 3811 // CHECK5-NEXT: store ptr [[VLA1]], ptr [[TMP106]], align 8 3812 // CHECK5-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 3813 // CHECK5-NEXT: store i64 [[TMP82]], ptr [[TMP107]], align 8 3814 // CHECK5-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 7 3815 // CHECK5-NEXT: store ptr null, ptr [[TMP108]], align 8 3816 // CHECK5-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 3817 // CHECK5-NEXT: store ptr [[D]], ptr [[TMP109]], align 8 3818 // CHECK5-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 3819 // CHECK5-NEXT: store ptr [[D]], ptr [[TMP110]], align 8 3820 // CHECK5-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 8 3821 // CHECK5-NEXT: store ptr null, ptr [[TMP111]], align 8 3822 // CHECK5-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 3823 // CHECK5-NEXT: store i64 [[TMP78]], ptr [[TMP112]], align 8 3824 // CHECK5-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 3825 // CHECK5-NEXT: store i64 [[TMP78]], ptr [[TMP113]], align 8 3826 // CHECK5-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 9 3827 // CHECK5-NEXT: store ptr null, ptr [[TMP114]], align 8 3828 // CHECK5-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 3829 // CHECK5-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 3830 // CHECK5-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3831 // CHECK5-NEXT: [[TMP118:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0 3832 // CHECK5-NEXT: store i32 2, ptr [[TMP118]], align 4 3833 // CHECK5-NEXT: [[TMP119:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1 3834 // CHECK5-NEXT: store i32 10, ptr [[TMP119]], align 4 3835 // CHECK5-NEXT: [[TMP120:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2 3836 // CHECK5-NEXT: store ptr [[TMP115]], ptr [[TMP120]], align 8 3837 // CHECK5-NEXT: [[TMP121:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3 3838 // CHECK5-NEXT: store ptr [[TMP116]], ptr [[TMP121]], align 8 3839 // CHECK5-NEXT: [[TMP122:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4 3840 // CHECK5-NEXT: store ptr [[TMP117]], ptr [[TMP122]], align 8 3841 // CHECK5-NEXT: [[TMP123:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5 3842 // CHECK5-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP123]], align 8 3843 // CHECK5-NEXT: [[TMP124:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6 3844 // CHECK5-NEXT: store ptr null, ptr [[TMP124]], align 8 3845 // CHECK5-NEXT: [[TMP125:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7 3846 // CHECK5-NEXT: store ptr null, ptr [[TMP125]], align 8 3847 // CHECK5-NEXT: [[TMP126:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8 3848 // CHECK5-NEXT: store i64 0, ptr [[TMP126]], align 8 3849 // CHECK5-NEXT: [[TMP127:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 9 3850 // CHECK5-NEXT: store i64 0, ptr [[TMP127]], align 8 3851 // CHECK5-NEXT: [[TMP128:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 10 3852 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP128]], align 4 3853 // CHECK5-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 11 3854 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP129]], align 4 3855 // CHECK5-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12 3856 // CHECK5-NEXT: store i32 0, ptr [[TMP130]], align 4 3857 // CHECK5-NEXT: [[TMP131:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, ptr [[KERNEL_ARGS17]]) 3858 // CHECK5-NEXT: [[TMP132:%.*]] = icmp ne i32 [[TMP131]], 0 3859 // CHECK5-NEXT: br i1 [[TMP132]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] 3860 // CHECK5: omp_offload.failed18: 3861 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR4]] 3862 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT19]] 3863 // CHECK5: omp_offload.cont19: 3864 // CHECK5-NEXT: br label [[OMP_IF_END21:%.*]] 3865 // CHECK5: omp_if.else20: 3866 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR4]] 3867 // CHECK5-NEXT: br label [[OMP_IF_END21]] 3868 // CHECK5: omp_if.end21: 3869 // CHECK5-NEXT: [[TMP133:%.*]] = load i32, ptr [[A]], align 4 3870 // CHECK5-NEXT: [[TMP134:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 3871 // CHECK5-NEXT: call void @llvm.stackrestore(ptr [[TMP134]]) 3872 // CHECK5-NEXT: ret i32 [[TMP133]] 3873 // 3874 // 3875 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 3876 // CHECK5-SAME: () #[[ATTR2:[0-9]+]] { 3877 // CHECK5-NEXT: entry: 3878 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) 3879 // CHECK5-NEXT: ret void 3880 // 3881 // 3882 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined 3883 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 3884 // CHECK5-NEXT: entry: 3885 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3886 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3887 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3888 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 3889 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3890 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3891 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3892 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3893 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3894 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3895 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3896 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3897 // CHECK5-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 3898 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3899 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3900 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3901 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 3902 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3903 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3904 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 3905 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3906 // CHECK5: cond.true: 3907 // CHECK5-NEXT: br label [[COND_END:%.*]] 3908 // CHECK5: cond.false: 3909 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3910 // CHECK5-NEXT: br label [[COND_END]] 3911 // CHECK5: cond.end: 3912 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3913 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3914 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3915 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 3916 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3917 // CHECK5: omp.inner.for.cond: 3918 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 3919 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 3920 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3921 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3922 // CHECK5: omp.inner.for.body: 3923 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 3924 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 3925 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 3926 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 3927 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3928 // CHECK5: omp.body.continue: 3929 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3930 // CHECK5: omp.inner.for.inc: 3931 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 3932 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 3933 // CHECK5-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 3934 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 3935 // CHECK5: omp.inner.for.end: 3936 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3937 // CHECK5: omp.loop.exit: 3938 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 3939 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3940 // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 3941 // CHECK5-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3942 // CHECK5: .omp.final.then: 3943 // CHECK5-NEXT: store i32 33, ptr [[I]], align 4 3944 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 3945 // CHECK5: .omp.final.done: 3946 // CHECK5-NEXT: ret void 3947 // 3948 // 3949 // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry. 3950 // CHECK5-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 3951 // CHECK5-NEXT: entry: 3952 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 3953 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 3954 // CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 3955 // CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 3956 // CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 3957 // CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 3958 // CHECK5-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3959 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 3960 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 3961 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 3962 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 3963 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 3964 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 3965 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 3966 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 3967 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 3968 // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 3969 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 3970 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 3971 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 3972 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 3973 // CHECK5-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 3974 // CHECK5-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !25 3975 // CHECK5-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25 3976 // CHECK5-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25 3977 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !25 3978 // CHECK5-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !25 3979 // CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !25 3980 // CHECK5-NEXT: store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !25 3981 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 3982 // CHECK5-NEXT: store i32 0, ptr [[TMP9]], align 4, !noalias !25 3983 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 3984 // CHECK5-NEXT: store ptr null, ptr [[TMP10]], align 8, !noalias !25 3985 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 3986 // CHECK5-NEXT: store ptr null, ptr [[TMP11]], align 8, !noalias !25 3987 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 3988 // CHECK5-NEXT: store ptr null, ptr [[TMP12]], align 8, !noalias !25 3989 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 3990 // CHECK5-NEXT: store ptr null, ptr [[TMP13]], align 8, !noalias !25 3991 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 3992 // CHECK5-NEXT: store ptr null, ptr [[TMP14]], align 8, !noalias !25 3993 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 3994 // CHECK5-NEXT: store ptr null, ptr [[TMP15]], align 8, !noalias !25 3995 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 3996 // CHECK5-NEXT: store i64 0, ptr [[TMP16]], align 8, !noalias !25 3997 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9 3998 // CHECK5-NEXT: store i64 1, ptr [[TMP17]], align 8, !noalias !25 3999 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10 4000 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4, !noalias !25 4001 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11 4002 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4, !noalias !25 4003 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12 4004 // CHECK5-NEXT: store i32 0, ptr [[TMP20]], align 4, !noalias !25 4005 // CHECK5-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, ptr [[KERNEL_ARGS_I]]) 4006 // CHECK5-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 4007 // CHECK5-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] 4008 // CHECK5: omp_offload.failed.i: 4009 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] 4010 // CHECK5-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] 4011 // CHECK5: .omp_outlined..exit: 4012 // CHECK5-NEXT: ret i32 0 4013 // 4014 // 4015 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 4016 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 4017 // CHECK5-NEXT: entry: 4018 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4019 // CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 4020 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4021 // CHECK5-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 4022 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4023 // CHECK5-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8 4024 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4025 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 4026 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 4027 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[K_ADDR]], align 8 4028 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[K_CASTED]], align 8 4029 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[K_CASTED]], align 8 4030 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) 4031 // CHECK5-NEXT: ret void 4032 // 4033 // 4034 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined 4035 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 4036 // CHECK5-NEXT: entry: 4037 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4038 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4039 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4040 // CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 4041 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4042 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 4043 // CHECK5-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 4044 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4045 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4046 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4047 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4048 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 4049 // CHECK5-NEXT: [[K1:%.*]] = alloca i64, align 8 4050 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4051 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4052 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4053 // CHECK5-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8 4054 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[K_ADDR]], align 8 4055 // CHECK5-NEXT: store i64 [[TMP0]], ptr [[DOTLINEAR_START]], align 8 4056 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4057 // CHECK5-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 4 4058 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4059 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4060 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4061 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 4062 // CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 4063 // CHECK5-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 4064 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4065 // CHECK5: omp.dispatch.cond: 4066 // CHECK5-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP2]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]) 4067 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 4068 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4069 // CHECK5: omp.dispatch.body: 4070 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4071 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 4072 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4073 // CHECK5: omp.inner.for.cond: 4074 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] 4075 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] 4076 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4077 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4078 // CHECK5: omp.inner.for.body: 4079 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 4080 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4081 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 4082 // CHECK5-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] 4083 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP26]] 4084 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 4085 // CHECK5-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 4086 // CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 4087 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV]] 4088 // CHECK5-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP26]] 4089 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] 4090 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 4091 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] 4092 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4093 // CHECK5: omp.body.continue: 4094 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4095 // CHECK5: omp.inner.for.inc: 4096 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 4097 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 4098 // CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 4099 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] 4100 // CHECK5: omp.inner.for.end: 4101 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4102 // CHECK5: omp.dispatch.inc: 4103 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] 4104 // CHECK5: omp.dispatch.end: 4105 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4106 // CHECK5-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 4107 // CHECK5-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4108 // CHECK5: .omp.final.then: 4109 // CHECK5-NEXT: store i32 1, ptr [[I]], align 4 4110 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4111 // CHECK5: .omp.final.done: 4112 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4113 // CHECK5-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 4114 // CHECK5-NEXT: br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 4115 // CHECK5: .omp.linear.pu: 4116 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[K1]], align 8 4117 // CHECK5-NEXT: store i64 [[TMP16]], ptr [[K_ADDR]], align 8 4118 // CHECK5-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 4119 // CHECK5: .omp.linear.pu.done: 4120 // CHECK5-NEXT: ret void 4121 // 4122 // 4123 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 4124 // CHECK5-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 4125 // CHECK5-NEXT: entry: 4126 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4127 // CHECK5-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 4128 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4129 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4130 // CHECK5-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 4131 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4132 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4133 // CHECK5-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 4134 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4135 // CHECK5-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4136 // CHECK5-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 4137 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 4138 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 4139 // CHECK5-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 4140 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 4141 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 4142 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 4143 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8 4144 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 4145 // CHECK5-NEXT: ret void 4146 // 4147 // 4148 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined 4149 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 4150 // CHECK5-NEXT: entry: 4151 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4152 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4153 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4154 // CHECK5-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 4155 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4156 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4157 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 4158 // CHECK5-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 4159 // CHECK5-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 4160 // CHECK5-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 4161 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4162 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4163 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4164 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4165 // CHECK5-NEXT: [[IT:%.*]] = alloca i64, align 8 4166 // CHECK5-NEXT: [[LIN2:%.*]] = alloca i32, align 4 4167 // CHECK5-NEXT: [[A3:%.*]] = alloca i32, align 4 4168 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4169 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4170 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4171 // CHECK5-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 4172 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4173 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 4174 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 4175 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 4176 // CHECK5-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 4177 // CHECK5-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 4178 // CHECK5-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 4179 // CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 4180 // CHECK5-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 4181 // CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 4182 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4183 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4184 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 4185 // CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]]) 4186 // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 4187 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 4188 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 4189 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4190 // CHECK5: cond.true: 4191 // CHECK5-NEXT: br label [[COND_END:%.*]] 4192 // CHECK5: cond.false: 4193 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 4194 // CHECK5-NEXT: br label [[COND_END]] 4195 // CHECK5: cond.end: 4196 // CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 4197 // CHECK5-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 4198 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 4199 // CHECK5-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 4200 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4201 // CHECK5: omp.inner.for.cond: 4202 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29:![0-9]+]] 4203 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP29]] 4204 // CHECK5-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 4205 // CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4206 // CHECK5: omp.inner.for.body: 4207 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4208 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 4209 // CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 4210 // CHECK5-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP29]] 4211 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP29]] 4212 // CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 4213 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4214 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]] 4215 // CHECK5-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 4216 // CHECK5-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 4217 // CHECK5-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 4218 // CHECK5-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP29]] 4219 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP29]] 4220 // CHECK5-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 4221 // CHECK5-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4222 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]] 4223 // CHECK5-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 4224 // CHECK5-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 4225 // CHECK5-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 4226 // CHECK5-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP29]] 4227 // CHECK5-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] 4228 // CHECK5-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 4229 // CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 4230 // CHECK5-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 4231 // CHECK5-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] 4232 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4233 // CHECK5: omp.body.continue: 4234 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4235 // CHECK5: omp.inner.for.inc: 4236 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4237 // CHECK5-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 4238 // CHECK5-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4239 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] 4240 // CHECK5: omp.inner.for.end: 4241 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4242 // CHECK5: omp.loop.exit: 4243 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 4244 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4245 // CHECK5-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 4246 // CHECK5-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4247 // CHECK5: .omp.final.then: 4248 // CHECK5-NEXT: store i64 400, ptr [[IT]], align 8 4249 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4250 // CHECK5: .omp.final.done: 4251 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4252 // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 4253 // CHECK5-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 4254 // CHECK5: .omp.linear.pu: 4255 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 4256 // CHECK5-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 4257 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 4258 // CHECK5-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 4259 // CHECK5-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 4260 // CHECK5: .omp.linear.pu.done: 4261 // CHECK5-NEXT: ret void 4262 // 4263 // 4264 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 4265 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 4266 // CHECK5-NEXT: entry: 4267 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4268 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4269 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4270 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4271 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4272 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4273 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4274 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 4275 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 4276 // CHECK5-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4277 // CHECK5-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 4278 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 4279 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) 4280 // CHECK5-NEXT: ret void 4281 // 4282 // 4283 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined 4284 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 4285 // CHECK5-NEXT: entry: 4286 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4287 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4288 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4289 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4290 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4291 // CHECK5-NEXT: [[TMP:%.*]] = alloca i16, align 2 4292 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4293 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4294 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4295 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4296 // CHECK5-NEXT: [[IT:%.*]] = alloca i16, align 2 4297 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4298 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4299 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4300 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4301 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4302 // CHECK5-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 4303 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4304 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4305 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4306 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 4307 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 4308 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4309 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 4310 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4311 // CHECK5: cond.true: 4312 // CHECK5-NEXT: br label [[COND_END:%.*]] 4313 // CHECK5: cond.false: 4314 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4315 // CHECK5-NEXT: br label [[COND_END]] 4316 // CHECK5: cond.end: 4317 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4318 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4319 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4320 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 4321 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4322 // CHECK5: omp.inner.for.cond: 4323 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]] 4324 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]] 4325 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4326 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4327 // CHECK5: omp.inner.for.body: 4328 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 4329 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 4330 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 4331 // CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 4332 // CHECK5-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP32]] 4333 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] 4334 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 4335 // CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] 4336 // CHECK5-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] 4337 // CHECK5-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 4338 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 4339 // CHECK5-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 4340 // CHECK5-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] 4341 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4342 // CHECK5: omp.body.continue: 4343 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4344 // CHECK5: omp.inner.for.inc: 4345 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 4346 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 4347 // CHECK5-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 4348 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] 4349 // CHECK5: omp.inner.for.end: 4350 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4351 // CHECK5: omp.loop.exit: 4352 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 4353 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4354 // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 4355 // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4356 // CHECK5: .omp.final.then: 4357 // CHECK5-NEXT: store i16 22, ptr [[IT]], align 2 4358 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4359 // CHECK5: .omp.final.done: 4360 // CHECK5-NEXT: ret void 4361 // 4362 // 4363 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 4364 // CHECK5-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 4365 // CHECK5-NEXT: entry: 4366 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4367 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4368 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4369 // CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 4370 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4371 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4372 // CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4373 // CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 4374 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 4375 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4376 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4377 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4378 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4379 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4380 // CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4381 // CHECK5-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 4382 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4383 // CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 4384 // CHECK5-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 4385 // CHECK5-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 4386 // CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 4387 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 4388 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 4389 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4390 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 4391 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4392 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 4393 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 4394 // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 4395 // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 4396 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 4397 // CHECK5-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 4398 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 4399 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 4400 // CHECK5-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 4401 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 4402 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]]) 4403 // CHECK5-NEXT: ret void 4404 // 4405 // 4406 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined 4407 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 4408 // CHECK5-NEXT: entry: 4409 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4410 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4411 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4412 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4413 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4414 // CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 4415 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4416 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4417 // CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4418 // CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 4419 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 4420 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4421 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4422 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1 4423 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4424 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4425 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4426 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4427 // CHECK5-NEXT: [[IT:%.*]] = alloca i8, align 1 4428 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4429 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4430 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4431 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4432 // CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4433 // CHECK5-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 4434 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4435 // CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 4436 // CHECK5-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 4437 // CHECK5-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 4438 // CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 4439 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 4440 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 4441 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4442 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 4443 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4444 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 4445 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 4446 // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 4447 // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 4448 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4449 // CHECK5-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 4450 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4451 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4452 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 4453 // CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4454 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 4455 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 4456 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4457 // CHECK5: omp.dispatch.cond: 4458 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4459 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 4460 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4461 // CHECK5: cond.true: 4462 // CHECK5-NEXT: br label [[COND_END:%.*]] 4463 // CHECK5: cond.false: 4464 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4465 // CHECK5-NEXT: br label [[COND_END]] 4466 // CHECK5: cond.end: 4467 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 4468 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4469 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4470 // CHECK5-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 4471 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4472 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4473 // CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 4474 // CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4475 // CHECK5: omp.dispatch.body: 4476 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4477 // CHECK5: omp.inner.for.cond: 4478 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]] 4479 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]] 4480 // CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 4481 // CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4482 // CHECK5: omp.inner.for.body: 4483 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 4484 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 4485 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 4486 // CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 4487 // CHECK5-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP35]] 4488 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] 4489 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 4490 // CHECK5-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] 4491 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 4492 // CHECK5-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] 4493 // CHECK5-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 4494 // CHECK5-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 4495 // CHECK5-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 4496 // CHECK5-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] 4497 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 4498 // CHECK5-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP35]] 4499 // CHECK5-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 4500 // CHECK5-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 4501 // CHECK5-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 4502 // CHECK5-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP35]] 4503 // CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 4504 // CHECK5-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 4505 // CHECK5-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]] 4506 // CHECK5-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 4507 // CHECK5-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]] 4508 // CHECK5-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 4509 // CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]] 4510 // CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3 4511 // CHECK5-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP35]] 4512 // CHECK5-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 4513 // CHECK5-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP35]] 4514 // CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 4515 // CHECK5-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]] 4516 // CHECK5-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 4517 // CHECK5-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]] 4518 // CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 4519 // CHECK5-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]] 4520 // CHECK5-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 4521 // CHECK5-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 4522 // CHECK5-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 4523 // CHECK5-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]] 4524 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4525 // CHECK5: omp.body.continue: 4526 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4527 // CHECK5: omp.inner.for.inc: 4528 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 4529 // CHECK5-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 4530 // CHECK5-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 4531 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] 4532 // CHECK5: omp.inner.for.end: 4533 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4534 // CHECK5: omp.dispatch.inc: 4535 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4536 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 4537 // CHECK5-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 4538 // CHECK5-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 4539 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4540 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 4541 // CHECK5-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 4542 // CHECK5-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 4543 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] 4544 // CHECK5: omp.dispatch.end: 4545 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 4546 // CHECK5-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4547 // CHECK5-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 4548 // CHECK5-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4549 // CHECK5: .omp.final.then: 4550 // CHECK5-NEXT: store i8 96, ptr [[IT]], align 1 4551 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4552 // CHECK5: .omp.final.done: 4553 // CHECK5-NEXT: ret void 4554 // 4555 // 4556 // CHECK5-LABEL: define {{[^@]+}}@_Z3bari 4557 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 4558 // CHECK5-NEXT: entry: 4559 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4560 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 4561 // CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 4562 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 4563 // CHECK5-NEXT: store i32 0, ptr [[A]], align 4 4564 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 4565 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 4566 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 4567 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 4568 // CHECK5-NEXT: store i32 [[ADD]], ptr [[A]], align 4 4569 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 4570 // CHECK5-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 4571 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 4572 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 4573 // CHECK5-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 4574 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 4575 // CHECK5-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 4576 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 4577 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 4578 // CHECK5-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 4579 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 4580 // CHECK5-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 4581 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 4582 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 4583 // CHECK5-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 4584 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 4585 // CHECK5-NEXT: ret i32 [[TMP8]] 4586 // 4587 // 4588 // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 4589 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 4590 // CHECK5-NEXT: entry: 4591 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4592 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4593 // CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 4594 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 4595 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4596 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4597 // CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4598 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4599 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x ptr], align 8 4600 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x ptr], align 8 4601 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x ptr], align 8 4602 // CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 8 4603 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 4604 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4605 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 4606 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4607 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 4608 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4609 // CHECK5-NEXT: store i32 [[ADD]], ptr [[B]], align 4 4610 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 4611 // CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 4612 // CHECK5-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() 4613 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 4614 // CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 4615 // CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 4616 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 4617 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 4618 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 4619 // CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 4620 // CHECK5-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 4621 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[B]], align 4 4622 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[B_CASTED]], align 4 4623 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[B_CASTED]], align 8 4624 // CHECK5-NEXT: [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4625 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1 4626 // CHECK5-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8 4627 // CHECK5-NEXT: store i8 [[FROMBOOL2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 4628 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 4629 // CHECK5-NEXT: [[TMP10:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4630 // CHECK5-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP10]] to i1 4631 // CHECK5-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4632 // CHECK5: omp_if.then: 4633 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 4634 // CHECK5-NEXT: [[TMP11:%.*]] = mul nuw i64 2, [[TMP2]] 4635 // CHECK5-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 2 4636 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 48, i1 false) 4637 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4638 // CHECK5-NEXT: store ptr [[THIS1]], ptr [[TMP13]], align 8 4639 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4640 // CHECK5-NEXT: store ptr [[A]], ptr [[TMP14]], align 8 4641 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4642 // CHECK5-NEXT: store ptr null, ptr [[TMP15]], align 8 4643 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4644 // CHECK5-NEXT: store i64 [[TMP7]], ptr [[TMP16]], align 8 4645 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4646 // CHECK5-NEXT: store i64 [[TMP7]], ptr [[TMP17]], align 8 4647 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4648 // CHECK5-NEXT: store ptr null, ptr [[TMP18]], align 8 4649 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4650 // CHECK5-NEXT: store i64 2, ptr [[TMP19]], align 8 4651 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4652 // CHECK5-NEXT: store i64 2, ptr [[TMP20]], align 8 4653 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4654 // CHECK5-NEXT: store ptr null, ptr [[TMP21]], align 8 4655 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4656 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP22]], align 8 4657 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4658 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP23]], align 8 4659 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 4660 // CHECK5-NEXT: store ptr null, ptr [[TMP24]], align 8 4661 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 4662 // CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP25]], align 8 4663 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 4664 // CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP26]], align 8 4665 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 4666 // CHECK5-NEXT: store i64 [[TMP12]], ptr [[TMP27]], align 8 4667 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 4668 // CHECK5-NEXT: store ptr null, ptr [[TMP28]], align 8 4669 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 4670 // CHECK5-NEXT: store i64 [[TMP9]], ptr [[TMP29]], align 8 4671 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5 4672 // CHECK5-NEXT: store i64 [[TMP9]], ptr [[TMP30]], align 8 4673 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 4674 // CHECK5-NEXT: store ptr null, ptr [[TMP31]], align 8 4675 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4676 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4677 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4678 // CHECK5-NEXT: [[TMP35:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4679 // CHECK5-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP35]] to i1 4680 // CHECK5-NEXT: [[TMP36:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 4681 // CHECK5-NEXT: [[TMP37:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP36]], 0 4682 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 4683 // CHECK5-NEXT: store i32 2, ptr [[TMP38]], align 4 4684 // CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 4685 // CHECK5-NEXT: store i32 6, ptr [[TMP39]], align 4 4686 // CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 4687 // CHECK5-NEXT: store ptr [[TMP32]], ptr [[TMP40]], align 8 4688 // CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 4689 // CHECK5-NEXT: store ptr [[TMP33]], ptr [[TMP41]], align 8 4690 // CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 4691 // CHECK5-NEXT: store ptr [[TMP34]], ptr [[TMP42]], align 8 4692 // CHECK5-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 4693 // CHECK5-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP43]], align 8 4694 // CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 4695 // CHECK5-NEXT: store ptr null, ptr [[TMP44]], align 8 4696 // CHECK5-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 4697 // CHECK5-NEXT: store ptr null, ptr [[TMP45]], align 8 4698 // CHECK5-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 4699 // CHECK5-NEXT: store i64 0, ptr [[TMP46]], align 8 4700 // CHECK5-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 4701 // CHECK5-NEXT: store i64 0, ptr [[TMP47]], align 8 4702 // CHECK5-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 4703 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP48]], align 4 4704 // CHECK5-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 4705 // CHECK5-NEXT: store [3 x i32] [[TMP37]], ptr [[TMP49]], align 4 4706 // CHECK5-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 4707 // CHECK5-NEXT: store i32 0, ptr [[TMP50]], align 4 4708 // CHECK5-NEXT: [[TMP51:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 [[TMP36]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, ptr [[KERNEL_ARGS]]) 4709 // CHECK5-NEXT: [[TMP52:%.*]] = icmp ne i32 [[TMP51]], 0 4710 // CHECK5-NEXT: br i1 [[TMP52]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4711 // CHECK5: omp_offload.failed: 4712 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR4]] 4713 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 4714 // CHECK5: omp_offload.cont: 4715 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4716 // CHECK5: omp_if.else: 4717 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR4]] 4718 // CHECK5-NEXT: br label [[OMP_IF_END]] 4719 // CHECK5: omp_if.end: 4720 // CHECK5-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP2]] 4721 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP53]] 4722 // CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 4723 // CHECK5-NEXT: [[TMP54:%.*]] = load i16, ptr [[ARRAYIDX5]], align 2 4724 // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP54]] to i32 4725 // CHECK5-NEXT: [[TMP55:%.*]] = load i32, ptr [[B]], align 4 4726 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV]], [[TMP55]] 4727 // CHECK5-NEXT: [[TMP56:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 4728 // CHECK5-NEXT: call void @llvm.stackrestore(ptr [[TMP56]]) 4729 // CHECK5-NEXT: ret i32 [[ADD6]] 4730 // 4731 // 4732 // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici 4733 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 4734 // CHECK5-NEXT: entry: 4735 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4736 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 4737 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 4738 // CHECK5-NEXT: [[AAA:%.*]] = alloca i8, align 1 4739 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4740 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4741 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4742 // CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 4743 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 4744 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 4745 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 4746 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 4747 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 4748 // CHECK5-NEXT: store i32 0, ptr [[A]], align 4 4749 // CHECK5-NEXT: store i16 0, ptr [[AA]], align 2 4750 // CHECK5-NEXT: store i8 0, ptr [[AAA]], align 1 4751 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 4752 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 4753 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 4754 // CHECK5-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 4755 // CHECK5-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 4756 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 4757 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1 4758 // CHECK5-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1 4759 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 4760 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 4761 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 4762 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4763 // CHECK5: omp_if.then: 4764 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4765 // CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP7]], align 8 4766 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4767 // CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP8]], align 8 4768 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4769 // CHECK5-NEXT: store ptr null, ptr [[TMP9]], align 8 4770 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4771 // CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP10]], align 8 4772 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4773 // CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP11]], align 8 4774 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4775 // CHECK5-NEXT: store ptr null, ptr [[TMP12]], align 8 4776 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4777 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP13]], align 8 4778 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4779 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP14]], align 8 4780 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4781 // CHECK5-NEXT: store ptr null, ptr [[TMP15]], align 8 4782 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4783 // CHECK5-NEXT: store ptr [[B]], ptr [[TMP16]], align 8 4784 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4785 // CHECK5-NEXT: store ptr [[B]], ptr [[TMP17]], align 8 4786 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 4787 // CHECK5-NEXT: store ptr null, ptr [[TMP18]], align 8 4788 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4789 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4790 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 4791 // CHECK5-NEXT: store i32 2, ptr [[TMP21]], align 4 4792 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 4793 // CHECK5-NEXT: store i32 4, ptr [[TMP22]], align 4 4794 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 4795 // CHECK5-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8 4796 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 4797 // CHECK5-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8 4798 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 4799 // CHECK5-NEXT: store ptr @.offload_sizes.7, ptr [[TMP25]], align 8 4800 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 4801 // CHECK5-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP26]], align 8 4802 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 4803 // CHECK5-NEXT: store ptr null, ptr [[TMP27]], align 8 4804 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 4805 // CHECK5-NEXT: store ptr null, ptr [[TMP28]], align 8 4806 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 4807 // CHECK5-NEXT: store i64 0, ptr [[TMP29]], align 8 4808 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 4809 // CHECK5-NEXT: store i64 0, ptr [[TMP30]], align 8 4810 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 4811 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4 4812 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 4813 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 4814 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 4815 // CHECK5-NEXT: store i32 0, ptr [[TMP33]], align 4 4816 // CHECK5-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, ptr [[KERNEL_ARGS]]) 4817 // CHECK5-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 4818 // CHECK5-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4819 // CHECK5: omp_offload.failed: 4820 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]] 4821 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 4822 // CHECK5: omp_offload.cont: 4823 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4824 // CHECK5: omp_if.else: 4825 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]] 4826 // CHECK5-NEXT: br label [[OMP_IF_END]] 4827 // CHECK5: omp_if.end: 4828 // CHECK5-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 4829 // CHECK5-NEXT: ret i32 [[TMP36]] 4830 // 4831 // 4832 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 4833 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 4834 // CHECK5-NEXT: entry: 4835 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4836 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 4837 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 4838 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4839 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4840 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4841 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 4842 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 4843 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 4844 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 4845 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 4846 // CHECK5-NEXT: store i32 0, ptr [[A]], align 4 4847 // CHECK5-NEXT: store i16 0, ptr [[AA]], align 2 4848 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 4849 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 4850 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 4851 // CHECK5-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 4852 // CHECK5-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 4853 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 4854 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 4855 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 4856 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4857 // CHECK5: omp_if.then: 4858 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4859 // CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 4860 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4861 // CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 8 4862 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4863 // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 4864 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4865 // CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 8 4866 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4867 // CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP9]], align 8 4868 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4869 // CHECK5-NEXT: store ptr null, ptr [[TMP10]], align 8 4870 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4871 // CHECK5-NEXT: store ptr [[B]], ptr [[TMP11]], align 8 4872 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4873 // CHECK5-NEXT: store ptr [[B]], ptr [[TMP12]], align 8 4874 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4875 // CHECK5-NEXT: store ptr null, ptr [[TMP13]], align 8 4876 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4877 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4878 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 4879 // CHECK5-NEXT: store i32 2, ptr [[TMP16]], align 4 4880 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 4881 // CHECK5-NEXT: store i32 3, ptr [[TMP17]], align 4 4882 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 4883 // CHECK5-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8 4884 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 4885 // CHECK5-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8 4886 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 4887 // CHECK5-NEXT: store ptr @.offload_sizes.9, ptr [[TMP20]], align 8 4888 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 4889 // CHECK5-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP21]], align 8 4890 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 4891 // CHECK5-NEXT: store ptr null, ptr [[TMP22]], align 8 4892 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 4893 // CHECK5-NEXT: store ptr null, ptr [[TMP23]], align 8 4894 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 4895 // CHECK5-NEXT: store i64 0, ptr [[TMP24]], align 8 4896 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 4897 // CHECK5-NEXT: store i64 0, ptr [[TMP25]], align 8 4898 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 4899 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4 4900 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 4901 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 4902 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 4903 // CHECK5-NEXT: store i32 0, ptr [[TMP28]], align 4 4904 // CHECK5-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, ptr [[KERNEL_ARGS]]) 4905 // CHECK5-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 4906 // CHECK5-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4907 // CHECK5: omp_offload.failed: 4908 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] 4909 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 4910 // CHECK5: omp_offload.cont: 4911 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4912 // CHECK5: omp_if.else: 4913 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] 4914 // CHECK5-NEXT: br label [[OMP_IF_END]] 4915 // CHECK5: omp_if.end: 4916 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 4917 // CHECK5-NEXT: ret i32 [[TMP31]] 4918 // 4919 // 4920 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 4921 // CHECK5-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 4922 // CHECK5-NEXT: entry: 4923 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4924 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4925 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4926 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4927 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4928 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4929 // CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4930 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4931 // CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 4932 // CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 4933 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 4934 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4935 // CHECK5-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 4936 // CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4937 // CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 4938 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4939 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 4940 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4941 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4942 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 4943 // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4944 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4 4945 // CHECK5-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 4946 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 4947 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 4948 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 4949 // CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 4950 // CHECK5-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 4951 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 4952 // CHECK5-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 4953 // CHECK5-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1 4954 // CHECK5-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4955 // CHECK5: omp_if.then: 4956 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) 4957 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4958 // CHECK5: omp_if.else: 4959 // CHECK5-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 4960 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 4961 // CHECK5-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 4962 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) #[[ATTR4]] 4963 // CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 4964 // CHECK5-NEXT: br label [[OMP_IF_END]] 4965 // CHECK5: omp_if.end: 4966 // CHECK5-NEXT: ret void 4967 // 4968 // 4969 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined 4970 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 4971 // CHECK5-NEXT: entry: 4972 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4973 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4974 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4975 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4976 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4977 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4978 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4979 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4980 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4981 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 4982 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4983 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4984 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4985 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4986 // CHECK5-NEXT: [[IT:%.*]] = alloca i64, align 8 4987 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4988 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4989 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4990 // CHECK5-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 4991 // CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4992 // CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 4993 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4994 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 4995 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4996 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4997 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 4998 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4999 // CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 5000 // CHECK5-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 5001 // CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 5002 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5003 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 5004 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 5005 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5006 // CHECK5: omp_if.then: 5007 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 5008 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 5009 // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 5010 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5011 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 5012 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5013 // CHECK5: cond.true: 5014 // CHECK5-NEXT: br label [[COND_END:%.*]] 5015 // CHECK5: cond.false: 5016 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5017 // CHECK5-NEXT: br label [[COND_END]] 5018 // CHECK5: cond.end: 5019 // CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 5020 // CHECK5-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 5021 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 5022 // CHECK5-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV]], align 8 5023 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5024 // CHECK5: omp.inner.for.cond: 5025 // CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38:![0-9]+]] 5026 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP38]] 5027 // CHECK5-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 5028 // CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5029 // CHECK5: omp.inner.for.body: 5030 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 5031 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 5032 // CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 5033 // CHECK5-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP38]] 5034 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]] 5035 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double 5036 // CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 5037 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 5038 // CHECK5-NEXT: store double [[ADD]], ptr [[A]], align 8, !nontemporal !39, !llvm.access.group [[ACC_GRP38]] 5039 // CHECK5-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 5040 // CHECK5-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 8, !nontemporal !39, !llvm.access.group [[ACC_GRP38]] 5041 // CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 5042 // CHECK5-NEXT: store double [[INC]], ptr [[A4]], align 8, !nontemporal !39, !llvm.access.group [[ACC_GRP38]] 5043 // CHECK5-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 5044 // CHECK5-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]] 5045 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP15]] 5046 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 5047 // CHECK5-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP38]] 5048 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5049 // CHECK5: omp.body.continue: 5050 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5051 // CHECK5: omp.inner.for.inc: 5052 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 5053 // CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1 5054 // CHECK5-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 5055 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] 5056 // CHECK5: omp.inner.for.end: 5057 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 5058 // CHECK5: omp_if.else: 5059 // CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 5060 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 5061 // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP18]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 5062 // CHECK5-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5063 // CHECK5-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[TMP19]], 3 5064 // CHECK5-NEXT: br i1 [[CMP8]], label [[COND_TRUE9:%.*]], label [[COND_FALSE10:%.*]] 5065 // CHECK5: cond.true9: 5066 // CHECK5-NEXT: br label [[COND_END11:%.*]] 5067 // CHECK5: cond.false10: 5068 // CHECK5-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5069 // CHECK5-NEXT: br label [[COND_END11]] 5070 // CHECK5: cond.end11: 5071 // CHECK5-NEXT: [[COND12:%.*]] = phi i64 [ 3, [[COND_TRUE9]] ], [ [[TMP20]], [[COND_FALSE10]] ] 5072 // CHECK5-NEXT: store i64 [[COND12]], ptr [[DOTOMP_UB]], align 8 5073 // CHECK5-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 5074 // CHECK5-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV]], align 8 5075 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 5076 // CHECK5: omp.inner.for.cond13: 5077 // CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 5078 // CHECK5-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5079 // CHECK5-NEXT: [[CMP14:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 5080 // CHECK5-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END29:%.*]] 5081 // CHECK5: omp.inner.for.body15: 5082 // CHECK5-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 5083 // CHECK5-NEXT: [[MUL16:%.*]] = mul i64 [[TMP24]], 400 5084 // CHECK5-NEXT: [[SUB17:%.*]] = sub i64 2000, [[MUL16]] 5085 // CHECK5-NEXT: store i64 [[SUB17]], ptr [[IT]], align 8 5086 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[B_ADDR]], align 4 5087 // CHECK5-NEXT: [[CONV18:%.*]] = sitofp i32 [[TMP25]] to double 5088 // CHECK5-NEXT: [[ADD19:%.*]] = fadd double [[CONV18]], 1.500000e+00 5089 // CHECK5-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 5090 // CHECK5-NEXT: store double [[ADD19]], ptr [[A20]], align 8 5091 // CHECK5-NEXT: [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 5092 // CHECK5-NEXT: [[TMP26:%.*]] = load double, ptr [[A21]], align 8 5093 // CHECK5-NEXT: [[INC22:%.*]] = fadd double [[TMP26]], 1.000000e+00 5094 // CHECK5-NEXT: store double [[INC22]], ptr [[A21]], align 8 5095 // CHECK5-NEXT: [[CONV23:%.*]] = fptosi double [[INC22]] to i16 5096 // CHECK5-NEXT: [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]] 5097 // CHECK5-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP27]] 5098 // CHECK5-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX24]], i64 1 5099 // CHECK5-NEXT: store i16 [[CONV23]], ptr [[ARRAYIDX25]], align 2 5100 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] 5101 // CHECK5: omp.body.continue26: 5102 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] 5103 // CHECK5: omp.inner.for.inc27: 5104 // CHECK5-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 5105 // CHECK5-NEXT: [[ADD28:%.*]] = add i64 [[TMP28]], 1 5106 // CHECK5-NEXT: store i64 [[ADD28]], ptr [[DOTOMP_IV]], align 8 5107 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP42:![0-9]+]] 5108 // CHECK5: omp.inner.for.end29: 5109 // CHECK5-NEXT: br label [[OMP_IF_END]] 5110 // CHECK5: omp_if.end: 5111 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5112 // CHECK5: omp.loop.exit: 5113 // CHECK5-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 5114 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4 5115 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]]) 5116 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5117 // CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 5118 // CHECK5-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5119 // CHECK5: .omp.final.then: 5120 // CHECK5-NEXT: store i64 400, ptr [[IT]], align 8 5121 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 5122 // CHECK5: .omp.final.done: 5123 // CHECK5-NEXT: ret void 5124 // 5125 // 5126 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 5127 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5128 // CHECK5-NEXT: entry: 5129 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5130 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5131 // CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 5132 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 5133 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5134 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 5135 // CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 5136 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 5137 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 5138 // CHECK5-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 5139 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 5140 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 5141 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 5142 // CHECK5-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 5143 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 5144 // CHECK5-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 5145 // CHECK5-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 5146 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 5147 // CHECK5-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 5148 // CHECK5-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 5149 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 5150 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]]) 5151 // CHECK5-NEXT: ret void 5152 // 5153 // 5154 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined 5155 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 5156 // CHECK5-NEXT: entry: 5157 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 5158 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 5159 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5160 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5161 // CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 5162 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 5163 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5164 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 5165 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 5166 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 5167 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 5168 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 5169 // CHECK5-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 5170 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 5171 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 5172 // CHECK5-NEXT: ret void 5173 // 5174 // 5175 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 5176 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5177 // CHECK5-NEXT: entry: 5178 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5179 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5180 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 5181 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5182 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 5183 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 5184 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 5185 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 5186 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 5187 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 5188 // CHECK5-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 5189 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 5190 // CHECK5-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 5191 // CHECK5-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 5192 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 5193 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) 5194 // CHECK5-NEXT: ret void 5195 // 5196 // 5197 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined 5198 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 5199 // CHECK5-NEXT: entry: 5200 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 5201 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 5202 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5203 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5204 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 5205 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5206 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 5207 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5208 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5209 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5210 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5211 // CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8 5212 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 5213 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 5214 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 5215 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 5216 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 5217 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 5218 // CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 5219 // CHECK5-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 5220 // CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 5221 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5222 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 5223 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 5224 // CHECK5-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 5225 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5226 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 5227 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5228 // CHECK5: cond.true: 5229 // CHECK5-NEXT: br label [[COND_END:%.*]] 5230 // CHECK5: cond.false: 5231 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5232 // CHECK5-NEXT: br label [[COND_END]] 5233 // CHECK5: cond.end: 5234 // CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 5235 // CHECK5-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 5236 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 5237 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 5238 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5239 // CHECK5: omp.inner.for.cond: 5240 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44:![0-9]+]] 5241 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP44]] 5242 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 5243 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5244 // CHECK5: omp.inner.for.body: 5245 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44]] 5246 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 5247 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 5248 // CHECK5-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP44]] 5249 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]] 5250 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 5251 // CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]] 5252 // CHECK5-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]] 5253 // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 5254 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 5255 // CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 5256 // CHECK5-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]] 5257 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 5258 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] 5259 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 5260 // CHECK5-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] 5261 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5262 // CHECK5: omp.body.continue: 5263 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5264 // CHECK5: omp.inner.for.inc: 5265 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44]] 5266 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 5267 // CHECK5-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44]] 5268 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]] 5269 // CHECK5: omp.inner.for.end: 5270 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5271 // CHECK5: omp.loop.exit: 5272 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 5273 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5274 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 5275 // CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5276 // CHECK5: .omp.final.then: 5277 // CHECK5-NEXT: store i64 11, ptr [[I]], align 8 5278 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 5279 // CHECK5: .omp.final.done: 5280 // CHECK5-NEXT: ret void 5281 // 5282 // 5283 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 5284 // CHECK5-SAME: () #[[ATTR8:[0-9]+]] { 5285 // CHECK5-NEXT: entry: 5286 // CHECK5-NEXT: call void @__tgt_register_requires(i64 1) 5287 // CHECK5-NEXT: ret void 5288 // 5289 // 5290 // CHECK7-LABEL: define {{[^@]+}}@_Z7get_valv 5291 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 5292 // CHECK7-NEXT: entry: 5293 // CHECK7-NEXT: ret i64 0 5294 // 5295 // 5296 // CHECK7-LABEL: define {{[^@]+}}@_Z3fooi 5297 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 5298 // CHECK7-NEXT: entry: 5299 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5300 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 5301 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 5302 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x float], align 4 5303 // CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 5304 // CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 5305 // CHECK7-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 5306 // CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 5307 // CHECK7-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 5308 // CHECK7-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 5309 // CHECK7-NEXT: [[K:%.*]] = alloca i64, align 8 5310 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5311 // CHECK7-NEXT: [[LIN:%.*]] = alloca i32, align 4 5312 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5313 // CHECK7-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 5314 // CHECK7-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 5315 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 5316 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 5317 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 5318 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 5319 // CHECK7-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 5320 // CHECK7-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 5321 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 4 5322 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 4 5323 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 4 5324 // CHECK7-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 5325 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5326 // CHECK7-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 5327 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 5328 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 4 5329 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 4 5330 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 4 5331 // CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 5332 // CHECK7-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 5333 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 5334 // CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 5335 // CHECK7-NEXT: store i32 0, ptr [[A]], align 4 5336 // CHECK7-NEXT: store i16 0, ptr [[AA]], align 2 5337 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 5338 // CHECK7-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() 5339 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 5340 // CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 5341 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 5342 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 5343 // CHECK7-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 5344 // CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 5345 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 5346 // CHECK7-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, ptr @.omp_task_entry., i64 -1) 5347 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP5]], i32 0, i32 0 5348 // CHECK7-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP5]]) 5349 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 5350 // CHECK7-NEXT: store i64 [[CALL]], ptr [[K]], align 8 5351 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 5352 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 5353 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 5354 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP9]], ptr [[K]]) #[[ATTR4:[0-9]+]] 5355 // CHECK7-NEXT: store i32 12, ptr [[LIN]], align 4 5356 // CHECK7-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2 5357 // CHECK7-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2 5358 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4 5359 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[LIN]], align 4 5360 // CHECK7-NEXT: store i32 [[TMP12]], ptr [[LIN_CASTED]], align 4 5361 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 5362 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4 5363 // CHECK7-NEXT: store i32 [[TMP14]], ptr [[A_CASTED2]], align 4 5364 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[A_CASTED2]], align 4 5365 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5366 // CHECK7-NEXT: store i32 [[TMP11]], ptr [[TMP16]], align 4 5367 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5368 // CHECK7-NEXT: store i32 [[TMP11]], ptr [[TMP17]], align 4 5369 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5370 // CHECK7-NEXT: store ptr null, ptr [[TMP18]], align 4 5371 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5372 // CHECK7-NEXT: store i32 [[TMP13]], ptr [[TMP19]], align 4 5373 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5374 // CHECK7-NEXT: store i32 [[TMP13]], ptr [[TMP20]], align 4 5375 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5376 // CHECK7-NEXT: store ptr null, ptr [[TMP21]], align 4 5377 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5378 // CHECK7-NEXT: store i32 [[TMP15]], ptr [[TMP22]], align 4 5379 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5380 // CHECK7-NEXT: store i32 [[TMP15]], ptr [[TMP23]], align 4 5381 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5382 // CHECK7-NEXT: store ptr null, ptr [[TMP24]], align 4 5383 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5384 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5385 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 5386 // CHECK7-NEXT: store i32 2, ptr [[TMP27]], align 4 5387 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 5388 // CHECK7-NEXT: store i32 3, ptr [[TMP28]], align 4 5389 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 5390 // CHECK7-NEXT: store ptr [[TMP25]], ptr [[TMP29]], align 4 5391 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 5392 // CHECK7-NEXT: store ptr [[TMP26]], ptr [[TMP30]], align 4 5393 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 5394 // CHECK7-NEXT: store ptr @.offload_sizes, ptr [[TMP31]], align 4 5395 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 5396 // CHECK7-NEXT: store ptr @.offload_maptypes, ptr [[TMP32]], align 4 5397 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 5398 // CHECK7-NEXT: store ptr null, ptr [[TMP33]], align 4 5399 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 5400 // CHECK7-NEXT: store ptr null, ptr [[TMP34]], align 4 5401 // CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 5402 // CHECK7-NEXT: store i64 0, ptr [[TMP35]], align 8 5403 // CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 5404 // CHECK7-NEXT: store i64 0, ptr [[TMP36]], align 8 5405 // CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 5406 // CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP37]], align 4 5407 // CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 5408 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP38]], align 4 5409 // CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 5410 // CHECK7-NEXT: store i32 0, ptr [[TMP39]], align 4 5411 // CHECK7-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, ptr [[KERNEL_ARGS]]) 5412 // CHECK7-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 5413 // CHECK7-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5414 // CHECK7: omp_offload.failed: 5415 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP11]], i32 [[TMP13]], i32 [[TMP15]]) #[[ATTR4]] 5416 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 5417 // CHECK7: omp_offload.cont: 5418 // CHECK7-NEXT: [[TMP42:%.*]] = load i32, ptr [[A]], align 4 5419 // CHECK7-NEXT: store i32 [[TMP42]], ptr [[A_CASTED3]], align 4 5420 // CHECK7-NEXT: [[TMP43:%.*]] = load i32, ptr [[A_CASTED3]], align 4 5421 // CHECK7-NEXT: [[TMP44:%.*]] = load i16, ptr [[AA]], align 2 5422 // CHECK7-NEXT: store i16 [[TMP44]], ptr [[AA_CASTED4]], align 2 5423 // CHECK7-NEXT: [[TMP45:%.*]] = load i32, ptr [[AA_CASTED4]], align 4 5424 // CHECK7-NEXT: [[TMP46:%.*]] = load i32, ptr [[N_ADDR]], align 4 5425 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP46]], 10 5426 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5427 // CHECK7: omp_if.then: 5428 // CHECK7-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 5429 // CHECK7-NEXT: store i32 [[TMP43]], ptr [[TMP47]], align 4 5430 // CHECK7-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 5431 // CHECK7-NEXT: store i32 [[TMP43]], ptr [[TMP48]], align 4 5432 // CHECK7-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 5433 // CHECK7-NEXT: store ptr null, ptr [[TMP49]], align 4 5434 // CHECK7-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 5435 // CHECK7-NEXT: store i32 [[TMP45]], ptr [[TMP50]], align 4 5436 // CHECK7-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 5437 // CHECK7-NEXT: store i32 [[TMP45]], ptr [[TMP51]], align 4 5438 // CHECK7-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 5439 // CHECK7-NEXT: store ptr null, ptr [[TMP52]], align 4 5440 // CHECK7-NEXT: [[TMP53:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 5441 // CHECK7-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 5442 // CHECK7-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0 5443 // CHECK7-NEXT: store i32 2, ptr [[TMP55]], align 4 5444 // CHECK7-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1 5445 // CHECK7-NEXT: store i32 2, ptr [[TMP56]], align 4 5446 // CHECK7-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2 5447 // CHECK7-NEXT: store ptr [[TMP53]], ptr [[TMP57]], align 4 5448 // CHECK7-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3 5449 // CHECK7-NEXT: store ptr [[TMP54]], ptr [[TMP58]], align 4 5450 // CHECK7-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4 5451 // CHECK7-NEXT: store ptr @.offload_sizes.1, ptr [[TMP59]], align 4 5452 // CHECK7-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5 5453 // CHECK7-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP60]], align 4 5454 // CHECK7-NEXT: [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6 5455 // CHECK7-NEXT: store ptr null, ptr [[TMP61]], align 4 5456 // CHECK7-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7 5457 // CHECK7-NEXT: store ptr null, ptr [[TMP62]], align 4 5458 // CHECK7-NEXT: [[TMP63:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8 5459 // CHECK7-NEXT: store i64 0, ptr [[TMP63]], align 8 5460 // CHECK7-NEXT: [[TMP64:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 9 5461 // CHECK7-NEXT: store i64 0, ptr [[TMP64]], align 8 5462 // CHECK7-NEXT: [[TMP65:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 10 5463 // CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP65]], align 4 5464 // CHECK7-NEXT: [[TMP66:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 11 5465 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP66]], align 4 5466 // CHECK7-NEXT: [[TMP67:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12 5467 // CHECK7-NEXT: store i32 0, ptr [[TMP67]], align 4 5468 // CHECK7-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, ptr [[KERNEL_ARGS8]]) 5469 // CHECK7-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 5470 // CHECK7-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 5471 // CHECK7: omp_offload.failed9: 5472 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR4]] 5473 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT10]] 5474 // CHECK7: omp_offload.cont10: 5475 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 5476 // CHECK7: omp_if.else: 5477 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR4]] 5478 // CHECK7-NEXT: br label [[OMP_IF_END]] 5479 // CHECK7: omp_if.end: 5480 // CHECK7-NEXT: [[TMP70:%.*]] = load i32, ptr [[A]], align 4 5481 // CHECK7-NEXT: store i32 [[TMP70]], ptr [[DOTCAPTURE_EXPR_]], align 4 5482 // CHECK7-NEXT: [[TMP71:%.*]] = load i32, ptr [[A]], align 4 5483 // CHECK7-NEXT: store i32 [[TMP71]], ptr [[A_CASTED11]], align 4 5484 // CHECK7-NEXT: [[TMP72:%.*]] = load i32, ptr [[A_CASTED11]], align 4 5485 // CHECK7-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 5486 // CHECK7-NEXT: store i32 [[TMP73]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 5487 // CHECK7-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 5488 // CHECK7-NEXT: [[TMP75:%.*]] = load i32, ptr [[N_ADDR]], align 4 5489 // CHECK7-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP75]], 20 5490 // CHECK7-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]] 5491 // CHECK7: omp_if.then13: 5492 // CHECK7-NEXT: [[TMP76:%.*]] = mul nuw i32 [[TMP1]], 4 5493 // CHECK7-NEXT: [[TMP77:%.*]] = sext i32 [[TMP76]] to i64 5494 // CHECK7-NEXT: [[TMP78:%.*]] = mul nuw i32 5, [[TMP3]] 5495 // CHECK7-NEXT: [[TMP79:%.*]] = mul nuw i32 [[TMP78]], 8 5496 // CHECK7-NEXT: [[TMP80:%.*]] = sext i32 [[TMP79]] to i64 5497 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.3, i32 80, i1 false) 5498 // CHECK7-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 5499 // CHECK7-NEXT: store i32 [[TMP72]], ptr [[TMP81]], align 4 5500 // CHECK7-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 5501 // CHECK7-NEXT: store i32 [[TMP72]], ptr [[TMP82]], align 4 5502 // CHECK7-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 5503 // CHECK7-NEXT: store ptr null, ptr [[TMP83]], align 4 5504 // CHECK7-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 5505 // CHECK7-NEXT: store ptr [[B]], ptr [[TMP84]], align 4 5506 // CHECK7-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 5507 // CHECK7-NEXT: store ptr [[B]], ptr [[TMP85]], align 4 5508 // CHECK7-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 5509 // CHECK7-NEXT: store ptr null, ptr [[TMP86]], align 4 5510 // CHECK7-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 5511 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP87]], align 4 5512 // CHECK7-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 5513 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP88]], align 4 5514 // CHECK7-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 5515 // CHECK7-NEXT: store ptr null, ptr [[TMP89]], align 4 5516 // CHECK7-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 5517 // CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP90]], align 4 5518 // CHECK7-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 5519 // CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP91]], align 4 5520 // CHECK7-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 5521 // CHECK7-NEXT: store i64 [[TMP77]], ptr [[TMP92]], align 4 5522 // CHECK7-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 5523 // CHECK7-NEXT: store ptr null, ptr [[TMP93]], align 4 5524 // CHECK7-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 5525 // CHECK7-NEXT: store ptr [[C]], ptr [[TMP94]], align 4 5526 // CHECK7-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 5527 // CHECK7-NEXT: store ptr [[C]], ptr [[TMP95]], align 4 5528 // CHECK7-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 5529 // CHECK7-NEXT: store ptr null, ptr [[TMP96]], align 4 5530 // CHECK7-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 5531 // CHECK7-NEXT: store i32 5, ptr [[TMP97]], align 4 5532 // CHECK7-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 5533 // CHECK7-NEXT: store i32 5, ptr [[TMP98]], align 4 5534 // CHECK7-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 5535 // CHECK7-NEXT: store ptr null, ptr [[TMP99]], align 4 5536 // CHECK7-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 5537 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP100]], align 4 5538 // CHECK7-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 5539 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP101]], align 4 5540 // CHECK7-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 5541 // CHECK7-NEXT: store ptr null, ptr [[TMP102]], align 4 5542 // CHECK7-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 5543 // CHECK7-NEXT: store ptr [[VLA1]], ptr [[TMP103]], align 4 5544 // CHECK7-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 5545 // CHECK7-NEXT: store ptr [[VLA1]], ptr [[TMP104]], align 4 5546 // CHECK7-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 5547 // CHECK7-NEXT: store i64 [[TMP80]], ptr [[TMP105]], align 4 5548 // CHECK7-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 5549 // CHECK7-NEXT: store ptr null, ptr [[TMP106]], align 4 5550 // CHECK7-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 5551 // CHECK7-NEXT: store ptr [[D]], ptr [[TMP107]], align 4 5552 // CHECK7-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 5553 // CHECK7-NEXT: store ptr [[D]], ptr [[TMP108]], align 4 5554 // CHECK7-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 5555 // CHECK7-NEXT: store ptr null, ptr [[TMP109]], align 4 5556 // CHECK7-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 5557 // CHECK7-NEXT: store i32 [[TMP74]], ptr [[TMP110]], align 4 5558 // CHECK7-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 5559 // CHECK7-NEXT: store i32 [[TMP74]], ptr [[TMP111]], align 4 5560 // CHECK7-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 5561 // CHECK7-NEXT: store ptr null, ptr [[TMP112]], align 4 5562 // CHECK7-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 5563 // CHECK7-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 5564 // CHECK7-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5565 // CHECK7-NEXT: [[TMP116:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0 5566 // CHECK7-NEXT: store i32 2, ptr [[TMP116]], align 4 5567 // CHECK7-NEXT: [[TMP117:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1 5568 // CHECK7-NEXT: store i32 10, ptr [[TMP117]], align 4 5569 // CHECK7-NEXT: [[TMP118:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2 5570 // CHECK7-NEXT: store ptr [[TMP113]], ptr [[TMP118]], align 4 5571 // CHECK7-NEXT: [[TMP119:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3 5572 // CHECK7-NEXT: store ptr [[TMP114]], ptr [[TMP119]], align 4 5573 // CHECK7-NEXT: [[TMP120:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4 5574 // CHECK7-NEXT: store ptr [[TMP115]], ptr [[TMP120]], align 4 5575 // CHECK7-NEXT: [[TMP121:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5 5576 // CHECK7-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP121]], align 4 5577 // CHECK7-NEXT: [[TMP122:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6 5578 // CHECK7-NEXT: store ptr null, ptr [[TMP122]], align 4 5579 // CHECK7-NEXT: [[TMP123:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7 5580 // CHECK7-NEXT: store ptr null, ptr [[TMP123]], align 4 5581 // CHECK7-NEXT: [[TMP124:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8 5582 // CHECK7-NEXT: store i64 0, ptr [[TMP124]], align 8 5583 // CHECK7-NEXT: [[TMP125:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 9 5584 // CHECK7-NEXT: store i64 0, ptr [[TMP125]], align 8 5585 // CHECK7-NEXT: [[TMP126:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 10 5586 // CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP126]], align 4 5587 // CHECK7-NEXT: [[TMP127:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 11 5588 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP127]], align 4 5589 // CHECK7-NEXT: [[TMP128:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12 5590 // CHECK7-NEXT: store i32 0, ptr [[TMP128]], align 4 5591 // CHECK7-NEXT: [[TMP129:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, ptr [[KERNEL_ARGS17]]) 5592 // CHECK7-NEXT: [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 0 5593 // CHECK7-NEXT: br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] 5594 // CHECK7: omp_offload.failed18: 5595 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR4]] 5596 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT19]] 5597 // CHECK7: omp_offload.cont19: 5598 // CHECK7-NEXT: br label [[OMP_IF_END21:%.*]] 5599 // CHECK7: omp_if.else20: 5600 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR4]] 5601 // CHECK7-NEXT: br label [[OMP_IF_END21]] 5602 // CHECK7: omp_if.end21: 5603 // CHECK7-NEXT: [[TMP131:%.*]] = load i32, ptr [[A]], align 4 5604 // CHECK7-NEXT: [[TMP132:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 5605 // CHECK7-NEXT: call void @llvm.stackrestore(ptr [[TMP132]]) 5606 // CHECK7-NEXT: ret i32 [[TMP131]] 5607 // 5608 // 5609 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 5610 // CHECK7-SAME: () #[[ATTR2:[0-9]+]] { 5611 // CHECK7-NEXT: entry: 5612 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) 5613 // CHECK7-NEXT: ret void 5614 // 5615 // 5616 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined 5617 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 5618 // CHECK7-NEXT: entry: 5619 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 5620 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 5621 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5622 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5623 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5624 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5625 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5626 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5627 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 5628 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 5629 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 5630 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5631 // CHECK7-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 5632 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 5633 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5634 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 5635 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 5636 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 5637 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5638 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 5639 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5640 // CHECK7: cond.true: 5641 // CHECK7-NEXT: br label [[COND_END:%.*]] 5642 // CHECK7: cond.false: 5643 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5644 // CHECK7-NEXT: br label [[COND_END]] 5645 // CHECK7: cond.end: 5646 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 5647 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 5648 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5649 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 5650 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5651 // CHECK7: omp.inner.for.cond: 5652 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 5653 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 5654 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 5655 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5656 // CHECK7: omp.inner.for.body: 5657 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 5658 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 5659 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 5660 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 5661 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5662 // CHECK7: omp.body.continue: 5663 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5664 // CHECK7: omp.inner.for.inc: 5665 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 5666 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 5667 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 5668 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 5669 // CHECK7: omp.inner.for.end: 5670 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5671 // CHECK7: omp.loop.exit: 5672 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 5673 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5674 // CHECK7-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 5675 // CHECK7-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5676 // CHECK7: .omp.final.then: 5677 // CHECK7-NEXT: store i32 33, ptr [[I]], align 4 5678 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 5679 // CHECK7: .omp.final.done: 5680 // CHECK7-NEXT: ret void 5681 // 5682 // 5683 // CHECK7-LABEL: define {{[^@]+}}@.omp_task_entry. 5684 // CHECK7-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 5685 // CHECK7-NEXT: entry: 5686 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 5687 // CHECK7-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4 5688 // CHECK7-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4 5689 // CHECK7-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4 5690 // CHECK7-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4 5691 // CHECK7-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4 5692 // CHECK7-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 5693 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 5694 // CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 5695 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 5696 // CHECK7-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 5697 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 5698 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 5699 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 5700 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 5701 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 5702 // CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 5703 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 5704 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 5705 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 5706 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) 5707 // CHECK7-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 5708 // CHECK7-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias !26 5709 // CHECK7-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26 5710 // CHECK7-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26 5711 // CHECK7-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias !26 5712 // CHECK7-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !26 5713 // CHECK7-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !26 5714 // CHECK7-NEXT: store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !26 5715 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 5716 // CHECK7-NEXT: store i32 0, ptr [[TMP9]], align 4, !noalias !26 5717 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 5718 // CHECK7-NEXT: store ptr null, ptr [[TMP10]], align 4, !noalias !26 5719 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 5720 // CHECK7-NEXT: store ptr null, ptr [[TMP11]], align 4, !noalias !26 5721 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 5722 // CHECK7-NEXT: store ptr null, ptr [[TMP12]], align 4, !noalias !26 5723 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 5724 // CHECK7-NEXT: store ptr null, ptr [[TMP13]], align 4, !noalias !26 5725 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 5726 // CHECK7-NEXT: store ptr null, ptr [[TMP14]], align 4, !noalias !26 5727 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 5728 // CHECK7-NEXT: store ptr null, ptr [[TMP15]], align 4, !noalias !26 5729 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 5730 // CHECK7-NEXT: store i64 0, ptr [[TMP16]], align 8, !noalias !26 5731 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9 5732 // CHECK7-NEXT: store i64 1, ptr [[TMP17]], align 8, !noalias !26 5733 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10 5734 // CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4, !noalias !26 5735 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11 5736 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4, !noalias !26 5737 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12 5738 // CHECK7-NEXT: store i32 0, ptr [[TMP20]], align 4, !noalias !26 5739 // CHECK7-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, ptr [[KERNEL_ARGS_I]]) 5740 // CHECK7-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 5741 // CHECK7-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] 5742 // CHECK7: omp_offload.failed.i: 5743 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] 5744 // CHECK7-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] 5745 // CHECK7: .omp_outlined..exit: 5746 // CHECK7-NEXT: ret i32 0 5747 // 5748 // 5749 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 5750 // CHECK7-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 5751 // CHECK7-NEXT: entry: 5752 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5753 // CHECK7-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4 5754 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5755 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5756 // CHECK7-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4 5757 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4 5758 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 5759 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 5760 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 5761 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i32 [[TMP2]], ptr [[TMP0]]) 5762 // CHECK7-NEXT: ret void 5763 // 5764 // 5765 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined 5766 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 5767 // CHECK7-NEXT: entry: 5768 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 5769 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 5770 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5771 // CHECK7-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4 5772 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5773 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5774 // CHECK7-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 5775 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5776 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5777 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5778 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5779 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 5780 // CHECK7-NEXT: [[K1:%.*]] = alloca i64, align 8 5781 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 5782 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 5783 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5784 // CHECK7-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4 5785 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4 5786 // CHECK7-NEXT: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 8 5787 // CHECK7-NEXT: store i64 [[TMP1]], ptr [[DOTLINEAR_START]], align 8 5788 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5789 // CHECK7-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 4 5790 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 5791 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5792 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 5793 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 5794 // CHECK7-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 5795 // CHECK7-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 5796 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 5797 // CHECK7: omp.dispatch.cond: 5798 // CHECK7-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]) 5799 // CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 5800 // CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 5801 // CHECK7: omp.dispatch.body: 5802 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5803 // CHECK7-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 5804 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5805 // CHECK7: omp.inner.for.cond: 5806 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] 5807 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] 5808 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 5809 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5810 // CHECK7: omp.inner.for.body: 5811 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 5812 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 5813 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 5814 // CHECK7-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] 5815 // CHECK7-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP27]] 5816 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 5817 // CHECK7-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 5818 // CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 5819 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 5820 // CHECK7-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP27]] 5821 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 5822 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 5823 // CHECK7-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 5824 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5825 // CHECK7: omp.body.continue: 5826 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5827 // CHECK7: omp.inner.for.inc: 5828 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 5829 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 5830 // CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 5831 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 5832 // CHECK7: omp.inner.for.end: 5833 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 5834 // CHECK7: omp.dispatch.inc: 5835 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] 5836 // CHECK7: omp.dispatch.end: 5837 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5838 // CHECK7-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 5839 // CHECK7-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5840 // CHECK7: .omp.final.then: 5841 // CHECK7-NEXT: store i32 1, ptr [[I]], align 4 5842 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 5843 // CHECK7: .omp.final.done: 5844 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5845 // CHECK7-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 5846 // CHECK7-NEXT: br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 5847 // CHECK7: .omp.linear.pu: 5848 // CHECK7-NEXT: [[TMP17:%.*]] = load i64, ptr [[K1]], align 8 5849 // CHECK7-NEXT: store i64 [[TMP17]], ptr [[TMP0]], align 8 5850 // CHECK7-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 5851 // CHECK7: .omp.linear.pu.done: 5852 // CHECK7-NEXT: ret void 5853 // 5854 // 5855 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 5856 // CHECK7-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 5857 // CHECK7-NEXT: entry: 5858 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5859 // CHECK7-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 5860 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5861 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5862 // CHECK7-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 5863 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5864 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 5865 // CHECK7-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 5866 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5867 // CHECK7-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 5868 // CHECK7-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 5869 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 5870 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 5871 // CHECK7-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 5872 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 5873 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 5874 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 5875 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4 5876 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 5877 // CHECK7-NEXT: ret void 5878 // 5879 // 5880 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined 5881 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 5882 // CHECK7-NEXT: entry: 5883 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 5884 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 5885 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5886 // CHECK7-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 5887 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5888 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5889 // CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 5890 // CHECK7-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 5891 // CHECK7-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 5892 // CHECK7-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 5893 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5894 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5895 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5896 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5897 // CHECK7-NEXT: [[IT:%.*]] = alloca i64, align 8 5898 // CHECK7-NEXT: [[LIN2:%.*]] = alloca i32, align 4 5899 // CHECK7-NEXT: [[A3:%.*]] = alloca i32, align 4 5900 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 5901 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 5902 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 5903 // CHECK7-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 5904 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5905 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 5906 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 5907 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 5908 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 5909 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 5910 // CHECK7-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 5911 // CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 5912 // CHECK7-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 5913 // CHECK7-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 5914 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5915 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 5916 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 5917 // CHECK7-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]]) 5918 // CHECK7-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 5919 // CHECK7-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5920 // CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 5921 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5922 // CHECK7: cond.true: 5923 // CHECK7-NEXT: br label [[COND_END:%.*]] 5924 // CHECK7: cond.false: 5925 // CHECK7-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 5926 // CHECK7-NEXT: br label [[COND_END]] 5927 // CHECK7: cond.end: 5928 // CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 5929 // CHECK7-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 5930 // CHECK7-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 5931 // CHECK7-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 5932 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5933 // CHECK7: omp.inner.for.cond: 5934 // CHECK7-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30:![0-9]+]] 5935 // CHECK7-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP30]] 5936 // CHECK7-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 5937 // CHECK7-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5938 // CHECK7: omp.inner.for.body: 5939 // CHECK7-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 5940 // CHECK7-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 5941 // CHECK7-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 5942 // CHECK7-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP30]] 5943 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP30]] 5944 // CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 5945 // CHECK7-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 5946 // CHECK7-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]] 5947 // CHECK7-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 5948 // CHECK7-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 5949 // CHECK7-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 5950 // CHECK7-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP30]] 5951 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP30]] 5952 // CHECK7-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 5953 // CHECK7-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 5954 // CHECK7-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]] 5955 // CHECK7-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 5956 // CHECK7-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 5957 // CHECK7-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 5958 // CHECK7-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP30]] 5959 // CHECK7-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] 5960 // CHECK7-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 5961 // CHECK7-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 5962 // CHECK7-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 5963 // CHECK7-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] 5964 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5965 // CHECK7: omp.body.continue: 5966 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5967 // CHECK7: omp.inner.for.inc: 5968 // CHECK7-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 5969 // CHECK7-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 5970 // CHECK7-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 5971 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 5972 // CHECK7: omp.inner.for.end: 5973 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5974 // CHECK7: omp.loop.exit: 5975 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 5976 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5977 // CHECK7-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 5978 // CHECK7-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5979 // CHECK7: .omp.final.then: 5980 // CHECK7-NEXT: store i64 400, ptr [[IT]], align 8 5981 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 5982 // CHECK7: .omp.final.done: 5983 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5984 // CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 5985 // CHECK7-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 5986 // CHECK7: .omp.linear.pu: 5987 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 5988 // CHECK7-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 5989 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 5990 // CHECK7-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 5991 // CHECK7-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 5992 // CHECK7: .omp.linear.pu.done: 5993 // CHECK7-NEXT: ret void 5994 // 5995 // 5996 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 5997 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 5998 // CHECK7-NEXT: entry: 5999 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6000 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6001 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6002 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6003 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6004 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 6005 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 6006 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 6007 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 6008 // CHECK7-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 6009 // CHECK7-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 6010 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 6011 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) 6012 // CHECK7-NEXT: ret void 6013 // 6014 // 6015 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined 6016 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 6017 // CHECK7-NEXT: entry: 6018 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 6019 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 6020 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6021 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6022 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6023 // CHECK7-NEXT: [[TMP:%.*]] = alloca i16, align 2 6024 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6025 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6026 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6027 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6028 // CHECK7-NEXT: [[IT:%.*]] = alloca i16, align 2 6029 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 6030 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 6031 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6032 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 6033 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 6034 // CHECK7-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 6035 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 6036 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 6037 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6038 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 6039 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 6040 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6041 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 6042 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6043 // CHECK7: cond.true: 6044 // CHECK7-NEXT: br label [[COND_END:%.*]] 6045 // CHECK7: cond.false: 6046 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6047 // CHECK7-NEXT: br label [[COND_END]] 6048 // CHECK7: cond.end: 6049 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 6050 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 6051 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6052 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 6053 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6054 // CHECK7: omp.inner.for.cond: 6055 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] 6056 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] 6057 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 6058 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6059 // CHECK7: omp.inner.for.body: 6060 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 6061 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 6062 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 6063 // CHECK7-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 6064 // CHECK7-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP33]] 6065 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 6066 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 6067 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 6068 // CHECK7-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] 6069 // CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 6070 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 6071 // CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 6072 // CHECK7-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] 6073 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6074 // CHECK7: omp.body.continue: 6075 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6076 // CHECK7: omp.inner.for.inc: 6077 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 6078 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 6079 // CHECK7-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 6080 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 6081 // CHECK7: omp.inner.for.end: 6082 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6083 // CHECK7: omp.loop.exit: 6084 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 6085 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 6086 // CHECK7-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 6087 // CHECK7-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6088 // CHECK7: .omp.final.then: 6089 // CHECK7-NEXT: store i16 22, ptr [[IT]], align 2 6090 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6091 // CHECK7: .omp.final.done: 6092 // CHECK7-NEXT: ret void 6093 // 6094 // 6095 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 6096 // CHECK7-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 6097 // CHECK7-NEXT: entry: 6098 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6099 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6100 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6101 // CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 6102 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 6103 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6104 // CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 6105 // CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 6106 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 6107 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6108 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6109 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 6110 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6111 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6112 // CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 6113 // CHECK7-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 6114 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 6115 // CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 6116 // CHECK7-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 6117 // CHECK7-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 6118 // CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 6119 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 6120 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 6121 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 6122 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 6123 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 6124 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 6125 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 6126 // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 6127 // CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 6128 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 6129 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 6130 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 6131 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 6132 // CHECK7-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 6133 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 6134 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]]) 6135 // CHECK7-NEXT: ret void 6136 // 6137 // 6138 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined 6139 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 6140 // CHECK7-NEXT: entry: 6141 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 6142 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 6143 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6144 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6145 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6146 // CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 6147 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 6148 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6149 // CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 6150 // CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 6151 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 6152 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6153 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6154 // CHECK7-NEXT: [[TMP:%.*]] = alloca i8, align 1 6155 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6156 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6157 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6158 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6159 // CHECK7-NEXT: [[IT:%.*]] = alloca i8, align 1 6160 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 6161 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 6162 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6163 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6164 // CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 6165 // CHECK7-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 6166 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 6167 // CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 6168 // CHECK7-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 6169 // CHECK7-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 6170 // CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 6171 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 6172 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 6173 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 6174 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 6175 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 6176 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 6177 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 6178 // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 6179 // CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 6180 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 6181 // CHECK7-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 6182 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 6183 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 6184 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 6185 // CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6186 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 6187 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 6188 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6189 // CHECK7: omp.dispatch.cond: 6190 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6191 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 6192 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6193 // CHECK7: cond.true: 6194 // CHECK7-NEXT: br label [[COND_END:%.*]] 6195 // CHECK7: cond.false: 6196 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6197 // CHECK7-NEXT: br label [[COND_END]] 6198 // CHECK7: cond.end: 6199 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 6200 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 6201 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6202 // CHECK7-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 6203 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 6204 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6205 // CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 6206 // CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6207 // CHECK7: omp.dispatch.body: 6208 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6209 // CHECK7: omp.inner.for.cond: 6210 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] 6211 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]] 6212 // CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 6213 // CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6214 // CHECK7: omp.inner.for.body: 6215 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 6216 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 6217 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 6218 // CHECK7-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 6219 // CHECK7-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP36]] 6220 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] 6221 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 6222 // CHECK7-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] 6223 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 6224 // CHECK7-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] 6225 // CHECK7-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 6226 // CHECK7-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 6227 // CHECK7-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 6228 // CHECK7-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] 6229 // CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 6230 // CHECK7-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]] 6231 // CHECK7-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 6232 // CHECK7-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 6233 // CHECK7-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 6234 // CHECK7-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]] 6235 // CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 6236 // CHECK7-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 6237 // CHECK7-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] 6238 // CHECK7-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 6239 // CHECK7-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] 6240 // CHECK7-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 6241 // CHECK7-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]] 6242 // CHECK7-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3 6243 // CHECK7-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]] 6244 // CHECK7-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 6245 // CHECK7-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]] 6246 // CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 6247 // CHECK7-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]] 6248 // CHECK7-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 6249 // CHECK7-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]] 6250 // CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 6251 // CHECK7-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]] 6252 // CHECK7-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 6253 // CHECK7-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 6254 // CHECK7-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 6255 // CHECK7-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]] 6256 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6257 // CHECK7: omp.body.continue: 6258 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6259 // CHECK7: omp.inner.for.inc: 6260 // CHECK7-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 6261 // CHECK7-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 6262 // CHECK7-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 6263 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] 6264 // CHECK7: omp.inner.for.end: 6265 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6266 // CHECK7: omp.dispatch.inc: 6267 // CHECK7-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6268 // CHECK7-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 6269 // CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 6270 // CHECK7-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 6271 // CHECK7-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6272 // CHECK7-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 6273 // CHECK7-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 6274 // CHECK7-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 6275 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] 6276 // CHECK7: omp.dispatch.end: 6277 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 6278 // CHECK7-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 6279 // CHECK7-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 6280 // CHECK7-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6281 // CHECK7: .omp.final.then: 6282 // CHECK7-NEXT: store i8 96, ptr [[IT]], align 1 6283 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6284 // CHECK7: .omp.final.done: 6285 // CHECK7-NEXT: ret void 6286 // 6287 // 6288 // CHECK7-LABEL: define {{[^@]+}}@_Z3bari 6289 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 6290 // CHECK7-NEXT: entry: 6291 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6292 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6293 // CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 6294 // CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 6295 // CHECK7-NEXT: store i32 0, ptr [[A]], align 4 6296 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 6297 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 6298 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 6299 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6300 // CHECK7-NEXT: store i32 [[ADD]], ptr [[A]], align 4 6301 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 6302 // CHECK7-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 6303 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 6304 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6305 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 6306 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 6307 // CHECK7-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 6308 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 6309 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6310 // CHECK7-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 6311 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 6312 // CHECK7-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 6313 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 6314 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 6315 // CHECK7-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 6316 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 6317 // CHECK7-NEXT: ret i32 [[TMP8]] 6318 // 6319 // 6320 // CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6321 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6322 // CHECK7-NEXT: entry: 6323 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 6324 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6325 // CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 6326 // CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 6327 // CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 6328 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 6329 // CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6330 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 6331 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x ptr], align 4 6332 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x ptr], align 4 6333 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x ptr], align 4 6334 // CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 4 6335 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 6336 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 6337 // CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 6338 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 6339 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 6340 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6341 // CHECK7-NEXT: store i32 [[ADD]], ptr [[B]], align 4 6342 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 6343 // CHECK7-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() 6344 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 6345 // CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 6346 // CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 6347 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 6348 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 6349 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 6350 // CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 6351 // CHECK7-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 6352 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 6353 // CHECK7-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 6354 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4 6355 // CHECK7-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 6356 // CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 6357 // CHECK7-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8 6358 // CHECK7-NEXT: store i8 [[FROMBOOL2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 6359 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 6360 // CHECK7-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 6361 // CHECK7-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1 6362 // CHECK7-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6363 // CHECK7: omp_if.then: 6364 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 6365 // CHECK7-NEXT: [[TMP10:%.*]] = mul nuw i32 2, [[TMP1]] 6366 // CHECK7-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 2 6367 // CHECK7-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 6368 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 48, i1 false) 6369 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6370 // CHECK7-NEXT: store ptr [[THIS1]], ptr [[TMP13]], align 4 6371 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6372 // CHECK7-NEXT: store ptr [[A]], ptr [[TMP14]], align 4 6373 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6374 // CHECK7-NEXT: store ptr null, ptr [[TMP15]], align 4 6375 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6376 // CHECK7-NEXT: store i32 [[TMP6]], ptr [[TMP16]], align 4 6377 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6378 // CHECK7-NEXT: store i32 [[TMP6]], ptr [[TMP17]], align 4 6379 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6380 // CHECK7-NEXT: store ptr null, ptr [[TMP18]], align 4 6381 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6382 // CHECK7-NEXT: store i32 2, ptr [[TMP19]], align 4 6383 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6384 // CHECK7-NEXT: store i32 2, ptr [[TMP20]], align 4 6385 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6386 // CHECK7-NEXT: store ptr null, ptr [[TMP21]], align 4 6387 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6388 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP22]], align 4 6389 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6390 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP23]], align 4 6391 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 6392 // CHECK7-NEXT: store ptr null, ptr [[TMP24]], align 4 6393 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 6394 // CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP25]], align 4 6395 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 6396 // CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP26]], align 4 6397 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 6398 // CHECK7-NEXT: store i64 [[TMP12]], ptr [[TMP27]], align 4 6399 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 6400 // CHECK7-NEXT: store ptr null, ptr [[TMP28]], align 4 6401 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 6402 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[TMP29]], align 4 6403 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5 6404 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[TMP30]], align 4 6405 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 6406 // CHECK7-NEXT: store ptr null, ptr [[TMP31]], align 4 6407 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6408 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6409 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 6410 // CHECK7-NEXT: [[TMP35:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 6411 // CHECK7-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP35]] to i1 6412 // CHECK7-NEXT: [[TMP36:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 6413 // CHECK7-NEXT: [[TMP37:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP36]], 0 6414 // CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 6415 // CHECK7-NEXT: store i32 2, ptr [[TMP38]], align 4 6416 // CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 6417 // CHECK7-NEXT: store i32 6, ptr [[TMP39]], align 4 6418 // CHECK7-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 6419 // CHECK7-NEXT: store ptr [[TMP32]], ptr [[TMP40]], align 4 6420 // CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 6421 // CHECK7-NEXT: store ptr [[TMP33]], ptr [[TMP41]], align 4 6422 // CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 6423 // CHECK7-NEXT: store ptr [[TMP34]], ptr [[TMP42]], align 4 6424 // CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 6425 // CHECK7-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP43]], align 4 6426 // CHECK7-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 6427 // CHECK7-NEXT: store ptr null, ptr [[TMP44]], align 4 6428 // CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 6429 // CHECK7-NEXT: store ptr null, ptr [[TMP45]], align 4 6430 // CHECK7-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 6431 // CHECK7-NEXT: store i64 0, ptr [[TMP46]], align 8 6432 // CHECK7-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 6433 // CHECK7-NEXT: store i64 0, ptr [[TMP47]], align 8 6434 // CHECK7-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 6435 // CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP48]], align 4 6436 // CHECK7-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 6437 // CHECK7-NEXT: store [3 x i32] [[TMP37]], ptr [[TMP49]], align 4 6438 // CHECK7-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 6439 // CHECK7-NEXT: store i32 0, ptr [[TMP50]], align 4 6440 // CHECK7-NEXT: [[TMP51:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 [[TMP36]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, ptr [[KERNEL_ARGS]]) 6441 // CHECK7-NEXT: [[TMP52:%.*]] = icmp ne i32 [[TMP51]], 0 6442 // CHECK7-NEXT: br i1 [[TMP52]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6443 // CHECK7: omp_offload.failed: 6444 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR4]] 6445 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 6446 // CHECK7: omp_offload.cont: 6447 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6448 // CHECK7: omp_if.else: 6449 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR4]] 6450 // CHECK7-NEXT: br label [[OMP_IF_END]] 6451 // CHECK7: omp_if.end: 6452 // CHECK7-NEXT: [[TMP53:%.*]] = mul nsw i32 1, [[TMP1]] 6453 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP53]] 6454 // CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 6455 // CHECK7-NEXT: [[TMP54:%.*]] = load i16, ptr [[ARRAYIDX5]], align 2 6456 // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP54]] to i32 6457 // CHECK7-NEXT: [[TMP55:%.*]] = load i32, ptr [[B]], align 4 6458 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV]], [[TMP55]] 6459 // CHECK7-NEXT: [[TMP56:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 6460 // CHECK7-NEXT: call void @llvm.stackrestore(ptr [[TMP56]]) 6461 // CHECK7-NEXT: ret i32 [[ADD6]] 6462 // 6463 // 6464 // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici 6465 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 6466 // CHECK7-NEXT: entry: 6467 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6468 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6469 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 6470 // CHECK7-NEXT: [[AAA:%.*]] = alloca i8, align 1 6471 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6472 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6473 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6474 // CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 6475 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 6476 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 6477 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 6478 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 6479 // CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 6480 // CHECK7-NEXT: store i32 0, ptr [[A]], align 4 6481 // CHECK7-NEXT: store i16 0, ptr [[AA]], align 2 6482 // CHECK7-NEXT: store i8 0, ptr [[AAA]], align 1 6483 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 6484 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 6485 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 6486 // CHECK7-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 6487 // CHECK7-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 6488 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 6489 // CHECK7-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1 6490 // CHECK7-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1 6491 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 6492 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 6493 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 6494 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6495 // CHECK7: omp_if.then: 6496 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6497 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 4 6498 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6499 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 4 6500 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6501 // CHECK7-NEXT: store ptr null, ptr [[TMP9]], align 4 6502 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6503 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP10]], align 4 6504 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6505 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP11]], align 4 6506 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6507 // CHECK7-NEXT: store ptr null, ptr [[TMP12]], align 4 6508 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6509 // CHECK7-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 4 6510 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6511 // CHECK7-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 4 6512 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6513 // CHECK7-NEXT: store ptr null, ptr [[TMP15]], align 4 6514 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6515 // CHECK7-NEXT: store ptr [[B]], ptr [[TMP16]], align 4 6516 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6517 // CHECK7-NEXT: store ptr [[B]], ptr [[TMP17]], align 4 6518 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 6519 // CHECK7-NEXT: store ptr null, ptr [[TMP18]], align 4 6520 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6521 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6522 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 6523 // CHECK7-NEXT: store i32 2, ptr [[TMP21]], align 4 6524 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 6525 // CHECK7-NEXT: store i32 4, ptr [[TMP22]], align 4 6526 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 6527 // CHECK7-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4 6528 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 6529 // CHECK7-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4 6530 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 6531 // CHECK7-NEXT: store ptr @.offload_sizes.7, ptr [[TMP25]], align 4 6532 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 6533 // CHECK7-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP26]], align 4 6534 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 6535 // CHECK7-NEXT: store ptr null, ptr [[TMP27]], align 4 6536 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 6537 // CHECK7-NEXT: store ptr null, ptr [[TMP28]], align 4 6538 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 6539 // CHECK7-NEXT: store i64 0, ptr [[TMP29]], align 8 6540 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 6541 // CHECK7-NEXT: store i64 0, ptr [[TMP30]], align 8 6542 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 6543 // CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4 6544 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 6545 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 6546 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 6547 // CHECK7-NEXT: store i32 0, ptr [[TMP33]], align 4 6548 // CHECK7-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, ptr [[KERNEL_ARGS]]) 6549 // CHECK7-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 6550 // CHECK7-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6551 // CHECK7: omp_offload.failed: 6552 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]] 6553 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 6554 // CHECK7: omp_offload.cont: 6555 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6556 // CHECK7: omp_if.else: 6557 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]] 6558 // CHECK7-NEXT: br label [[OMP_IF_END]] 6559 // CHECK7: omp_if.end: 6560 // CHECK7-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 6561 // CHECK7-NEXT: ret i32 [[TMP36]] 6562 // 6563 // 6564 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6565 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 6566 // CHECK7-NEXT: entry: 6567 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6568 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6569 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 6570 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6571 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6572 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6573 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 6574 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 6575 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 6576 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 6577 // CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 6578 // CHECK7-NEXT: store i32 0, ptr [[A]], align 4 6579 // CHECK7-NEXT: store i16 0, ptr [[AA]], align 2 6580 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 6581 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 6582 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 6583 // CHECK7-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 6584 // CHECK7-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 6585 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 6586 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 6587 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 6588 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6589 // CHECK7: omp_if.then: 6590 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6591 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 6592 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6593 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 4 6594 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6595 // CHECK7-NEXT: store ptr null, ptr [[TMP7]], align 4 6596 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6597 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 4 6598 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6599 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP9]], align 4 6600 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6601 // CHECK7-NEXT: store ptr null, ptr [[TMP10]], align 4 6602 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6603 // CHECK7-NEXT: store ptr [[B]], ptr [[TMP11]], align 4 6604 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6605 // CHECK7-NEXT: store ptr [[B]], ptr [[TMP12]], align 4 6606 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6607 // CHECK7-NEXT: store ptr null, ptr [[TMP13]], align 4 6608 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6609 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6610 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 6611 // CHECK7-NEXT: store i32 2, ptr [[TMP16]], align 4 6612 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 6613 // CHECK7-NEXT: store i32 3, ptr [[TMP17]], align 4 6614 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 6615 // CHECK7-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4 6616 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 6617 // CHECK7-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 4 6618 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 6619 // CHECK7-NEXT: store ptr @.offload_sizes.9, ptr [[TMP20]], align 4 6620 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 6621 // CHECK7-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP21]], align 4 6622 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 6623 // CHECK7-NEXT: store ptr null, ptr [[TMP22]], align 4 6624 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 6625 // CHECK7-NEXT: store ptr null, ptr [[TMP23]], align 4 6626 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 6627 // CHECK7-NEXT: store i64 0, ptr [[TMP24]], align 8 6628 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 6629 // CHECK7-NEXT: store i64 0, ptr [[TMP25]], align 8 6630 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 6631 // CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4 6632 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 6633 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 6634 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 6635 // CHECK7-NEXT: store i32 0, ptr [[TMP28]], align 4 6636 // CHECK7-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, ptr [[KERNEL_ARGS]]) 6637 // CHECK7-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 6638 // CHECK7-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6639 // CHECK7: omp_offload.failed: 6640 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] 6641 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 6642 // CHECK7: omp_offload.cont: 6643 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6644 // CHECK7: omp_if.else: 6645 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] 6646 // CHECK7-NEXT: br label [[OMP_IF_END]] 6647 // CHECK7: omp_if.end: 6648 // CHECK7-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 6649 // CHECK7-NEXT: ret i32 [[TMP31]] 6650 // 6651 // 6652 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 6653 // CHECK7-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 6654 // CHECK7-NEXT: entry: 6655 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 6656 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6657 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6658 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6659 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 6660 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6661 // CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6662 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 6663 // CHECK7-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 6664 // CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 6665 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 6666 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 6667 // CHECK7-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 6668 // CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 6669 // CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 6670 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 6671 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 6672 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 6673 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 6674 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 6675 // CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 4 6676 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4 6677 // CHECK7-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 6678 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4 6679 // CHECK7-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 6680 // CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 6681 // CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 6682 // CHECK7-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 6683 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 6684 // CHECK7-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 6685 // CHECK7-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1 6686 // CHECK7-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6687 // CHECK7: omp_if.then: 6688 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) 6689 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6690 // CHECK7: omp_if.else: 6691 // CHECK7-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 6692 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 6693 // CHECK7-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 6694 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) #[[ATTR4]] 6695 // CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 6696 // CHECK7-NEXT: br label [[OMP_IF_END]] 6697 // CHECK7: omp_if.end: 6698 // CHECK7-NEXT: ret void 6699 // 6700 // 6701 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined 6702 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 6703 // CHECK7-NEXT: entry: 6704 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 6705 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 6706 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 6707 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6708 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6709 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6710 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 6711 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6712 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6713 // CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 6714 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6715 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6716 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6717 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6718 // CHECK7-NEXT: [[IT:%.*]] = alloca i64, align 8 6719 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 6720 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 6721 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 6722 // CHECK7-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 6723 // CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 6724 // CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 6725 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 6726 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 6727 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 6728 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 6729 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 6730 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 6731 // CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 6732 // CHECK7-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 6733 // CHECK7-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 6734 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 6735 // CHECK7-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 6736 // CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 6737 // CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6738 // CHECK7: omp_if.then: 6739 // CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6740 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 6741 // CHECK7-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 6742 // CHECK7-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6743 // CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 6744 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6745 // CHECK7: cond.true: 6746 // CHECK7-NEXT: br label [[COND_END:%.*]] 6747 // CHECK7: cond.false: 6748 // CHECK7-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6749 // CHECK7-NEXT: br label [[COND_END]] 6750 // CHECK7: cond.end: 6751 // CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 6752 // CHECK7-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 6753 // CHECK7-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 6754 // CHECK7-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV]], align 8 6755 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6756 // CHECK7: omp.inner.for.cond: 6757 // CHECK7-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39:![0-9]+]] 6758 // CHECK7-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP39]] 6759 // CHECK7-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 6760 // CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6761 // CHECK7: omp.inner.for.body: 6762 // CHECK7-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 6763 // CHECK7-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 6764 // CHECK7-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 6765 // CHECK7-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP39]] 6766 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]] 6767 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double 6768 // CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 6769 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 6770 // CHECK7-NEXT: store double [[ADD]], ptr [[A]], align 4, !nontemporal !40, !llvm.access.group [[ACC_GRP39]] 6771 // CHECK7-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 6772 // CHECK7-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 4, !nontemporal !40, !llvm.access.group [[ACC_GRP39]] 6773 // CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 6774 // CHECK7-NEXT: store double [[INC]], ptr [[A4]], align 4, !nontemporal !40, !llvm.access.group [[ACC_GRP39]] 6775 // CHECK7-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 6776 // CHECK7-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]] 6777 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP15]] 6778 // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 6779 // CHECK7-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP39]] 6780 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6781 // CHECK7: omp.body.continue: 6782 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6783 // CHECK7: omp.inner.for.inc: 6784 // CHECK7-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 6785 // CHECK7-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1 6786 // CHECK7-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 6787 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] 6788 // CHECK7: omp.inner.for.end: 6789 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6790 // CHECK7: omp_if.else: 6791 // CHECK7-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6792 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 6793 // CHECK7-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP18]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 6794 // CHECK7-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6795 // CHECK7-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[TMP19]], 3 6796 // CHECK7-NEXT: br i1 [[CMP8]], label [[COND_TRUE9:%.*]], label [[COND_FALSE10:%.*]] 6797 // CHECK7: cond.true9: 6798 // CHECK7-NEXT: br label [[COND_END11:%.*]] 6799 // CHECK7: cond.false10: 6800 // CHECK7-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6801 // CHECK7-NEXT: br label [[COND_END11]] 6802 // CHECK7: cond.end11: 6803 // CHECK7-NEXT: [[COND12:%.*]] = phi i64 [ 3, [[COND_TRUE9]] ], [ [[TMP20]], [[COND_FALSE10]] ] 6804 // CHECK7-NEXT: store i64 [[COND12]], ptr [[DOTOMP_UB]], align 8 6805 // CHECK7-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 6806 // CHECK7-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV]], align 8 6807 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 6808 // CHECK7: omp.inner.for.cond13: 6809 // CHECK7-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 6810 // CHECK7-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6811 // CHECK7-NEXT: [[CMP14:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 6812 // CHECK7-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END29:%.*]] 6813 // CHECK7: omp.inner.for.body15: 6814 // CHECK7-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 6815 // CHECK7-NEXT: [[MUL16:%.*]] = mul i64 [[TMP24]], 400 6816 // CHECK7-NEXT: [[SUB17:%.*]] = sub i64 2000, [[MUL16]] 6817 // CHECK7-NEXT: store i64 [[SUB17]], ptr [[IT]], align 8 6818 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, ptr [[B_ADDR]], align 4 6819 // CHECK7-NEXT: [[CONV18:%.*]] = sitofp i32 [[TMP25]] to double 6820 // CHECK7-NEXT: [[ADD19:%.*]] = fadd double [[CONV18]], 1.500000e+00 6821 // CHECK7-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 6822 // CHECK7-NEXT: store double [[ADD19]], ptr [[A20]], align 4 6823 // CHECK7-NEXT: [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 6824 // CHECK7-NEXT: [[TMP26:%.*]] = load double, ptr [[A21]], align 4 6825 // CHECK7-NEXT: [[INC22:%.*]] = fadd double [[TMP26]], 1.000000e+00 6826 // CHECK7-NEXT: store double [[INC22]], ptr [[A21]], align 4 6827 // CHECK7-NEXT: [[CONV23:%.*]] = fptosi double [[INC22]] to i16 6828 // CHECK7-NEXT: [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]] 6829 // CHECK7-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP27]] 6830 // CHECK7-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX24]], i32 1 6831 // CHECK7-NEXT: store i16 [[CONV23]], ptr [[ARRAYIDX25]], align 2 6832 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] 6833 // CHECK7: omp.body.continue26: 6834 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] 6835 // CHECK7: omp.inner.for.inc27: 6836 // CHECK7-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 6837 // CHECK7-NEXT: [[ADD28:%.*]] = add i64 [[TMP28]], 1 6838 // CHECK7-NEXT: store i64 [[ADD28]], ptr [[DOTOMP_IV]], align 8 6839 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP43:![0-9]+]] 6840 // CHECK7: omp.inner.for.end29: 6841 // CHECK7-NEXT: br label [[OMP_IF_END]] 6842 // CHECK7: omp_if.end: 6843 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6844 // CHECK7: omp.loop.exit: 6845 // CHECK7-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6846 // CHECK7-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4 6847 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]]) 6848 // CHECK7-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 6849 // CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 6850 // CHECK7-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6851 // CHECK7: .omp.final.then: 6852 // CHECK7-NEXT: store i64 400, ptr [[IT]], align 8 6853 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6854 // CHECK7: .omp.final.done: 6855 // CHECK7-NEXT: ret void 6856 // 6857 // 6858 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 6859 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6860 // CHECK7-NEXT: entry: 6861 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6862 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6863 // CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 6864 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6865 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6866 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6867 // CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 6868 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6869 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 6870 // CHECK7-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 6871 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6872 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 6873 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 6874 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 6875 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 6876 // CHECK7-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 6877 // CHECK7-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 6878 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 6879 // CHECK7-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 6880 // CHECK7-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 6881 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 6882 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]]) 6883 // CHECK7-NEXT: ret void 6884 // 6885 // 6886 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined 6887 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 6888 // CHECK7-NEXT: entry: 6889 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 6890 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 6891 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6892 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6893 // CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 6894 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6895 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6896 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 6897 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 6898 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 6899 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6900 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 6901 // CHECK7-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 6902 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6903 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 6904 // CHECK7-NEXT: ret void 6905 // 6906 // 6907 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 6908 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6909 // CHECK7-NEXT: entry: 6910 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6911 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6912 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6913 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6914 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6915 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6916 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 6917 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6918 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 6919 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 6920 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 6921 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 6922 // CHECK7-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 6923 // CHECK7-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 6924 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 6925 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) 6926 // CHECK7-NEXT: ret void 6927 // 6928 // 6929 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined 6930 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 6931 // CHECK7-NEXT: entry: 6932 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 6933 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 6934 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6935 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6936 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6937 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6938 // CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 6939 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6940 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6941 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6942 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6943 // CHECK7-NEXT: [[I:%.*]] = alloca i64, align 8 6944 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 6945 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 6946 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6947 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 6948 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6949 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 6950 // CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 6951 // CHECK7-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 6952 // CHECK7-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 6953 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 6954 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6955 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 6956 // CHECK7-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 6957 // CHECK7-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6958 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 6959 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6960 // CHECK7: cond.true: 6961 // CHECK7-NEXT: br label [[COND_END:%.*]] 6962 // CHECK7: cond.false: 6963 // CHECK7-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 6964 // CHECK7-NEXT: br label [[COND_END]] 6965 // CHECK7: cond.end: 6966 // CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 6967 // CHECK7-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 6968 // CHECK7-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 6969 // CHECK7-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 6970 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6971 // CHECK7: omp.inner.for.cond: 6972 // CHECK7-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45:![0-9]+]] 6973 // CHECK7-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP45]] 6974 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 6975 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6976 // CHECK7: omp.inner.for.body: 6977 // CHECK7-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45]] 6978 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 6979 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 6980 // CHECK7-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP45]] 6981 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]] 6982 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 6983 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]] 6984 // CHECK7-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]] 6985 // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 6986 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 6987 // CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 6988 // CHECK7-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]] 6989 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 6990 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] 6991 // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 6992 // CHECK7-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] 6993 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6994 // CHECK7: omp.body.continue: 6995 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6996 // CHECK7: omp.inner.for.inc: 6997 // CHECK7-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45]] 6998 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 6999 // CHECK7-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45]] 7000 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] 7001 // CHECK7: omp.inner.for.end: 7002 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7003 // CHECK7: omp.loop.exit: 7004 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 7005 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 7006 // CHECK7-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 7007 // CHECK7-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 7008 // CHECK7: .omp.final.then: 7009 // CHECK7-NEXT: store i64 11, ptr [[I]], align 8 7010 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 7011 // CHECK7: .omp.final.done: 7012 // CHECK7-NEXT: ret void 7013 // 7014 // 7015 // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 7016 // CHECK7-SAME: () #[[ATTR8:[0-9]+]] { 7017 // CHECK7-NEXT: entry: 7018 // CHECK7-NEXT: call void @__tgt_register_requires(i64 1) 7019 // CHECK7-NEXT: ret void 7020 // 7021 // 7022 // CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv 7023 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 7024 // CHECK9-NEXT: entry: 7025 // CHECK9-NEXT: ret i64 0 7026 // 7027 // 7028 // CHECK9-LABEL: define {{[^@]+}}@_Z3fooi 7029 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7030 // CHECK9-NEXT: entry: 7031 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7032 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7033 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 7034 // CHECK9-NEXT: [[B:%.*]] = alloca [10 x float], align 4 7035 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 7036 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7037 // CHECK9-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 7038 // CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 7039 // CHECK9-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 7040 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 7041 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7042 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7043 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7044 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 7045 // CHECK9-NEXT: [[K:%.*]] = alloca i64, align 8 7046 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 7047 // CHECK9-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 7048 // CHECK9-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 7049 // CHECK9-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 7050 // CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 7051 // CHECK9-NEXT: [[I7:%.*]] = alloca i32, align 4 7052 // CHECK9-NEXT: [[K8:%.*]] = alloca i64, align 8 7053 // CHECK9-NEXT: [[LIN:%.*]] = alloca i32, align 4 7054 // CHECK9-NEXT: [[_TMP20:%.*]] = alloca i64, align 8 7055 // CHECK9-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 7056 // CHECK9-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 7057 // CHECK9-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 7058 // CHECK9-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 7059 // CHECK9-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 7060 // CHECK9-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 7061 // CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8 7062 // CHECK9-NEXT: [[LIN27:%.*]] = alloca i32, align 4 7063 // CHECK9-NEXT: [[A28:%.*]] = alloca i32, align 4 7064 // CHECK9-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 7065 // CHECK9-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 7066 // CHECK9-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 7067 // CHECK9-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 7068 // CHECK9-NEXT: [[IT53:%.*]] = alloca i16, align 2 7069 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 7070 // CHECK9-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 7071 // CHECK9-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 7072 // CHECK9-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 7073 // CHECK9-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 7074 // CHECK9-NEXT: [[IT72:%.*]] = alloca i8, align 1 7075 // CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7076 // CHECK9-NEXT: store i32 0, ptr [[A]], align 4 7077 // CHECK9-NEXT: store i16 0, ptr [[AA]], align 2 7078 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 7079 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 7080 // CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() 7081 // CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 7082 // CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 7083 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 7084 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 7085 // CHECK9-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 7086 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 7087 // CHECK9-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 7088 // CHECK9-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 7089 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 7090 // CHECK9-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 7091 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 7092 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 7093 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7094 // CHECK9: omp.inner.for.cond: 7095 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 7096 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 7097 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 7098 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7099 // CHECK9: omp.inner.for.body: 7100 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 7101 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5 7102 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 7103 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 7104 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7105 // CHECK9: omp.body.continue: 7106 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7107 // CHECK9: omp.inner.for.inc: 7108 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 7109 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 7110 // CHECK9-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 7111 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 7112 // CHECK9: omp.inner.for.end: 7113 // CHECK9-NEXT: store i32 33, ptr [[I]], align 4 7114 // CHECK9-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 7115 // CHECK9-NEXT: store i64 [[CALL]], ptr [[K]], align 8 7116 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 4 7117 // CHECK9-NEXT: store i32 8, ptr [[DOTOMP_UB5]], align 4 7118 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 4 7119 // CHECK9-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV6]], align 4 7120 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[K]], align 8 7121 // CHECK9-NEXT: store i64 [[TMP12]], ptr [[DOTLINEAR_START]], align 8 7122 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 7123 // CHECK9: omp.inner.for.cond9: 7124 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 7125 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP6]] 7126 // CHECK9-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 7127 // CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 7128 // CHECK9: omp.inner.for.body11: 7129 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 7130 // CHECK9-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1 7131 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 7132 // CHECK9-NEXT: store i32 [[SUB]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP6]] 7133 // CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP6]] 7134 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 7135 // CHECK9-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3 7136 // CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 7137 // CHECK9-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]] 7138 // CHECK9-NEXT: store i64 [[ADD14]], ptr [[K8]], align 8, !llvm.access.group [[ACC_GRP6]] 7139 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP6]] 7140 // CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 7141 // CHECK9-NEXT: store i32 [[ADD15]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP6]] 7142 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 7143 // CHECK9: omp.body.continue16: 7144 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 7145 // CHECK9: omp.inner.for.inc17: 7146 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 7147 // CHECK9-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 7148 // CHECK9-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 7149 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] 7150 // CHECK9: omp.inner.for.end19: 7151 // CHECK9-NEXT: store i32 1, ptr [[I7]], align 4 7152 // CHECK9-NEXT: [[TMP20:%.*]] = load i64, ptr [[K8]], align 8 7153 // CHECK9-NEXT: store i64 [[TMP20]], ptr [[K]], align 8 7154 // CHECK9-NEXT: store i32 12, ptr [[LIN]], align 4 7155 // CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB21]], align 8 7156 // CHECK9-NEXT: store i64 3, ptr [[DOTOMP_UB22]], align 8 7157 // CHECK9-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB21]], align 8 7158 // CHECK9-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV23]], align 8 7159 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN]], align 4 7160 // CHECK9-NEXT: store i32 [[TMP22]], ptr [[DOTLINEAR_START24]], align 4 7161 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[A]], align 4 7162 // CHECK9-NEXT: store i32 [[TMP23]], ptr [[DOTLINEAR_START25]], align 4 7163 // CHECK9-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 7164 // CHECK9-NEXT: store i64 [[CALL26]], ptr [[DOTLINEAR_STEP]], align 8 7165 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 7166 // CHECK9: omp.inner.for.cond29: 7167 // CHECK9-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9:![0-9]+]] 7168 // CHECK9-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP9]] 7169 // CHECK9-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]] 7170 // CHECK9-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 7171 // CHECK9: omp.inner.for.body31: 7172 // CHECK9-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7173 // CHECK9-NEXT: [[MUL32:%.*]] = mul i64 [[TMP26]], 400 7174 // CHECK9-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 7175 // CHECK9-NEXT: store i64 [[SUB33]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP9]] 7176 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP9]] 7177 // CHECK9-NEXT: [[CONV34:%.*]] = sext i32 [[TMP27]] to i64 7178 // CHECK9-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7179 // CHECK9-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]] 7180 // CHECK9-NEXT: [[MUL35:%.*]] = mul i64 [[TMP28]], [[TMP29]] 7181 // CHECK9-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 7182 // CHECK9-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 7183 // CHECK9-NEXT: store i32 [[CONV37]], ptr [[LIN27]], align 4, !llvm.access.group [[ACC_GRP9]] 7184 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP9]] 7185 // CHECK9-NEXT: [[CONV38:%.*]] = sext i32 [[TMP30]] to i64 7186 // CHECK9-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7187 // CHECK9-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]] 7188 // CHECK9-NEXT: [[MUL39:%.*]] = mul i64 [[TMP31]], [[TMP32]] 7189 // CHECK9-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 7190 // CHECK9-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 7191 // CHECK9-NEXT: store i32 [[CONV41]], ptr [[A28]], align 4, !llvm.access.group [[ACC_GRP9]] 7192 // CHECK9-NEXT: [[TMP33:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]] 7193 // CHECK9-NEXT: [[CONV42:%.*]] = sext i16 [[TMP33]] to i32 7194 // CHECK9-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 7195 // CHECK9-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 7196 // CHECK9-NEXT: store i16 [[CONV44]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]] 7197 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 7198 // CHECK9: omp.body.continue45: 7199 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 7200 // CHECK9: omp.inner.for.inc46: 7201 // CHECK9-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7202 // CHECK9-NEXT: [[ADD47:%.*]] = add i64 [[TMP34]], 1 7203 // CHECK9-NEXT: store i64 [[ADD47]], ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7204 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP10:![0-9]+]] 7205 // CHECK9: omp.inner.for.end48: 7206 // CHECK9-NEXT: store i64 400, ptr [[IT]], align 8 7207 // CHECK9-NEXT: [[TMP35:%.*]] = load i32, ptr [[LIN27]], align 4 7208 // CHECK9-NEXT: store i32 [[TMP35]], ptr [[LIN]], align 4 7209 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[A28]], align 4 7210 // CHECK9-NEXT: store i32 [[TMP36]], ptr [[A]], align 4 7211 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB50]], align 4 7212 // CHECK9-NEXT: store i32 3, ptr [[DOTOMP_UB51]], align 4 7213 // CHECK9-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_LB50]], align 4 7214 // CHECK9-NEXT: store i32 [[TMP37]], ptr [[DOTOMP_IV52]], align 4 7215 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 7216 // CHECK9: omp.inner.for.cond54: 7217 // CHECK9-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 7218 // CHECK9-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP12]] 7219 // CHECK9-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]] 7220 // CHECK9-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 7221 // CHECK9: omp.inner.for.body56: 7222 // CHECK9-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 7223 // CHECK9-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP40]], 4 7224 // CHECK9-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 7225 // CHECK9-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 7226 // CHECK9-NEXT: store i16 [[CONV59]], ptr [[IT53]], align 2, !llvm.access.group [[ACC_GRP12]] 7227 // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]] 7228 // CHECK9-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP41]], 1 7229 // CHECK9-NEXT: store i32 [[ADD60]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]] 7230 // CHECK9-NEXT: [[TMP42:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]] 7231 // CHECK9-NEXT: [[CONV61:%.*]] = sext i16 [[TMP42]] to i32 7232 // CHECK9-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 7233 // CHECK9-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 7234 // CHECK9-NEXT: store i16 [[CONV63]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]] 7235 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 7236 // CHECK9: omp.body.continue64: 7237 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 7238 // CHECK9: omp.inner.for.inc65: 7239 // CHECK9-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 7240 // CHECK9-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP43]], 1 7241 // CHECK9-NEXT: store i32 [[ADD66]], ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 7242 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP13:![0-9]+]] 7243 // CHECK9: omp.inner.for.end67: 7244 // CHECK9-NEXT: store i16 22, ptr [[IT53]], align 2 7245 // CHECK9-NEXT: [[TMP44:%.*]] = load i32, ptr [[A]], align 4 7246 // CHECK9-NEXT: store i32 [[TMP44]], ptr [[DOTCAPTURE_EXPR_]], align 4 7247 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB69]], align 4 7248 // CHECK9-NEXT: store i32 25, ptr [[DOTOMP_UB70]], align 4 7249 // CHECK9-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_LB69]], align 4 7250 // CHECK9-NEXT: store i32 [[TMP45]], ptr [[DOTOMP_IV71]], align 4 7251 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 7252 // CHECK9: omp.inner.for.cond73: 7253 // CHECK9-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] 7254 // CHECK9-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP15]] 7255 // CHECK9-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]] 7256 // CHECK9-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 7257 // CHECK9: omp.inner.for.body75: 7258 // CHECK9-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 7259 // CHECK9-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP48]], 1 7260 // CHECK9-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 7261 // CHECK9-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 7262 // CHECK9-NEXT: store i8 [[CONV78]], ptr [[IT72]], align 1, !llvm.access.group [[ACC_GRP15]] 7263 // CHECK9-NEXT: [[TMP49:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]] 7264 // CHECK9-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP49]], 1 7265 // CHECK9-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]] 7266 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 2 7267 // CHECK9-NEXT: [[TMP50:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] 7268 // CHECK9-NEXT: [[CONV80:%.*]] = fpext float [[TMP50]] to double 7269 // CHECK9-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 7270 // CHECK9-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 7271 // CHECK9-NEXT: store float [[CONV82]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] 7272 // CHECK9-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 3 7273 // CHECK9-NEXT: [[TMP51:%.*]] = load float, ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]] 7274 // CHECK9-NEXT: [[CONV84:%.*]] = fpext float [[TMP51]] to double 7275 // CHECK9-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 7276 // CHECK9-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 7277 // CHECK9-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]] 7278 // CHECK9-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 1 7279 // CHECK9-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i64 0, i64 2 7280 // CHECK9-NEXT: [[TMP52:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] 7281 // CHECK9-NEXT: [[ADD89:%.*]] = fadd double [[TMP52]], 1.000000e+00 7282 // CHECK9-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] 7283 // CHECK9-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP4]] 7284 // CHECK9-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP53]] 7285 // CHECK9-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX90]], i64 3 7286 // CHECK9-NEXT: [[TMP54:%.*]] = load double, ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]] 7287 // CHECK9-NEXT: [[ADD92:%.*]] = fadd double [[TMP54]], 1.000000e+00 7288 // CHECK9-NEXT: store double [[ADD92]], ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]] 7289 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 7290 // CHECK9-NEXT: [[TMP55:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]] 7291 // CHECK9-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP55]], 1 7292 // CHECK9-NEXT: store i64 [[ADD93]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]] 7293 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 7294 // CHECK9-NEXT: [[TMP56:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]] 7295 // CHECK9-NEXT: [[CONV94:%.*]] = sext i8 [[TMP56]] to i32 7296 // CHECK9-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 7297 // CHECK9-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 7298 // CHECK9-NEXT: store i8 [[CONV96]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]] 7299 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 7300 // CHECK9: omp.body.continue97: 7301 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 7302 // CHECK9: omp.inner.for.inc98: 7303 // CHECK9-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 7304 // CHECK9-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 1 7305 // CHECK9-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 7306 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]] 7307 // CHECK9: omp.inner.for.end100: 7308 // CHECK9-NEXT: store i8 96, ptr [[IT72]], align 1 7309 // CHECK9-NEXT: [[TMP58:%.*]] = load i32, ptr [[A]], align 4 7310 // CHECK9-NEXT: [[TMP59:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 7311 // CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP59]]) 7312 // CHECK9-NEXT: ret i32 [[TMP58]] 7313 // 7314 // 7315 // CHECK9-LABEL: define {{[^@]+}}@_Z3bari 7316 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7317 // CHECK9-NEXT: entry: 7318 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7319 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7320 // CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 7321 // CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7322 // CHECK9-NEXT: store i32 0, ptr [[A]], align 4 7323 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 7324 // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 7325 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 7326 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 7327 // CHECK9-NEXT: store i32 [[ADD]], ptr [[A]], align 4 7328 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 7329 // CHECK9-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 7330 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 7331 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 7332 // CHECK9-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 7333 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 7334 // CHECK9-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 7335 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 7336 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 7337 // CHECK9-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 7338 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 7339 // CHECK9-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 7340 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 7341 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 7342 // CHECK9-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 7343 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 7344 // CHECK9-NEXT: ret i32 [[TMP8]] 7345 // 7346 // 7347 // CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 7348 // CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 7349 // CHECK9-NEXT: entry: 7350 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 7351 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7352 // CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 7353 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 7354 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7355 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 7356 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7357 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7358 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7359 // CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8 7360 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 7361 // CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7362 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 7363 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 7364 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7365 // CHECK9-NEXT: store i32 [[ADD]], ptr [[B]], align 4 7366 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 7367 // CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 7368 // CHECK9-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() 7369 // CHECK9-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 7370 // CHECK9-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 7371 // CHECK9-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 7372 // CHECK9-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 7373 // CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 7374 // CHECK9-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 7375 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 7376 // CHECK9-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 7377 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7378 // CHECK9: omp.inner.for.cond: 7379 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]] 7380 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]] 7381 // CHECK9-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP6]], [[TMP7]] 7382 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7383 // CHECK9: omp.inner.for.body: 7384 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 7385 // CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP8]], 400 7386 // CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 7387 // CHECK9-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP18]] 7388 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP18]] 7389 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double 7390 // CHECK9-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 7391 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 7392 // CHECK9-NEXT: store double [[ADD2]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP18]] 7393 // CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 7394 // CHECK9-NEXT: [[TMP10:%.*]] = load double, ptr [[A3]], align 8, !llvm.access.group [[ACC_GRP18]] 7395 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00 7396 // CHECK9-NEXT: store double [[INC]], ptr [[A3]], align 8, !llvm.access.group [[ACC_GRP18]] 7397 // CHECK9-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 7398 // CHECK9-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]] 7399 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP11]] 7400 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 7401 // CHECK9-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2, !llvm.access.group [[ACC_GRP18]] 7402 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7403 // CHECK9: omp.body.continue: 7404 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7405 // CHECK9: omp.inner.for.inc: 7406 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 7407 // CHECK9-NEXT: [[ADD6:%.*]] = add i64 [[TMP12]], 1 7408 // CHECK9-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 7409 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 7410 // CHECK9: omp.inner.for.end: 7411 // CHECK9-NEXT: store i64 400, ptr [[IT]], align 8 7412 // CHECK9-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] 7413 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP13]] 7414 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX7]], i64 1 7415 // CHECK9-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX8]], align 2 7416 // CHECK9-NEXT: [[CONV9:%.*]] = sext i16 [[TMP14]] to i32 7417 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4 7418 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP15]] 7419 // CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 7420 // CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP16]]) 7421 // CHECK9-NEXT: ret i32 [[ADD10]] 7422 // 7423 // 7424 // CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici 7425 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7426 // CHECK9-NEXT: entry: 7427 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7428 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7429 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 7430 // CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 1 7431 // CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7432 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 7433 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7434 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7435 // CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7436 // CHECK9-NEXT: store i32 0, ptr [[A]], align 4 7437 // CHECK9-NEXT: store i16 0, ptr [[AA]], align 2 7438 // CHECK9-NEXT: store i8 0, ptr [[AAA]], align 1 7439 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 7440 // CHECK9-NEXT: store i32 429496720, ptr [[DOTOMP_UB]], align 4 7441 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 7442 // CHECK9-NEXT: ret i32 [[TMP0]] 7443 // 7444 // 7445 // CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 7446 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 7447 // CHECK9-NEXT: entry: 7448 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7449 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7450 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 7451 // CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7452 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 7453 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7454 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7455 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7456 // CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8 7457 // CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7458 // CHECK9-NEXT: store i32 0, ptr [[A]], align 4 7459 // CHECK9-NEXT: store i16 0, ptr [[AA]], align 2 7460 // CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 7461 // CHECK9-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 7462 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 7463 // CHECK9-NEXT: store i64 [[TMP0]], ptr [[DOTOMP_IV]], align 8 7464 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7465 // CHECK9: omp.inner.for.cond: 7466 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21:![0-9]+]] 7467 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP21]] 7468 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 7469 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7470 // CHECK9: omp.inner.for.body: 7471 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21]] 7472 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 7473 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 7474 // CHECK9-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP21]] 7475 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP21]] 7476 // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 7477 // CHECK9-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP21]] 7478 // CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP21]] 7479 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 7480 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 7481 // CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 7482 // CHECK9-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP21]] 7483 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 7484 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] 7485 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 7486 // CHECK9-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] 7487 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7488 // CHECK9: omp.body.continue: 7489 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7490 // CHECK9: omp.inner.for.inc: 7491 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21]] 7492 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 7493 // CHECK9-NEXT: store i64 [[ADD5]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21]] 7494 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 7495 // CHECK9: omp.inner.for.end: 7496 // CHECK9-NEXT: store i64 11, ptr [[I]], align 8 7497 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 7498 // CHECK9-NEXT: ret i32 [[TMP8]] 7499 // 7500 // 7501 // CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv 7502 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 7503 // CHECK11-NEXT: entry: 7504 // CHECK11-NEXT: ret i64 0 7505 // 7506 // 7507 // CHECK11-LABEL: define {{[^@]+}}@_Z3fooi 7508 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 7509 // CHECK11-NEXT: entry: 7510 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7511 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 7512 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 7513 // CHECK11-NEXT: [[B:%.*]] = alloca [10 x float], align 4 7514 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 7515 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 7516 // CHECK11-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 7517 // CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 7518 // CHECK11-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 7519 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 7520 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7521 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7522 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7523 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 7524 // CHECK11-NEXT: [[K:%.*]] = alloca i64, align 8 7525 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 7526 // CHECK11-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 7527 // CHECK11-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 7528 // CHECK11-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 7529 // CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 7530 // CHECK11-NEXT: [[I7:%.*]] = alloca i32, align 4 7531 // CHECK11-NEXT: [[K8:%.*]] = alloca i64, align 8 7532 // CHECK11-NEXT: [[LIN:%.*]] = alloca i32, align 4 7533 // CHECK11-NEXT: [[_TMP20:%.*]] = alloca i64, align 4 7534 // CHECK11-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 7535 // CHECK11-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 7536 // CHECK11-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 7537 // CHECK11-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 7538 // CHECK11-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 7539 // CHECK11-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 7540 // CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8 7541 // CHECK11-NEXT: [[LIN27:%.*]] = alloca i32, align 4 7542 // CHECK11-NEXT: [[A28:%.*]] = alloca i32, align 4 7543 // CHECK11-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 7544 // CHECK11-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 7545 // CHECK11-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 7546 // CHECK11-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 7547 // CHECK11-NEXT: [[IT53:%.*]] = alloca i16, align 2 7548 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 7549 // CHECK11-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 7550 // CHECK11-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 7551 // CHECK11-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 7552 // CHECK11-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 7553 // CHECK11-NEXT: [[IT72:%.*]] = alloca i8, align 1 7554 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7555 // CHECK11-NEXT: store i32 0, ptr [[A]], align 4 7556 // CHECK11-NEXT: store i16 0, ptr [[AA]], align 2 7557 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 7558 // CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() 7559 // CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 7560 // CHECK11-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 7561 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 7562 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 7563 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 7564 // CHECK11-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 7565 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 7566 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 7567 // CHECK11-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 7568 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 7569 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 7570 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7571 // CHECK11: omp.inner.for.cond: 7572 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 7573 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 7574 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 7575 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7576 // CHECK11: omp.inner.for.body: 7577 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 7578 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 7579 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 7580 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 7581 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7582 // CHECK11: omp.body.continue: 7583 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7584 // CHECK11: omp.inner.for.inc: 7585 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 7586 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 7587 // CHECK11-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 7588 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 7589 // CHECK11: omp.inner.for.end: 7590 // CHECK11-NEXT: store i32 33, ptr [[I]], align 4 7591 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 7592 // CHECK11-NEXT: store i64 [[CALL]], ptr [[K]], align 8 7593 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 4 7594 // CHECK11-NEXT: store i32 8, ptr [[DOTOMP_UB5]], align 4 7595 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 4 7596 // CHECK11-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV6]], align 4 7597 // CHECK11-NEXT: [[TMP10:%.*]] = load i64, ptr [[K]], align 8 7598 // CHECK11-NEXT: store i64 [[TMP10]], ptr [[DOTLINEAR_START]], align 8 7599 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 7600 // CHECK11: omp.inner.for.cond9: 7601 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 7602 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP7]] 7603 // CHECK11-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 7604 // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 7605 // CHECK11: omp.inner.for.body11: 7606 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 7607 // CHECK11-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1 7608 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 7609 // CHECK11-NEXT: store i32 [[SUB]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] 7610 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP7]] 7611 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 7612 // CHECK11-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3 7613 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 7614 // CHECK11-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]] 7615 // CHECK11-NEXT: store i64 [[ADD14]], ptr [[K8]], align 8, !llvm.access.group [[ACC_GRP7]] 7616 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP7]] 7617 // CHECK11-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 7618 // CHECK11-NEXT: store i32 [[ADD15]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP7]] 7619 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 7620 // CHECK11: omp.body.continue16: 7621 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 7622 // CHECK11: omp.inner.for.inc17: 7623 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 7624 // CHECK11-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 7625 // CHECK11-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 7626 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]] 7627 // CHECK11: omp.inner.for.end19: 7628 // CHECK11-NEXT: store i32 1, ptr [[I7]], align 4 7629 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, ptr [[K8]], align 8 7630 // CHECK11-NEXT: store i64 [[TMP18]], ptr [[K]], align 8 7631 // CHECK11-NEXT: store i32 12, ptr [[LIN]], align 4 7632 // CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB21]], align 8 7633 // CHECK11-NEXT: store i64 3, ptr [[DOTOMP_UB22]], align 8 7634 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_LB21]], align 8 7635 // CHECK11-NEXT: store i64 [[TMP19]], ptr [[DOTOMP_IV23]], align 8 7636 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN]], align 4 7637 // CHECK11-NEXT: store i32 [[TMP20]], ptr [[DOTLINEAR_START24]], align 4 7638 // CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 4 7639 // CHECK11-NEXT: store i32 [[TMP21]], ptr [[DOTLINEAR_START25]], align 4 7640 // CHECK11-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 7641 // CHECK11-NEXT: store i64 [[CALL26]], ptr [[DOTLINEAR_STEP]], align 8 7642 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 7643 // CHECK11: omp.inner.for.cond29: 7644 // CHECK11-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10:![0-9]+]] 7645 // CHECK11-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP10]] 7646 // CHECK11-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 7647 // CHECK11-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 7648 // CHECK11: omp.inner.for.body31: 7649 // CHECK11-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7650 // CHECK11-NEXT: [[MUL32:%.*]] = mul i64 [[TMP24]], 400 7651 // CHECK11-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 7652 // CHECK11-NEXT: store i64 [[SUB33]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP10]] 7653 // CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP10]] 7654 // CHECK11-NEXT: [[CONV34:%.*]] = sext i32 [[TMP25]] to i64 7655 // CHECK11-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7656 // CHECK11-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]] 7657 // CHECK11-NEXT: [[MUL35:%.*]] = mul i64 [[TMP26]], [[TMP27]] 7658 // CHECK11-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 7659 // CHECK11-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 7660 // CHECK11-NEXT: store i32 [[CONV37]], ptr [[LIN27]], align 4, !llvm.access.group [[ACC_GRP10]] 7661 // CHECK11-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP10]] 7662 // CHECK11-NEXT: [[CONV38:%.*]] = sext i32 [[TMP28]] to i64 7663 // CHECK11-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7664 // CHECK11-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]] 7665 // CHECK11-NEXT: [[MUL39:%.*]] = mul i64 [[TMP29]], [[TMP30]] 7666 // CHECK11-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 7667 // CHECK11-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 7668 // CHECK11-NEXT: store i32 [[CONV41]], ptr [[A28]], align 4, !llvm.access.group [[ACC_GRP10]] 7669 // CHECK11-NEXT: [[TMP31:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]] 7670 // CHECK11-NEXT: [[CONV42:%.*]] = sext i16 [[TMP31]] to i32 7671 // CHECK11-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 7672 // CHECK11-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 7673 // CHECK11-NEXT: store i16 [[CONV44]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]] 7674 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 7675 // CHECK11: omp.body.continue45: 7676 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 7677 // CHECK11: omp.inner.for.inc46: 7678 // CHECK11-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7679 // CHECK11-NEXT: [[ADD47:%.*]] = add i64 [[TMP32]], 1 7680 // CHECK11-NEXT: store i64 [[ADD47]], ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7681 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP11:![0-9]+]] 7682 // CHECK11: omp.inner.for.end48: 7683 // CHECK11-NEXT: store i64 400, ptr [[IT]], align 8 7684 // CHECK11-NEXT: [[TMP33:%.*]] = load i32, ptr [[LIN27]], align 4 7685 // CHECK11-NEXT: store i32 [[TMP33]], ptr [[LIN]], align 4 7686 // CHECK11-NEXT: [[TMP34:%.*]] = load i32, ptr [[A28]], align 4 7687 // CHECK11-NEXT: store i32 [[TMP34]], ptr [[A]], align 4 7688 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB50]], align 4 7689 // CHECK11-NEXT: store i32 3, ptr [[DOTOMP_UB51]], align 4 7690 // CHECK11-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_LB50]], align 4 7691 // CHECK11-NEXT: store i32 [[TMP35]], ptr [[DOTOMP_IV52]], align 4 7692 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 7693 // CHECK11: omp.inner.for.cond54: 7694 // CHECK11-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] 7695 // CHECK11-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP13]] 7696 // CHECK11-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP36]], [[TMP37]] 7697 // CHECK11-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 7698 // CHECK11: omp.inner.for.body56: 7699 // CHECK11-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 7700 // CHECK11-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP38]], 4 7701 // CHECK11-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 7702 // CHECK11-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 7703 // CHECK11-NEXT: store i16 [[CONV59]], ptr [[IT53]], align 2, !llvm.access.group [[ACC_GRP13]] 7704 // CHECK11-NEXT: [[TMP39:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]] 7705 // CHECK11-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP39]], 1 7706 // CHECK11-NEXT: store i32 [[ADD60]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]] 7707 // CHECK11-NEXT: [[TMP40:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]] 7708 // CHECK11-NEXT: [[CONV61:%.*]] = sext i16 [[TMP40]] to i32 7709 // CHECK11-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 7710 // CHECK11-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 7711 // CHECK11-NEXT: store i16 [[CONV63]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]] 7712 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 7713 // CHECK11: omp.body.continue64: 7714 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 7715 // CHECK11: omp.inner.for.inc65: 7716 // CHECK11-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 7717 // CHECK11-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP41]], 1 7718 // CHECK11-NEXT: store i32 [[ADD66]], ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 7719 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP14:![0-9]+]] 7720 // CHECK11: omp.inner.for.end67: 7721 // CHECK11-NEXT: store i16 22, ptr [[IT53]], align 2 7722 // CHECK11-NEXT: [[TMP42:%.*]] = load i32, ptr [[A]], align 4 7723 // CHECK11-NEXT: store i32 [[TMP42]], ptr [[DOTCAPTURE_EXPR_]], align 4 7724 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB69]], align 4 7725 // CHECK11-NEXT: store i32 25, ptr [[DOTOMP_UB70]], align 4 7726 // CHECK11-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_LB69]], align 4 7727 // CHECK11-NEXT: store i32 [[TMP43]], ptr [[DOTOMP_IV71]], align 4 7728 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 7729 // CHECK11: omp.inner.for.cond73: 7730 // CHECK11-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] 7731 // CHECK11-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP16]] 7732 // CHECK11-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP44]], [[TMP45]] 7733 // CHECK11-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 7734 // CHECK11: omp.inner.for.body75: 7735 // CHECK11-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 7736 // CHECK11-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP46]], 1 7737 // CHECK11-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 7738 // CHECK11-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 7739 // CHECK11-NEXT: store i8 [[CONV78]], ptr [[IT72]], align 1, !llvm.access.group [[ACC_GRP16]] 7740 // CHECK11-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] 7741 // CHECK11-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP47]], 1 7742 // CHECK11-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] 7743 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 2 7744 // CHECK11-NEXT: [[TMP48:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] 7745 // CHECK11-NEXT: [[CONV80:%.*]] = fpext float [[TMP48]] to double 7746 // CHECK11-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 7747 // CHECK11-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 7748 // CHECK11-NEXT: store float [[CONV82]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] 7749 // CHECK11-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 3 7750 // CHECK11-NEXT: [[TMP49:%.*]] = load float, ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]] 7751 // CHECK11-NEXT: [[CONV84:%.*]] = fpext float [[TMP49]] to double 7752 // CHECK11-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 7753 // CHECK11-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 7754 // CHECK11-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]] 7755 // CHECK11-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 1 7756 // CHECK11-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i32 0, i32 2 7757 // CHECK11-NEXT: [[TMP50:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] 7758 // CHECK11-NEXT: [[ADD89:%.*]] = fadd double [[TMP50]], 1.000000e+00 7759 // CHECK11-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] 7760 // CHECK11-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP2]] 7761 // CHECK11-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP51]] 7762 // CHECK11-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX90]], i32 3 7763 // CHECK11-NEXT: [[TMP52:%.*]] = load double, ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]] 7764 // CHECK11-NEXT: [[ADD92:%.*]] = fadd double [[TMP52]], 1.000000e+00 7765 // CHECK11-NEXT: store double [[ADD92]], ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]] 7766 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 7767 // CHECK11-NEXT: [[TMP53:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]] 7768 // CHECK11-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP53]], 1 7769 // CHECK11-NEXT: store i64 [[ADD93]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]] 7770 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 7771 // CHECK11-NEXT: [[TMP54:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]] 7772 // CHECK11-NEXT: [[CONV94:%.*]] = sext i8 [[TMP54]] to i32 7773 // CHECK11-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 7774 // CHECK11-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 7775 // CHECK11-NEXT: store i8 [[CONV96]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]] 7776 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 7777 // CHECK11: omp.body.continue97: 7778 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 7779 // CHECK11: omp.inner.for.inc98: 7780 // CHECK11-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 7781 // CHECK11-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 1 7782 // CHECK11-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 7783 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]] 7784 // CHECK11: omp.inner.for.end100: 7785 // CHECK11-NEXT: store i8 96, ptr [[IT72]], align 1 7786 // CHECK11-NEXT: [[TMP56:%.*]] = load i32, ptr [[A]], align 4 7787 // CHECK11-NEXT: [[TMP57:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 7788 // CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP57]]) 7789 // CHECK11-NEXT: ret i32 [[TMP56]] 7790 // 7791 // 7792 // CHECK11-LABEL: define {{[^@]+}}@_Z3bari 7793 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 7794 // CHECK11-NEXT: entry: 7795 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7796 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 7797 // CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 7798 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7799 // CHECK11-NEXT: store i32 0, ptr [[A]], align 4 7800 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 7801 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 7802 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 7803 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 7804 // CHECK11-NEXT: store i32 [[ADD]], ptr [[A]], align 4 7805 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 7806 // CHECK11-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 7807 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 7808 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 7809 // CHECK11-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 7810 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 7811 // CHECK11-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 7812 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 7813 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 7814 // CHECK11-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 7815 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 7816 // CHECK11-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 7817 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 7818 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 7819 // CHECK11-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 7820 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 7821 // CHECK11-NEXT: ret i32 [[TMP8]] 7822 // 7823 // 7824 // CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 7825 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 7826 // CHECK11-NEXT: entry: 7827 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 7828 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7829 // CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 7830 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 7831 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 7832 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4 7833 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7834 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7835 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7836 // CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8 7837 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 7838 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7839 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 7840 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 7841 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7842 // CHECK11-NEXT: store i32 [[ADD]], ptr [[B]], align 4 7843 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 7844 // CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() 7845 // CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 7846 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 7847 // CHECK11-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 7848 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 7849 // CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 7850 // CHECK11-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 7851 // CHECK11-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 7852 // CHECK11-NEXT: store i64 [[TMP4]], ptr [[DOTOMP_IV]], align 8 7853 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7854 // CHECK11: omp.inner.for.cond: 7855 // CHECK11-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19:![0-9]+]] 7856 // CHECK11-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP19]] 7857 // CHECK11-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP5]], [[TMP6]] 7858 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7859 // CHECK11: omp.inner.for.body: 7860 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 7861 // CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP7]], 400 7862 // CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 7863 // CHECK11-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP19]] 7864 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP19]] 7865 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double 7866 // CHECK11-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 7867 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 7868 // CHECK11-NEXT: store double [[ADD2]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP19]] 7869 // CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 7870 // CHECK11-NEXT: [[TMP9:%.*]] = load double, ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP19]] 7871 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 7872 // CHECK11-NEXT: store double [[INC]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP19]] 7873 // CHECK11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 7874 // CHECK11-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]] 7875 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP10]] 7876 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 7877 // CHECK11-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2, !llvm.access.group [[ACC_GRP19]] 7878 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7879 // CHECK11: omp.body.continue: 7880 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7881 // CHECK11: omp.inner.for.inc: 7882 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 7883 // CHECK11-NEXT: [[ADD6:%.*]] = add i64 [[TMP11]], 1 7884 // CHECK11-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 7885 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 7886 // CHECK11: omp.inner.for.end: 7887 // CHECK11-NEXT: store i64 400, ptr [[IT]], align 8 7888 // CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] 7889 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP12]] 7890 // CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX7]], i32 1 7891 // CHECK11-NEXT: [[TMP13:%.*]] = load i16, ptr [[ARRAYIDX8]], align 2 7892 // CHECK11-NEXT: [[CONV9:%.*]] = sext i16 [[TMP13]] to i32 7893 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[B]], align 4 7894 // CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP14]] 7895 // CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 7896 // CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) 7897 // CHECK11-NEXT: ret i32 [[ADD10]] 7898 // 7899 // 7900 // CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici 7901 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 7902 // CHECK11-NEXT: entry: 7903 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7904 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 7905 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 7906 // CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 1 7907 // CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7908 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 7909 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7910 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7911 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7912 // CHECK11-NEXT: store i32 0, ptr [[A]], align 4 7913 // CHECK11-NEXT: store i16 0, ptr [[AA]], align 2 7914 // CHECK11-NEXT: store i8 0, ptr [[AAA]], align 1 7915 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 7916 // CHECK11-NEXT: store i32 429496720, ptr [[DOTOMP_UB]], align 4 7917 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 7918 // CHECK11-NEXT: ret i32 [[TMP0]] 7919 // 7920 // 7921 // CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 7922 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 7923 // CHECK11-NEXT: entry: 7924 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7925 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 7926 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 7927 // CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7928 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4 7929 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7930 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7931 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7932 // CHECK11-NEXT: [[I:%.*]] = alloca i64, align 8 7933 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 7934 // CHECK11-NEXT: store i32 0, ptr [[A]], align 4 7935 // CHECK11-NEXT: store i16 0, ptr [[AA]], align 2 7936 // CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 7937 // CHECK11-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 7938 // CHECK11-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 7939 // CHECK11-NEXT: store i64 [[TMP0]], ptr [[DOTOMP_IV]], align 8 7940 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7941 // CHECK11: omp.inner.for.cond: 7942 // CHECK11-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22:![0-9]+]] 7943 // CHECK11-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP22]] 7944 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 7945 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7946 // CHECK11: omp.inner.for.body: 7947 // CHECK11-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22]] 7948 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 7949 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 7950 // CHECK11-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP22]] 7951 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP22]] 7952 // CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 7953 // CHECK11-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP22]] 7954 // CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP22]] 7955 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 7956 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 7957 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 7958 // CHECK11-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP22]] 7959 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 7960 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] 7961 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 7962 // CHECK11-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] 7963 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7964 // CHECK11: omp.body.continue: 7965 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7966 // CHECK11: omp.inner.for.inc: 7967 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22]] 7968 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 7969 // CHECK11-NEXT: store i64 [[ADD5]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22]] 7970 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] 7971 // CHECK11: omp.inner.for.end: 7972 // CHECK11-NEXT: store i64 11, ptr [[I]], align 8 7973 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 7974 // CHECK11-NEXT: ret i32 [[TMP8]] 7975 // 7976 // 7977 // CHECK13-LABEL: define {{[^@]+}}@_Z7get_valv 7978 // CHECK13-SAME: () #[[ATTR0:[0-9]+]] { 7979 // CHECK13-NEXT: entry: 7980 // CHECK13-NEXT: ret i64 0 7981 // 7982 // 7983 // CHECK13-LABEL: define {{[^@]+}}@_Z3fooi 7984 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7985 // CHECK13-NEXT: entry: 7986 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7987 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 7988 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 7989 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x float], align 4 7990 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 7991 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7992 // CHECK13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 7993 // CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 7994 // CHECK13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 7995 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 7996 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7997 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7998 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7999 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 8000 // CHECK13-NEXT: [[K:%.*]] = alloca i64, align 8 8001 // CHECK13-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 8002 // CHECK13-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 8003 // CHECK13-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 8004 // CHECK13-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 8005 // CHECK13-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 8006 // CHECK13-NEXT: [[I7:%.*]] = alloca i32, align 4 8007 // CHECK13-NEXT: [[K8:%.*]] = alloca i64, align 8 8008 // CHECK13-NEXT: [[LIN:%.*]] = alloca i32, align 4 8009 // CHECK13-NEXT: [[_TMP20:%.*]] = alloca i64, align 8 8010 // CHECK13-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 8011 // CHECK13-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 8012 // CHECK13-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 8013 // CHECK13-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 8014 // CHECK13-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 8015 // CHECK13-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 8016 // CHECK13-NEXT: [[IT:%.*]] = alloca i64, align 8 8017 // CHECK13-NEXT: [[LIN27:%.*]] = alloca i32, align 4 8018 // CHECK13-NEXT: [[A28:%.*]] = alloca i32, align 4 8019 // CHECK13-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 8020 // CHECK13-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 8021 // CHECK13-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 8022 // CHECK13-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 8023 // CHECK13-NEXT: [[IT53:%.*]] = alloca i16, align 2 8024 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 8025 // CHECK13-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 8026 // CHECK13-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 8027 // CHECK13-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 8028 // CHECK13-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 8029 // CHECK13-NEXT: [[IT72:%.*]] = alloca i8, align 1 8030 // CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8031 // CHECK13-NEXT: store i32 0, ptr [[A]], align 4 8032 // CHECK13-NEXT: store i16 0, ptr [[AA]], align 2 8033 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 8034 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 8035 // CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() 8036 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 8037 // CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 8038 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 8039 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 8040 // CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 8041 // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 8042 // CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 8043 // CHECK13-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 8044 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 8045 // CHECK13-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 8046 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 8047 // CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 8048 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8049 // CHECK13: omp.inner.for.cond: 8050 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 8051 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 8052 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 8053 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8054 // CHECK13: omp.inner.for.body: 8055 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 8056 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5 8057 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 8058 // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 8059 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8060 // CHECK13: omp.body.continue: 8061 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8062 // CHECK13: omp.inner.for.inc: 8063 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 8064 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 8065 // CHECK13-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 8066 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 8067 // CHECK13: omp.inner.for.end: 8068 // CHECK13-NEXT: store i32 33, ptr [[I]], align 4 8069 // CHECK13-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 8070 // CHECK13-NEXT: store i64 [[CALL]], ptr [[K]], align 8 8071 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 4 8072 // CHECK13-NEXT: store i32 8, ptr [[DOTOMP_UB5]], align 4 8073 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 4 8074 // CHECK13-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV6]], align 4 8075 // CHECK13-NEXT: [[TMP12:%.*]] = load i64, ptr [[K]], align 8 8076 // CHECK13-NEXT: store i64 [[TMP12]], ptr [[DOTLINEAR_START]], align 8 8077 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 8078 // CHECK13: omp.inner.for.cond9: 8079 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 8080 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP6]] 8081 // CHECK13-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 8082 // CHECK13-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 8083 // CHECK13: omp.inner.for.body11: 8084 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 8085 // CHECK13-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1 8086 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 8087 // CHECK13-NEXT: store i32 [[SUB]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP6]] 8088 // CHECK13-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP6]] 8089 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 8090 // CHECK13-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3 8091 // CHECK13-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 8092 // CHECK13-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]] 8093 // CHECK13-NEXT: store i64 [[ADD14]], ptr [[K8]], align 8, !llvm.access.group [[ACC_GRP6]] 8094 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP6]] 8095 // CHECK13-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 8096 // CHECK13-NEXT: store i32 [[ADD15]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP6]] 8097 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 8098 // CHECK13: omp.body.continue16: 8099 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 8100 // CHECK13: omp.inner.for.inc17: 8101 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 8102 // CHECK13-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 8103 // CHECK13-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 8104 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] 8105 // CHECK13: omp.inner.for.end19: 8106 // CHECK13-NEXT: store i32 1, ptr [[I7]], align 4 8107 // CHECK13-NEXT: [[TMP20:%.*]] = load i64, ptr [[K8]], align 8 8108 // CHECK13-NEXT: store i64 [[TMP20]], ptr [[K]], align 8 8109 // CHECK13-NEXT: store i32 12, ptr [[LIN]], align 4 8110 // CHECK13-NEXT: store i64 0, ptr [[DOTOMP_LB21]], align 8 8111 // CHECK13-NEXT: store i64 3, ptr [[DOTOMP_UB22]], align 8 8112 // CHECK13-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB21]], align 8 8113 // CHECK13-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV23]], align 8 8114 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN]], align 4 8115 // CHECK13-NEXT: store i32 [[TMP22]], ptr [[DOTLINEAR_START24]], align 4 8116 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, ptr [[A]], align 4 8117 // CHECK13-NEXT: store i32 [[TMP23]], ptr [[DOTLINEAR_START25]], align 4 8118 // CHECK13-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 8119 // CHECK13-NEXT: store i64 [[CALL26]], ptr [[DOTLINEAR_STEP]], align 8 8120 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 8121 // CHECK13: omp.inner.for.cond29: 8122 // CHECK13-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9:![0-9]+]] 8123 // CHECK13-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP9]] 8124 // CHECK13-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]] 8125 // CHECK13-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 8126 // CHECK13: omp.inner.for.body31: 8127 // CHECK13-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 8128 // CHECK13-NEXT: [[MUL32:%.*]] = mul i64 [[TMP26]], 400 8129 // CHECK13-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 8130 // CHECK13-NEXT: store i64 [[SUB33]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP9]] 8131 // CHECK13-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP9]] 8132 // CHECK13-NEXT: [[CONV34:%.*]] = sext i32 [[TMP27]] to i64 8133 // CHECK13-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 8134 // CHECK13-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]] 8135 // CHECK13-NEXT: [[MUL35:%.*]] = mul i64 [[TMP28]], [[TMP29]] 8136 // CHECK13-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 8137 // CHECK13-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 8138 // CHECK13-NEXT: store i32 [[CONV37]], ptr [[LIN27]], align 4, !llvm.access.group [[ACC_GRP9]] 8139 // CHECK13-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP9]] 8140 // CHECK13-NEXT: [[CONV38:%.*]] = sext i32 [[TMP30]] to i64 8141 // CHECK13-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 8142 // CHECK13-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]] 8143 // CHECK13-NEXT: [[MUL39:%.*]] = mul i64 [[TMP31]], [[TMP32]] 8144 // CHECK13-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 8145 // CHECK13-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 8146 // CHECK13-NEXT: store i32 [[CONV41]], ptr [[A28]], align 4, !llvm.access.group [[ACC_GRP9]] 8147 // CHECK13-NEXT: [[TMP33:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]] 8148 // CHECK13-NEXT: [[CONV42:%.*]] = sext i16 [[TMP33]] to i32 8149 // CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 8150 // CHECK13-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 8151 // CHECK13-NEXT: store i16 [[CONV44]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]] 8152 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 8153 // CHECK13: omp.body.continue45: 8154 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 8155 // CHECK13: omp.inner.for.inc46: 8156 // CHECK13-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 8157 // CHECK13-NEXT: [[ADD47:%.*]] = add i64 [[TMP34]], 1 8158 // CHECK13-NEXT: store i64 [[ADD47]], ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 8159 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP10:![0-9]+]] 8160 // CHECK13: omp.inner.for.end48: 8161 // CHECK13-NEXT: store i64 400, ptr [[IT]], align 8 8162 // CHECK13-NEXT: [[TMP35:%.*]] = load i32, ptr [[LIN27]], align 4 8163 // CHECK13-NEXT: store i32 [[TMP35]], ptr [[LIN]], align 4 8164 // CHECK13-NEXT: [[TMP36:%.*]] = load i32, ptr [[A28]], align 4 8165 // CHECK13-NEXT: store i32 [[TMP36]], ptr [[A]], align 4 8166 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB50]], align 4 8167 // CHECK13-NEXT: store i32 3, ptr [[DOTOMP_UB51]], align 4 8168 // CHECK13-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_LB50]], align 4 8169 // CHECK13-NEXT: store i32 [[TMP37]], ptr [[DOTOMP_IV52]], align 4 8170 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 8171 // CHECK13: omp.inner.for.cond54: 8172 // CHECK13-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 8173 // CHECK13-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP12]] 8174 // CHECK13-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]] 8175 // CHECK13-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 8176 // CHECK13: omp.inner.for.body56: 8177 // CHECK13-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 8178 // CHECK13-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP40]], 4 8179 // CHECK13-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 8180 // CHECK13-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 8181 // CHECK13-NEXT: store i16 [[CONV59]], ptr [[IT53]], align 2, !llvm.access.group [[ACC_GRP12]] 8182 // CHECK13-NEXT: [[TMP41:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]] 8183 // CHECK13-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP41]], 1 8184 // CHECK13-NEXT: store i32 [[ADD60]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]] 8185 // CHECK13-NEXT: [[TMP42:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]] 8186 // CHECK13-NEXT: [[CONV61:%.*]] = sext i16 [[TMP42]] to i32 8187 // CHECK13-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 8188 // CHECK13-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 8189 // CHECK13-NEXT: store i16 [[CONV63]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]] 8190 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 8191 // CHECK13: omp.body.continue64: 8192 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 8193 // CHECK13: omp.inner.for.inc65: 8194 // CHECK13-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 8195 // CHECK13-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP43]], 1 8196 // CHECK13-NEXT: store i32 [[ADD66]], ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 8197 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP13:![0-9]+]] 8198 // CHECK13: omp.inner.for.end67: 8199 // CHECK13-NEXT: store i16 22, ptr [[IT53]], align 2 8200 // CHECK13-NEXT: [[TMP44:%.*]] = load i32, ptr [[A]], align 4 8201 // CHECK13-NEXT: store i32 [[TMP44]], ptr [[DOTCAPTURE_EXPR_]], align 4 8202 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB69]], align 4 8203 // CHECK13-NEXT: store i32 25, ptr [[DOTOMP_UB70]], align 4 8204 // CHECK13-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_LB69]], align 4 8205 // CHECK13-NEXT: store i32 [[TMP45]], ptr [[DOTOMP_IV71]], align 4 8206 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 8207 // CHECK13: omp.inner.for.cond73: 8208 // CHECK13-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] 8209 // CHECK13-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP15]] 8210 // CHECK13-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]] 8211 // CHECK13-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 8212 // CHECK13: omp.inner.for.body75: 8213 // CHECK13-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 8214 // CHECK13-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP48]], 1 8215 // CHECK13-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 8216 // CHECK13-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 8217 // CHECK13-NEXT: store i8 [[CONV78]], ptr [[IT72]], align 1, !llvm.access.group [[ACC_GRP15]] 8218 // CHECK13-NEXT: [[TMP49:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]] 8219 // CHECK13-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP49]], 1 8220 // CHECK13-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]] 8221 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 2 8222 // CHECK13-NEXT: [[TMP50:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] 8223 // CHECK13-NEXT: [[CONV80:%.*]] = fpext float [[TMP50]] to double 8224 // CHECK13-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 8225 // CHECK13-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 8226 // CHECK13-NEXT: store float [[CONV82]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] 8227 // CHECK13-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 3 8228 // CHECK13-NEXT: [[TMP51:%.*]] = load float, ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]] 8229 // CHECK13-NEXT: [[CONV84:%.*]] = fpext float [[TMP51]] to double 8230 // CHECK13-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 8231 // CHECK13-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 8232 // CHECK13-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]] 8233 // CHECK13-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 1 8234 // CHECK13-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i64 0, i64 2 8235 // CHECK13-NEXT: [[TMP52:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] 8236 // CHECK13-NEXT: [[ADD89:%.*]] = fadd double [[TMP52]], 1.000000e+00 8237 // CHECK13-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] 8238 // CHECK13-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP4]] 8239 // CHECK13-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP53]] 8240 // CHECK13-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX90]], i64 3 8241 // CHECK13-NEXT: [[TMP54:%.*]] = load double, ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]] 8242 // CHECK13-NEXT: [[ADD92:%.*]] = fadd double [[TMP54]], 1.000000e+00 8243 // CHECK13-NEXT: store double [[ADD92]], ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]] 8244 // CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 8245 // CHECK13-NEXT: [[TMP55:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]] 8246 // CHECK13-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP55]], 1 8247 // CHECK13-NEXT: store i64 [[ADD93]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]] 8248 // CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 8249 // CHECK13-NEXT: [[TMP56:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]] 8250 // CHECK13-NEXT: [[CONV94:%.*]] = sext i8 [[TMP56]] to i32 8251 // CHECK13-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 8252 // CHECK13-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 8253 // CHECK13-NEXT: store i8 [[CONV96]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]] 8254 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 8255 // CHECK13: omp.body.continue97: 8256 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 8257 // CHECK13: omp.inner.for.inc98: 8258 // CHECK13-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 8259 // CHECK13-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 1 8260 // CHECK13-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 8261 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]] 8262 // CHECK13: omp.inner.for.end100: 8263 // CHECK13-NEXT: store i8 96, ptr [[IT72]], align 1 8264 // CHECK13-NEXT: [[TMP58:%.*]] = load i32, ptr [[A]], align 4 8265 // CHECK13-NEXT: [[TMP59:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 8266 // CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP59]]) 8267 // CHECK13-NEXT: ret i32 [[TMP58]] 8268 // 8269 // 8270 // CHECK13-LABEL: define {{[^@]+}}@_Z3bari 8271 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 8272 // CHECK13-NEXT: entry: 8273 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8274 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8275 // CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 8276 // CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8277 // CHECK13-NEXT: store i32 0, ptr [[A]], align 4 8278 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 8279 // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 8280 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 8281 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 8282 // CHECK13-NEXT: store i32 [[ADD]], ptr [[A]], align 4 8283 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 8284 // CHECK13-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 8285 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 8286 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 8287 // CHECK13-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 8288 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 8289 // CHECK13-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 8290 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 8291 // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 8292 // CHECK13-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 8293 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 8294 // CHECK13-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 8295 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 8296 // CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 8297 // CHECK13-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 8298 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 8299 // CHECK13-NEXT: ret i32 [[TMP8]] 8300 // 8301 // 8302 // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 8303 // CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 8304 // CHECK13-NEXT: entry: 8305 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 8306 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8307 // CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 8308 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 8309 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 8310 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 8311 // CHECK13-NEXT: [[TMP:%.*]] = alloca i64, align 8 8312 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8313 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8314 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8315 // CHECK13-NEXT: [[IT:%.*]] = alloca i64, align 8 8316 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 8317 // CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8318 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 8319 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 8320 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8321 // CHECK13-NEXT: store i32 [[ADD]], ptr [[B]], align 4 8322 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 8323 // CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 8324 // CHECK13-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() 8325 // CHECK13-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 8326 // CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 8327 // CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 8328 // CHECK13-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 8329 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 8330 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 8331 // CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 8332 // CHECK13-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 8333 // CHECK13-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 8334 // CHECK13-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 8335 // CHECK13-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 8336 // CHECK13-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 8337 // CHECK13-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 8338 // CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 8339 // CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8340 // CHECK13: omp_if.then: 8341 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8342 // CHECK13: omp.inner.for.cond: 8343 // CHECK13-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]] 8344 // CHECK13-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]] 8345 // CHECK13-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP8]], [[TMP9]] 8346 // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8347 // CHECK13: omp.inner.for.body: 8348 // CHECK13-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 8349 // CHECK13-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 400 8350 // CHECK13-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 8351 // CHECK13-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP18]] 8352 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP18]] 8353 // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP11]] to double 8354 // CHECK13-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 8355 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 8356 // CHECK13-NEXT: store double [[ADD3]], ptr [[A]], align 8, !nontemporal !19, !llvm.access.group [[ACC_GRP18]] 8357 // CHECK13-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 8358 // CHECK13-NEXT: [[TMP12:%.*]] = load double, ptr [[A4]], align 8, !nontemporal !19, !llvm.access.group [[ACC_GRP18]] 8359 // CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00 8360 // CHECK13-NEXT: store double [[INC]], ptr [[A4]], align 8, !nontemporal !19, !llvm.access.group [[ACC_GRP18]] 8361 // CHECK13-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 8362 // CHECK13-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] 8363 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP13]] 8364 // CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 8365 // CHECK13-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP18]] 8366 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8367 // CHECK13: omp.body.continue: 8368 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8369 // CHECK13: omp.inner.for.inc: 8370 // CHECK13-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 8371 // CHECK13-NEXT: [[ADD7:%.*]] = add i64 [[TMP14]], 1 8372 // CHECK13-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 8373 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 8374 // CHECK13: omp.inner.for.end: 8375 // CHECK13-NEXT: br label [[OMP_IF_END:%.*]] 8376 // CHECK13: omp_if.else: 8377 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]] 8378 // CHECK13: omp.inner.for.cond8: 8379 // CHECK13-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 8380 // CHECK13-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 8381 // CHECK13-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP15]], [[TMP16]] 8382 // CHECK13-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]] 8383 // CHECK13: omp.inner.for.body10: 8384 // CHECK13-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 8385 // CHECK13-NEXT: [[MUL11:%.*]] = mul i64 [[TMP17]], 400 8386 // CHECK13-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]] 8387 // CHECK13-NEXT: store i64 [[SUB12]], ptr [[IT]], align 8 8388 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[B]], align 4 8389 // CHECK13-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP18]] to double 8390 // CHECK13-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00 8391 // CHECK13-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 8392 // CHECK13-NEXT: store double [[ADD14]], ptr [[A15]], align 8 8393 // CHECK13-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 8394 // CHECK13-NEXT: [[TMP19:%.*]] = load double, ptr [[A16]], align 8 8395 // CHECK13-NEXT: [[INC17:%.*]] = fadd double [[TMP19]], 1.000000e+00 8396 // CHECK13-NEXT: store double [[INC17]], ptr [[A16]], align 8 8397 // CHECK13-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16 8398 // CHECK13-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]] 8399 // CHECK13-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP20]] 8400 // CHECK13-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX19]], i64 1 8401 // CHECK13-NEXT: store i16 [[CONV18]], ptr [[ARRAYIDX20]], align 2 8402 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]] 8403 // CHECK13: omp.body.continue21: 8404 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]] 8405 // CHECK13: omp.inner.for.inc22: 8406 // CHECK13-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 8407 // CHECK13-NEXT: [[ADD23:%.*]] = add i64 [[TMP21]], 1 8408 // CHECK13-NEXT: store i64 [[ADD23]], ptr [[DOTOMP_IV]], align 8 8409 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP22:![0-9]+]] 8410 // CHECK13: omp.inner.for.end24: 8411 // CHECK13-NEXT: br label [[OMP_IF_END]] 8412 // CHECK13: omp_if.end: 8413 // CHECK13-NEXT: store i64 400, ptr [[IT]], align 8 8414 // CHECK13-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]] 8415 // CHECK13-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP22]] 8416 // CHECK13-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX25]], i64 1 8417 // CHECK13-NEXT: [[TMP23:%.*]] = load i16, ptr [[ARRAYIDX26]], align 2 8418 // CHECK13-NEXT: [[CONV27:%.*]] = sext i16 [[TMP23]] to i32 8419 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, ptr [[B]], align 4 8420 // CHECK13-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP24]] 8421 // CHECK13-NEXT: [[TMP25:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 8422 // CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP25]]) 8423 // CHECK13-NEXT: ret i32 [[ADD28]] 8424 // 8425 // 8426 // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici 8427 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 8428 // CHECK13-NEXT: entry: 8429 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8430 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8431 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 8432 // CHECK13-NEXT: [[AAA:%.*]] = alloca i8, align 1 8433 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8434 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 8435 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8436 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8437 // CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8438 // CHECK13-NEXT: store i32 0, ptr [[A]], align 4 8439 // CHECK13-NEXT: store i16 0, ptr [[AA]], align 2 8440 // CHECK13-NEXT: store i8 0, ptr [[AAA]], align 1 8441 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 8442 // CHECK13-NEXT: store i32 429496720, ptr [[DOTOMP_UB]], align 4 8443 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 8444 // CHECK13-NEXT: ret i32 [[TMP0]] 8445 // 8446 // 8447 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 8448 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 8449 // CHECK13-NEXT: entry: 8450 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8451 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8452 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 8453 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8454 // CHECK13-NEXT: [[TMP:%.*]] = alloca i64, align 8 8455 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8456 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8457 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8458 // CHECK13-NEXT: [[I:%.*]] = alloca i64, align 8 8459 // CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8460 // CHECK13-NEXT: store i32 0, ptr [[A]], align 4 8461 // CHECK13-NEXT: store i16 0, ptr [[AA]], align 2 8462 // CHECK13-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 8463 // CHECK13-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 8464 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 8465 // CHECK13-NEXT: store i64 [[TMP0]], ptr [[DOTOMP_IV]], align 8 8466 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8467 // CHECK13: omp.inner.for.cond: 8468 // CHECK13-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24:![0-9]+]] 8469 // CHECK13-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP24]] 8470 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 8471 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8472 // CHECK13: omp.inner.for.body: 8473 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24]] 8474 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 8475 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 8476 // CHECK13-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP24]] 8477 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP24]] 8478 // CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 8479 // CHECK13-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP24]] 8480 // CHECK13-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP24]] 8481 // CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 8482 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 8483 // CHECK13-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 8484 // CHECK13-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP24]] 8485 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 8486 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 8487 // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 8488 // CHECK13-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 8489 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8490 // CHECK13: omp.body.continue: 8491 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8492 // CHECK13: omp.inner.for.inc: 8493 // CHECK13-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24]] 8494 // CHECK13-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 8495 // CHECK13-NEXT: store i64 [[ADD5]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24]] 8496 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 8497 // CHECK13: omp.inner.for.end: 8498 // CHECK13-NEXT: store i64 11, ptr [[I]], align 8 8499 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 8500 // CHECK13-NEXT: ret i32 [[TMP8]] 8501 // 8502 // 8503 // CHECK15-LABEL: define {{[^@]+}}@_Z7get_valv 8504 // CHECK15-SAME: () #[[ATTR0:[0-9]+]] { 8505 // CHECK15-NEXT: entry: 8506 // CHECK15-NEXT: ret i64 0 8507 // 8508 // 8509 // CHECK15-LABEL: define {{[^@]+}}@_Z3fooi 8510 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 8511 // CHECK15-NEXT: entry: 8512 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8513 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 8514 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 8515 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x float], align 4 8516 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 8517 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 8518 // CHECK15-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 8519 // CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 8520 // CHECK15-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 8521 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 8522 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8523 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8524 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8525 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 8526 // CHECK15-NEXT: [[K:%.*]] = alloca i64, align 8 8527 // CHECK15-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 8528 // CHECK15-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 8529 // CHECK15-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 8530 // CHECK15-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 8531 // CHECK15-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 8532 // CHECK15-NEXT: [[I7:%.*]] = alloca i32, align 4 8533 // CHECK15-NEXT: [[K8:%.*]] = alloca i64, align 8 8534 // CHECK15-NEXT: [[LIN:%.*]] = alloca i32, align 4 8535 // CHECK15-NEXT: [[_TMP20:%.*]] = alloca i64, align 4 8536 // CHECK15-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 8537 // CHECK15-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 8538 // CHECK15-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 8539 // CHECK15-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 8540 // CHECK15-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 8541 // CHECK15-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 8542 // CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 8 8543 // CHECK15-NEXT: [[LIN27:%.*]] = alloca i32, align 4 8544 // CHECK15-NEXT: [[A28:%.*]] = alloca i32, align 4 8545 // CHECK15-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 8546 // CHECK15-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 8547 // CHECK15-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 8548 // CHECK15-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 8549 // CHECK15-NEXT: [[IT53:%.*]] = alloca i16, align 2 8550 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 8551 // CHECK15-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 8552 // CHECK15-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 8553 // CHECK15-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 8554 // CHECK15-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 8555 // CHECK15-NEXT: [[IT72:%.*]] = alloca i8, align 1 8556 // CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8557 // CHECK15-NEXT: store i32 0, ptr [[A]], align 4 8558 // CHECK15-NEXT: store i16 0, ptr [[AA]], align 2 8559 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 8560 // CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() 8561 // CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 8562 // CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 8563 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 8564 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 8565 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 8566 // CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 8567 // CHECK15-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 8568 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 8569 // CHECK15-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 8570 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 8571 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 8572 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8573 // CHECK15: omp.inner.for.cond: 8574 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 8575 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 8576 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 8577 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8578 // CHECK15: omp.inner.for.body: 8579 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 8580 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 8581 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 8582 // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 8583 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8584 // CHECK15: omp.body.continue: 8585 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8586 // CHECK15: omp.inner.for.inc: 8587 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 8588 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 8589 // CHECK15-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 8590 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 8591 // CHECK15: omp.inner.for.end: 8592 // CHECK15-NEXT: store i32 33, ptr [[I]], align 4 8593 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 8594 // CHECK15-NEXT: store i64 [[CALL]], ptr [[K]], align 8 8595 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 4 8596 // CHECK15-NEXT: store i32 8, ptr [[DOTOMP_UB5]], align 4 8597 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 4 8598 // CHECK15-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV6]], align 4 8599 // CHECK15-NEXT: [[TMP10:%.*]] = load i64, ptr [[K]], align 8 8600 // CHECK15-NEXT: store i64 [[TMP10]], ptr [[DOTLINEAR_START]], align 8 8601 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 8602 // CHECK15: omp.inner.for.cond9: 8603 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 8604 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP7]] 8605 // CHECK15-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 8606 // CHECK15-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 8607 // CHECK15: omp.inner.for.body11: 8608 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 8609 // CHECK15-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1 8610 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 8611 // CHECK15-NEXT: store i32 [[SUB]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] 8612 // CHECK15-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP7]] 8613 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 8614 // CHECK15-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3 8615 // CHECK15-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 8616 // CHECK15-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]] 8617 // CHECK15-NEXT: store i64 [[ADD14]], ptr [[K8]], align 8, !llvm.access.group [[ACC_GRP7]] 8618 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP7]] 8619 // CHECK15-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 8620 // CHECK15-NEXT: store i32 [[ADD15]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP7]] 8621 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 8622 // CHECK15: omp.body.continue16: 8623 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 8624 // CHECK15: omp.inner.for.inc17: 8625 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 8626 // CHECK15-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 8627 // CHECK15-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 8628 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]] 8629 // CHECK15: omp.inner.for.end19: 8630 // CHECK15-NEXT: store i32 1, ptr [[I7]], align 4 8631 // CHECK15-NEXT: [[TMP18:%.*]] = load i64, ptr [[K8]], align 8 8632 // CHECK15-NEXT: store i64 [[TMP18]], ptr [[K]], align 8 8633 // CHECK15-NEXT: store i32 12, ptr [[LIN]], align 4 8634 // CHECK15-NEXT: store i64 0, ptr [[DOTOMP_LB21]], align 8 8635 // CHECK15-NEXT: store i64 3, ptr [[DOTOMP_UB22]], align 8 8636 // CHECK15-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_LB21]], align 8 8637 // CHECK15-NEXT: store i64 [[TMP19]], ptr [[DOTOMP_IV23]], align 8 8638 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN]], align 4 8639 // CHECK15-NEXT: store i32 [[TMP20]], ptr [[DOTLINEAR_START24]], align 4 8640 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 4 8641 // CHECK15-NEXT: store i32 [[TMP21]], ptr [[DOTLINEAR_START25]], align 4 8642 // CHECK15-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 8643 // CHECK15-NEXT: store i64 [[CALL26]], ptr [[DOTLINEAR_STEP]], align 8 8644 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 8645 // CHECK15: omp.inner.for.cond29: 8646 // CHECK15-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10:![0-9]+]] 8647 // CHECK15-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP10]] 8648 // CHECK15-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 8649 // CHECK15-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 8650 // CHECK15: omp.inner.for.body31: 8651 // CHECK15-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8652 // CHECK15-NEXT: [[MUL32:%.*]] = mul i64 [[TMP24]], 400 8653 // CHECK15-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 8654 // CHECK15-NEXT: store i64 [[SUB33]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP10]] 8655 // CHECK15-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP10]] 8656 // CHECK15-NEXT: [[CONV34:%.*]] = sext i32 [[TMP25]] to i64 8657 // CHECK15-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8658 // CHECK15-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]] 8659 // CHECK15-NEXT: [[MUL35:%.*]] = mul i64 [[TMP26]], [[TMP27]] 8660 // CHECK15-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 8661 // CHECK15-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 8662 // CHECK15-NEXT: store i32 [[CONV37]], ptr [[LIN27]], align 4, !llvm.access.group [[ACC_GRP10]] 8663 // CHECK15-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP10]] 8664 // CHECK15-NEXT: [[CONV38:%.*]] = sext i32 [[TMP28]] to i64 8665 // CHECK15-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8666 // CHECK15-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]] 8667 // CHECK15-NEXT: [[MUL39:%.*]] = mul i64 [[TMP29]], [[TMP30]] 8668 // CHECK15-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 8669 // CHECK15-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 8670 // CHECK15-NEXT: store i32 [[CONV41]], ptr [[A28]], align 4, !llvm.access.group [[ACC_GRP10]] 8671 // CHECK15-NEXT: [[TMP31:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]] 8672 // CHECK15-NEXT: [[CONV42:%.*]] = sext i16 [[TMP31]] to i32 8673 // CHECK15-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 8674 // CHECK15-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 8675 // CHECK15-NEXT: store i16 [[CONV44]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]] 8676 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 8677 // CHECK15: omp.body.continue45: 8678 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 8679 // CHECK15: omp.inner.for.inc46: 8680 // CHECK15-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8681 // CHECK15-NEXT: [[ADD47:%.*]] = add i64 [[TMP32]], 1 8682 // CHECK15-NEXT: store i64 [[ADD47]], ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8683 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP11:![0-9]+]] 8684 // CHECK15: omp.inner.for.end48: 8685 // CHECK15-NEXT: store i64 400, ptr [[IT]], align 8 8686 // CHECK15-NEXT: [[TMP33:%.*]] = load i32, ptr [[LIN27]], align 4 8687 // CHECK15-NEXT: store i32 [[TMP33]], ptr [[LIN]], align 4 8688 // CHECK15-NEXT: [[TMP34:%.*]] = load i32, ptr [[A28]], align 4 8689 // CHECK15-NEXT: store i32 [[TMP34]], ptr [[A]], align 4 8690 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB50]], align 4 8691 // CHECK15-NEXT: store i32 3, ptr [[DOTOMP_UB51]], align 4 8692 // CHECK15-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_LB50]], align 4 8693 // CHECK15-NEXT: store i32 [[TMP35]], ptr [[DOTOMP_IV52]], align 4 8694 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 8695 // CHECK15: omp.inner.for.cond54: 8696 // CHECK15-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] 8697 // CHECK15-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP13]] 8698 // CHECK15-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP36]], [[TMP37]] 8699 // CHECK15-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 8700 // CHECK15: omp.inner.for.body56: 8701 // CHECK15-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 8702 // CHECK15-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP38]], 4 8703 // CHECK15-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 8704 // CHECK15-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 8705 // CHECK15-NEXT: store i16 [[CONV59]], ptr [[IT53]], align 2, !llvm.access.group [[ACC_GRP13]] 8706 // CHECK15-NEXT: [[TMP39:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]] 8707 // CHECK15-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP39]], 1 8708 // CHECK15-NEXT: store i32 [[ADD60]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]] 8709 // CHECK15-NEXT: [[TMP40:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]] 8710 // CHECK15-NEXT: [[CONV61:%.*]] = sext i16 [[TMP40]] to i32 8711 // CHECK15-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 8712 // CHECK15-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 8713 // CHECK15-NEXT: store i16 [[CONV63]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]] 8714 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 8715 // CHECK15: omp.body.continue64: 8716 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 8717 // CHECK15: omp.inner.for.inc65: 8718 // CHECK15-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 8719 // CHECK15-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP41]], 1 8720 // CHECK15-NEXT: store i32 [[ADD66]], ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 8721 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP14:![0-9]+]] 8722 // CHECK15: omp.inner.for.end67: 8723 // CHECK15-NEXT: store i16 22, ptr [[IT53]], align 2 8724 // CHECK15-NEXT: [[TMP42:%.*]] = load i32, ptr [[A]], align 4 8725 // CHECK15-NEXT: store i32 [[TMP42]], ptr [[DOTCAPTURE_EXPR_]], align 4 8726 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB69]], align 4 8727 // CHECK15-NEXT: store i32 25, ptr [[DOTOMP_UB70]], align 4 8728 // CHECK15-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_LB69]], align 4 8729 // CHECK15-NEXT: store i32 [[TMP43]], ptr [[DOTOMP_IV71]], align 4 8730 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 8731 // CHECK15: omp.inner.for.cond73: 8732 // CHECK15-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] 8733 // CHECK15-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP16]] 8734 // CHECK15-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP44]], [[TMP45]] 8735 // CHECK15-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 8736 // CHECK15: omp.inner.for.body75: 8737 // CHECK15-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 8738 // CHECK15-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP46]], 1 8739 // CHECK15-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 8740 // CHECK15-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 8741 // CHECK15-NEXT: store i8 [[CONV78]], ptr [[IT72]], align 1, !llvm.access.group [[ACC_GRP16]] 8742 // CHECK15-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] 8743 // CHECK15-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP47]], 1 8744 // CHECK15-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] 8745 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 2 8746 // CHECK15-NEXT: [[TMP48:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] 8747 // CHECK15-NEXT: [[CONV80:%.*]] = fpext float [[TMP48]] to double 8748 // CHECK15-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 8749 // CHECK15-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 8750 // CHECK15-NEXT: store float [[CONV82]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] 8751 // CHECK15-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 3 8752 // CHECK15-NEXT: [[TMP49:%.*]] = load float, ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]] 8753 // CHECK15-NEXT: [[CONV84:%.*]] = fpext float [[TMP49]] to double 8754 // CHECK15-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 8755 // CHECK15-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 8756 // CHECK15-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]] 8757 // CHECK15-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 1 8758 // CHECK15-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i32 0, i32 2 8759 // CHECK15-NEXT: [[TMP50:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] 8760 // CHECK15-NEXT: [[ADD89:%.*]] = fadd double [[TMP50]], 1.000000e+00 8761 // CHECK15-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] 8762 // CHECK15-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP2]] 8763 // CHECK15-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP51]] 8764 // CHECK15-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX90]], i32 3 8765 // CHECK15-NEXT: [[TMP52:%.*]] = load double, ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]] 8766 // CHECK15-NEXT: [[ADD92:%.*]] = fadd double [[TMP52]], 1.000000e+00 8767 // CHECK15-NEXT: store double [[ADD92]], ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]] 8768 // CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 8769 // CHECK15-NEXT: [[TMP53:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]] 8770 // CHECK15-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP53]], 1 8771 // CHECK15-NEXT: store i64 [[ADD93]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]] 8772 // CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 8773 // CHECK15-NEXT: [[TMP54:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]] 8774 // CHECK15-NEXT: [[CONV94:%.*]] = sext i8 [[TMP54]] to i32 8775 // CHECK15-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 8776 // CHECK15-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 8777 // CHECK15-NEXT: store i8 [[CONV96]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]] 8778 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 8779 // CHECK15: omp.body.continue97: 8780 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 8781 // CHECK15: omp.inner.for.inc98: 8782 // CHECK15-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 8783 // CHECK15-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 1 8784 // CHECK15-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 8785 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]] 8786 // CHECK15: omp.inner.for.end100: 8787 // CHECK15-NEXT: store i8 96, ptr [[IT72]], align 1 8788 // CHECK15-NEXT: [[TMP56:%.*]] = load i32, ptr [[A]], align 4 8789 // CHECK15-NEXT: [[TMP57:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 8790 // CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP57]]) 8791 // CHECK15-NEXT: ret i32 [[TMP56]] 8792 // 8793 // 8794 // CHECK15-LABEL: define {{[^@]+}}@_Z3bari 8795 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 8796 // CHECK15-NEXT: entry: 8797 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8798 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 8799 // CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 8800 // CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8801 // CHECK15-NEXT: store i32 0, ptr [[A]], align 4 8802 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 8803 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 8804 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 8805 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 8806 // CHECK15-NEXT: store i32 [[ADD]], ptr [[A]], align 4 8807 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 8808 // CHECK15-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 8809 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 8810 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 8811 // CHECK15-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 8812 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 8813 // CHECK15-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 8814 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 8815 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 8816 // CHECK15-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 8817 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 8818 // CHECK15-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 8819 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 8820 // CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 8821 // CHECK15-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 8822 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 8823 // CHECK15-NEXT: ret i32 [[TMP8]] 8824 // 8825 // 8826 // CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 8827 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 8828 // CHECK15-NEXT: entry: 8829 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 8830 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8831 // CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 8832 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 8833 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 8834 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 8835 // CHECK15-NEXT: [[TMP:%.*]] = alloca i64, align 4 8836 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8837 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8838 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8839 // CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 8 8840 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 8841 // CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8842 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 8843 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 8844 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8845 // CHECK15-NEXT: store i32 [[ADD]], ptr [[B]], align 4 8846 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 8847 // CHECK15-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() 8848 // CHECK15-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 8849 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 8850 // CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 8851 // CHECK15-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 8852 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 8853 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 8854 // CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 8855 // CHECK15-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 8856 // CHECK15-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 8857 // CHECK15-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 8858 // CHECK15-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 8859 // CHECK15-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 8860 // CHECK15-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 8861 // CHECK15-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 8862 // CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8863 // CHECK15: omp_if.then: 8864 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8865 // CHECK15: omp.inner.for.cond: 8866 // CHECK15-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19:![0-9]+]] 8867 // CHECK15-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP19]] 8868 // CHECK15-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 8869 // CHECK15-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8870 // CHECK15: omp.inner.for.body: 8871 // CHECK15-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 8872 // CHECK15-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 8873 // CHECK15-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 8874 // CHECK15-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP19]] 8875 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP19]] 8876 // CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double 8877 // CHECK15-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 8878 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 8879 // CHECK15-NEXT: store double [[ADD3]], ptr [[A]], align 4, !nontemporal !20, !llvm.access.group [[ACC_GRP19]] 8880 // CHECK15-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 8881 // CHECK15-NEXT: [[TMP11:%.*]] = load double, ptr [[A4]], align 4, !nontemporal !20, !llvm.access.group [[ACC_GRP19]] 8882 // CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 8883 // CHECK15-NEXT: store double [[INC]], ptr [[A4]], align 4, !nontemporal !20, !llvm.access.group [[ACC_GRP19]] 8884 // CHECK15-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 8885 // CHECK15-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] 8886 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP12]] 8887 // CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 8888 // CHECK15-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP19]] 8889 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8890 // CHECK15: omp.body.continue: 8891 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8892 // CHECK15: omp.inner.for.inc: 8893 // CHECK15-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 8894 // CHECK15-NEXT: [[ADD7:%.*]] = add i64 [[TMP13]], 1 8895 // CHECK15-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 8896 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 8897 // CHECK15: omp.inner.for.end: 8898 // CHECK15-NEXT: br label [[OMP_IF_END:%.*]] 8899 // CHECK15: omp_if.else: 8900 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]] 8901 // CHECK15: omp.inner.for.cond8: 8902 // CHECK15-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 8903 // CHECK15-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 8904 // CHECK15-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP14]], [[TMP15]] 8905 // CHECK15-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]] 8906 // CHECK15: omp.inner.for.body10: 8907 // CHECK15-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 8908 // CHECK15-NEXT: [[MUL11:%.*]] = mul i64 [[TMP16]], 400 8909 // CHECK15-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]] 8910 // CHECK15-NEXT: store i64 [[SUB12]], ptr [[IT]], align 8 8911 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[B]], align 4 8912 // CHECK15-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP17]] to double 8913 // CHECK15-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00 8914 // CHECK15-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 8915 // CHECK15-NEXT: store double [[ADD14]], ptr [[A15]], align 4 8916 // CHECK15-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 8917 // CHECK15-NEXT: [[TMP18:%.*]] = load double, ptr [[A16]], align 4 8918 // CHECK15-NEXT: [[INC17:%.*]] = fadd double [[TMP18]], 1.000000e+00 8919 // CHECK15-NEXT: store double [[INC17]], ptr [[A16]], align 4 8920 // CHECK15-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16 8921 // CHECK15-NEXT: [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]] 8922 // CHECK15-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP19]] 8923 // CHECK15-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX19]], i32 1 8924 // CHECK15-NEXT: store i16 [[CONV18]], ptr [[ARRAYIDX20]], align 2 8925 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]] 8926 // CHECK15: omp.body.continue21: 8927 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]] 8928 // CHECK15: omp.inner.for.inc22: 8929 // CHECK15-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 8930 // CHECK15-NEXT: [[ADD23:%.*]] = add i64 [[TMP20]], 1 8931 // CHECK15-NEXT: store i64 [[ADD23]], ptr [[DOTOMP_IV]], align 8 8932 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP23:![0-9]+]] 8933 // CHECK15: omp.inner.for.end24: 8934 // CHECK15-NEXT: br label [[OMP_IF_END]] 8935 // CHECK15: omp_if.end: 8936 // CHECK15-NEXT: store i64 400, ptr [[IT]], align 8 8937 // CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]] 8938 // CHECK15-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP21]] 8939 // CHECK15-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX25]], i32 1 8940 // CHECK15-NEXT: [[TMP22:%.*]] = load i16, ptr [[ARRAYIDX26]], align 2 8941 // CHECK15-NEXT: [[CONV27:%.*]] = sext i16 [[TMP22]] to i32 8942 // CHECK15-NEXT: [[TMP23:%.*]] = load i32, ptr [[B]], align 4 8943 // CHECK15-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP23]] 8944 // CHECK15-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 8945 // CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP24]]) 8946 // CHECK15-NEXT: ret i32 [[ADD28]] 8947 // 8948 // 8949 // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici 8950 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 8951 // CHECK15-NEXT: entry: 8952 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8953 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 8954 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 8955 // CHECK15-NEXT: [[AAA:%.*]] = alloca i8, align 1 8956 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8957 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 8958 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8959 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8960 // CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8961 // CHECK15-NEXT: store i32 0, ptr [[A]], align 4 8962 // CHECK15-NEXT: store i16 0, ptr [[AA]], align 2 8963 // CHECK15-NEXT: store i8 0, ptr [[AAA]], align 1 8964 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 8965 // CHECK15-NEXT: store i32 429496720, ptr [[DOTOMP_UB]], align 4 8966 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 8967 // CHECK15-NEXT: ret i32 [[TMP0]] 8968 // 8969 // 8970 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 8971 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 8972 // CHECK15-NEXT: entry: 8973 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8974 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 8975 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 8976 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8977 // CHECK15-NEXT: [[TMP:%.*]] = alloca i64, align 4 8978 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8979 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8980 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8981 // CHECK15-NEXT: [[I:%.*]] = alloca i64, align 8 8982 // CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 8983 // CHECK15-NEXT: store i32 0, ptr [[A]], align 4 8984 // CHECK15-NEXT: store i16 0, ptr [[AA]], align 2 8985 // CHECK15-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 8986 // CHECK15-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 8987 // CHECK15-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 8988 // CHECK15-NEXT: store i64 [[TMP0]], ptr [[DOTOMP_IV]], align 8 8989 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8990 // CHECK15: omp.inner.for.cond: 8991 // CHECK15-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25:![0-9]+]] 8992 // CHECK15-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP25]] 8993 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 8994 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8995 // CHECK15: omp.inner.for.body: 8996 // CHECK15-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25]] 8997 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 8998 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 8999 // CHECK15-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP25]] 9000 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP25]] 9001 // CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 9002 // CHECK15-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP25]] 9003 // CHECK15-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP25]] 9004 // CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 9005 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 9006 // CHECK15-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 9007 // CHECK15-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP25]] 9008 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 9009 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] 9010 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 9011 // CHECK15-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] 9012 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9013 // CHECK15: omp.body.continue: 9014 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9015 // CHECK15: omp.inner.for.inc: 9016 // CHECK15-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25]] 9017 // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 9018 // CHECK15-NEXT: store i64 [[ADD5]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25]] 9019 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] 9020 // CHECK15: omp.inner.for.end: 9021 // CHECK15-NEXT: store i64 11, ptr [[I]], align 8 9022 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 9023 // CHECK15-NEXT: ret i32 [[TMP8]] 9024 // 9025 // 9026 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 9027 // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { 9028 // CHECK17-NEXT: entry: 9029 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) 9030 // CHECK17-NEXT: ret void 9031 // 9032 // 9033 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined 9034 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 9035 // CHECK17-NEXT: entry: 9036 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 9037 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 9038 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9039 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 9040 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9041 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9042 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9043 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9044 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 9045 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 9046 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 9047 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 9048 // CHECK17-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 9049 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 9050 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9051 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 9052 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 9053 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 9054 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9055 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 9056 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9057 // CHECK17: cond.true: 9058 // CHECK17-NEXT: br label [[COND_END:%.*]] 9059 // CHECK17: cond.false: 9060 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9061 // CHECK17-NEXT: br label [[COND_END]] 9062 // CHECK17: cond.end: 9063 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9064 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 9065 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 9066 // CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 9067 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9068 // CHECK17: omp.inner.for.cond: 9069 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 9070 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 9071 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9072 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9073 // CHECK17: omp.inner.for.body: 9074 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 9075 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 9076 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 9077 // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 9078 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9079 // CHECK17: omp.body.continue: 9080 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9081 // CHECK17: omp.inner.for.inc: 9082 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 9083 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 9084 // CHECK17-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 9085 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 9086 // CHECK17: omp.inner.for.end: 9087 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9088 // CHECK17: omp.loop.exit: 9089 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 9090 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9091 // CHECK17-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 9092 // CHECK17-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9093 // CHECK17: .omp.final.then: 9094 // CHECK17-NEXT: store i32 33, ptr [[I]], align 4 9095 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9096 // CHECK17: .omp.final.done: 9097 // CHECK17-NEXT: ret void 9098 // 9099 // 9100 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 9101 // CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 9102 // CHECK17-NEXT: entry: 9103 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9104 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 9105 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9106 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9107 // CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 9108 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9109 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9110 // CHECK17-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 9111 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9112 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 9113 // CHECK17-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 9114 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 9115 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 9116 // CHECK17-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 9117 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 9118 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 9119 // CHECK17-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 9120 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8 9121 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 9122 // CHECK17-NEXT: ret void 9123 // 9124 // 9125 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined 9126 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 9127 // CHECK17-NEXT: entry: 9128 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 9129 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 9130 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9131 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 9132 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9133 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9134 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 9135 // CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 9136 // CHECK17-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 9137 // CHECK17-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 9138 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9139 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9140 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9141 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9142 // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 9143 // CHECK17-NEXT: [[LIN2:%.*]] = alloca i32, align 4 9144 // CHECK17-NEXT: [[A3:%.*]] = alloca i32, align 4 9145 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 9146 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 9147 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9148 // CHECK17-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 9149 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9150 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 9151 // CHECK17-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 9152 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 9153 // CHECK17-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 9154 // CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 9155 // CHECK17-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 9156 // CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 9157 // CHECK17-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 9158 // CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 9159 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9160 // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 9161 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 9162 // CHECK17-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 9163 // CHECK17-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 9164 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9165 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 9166 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9167 // CHECK17: cond.true: 9168 // CHECK17-NEXT: br label [[COND_END:%.*]] 9169 // CHECK17: cond.false: 9170 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9171 // CHECK17-NEXT: br label [[COND_END]] 9172 // CHECK17: cond.end: 9173 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 9174 // CHECK17-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 9175 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 9176 // CHECK17-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 9177 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9178 // CHECK17: omp.inner.for.cond: 9179 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17:![0-9]+]] 9180 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP17]] 9181 // CHECK17-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 9182 // CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9183 // CHECK17: omp.inner.for.body: 9184 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 9185 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 9186 // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 9187 // CHECK17-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP17]] 9188 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP17]] 9189 // CHECK17-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 9190 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 9191 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]] 9192 // CHECK17-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 9193 // CHECK17-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 9194 // CHECK17-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 9195 // CHECK17-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP17]] 9196 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP17]] 9197 // CHECK17-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 9198 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 9199 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]] 9200 // CHECK17-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 9201 // CHECK17-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 9202 // CHECK17-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 9203 // CHECK17-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP17]] 9204 // CHECK17-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP17]] 9205 // CHECK17-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 9206 // CHECK17-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 9207 // CHECK17-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 9208 // CHECK17-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP17]] 9209 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9210 // CHECK17: omp.body.continue: 9211 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9212 // CHECK17: omp.inner.for.inc: 9213 // CHECK17-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 9214 // CHECK17-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 9215 // CHECK17-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 9216 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 9217 // CHECK17: omp.inner.for.end: 9218 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9219 // CHECK17: omp.loop.exit: 9220 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 9221 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9222 // CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 9223 // CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9224 // CHECK17: .omp.final.then: 9225 // CHECK17-NEXT: store i64 400, ptr [[IT]], align 8 9226 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9227 // CHECK17: .omp.final.done: 9228 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9229 // CHECK17-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 9230 // CHECK17-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 9231 // CHECK17: .omp.linear.pu: 9232 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 9233 // CHECK17-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 9234 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 9235 // CHECK17-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 9236 // CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 9237 // CHECK17: .omp.linear.pu.done: 9238 // CHECK17-NEXT: ret void 9239 // 9240 // 9241 // CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv 9242 // CHECK17-SAME: () #[[ATTR3:[0-9]+]] { 9243 // CHECK17-NEXT: entry: 9244 // CHECK17-NEXT: ret i64 0 9245 // 9246 // 9247 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 9248 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 9249 // CHECK17-NEXT: entry: 9250 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9251 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9252 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9253 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9254 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9255 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9256 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 9257 // CHECK17-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 9258 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 9259 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 9260 // CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 9261 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 9262 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) 9263 // CHECK17-NEXT: ret void 9264 // 9265 // 9266 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined 9267 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 9268 // CHECK17-NEXT: entry: 9269 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 9270 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 9271 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9272 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9273 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9274 // CHECK17-NEXT: [[TMP:%.*]] = alloca i16, align 2 9275 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9276 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9277 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9278 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9279 // CHECK17-NEXT: [[IT:%.*]] = alloca i16, align 2 9280 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 9281 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 9282 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9283 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9284 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 9285 // CHECK17-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 9286 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 9287 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9288 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 9289 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 9290 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 9291 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9292 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 9293 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9294 // CHECK17: cond.true: 9295 // CHECK17-NEXT: br label [[COND_END:%.*]] 9296 // CHECK17: cond.false: 9297 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9298 // CHECK17-NEXT: br label [[COND_END]] 9299 // CHECK17: cond.end: 9300 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9301 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 9302 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 9303 // CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 9304 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9305 // CHECK17: omp.inner.for.cond: 9306 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] 9307 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] 9308 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9309 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9310 // CHECK17: omp.inner.for.body: 9311 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 9312 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 9313 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 9314 // CHECK17-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 9315 // CHECK17-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP20]] 9316 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]] 9317 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 9318 // CHECK17-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]] 9319 // CHECK17-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP20]] 9320 // CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 9321 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 9322 // CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 9323 // CHECK17-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP20]] 9324 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9325 // CHECK17: omp.body.continue: 9326 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9327 // CHECK17: omp.inner.for.inc: 9328 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 9329 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 9330 // CHECK17-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 9331 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 9332 // CHECK17: omp.inner.for.end: 9333 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9334 // CHECK17: omp.loop.exit: 9335 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 9336 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9337 // CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 9338 // CHECK17-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9339 // CHECK17: .omp.final.then: 9340 // CHECK17-NEXT: store i16 22, ptr [[IT]], align 2 9341 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9342 // CHECK17: .omp.final.done: 9343 // CHECK17-NEXT: ret void 9344 // 9345 // 9346 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 9347 // CHECK17-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 9348 // CHECK17-NEXT: entry: 9349 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9350 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 9351 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9352 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 9353 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 9354 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9355 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 9356 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 9357 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 9358 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 9359 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9360 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 9361 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9362 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 9363 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 9364 // CHECK17-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 9365 // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 9366 // CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 9367 // CHECK17-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 9368 // CHECK17-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 9369 // CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 9370 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 9371 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 9372 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 9373 // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 9374 // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 9375 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 9376 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 9377 // CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 9378 // CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 9379 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 9380 // CHECK17-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 9381 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 9382 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 9383 // CHECK17-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 9384 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 9385 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]]) 9386 // CHECK17-NEXT: ret void 9387 // 9388 // 9389 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined 9390 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 9391 // CHECK17-NEXT: entry: 9392 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 9393 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 9394 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9395 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 9396 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9397 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 9398 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 9399 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9400 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 9401 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 9402 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 9403 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 9404 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9405 // CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1 9406 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9407 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9408 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9409 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9410 // CHECK17-NEXT: [[IT:%.*]] = alloca i8, align 1 9411 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 9412 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 9413 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9414 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 9415 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 9416 // CHECK17-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 9417 // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 9418 // CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 9419 // CHECK17-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 9420 // CHECK17-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 9421 // CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 9422 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 9423 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 9424 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 9425 // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 9426 // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 9427 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 9428 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 9429 // CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 9430 // CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 9431 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 9432 // CHECK17-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 9433 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 9434 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9435 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 9436 // CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 9437 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 9438 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 9439 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 9440 // CHECK17: omp.dispatch.cond: 9441 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9442 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 9443 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9444 // CHECK17: cond.true: 9445 // CHECK17-NEXT: br label [[COND_END:%.*]] 9446 // CHECK17: cond.false: 9447 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9448 // CHECK17-NEXT: br label [[COND_END]] 9449 // CHECK17: cond.end: 9450 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 9451 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 9452 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 9453 // CHECK17-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 9454 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 9455 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9456 // CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 9457 // CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 9458 // CHECK17: omp.dispatch.body: 9459 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9460 // CHECK17: omp.inner.for.cond: 9461 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] 9462 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] 9463 // CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 9464 // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9465 // CHECK17: omp.inner.for.body: 9466 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 9467 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 9468 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 9469 // CHECK17-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 9470 // CHECK17-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP23]] 9471 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] 9472 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 9473 // CHECK17-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] 9474 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 9475 // CHECK17-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] 9476 // CHECK17-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 9477 // CHECK17-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 9478 // CHECK17-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 9479 // CHECK17-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] 9480 // CHECK17-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 9481 // CHECK17-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]] 9482 // CHECK17-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 9483 // CHECK17-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 9484 // CHECK17-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 9485 // CHECK17-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]] 9486 // CHECK17-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 9487 // CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 9488 // CHECK17-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] 9489 // CHECK17-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 9490 // CHECK17-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] 9491 // CHECK17-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 9492 // CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]] 9493 // CHECK17-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3 9494 // CHECK17-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]] 9495 // CHECK17-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 9496 // CHECK17-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]] 9497 // CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 9498 // CHECK17-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP23]] 9499 // CHECK17-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 9500 // CHECK17-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP23]] 9501 // CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 9502 // CHECK17-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP23]] 9503 // CHECK17-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 9504 // CHECK17-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 9505 // CHECK17-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 9506 // CHECK17-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP23]] 9507 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9508 // CHECK17: omp.body.continue: 9509 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9510 // CHECK17: omp.inner.for.inc: 9511 // CHECK17-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 9512 // CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 9513 // CHECK17-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 9514 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] 9515 // CHECK17: omp.inner.for.end: 9516 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 9517 // CHECK17: omp.dispatch.inc: 9518 // CHECK17-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 9519 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 9520 // CHECK17-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 9521 // CHECK17-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 9522 // CHECK17-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9523 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 9524 // CHECK17-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 9525 // CHECK17-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 9526 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 9527 // CHECK17: omp.dispatch.end: 9528 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 9529 // CHECK17-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9530 // CHECK17-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 9531 // CHECK17-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9532 // CHECK17: .omp.final.then: 9533 // CHECK17-NEXT: store i8 96, ptr [[IT]], align 1 9534 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9535 // CHECK17: .omp.final.done: 9536 // CHECK17-NEXT: ret void 9537 // 9538 // 9539 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 9540 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 9541 // CHECK17-NEXT: entry: 9542 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9543 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9544 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 9545 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 9546 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9547 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9548 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 9549 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9550 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9551 // CHECK17-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 9552 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 9553 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 9554 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 9555 // CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 9556 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 9557 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 9558 // CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 9559 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 9560 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 9561 // CHECK17-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 9562 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 9563 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]]) 9564 // CHECK17-NEXT: ret void 9565 // 9566 // 9567 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined 9568 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 9569 // CHECK17-NEXT: entry: 9570 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 9571 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 9572 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9573 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9574 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 9575 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 9576 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9577 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 9578 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 9579 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 9580 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9581 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9582 // CHECK17-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 9583 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 9584 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 9585 // CHECK17-NEXT: ret void 9586 // 9587 // 9588 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 9589 // CHECK17-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 9590 // CHECK17-NEXT: entry: 9591 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 9592 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 9593 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9594 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9595 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 9596 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 9597 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 9598 // CHECK17-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 9599 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 9600 // CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 9601 // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 9602 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 9603 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 9604 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 9605 // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 9606 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 9607 // CHECK17-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 9608 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8 9609 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) 9610 // CHECK17-NEXT: ret void 9611 // 9612 // 9613 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined 9614 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 9615 // CHECK17-NEXT: entry: 9616 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 9617 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 9618 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 9619 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 9620 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9621 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9622 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 9623 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9624 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 9625 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9626 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9627 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9628 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9629 // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 9630 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 9631 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 9632 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 9633 // CHECK17-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 9634 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 9635 // CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 9636 // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 9637 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 9638 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 9639 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 9640 // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 9641 // CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 9642 // CHECK17-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 9643 // CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 9644 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9645 // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 9646 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 9647 // CHECK17-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 9648 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9649 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 9650 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9651 // CHECK17: cond.true: 9652 // CHECK17-NEXT: br label [[COND_END:%.*]] 9653 // CHECK17: cond.false: 9654 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9655 // CHECK17-NEXT: br label [[COND_END]] 9656 // CHECK17: cond.end: 9657 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 9658 // CHECK17-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 9659 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 9660 // CHECK17-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8 9661 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9662 // CHECK17: omp.inner.for.cond: 9663 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26:![0-9]+]] 9664 // CHECK17-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP26]] 9665 // CHECK17-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 9666 // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9667 // CHECK17: omp.inner.for.body: 9668 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 9669 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 9670 // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 9671 // CHECK17-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP26]] 9672 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] 9673 // CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 9674 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 9675 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 9676 // CHECK17-NEXT: store double [[ADD]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP26]] 9677 // CHECK17-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 9678 // CHECK17-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP26]] 9679 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 9680 // CHECK17-NEXT: store double [[INC]], ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP26]] 9681 // CHECK17-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 9682 // CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 9683 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]] 9684 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 9685 // CHECK17-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP26]] 9686 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9687 // CHECK17: omp.body.continue: 9688 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9689 // CHECK17: omp.inner.for.inc: 9690 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 9691 // CHECK17-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 9692 // CHECK17-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 9693 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] 9694 // CHECK17: omp.inner.for.end: 9695 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9696 // CHECK17: omp.loop.exit: 9697 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 9698 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9699 // CHECK17-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 9700 // CHECK17-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9701 // CHECK17: .omp.final.then: 9702 // CHECK17-NEXT: store i64 400, ptr [[IT]], align 8 9703 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9704 // CHECK17: .omp.final.done: 9705 // CHECK17-NEXT: ret void 9706 // 9707 // 9708 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 9709 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 9710 // CHECK17-NEXT: entry: 9711 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9712 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9713 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 9714 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9715 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9716 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9717 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9718 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 9719 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 9720 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 9721 // CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 9722 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 9723 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 9724 // CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 9725 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 9726 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) 9727 // CHECK17-NEXT: ret void 9728 // 9729 // 9730 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined 9731 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 9732 // CHECK17-NEXT: entry: 9733 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 9734 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 9735 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9736 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9737 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 9738 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9739 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 9740 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9741 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9742 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9743 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9744 // CHECK17-NEXT: [[I:%.*]] = alloca i64, align 8 9745 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 9746 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 9747 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 9748 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 9749 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 9750 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 9751 // CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 9752 // CHECK17-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 9753 // CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 9754 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9755 // CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 9756 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 9757 // CHECK17-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 9758 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9759 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 9760 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9761 // CHECK17: cond.true: 9762 // CHECK17-NEXT: br label [[COND_END:%.*]] 9763 // CHECK17: cond.false: 9764 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9765 // CHECK17-NEXT: br label [[COND_END]] 9766 // CHECK17: cond.end: 9767 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 9768 // CHECK17-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 9769 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 9770 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 9771 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9772 // CHECK17: omp.inner.for.cond: 9773 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29:![0-9]+]] 9774 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP29]] 9775 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 9776 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9777 // CHECK17: omp.inner.for.body: 9778 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 9779 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 9780 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 9781 // CHECK17-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP29]] 9782 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP29]] 9783 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 9784 // CHECK17-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP29]] 9785 // CHECK17-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] 9786 // CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 9787 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 9788 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 9789 // CHECK17-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] 9790 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 9791 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP29]] 9792 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 9793 // CHECK17-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP29]] 9794 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9795 // CHECK17: omp.body.continue: 9796 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9797 // CHECK17: omp.inner.for.inc: 9798 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 9799 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 9800 // CHECK17-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 9801 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] 9802 // CHECK17: omp.inner.for.end: 9803 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9804 // CHECK17: omp.loop.exit: 9805 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 9806 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9807 // CHECK17-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 9808 // CHECK17-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9809 // CHECK17: .omp.final.then: 9810 // CHECK17-NEXT: store i64 11, ptr [[I]], align 8 9811 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9812 // CHECK17: .omp.final.done: 9813 // CHECK17-NEXT: ret void 9814 // 9815 // 9816 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 9817 // CHECK19-SAME: () #[[ATTR0:[0-9]+]] { 9818 // CHECK19-NEXT: entry: 9819 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) 9820 // CHECK19-NEXT: ret void 9821 // 9822 // 9823 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined 9824 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 9825 // CHECK19-NEXT: entry: 9826 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 9827 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 9828 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9829 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 9830 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9831 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9832 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9833 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9834 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 9835 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 9836 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 9837 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 9838 // CHECK19-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 9839 // CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 9840 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9841 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 9842 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 9843 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 9844 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9845 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 9846 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9847 // CHECK19: cond.true: 9848 // CHECK19-NEXT: br label [[COND_END:%.*]] 9849 // CHECK19: cond.false: 9850 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 9851 // CHECK19-NEXT: br label [[COND_END]] 9852 // CHECK19: cond.end: 9853 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9854 // CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 9855 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 9856 // CHECK19-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 9857 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9858 // CHECK19: omp.inner.for.cond: 9859 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 9860 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] 9861 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9862 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9863 // CHECK19: omp.inner.for.body: 9864 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 9865 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 9866 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 9867 // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] 9868 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9869 // CHECK19: omp.body.continue: 9870 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9871 // CHECK19: omp.inner.for.inc: 9872 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 9873 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 9874 // CHECK19-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 9875 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 9876 // CHECK19: omp.inner.for.end: 9877 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9878 // CHECK19: omp.loop.exit: 9879 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 9880 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 9881 // CHECK19-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 9882 // CHECK19-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9883 // CHECK19: .omp.final.then: 9884 // CHECK19-NEXT: store i32 33, ptr [[I]], align 4 9885 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 9886 // CHECK19: .omp.final.done: 9887 // CHECK19-NEXT: ret void 9888 // 9889 // 9890 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 9891 // CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 9892 // CHECK19-NEXT: entry: 9893 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9894 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 9895 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9896 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9897 // CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 9898 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9899 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 9900 // CHECK19-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 9901 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 9902 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 9903 // CHECK19-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 9904 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 9905 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 9906 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 9907 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 9908 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 9909 // CHECK19-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 9910 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4 9911 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 9912 // CHECK19-NEXT: ret void 9913 // 9914 // 9915 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined 9916 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 9917 // CHECK19-NEXT: entry: 9918 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 9919 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 9920 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9921 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 9922 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9923 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9924 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 9925 // CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 9926 // CHECK19-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 9927 // CHECK19-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 9928 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9929 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9930 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9931 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9932 // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 9933 // CHECK19-NEXT: [[LIN2:%.*]] = alloca i32, align 4 9934 // CHECK19-NEXT: [[A3:%.*]] = alloca i32, align 4 9935 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 9936 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 9937 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 9938 // CHECK19-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 9939 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 9940 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 9941 // CHECK19-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 9942 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 9943 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 9944 // CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 9945 // CHECK19-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 9946 // CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 9947 // CHECK19-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 9948 // CHECK19-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 9949 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 9950 // CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 9951 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 9952 // CHECK19-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 9953 // CHECK19-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 9954 // CHECK19-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9955 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 9956 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9957 // CHECK19: cond.true: 9958 // CHECK19-NEXT: br label [[COND_END:%.*]] 9959 // CHECK19: cond.false: 9960 // CHECK19-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 9961 // CHECK19-NEXT: br label [[COND_END]] 9962 // CHECK19: cond.end: 9963 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 9964 // CHECK19-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 9965 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 9966 // CHECK19-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 9967 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9968 // CHECK19: omp.inner.for.cond: 9969 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]] 9970 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]] 9971 // CHECK19-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 9972 // CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9973 // CHECK19: omp.inner.for.body: 9974 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 9975 // CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 9976 // CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 9977 // CHECK19-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP18]] 9978 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP18]] 9979 // CHECK19-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 9980 // CHECK19-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 9981 // CHECK19-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]] 9982 // CHECK19-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 9983 // CHECK19-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 9984 // CHECK19-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 9985 // CHECK19-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP18]] 9986 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP18]] 9987 // CHECK19-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 9988 // CHECK19-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 9989 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]] 9990 // CHECK19-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 9991 // CHECK19-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 9992 // CHECK19-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 9993 // CHECK19-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP18]] 9994 // CHECK19-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]] 9995 // CHECK19-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 9996 // CHECK19-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 9997 // CHECK19-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 9998 // CHECK19-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]] 9999 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10000 // CHECK19: omp.body.continue: 10001 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10002 // CHECK19: omp.inner.for.inc: 10003 // CHECK19-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 10004 // CHECK19-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 10005 // CHECK19-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 10006 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 10007 // CHECK19: omp.inner.for.end: 10008 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10009 // CHECK19: omp.loop.exit: 10010 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 10011 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10012 // CHECK19-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 10013 // CHECK19-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10014 // CHECK19: .omp.final.then: 10015 // CHECK19-NEXT: store i64 400, ptr [[IT]], align 8 10016 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10017 // CHECK19: .omp.final.done: 10018 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10019 // CHECK19-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 10020 // CHECK19-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 10021 // CHECK19: .omp.linear.pu: 10022 // CHECK19-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 10023 // CHECK19-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 10024 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 10025 // CHECK19-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 10026 // CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 10027 // CHECK19: .omp.linear.pu.done: 10028 // CHECK19-NEXT: ret void 10029 // 10030 // 10031 // CHECK19-LABEL: define {{[^@]+}}@_Z7get_valv 10032 // CHECK19-SAME: () #[[ATTR3:[0-9]+]] { 10033 // CHECK19-NEXT: entry: 10034 // CHECK19-NEXT: ret i64 0 10035 // 10036 // 10037 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 10038 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 10039 // CHECK19-NEXT: entry: 10040 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10041 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10042 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10043 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10044 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10045 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 10046 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 10047 // CHECK19-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 10048 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 10049 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 10050 // CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 10051 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 10052 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) 10053 // CHECK19-NEXT: ret void 10054 // 10055 // 10056 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined 10057 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 10058 // CHECK19-NEXT: entry: 10059 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 10060 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 10061 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10062 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10063 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10064 // CHECK19-NEXT: [[TMP:%.*]] = alloca i16, align 2 10065 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10066 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10067 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10068 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10069 // CHECK19-NEXT: [[IT:%.*]] = alloca i16, align 2 10070 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 10071 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 10072 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10073 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 10074 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 10075 // CHECK19-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 10076 // CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 10077 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10078 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 10079 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 10080 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 10081 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10082 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 10083 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10084 // CHECK19: cond.true: 10085 // CHECK19-NEXT: br label [[COND_END:%.*]] 10086 // CHECK19: cond.false: 10087 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10088 // CHECK19-NEXT: br label [[COND_END]] 10089 // CHECK19: cond.end: 10090 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10091 // CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 10092 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 10093 // CHECK19-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 10094 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10095 // CHECK19: omp.inner.for.cond: 10096 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] 10097 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] 10098 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10099 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10100 // CHECK19: omp.inner.for.body: 10101 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 10102 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 10103 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 10104 // CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 10105 // CHECK19-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP21]] 10106 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] 10107 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 10108 // CHECK19-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] 10109 // CHECK19-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]] 10110 // CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 10111 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 10112 // CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 10113 // CHECK19-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]] 10114 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10115 // CHECK19: omp.body.continue: 10116 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10117 // CHECK19: omp.inner.for.inc: 10118 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 10119 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 10120 // CHECK19-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 10121 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 10122 // CHECK19: omp.inner.for.end: 10123 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10124 // CHECK19: omp.loop.exit: 10125 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 10126 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10127 // CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 10128 // CHECK19-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10129 // CHECK19: .omp.final.then: 10130 // CHECK19-NEXT: store i16 22, ptr [[IT]], align 2 10131 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10132 // CHECK19: .omp.final.done: 10133 // CHECK19-NEXT: ret void 10134 // 10135 // 10136 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 10137 // CHECK19-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 10138 // CHECK19-NEXT: entry: 10139 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10140 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 10141 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10142 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 10143 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 10144 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10145 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 10146 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 10147 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 10148 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 10149 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10150 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 10151 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10152 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 10153 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 10154 // CHECK19-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 10155 // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 10156 // CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 10157 // CHECK19-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 10158 // CHECK19-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 10159 // CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 10160 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 10161 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 10162 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 10163 // CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 10164 // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 10165 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 10166 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 10167 // CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 10168 // CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 10169 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 10170 // CHECK19-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 10171 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 10172 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 10173 // CHECK19-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 10174 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 10175 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]]) 10176 // CHECK19-NEXT: ret void 10177 // 10178 // 10179 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined 10180 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 10181 // CHECK19-NEXT: entry: 10182 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 10183 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 10184 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10185 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 10186 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10187 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 10188 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 10189 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10190 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 10191 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 10192 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 10193 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 10194 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10195 // CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1 10196 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10197 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10198 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10199 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10200 // CHECK19-NEXT: [[IT:%.*]] = alloca i8, align 1 10201 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 10202 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 10203 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10204 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 10205 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 10206 // CHECK19-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 10207 // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 10208 // CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 10209 // CHECK19-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 10210 // CHECK19-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 10211 // CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 10212 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 10213 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 10214 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 10215 // CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 10216 // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 10217 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 10218 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 10219 // CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 10220 // CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 10221 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 10222 // CHECK19-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 10223 // CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 10224 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10225 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 10226 // CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 10227 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 10228 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 10229 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 10230 // CHECK19: omp.dispatch.cond: 10231 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10232 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 10233 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10234 // CHECK19: cond.true: 10235 // CHECK19-NEXT: br label [[COND_END:%.*]] 10236 // CHECK19: cond.false: 10237 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10238 // CHECK19-NEXT: br label [[COND_END]] 10239 // CHECK19: cond.end: 10240 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 10241 // CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 10242 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 10243 // CHECK19-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 10244 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 10245 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10246 // CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 10247 // CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 10248 // CHECK19: omp.dispatch.body: 10249 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10250 // CHECK19: omp.inner.for.cond: 10251 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] 10252 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]] 10253 // CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 10254 // CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10255 // CHECK19: omp.inner.for.body: 10256 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 10257 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 10258 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 10259 // CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 10260 // CHECK19-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP24]] 10261 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] 10262 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 10263 // CHECK19-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] 10264 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 10265 // CHECK19-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 10266 // CHECK19-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 10267 // CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 10268 // CHECK19-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 10269 // CHECK19-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 10270 // CHECK19-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 10271 // CHECK19-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]] 10272 // CHECK19-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 10273 // CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 10274 // CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 10275 // CHECK19-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]] 10276 // CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 10277 // CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 10278 // CHECK19-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] 10279 // CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 10280 // CHECK19-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] 10281 // CHECK19-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 10282 // CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]] 10283 // CHECK19-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3 10284 // CHECK19-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]] 10285 // CHECK19-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 10286 // CHECK19-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]] 10287 // CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 10288 // CHECK19-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP24]] 10289 // CHECK19-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 10290 // CHECK19-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP24]] 10291 // CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 10292 // CHECK19-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP24]] 10293 // CHECK19-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 10294 // CHECK19-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 10295 // CHECK19-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 10296 // CHECK19-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP24]] 10297 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10298 // CHECK19: omp.body.continue: 10299 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10300 // CHECK19: omp.inner.for.inc: 10301 // CHECK19-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 10302 // CHECK19-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 10303 // CHECK19-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 10304 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 10305 // CHECK19: omp.inner.for.end: 10306 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 10307 // CHECK19: omp.dispatch.inc: 10308 // CHECK19-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 10309 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 10310 // CHECK19-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 10311 // CHECK19-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 10312 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10313 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 10314 // CHECK19-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 10315 // CHECK19-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 10316 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 10317 // CHECK19: omp.dispatch.end: 10318 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 10319 // CHECK19-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10320 // CHECK19-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 10321 // CHECK19-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10322 // CHECK19: .omp.final.then: 10323 // CHECK19-NEXT: store i8 96, ptr [[IT]], align 1 10324 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10325 // CHECK19: .omp.final.done: 10326 // CHECK19-NEXT: ret void 10327 // 10328 // 10329 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 10330 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10331 // CHECK19-NEXT: entry: 10332 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10333 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10334 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 10335 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 10336 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10337 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10338 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 10339 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10340 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 10341 // CHECK19-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 10342 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 10343 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 10344 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 10345 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 10346 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 10347 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 10348 // CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 10349 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 10350 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 10351 // CHECK19-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 10352 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 10353 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]]) 10354 // CHECK19-NEXT: ret void 10355 // 10356 // 10357 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined 10358 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10359 // CHECK19-NEXT: entry: 10360 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 10361 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 10362 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10363 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10364 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 10365 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 10366 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10367 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 10368 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 10369 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 10370 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10371 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 10372 // CHECK19-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 10373 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 10374 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 10375 // CHECK19-NEXT: ret void 10376 // 10377 // 10378 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 10379 // CHECK19-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 10380 // CHECK19-NEXT: entry: 10381 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 10382 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 10383 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10384 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10385 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 10386 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 10387 // CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 10388 // CHECK19-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 10389 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 10390 // CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 10391 // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 10392 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 10393 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 10394 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 10395 // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 10396 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 10397 // CHECK19-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 10398 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 10399 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]]) 10400 // CHECK19-NEXT: ret void 10401 // 10402 // 10403 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined 10404 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 10405 // CHECK19-NEXT: entry: 10406 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 10407 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 10408 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 10409 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 10410 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10411 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10412 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 10413 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 10414 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 10415 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 10416 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 10417 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 10418 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10419 // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 10420 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 10421 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 10422 // CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 10423 // CHECK19-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 10424 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 10425 // CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 10426 // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 10427 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 10428 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 10429 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 10430 // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 10431 // CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 10432 // CHECK19-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 10433 // CHECK19-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 10434 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10435 // CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 10436 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 10437 // CHECK19-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 10438 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 10439 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 10440 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10441 // CHECK19: cond.true: 10442 // CHECK19-NEXT: br label [[COND_END:%.*]] 10443 // CHECK19: cond.false: 10444 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 10445 // CHECK19-NEXT: br label [[COND_END]] 10446 // CHECK19: cond.end: 10447 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 10448 // CHECK19-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 10449 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 10450 // CHECK19-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8 10451 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10452 // CHECK19: omp.inner.for.cond: 10453 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27:![0-9]+]] 10454 // CHECK19-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP27]] 10455 // CHECK19-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 10456 // CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10457 // CHECK19: omp.inner.for.body: 10458 // CHECK19-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 10459 // CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 10460 // CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 10461 // CHECK19-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP27]] 10462 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 10463 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 10464 // CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 10465 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 10466 // CHECK19-NEXT: store double [[ADD]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP27]] 10467 // CHECK19-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 10468 // CHECK19-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP27]] 10469 // CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 10470 // CHECK19-NEXT: store double [[INC]], ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP27]] 10471 // CHECK19-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 10472 // CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 10473 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]] 10474 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 10475 // CHECK19-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP27]] 10476 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10477 // CHECK19: omp.body.continue: 10478 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10479 // CHECK19: omp.inner.for.inc: 10480 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 10481 // CHECK19-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 10482 // CHECK19-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 10483 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 10484 // CHECK19: omp.inner.for.end: 10485 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10486 // CHECK19: omp.loop.exit: 10487 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 10488 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10489 // CHECK19-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 10490 // CHECK19-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10491 // CHECK19: .omp.final.then: 10492 // CHECK19-NEXT: store i64 400, ptr [[IT]], align 8 10493 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10494 // CHECK19: .omp.final.done: 10495 // CHECK19-NEXT: ret void 10496 // 10497 // 10498 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 10499 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10500 // CHECK19-NEXT: entry: 10501 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10502 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10503 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 10504 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10505 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10506 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10507 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 10508 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 10509 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 10510 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 10511 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 10512 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 10513 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 10514 // CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 10515 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 10516 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) 10517 // CHECK19-NEXT: ret void 10518 // 10519 // 10520 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined 10521 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10522 // CHECK19-NEXT: entry: 10523 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 10524 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 10525 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10526 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10527 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 10528 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 10529 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 10530 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 10531 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 10532 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 10533 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10534 // CHECK19-NEXT: [[I:%.*]] = alloca i64, align 8 10535 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 10536 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 10537 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 10538 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 10539 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 10540 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 10541 // CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 10542 // CHECK19-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 10543 // CHECK19-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 10544 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10545 // CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 10546 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 10547 // CHECK19-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 10548 // CHECK19-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 10549 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 10550 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10551 // CHECK19: cond.true: 10552 // CHECK19-NEXT: br label [[COND_END:%.*]] 10553 // CHECK19: cond.false: 10554 // CHECK19-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 10555 // CHECK19-NEXT: br label [[COND_END]] 10556 // CHECK19: cond.end: 10557 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 10558 // CHECK19-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 10559 // CHECK19-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 10560 // CHECK19-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 10561 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10562 // CHECK19: omp.inner.for.cond: 10563 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30:![0-9]+]] 10564 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP30]] 10565 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 10566 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10567 // CHECK19: omp.inner.for.body: 10568 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 10569 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 10570 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 10571 // CHECK19-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP30]] 10572 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP30]] 10573 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 10574 // CHECK19-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP30]] 10575 // CHECK19-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] 10576 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 10577 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 10578 // CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 10579 // CHECK19-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] 10580 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 10581 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP30]] 10582 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 10583 // CHECK19-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP30]] 10584 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10585 // CHECK19: omp.body.continue: 10586 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10587 // CHECK19: omp.inner.for.inc: 10588 // CHECK19-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 10589 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 10590 // CHECK19-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 10591 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 10592 // CHECK19: omp.inner.for.end: 10593 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10594 // CHECK19: omp.loop.exit: 10595 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 10596 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10597 // CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 10598 // CHECK19-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10599 // CHECK19: .omp.final.then: 10600 // CHECK19-NEXT: store i64 11, ptr [[I]], align 8 10601 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10602 // CHECK19: .omp.final.done: 10603 // CHECK19-NEXT: ret void 10604 // 10605 // 10606 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 10607 // CHECK21-SAME: () #[[ATTR0:[0-9]+]] { 10608 // CHECK21-NEXT: entry: 10609 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) 10610 // CHECK21-NEXT: ret void 10611 // 10612 // 10613 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined 10614 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 10615 // CHECK21-NEXT: entry: 10616 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 10617 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 10618 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10619 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 10620 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10621 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10622 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10623 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10624 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 10625 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 10626 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 10627 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 10628 // CHECK21-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 10629 // CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 10630 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10631 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 10632 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 10633 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 10634 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10635 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 10636 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10637 // CHECK21: cond.true: 10638 // CHECK21-NEXT: br label [[COND_END:%.*]] 10639 // CHECK21: cond.false: 10640 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10641 // CHECK21-NEXT: br label [[COND_END]] 10642 // CHECK21: cond.end: 10643 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10644 // CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 10645 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 10646 // CHECK21-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 10647 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10648 // CHECK21: omp.inner.for.cond: 10649 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 10650 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 10651 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10652 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10653 // CHECK21: omp.inner.for.body: 10654 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 10655 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 10656 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 10657 // CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 10658 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10659 // CHECK21: omp.body.continue: 10660 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10661 // CHECK21: omp.inner.for.inc: 10662 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 10663 // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 10664 // CHECK21-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 10665 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 10666 // CHECK21: omp.inner.for.end: 10667 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10668 // CHECK21: omp.loop.exit: 10669 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 10670 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10671 // CHECK21-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 10672 // CHECK21-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10673 // CHECK21: .omp.final.then: 10674 // CHECK21-NEXT: store i32 33, ptr [[I]], align 4 10675 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 10676 // CHECK21: .omp.final.done: 10677 // CHECK21-NEXT: ret void 10678 // 10679 // 10680 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 10681 // CHECK21-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 10682 // CHECK21-NEXT: entry: 10683 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10684 // CHECK21-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 10685 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10686 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10687 // CHECK21-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 10688 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10689 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 10690 // CHECK21-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 10691 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 10692 // CHECK21-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 10693 // CHECK21-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 10694 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 10695 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 10696 // CHECK21-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 10697 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 10698 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 10699 // CHECK21-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 10700 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8 10701 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 10702 // CHECK21-NEXT: ret void 10703 // 10704 // 10705 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined 10706 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 10707 // CHECK21-NEXT: entry: 10708 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 10709 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 10710 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10711 // CHECK21-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 10712 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10713 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 10714 // CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8 10715 // CHECK21-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 10716 // CHECK21-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 10717 // CHECK21-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 10718 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 10719 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 10720 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 10721 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10722 // CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 8 10723 // CHECK21-NEXT: [[LIN2:%.*]] = alloca i32, align 4 10724 // CHECK21-NEXT: [[A3:%.*]] = alloca i32, align 4 10725 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 10726 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 10727 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 10728 // CHECK21-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 10729 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 10730 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 10731 // CHECK21-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 10732 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 10733 // CHECK21-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 10734 // CHECK21-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 10735 // CHECK21-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 10736 // CHECK21-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 10737 // CHECK21-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 10738 // CHECK21-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 10739 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10740 // CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 10741 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 10742 // CHECK21-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 10743 // CHECK21-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 10744 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 10745 // CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 10746 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10747 // CHECK21: cond.true: 10748 // CHECK21-NEXT: br label [[COND_END:%.*]] 10749 // CHECK21: cond.false: 10750 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 10751 // CHECK21-NEXT: br label [[COND_END]] 10752 // CHECK21: cond.end: 10753 // CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 10754 // CHECK21-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 10755 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 10756 // CHECK21-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 10757 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10758 // CHECK21: omp.inner.for.cond: 10759 // CHECK21-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17:![0-9]+]] 10760 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP17]] 10761 // CHECK21-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 10762 // CHECK21-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10763 // CHECK21: omp.inner.for.body: 10764 // CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 10765 // CHECK21-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 10766 // CHECK21-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 10767 // CHECK21-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP17]] 10768 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP17]] 10769 // CHECK21-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 10770 // CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 10771 // CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]] 10772 // CHECK21-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 10773 // CHECK21-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 10774 // CHECK21-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 10775 // CHECK21-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP17]] 10776 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP17]] 10777 // CHECK21-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 10778 // CHECK21-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 10779 // CHECK21-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]] 10780 // CHECK21-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 10781 // CHECK21-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 10782 // CHECK21-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 10783 // CHECK21-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP17]] 10784 // CHECK21-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP17]] 10785 // CHECK21-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 10786 // CHECK21-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 10787 // CHECK21-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 10788 // CHECK21-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP17]] 10789 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10790 // CHECK21: omp.body.continue: 10791 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10792 // CHECK21: omp.inner.for.inc: 10793 // CHECK21-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 10794 // CHECK21-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 10795 // CHECK21-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 10796 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 10797 // CHECK21: omp.inner.for.end: 10798 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10799 // CHECK21: omp.loop.exit: 10800 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 10801 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10802 // CHECK21-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 10803 // CHECK21-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10804 // CHECK21: .omp.final.then: 10805 // CHECK21-NEXT: store i64 400, ptr [[IT]], align 8 10806 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 10807 // CHECK21: .omp.final.done: 10808 // CHECK21-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10809 // CHECK21-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 10810 // CHECK21-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 10811 // CHECK21: .omp.linear.pu: 10812 // CHECK21-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 10813 // CHECK21-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 10814 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 10815 // CHECK21-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 10816 // CHECK21-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 10817 // CHECK21: .omp.linear.pu.done: 10818 // CHECK21-NEXT: ret void 10819 // 10820 // 10821 // CHECK21-LABEL: define {{[^@]+}}@_Z7get_valv 10822 // CHECK21-SAME: () #[[ATTR3:[0-9]+]] { 10823 // CHECK21-NEXT: entry: 10824 // CHECK21-NEXT: ret i64 0 10825 // 10826 // 10827 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 10828 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 10829 // CHECK21-NEXT: entry: 10830 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10831 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10832 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10833 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10834 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 10835 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 10836 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 10837 // CHECK21-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 10838 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 10839 // CHECK21-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 10840 // CHECK21-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 10841 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 10842 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) 10843 // CHECK21-NEXT: ret void 10844 // 10845 // 10846 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined 10847 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 10848 // CHECK21-NEXT: entry: 10849 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 10850 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 10851 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10852 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10853 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10854 // CHECK21-NEXT: [[TMP:%.*]] = alloca i16, align 2 10855 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10856 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10857 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10858 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10859 // CHECK21-NEXT: [[IT:%.*]] = alloca i16, align 2 10860 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 10861 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 10862 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 10863 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 10864 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 10865 // CHECK21-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 10866 // CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 10867 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 10868 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 10869 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 10870 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 10871 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10872 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 10873 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10874 // CHECK21: cond.true: 10875 // CHECK21-NEXT: br label [[COND_END:%.*]] 10876 // CHECK21: cond.false: 10877 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 10878 // CHECK21-NEXT: br label [[COND_END]] 10879 // CHECK21: cond.end: 10880 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10881 // CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 10882 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 10883 // CHECK21-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 10884 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10885 // CHECK21: omp.inner.for.cond: 10886 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] 10887 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] 10888 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10889 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10890 // CHECK21: omp.inner.for.body: 10891 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 10892 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 10893 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 10894 // CHECK21-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 10895 // CHECK21-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP20]] 10896 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]] 10897 // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 10898 // CHECK21-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]] 10899 // CHECK21-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP20]] 10900 // CHECK21-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 10901 // CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 10902 // CHECK21-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 10903 // CHECK21-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP20]] 10904 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10905 // CHECK21: omp.body.continue: 10906 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10907 // CHECK21: omp.inner.for.inc: 10908 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 10909 // CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 10910 // CHECK21-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 10911 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 10912 // CHECK21: omp.inner.for.end: 10913 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10914 // CHECK21: omp.loop.exit: 10915 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 10916 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 10917 // CHECK21-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 10918 // CHECK21-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10919 // CHECK21: .omp.final.then: 10920 // CHECK21-NEXT: store i16 22, ptr [[IT]], align 2 10921 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 10922 // CHECK21: .omp.final.done: 10923 // CHECK21-NEXT: ret void 10924 // 10925 // 10926 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 10927 // CHECK21-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 10928 // CHECK21-NEXT: entry: 10929 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10930 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 10931 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10932 // CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 10933 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 10934 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10935 // CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10936 // CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 10937 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 10938 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 10939 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10940 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 10941 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 10942 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 10943 // CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 10944 // CHECK21-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 10945 // CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 10946 // CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 10947 // CHECK21-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 10948 // CHECK21-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 10949 // CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 10950 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 10951 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 10952 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 10953 // CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 10954 // CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 10955 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 10956 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 10957 // CHECK21-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 10958 // CHECK21-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 10959 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 10960 // CHECK21-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 10961 // CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 10962 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 10963 // CHECK21-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 10964 // CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 10965 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]]) 10966 // CHECK21-NEXT: ret void 10967 // 10968 // 10969 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined 10970 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 10971 // CHECK21-NEXT: entry: 10972 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 10973 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 10974 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10975 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 10976 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10977 // CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 10978 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 10979 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10980 // CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10981 // CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 10982 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 10983 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 10984 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10985 // CHECK21-NEXT: [[TMP:%.*]] = alloca i8, align 1 10986 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10987 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10988 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10989 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10990 // CHECK21-NEXT: [[IT:%.*]] = alloca i8, align 1 10991 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 10992 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 10993 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 10994 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 10995 // CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 10996 // CHECK21-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 10997 // CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 10998 // CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 10999 // CHECK21-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 11000 // CHECK21-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 11001 // CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 11002 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 11003 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 11004 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 11005 // CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 11006 // CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 11007 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 11008 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 11009 // CHECK21-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 11010 // CHECK21-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 11011 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 11012 // CHECK21-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 11013 // CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 11014 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11015 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 11016 // CHECK21-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 11017 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 11018 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 11019 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 11020 // CHECK21: omp.dispatch.cond: 11021 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11022 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 11023 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11024 // CHECK21: cond.true: 11025 // CHECK21-NEXT: br label [[COND_END:%.*]] 11026 // CHECK21: cond.false: 11027 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11028 // CHECK21-NEXT: br label [[COND_END]] 11029 // CHECK21: cond.end: 11030 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 11031 // CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 11032 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 11033 // CHECK21-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 11034 // CHECK21-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 11035 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11036 // CHECK21-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 11037 // CHECK21-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 11038 // CHECK21: omp.dispatch.body: 11039 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11040 // CHECK21: omp.inner.for.cond: 11041 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] 11042 // CHECK21-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] 11043 // CHECK21-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 11044 // CHECK21-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11045 // CHECK21: omp.inner.for.body: 11046 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 11047 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 11048 // CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 11049 // CHECK21-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 11050 // CHECK21-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP23]] 11051 // CHECK21-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] 11052 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 11053 // CHECK21-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] 11054 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 11055 // CHECK21-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] 11056 // CHECK21-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 11057 // CHECK21-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 11058 // CHECK21-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 11059 // CHECK21-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] 11060 // CHECK21-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 11061 // CHECK21-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]] 11062 // CHECK21-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 11063 // CHECK21-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 11064 // CHECK21-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 11065 // CHECK21-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]] 11066 // CHECK21-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 11067 // CHECK21-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 11068 // CHECK21-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] 11069 // CHECK21-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 11070 // CHECK21-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] 11071 // CHECK21-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 11072 // CHECK21-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]] 11073 // CHECK21-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3 11074 // CHECK21-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]] 11075 // CHECK21-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 11076 // CHECK21-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]] 11077 // CHECK21-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 11078 // CHECK21-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP23]] 11079 // CHECK21-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 11080 // CHECK21-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP23]] 11081 // CHECK21-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 11082 // CHECK21-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP23]] 11083 // CHECK21-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 11084 // CHECK21-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 11085 // CHECK21-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 11086 // CHECK21-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP23]] 11087 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11088 // CHECK21: omp.body.continue: 11089 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11090 // CHECK21: omp.inner.for.inc: 11091 // CHECK21-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 11092 // CHECK21-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 11093 // CHECK21-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 11094 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] 11095 // CHECK21: omp.inner.for.end: 11096 // CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 11097 // CHECK21: omp.dispatch.inc: 11098 // CHECK21-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 11099 // CHECK21-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 11100 // CHECK21-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 11101 // CHECK21-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 11102 // CHECK21-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11103 // CHECK21-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 11104 // CHECK21-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 11105 // CHECK21-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 11106 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND]] 11107 // CHECK21: omp.dispatch.end: 11108 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 11109 // CHECK21-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11110 // CHECK21-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 11111 // CHECK21-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11112 // CHECK21: .omp.final.then: 11113 // CHECK21-NEXT: store i8 96, ptr [[IT]], align 1 11114 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11115 // CHECK21: .omp.final.done: 11116 // CHECK21-NEXT: ret void 11117 // 11118 // 11119 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 11120 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11121 // CHECK21-NEXT: entry: 11122 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11123 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11124 // CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 11125 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 11126 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11127 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11128 // CHECK21-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 11129 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 11130 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 11131 // CHECK21-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 11132 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 11133 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 11134 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 11135 // CHECK21-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 11136 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 11137 // CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 11138 // CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 11139 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 11140 // CHECK21-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 11141 // CHECK21-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 11142 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 11143 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]]) 11144 // CHECK21-NEXT: ret void 11145 // 11146 // 11147 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined 11148 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 11149 // CHECK21-NEXT: entry: 11150 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 11151 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 11152 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11153 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11154 // CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 11155 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 11156 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11157 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 11158 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 11159 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 11160 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 11161 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 11162 // CHECK21-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 11163 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 11164 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 11165 // CHECK21-NEXT: ret void 11166 // 11167 // 11168 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 11169 // CHECK21-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 11170 // CHECK21-NEXT: entry: 11171 // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 11172 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 11173 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 11174 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11175 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 11176 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 11177 // CHECK21-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 11178 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 11179 // CHECK21-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 11180 // CHECK21-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 11181 // CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 11182 // CHECK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 11183 // CHECK21-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 11184 // CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 11185 // CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 11186 // CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 11187 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 11188 // CHECK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 11189 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 11190 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 11191 // CHECK21-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8 11192 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4 11193 // CHECK21-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 11194 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 11195 // CHECK21-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 11196 // CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 11197 // CHECK21-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 11198 // CHECK21-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 11199 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 11200 // CHECK21-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 11201 // CHECK21-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1 11202 // CHECK21-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11203 // CHECK21: omp_if.then: 11204 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) 11205 // CHECK21-NEXT: br label [[OMP_IF_END:%.*]] 11206 // CHECK21: omp_if.else: 11207 // CHECK21-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 11208 // CHECK21-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 11209 // CHECK21-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 11210 // CHECK21-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) #[[ATTR2:[0-9]+]] 11211 // CHECK21-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 11212 // CHECK21-NEXT: br label [[OMP_IF_END]] 11213 // CHECK21: omp_if.end: 11214 // CHECK21-NEXT: ret void 11215 // 11216 // 11217 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined 11218 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 11219 // CHECK21-NEXT: entry: 11220 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 11221 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 11222 // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 11223 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 11224 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 11225 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11226 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 11227 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 11228 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11229 // CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8 11230 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11231 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11232 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11233 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11234 // CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 8 11235 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 11236 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 11237 // CHECK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 11238 // CHECK21-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 11239 // CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 11240 // CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 11241 // CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 11242 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 11243 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 11244 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 11245 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 11246 // CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 11247 // CHECK21-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 11248 // CHECK21-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 11249 // CHECK21-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 11250 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11251 // CHECK21-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 11252 // CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 11253 // CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11254 // CHECK21: omp_if.then: 11255 // CHECK21-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 11256 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 11257 // CHECK21-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 11258 // CHECK21-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11259 // CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 11260 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11261 // CHECK21: cond.true: 11262 // CHECK21-NEXT: br label [[COND_END:%.*]] 11263 // CHECK21: cond.false: 11264 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11265 // CHECK21-NEXT: br label [[COND_END]] 11266 // CHECK21: cond.end: 11267 // CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 11268 // CHECK21-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 11269 // CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 11270 // CHECK21-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV]], align 8 11271 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11272 // CHECK21: omp.inner.for.cond: 11273 // CHECK21-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26:![0-9]+]] 11274 // CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP26]] 11275 // CHECK21-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 11276 // CHECK21-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11277 // CHECK21: omp.inner.for.body: 11278 // CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 11279 // CHECK21-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 11280 // CHECK21-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 11281 // CHECK21-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP26]] 11282 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] 11283 // CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double 11284 // CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 11285 // CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 11286 // CHECK21-NEXT: store double [[ADD]], ptr [[A]], align 8, !nontemporal !27, !llvm.access.group [[ACC_GRP26]] 11287 // CHECK21-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 11288 // CHECK21-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 8, !nontemporal !27, !llvm.access.group [[ACC_GRP26]] 11289 // CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 11290 // CHECK21-NEXT: store double [[INC]], ptr [[A4]], align 8, !nontemporal !27, !llvm.access.group [[ACC_GRP26]] 11291 // CHECK21-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 11292 // CHECK21-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]] 11293 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP15]] 11294 // CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 11295 // CHECK21-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP26]] 11296 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11297 // CHECK21: omp.body.continue: 11298 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11299 // CHECK21: omp.inner.for.inc: 11300 // CHECK21-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 11301 // CHECK21-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1 11302 // CHECK21-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 11303 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 11304 // CHECK21: omp.inner.for.end: 11305 // CHECK21-NEXT: br label [[OMP_IF_END:%.*]] 11306 // CHECK21: omp_if.else: 11307 // CHECK21-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 11308 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 11309 // CHECK21-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP18]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 11310 // CHECK21-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11311 // CHECK21-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[TMP19]], 3 11312 // CHECK21-NEXT: br i1 [[CMP8]], label [[COND_TRUE9:%.*]], label [[COND_FALSE10:%.*]] 11313 // CHECK21: cond.true9: 11314 // CHECK21-NEXT: br label [[COND_END11:%.*]] 11315 // CHECK21: cond.false10: 11316 // CHECK21-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11317 // CHECK21-NEXT: br label [[COND_END11]] 11318 // CHECK21: cond.end11: 11319 // CHECK21-NEXT: [[COND12:%.*]] = phi i64 [ 3, [[COND_TRUE9]] ], [ [[TMP20]], [[COND_FALSE10]] ] 11320 // CHECK21-NEXT: store i64 [[COND12]], ptr [[DOTOMP_UB]], align 8 11321 // CHECK21-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 11322 // CHECK21-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV]], align 8 11323 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 11324 // CHECK21: omp.inner.for.cond13: 11325 // CHECK21-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 11326 // CHECK21-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11327 // CHECK21-NEXT: [[CMP14:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 11328 // CHECK21-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END29:%.*]] 11329 // CHECK21: omp.inner.for.body15: 11330 // CHECK21-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 11331 // CHECK21-NEXT: [[MUL16:%.*]] = mul i64 [[TMP24]], 400 11332 // CHECK21-NEXT: [[SUB17:%.*]] = sub i64 2000, [[MUL16]] 11333 // CHECK21-NEXT: store i64 [[SUB17]], ptr [[IT]], align 8 11334 // CHECK21-NEXT: [[TMP25:%.*]] = load i32, ptr [[B_ADDR]], align 4 11335 // CHECK21-NEXT: [[CONV18:%.*]] = sitofp i32 [[TMP25]] to double 11336 // CHECK21-NEXT: [[ADD19:%.*]] = fadd double [[CONV18]], 1.500000e+00 11337 // CHECK21-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 11338 // CHECK21-NEXT: store double [[ADD19]], ptr [[A20]], align 8 11339 // CHECK21-NEXT: [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 11340 // CHECK21-NEXT: [[TMP26:%.*]] = load double, ptr [[A21]], align 8 11341 // CHECK21-NEXT: [[INC22:%.*]] = fadd double [[TMP26]], 1.000000e+00 11342 // CHECK21-NEXT: store double [[INC22]], ptr [[A21]], align 8 11343 // CHECK21-NEXT: [[CONV23:%.*]] = fptosi double [[INC22]] to i16 11344 // CHECK21-NEXT: [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]] 11345 // CHECK21-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP27]] 11346 // CHECK21-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX24]], i64 1 11347 // CHECK21-NEXT: store i16 [[CONV23]], ptr [[ARRAYIDX25]], align 2 11348 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] 11349 // CHECK21: omp.body.continue26: 11350 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] 11351 // CHECK21: omp.inner.for.inc27: 11352 // CHECK21-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 11353 // CHECK21-NEXT: [[ADD28:%.*]] = add i64 [[TMP28]], 1 11354 // CHECK21-NEXT: store i64 [[ADD28]], ptr [[DOTOMP_IV]], align 8 11355 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP30:![0-9]+]] 11356 // CHECK21: omp.inner.for.end29: 11357 // CHECK21-NEXT: br label [[OMP_IF_END]] 11358 // CHECK21: omp_if.end: 11359 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11360 // CHECK21: omp.loop.exit: 11361 // CHECK21-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 11362 // CHECK21-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4 11363 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]]) 11364 // CHECK21-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11365 // CHECK21-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 11366 // CHECK21-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11367 // CHECK21: .omp.final.then: 11368 // CHECK21-NEXT: store i64 400, ptr [[IT]], align 8 11369 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11370 // CHECK21: .omp.final.done: 11371 // CHECK21-NEXT: ret void 11372 // 11373 // 11374 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 11375 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11376 // CHECK21-NEXT: entry: 11377 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11378 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11379 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 11380 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11381 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11382 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 11383 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 11384 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 11385 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 11386 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 11387 // CHECK21-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 11388 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 11389 // CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 11390 // CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 11391 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 11392 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) 11393 // CHECK21-NEXT: ret void 11394 // 11395 // 11396 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined 11397 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 11398 // CHECK21-NEXT: entry: 11399 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 11400 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 11401 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11402 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11403 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 11404 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11405 // CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8 11406 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11407 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11408 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11409 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11410 // CHECK21-NEXT: [[I:%.*]] = alloca i64, align 8 11411 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 11412 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 11413 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 11414 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 11415 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 11416 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 11417 // CHECK21-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 11418 // CHECK21-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 11419 // CHECK21-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 11420 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11421 // CHECK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 11422 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 11423 // CHECK21-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 11424 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11425 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 11426 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11427 // CHECK21: cond.true: 11428 // CHECK21-NEXT: br label [[COND_END:%.*]] 11429 // CHECK21: cond.false: 11430 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11431 // CHECK21-NEXT: br label [[COND_END]] 11432 // CHECK21: cond.end: 11433 // CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 11434 // CHECK21-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 11435 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 11436 // CHECK21-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 11437 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11438 // CHECK21: omp.inner.for.cond: 11439 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32:![0-9]+]] 11440 // CHECK21-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP32]] 11441 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 11442 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11443 // CHECK21: omp.inner.for.body: 11444 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32]] 11445 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 11446 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 11447 // CHECK21-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP32]] 11448 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] 11449 // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 11450 // CHECK21-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] 11451 // CHECK21-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] 11452 // CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 11453 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 11454 // CHECK21-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 11455 // CHECK21-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] 11456 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 11457 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] 11458 // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 11459 // CHECK21-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] 11460 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11461 // CHECK21: omp.body.continue: 11462 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11463 // CHECK21: omp.inner.for.inc: 11464 // CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32]] 11465 // CHECK21-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 11466 // CHECK21-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32]] 11467 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] 11468 // CHECK21: omp.inner.for.end: 11469 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11470 // CHECK21: omp.loop.exit: 11471 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 11472 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11473 // CHECK21-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 11474 // CHECK21-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11475 // CHECK21: .omp.final.then: 11476 // CHECK21-NEXT: store i64 11, ptr [[I]], align 8 11477 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11478 // CHECK21: .omp.final.done: 11479 // CHECK21-NEXT: ret void 11480 // 11481 // 11482 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 11483 // CHECK23-SAME: () #[[ATTR0:[0-9]+]] { 11484 // CHECK23-NEXT: entry: 11485 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) 11486 // CHECK23-NEXT: ret void 11487 // 11488 // 11489 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined 11490 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 11491 // CHECK23-NEXT: entry: 11492 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 11493 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 11494 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11495 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 11496 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11497 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11498 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11499 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11500 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 11501 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 11502 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 11503 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 11504 // CHECK23-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4 11505 // CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 11506 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11507 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 11508 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 11509 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 11510 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11511 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 11512 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11513 // CHECK23: cond.true: 11514 // CHECK23-NEXT: br label [[COND_END:%.*]] 11515 // CHECK23: cond.false: 11516 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11517 // CHECK23-NEXT: br label [[COND_END]] 11518 // CHECK23: cond.end: 11519 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 11520 // CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 11521 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 11522 // CHECK23-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 11523 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11524 // CHECK23: omp.inner.for.cond: 11525 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 11526 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] 11527 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 11528 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11529 // CHECK23: omp.inner.for.body: 11530 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 11531 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 11532 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 11533 // CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] 11534 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11535 // CHECK23: omp.body.continue: 11536 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11537 // CHECK23: omp.inner.for.inc: 11538 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 11539 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 11540 // CHECK23-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 11541 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 11542 // CHECK23: omp.inner.for.end: 11543 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11544 // CHECK23: omp.loop.exit: 11545 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 11546 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11547 // CHECK23-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 11548 // CHECK23-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11549 // CHECK23: .omp.final.then: 11550 // CHECK23-NEXT: store i32 33, ptr [[I]], align 4 11551 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 11552 // CHECK23: .omp.final.done: 11553 // CHECK23-NEXT: ret void 11554 // 11555 // 11556 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 11557 // CHECK23-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 11558 // CHECK23-NEXT: entry: 11559 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11560 // CHECK23-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 11561 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11562 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11563 // CHECK23-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 11564 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11565 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 11566 // CHECK23-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 11567 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11568 // CHECK23-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 11569 // CHECK23-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 11570 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 11571 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 11572 // CHECK23-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 11573 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 11574 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 11575 // CHECK23-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 11576 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4 11577 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 11578 // CHECK23-NEXT: ret void 11579 // 11580 // 11581 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined 11582 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 11583 // CHECK23-NEXT: entry: 11584 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 11585 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 11586 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11587 // CHECK23-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 11588 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11589 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11590 // CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4 11591 // CHECK23-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 11592 // CHECK23-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 11593 // CHECK23-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 11594 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11595 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11596 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11597 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11598 // CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 8 11599 // CHECK23-NEXT: [[LIN2:%.*]] = alloca i32, align 4 11600 // CHECK23-NEXT: [[A3:%.*]] = alloca i32, align 4 11601 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 11602 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 11603 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 11604 // CHECK23-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 11605 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11606 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 11607 // CHECK23-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 11608 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 11609 // CHECK23-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 11610 // CHECK23-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 11611 // CHECK23-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 11612 // CHECK23-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 11613 // CHECK23-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 11614 // CHECK23-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 11615 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11616 // CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 11617 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 11618 // CHECK23-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 11619 // CHECK23-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 11620 // CHECK23-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11621 // CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 11622 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11623 // CHECK23: cond.true: 11624 // CHECK23-NEXT: br label [[COND_END:%.*]] 11625 // CHECK23: cond.false: 11626 // CHECK23-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 11627 // CHECK23-NEXT: br label [[COND_END]] 11628 // CHECK23: cond.end: 11629 // CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 11630 // CHECK23-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 11631 // CHECK23-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 11632 // CHECK23-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8 11633 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11634 // CHECK23: omp.inner.for.cond: 11635 // CHECK23-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]] 11636 // CHECK23-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]] 11637 // CHECK23-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 11638 // CHECK23-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11639 // CHECK23: omp.inner.for.body: 11640 // CHECK23-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11641 // CHECK23-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 11642 // CHECK23-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 11643 // CHECK23-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP18]] 11644 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP18]] 11645 // CHECK23-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64 11646 // CHECK23-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11647 // CHECK23-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]] 11648 // CHECK23-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]] 11649 // CHECK23-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]] 11650 // CHECK23-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32 11651 // CHECK23-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP18]] 11652 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP18]] 11653 // CHECK23-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 11654 // CHECK23-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11655 // CHECK23-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]] 11656 // CHECK23-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]] 11657 // CHECK23-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]] 11658 // CHECK23-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32 11659 // CHECK23-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP18]] 11660 // CHECK23-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]] 11661 // CHECK23-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32 11662 // CHECK23-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1 11663 // CHECK23-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 11664 // CHECK23-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]] 11665 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11666 // CHECK23: omp.body.continue: 11667 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11668 // CHECK23: omp.inner.for.inc: 11669 // CHECK23-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11670 // CHECK23-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1 11671 // CHECK23-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11672 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 11673 // CHECK23: omp.inner.for.end: 11674 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11675 // CHECK23: omp.loop.exit: 11676 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 11677 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11678 // CHECK23-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 11679 // CHECK23-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11680 // CHECK23: .omp.final.then: 11681 // CHECK23-NEXT: store i64 400, ptr [[IT]], align 8 11682 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 11683 // CHECK23: .omp.final.done: 11684 // CHECK23-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11685 // CHECK23-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 11686 // CHECK23-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 11687 // CHECK23: .omp.linear.pu: 11688 // CHECK23-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 4 11689 // CHECK23-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 4 11690 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 4 11691 // CHECK23-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 4 11692 // CHECK23-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 11693 // CHECK23: .omp.linear.pu.done: 11694 // CHECK23-NEXT: ret void 11695 // 11696 // 11697 // CHECK23-LABEL: define {{[^@]+}}@_Z7get_valv 11698 // CHECK23-SAME: () #[[ATTR3:[0-9]+]] { 11699 // CHECK23-NEXT: entry: 11700 // CHECK23-NEXT: ret i64 0 11701 // 11702 // 11703 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 11704 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 11705 // CHECK23-NEXT: entry: 11706 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11707 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11708 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11709 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11710 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11711 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 11712 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 11713 // CHECK23-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 11714 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 11715 // CHECK23-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 11716 // CHECK23-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 11717 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 11718 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) 11719 // CHECK23-NEXT: ret void 11720 // 11721 // 11722 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined 11723 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 11724 // CHECK23-NEXT: entry: 11725 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 11726 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 11727 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11728 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11729 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11730 // CHECK23-NEXT: [[TMP:%.*]] = alloca i16, align 2 11731 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11732 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11733 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11734 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11735 // CHECK23-NEXT: [[IT:%.*]] = alloca i16, align 2 11736 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 11737 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 11738 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11739 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 11740 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 11741 // CHECK23-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 11742 // CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 11743 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11744 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 11745 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 11746 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 11747 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11748 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 11749 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11750 // CHECK23: cond.true: 11751 // CHECK23-NEXT: br label [[COND_END:%.*]] 11752 // CHECK23: cond.false: 11753 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11754 // CHECK23-NEXT: br label [[COND_END]] 11755 // CHECK23: cond.end: 11756 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 11757 // CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 11758 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 11759 // CHECK23-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 11760 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11761 // CHECK23: omp.inner.for.cond: 11762 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] 11763 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] 11764 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 11765 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11766 // CHECK23: omp.inner.for.body: 11767 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 11768 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 11769 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 11770 // CHECK23-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16 11771 // CHECK23-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP21]] 11772 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] 11773 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 11774 // CHECK23-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] 11775 // CHECK23-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]] 11776 // CHECK23-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 11777 // CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 11778 // CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 11779 // CHECK23-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]] 11780 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11781 // CHECK23: omp.body.continue: 11782 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11783 // CHECK23: omp.inner.for.inc: 11784 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 11785 // CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 11786 // CHECK23-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 11787 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 11788 // CHECK23: omp.inner.for.end: 11789 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11790 // CHECK23: omp.loop.exit: 11791 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 11792 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11793 // CHECK23-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 11794 // CHECK23-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11795 // CHECK23: .omp.final.then: 11796 // CHECK23-NEXT: store i16 22, ptr [[IT]], align 2 11797 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 11798 // CHECK23: .omp.final.done: 11799 // CHECK23-NEXT: ret void 11800 // 11801 // 11802 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 11803 // CHECK23-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 11804 // CHECK23-NEXT: entry: 11805 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11806 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 11807 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11808 // CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 11809 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 11810 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11811 // CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 11812 // CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 11813 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 11814 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 11815 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11816 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 11817 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11818 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 11819 // CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 11820 // CHECK23-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 11821 // CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 11822 // CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 11823 // CHECK23-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 11824 // CHECK23-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 11825 // CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 11826 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 11827 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 11828 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 11829 // CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 11830 // CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 11831 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 11832 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 11833 // CHECK23-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 11834 // CHECK23-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 11835 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 11836 // CHECK23-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 11837 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 11838 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 11839 // CHECK23-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 11840 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 11841 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]]) 11842 // CHECK23-NEXT: ret void 11843 // 11844 // 11845 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined 11846 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 11847 // CHECK23-NEXT: entry: 11848 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 11849 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 11850 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11851 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 11852 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11853 // CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 11854 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 11855 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11856 // CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 11857 // CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 11858 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 11859 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 11860 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11861 // CHECK23-NEXT: [[TMP:%.*]] = alloca i8, align 1 11862 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11863 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11864 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11865 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11866 // CHECK23-NEXT: [[IT:%.*]] = alloca i8, align 1 11867 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 11868 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 11869 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 11870 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 11871 // CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 11872 // CHECK23-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 11873 // CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 11874 // CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 11875 // CHECK23-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 11876 // CHECK23-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 11877 // CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 11878 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 11879 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 11880 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 11881 // CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 11882 // CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 11883 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 11884 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 11885 // CHECK23-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 11886 // CHECK23-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 11887 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 11888 // CHECK23-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4 11889 // CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 11890 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 11891 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 11892 // CHECK23-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 11893 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 11894 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 11895 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 11896 // CHECK23: omp.dispatch.cond: 11897 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11898 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 11899 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11900 // CHECK23: cond.true: 11901 // CHECK23-NEXT: br label [[COND_END:%.*]] 11902 // CHECK23: cond.false: 11903 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11904 // CHECK23-NEXT: br label [[COND_END]] 11905 // CHECK23: cond.end: 11906 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 11907 // CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 11908 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 11909 // CHECK23-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 11910 // CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 11911 // CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11912 // CHECK23-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 11913 // CHECK23-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 11914 // CHECK23: omp.dispatch.body: 11915 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11916 // CHECK23: omp.inner.for.cond: 11917 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] 11918 // CHECK23-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]] 11919 // CHECK23-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 11920 // CHECK23-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11921 // CHECK23: omp.inner.for.body: 11922 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 11923 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 11924 // CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 11925 // CHECK23-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 11926 // CHECK23-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP24]] 11927 // CHECK23-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] 11928 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 11929 // CHECK23-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] 11930 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 11931 // CHECK23-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 11932 // CHECK23-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 11933 // CHECK23-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 11934 // CHECK23-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 11935 // CHECK23-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 11936 // CHECK23-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 11937 // CHECK23-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]] 11938 // CHECK23-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 11939 // CHECK23-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 11940 // CHECK23-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 11941 // CHECK23-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]] 11942 // CHECK23-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 11943 // CHECK23-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 11944 // CHECK23-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] 11945 // CHECK23-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 11946 // CHECK23-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] 11947 // CHECK23-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 11948 // CHECK23-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]] 11949 // CHECK23-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3 11950 // CHECK23-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]] 11951 // CHECK23-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 11952 // CHECK23-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]] 11953 // CHECK23-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 11954 // CHECK23-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP24]] 11955 // CHECK23-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 11956 // CHECK23-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP24]] 11957 // CHECK23-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 11958 // CHECK23-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP24]] 11959 // CHECK23-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 11960 // CHECK23-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 11961 // CHECK23-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 11962 // CHECK23-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP24]] 11963 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11964 // CHECK23: omp.body.continue: 11965 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11966 // CHECK23: omp.inner.for.inc: 11967 // CHECK23-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 11968 // CHECK23-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 11969 // CHECK23-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 11970 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 11971 // CHECK23: omp.inner.for.end: 11972 // CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 11973 // CHECK23: omp.dispatch.inc: 11974 // CHECK23-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 11975 // CHECK23-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 11976 // CHECK23-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 11977 // CHECK23-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 11978 // CHECK23-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 11979 // CHECK23-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 11980 // CHECK23-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 11981 // CHECK23-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 11982 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND]] 11983 // CHECK23: omp.dispatch.end: 11984 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 11985 // CHECK23-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 11986 // CHECK23-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 11987 // CHECK23-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11988 // CHECK23: .omp.final.then: 11989 // CHECK23-NEXT: store i8 96, ptr [[IT]], align 1 11990 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 11991 // CHECK23: .omp.final.done: 11992 // CHECK23-NEXT: ret void 11993 // 11994 // 11995 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 11996 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11997 // CHECK23-NEXT: entry: 11998 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11999 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12000 // CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 12001 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 12002 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 12003 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12004 // CHECK23-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 12005 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 12006 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 12007 // CHECK23-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 12008 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 12009 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 12010 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 12011 // CHECK23-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 12012 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 12013 // CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 12014 // CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 12015 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 12016 // CHECK23-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 12017 // CHECK23-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 12018 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 12019 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]]) 12020 // CHECK23-NEXT: ret void 12021 // 12022 // 12023 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined 12024 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 12025 // CHECK23-NEXT: entry: 12026 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 12027 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 12028 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12029 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12030 // CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 12031 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 12032 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 12033 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 12034 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 12035 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 12036 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 12037 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 12038 // CHECK23-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 12039 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 12040 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 12041 // CHECK23-NEXT: ret void 12042 // 12043 // 12044 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 12045 // CHECK23-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 12046 // CHECK23-NEXT: entry: 12047 // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 12048 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 12049 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 12050 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 12051 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 12052 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 12053 // CHECK23-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 12054 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 12055 // CHECK23-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 12056 // CHECK23-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 12057 // CHECK23-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 12058 // CHECK23-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 12059 // CHECK23-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 12060 // CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 12061 // CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 12062 // CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 12063 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 12064 // CHECK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 12065 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 12066 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 12067 // CHECK23-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 4 12068 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4 12069 // CHECK23-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 12070 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4 12071 // CHECK23-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 12072 // CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 12073 // CHECK23-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 12074 // CHECK23-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 12075 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 12076 // CHECK23-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 12077 // CHECK23-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1 12078 // CHECK23-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12079 // CHECK23: omp_if.then: 12080 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) 12081 // CHECK23-NEXT: br label [[OMP_IF_END:%.*]] 12082 // CHECK23: omp_if.else: 12083 // CHECK23-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 12084 // CHECK23-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 12085 // CHECK23-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 12086 // CHECK23-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) #[[ATTR2:[0-9]+]] 12087 // CHECK23-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) 12088 // CHECK23-NEXT: br label [[OMP_IF_END]] 12089 // CHECK23: omp_if.end: 12090 // CHECK23-NEXT: ret void 12091 // 12092 // 12093 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined 12094 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 12095 // CHECK23-NEXT: entry: 12096 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 12097 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 12098 // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 12099 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 12100 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 12101 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 12102 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 12103 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 12104 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 12105 // CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4 12106 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 12107 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 12108 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 12109 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12110 // CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 8 12111 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 12112 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 12113 // CHECK23-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 12114 // CHECK23-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 12115 // CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 12116 // CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 12117 // CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 12118 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 12119 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 12120 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 12121 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 12122 // CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 12123 // CHECK23-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 12124 // CHECK23-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 12125 // CHECK23-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 12126 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 12127 // CHECK23-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 12128 // CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 12129 // CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12130 // CHECK23: omp_if.then: 12131 // CHECK23-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 12132 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 12133 // CHECK23-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 12134 // CHECK23-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 12135 // CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 12136 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12137 // CHECK23: cond.true: 12138 // CHECK23-NEXT: br label [[COND_END:%.*]] 12139 // CHECK23: cond.false: 12140 // CHECK23-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 12141 // CHECK23-NEXT: br label [[COND_END]] 12142 // CHECK23: cond.end: 12143 // CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 12144 // CHECK23-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 12145 // CHECK23-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 12146 // CHECK23-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV]], align 8 12147 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12148 // CHECK23: omp.inner.for.cond: 12149 // CHECK23-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27:![0-9]+]] 12150 // CHECK23-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP27]] 12151 // CHECK23-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 12152 // CHECK23-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12153 // CHECK23: omp.inner.for.body: 12154 // CHECK23-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 12155 // CHECK23-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 12156 // CHECK23-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 12157 // CHECK23-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP27]] 12158 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 12159 // CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double 12160 // CHECK23-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 12161 // CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 12162 // CHECK23-NEXT: store double [[ADD]], ptr [[A]], align 4, !nontemporal !28, !llvm.access.group [[ACC_GRP27]] 12163 // CHECK23-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 12164 // CHECK23-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 4, !nontemporal !28, !llvm.access.group [[ACC_GRP27]] 12165 // CHECK23-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 12166 // CHECK23-NEXT: store double [[INC]], ptr [[A4]], align 4, !nontemporal !28, !llvm.access.group [[ACC_GRP27]] 12167 // CHECK23-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 12168 // CHECK23-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]] 12169 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP15]] 12170 // CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 12171 // CHECK23-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP27]] 12172 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12173 // CHECK23: omp.body.continue: 12174 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12175 // CHECK23: omp.inner.for.inc: 12176 // CHECK23-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 12177 // CHECK23-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1 12178 // CHECK23-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 12179 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] 12180 // CHECK23: omp.inner.for.end: 12181 // CHECK23-NEXT: br label [[OMP_IF_END:%.*]] 12182 // CHECK23: omp_if.else: 12183 // CHECK23-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 12184 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 12185 // CHECK23-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP18]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 12186 // CHECK23-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 12187 // CHECK23-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[TMP19]], 3 12188 // CHECK23-NEXT: br i1 [[CMP8]], label [[COND_TRUE9:%.*]], label [[COND_FALSE10:%.*]] 12189 // CHECK23: cond.true9: 12190 // CHECK23-NEXT: br label [[COND_END11:%.*]] 12191 // CHECK23: cond.false10: 12192 // CHECK23-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 12193 // CHECK23-NEXT: br label [[COND_END11]] 12194 // CHECK23: cond.end11: 12195 // CHECK23-NEXT: [[COND12:%.*]] = phi i64 [ 3, [[COND_TRUE9]] ], [ [[TMP20]], [[COND_FALSE10]] ] 12196 // CHECK23-NEXT: store i64 [[COND12]], ptr [[DOTOMP_UB]], align 8 12197 // CHECK23-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 12198 // CHECK23-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV]], align 8 12199 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 12200 // CHECK23: omp.inner.for.cond13: 12201 // CHECK23-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 12202 // CHECK23-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 12203 // CHECK23-NEXT: [[CMP14:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 12204 // CHECK23-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END29:%.*]] 12205 // CHECK23: omp.inner.for.body15: 12206 // CHECK23-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 12207 // CHECK23-NEXT: [[MUL16:%.*]] = mul i64 [[TMP24]], 400 12208 // CHECK23-NEXT: [[SUB17:%.*]] = sub i64 2000, [[MUL16]] 12209 // CHECK23-NEXT: store i64 [[SUB17]], ptr [[IT]], align 8 12210 // CHECK23-NEXT: [[TMP25:%.*]] = load i32, ptr [[B_ADDR]], align 4 12211 // CHECK23-NEXT: [[CONV18:%.*]] = sitofp i32 [[TMP25]] to double 12212 // CHECK23-NEXT: [[ADD19:%.*]] = fadd double [[CONV18]], 1.500000e+00 12213 // CHECK23-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 12214 // CHECK23-NEXT: store double [[ADD19]], ptr [[A20]], align 4 12215 // CHECK23-NEXT: [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 12216 // CHECK23-NEXT: [[TMP26:%.*]] = load double, ptr [[A21]], align 4 12217 // CHECK23-NEXT: [[INC22:%.*]] = fadd double [[TMP26]], 1.000000e+00 12218 // CHECK23-NEXT: store double [[INC22]], ptr [[A21]], align 4 12219 // CHECK23-NEXT: [[CONV23:%.*]] = fptosi double [[INC22]] to i16 12220 // CHECK23-NEXT: [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]] 12221 // CHECK23-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP27]] 12222 // CHECK23-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX24]], i32 1 12223 // CHECK23-NEXT: store i16 [[CONV23]], ptr [[ARRAYIDX25]], align 2 12224 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] 12225 // CHECK23: omp.body.continue26: 12226 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] 12227 // CHECK23: omp.inner.for.inc27: 12228 // CHECK23-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 12229 // CHECK23-NEXT: [[ADD28:%.*]] = add i64 [[TMP28]], 1 12230 // CHECK23-NEXT: store i64 [[ADD28]], ptr [[DOTOMP_IV]], align 8 12231 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP31:![0-9]+]] 12232 // CHECK23: omp.inner.for.end29: 12233 // CHECK23-NEXT: br label [[OMP_IF_END]] 12234 // CHECK23: omp_if.end: 12235 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12236 // CHECK23: omp.loop.exit: 12237 // CHECK23-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 12238 // CHECK23-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4 12239 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]]) 12240 // CHECK23-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 12241 // CHECK23-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 12242 // CHECK23-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12243 // CHECK23: .omp.final.then: 12244 // CHECK23-NEXT: store i64 400, ptr [[IT]], align 8 12245 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12246 // CHECK23: .omp.final.done: 12247 // CHECK23-NEXT: ret void 12248 // 12249 // 12250 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 12251 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 12252 // CHECK23-NEXT: entry: 12253 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12254 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12255 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 12256 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 12257 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12258 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 12259 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 12260 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 12261 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 12262 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 12263 // CHECK23-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 12264 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 12265 // CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 12266 // CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 12267 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 12268 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) 12269 // CHECK23-NEXT: ret void 12270 // 12271 // 12272 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined 12273 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 12274 // CHECK23-NEXT: entry: 12275 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 12276 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 12277 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12278 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12279 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 12280 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 12281 // CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4 12282 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 12283 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 12284 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 12285 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12286 // CHECK23-NEXT: [[I:%.*]] = alloca i64, align 8 12287 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 12288 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 12289 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 12290 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 12291 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 12292 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 12293 // CHECK23-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 12294 // CHECK23-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8 12295 // CHECK23-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 12296 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 12297 // CHECK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 12298 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 12299 // CHECK23-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 12300 // CHECK23-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 12301 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 12302 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12303 // CHECK23: cond.true: 12304 // CHECK23-NEXT: br label [[COND_END:%.*]] 12305 // CHECK23: cond.false: 12306 // CHECK23-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 12307 // CHECK23-NEXT: br label [[COND_END]] 12308 // CHECK23: cond.end: 12309 // CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 12310 // CHECK23-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 12311 // CHECK23-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 12312 // CHECK23-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 12313 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12314 // CHECK23: omp.inner.for.cond: 12315 // CHECK23-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33:![0-9]+]] 12316 // CHECK23-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP33]] 12317 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 12318 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12319 // CHECK23: omp.inner.for.body: 12320 // CHECK23-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33]] 12321 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 12322 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 12323 // CHECK23-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP33]] 12324 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 12325 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 12326 // CHECK23-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 12327 // CHECK23-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] 12328 // CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 12329 // CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 12330 // CHECK23-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 12331 // CHECK23-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] 12332 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 12333 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] 12334 // CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 12335 // CHECK23-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] 12336 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12337 // CHECK23: omp.body.continue: 12338 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12339 // CHECK23: omp.inner.for.inc: 12340 // CHECK23-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33]] 12341 // CHECK23-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1 12342 // CHECK23-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33]] 12343 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 12344 // CHECK23: omp.inner.for.end: 12345 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12346 // CHECK23: omp.loop.exit: 12347 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 12348 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 12349 // CHECK23-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 12350 // CHECK23-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12351 // CHECK23: .omp.final.then: 12352 // CHECK23-NEXT: store i64 11, ptr [[I]], align 8 12353 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12354 // CHECK23: .omp.final.done: 12355 // CHECK23-NEXT: ret void 12356 // 12357