1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s 4 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 7 8 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 9 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s 10 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 12 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // expected-no-diagnostics 14 #ifndef HEADER 15 #define HEADER 16 17 struct St { 18 int a, b; 19 St() : a(0), b(0) {} 20 St(const St &st) : a(st.a + st.b), b(0) {} 21 ~St() {} 22 }; 23 24 volatile int g = 1212; 25 26 template <class T> 27 struct S { 28 T f; 29 S(T a) : f(a + g) {} 30 S() : f(g) {} 31 S(const S &s, St t = St()) : f(s.f + t.a) {} 32 operator T() { return T(); } 33 ~S() {} 34 }; 35 36 37 template <typename T> 38 T tmain() { 39 S<T> test; 40 T t_var = T(); 41 T vec[] = {1, 2}; 42 S<T> s_arr[] = {1, 2}; 43 S<T> var(3); 44 #pragma omp parallel 45 #pragma omp sections firstprivate(t_var, vec, s_arr, var) 46 { 47 vec[0] = t_var; 48 #pragma omp section 49 s_arr[0] = var; 50 } 51 return T(); 52 } 53 54 S<float> test; 55 int t_var = 333; 56 int vec[] = {1, 2}; 57 S<float> s_arr[] = {1, 2}; 58 S<float> var(3); 59 60 int main() { 61 static int sivar; 62 #ifdef LAMBDA 63 [&]() { 64 #pragma omp parallel 65 #pragma omp sections firstprivate(g, sivar) 66 { 67 // Skip temp vars for loop 68 69 70 71 { 72 g = 1; 73 sivar = 10; 74 } 75 #pragma omp section 76 [&]() { 77 g = 2; 78 sivar = 20; 79 }(); 80 } 81 }(); 82 return 0; 83 #elif defined(BLOCKS) 84 ^{ 85 #pragma omp parallel 86 #pragma omp sections firstprivate(g, sivar) 87 { 88 // Skip temp vars for loop 89 90 91 92 { 93 g = 1; 94 sivar = 10; 95 } 96 #pragma omp section 97 ^{ 98 g = 2; 99 sivar = 20; 100 }(); 101 } 102 }(); 103 return 0; 104 #else 105 #pragma omp sections firstprivate(t_var, vec, s_arr, var, sivar) nowait 106 { 107 { 108 vec[0] = t_var; 109 s_arr[0] = var; 110 sivar = 31; 111 } 112 } 113 return tmain<int>(); 114 #endif 115 } 116 117 118 // firstprivate t_var(t_var) 119 120 // firstprivate vec(vec) 121 122 // firstprivate s_arr(s_arr) 123 124 // firstprivate var(var) 125 126 // firstprivate isvar 127 128 129 // ~(firstprivate var), ~(firstprivate s_arr) 130 131 132 133 // Skip temp vars for loop 134 135 136 // firstprivate t_var(t_var) 137 138 // firstprivate vec(vec) 139 140 // firstprivate s_arr(s_arr) 141 142 // firstprivate var(var) 143 144 // No synchronization for initialization. 145 146 147 // ~(firstprivate var), ~(firstprivate s_arr) 148 #endif 149 150 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 151 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { 152 // CHECK1-NEXT: entry: 153 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 154 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 155 // CHECK1-NEXT: ret void 156 // 157 // 158 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 159 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 160 // CHECK1-NEXT: entry: 161 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 162 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 163 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 164 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 165 // CHECK1-NEXT: ret void 166 // 167 // 168 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 169 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 170 // CHECK1-NEXT: entry: 171 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 172 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 173 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 174 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 175 // CHECK1-NEXT: ret void 176 // 177 // 178 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 179 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 180 // CHECK1-NEXT: entry: 181 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 182 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 183 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 184 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 185 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 186 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 187 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 188 // CHECK1-NEXT: ret void 189 // 190 // 191 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 192 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 193 // CHECK1-NEXT: entry: 194 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 195 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 196 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 197 // CHECK1-NEXT: ret void 198 // 199 // 200 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 201 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 202 // CHECK1-NEXT: entry: 203 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 204 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 205 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 206 // CHECK1-NEXT: ret void 207 // 208 // 209 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 210 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 211 // CHECK1-NEXT: entry: 212 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 213 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 214 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 215 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 216 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 217 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 218 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 219 // CHECK1-NEXT: ret void 220 // 221 // 222 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 223 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 224 // CHECK1-NEXT: entry: 225 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 226 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 227 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 228 // CHECK1: arraydestroy.body: 229 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 230 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 231 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 232 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 233 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 234 // CHECK1: arraydestroy.done1: 235 // CHECK1-NEXT: ret void 236 // 237 // 238 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 239 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 240 // CHECK1-NEXT: entry: 241 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 242 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 243 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 244 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 245 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 246 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 247 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 248 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 249 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 250 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 251 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 252 // CHECK1-NEXT: ret void 253 // 254 // 255 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 256 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 257 // CHECK1-NEXT: entry: 258 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 259 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 260 // CHECK1-NEXT: ret void 261 // 262 // 263 // CHECK1-LABEL: define {{[^@]+}}@main 264 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 265 // CHECK1-NEXT: entry: 266 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 267 // CHECK1-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 268 // CHECK1-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 269 // CHECK1-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 270 // CHECK1-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 271 // CHECK1-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 272 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 273 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 274 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 275 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 276 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 277 // CHECK1-NEXT: [[AGG_TMP2:%.*]] = alloca [[STRUCT_ST]], align 4 278 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 279 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 280 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 281 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4 282 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_UB_]], align 4 283 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4 284 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4 285 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr @t_var, align 4 286 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[T_VAR]], align 4 287 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @vec, i64 8, i1 false) 288 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 289 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 290 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP2]] 291 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 292 // CHECK1: omp.arraycpy.body: 293 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ @s_arr, [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 294 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 295 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 296 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 297 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 298 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 299 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 300 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP2]] 301 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] 302 // CHECK1: omp.arraycpy.done1: 303 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) 304 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], ptr noundef nonnull align 4 dereferenceable(4) @var, ptr noundef [[AGG_TMP2]]) 305 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] 306 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 307 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[SIVAR]], align 4 308 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_SECTIONS_IL_]], ptr [[DOTOMP_SECTIONS_LB_]], ptr [[DOTOMP_SECTIONS_UB_]], ptr [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) 309 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4 310 // CHECK1-NEXT: [[TMP5:%.*]] = icmp slt i32 [[TMP4]], 0 311 // CHECK1-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], i32 [[TMP4]], i32 0 312 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_SECTIONS_UB_]], align 4 313 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_LB_]], align 4 314 // CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_SECTIONS_IV_]], align 4 315 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 316 // CHECK1: omp.inner.for.cond: 317 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4 318 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4 319 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 320 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 321 // CHECK1: omp.inner.for.body: 322 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4 323 // CHECK1-NEXT: switch i32 [[TMP10]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ 324 // CHECK1-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] 325 // CHECK1-NEXT: ] 326 // CHECK1: .omp.sections.case: 327 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[T_VAR]], align 4 328 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 329 // CHECK1-NEXT: store i32 [[TMP11]], ptr [[ARRAYIDX]], align 4 330 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 331 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) 332 // CHECK1-NEXT: store i32 31, ptr [[SIVAR]], align 4 333 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 334 // CHECK1: .omp.sections.exit: 335 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 336 // CHECK1: omp.inner.for.inc: 337 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4 338 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 339 // CHECK1-NEXT: store i32 [[INC]], ptr [[DOTOMP_SECTIONS_IV_]], align 4 340 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 341 // CHECK1: omp.inner.for.end: 342 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) 343 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 344 // CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 345 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i64 2 346 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 347 // CHECK1: arraydestroy.body: 348 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 349 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 350 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 351 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 352 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 353 // CHECK1: arraydestroy.done5: 354 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 355 // CHECK1-NEXT: ret i32 [[CALL]] 356 // 357 // 358 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev 359 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 360 // CHECK1-NEXT: entry: 361 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 362 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 363 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 364 // CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 365 // CHECK1-NEXT: ret void 366 // 367 // 368 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 369 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 370 // CHECK1-NEXT: entry: 371 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 372 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 373 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 374 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 375 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 376 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 377 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 378 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 379 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 380 // CHECK1-NEXT: ret void 381 // 382 // 383 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev 384 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 385 // CHECK1-NEXT: entry: 386 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 387 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 388 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 389 // CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 390 // CHECK1-NEXT: ret void 391 // 392 // 393 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 394 // CHECK1-SAME: () #[[ATTR1]] { 395 // CHECK1-NEXT: entry: 396 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 397 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 398 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 399 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 400 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 401 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 402 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 403 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 404 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 405 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 406 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 407 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 408 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) 409 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]]) 410 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 411 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 412 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 413 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 414 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 415 // CHECK1: arraydestroy.body: 416 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 417 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 418 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 419 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 420 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 421 // CHECK1: arraydestroy.done1: 422 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 423 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 424 // CHECK1-NEXT: ret i32 [[TMP1]] 425 // 426 // 427 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev 428 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 429 // CHECK1-NEXT: entry: 430 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 431 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 432 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 433 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 434 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 435 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 436 // CHECK1-NEXT: store i32 0, ptr [[B]], align 4 437 // CHECK1-NEXT: ret void 438 // 439 // 440 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 441 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 442 // CHECK1-NEXT: entry: 443 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 444 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 445 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 446 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 447 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 448 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 449 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 450 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 451 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 452 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 453 // CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 454 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 455 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 456 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 457 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 458 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 459 // CHECK1-NEXT: ret void 460 // 461 // 462 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev 463 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 464 // CHECK1-NEXT: entry: 465 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 466 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 467 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 468 // CHECK1-NEXT: ret void 469 // 470 // 471 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 472 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 473 // CHECK1-NEXT: entry: 474 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 475 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 476 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 477 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 478 // CHECK1-NEXT: ret void 479 // 480 // 481 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 482 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 483 // CHECK1-NEXT: entry: 484 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 485 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 486 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 487 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 488 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 489 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 490 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 491 // CHECK1-NEXT: ret void 492 // 493 // 494 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined 495 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5:[0-9]+]] { 496 // CHECK1-NEXT: entry: 497 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 498 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 499 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 500 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 501 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 502 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 503 // CHECK1-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 504 // CHECK1-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 505 // CHECK1-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 506 // CHECK1-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 507 // CHECK1-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 508 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 509 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 510 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 511 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 512 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 513 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 514 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 515 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 516 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 517 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 518 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 519 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 520 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 521 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 522 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 523 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 524 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4 525 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_UB_]], align 4 526 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4 527 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4 528 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP0]], align 4 529 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[T_VAR1]], align 4 530 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP1]], i64 8, i1 false) 531 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 532 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 533 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 534 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 535 // CHECK1: omp.arraycpy.body: 536 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 537 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 538 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 539 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) 540 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 541 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 542 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 543 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 544 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 545 // CHECK1: omp.arraycpy.done4: 546 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 547 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP3]], ptr noundef [[AGG_TMP6]]) 548 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 549 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 550 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 551 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_SECTIONS_IL_]], ptr [[DOTOMP_SECTIONS_LB_]], ptr [[DOTOMP_SECTIONS_UB_]], ptr [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) 552 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4 553 // CHECK1-NEXT: [[TMP9:%.*]] = icmp slt i32 [[TMP8]], 1 554 // CHECK1-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], i32 [[TMP8]], i32 1 555 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_SECTIONS_UB_]], align 4 556 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_LB_]], align 4 557 // CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_SECTIONS_IV_]], align 4 558 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 559 // CHECK1: omp.inner.for.cond: 560 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4 561 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4 562 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 563 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 564 // CHECK1: omp.inner.for.body: 565 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4 566 // CHECK1-NEXT: switch i32 [[TMP14]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ 567 // CHECK1-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] 568 // CHECK1-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE7:%.*]] 569 // CHECK1-NEXT: ] 570 // CHECK1: .omp.sections.case: 571 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR1]], align 4 572 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0 573 // CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 574 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 575 // CHECK1: .omp.sections.case7: 576 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 0 577 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR5]], i64 4, i1 false) 578 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 579 // CHECK1: .omp.sections.exit: 580 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 581 // CHECK1: omp.inner.for.inc: 582 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4 583 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP16]], 1 584 // CHECK1-NEXT: store i32 [[INC]], ptr [[DOTOMP_SECTIONS_IV_]], align 4 585 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 586 // CHECK1: omp.inner.for.end: 587 // CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 588 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 589 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP18]]) 590 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 591 // CHECK1-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 592 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 2 593 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 594 // CHECK1: arraydestroy.body: 595 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 596 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 597 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 598 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] 599 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] 600 // CHECK1: arraydestroy.done10: 601 // CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 602 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 603 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP21]]) 604 // CHECK1-NEXT: ret void 605 // 606 // 607 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 608 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 609 // CHECK1-NEXT: entry: 610 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 611 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 612 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 613 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 614 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 615 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 616 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 617 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 618 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) 619 // CHECK1-NEXT: ret void 620 // 621 // 622 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 623 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 624 // CHECK1-NEXT: entry: 625 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 626 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 627 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 628 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 629 // CHECK1-NEXT: ret void 630 // 631 // 632 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 633 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 634 // CHECK1-NEXT: entry: 635 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 636 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 637 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 638 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 639 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 640 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 641 // CHECK1-NEXT: ret void 642 // 643 // 644 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 645 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 646 // CHECK1-NEXT: entry: 647 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 648 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 649 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 650 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 651 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 652 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 653 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 654 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 655 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 656 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 657 // CHECK1-NEXT: ret void 658 // 659 // 660 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 661 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 662 // CHECK1-NEXT: entry: 663 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 664 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 665 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 666 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 667 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 668 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 669 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 670 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 671 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 672 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 673 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 674 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 675 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 676 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 677 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 678 // CHECK1-NEXT: ret void 679 // 680 // 681 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 682 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 683 // CHECK1-NEXT: entry: 684 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 685 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 686 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 687 // CHECK1-NEXT: ret void 688 // 689 // 690 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp 691 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 692 // CHECK1-NEXT: entry: 693 // CHECK1-NEXT: call void @__cxx_global_var_init() 694 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 695 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 696 // CHECK1-NEXT: ret void 697 // 698 // 699 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 700 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { 701 // CHECK3-NEXT: entry: 702 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 703 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 704 // CHECK3-NEXT: ret void 705 // 706 // 707 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 708 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 709 // CHECK3-NEXT: entry: 710 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 711 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 712 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 713 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 714 // CHECK3-NEXT: ret void 715 // 716 // 717 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 718 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 719 // CHECK3-NEXT: entry: 720 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 721 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 722 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 723 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 724 // CHECK3-NEXT: ret void 725 // 726 // 727 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 728 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 729 // CHECK3-NEXT: entry: 730 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 731 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 732 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 733 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 734 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 735 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 736 // CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4 737 // CHECK3-NEXT: ret void 738 // 739 // 740 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 741 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 742 // CHECK3-NEXT: entry: 743 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 744 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 745 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 746 // CHECK3-NEXT: ret void 747 // 748 // 749 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 750 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 751 // CHECK3-NEXT: entry: 752 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 753 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 754 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 755 // CHECK3-NEXT: ret void 756 // 757 // 758 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 759 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 760 // CHECK3-NEXT: entry: 761 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 762 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 763 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 764 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 765 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 766 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 767 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 768 // CHECK3-NEXT: ret void 769 // 770 // 771 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 772 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 773 // CHECK3-NEXT: entry: 774 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 775 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 776 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 777 // CHECK3: arraydestroy.body: 778 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 779 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 780 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 781 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 782 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 783 // CHECK3: arraydestroy.done1: 784 // CHECK3-NEXT: ret void 785 // 786 // 787 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 788 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 789 // CHECK3-NEXT: entry: 790 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 791 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 792 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 793 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 794 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 795 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 796 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 797 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 798 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 799 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 800 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 801 // CHECK3-NEXT: ret void 802 // 803 // 804 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 805 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 806 // CHECK3-NEXT: entry: 807 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 808 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 809 // CHECK3-NEXT: ret void 810 // 811 // 812 // CHECK3-LABEL: define {{[^@]+}}@main 813 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 814 // CHECK3-NEXT: entry: 815 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 816 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 817 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 818 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 819 // CHECK3-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP0]], align 8 820 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[REF_TMP]]) 821 // CHECK3-NEXT: ret i32 0 822 // 823 // 824 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp 825 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 826 // CHECK3-NEXT: entry: 827 // CHECK3-NEXT: call void @__cxx_global_var_init() 828 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 829 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 830 // CHECK3-NEXT: ret void 831 // 832 // 833 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init 834 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { 835 // CHECK4-NEXT: entry: 836 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 837 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 838 // CHECK4-NEXT: ret void 839 // 840 // 841 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 842 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 843 // CHECK4-NEXT: entry: 844 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 845 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 846 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 847 // CHECK4-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 848 // CHECK4-NEXT: ret void 849 // 850 // 851 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 852 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 853 // CHECK4-NEXT: entry: 854 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 855 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 856 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 857 // CHECK4-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 858 // CHECK4-NEXT: ret void 859 // 860 // 861 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 862 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 863 // CHECK4-NEXT: entry: 864 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 865 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 866 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 867 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 868 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 869 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 870 // CHECK4-NEXT: store float [[CONV]], ptr [[F]], align 4 871 // CHECK4-NEXT: ret void 872 // 873 // 874 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 875 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 876 // CHECK4-NEXT: entry: 877 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 878 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 879 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 880 // CHECK4-NEXT: ret void 881 // 882 // 883 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 884 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 885 // CHECK4-NEXT: entry: 886 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 887 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 888 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 889 // CHECK4-NEXT: ret void 890 // 891 // 892 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 893 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 894 // CHECK4-NEXT: entry: 895 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 896 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 897 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 898 // CHECK4-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 899 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 900 // CHECK4-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 901 // CHECK4-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 902 // CHECK4-NEXT: ret void 903 // 904 // 905 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 906 // CHECK4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 907 // CHECK4-NEXT: entry: 908 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 909 // CHECK4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 910 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 911 // CHECK4: arraydestroy.body: 912 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 913 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 914 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 915 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 916 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 917 // CHECK4: arraydestroy.done1: 918 // CHECK4-NEXT: ret void 919 // 920 // 921 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 922 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 923 // CHECK4-NEXT: entry: 924 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 925 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 926 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 927 // CHECK4-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 928 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 929 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 930 // CHECK4-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 931 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 932 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 933 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 934 // CHECK4-NEXT: store float [[ADD]], ptr [[F]], align 4 935 // CHECK4-NEXT: ret void 936 // 937 // 938 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 939 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 940 // CHECK4-NEXT: entry: 941 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 942 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 943 // CHECK4-NEXT: ret void 944 // 945 // 946 // CHECK4-LABEL: define {{[^@]+}}@main 947 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 948 // CHECK4-NEXT: entry: 949 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 950 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32 }>, align 8 951 // CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4 952 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 0 953 // CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8 954 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 1 955 // CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8 956 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 2 957 // CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4 958 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 3 959 // CHECK4-NEXT: store ptr @__main_block_invoke, ptr [[BLOCK_INVOKE]], align 8 960 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 4 961 // CHECK4-NEXT: store ptr @__block_descriptor_tmp.3, ptr [[BLOCK_DESCRIPTOR]], align 8 962 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5 963 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 964 // CHECK4-NEXT: store i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 8 965 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 966 // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 967 // CHECK4-NEXT: call void [[TMP2]](ptr noundef [[BLOCK]]) 968 // CHECK4-NEXT: ret i32 0 969 // 970 // 971 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke 972 // CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR4:[0-9]+]] { 973 // CHECK4-NEXT: entry: 974 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 975 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 976 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 977 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 978 // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 1, ptr @__main_block_invoke.omp_outlined, ptr @_ZZ4mainE5sivar) 979 // CHECK4-NEXT: ret void 980 // 981 // 982 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined 983 // CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { 984 // CHECK4-NEXT: entry: 985 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 986 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 987 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 988 // CHECK4-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 989 // CHECK4-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 990 // CHECK4-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 991 // CHECK4-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 992 // CHECK4-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 993 // CHECK4-NEXT: [[G:%.*]] = alloca i32, align 4 994 // CHECK4-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 995 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, align 8 996 // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 997 // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 998 // CHECK4-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 999 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 1000 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4 1001 // CHECK4-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_UB_]], align 4 1002 // CHECK4-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4 1003 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4 1004 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1005 // CHECK4-NEXT: store i32 [[TMP1]], ptr [[G]], align 4 1006 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4 1007 // CHECK4-NEXT: store i32 [[TMP2]], ptr [[SIVAR1]], align 4 1008 // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1009 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 1010 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_SECTIONS_IL_]], ptr [[DOTOMP_SECTIONS_LB_]], ptr [[DOTOMP_SECTIONS_UB_]], ptr [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) 1011 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4 1012 // CHECK4-NEXT: [[TMP6:%.*]] = icmp slt i32 [[TMP5]], 1 1013 // CHECK4-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP5]], i32 1 1014 // CHECK4-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_SECTIONS_UB_]], align 4 1015 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_LB_]], align 4 1016 // CHECK4-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_SECTIONS_IV_]], align 4 1017 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1018 // CHECK4: omp.inner.for.cond: 1019 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4 1020 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4 1021 // CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1022 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1023 // CHECK4: omp.inner.for.body: 1024 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4 1025 // CHECK4-NEXT: switch i32 [[TMP11]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ 1026 // CHECK4-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] 1027 // CHECK4-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE2:%.*]] 1028 // CHECK4-NEXT: ] 1029 // CHECK4: .omp.sections.case: 1030 // CHECK4-NEXT: store i32 1, ptr [[G]], align 4 1031 // CHECK4-NEXT: store i32 10, ptr [[SIVAR1]], align 4 1032 // CHECK4-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 1033 // CHECK4: .omp.sections.case2: 1034 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 0 1035 // CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8 1036 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 1 1037 // CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8 1038 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 2 1039 // CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4 1040 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 3 1041 // CHECK4-NEXT: store ptr @var_block_invoke, ptr [[BLOCK_INVOKE]], align 8 1042 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 4 1043 // CHECK4-NEXT: store ptr @__block_descriptor_tmp, ptr [[BLOCK_DESCRIPTOR]], align 8 1044 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 5 1045 // CHECK4-NEXT: [[TMP12:%.*]] = load volatile i32, ptr [[G]], align 4 1046 // CHECK4-NEXT: store volatile i32 [[TMP12]], ptr [[BLOCK_CAPTURED]], align 8 1047 // CHECK4-NEXT: [[BLOCK_CAPTURED3:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 6 1048 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, ptr [[SIVAR1]], align 4 1049 // CHECK4-NEXT: store i32 [[TMP13]], ptr [[BLOCK_CAPTURED3]], align 4 1050 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 1051 // CHECK4-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8 1052 // CHECK4-NEXT: call void [[TMP15]](ptr noundef [[BLOCK]]) 1053 // CHECK4-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 1054 // CHECK4: .omp.sections.exit: 1055 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1056 // CHECK4: omp.inner.for.inc: 1057 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4 1058 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP16]], 1 1059 // CHECK4-NEXT: store i32 [[INC]], ptr [[DOTOMP_SECTIONS_IV_]], align 4 1060 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 1061 // CHECK4: omp.inner.for.end: 1062 // CHECK4-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) 1063 // CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]]) 1064 // CHECK4-NEXT: ret void 1065 // 1066 // 1067 // CHECK4-LABEL: define {{[^@]+}}@var_block_invoke 1068 // CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR4]] { 1069 // CHECK4-NEXT: entry: 1070 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 1071 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 1072 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 1073 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 1074 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 1075 // CHECK4-NEXT: store i32 2, ptr [[BLOCK_CAPTURE_ADDR]], align 8 1076 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 1077 // CHECK4-NEXT: store i32 20, ptr [[BLOCK_CAPTURE_ADDR1]], align 4 1078 // CHECK4-NEXT: ret void 1079 // 1080 // 1081 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp 1082 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1083 // CHECK4-NEXT: entry: 1084 // CHECK4-NEXT: call void @__cxx_global_var_init() 1085 // CHECK4-NEXT: call void @__cxx_global_var_init.1() 1086 // CHECK4-NEXT: call void @__cxx_global_var_init.2() 1087 // CHECK4-NEXT: ret void 1088 // 1089