1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1 3 4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 6 7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 9 10 // RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -std=c++11 -fopenmp -fopenmp-version=52 -fnoopenmp-use-tls -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 11 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 12 13 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 // RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -std=c++11 -fopenmp-simd -fopenmp-version=52 -fnoopenmp-use-tls -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 17 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 18 // expected-no-diagnostics 19 20 typedef void **omp_allocator_handle_t; 21 extern const omp_allocator_handle_t omp_null_allocator; 22 extern const omp_allocator_handle_t omp_default_mem_alloc; 23 extern const omp_allocator_handle_t omp_large_cap_mem_alloc; 24 extern const omp_allocator_handle_t omp_const_mem_alloc; 25 extern const omp_allocator_handle_t omp_high_bw_mem_alloc; 26 extern const omp_allocator_handle_t omp_low_lat_mem_alloc; 27 extern const omp_allocator_handle_t omp_cgroup_mem_alloc; 28 extern const omp_allocator_handle_t omp_pteam_mem_alloc; 29 extern const omp_allocator_handle_t omp_thread_mem_alloc; 30 31 #ifndef ARRAY 32 #ifndef HEADER 33 #define HEADER 34 35 class TestClass { 36 public: 37 int a; 38 TestClass() : a(0) {} 39 TestClass(const TestClass &C) : a(C.a) {} 40 TestClass &operator=(const TestClass &) { return *this;} 41 ~TestClass(){}; 42 }; 43 44 45 TestClass tc; 46 TestClass tc2[2]; 47 48 void foo() { extern void mayThrow(); mayThrow(); } 49 50 struct SS { 51 int e; 52 int a; 53 int b : 4; 54 int &c; 55 SS(int &d) : a(0), b(0), c(d) { 56 #pragma omp scope private(a, this->b, (this)->c) allocate(omp_default_mem_alloc:b) nowait 57 [&]() { 58 ++this->a, --b, (this)->c /= 1; 59 #pragma omp parallel num_threads(b) 60 #pragma omp scope firstprivate(a, this->b, (this)->c) reduction(+:e) 61 ++(this)->a, e+=1, this->c /= 1; 62 }(); 63 } 64 }; 65 66 template<typename T> 67 struct SST { 68 T a; 69 SST() : a(T()) { 70 #pragma omp target teams 71 #pragma omp parallel firstprivate(a) 72 #pragma omp scope private(this->a) 73 [&]() { 74 [&]() { 75 int c; 76 ++this->a; 77 #pragma omp parallel firstprivate(a) 78 #pragma omp scope private((this)->a) allocate(omp_cgroup_mem_alloc:a) 79 ++(this)->a; 80 }(); 81 }(); 82 } 83 }; 84 85 int main() { 86 char a; 87 char a2[2]; 88 TestClass &c = tc; 89 SST<double> sst; 90 SS ss(c.a); 91 92 #pragma omp scope nowait 93 a = 2; 94 #pragma omp scope 95 a = 2; 96 #pragma omp scope firstprivate(a,c, tc) private(a2, tc2) 97 foo(); 98 return a; 99 } 100 101 102 void parallel_single() { 103 #pragma omp parallel 104 #pragma omp scope 105 foo(); 106 } 107 #endif 108 #else 109 struct St { 110 int a, b; 111 St() : a(0), b(0) {} 112 St &operator=(const St &) { return *this; }; 113 ~St() {} 114 }; 115 116 void array_func(int n, int a[n], St s[2]) { 117 int b,c; 118 #pragma omp scope nowait firstprivate(b) allocate(omp_high_bw_mem_alloc:c) private(a,s) reduction(*:c) 119 ; 120 } 121 122 int main() { 123 int n; 124 int a[10]; 125 St s[2]; 126 127 array_func(n, a, s); 128 return 0; 129 } 130 #endif 131 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 132 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 133 // CHECK1-NEXT: entry: 134 // CHECK1-NEXT: call void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @tc) 135 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN9TestClassD1Ev, ptr @tc, ptr @__dso_handle) #[[ATTR3:[0-9]+]] 136 // CHECK1-NEXT: ret void 137 // 138 // 139 // CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassC1Ev 140 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 141 // CHECK1-NEXT: entry: 142 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 143 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 144 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 145 // CHECK1-NEXT: call void @_ZN9TestClassC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 146 // CHECK1-NEXT: ret void 147 // 148 // 149 // CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev 150 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { 151 // CHECK1-NEXT: entry: 152 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 153 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 154 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 155 // CHECK1-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] 156 // CHECK1-NEXT: ret void 157 // 158 // 159 // CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassC2Ev 160 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 161 // CHECK1-NEXT: entry: 162 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 163 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 164 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 165 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS:%.*]], ptr [[THIS1]], i32 0, i32 0 166 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 167 // CHECK1-NEXT: ret void 168 // 169 // 170 // CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev 171 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 172 // CHECK1-NEXT: entry: 173 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 174 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 175 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 176 // CHECK1-NEXT: ret void 177 // 178 // 179 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 180 // CHECK1-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 { 181 // CHECK1-NEXT: entry: 182 // CHECK1-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 183 // CHECK1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 184 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 185 // CHECK1: arrayctor.loop: 186 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ @tc2, [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ] 187 // CHECK1-NEXT: invoke void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 188 // CHECK1-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]] 189 // CHECK1: invoke.cont: 190 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], ptr [[ARRAYCTOR_CUR]], i64 1 191 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[CLASS_TESTCLASS]], ptr @tc2, i64 2) 192 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 193 // CHECK1: arrayctor.cont: 194 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]] 195 // CHECK1-NEXT: ret void 196 // CHECK1: lpad: 197 // CHECK1-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } 198 // CHECK1-NEXT: cleanup 199 // CHECK1-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0 200 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8 201 // CHECK1-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1 202 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4 203 // CHECK1-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @tc2, [[ARRAYCTOR_CUR]] 204 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY:%.*]] 205 // CHECK1: arraydestroy.body: 206 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 207 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 208 // CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 209 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2 210 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] 211 // CHECK1: arraydestroy.done1: 212 // CHECK1-NEXT: br label [[EH_RESUME:%.*]] 213 // CHECK1: eh.resume: 214 // CHECK1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 215 // CHECK1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 216 // CHECK1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 217 // CHECK1-NEXT: [[LPAD_VAL2:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 218 // CHECK1-NEXT: resume { ptr, i32 } [[LPAD_VAL2]] 219 // 220 // 221 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 222 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 223 // CHECK1-NEXT: entry: 224 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 225 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 226 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 227 // CHECK1: arraydestroy.body: 228 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], ptr @tc2, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 229 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 230 // CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 231 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2 232 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 233 // CHECK1: arraydestroy.done1: 234 // CHECK1-NEXT: ret void 235 // 236 // 237 // CHECK1-LABEL: define {{[^@]+}}@_Z3foov 238 // CHECK1-SAME: () #[[ATTR1]] { 239 // CHECK1-NEXT: entry: 240 // CHECK1-NEXT: call void @_Z8mayThrowv() 241 // CHECK1-NEXT: ret void 242 // 243 // 244 // CHECK1-LABEL: define {{[^@]+}}@main 245 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] personality ptr @__gxx_personality_v0 { 246 // CHECK1-NEXT: entry: 247 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 248 // CHECK1-NEXT: [[A:%.*]] = alloca i8, align 1 249 // CHECK1-NEXT: [[A2:%.*]] = alloca [2 x i8], align 1 250 // CHECK1-NEXT: [[C:%.*]] = alloca ptr, align 8 251 // CHECK1-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 8 252 // CHECK1-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 253 // CHECK1-NEXT: [[A1:%.*]] = alloca i8, align 1 254 // CHECK1-NEXT: [[C2:%.*]] = alloca [[CLASS_TESTCLASS:%.*]], align 4 255 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 256 // CHECK1-NEXT: [[TC:%.*]] = alloca [[CLASS_TESTCLASS]], align 4 257 // CHECK1-NEXT: [[A24:%.*]] = alloca [2 x i8], align 1 258 // CHECK1-NEXT: [[TC2:%.*]] = alloca [2 x %class.TestClass], align 4 259 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 260 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 261 // CHECK1-NEXT: store ptr @tc, ptr [[C]], align 8 262 // CHECK1-NEXT: call void @_ZN3SSTIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[SST]]) 263 // CHECK1-NEXT: call void @_ZN2SSC1ERi(ptr noundef nonnull align 8 dereferenceable(24) [[SS]], ptr noundef nonnull align 4 dereferenceable(4) @tc) 264 // CHECK1-NEXT: store i8 2, ptr [[A]], align 1 265 // CHECK1-NEXT: store i8 2, ptr [[A]], align 1 266 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]]) 267 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, ptr [[A]], align 1 268 // CHECK1-NEXT: store i8 [[TMP1]], ptr [[A1]], align 1 269 // CHECK1-NEXT: invoke void @_ZN9TestClassC1ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[C2]], ptr noundef nonnull align 4 dereferenceable(4) @tc) 270 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 271 // CHECK1: invoke.cont: 272 // CHECK1-NEXT: store ptr [[C2]], ptr [[TMP]], align 8 273 // CHECK1-NEXT: invoke void @_ZN9TestClassC1ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[TC]], ptr noundef nonnull align 4 dereferenceable(4) @tc) 274 // CHECK1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[TERMINATE_LPAD]] 275 // CHECK1: invoke.cont3: 276 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TC2]], i32 0, i32 0 277 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN]], i64 2 278 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 279 // CHECK1: arrayctor.loop: 280 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[INVOKE_CONT3]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT5:%.*]] ] 281 // CHECK1-NEXT: invoke void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 282 // CHECK1-NEXT: to label [[INVOKE_CONT5]] unwind label [[TERMINATE_LPAD]] 283 // CHECK1: invoke.cont5: 284 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYCTOR_CUR]], i64 1 285 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 286 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 287 // CHECK1: arrayctor.cont: 288 // CHECK1-NEXT: invoke void @_Z3foov() 289 // CHECK1-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] 290 // CHECK1: invoke.cont6: 291 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TC2]], i32 0, i32 0 292 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN7]], i64 2 293 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 294 // CHECK1: arraydestroy.body: 295 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[INVOKE_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 296 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 297 // CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 298 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 299 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 300 // CHECK1: arraydestroy.done8: 301 // CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TC]]) #[[ATTR3]] 302 // CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[C2]]) #[[ATTR3]] 303 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP0]]) 304 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, ptr [[A]], align 1 305 // CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 306 // CHECK1-NEXT: ret i32 [[CONV]] 307 // CHECK1: terminate.lpad: 308 // CHECK1-NEXT: [[TMP4:%.*]] = landingpad { ptr, i32 } 309 // CHECK1-NEXT: catch ptr null 310 // CHECK1-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP4]], 0 311 // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP5]]) #[[ATTR10:[0-9]+]] 312 // CHECK1-NEXT: unreachable 313 // 314 // 315 // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIdEC1Ev 316 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 317 // CHECK1-NEXT: entry: 318 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 319 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 320 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 321 // CHECK1-NEXT: call void @_ZN3SSTIdEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) 322 // CHECK1-NEXT: ret void 323 // 324 // 325 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 326 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 327 // CHECK1-NEXT: entry: 328 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 329 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 330 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 331 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 332 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 333 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 334 // CHECK1-NEXT: call void @_ZN2SSC2ERi(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]]) 335 // CHECK1-NEXT: ret void 336 // 337 // 338 // CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassC1ERKS_ 339 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 340 // CHECK1-NEXT: entry: 341 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 342 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 343 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 344 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 345 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 346 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8 347 // CHECK1-NEXT: call void @_ZN9TestClassC2ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]]) 348 // CHECK1-NEXT: ret void 349 // 350 // 351 // CHECK1-LABEL: define {{[^@]+}}@__clang_call_terminate 352 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR7:[0-9]+]] comdat { 353 // CHECK1-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR3]] 354 // CHECK1-NEXT: call void @_ZSt9terminatev() #[[ATTR10]] 355 // CHECK1-NEXT: unreachable 356 // 357 // 358 // 359 // 360 // 361 // 362 // 363 // 364 // 365 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 366 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 personality ptr @__gxx_personality_v0 { 367 // CHECK1-NEXT: entry: 368 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 369 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 370 // CHECK1-NEXT: [[A2:%.*]] = alloca i32, align 4 371 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 372 // CHECK1-NEXT: [[C3:%.*]] = alloca i32, align 4 373 // CHECK1-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8 374 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 375 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 376 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 377 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 378 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 379 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 1 380 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 381 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 382 // CHECK1-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 8 383 // CHECK1-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 384 // CHECK1-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 385 // CHECK1-NEXT: store i8 [[BF_SET]], ptr [[B]], align 8 386 // CHECK1-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3 387 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8 388 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[C]], align 8 389 // CHECK1-NEXT: store ptr [[A2]], ptr [[TMP]], align 8 390 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 8 391 // CHECK1-NEXT: [[DOTB__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP0]], i64 4, ptr [[TMP2]]) 392 // CHECK1-NEXT: store ptr [[C3]], ptr [[_TMP4]], align 8 393 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0 394 // CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP3]], align 8 395 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1 396 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 397 // CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8 398 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 2 399 // CHECK1-NEXT: store ptr [[DOTB__VOID_ADDR]], ptr [[TMP6]], align 8 400 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 3 401 // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8 402 // CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8 403 // CHECK1-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) 404 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 405 // CHECK1: invoke.cont: 406 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 8 407 // CHECK1-NEXT: call void @__kmpc_free(i32 [[TMP0]], ptr [[DOTB__VOID_ADDR]], ptr [[TMP9]]) 408 // CHECK1-NEXT: ret void 409 // CHECK1: terminate.lpad: 410 // CHECK1-NEXT: [[TMP10:%.*]] = landingpad { ptr, i32 } 411 // CHECK1-NEXT: catch ptr null 412 // CHECK1-NEXT: [[TMP11:%.*]] = extractvalue { ptr, i32 } [[TMP10]], 0 413 // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP11]]) #[[ATTR10]] 414 // CHECK1-NEXT: unreachable 415 // 416 // 417 // CHECK1-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv 418 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2]] align 2 { 419 // CHECK1-NEXT: entry: 420 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 421 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 422 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 423 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 424 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1:%.*]], ptr [[THIS1]], i32 0, i32 0 425 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 426 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1 427 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 428 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 429 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 430 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP4]], align 4 431 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2 432 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 433 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 434 // CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 435 // CHECK1-NEXT: store i32 [[DEC]], ptr [[TMP7]], align 4 436 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3 437 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 438 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 439 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1 440 // CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 4 441 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2 442 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8 443 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 444 // CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP14]]) 445 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1 446 // CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 447 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2 448 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 449 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3 450 // CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8 451 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP2]], ptr [[TMP16]], ptr [[TMP18]], ptr [[TMP20]]) 452 // CHECK1-NEXT: ret void 453 // 454 // 455 // CHECK1-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined 456 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR8:[0-9]+]] { 457 // CHECK1-NEXT: entry: 458 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 459 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 460 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 461 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 462 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 463 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 464 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 465 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 466 // CHECK1-NEXT: [[E:%.*]] = alloca ptr, align 8 467 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 468 // CHECK1-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8 469 // CHECK1-NEXT: [[_TMP5:%.*]] = alloca ptr, align 8 470 // CHECK1-NEXT: [[A6:%.*]] = alloca i32, align 4 471 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 472 // CHECK1-NEXT: [[B8:%.*]] = alloca i32, align 4 473 // CHECK1-NEXT: [[C9:%.*]] = alloca i32, align 4 474 // CHECK1-NEXT: [[_TMP10:%.*]] = alloca ptr, align 8 475 // CHECK1-NEXT: [[E11:%.*]] = alloca i32, align 4 476 // CHECK1-NEXT: [[_TMP12:%.*]] = alloca ptr, align 8 477 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 478 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 479 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 480 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 481 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 482 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 483 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 484 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 485 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 486 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8 487 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 488 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 489 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8 490 // CHECK1-NEXT: [[E2:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 491 // CHECK1-NEXT: store ptr [[E2]], ptr [[E]], align 8 492 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 493 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP3]], align 8 494 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[E]], align 8 495 // CHECK1-NEXT: store ptr [[TMP5]], ptr [[_TMP4]], align 8 496 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8 497 // CHECK1-NEXT: store ptr [[TMP6]], ptr [[_TMP5]], align 8 498 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8 499 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 500 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[A6]], align 4 501 // CHECK1-NEXT: store ptr [[A6]], ptr [[_TMP7]], align 8 502 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP2]], align 4 503 // CHECK1-NEXT: store i32 [[TMP9]], ptr [[B8]], align 4 504 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 8 505 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 506 // CHECK1-NEXT: store i32 [[TMP11]], ptr [[C9]], align 4 507 // CHECK1-NEXT: store ptr [[C9]], ptr [[_TMP10]], align 8 508 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8 509 // CHECK1-NEXT: store i32 0, ptr [[E11]], align 4 510 // CHECK1-NEXT: store ptr [[E11]], ptr [[_TMP12]], align 8 511 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP7]], align 8 512 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 513 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 514 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP13]], align 4 515 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP12]], align 8 516 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 517 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 518 // CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP15]], align 4 519 // CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP10]], align 8 520 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 521 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP18]], 1 522 // CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP17]], align 4 523 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 524 // CHECK1-NEXT: store ptr [[E11]], ptr [[TMP19]], align 8 525 // CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 526 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 527 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB3:[0-9]+]], i32 [[TMP21]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 528 // CHECK1-NEXT: switch i32 [[TMP22]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 529 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 530 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 531 // CHECK1-NEXT: ] 532 // CHECK1: .omp.reduction.case1: 533 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP12]], align 4 534 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[E11]], align 4 535 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] 536 // CHECK1-NEXT: store i32 [[ADD13]], ptr [[TMP12]], align 4 537 // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP21]], ptr @.gomp_critical_user_.reduction.var) 538 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 539 // CHECK1: .omp.reduction.case2: 540 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[E11]], align 4 541 // CHECK1-NEXT: [[TMP26:%.*]] = atomicrmw add ptr [[TMP12]], i32 [[TMP25]] monotonic, align 4 542 // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP21]], ptr @.gomp_critical_user_.reduction.var) 543 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 544 // CHECK1: .omp.reduction.default: 545 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP21]]) 546 // CHECK1-NEXT: ret void 547 // 548 // 549 // CHECK1-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined.omp.reduction.reduction_func 550 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR9:[0-9]+]] { 551 // CHECK1-NEXT: entry: 552 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 553 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 554 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 555 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 556 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 557 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 558 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 559 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 560 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 561 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 562 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 563 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 564 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 565 // CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 566 // CHECK1-NEXT: ret void 567 // 568 // 569 // CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassC2ERKS_ 570 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 571 // CHECK1-NEXT: entry: 572 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 573 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 574 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 575 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 576 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 577 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS:%.*]], ptr [[THIS1]], i32 0, i32 0 578 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8 579 // CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS]], ptr [[TMP0]], i32 0, i32 0 580 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A2]], align 4 581 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[A]], align 4 582 // CHECK1-NEXT: ret void 583 // 584 // 585 // CHECK1-LABEL: define {{[^@]+}}@_Z15parallel_singlev 586 // CHECK1-SAME: () #[[ATTR2]] { 587 // CHECK1-NEXT: entry: 588 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @_Z15parallel_singlev.omp_outlined) 589 // CHECK1-NEXT: ret void 590 // 591 // 592 // CHECK1-LABEL: define {{[^@]+}}@_Z15parallel_singlev.omp_outlined 593 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR8]] personality ptr @__gxx_personality_v0 { 594 // CHECK1-NEXT: entry: 595 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 596 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 597 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 598 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 599 // CHECK1-NEXT: invoke void @_Z3foov() 600 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 601 // CHECK1: invoke.cont: 602 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 603 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 604 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP1]]) 605 // CHECK1-NEXT: ret void 606 // CHECK1: terminate.lpad: 607 // CHECK1-NEXT: [[TMP2:%.*]] = landingpad { ptr, i32 } 608 // CHECK1-NEXT: catch ptr null 609 // CHECK1-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0 610 // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP3]]) #[[ATTR10]] 611 // CHECK1-NEXT: unreachable 612 // 613 // 614 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_scope_codegen.cpp 615 // CHECK1-SAME: () #[[ATTR0]] { 616 // CHECK1-NEXT: entry: 617 // CHECK1-NEXT: call void @__cxx_global_var_init() 618 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 619 // CHECK1-NEXT: ret void 620 // 621 // 622 // 623 // 624 // 625 // 626 // 627 // 628 // 629 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init 630 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 631 // CHECK4-NEXT: entry: 632 // CHECK4-NEXT: call void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @tc) 633 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN9TestClassD1Ev, ptr @tc, ptr @__dso_handle) #[[ATTR3:[0-9]+]] 634 // CHECK4-NEXT: ret void 635 // 636 // 637 // CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassC1Ev 638 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 639 // CHECK4-NEXT: entry: 640 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 641 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 642 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 643 // CHECK4-NEXT: call void @_ZN9TestClassC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 644 // CHECK4-NEXT: ret void 645 // 646 // 647 // CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev 648 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { 649 // CHECK4-NEXT: entry: 650 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 651 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 652 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 653 // CHECK4-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] 654 // CHECK4-NEXT: ret void 655 // 656 // 657 // CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassC2Ev 658 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 659 // CHECK4-NEXT: entry: 660 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 661 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 662 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 663 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS:%.*]], ptr [[THIS1]], i32 0, i32 0 664 // CHECK4-NEXT: store i32 0, ptr [[A]], align 4 665 // CHECK4-NEXT: ret void 666 // 667 // 668 // CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev 669 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 670 // CHECK4-NEXT: entry: 671 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 672 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 673 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 674 // CHECK4-NEXT: ret void 675 // 676 // 677 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 678 // CHECK4-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 { 679 // CHECK4-NEXT: entry: 680 // CHECK4-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 681 // CHECK4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 682 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 683 // CHECK4: arrayctor.loop: 684 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ @tc2, [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ] 685 // CHECK4-NEXT: invoke void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 686 // CHECK4-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]] 687 // CHECK4: invoke.cont: 688 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], ptr [[ARRAYCTOR_CUR]], i64 1 689 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[CLASS_TESTCLASS]], ptr @tc2, i64 2) 690 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 691 // CHECK4: arrayctor.cont: 692 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]] 693 // CHECK4-NEXT: ret void 694 // CHECK4: lpad: 695 // CHECK4-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } 696 // CHECK4-NEXT: cleanup 697 // CHECK4-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0 698 // CHECK4-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8 699 // CHECK4-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1 700 // CHECK4-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4 701 // CHECK4-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @tc2, [[ARRAYCTOR_CUR]] 702 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY:%.*]] 703 // CHECK4: arraydestroy.body: 704 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 705 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 706 // CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 707 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2 708 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] 709 // CHECK4: arraydestroy.done1: 710 // CHECK4-NEXT: br label [[EH_RESUME:%.*]] 711 // CHECK4: eh.resume: 712 // CHECK4-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 713 // CHECK4-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 714 // CHECK4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 715 // CHECK4-NEXT: [[LPAD_VAL2:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 716 // CHECK4-NEXT: resume { ptr, i32 } [[LPAD_VAL2]] 717 // 718 // 719 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 720 // CHECK4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 721 // CHECK4-NEXT: entry: 722 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 723 // CHECK4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 724 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 725 // CHECK4: arraydestroy.body: 726 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], ptr @tc2, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 727 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 728 // CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 729 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2 730 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 731 // CHECK4: arraydestroy.done1: 732 // CHECK4-NEXT: ret void 733 // 734 // 735 // CHECK4-LABEL: define {{[^@]+}}@_Z3foov 736 // CHECK4-SAME: () #[[ATTR1]] { 737 // CHECK4-NEXT: entry: 738 // CHECK4-NEXT: call void @_Z8mayThrowv() 739 // CHECK4-NEXT: ret void 740 // 741 // 742 // CHECK4-LABEL: define {{[^@]+}}@main 743 // CHECK4-SAME: () #[[ATTR5:[0-9]+]] personality ptr @__gxx_personality_v0 { 744 // CHECK4-NEXT: entry: 745 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 746 // CHECK4-NEXT: [[A:%.*]] = alloca i8, align 1 747 // CHECK4-NEXT: [[A2:%.*]] = alloca [2 x i8], align 1 748 // CHECK4-NEXT: [[C:%.*]] = alloca ptr, align 8 749 // CHECK4-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 8 750 // CHECK4-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 751 // CHECK4-NEXT: [[A1:%.*]] = alloca i8, align 1 752 // CHECK4-NEXT: [[C2:%.*]] = alloca [[CLASS_TESTCLASS:%.*]], align 4 753 // CHECK4-NEXT: [[TMP:%.*]] = alloca ptr, align 8 754 // CHECK4-NEXT: [[TC:%.*]] = alloca [[CLASS_TESTCLASS]], align 4 755 // CHECK4-NEXT: [[A24:%.*]] = alloca [2 x i8], align 1 756 // CHECK4-NEXT: [[TC2:%.*]] = alloca [2 x %class.TestClass], align 4 757 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 758 // CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4 759 // CHECK4-NEXT: store ptr @tc, ptr [[C]], align 8 760 // CHECK4-NEXT: call void @_ZN3SSTIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[SST]]) 761 // CHECK4-NEXT: call void @_ZN2SSC1ERi(ptr noundef nonnull align 8 dereferenceable(24) [[SS]], ptr noundef nonnull align 4 dereferenceable(4) @tc) 762 // CHECK4-NEXT: store i8 2, ptr [[A]], align 1 763 // CHECK4-NEXT: store i8 2, ptr [[A]], align 1 764 // CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]]) 765 // CHECK4-NEXT: [[TMP1:%.*]] = load i8, ptr [[A]], align 1 766 // CHECK4-NEXT: store i8 [[TMP1]], ptr [[A1]], align 1 767 // CHECK4-NEXT: invoke void @_ZN9TestClassC1ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[C2]], ptr noundef nonnull align 4 dereferenceable(4) @tc) 768 // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 769 // CHECK4: invoke.cont: 770 // CHECK4-NEXT: store ptr [[C2]], ptr [[TMP]], align 8 771 // CHECK4-NEXT: invoke void @_ZN9TestClassC1ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[TC]], ptr noundef nonnull align 4 dereferenceable(4) @tc) 772 // CHECK4-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[TERMINATE_LPAD]] 773 // CHECK4: invoke.cont3: 774 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TC2]], i32 0, i32 0 775 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN]], i64 2 776 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 777 // CHECK4: arrayctor.loop: 778 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[INVOKE_CONT3]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT5:%.*]] ] 779 // CHECK4-NEXT: invoke void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 780 // CHECK4-NEXT: to label [[INVOKE_CONT5]] unwind label [[TERMINATE_LPAD]] 781 // CHECK4: invoke.cont5: 782 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYCTOR_CUR]], i64 1 783 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 784 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 785 // CHECK4: arrayctor.cont: 786 // CHECK4-NEXT: invoke void @_Z3foov() 787 // CHECK4-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] 788 // CHECK4: invoke.cont6: 789 // CHECK4-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TC2]], i32 0, i32 0 790 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN7]], i64 2 791 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 792 // CHECK4: arraydestroy.body: 793 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[INVOKE_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 794 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 795 // CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] 796 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 797 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 798 // CHECK4: arraydestroy.done8: 799 // CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TC]]) #[[ATTR3]] 800 // CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[C2]]) #[[ATTR3]] 801 // CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP0]]) 802 // CHECK4-NEXT: [[TMP3:%.*]] = load i8, ptr [[A]], align 1 803 // CHECK4-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 804 // CHECK4-NEXT: ret i32 [[CONV]] 805 // CHECK4: terminate.lpad: 806 // CHECK4-NEXT: [[TMP4:%.*]] = landingpad { ptr, i32 } 807 // CHECK4-NEXT: catch ptr null 808 // CHECK4-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP4]], 0 809 // CHECK4-NEXT: call void @__clang_call_terminate(ptr [[TMP5]]) #[[ATTR10:[0-9]+]] 810 // CHECK4-NEXT: unreachable 811 // 812 // 813 // CHECK4-LABEL: define {{[^@]+}}@_ZN3SSTIdEC1Ev 814 // CHECK4-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 815 // CHECK4-NEXT: entry: 816 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 817 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 818 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 819 // CHECK4-NEXT: call void @_ZN3SSTIdEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) 820 // CHECK4-NEXT: ret void 821 // 822 // 823 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 824 // CHECK4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 825 // CHECK4-NEXT: entry: 826 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 827 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 828 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 829 // CHECK4-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 830 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 831 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 832 // CHECK4-NEXT: call void @_ZN2SSC2ERi(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]]) 833 // CHECK4-NEXT: ret void 834 // 835 // 836 // CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassC1ERKS_ 837 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 838 // CHECK4-NEXT: entry: 839 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 840 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 841 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 842 // CHECK4-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 843 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 844 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8 845 // CHECK4-NEXT: call void @_ZN9TestClassC2ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]]) 846 // CHECK4-NEXT: ret void 847 // 848 // 849 // CHECK4-LABEL: define {{[^@]+}}@__clang_call_terminate 850 // CHECK4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR7:[0-9]+]] comdat { 851 // CHECK4-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR3]] 852 // CHECK4-NEXT: call void @_ZSt9terminatev() #[[ATTR10]] 853 // CHECK4-NEXT: unreachable 854 // 855 // 856 // CHECK4-LABEL: define {{[^@]+}}@_ZN3SSTIdEC2Ev 857 // CHECK4-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 858 // CHECK4-NEXT: entry: 859 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 860 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 861 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 862 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[THIS1]], i32 0, i32 0 863 // CHECK4-NEXT: store double 0.000000e+00, ptr [[A]], align 8 864 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr @omp_cgroup_mem_alloc, align 8 865 // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr @omp_null_allocator, align 8 866 // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 8 867 // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr @omp_large_cap_mem_alloc, align 8 868 // CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr @omp_const_mem_alloc, align 8 869 // CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr @omp_high_bw_mem_alloc, align 8 870 // CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr @omp_low_lat_mem_alloc, align 8 871 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr @omp_pteam_mem_alloc, align 8 872 // CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr @omp_thread_mem_alloc, align 8 873 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70(ptr [[THIS1]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]], ptr [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], ptr [[TMP8]]) #[[ATTR3]] 874 // CHECK4-NEXT: ret void 875 // 876 // 877 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70 878 // CHECK4-SAME: (ptr noundef [[THIS:%.*]], ptr noundef [[OMP_CGROUP_MEM_ALLOC:%.*]], ptr noundef [[OMP_NULL_ALLOCATOR:%.*]], ptr noundef [[OMP_DEFAULT_MEM_ALLOC:%.*]], ptr noundef [[OMP_LARGE_CAP_MEM_ALLOC:%.*]], ptr noundef [[OMP_CONST_MEM_ALLOC:%.*]], ptr noundef [[OMP_HIGH_BW_MEM_ALLOC:%.*]], ptr noundef [[OMP_LOW_LAT_MEM_ALLOC:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]], ptr noundef [[OMP_THREAD_MEM_ALLOC:%.*]]) #[[ATTR8:[0-9]+]] { 879 // CHECK4-NEXT: entry: 880 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 881 // CHECK4-NEXT: [[OMP_CGROUP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 882 // CHECK4-NEXT: [[OMP_NULL_ALLOCATOR_ADDR:%.*]] = alloca ptr, align 8 883 // CHECK4-NEXT: [[OMP_DEFAULT_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 884 // CHECK4-NEXT: [[OMP_LARGE_CAP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 885 // CHECK4-NEXT: [[OMP_CONST_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 886 // CHECK4-NEXT: [[OMP_HIGH_BW_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 887 // CHECK4-NEXT: [[OMP_LOW_LAT_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 888 // CHECK4-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 889 // CHECK4-NEXT: [[OMP_THREAD_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 890 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 891 // CHECK4-NEXT: store ptr [[OMP_CGROUP_MEM_ALLOC]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8 892 // CHECK4-NEXT: store ptr [[OMP_NULL_ALLOCATOR]], ptr [[OMP_NULL_ALLOCATOR_ADDR]], align 8 893 // CHECK4-NEXT: store ptr [[OMP_DEFAULT_MEM_ALLOC]], ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], align 8 894 // CHECK4-NEXT: store ptr [[OMP_LARGE_CAP_MEM_ALLOC]], ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], align 8 895 // CHECK4-NEXT: store ptr [[OMP_CONST_MEM_ALLOC]], ptr [[OMP_CONST_MEM_ALLOC_ADDR]], align 8 896 // CHECK4-NEXT: store ptr [[OMP_HIGH_BW_MEM_ALLOC]], ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], align 8 897 // CHECK4-NEXT: store ptr [[OMP_LOW_LAT_MEM_ALLOC]], ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], align 8 898 // CHECK4-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8 899 // CHECK4-NEXT: store ptr [[OMP_THREAD_MEM_ALLOC]], ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 8 900 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 901 // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8 902 // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OMP_NULL_ALLOCATOR_ADDR]], align 8 903 // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], align 8 904 // CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], align 8 905 // CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[OMP_CONST_MEM_ALLOC_ADDR]], align 8 906 // CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], align 8 907 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], align 8 908 // CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8 909 // CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 8 910 // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70.omp_outlined, ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]], ptr [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], ptr [[TMP8]], ptr [[TMP9]]) 911 // CHECK4-NEXT: ret void 912 // 913 // 914 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70.omp_outlined 915 // CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef [[OMP_CGROUP_MEM_ALLOC:%.*]], ptr noundef [[OMP_NULL_ALLOCATOR:%.*]], ptr noundef [[OMP_DEFAULT_MEM_ALLOC:%.*]], ptr noundef [[OMP_LARGE_CAP_MEM_ALLOC:%.*]], ptr noundef [[OMP_CONST_MEM_ALLOC:%.*]], ptr noundef [[OMP_HIGH_BW_MEM_ALLOC:%.*]], ptr noundef [[OMP_LOW_LAT_MEM_ALLOC:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]], ptr noundef [[OMP_THREAD_MEM_ALLOC:%.*]]) #[[ATTR8]] { 916 // CHECK4-NEXT: entry: 917 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 918 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 919 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 920 // CHECK4-NEXT: [[OMP_CGROUP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 921 // CHECK4-NEXT: [[OMP_NULL_ALLOCATOR_ADDR:%.*]] = alloca ptr, align 8 922 // CHECK4-NEXT: [[OMP_DEFAULT_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 923 // CHECK4-NEXT: [[OMP_LARGE_CAP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 924 // CHECK4-NEXT: [[OMP_CONST_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 925 // CHECK4-NEXT: [[OMP_HIGH_BW_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 926 // CHECK4-NEXT: [[OMP_LOW_LAT_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 927 // CHECK4-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 928 // CHECK4-NEXT: [[OMP_THREAD_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 929 // CHECK4-NEXT: [[A:%.*]] = alloca ptr, align 8 930 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 931 // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 932 // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 933 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 934 // CHECK4-NEXT: store ptr [[OMP_CGROUP_MEM_ALLOC]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8 935 // CHECK4-NEXT: store ptr [[OMP_NULL_ALLOCATOR]], ptr [[OMP_NULL_ALLOCATOR_ADDR]], align 8 936 // CHECK4-NEXT: store ptr [[OMP_DEFAULT_MEM_ALLOC]], ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], align 8 937 // CHECK4-NEXT: store ptr [[OMP_LARGE_CAP_MEM_ALLOC]], ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], align 8 938 // CHECK4-NEXT: store ptr [[OMP_CONST_MEM_ALLOC]], ptr [[OMP_CONST_MEM_ALLOC_ADDR]], align 8 939 // CHECK4-NEXT: store ptr [[OMP_HIGH_BW_MEM_ALLOC]], ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], align 8 940 // CHECK4-NEXT: store ptr [[OMP_LOW_LAT_MEM_ALLOC]], ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], align 8 941 // CHECK4-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8 942 // CHECK4-NEXT: store ptr [[OMP_THREAD_MEM_ALLOC]], ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 8 943 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 944 // CHECK4-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[TMP0]], i32 0, i32 0 945 // CHECK4-NEXT: store ptr [[A1]], ptr [[A]], align 8 946 // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8 947 // CHECK4-NEXT: [[TMP2:%.*]] = load double, ptr [[TMP1]], align 8 948 // CHECK4-NEXT: store double [[TMP2]], ptr [[A_CASTED]], align 8 949 // CHECK4-NEXT: [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 8 950 // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 11, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70.omp_outlined.omp_outlined, ptr [[TMP0]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], ptr [[OMP_NULL_ALLOCATOR_ADDR]], ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], ptr [[OMP_CONST_MEM_ALLOC_ADDR]], ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], i64 [[TMP3]]) 951 // CHECK4-NEXT: ret void 952 // 953 // 954 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70.omp_outlined.omp_outlined 955 // CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_CGROUP_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_NULL_ALLOCATOR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_DEFAULT_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_LARGE_CAP_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_CONST_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_HIGH_BW_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_LOW_LAT_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_PTEAM_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_THREAD_MEM_ALLOC:%.*]], i64 noundef [[A:%.*]]) #[[ATTR8]] personality ptr @__gxx_personality_v0 { 956 // CHECK4-NEXT: entry: 957 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 958 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 959 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 960 // CHECK4-NEXT: [[OMP_CGROUP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 961 // CHECK4-NEXT: [[OMP_NULL_ALLOCATOR_ADDR:%.*]] = alloca ptr, align 8 962 // CHECK4-NEXT: [[OMP_DEFAULT_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 963 // CHECK4-NEXT: [[OMP_LARGE_CAP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 964 // CHECK4-NEXT: [[OMP_CONST_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 965 // CHECK4-NEXT: [[OMP_HIGH_BW_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 966 // CHECK4-NEXT: [[OMP_LOW_LAT_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 967 // CHECK4-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 968 // CHECK4-NEXT: [[OMP_THREAD_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 969 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 970 // CHECK4-NEXT: [[TMP:%.*]] = alloca ptr, align 8 971 // CHECK4-NEXT: [[A1:%.*]] = alloca double, align 8 972 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 973 // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 974 // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 975 // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 976 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 977 // CHECK4-NEXT: store ptr [[OMP_CGROUP_MEM_ALLOC]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8 978 // CHECK4-NEXT: store ptr [[OMP_NULL_ALLOCATOR]], ptr [[OMP_NULL_ALLOCATOR_ADDR]], align 8 979 // CHECK4-NEXT: store ptr [[OMP_DEFAULT_MEM_ALLOC]], ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], align 8 980 // CHECK4-NEXT: store ptr [[OMP_LARGE_CAP_MEM_ALLOC]], ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], align 8 981 // CHECK4-NEXT: store ptr [[OMP_CONST_MEM_ALLOC]], ptr [[OMP_CONST_MEM_ALLOC_ADDR]], align 8 982 // CHECK4-NEXT: store ptr [[OMP_HIGH_BW_MEM_ALLOC]], ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], align 8 983 // CHECK4-NEXT: store ptr [[OMP_LOW_LAT_MEM_ALLOC]], ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], align 8 984 // CHECK4-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8 985 // CHECK4-NEXT: store ptr [[OMP_THREAD_MEM_ALLOC]], ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 8 986 // CHECK4-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 987 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 988 // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8 989 // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OMP_NULL_ALLOCATOR_ADDR]], align 8 990 // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], align 8 991 // CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], align 8 992 // CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[OMP_CONST_MEM_ALLOC_ADDR]], align 8 993 // CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], align 8 994 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], align 8 995 // CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8 996 // CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 8 997 // CHECK4-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 998 // CHECK4-NEXT: store ptr [[A1]], ptr [[_TMP2]], align 8 999 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 1000 // CHECK4-NEXT: store ptr [[TMP0]], ptr [[TMP10]], align 8 1001 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 1002 // CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 8 1003 // CHECK4-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8 1004 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 2 1005 // CHECK4-NEXT: store ptr [[TMP1]], ptr [[TMP13]], align 8 1006 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 3 1007 // CHECK4-NEXT: store ptr [[TMP2]], ptr [[TMP14]], align 8 1008 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 4 1009 // CHECK4-NEXT: store ptr [[TMP3]], ptr [[TMP15]], align 8 1010 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 5 1011 // CHECK4-NEXT: store ptr [[TMP4]], ptr [[TMP16]], align 8 1012 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 6 1013 // CHECK4-NEXT: store ptr [[TMP5]], ptr [[TMP17]], align 8 1014 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 7 1015 // CHECK4-NEXT: store ptr [[TMP6]], ptr [[TMP18]], align 8 1016 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 8 1017 // CHECK4-NEXT: store ptr [[TMP7]], ptr [[TMP19]], align 8 1018 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 9 1019 // CHECK4-NEXT: store ptr [[TMP8]], ptr [[TMP20]], align 8 1020 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 10 1021 // CHECK4-NEXT: store ptr [[TMP9]], ptr [[TMP21]], align 8 1022 // CHECK4-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(88) [[REF_TMP]]) 1023 // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 1024 // CHECK4: invoke.cont: 1025 // CHECK4-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1026 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4 1027 // CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP23]]) 1028 // CHECK4-NEXT: ret void 1029 // CHECK4: terminate.lpad: 1030 // CHECK4-NEXT: [[TMP24:%.*]] = landingpad { ptr, i32 } 1031 // CHECK4-NEXT: catch ptr null 1032 // CHECK4-NEXT: [[TMP25:%.*]] = extractvalue { ptr, i32 } [[TMP24]], 0 1033 // CHECK4-NEXT: call void @__clang_call_terminate(ptr [[TMP25]]) #[[ATTR10]] 1034 // CHECK4-NEXT: unreachable 1035 // 1036 // 1037 // CHECK4-LABEL: define {{[^@]+}}@_ZZN3SSTIdEC1EvENKUlvE_clEv 1038 // CHECK4-SAME: (ptr noundef nonnull align 8 dereferenceable(88) [[THIS:%.*]]) #[[ATTR1]] align 2 { 1039 // CHECK4-NEXT: entry: 1040 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1041 // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1042 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1043 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1044 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON:%.*]], ptr [[THIS1]], i32 0, i32 0 1045 // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 1046 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 1047 // CHECK4-NEXT: store ptr [[TMP1]], ptr [[TMP2]], align 8 1048 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 1049 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1 1050 // CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 1051 // CHECK4-NEXT: store ptr [[TMP5]], ptr [[TMP3]], align 8 1052 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 1053 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 2 1054 // CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 1055 // CHECK4-NEXT: store ptr [[TMP8]], ptr [[TMP6]], align 8 1056 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3 1057 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 3 1058 // CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8 1059 // CHECK4-NEXT: store ptr [[TMP11]], ptr [[TMP9]], align 8 1060 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 4 1061 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 4 1062 // CHECK4-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8 1063 // CHECK4-NEXT: store ptr [[TMP14]], ptr [[TMP12]], align 8 1064 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 5 1065 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 5 1066 // CHECK4-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8 1067 // CHECK4-NEXT: store ptr [[TMP17]], ptr [[TMP15]], align 8 1068 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 6 1069 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 6 1070 // CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8 1071 // CHECK4-NEXT: store ptr [[TMP20]], ptr [[TMP18]], align 8 1072 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 7 1073 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 7 1074 // CHECK4-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP22]], align 8 1075 // CHECK4-NEXT: store ptr [[TMP23]], ptr [[TMP21]], align 8 1076 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 8 1077 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 8 1078 // CHECK4-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 8 1079 // CHECK4-NEXT: store ptr [[TMP26]], ptr [[TMP24]], align 8 1080 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 9 1081 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 9 1082 // CHECK4-NEXT: [[TMP29:%.*]] = load ptr, ptr [[TMP28]], align 8 1083 // CHECK4-NEXT: store ptr [[TMP29]], ptr [[TMP27]], align 8 1084 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 10 1085 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 10 1086 // CHECK4-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 8 1087 // CHECK4-NEXT: store ptr [[TMP32]], ptr [[TMP30]], align 8 1088 // CHECK4-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(88) [[REF_TMP]]) 1089 // CHECK4-NEXT: ret void 1090 // 1091 // 1092 // CHECK4-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv 1093 // CHECK4-SAME: (ptr noundef nonnull align 8 dereferenceable(88) [[THIS:%.*]]) #[[ATTR2]] align 2 { 1094 // CHECK4-NEXT: entry: 1095 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1096 // CHECK4-NEXT: [[C:%.*]] = alloca i32, align 4 1097 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1098 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1099 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1100 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1101 // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 1102 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 1103 // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 1104 // CHECK4-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP3]], align 8 1105 // CHECK4-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 1106 // CHECK4-NEXT: store double [[INC]], ptr [[TMP3]], align 8 1107 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2 1108 // CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 1109 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 1110 // CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 1111 // CHECK4-NEXT: [[TMP9:%.*]] = load double, ptr [[TMP8]], align 8 1112 // CHECK4-NEXT: store double [[TMP9]], ptr [[A_CASTED]], align 8 1113 // CHECK4-NEXT: [[TMP10:%.*]] = load i64, ptr [[A_CASTED]], align 8 1114 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3 1115 // CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 1116 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 4 1117 // CHECK4-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8 1118 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 5 1119 // CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 1120 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 6 1121 // CHECK4-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 1122 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 7 1123 // CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8 1124 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 8 1125 // CHECK4-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8 1126 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 9 1127 // CHECK4-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8 1128 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 10 1129 // CHECK4-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 8 1130 // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 11, ptr @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv.omp_outlined, ptr [[TMP1]], ptr [[TMP6]], i64 [[TMP10]], ptr [[TMP12]], ptr [[TMP14]], ptr [[TMP16]], ptr [[TMP18]], ptr [[TMP20]], ptr [[TMP22]], ptr [[TMP24]], ptr [[TMP26]]) 1131 // CHECK4-NEXT: ret void 1132 // 1133 // 1134 // CHECK4-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv.omp_outlined 1135 // CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_CGROUP_MEM_ALLOC:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_NULL_ALLOCATOR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_DEFAULT_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_LARGE_CAP_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_CONST_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_HIGH_BW_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_LOW_LAT_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_PTEAM_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_THREAD_MEM_ALLOC:%.*]]) #[[ATTR8]] { 1136 // CHECK4-NEXT: entry: 1137 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1138 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1139 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1140 // CHECK4-NEXT: [[OMP_CGROUP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 1141 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1142 // CHECK4-NEXT: [[OMP_NULL_ALLOCATOR_ADDR:%.*]] = alloca ptr, align 8 1143 // CHECK4-NEXT: [[OMP_DEFAULT_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 1144 // CHECK4-NEXT: [[OMP_LARGE_CAP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 1145 // CHECK4-NEXT: [[OMP_CONST_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 1146 // CHECK4-NEXT: [[OMP_HIGH_BW_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 1147 // CHECK4-NEXT: [[OMP_LOW_LAT_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 1148 // CHECK4-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 1149 // CHECK4-NEXT: [[OMP_THREAD_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 1150 // CHECK4-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1151 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1152 // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1153 // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1154 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1155 // CHECK4-NEXT: store ptr [[OMP_CGROUP_MEM_ALLOC]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8 1156 // CHECK4-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1157 // CHECK4-NEXT: store ptr [[OMP_NULL_ALLOCATOR]], ptr [[OMP_NULL_ALLOCATOR_ADDR]], align 8 1158 // CHECK4-NEXT: store ptr [[OMP_DEFAULT_MEM_ALLOC]], ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], align 8 1159 // CHECK4-NEXT: store ptr [[OMP_LARGE_CAP_MEM_ALLOC]], ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], align 8 1160 // CHECK4-NEXT: store ptr [[OMP_CONST_MEM_ALLOC]], ptr [[OMP_CONST_MEM_ALLOC_ADDR]], align 8 1161 // CHECK4-NEXT: store ptr [[OMP_HIGH_BW_MEM_ALLOC]], ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], align 8 1162 // CHECK4-NEXT: store ptr [[OMP_LOW_LAT_MEM_ALLOC]], ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], align 8 1163 // CHECK4-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8 1164 // CHECK4-NEXT: store ptr [[OMP_THREAD_MEM_ALLOC]], ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 8 1165 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1166 // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8 1167 // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OMP_NULL_ALLOCATOR_ADDR]], align 8 1168 // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], align 8 1169 // CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], align 8 1170 // CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[OMP_CONST_MEM_ALLOC_ADDR]], align 8 1171 // CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], align 8 1172 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], align 8 1173 // CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8 1174 // CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 8 1175 // CHECK4-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 1176 // CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1177 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 1178 // CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8 1179 // CHECK4-NEXT: [[DOTA__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP11]], i64 8, ptr [[TMP12]]) 1180 // CHECK4-NEXT: store ptr [[DOTA__VOID_ADDR]], ptr [[_TMP1]], align 8 1181 // CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP1]], align 8 1182 // CHECK4-NEXT: [[TMP14:%.*]] = load double, ptr [[TMP13]], align 8 1183 // CHECK4-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 1184 // CHECK4-NEXT: store double [[INC]], ptr [[TMP13]], align 8 1185 // CHECK4-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP1]], align 8 1186 // CHECK4-NEXT: call void @__kmpc_free(i32 [[TMP11]], ptr [[DOTA__VOID_ADDR]], ptr [[TMP15]]) 1187 // CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP11]]) 1188 // CHECK4-NEXT: ret void 1189 // 1190 // 1191 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 1192 // CHECK4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 personality ptr @__gxx_personality_v0 { 1193 // CHECK4-NEXT: entry: 1194 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1195 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 1196 // CHECK4-NEXT: [[A2:%.*]] = alloca i32, align 4 1197 // CHECK4-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1198 // CHECK4-NEXT: [[C3:%.*]] = alloca i32, align 4 1199 // CHECK4-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8 1200 // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 1201 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 1202 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1203 // CHECK4-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 1204 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1205 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 1 1206 // CHECK4-NEXT: store i32 0, ptr [[A]], align 4 1207 // CHECK4-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 1208 // CHECK4-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 8 1209 // CHECK4-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 1210 // CHECK4-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 1211 // CHECK4-NEXT: store i8 [[BF_SET]], ptr [[B]], align 8 1212 // CHECK4-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3 1213 // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8 1214 // CHECK4-NEXT: store ptr [[TMP1]], ptr [[C]], align 8 1215 // CHECK4-NEXT: store ptr [[A2]], ptr [[TMP]], align 8 1216 // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 8 1217 // CHECK4-NEXT: [[DOTB__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP0]], i64 4, ptr [[TMP2]]) 1218 // CHECK4-NEXT: store ptr [[C3]], ptr [[_TMP4]], align 8 1219 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0 1220 // CHECK4-NEXT: store ptr [[THIS1]], ptr [[TMP3]], align 8 1221 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1 1222 // CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 1223 // CHECK4-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8 1224 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 2 1225 // CHECK4-NEXT: store ptr [[DOTB__VOID_ADDR]], ptr [[TMP6]], align 8 1226 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 3 1227 // CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8 1228 // CHECK4-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8 1229 // CHECK4-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) 1230 // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 1231 // CHECK4: invoke.cont: 1232 // CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 8 1233 // CHECK4-NEXT: call void @__kmpc_free(i32 [[TMP0]], ptr [[DOTB__VOID_ADDR]], ptr [[TMP9]]) 1234 // CHECK4-NEXT: ret void 1235 // CHECK4: terminate.lpad: 1236 // CHECK4-NEXT: [[TMP10:%.*]] = landingpad { ptr, i32 } 1237 // CHECK4-NEXT: catch ptr null 1238 // CHECK4-NEXT: [[TMP11:%.*]] = extractvalue { ptr, i32 } [[TMP10]], 0 1239 // CHECK4-NEXT: call void @__clang_call_terminate(ptr [[TMP11]]) #[[ATTR10]] 1240 // CHECK4-NEXT: unreachable 1241 // 1242 // 1243 // CHECK4-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv 1244 // CHECK4-SAME: (ptr noundef nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2]] align 2 { 1245 // CHECK4-NEXT: entry: 1246 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1247 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 1248 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1249 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1250 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1:%.*]], ptr [[THIS1]], i32 0, i32 0 1251 // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 1252 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1 1253 // CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 1254 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 1255 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 1256 // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP4]], align 4 1257 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2 1258 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 1259 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1260 // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 1261 // CHECK4-NEXT: store i32 [[DEC]], ptr [[TMP7]], align 4 1262 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3 1263 // CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 1264 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 1265 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1 1266 // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 4 1267 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2 1268 // CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8 1269 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 1270 // CHECK4-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP14]]) 1271 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1 1272 // CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 1273 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2 1274 // CHECK4-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 1275 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3 1276 // CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8 1277 // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP2]], ptr [[TMP16]], ptr [[TMP18]], ptr [[TMP20]]) 1278 // CHECK4-NEXT: ret void 1279 // 1280 // 1281 // CHECK4-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined 1282 // CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR8]] { 1283 // CHECK4-NEXT: entry: 1284 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1285 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1286 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1287 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 1288 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1289 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1290 // CHECK4-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1291 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1292 // CHECK4-NEXT: [[E:%.*]] = alloca ptr, align 8 1293 // CHECK4-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 1294 // CHECK4-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8 1295 // CHECK4-NEXT: [[_TMP5:%.*]] = alloca ptr, align 8 1296 // CHECK4-NEXT: [[A6:%.*]] = alloca i32, align 4 1297 // CHECK4-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 1298 // CHECK4-NEXT: [[B8:%.*]] = alloca i32, align 4 1299 // CHECK4-NEXT: [[C9:%.*]] = alloca i32, align 4 1300 // CHECK4-NEXT: [[_TMP10:%.*]] = alloca ptr, align 8 1301 // CHECK4-NEXT: [[E11:%.*]] = alloca i32, align 4 1302 // CHECK4-NEXT: [[_TMP12:%.*]] = alloca ptr, align 8 1303 // CHECK4-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 1304 // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1305 // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1306 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1307 // CHECK4-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 1308 // CHECK4-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1309 // CHECK4-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1310 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1311 // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 1312 // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1313 // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1314 // CHECK4-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 1315 // CHECK4-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8 1316 // CHECK4-NEXT: [[E2:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 1317 // CHECK4-NEXT: store ptr [[E2]], ptr [[E]], align 8 1318 // CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 1319 // CHECK4-NEXT: store ptr [[TMP4]], ptr [[_TMP3]], align 8 1320 // CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[E]], align 8 1321 // CHECK4-NEXT: store ptr [[TMP5]], ptr [[_TMP4]], align 8 1322 // CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8 1323 // CHECK4-NEXT: store ptr [[TMP6]], ptr [[_TMP5]], align 8 1324 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8 1325 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1326 // CHECK4-NEXT: store i32 [[TMP8]], ptr [[A6]], align 4 1327 // CHECK4-NEXT: store ptr [[A6]], ptr [[_TMP7]], align 8 1328 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP2]], align 4 1329 // CHECK4-NEXT: store i32 [[TMP9]], ptr [[B8]], align 4 1330 // CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 8 1331 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 1332 // CHECK4-NEXT: store i32 [[TMP11]], ptr [[C9]], align 4 1333 // CHECK4-NEXT: store ptr [[C9]], ptr [[_TMP10]], align 8 1334 // CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8 1335 // CHECK4-NEXT: store i32 0, ptr [[E11]], align 4 1336 // CHECK4-NEXT: store ptr [[E11]], ptr [[_TMP12]], align 8 1337 // CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP7]], align 8 1338 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 1339 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 1340 // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP13]], align 4 1341 // CHECK4-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP12]], align 8 1342 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 1343 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 1344 // CHECK4-NEXT: store i32 [[ADD]], ptr [[TMP15]], align 4 1345 // CHECK4-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP10]], align 8 1346 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 1347 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP18]], 1 1348 // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP17]], align 4 1349 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 1350 // CHECK4-NEXT: store ptr [[E11]], ptr [[TMP19]], align 8 1351 // CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1352 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 1353 // CHECK4-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB3:[0-9]+]], i32 [[TMP21]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 1354 // CHECK4-NEXT: switch i32 [[TMP22]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1355 // CHECK4-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1356 // CHECK4-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1357 // CHECK4-NEXT: ] 1358 // CHECK4: .omp.reduction.case1: 1359 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP12]], align 4 1360 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, ptr [[E11]], align 4 1361 // CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] 1362 // CHECK4-NEXT: store i32 [[ADD13]], ptr [[TMP12]], align 4 1363 // CHECK4-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP21]], ptr @.gomp_critical_user_.reduction.var) 1364 // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1365 // CHECK4: .omp.reduction.case2: 1366 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, ptr [[E11]], align 4 1367 // CHECK4-NEXT: [[TMP26:%.*]] = atomicrmw add ptr [[TMP12]], i32 [[TMP25]] monotonic, align 4 1368 // CHECK4-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP21]], ptr @.gomp_critical_user_.reduction.var) 1369 // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1370 // CHECK4: .omp.reduction.default: 1371 // CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP21]]) 1372 // CHECK4-NEXT: ret void 1373 // 1374 // 1375 // CHECK4-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined.omp.reduction.reduction_func 1376 // CHECK4-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR9:[0-9]+]] { 1377 // CHECK4-NEXT: entry: 1378 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1379 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 1380 // CHECK4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1381 // CHECK4-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 1382 // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 1383 // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 1384 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 1385 // CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 1386 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 1387 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 1388 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1389 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 1390 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 1391 // CHECK4-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 1392 // CHECK4-NEXT: ret void 1393 // 1394 // 1395 // CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassC2ERKS_ 1396 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 1397 // CHECK4-NEXT: entry: 1398 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1399 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1400 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1401 // CHECK4-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1402 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1403 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS:%.*]], ptr [[THIS1]], i32 0, i32 0 1404 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1405 // CHECK4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS]], ptr [[TMP0]], i32 0, i32 0 1406 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[A2]], align 4 1407 // CHECK4-NEXT: store i32 [[TMP1]], ptr [[A]], align 4 1408 // CHECK4-NEXT: ret void 1409 // 1410 // 1411 // CHECK4-LABEL: define {{[^@]+}}@_Z15parallel_singlev 1412 // CHECK4-SAME: () #[[ATTR2]] { 1413 // CHECK4-NEXT: entry: 1414 // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @_Z15parallel_singlev.omp_outlined) 1415 // CHECK4-NEXT: ret void 1416 // 1417 // 1418 // CHECK4-LABEL: define {{[^@]+}}@_Z15parallel_singlev.omp_outlined 1419 // CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR8]] personality ptr @__gxx_personality_v0 { 1420 // CHECK4-NEXT: entry: 1421 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1422 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1423 // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1424 // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1425 // CHECK4-NEXT: invoke void @_Z3foov() 1426 // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 1427 // CHECK4: invoke.cont: 1428 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1429 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1430 // CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP1]]) 1431 // CHECK4-NEXT: ret void 1432 // CHECK4: terminate.lpad: 1433 // CHECK4-NEXT: [[TMP2:%.*]] = landingpad { ptr, i32 } 1434 // CHECK4-NEXT: catch ptr null 1435 // CHECK4-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0 1436 // CHECK4-NEXT: call void @__clang_call_terminate(ptr [[TMP3]]) #[[ATTR10]] 1437 // CHECK4-NEXT: unreachable 1438 // 1439 // 1440 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_scope_codegen.cpp 1441 // CHECK4-SAME: () #[[ATTR0]] { 1442 // CHECK4-NEXT: entry: 1443 // CHECK4-NEXT: call void @__cxx_global_var_init() 1444 // CHECK4-NEXT: call void @__cxx_global_var_init.1() 1445 // CHECK4-NEXT: ret void 1446 // 1447 // 1448 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 1449 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG6:![0-9]+]] { 1450 // CHECK5-NEXT: entry: 1451 // CHECK5-NEXT: call void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @tc), !dbg [[DBG9:![0-9]+]] 1452 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN9TestClassD1Ev, ptr @tc, ptr @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG12:![0-9]+]] 1453 // CHECK5-NEXT: ret void, !dbg [[DBG9]] 1454 // 1455 // 1456 // CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassC1Ev 1457 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 !dbg [[DBG13:![0-9]+]] { 1458 // CHECK5-NEXT: entry: 1459 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1460 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1461 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1462 // CHECK5-NEXT: call void @_ZN9TestClassC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]), !dbg [[DBG14:![0-9]+]] 1463 // CHECK5-NEXT: ret void, !dbg [[DBG15:![0-9]+]] 1464 // 1465 // 1466 // CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev 1467 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 !dbg [[DBG16:![0-9]+]] { 1468 // CHECK5-NEXT: entry: 1469 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1470 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1471 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1472 // CHECK5-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG17:![0-9]+]] 1473 // CHECK5-NEXT: ret void, !dbg [[DBG18:![0-9]+]] 1474 // 1475 // 1476 // CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassC2Ev 1477 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG19:![0-9]+]] { 1478 // CHECK5-NEXT: entry: 1479 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1480 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1481 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1482 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG20:![0-9]+]] 1483 // CHECK5-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG20]] 1484 // CHECK5-NEXT: ret void, !dbg [[DBG21:![0-9]+]] 1485 // 1486 // 1487 // CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev 1488 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG22:![0-9]+]] { 1489 // CHECK5-NEXT: entry: 1490 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1491 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1492 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1493 // CHECK5-NEXT: ret void, !dbg [[DBG23:![0-9]+]] 1494 // 1495 // 1496 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1497 // CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" personality ptr @__gxx_personality_v0 !dbg [[DBG24:![0-9]+]] { 1498 // CHECK5-NEXT: entry: 1499 // CHECK5-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 1500 // CHECK5-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 1501 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]], !dbg [[DBG25:![0-9]+]] 1502 // CHECK5: arrayctor.loop: 1503 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ @tc2, [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ], !dbg [[DBG25]] 1504 // CHECK5-NEXT: invoke void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1505 // CHECK5-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]], !dbg [[DBG25]] 1506 // CHECK5: invoke.cont: 1507 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], ptr [[ARRAYCTOR_CUR]], i64 1, !dbg [[DBG25]] 1508 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[CLASS_TESTCLASS]], ptr @tc2, i64 2), !dbg [[DBG25]] 1509 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]], !dbg [[DBG25]] 1510 // CHECK5: arrayctor.cont: 1511 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG27:![0-9]+]] 1512 // CHECK5-NEXT: ret void, !dbg [[DBG27]] 1513 // CHECK5: lpad: 1514 // CHECK5-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } 1515 // CHECK5-NEXT: cleanup, !dbg [[DBG28:![0-9]+]] 1516 // CHECK5-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG28]] 1517 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG28]] 1518 // CHECK5-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG28]] 1519 // CHECK5-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG28]] 1520 // CHECK5-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @tc2, [[ARRAYCTOR_CUR]], !dbg [[DBG25]] 1521 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG25]] 1522 // CHECK5: arraydestroy.body: 1523 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG25]] 1524 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG25]] 1525 // CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG25]] 1526 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2, !dbg [[DBG25]] 1527 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG25]] 1528 // CHECK5: arraydestroy.done1: 1529 // CHECK5-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG25]] 1530 // CHECK5: eh.resume: 1531 // CHECK5-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG25]] 1532 // CHECK5-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG25]] 1533 // CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG25]] 1534 // CHECK5-NEXT: [[LPAD_VAL2:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG25]] 1535 // CHECK5-NEXT: resume { ptr, i32 } [[LPAD_VAL2]], !dbg [[DBG25]] 1536 // 1537 // 1538 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1539 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG29:![0-9]+]] { 1540 // CHECK5-NEXT: entry: 1541 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1542 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1543 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG30:![0-9]+]] 1544 // CHECK5: arraydestroy.body: 1545 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], ptr @tc2, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG30]] 1546 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG30]] 1547 // CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG30]] 1548 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2, !dbg [[DBG30]] 1549 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG30]] 1550 // CHECK5: arraydestroy.done1: 1551 // CHECK5-NEXT: ret void, !dbg [[DBG30]] 1552 // 1553 // 1554 // CHECK5-LABEL: define {{[^@]+}}@_Z3foov 1555 // CHECK5-SAME: () #[[ATTR1]] !dbg [[DBG31:![0-9]+]] { 1556 // CHECK5-NEXT: entry: 1557 // CHECK5-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG32:![0-9]+]] 1558 // CHECK5-NEXT: ret void, !dbg [[DBG33:![0-9]+]] 1559 // 1560 // 1561 // CHECK5-LABEL: define {{[^@]+}}@main 1562 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] personality ptr @__gxx_personality_v0 !dbg [[DBG34:![0-9]+]] { 1563 // CHECK5-NEXT: entry: 1564 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1565 // CHECK5-NEXT: [[A:%.*]] = alloca i8, align 1 1566 // CHECK5-NEXT: [[A2:%.*]] = alloca [2 x i8], align 1 1567 // CHECK5-NEXT: [[C:%.*]] = alloca ptr, align 8 1568 // CHECK5-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 8 1569 // CHECK5-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 1570 // CHECK5-NEXT: [[A1:%.*]] = alloca i8, align 1 1571 // CHECK5-NEXT: [[C2:%.*]] = alloca [[CLASS_TESTCLASS:%.*]], align 4 1572 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1573 // CHECK5-NEXT: [[TC:%.*]] = alloca [[CLASS_TESTCLASS]], align 4 1574 // CHECK5-NEXT: [[A24:%.*]] = alloca [2 x i8], align 1 1575 // CHECK5-NEXT: [[TC2:%.*]] = alloca [2 x %class.TestClass], align 4 1576 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]), !dbg [[DBG35:![0-9]+]] 1577 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 1578 // CHECK5-NEXT: store ptr @tc, ptr [[C]], align 8, !dbg [[DBG36:![0-9]+]] 1579 // CHECK5-NEXT: call void @_ZN3SSTIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[SST]]), !dbg [[DBG37:![0-9]+]] 1580 // CHECK5-NEXT: call void @_ZN2SSC1ERi(ptr noundef nonnull align 8 dereferenceable(24) [[SS]], ptr noundef nonnull align 4 dereferenceable(4) @tc), !dbg [[DBG38:![0-9]+]] 1581 // CHECK5-NEXT: store i8 2, ptr [[A]], align 1, !dbg [[DBG39:![0-9]+]] 1582 // CHECK5-NEXT: store i8 2, ptr [[A]], align 1, !dbg [[DBG40:![0-9]+]] 1583 // CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]]), !dbg [[DBG41:![0-9]+]] 1584 // CHECK5-NEXT: [[TMP1:%.*]] = load i8, ptr [[A]], align 1, !dbg [[DBG42:![0-9]+]] 1585 // CHECK5-NEXT: store i8 [[TMP1]], ptr [[A1]], align 1, !dbg [[DBG42]] 1586 // CHECK5-NEXT: invoke void @_ZN9TestClassC1ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[C2]], ptr noundef nonnull align 4 dereferenceable(4) @tc) 1587 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG43:![0-9]+]] 1588 // CHECK5: invoke.cont: 1589 // CHECK5-NEXT: store ptr [[C2]], ptr [[TMP]], align 8, !dbg [[DBG44:![0-9]+]] 1590 // CHECK5-NEXT: invoke void @_ZN9TestClassC1ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[TC]], ptr noundef nonnull align 4 dereferenceable(4) @tc) 1591 // CHECK5-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[TERMINATE_LPAD]], !dbg [[DBG45:![0-9]+]] 1592 // CHECK5: invoke.cont3: 1593 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TC2]], i32 0, i32 0, !dbg [[DBG46:![0-9]+]] 1594 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN]], i64 2, !dbg [[DBG46]] 1595 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]], !dbg [[DBG46]] 1596 // CHECK5: arrayctor.loop: 1597 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[INVOKE_CONT3]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT5:%.*]] ], !dbg [[DBG46]] 1598 // CHECK5-NEXT: invoke void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1599 // CHECK5-NEXT: to label [[INVOKE_CONT5]] unwind label [[TERMINATE_LPAD]], !dbg [[DBG46]] 1600 // CHECK5: invoke.cont5: 1601 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYCTOR_CUR]], i64 1, !dbg [[DBG46]] 1602 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]], !dbg [[DBG46]] 1603 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]], !dbg [[DBG46]] 1604 // CHECK5: arrayctor.cont: 1605 // CHECK5-NEXT: invoke void @_Z3foov() 1606 // CHECK5-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]], !dbg [[DBG47:![0-9]+]] 1607 // CHECK5: invoke.cont6: 1608 // CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TC2]], i32 0, i32 0, !dbg [[DBG47]] 1609 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN7]], i64 2, !dbg [[DBG47]] 1610 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG47]] 1611 // CHECK5: arraydestroy.body: 1612 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[INVOKE_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG47]] 1613 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG47]] 1614 // CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG47]] 1615 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]], !dbg [[DBG47]] 1616 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG47]] 1617 // CHECK5: arraydestroy.done8: 1618 // CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TC]]) #[[ATTR3]], !dbg [[DBG47]] 1619 // CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[C2]]) #[[ATTR3]], !dbg [[DBG47]] 1620 // CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[TMP0]]), !dbg [[DBG48:![0-9]+]] 1621 // CHECK5-NEXT: [[TMP3:%.*]] = load i8, ptr [[A]], align 1, !dbg [[DBG49:![0-9]+]] 1622 // CHECK5-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32, !dbg [[DBG49]] 1623 // CHECK5-NEXT: ret i32 [[CONV]], !dbg [[DBG50:![0-9]+]] 1624 // CHECK5: terminate.lpad: 1625 // CHECK5-NEXT: [[TMP4:%.*]] = landingpad { ptr, i32 } 1626 // CHECK5-NEXT: catch ptr null, !dbg [[DBG43]] 1627 // CHECK5-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP4]], 0, !dbg [[DBG43]] 1628 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP5]]) #[[ATTR10:[0-9]+]], !dbg [[DBG43]] 1629 // CHECK5-NEXT: unreachable, !dbg [[DBG43]] 1630 // 1631 // 1632 // CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIdEC1Ev 1633 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG51:![0-9]+]] { 1634 // CHECK5-NEXT: entry: 1635 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1636 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1637 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1638 // CHECK5-NEXT: call void @_ZN3SSTIdEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]), !dbg [[DBG52:![0-9]+]] 1639 // CHECK5-NEXT: ret void, !dbg [[DBG53:![0-9]+]] 1640 // 1641 // 1642 // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 1643 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG54:![0-9]+]] { 1644 // CHECK5-NEXT: entry: 1645 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1646 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 1647 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1648 // CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 1649 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1650 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG55:![0-9]+]] 1651 // CHECK5-NEXT: call void @_ZN2SSC2ERi(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]]), !dbg [[DBG55]] 1652 // CHECK5-NEXT: ret void, !dbg [[DBG56:![0-9]+]] 1653 // 1654 // 1655 // CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassC1ERKS_ 1656 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG57:![0-9]+]] { 1657 // CHECK5-NEXT: entry: 1658 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1659 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1660 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1661 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1662 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1663 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG58:![0-9]+]] 1664 // CHECK5-NEXT: call void @_ZN9TestClassC2ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]]), !dbg [[DBG58]] 1665 // CHECK5-NEXT: ret void, !dbg [[DBG59:![0-9]+]] 1666 // 1667 // 1668 // CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate 1669 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR7:[0-9]+]] { 1670 // CHECK5-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR3]] 1671 // CHECK5-NEXT: call void @_ZSt9terminatev() #[[ATTR10]] 1672 // CHECK5-NEXT: unreachable 1673 // 1674 // 1675 // CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIdEC2Ev 1676 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG60:![0-9]+]] { 1677 // CHECK5-NEXT: entry: 1678 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1679 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1680 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1681 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG61:![0-9]+]] 1682 // CHECK5-NEXT: store double 0.000000e+00, ptr [[A]], align 8, !dbg [[DBG61]] 1683 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr @omp_cgroup_mem_alloc, align 8, !dbg [[DBG62:![0-9]+]] 1684 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70(ptr [[THIS1]], ptr [[TMP0]]) #[[ATTR3]], !dbg [[DBG62]] 1685 // CHECK5-NEXT: ret void, !dbg [[DBG63:![0-9]+]] 1686 // 1687 // 1688 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70 1689 // CHECK5-SAME: (ptr noundef [[THIS:%.*]], ptr noundef [[OMP_CGROUP_MEM_ALLOC:%.*]]) #[[ATTR8:[0-9]+]] !dbg [[DBG64:![0-9]+]] { 1690 // CHECK5-NEXT: entry: 1691 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1692 // CHECK5-NEXT: [[OMP_CGROUP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 1693 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1694 // CHECK5-NEXT: store ptr [[OMP_CGROUP_MEM_ALLOC]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8 1695 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG65:![0-9]+]] 1696 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8, !dbg [[DBG65]] 1697 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB10:[0-9]+]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]), !dbg [[DBG65]] 1698 // CHECK5-NEXT: ret void, !dbg [[DBG66:![0-9]+]] 1699 // 1700 // 1701 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70.omp_outlined 1702 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef [[OMP_CGROUP_MEM_ALLOC:%.*]]) #[[ATTR8]] !dbg [[DBG67:![0-9]+]] { 1703 // CHECK5-NEXT: entry: 1704 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1705 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1706 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1707 // CHECK5-NEXT: [[OMP_CGROUP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 1708 // CHECK5-NEXT: [[A:%.*]] = alloca ptr, align 8 1709 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1710 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1711 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1712 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1713 // CHECK5-NEXT: store ptr [[OMP_CGROUP_MEM_ALLOC]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8 1714 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG68:![0-9]+]] 1715 // CHECK5-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG69:![0-9]+]] 1716 // CHECK5-NEXT: store ptr [[A1]], ptr [[A]], align 8, !dbg [[DBG69]] 1717 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8, !dbg [[DBG69]] 1718 // CHECK5-NEXT: [[TMP2:%.*]] = load double, ptr [[TMP1]], align 8, !dbg [[DBG70:![0-9]+]] 1719 // CHECK5-NEXT: store double [[TMP2]], ptr [[A_CASTED]], align 8, !dbg [[DBG70]] 1720 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG70]] 1721 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB8:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70.omp_outlined.omp_outlined, ptr [[TMP0]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], i64 [[TMP3]]), !dbg [[DBG70]] 1722 // CHECK5-NEXT: ret void, !dbg [[DBG71:![0-9]+]] 1723 // 1724 // 1725 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70.omp_outlined.omp_outlined 1726 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_CGROUP_MEM_ALLOC:%.*]], i64 noundef [[A:%.*]]) #[[ATTR8]] personality ptr @__gxx_personality_v0 !dbg [[DBG72:![0-9]+]] { 1727 // CHECK5-NEXT: entry: 1728 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1729 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1730 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1731 // CHECK5-NEXT: [[OMP_CGROUP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 1732 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1733 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1734 // CHECK5-NEXT: [[A1:%.*]] = alloca double, align 8 1735 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 1736 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 1737 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1738 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1739 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1740 // CHECK5-NEXT: store ptr [[OMP_CGROUP_MEM_ALLOC]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8 1741 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1742 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG73:![0-9]+]] 1743 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8, !dbg [[DBG73]] 1744 // CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG73]] 1745 // CHECK5-NEXT: store ptr [[A1]], ptr [[_TMP2]], align 8, !dbg [[DBG74:![0-9]+]] 1746 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG75:![0-9]+]] 1747 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP2]], align 8, !dbg [[DBG75]] 1748 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG75]] 1749 // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG76:![0-9]+]] 1750 // CHECK5-NEXT: store ptr [[TMP4]], ptr [[TMP3]], align 8, !dbg [[DBG75]] 1751 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 2, !dbg [[DBG75]] 1752 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP5]], align 8, !dbg [[DBG75]] 1753 // CHECK5-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 1754 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG75]] 1755 // CHECK5: invoke.cont: 1756 // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG77:![0-9]+]] 1757 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4, !dbg [[DBG77]] 1758 // CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB6:[0-9]+]], i32 [[TMP7]]), !dbg [[DBG77]] 1759 // CHECK5-NEXT: ret void, !dbg [[DBG77]] 1760 // CHECK5: terminate.lpad: 1761 // CHECK5-NEXT: [[TMP8:%.*]] = landingpad { ptr, i32 } 1762 // CHECK5-NEXT: catch ptr null, !dbg [[DBG75]] 1763 // CHECK5-NEXT: [[TMP9:%.*]] = extractvalue { ptr, i32 } [[TMP8]], 0, !dbg [[DBG75]] 1764 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP9]]) #[[ATTR10]], !dbg [[DBG75]] 1765 // CHECK5-NEXT: unreachable, !dbg [[DBG75]] 1766 // 1767 // 1768 // CHECK5-LABEL: define {{[^@]+}}@_ZZN3SSTIdEC1EvENKUlvE_clEv 1769 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR1]] align 2 !dbg [[DBG78:![0-9]+]] { 1770 // CHECK5-NEXT: entry: 1771 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1772 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1773 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1774 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1775 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON:%.*]], ptr [[THIS1]], i32 0, i32 0 1776 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 1777 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG79:![0-9]+]] 1778 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP2]], align 8, !dbg [[DBG79]] 1779 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG79]] 1780 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG80:![0-9]+]] 1781 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG80]] 1782 // CHECK5-NEXT: store ptr [[TMP5]], ptr [[TMP3]], align 8, !dbg [[DBG79]] 1783 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2, !dbg [[DBG79]] 1784 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG80]] 1785 // CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8, !dbg [[DBG80]] 1786 // CHECK5-NEXT: store ptr [[TMP8]], ptr [[TMP6]], align 8, !dbg [[DBG79]] 1787 // CHECK5-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !dbg [[DBG79]] 1788 // CHECK5-NEXT: ret void, !dbg [[DBG81:![0-9]+]] 1789 // 1790 // 1791 // CHECK5-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv 1792 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2]] align 2 !dbg [[DBG84:![0-9]+]] { 1793 // CHECK5-NEXT: entry: 1794 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1795 // CHECK5-NEXT: [[C:%.*]] = alloca i32, align 4 1796 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1797 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1798 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1799 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1800 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 1801 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG85:![0-9]+]] 1802 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG85]] 1803 // CHECK5-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP3]], align 8, !dbg [[DBG86:![0-9]+]] 1804 // CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00, !dbg [[DBG86]] 1805 // CHECK5-NEXT: store double [[INC]], ptr [[TMP3]], align 8, !dbg [[DBG86]] 1806 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG87:![0-9]+]] 1807 // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !dbg [[DBG87]] 1808 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG88:![0-9]+]] 1809 // CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8, !dbg [[DBG88]] 1810 // CHECK5-NEXT: [[TMP9:%.*]] = load double, ptr [[TMP8]], align 8, !dbg [[DBG89:![0-9]+]] 1811 // CHECK5-NEXT: store double [[TMP9]], ptr [[A_CASTED]], align 8, !dbg [[DBG89]] 1812 // CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG89]] 1813 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB14:[0-9]+]], i32 3, ptr @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv.omp_outlined, ptr [[TMP1]], ptr [[TMP6]], i64 [[TMP10]]), !dbg [[DBG89]] 1814 // CHECK5-NEXT: ret void, !dbg [[DBG90:![0-9]+]] 1815 // 1816 // 1817 // CHECK5-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv.omp_outlined 1818 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_CGROUP_MEM_ALLOC:%.*]], i64 noundef [[A:%.*]]) #[[ATTR8]] !dbg [[DBG91:![0-9]+]] { 1819 // CHECK5-NEXT: entry: 1820 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1821 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1822 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1823 // CHECK5-NEXT: [[OMP_CGROUP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8 1824 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1825 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1826 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1827 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1828 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1829 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1830 // CHECK5-NEXT: store ptr [[OMP_CGROUP_MEM_ALLOC]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8 1831 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1832 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG92:![0-9]+]] 1833 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8, !dbg [[DBG92]] 1834 // CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG92]] 1835 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG93:![0-9]+]] 1836 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG93]] 1837 // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG94:![0-9]+]] 1838 // CHECK5-NEXT: [[DOTA__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP3]], i64 8, ptr [[TMP4]]), !dbg [[DBG93]] 1839 // CHECK5-NEXT: store ptr [[DOTA__VOID_ADDR]], ptr [[_TMP1]], align 8, !dbg [[DBG93]] 1840 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG95:![0-9]+]] 1841 // CHECK5-NEXT: [[TMP6:%.*]] = load double, ptr [[TMP5]], align 8, !dbg [[DBG96:![0-9]+]] 1842 // CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00, !dbg [[DBG96]] 1843 // CHECK5-NEXT: store double [[INC]], ptr [[TMP5]], align 8, !dbg [[DBG96]] 1844 // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG94]] 1845 // CHECK5-NEXT: call void @__kmpc_free(i32 [[TMP3]], ptr [[DOTA__VOID_ADDR]], ptr [[TMP7]]), !dbg [[DBG96]] 1846 // CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB12:[0-9]+]], i32 [[TMP3]]), !dbg [[DBG97:![0-9]+]] 1847 // CHECK5-NEXT: ret void, !dbg [[DBG97]] 1848 // 1849 // 1850 // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 1851 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 personality ptr @__gxx_personality_v0 !dbg [[DBG98:![0-9]+]] { 1852 // CHECK5-NEXT: entry: 1853 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1854 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 1855 // CHECK5-NEXT: [[A2:%.*]] = alloca i32, align 4 1856 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1857 // CHECK5-NEXT: [[C3:%.*]] = alloca i32, align 4 1858 // CHECK5-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8 1859 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 1860 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB16:[0-9]+]]), !dbg [[DBG99:![0-9]+]] 1861 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1862 // CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 1863 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1864 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG100:![0-9]+]] 1865 // CHECK5-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG100]] 1866 // CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG101:![0-9]+]] 1867 // CHECK5-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 8, !dbg [[DBG101]] 1868 // CHECK5-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16, !dbg [[DBG101]] 1869 // CHECK5-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0, !dbg [[DBG101]] 1870 // CHECK5-NEXT: store i8 [[BF_SET]], ptr [[B]], align 8, !dbg [[DBG101]] 1871 // CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG102:![0-9]+]] 1872 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG103:![0-9]+]] 1873 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[C]], align 8, !dbg [[DBG102]] 1874 // CHECK5-NEXT: store ptr [[A2]], ptr [[TMP]], align 8, !dbg [[DBG104:![0-9]+]] 1875 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 8, !dbg [[DBG105:![0-9]+]] 1876 // CHECK5-NEXT: [[DOTB__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP0]], i64 4, ptr [[TMP2]]), !dbg [[DBG104]] 1877 // CHECK5-NEXT: store ptr [[C3]], ptr [[_TMP4]], align 8, !dbg [[DBG104]] 1878 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG106:![0-9]+]] 1879 // CHECK5-NEXT: store ptr [[THIS1]], ptr [[TMP3]], align 8, !dbg [[DBG106]] 1880 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG106]] 1881 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG107:![0-9]+]] 1882 // CHECK5-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8, !dbg [[DBG106]] 1883 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 2, !dbg [[DBG106]] 1884 // CHECK5-NEXT: store ptr [[DOTB__VOID_ADDR]], ptr [[TMP6]], align 8, !dbg [[DBG106]] 1885 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 3, !dbg [[DBG106]] 1886 // CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8, !dbg [[DBG107]] 1887 // CHECK5-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8, !dbg [[DBG106]] 1888 // CHECK5-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) 1889 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG106]] 1890 // CHECK5: invoke.cont: 1891 // CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 8, !dbg [[DBG105]] 1892 // CHECK5-NEXT: call void @__kmpc_free(i32 [[TMP0]], ptr [[DOTB__VOID_ADDR]], ptr [[TMP9]]), !dbg [[DBG106]] 1893 // CHECK5-NEXT: ret void, !dbg [[DBG108:![0-9]+]] 1894 // CHECK5: terminate.lpad: 1895 // CHECK5-NEXT: [[TMP10:%.*]] = landingpad { ptr, i32 } 1896 // CHECK5-NEXT: catch ptr null, !dbg [[DBG106]] 1897 // CHECK5-NEXT: [[TMP11:%.*]] = extractvalue { ptr, i32 } [[TMP10]], 0, !dbg [[DBG106]] 1898 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP11]]) #[[ATTR10]], !dbg [[DBG106]] 1899 // CHECK5-NEXT: unreachable, !dbg [[DBG106]] 1900 // 1901 // 1902 // CHECK5-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv 1903 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2]] align 2 !dbg [[DBG109:![0-9]+]] { 1904 // CHECK5-NEXT: entry: 1905 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1906 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB22:[0-9]+]]), !dbg [[DBG110:![0-9]+]] 1907 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1908 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1909 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1:%.*]], ptr [[THIS1]], i32 0, i32 0 1910 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 1911 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG111:![0-9]+]] 1912 // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG111]] 1913 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG112:![0-9]+]] 1914 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1, !dbg [[DBG112]] 1915 // CHECK5-NEXT: store i32 [[INC]], ptr [[TMP4]], align 4, !dbg [[DBG112]] 1916 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG113:![0-9]+]] 1917 // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG113]] 1918 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG114:![0-9]+]] 1919 // CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1, !dbg [[DBG114]] 1920 // CHECK5-NEXT: store i32 [[DEC]], ptr [[TMP7]], align 4, !dbg [[DBG114]] 1921 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG115:![0-9]+]] 1922 // CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8, !dbg [[DBG115]] 1923 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4, !dbg [[DBG116:![0-9]+]] 1924 // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1, !dbg [[DBG116]] 1925 // CHECK5-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 4, !dbg [[DBG116]] 1926 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG117:![0-9]+]] 1927 // CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8, !dbg [[DBG117]] 1928 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG117]] 1929 // CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB22]], i32 [[TMP0]], i32 [[TMP14]]), !dbg [[DBG118:![0-9]+]] 1930 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG119:![0-9]+]] 1931 // CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !dbg [[DBG119]] 1932 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG120:![0-9]+]] 1933 // CHECK5-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8, !dbg [[DBG120]] 1934 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG121:![0-9]+]] 1935 // CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !dbg [[DBG121]] 1936 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB24:[0-9]+]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP2]], ptr [[TMP16]], ptr [[TMP18]], ptr [[TMP20]]), !dbg [[DBG118]] 1937 // CHECK5-NEXT: ret void, !dbg [[DBG122:![0-9]+]] 1938 // 1939 // 1940 // CHECK5-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined 1941 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR8]] !dbg [[DBG123:![0-9]+]] { 1942 // CHECK5-NEXT: entry: 1943 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1944 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1945 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1946 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 1947 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1948 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1949 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1950 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1951 // CHECK5-NEXT: [[E:%.*]] = alloca ptr, align 8 1952 // CHECK5-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 1953 // CHECK5-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8 1954 // CHECK5-NEXT: [[_TMP5:%.*]] = alloca ptr, align 8 1955 // CHECK5-NEXT: [[A6:%.*]] = alloca i32, align 4 1956 // CHECK5-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 1957 // CHECK5-NEXT: [[B8:%.*]] = alloca i32, align 4 1958 // CHECK5-NEXT: [[C9:%.*]] = alloca i32, align 4 1959 // CHECK5-NEXT: [[_TMP10:%.*]] = alloca ptr, align 8 1960 // CHECK5-NEXT: [[E11:%.*]] = alloca i32, align 4 1961 // CHECK5-NEXT: [[_TMP12:%.*]] = alloca ptr, align 8 1962 // CHECK5-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 1963 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1964 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1965 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1966 // CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 1967 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1968 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1969 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG124:![0-9]+]] 1970 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG124]] 1971 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG124]] 1972 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG124]] 1973 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG124]] 1974 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8, !dbg [[DBG124]] 1975 // CHECK5-NEXT: [[E2:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG125:![0-9]+]] 1976 // CHECK5-NEXT: store ptr [[E2]], ptr [[E]], align 8, !dbg [[DBG125]] 1977 // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG126:![0-9]+]] 1978 // CHECK5-NEXT: store ptr [[TMP4]], ptr [[_TMP3]], align 8, !dbg [[DBG127:![0-9]+]] 1979 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[E]], align 8, !dbg [[DBG128:![0-9]+]] 1980 // CHECK5-NEXT: store ptr [[TMP5]], ptr [[_TMP4]], align 8, !dbg [[DBG127]] 1981 // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG129:![0-9]+]] 1982 // CHECK5-NEXT: store ptr [[TMP6]], ptr [[_TMP5]], align 8, !dbg [[DBG127]] 1983 // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG130:![0-9]+]] 1984 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG130]] 1985 // CHECK5-NEXT: store i32 [[TMP8]], ptr [[A6]], align 4, !dbg [[DBG130]] 1986 // CHECK5-NEXT: store ptr [[A6]], ptr [[_TMP7]], align 8, !dbg [[DBG127]] 1987 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG131:![0-9]+]] 1988 // CHECK5-NEXT: store i32 [[TMP9]], ptr [[B8]], align 4, !dbg [[DBG131]] 1989 // CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 8, !dbg [[DBG132:![0-9]+]] 1990 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4, !dbg [[DBG132]] 1991 // CHECK5-NEXT: store i32 [[TMP11]], ptr [[C9]], align 4, !dbg [[DBG132]] 1992 // CHECK5-NEXT: store ptr [[C9]], ptr [[_TMP10]], align 8, !dbg [[DBG127]] 1993 // CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8, !dbg [[DBG125]] 1994 // CHECK5-NEXT: store i32 0, ptr [[E11]], align 4, !dbg [[DBG125]] 1995 // CHECK5-NEXT: store ptr [[E11]], ptr [[_TMP12]], align 8, !dbg [[DBG127]] 1996 // CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP7]], align 8, !dbg [[DBG126]] 1997 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG133:![0-9]+]] 1998 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1, !dbg [[DBG133]] 1999 // CHECK5-NEXT: store i32 [[INC]], ptr [[TMP13]], align 4, !dbg [[DBG133]] 2000 // CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP12]], align 8, !dbg [[DBG128]] 2001 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4, !dbg [[DBG134:![0-9]+]] 2002 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1, !dbg [[DBG134]] 2003 // CHECK5-NEXT: store i32 [[ADD]], ptr [[TMP15]], align 4, !dbg [[DBG134]] 2004 // CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP10]], align 8, !dbg [[DBG129]] 2005 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4, !dbg [[DBG135:![0-9]+]] 2006 // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP18]], 1, !dbg [[DBG135]] 2007 // CHECK5-NEXT: store i32 [[DIV]], ptr [[TMP17]], align 4, !dbg [[DBG135]] 2008 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0, !dbg [[DBG133]] 2009 // CHECK5-NEXT: store ptr [[E11]], ptr [[TMP19]], align 8, !dbg [[DBG133]] 2010 // CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG133]] 2011 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4, !dbg [[DBG133]] 2012 // CHECK5-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB18:[0-9]+]], i32 [[TMP21]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var), !dbg [[DBG133]] 2013 // CHECK5-NEXT: switch i32 [[TMP22]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 2014 // CHECK5-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 2015 // CHECK5-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 2016 // CHECK5-NEXT: ], !dbg [[DBG133]] 2017 // CHECK5: .omp.reduction.case1: 2018 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG125]] 2019 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[E11]], align 4, !dbg [[DBG125]] 2020 // CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP23]], [[TMP24]], !dbg [[DBG136:![0-9]+]] 2021 // CHECK5-NEXT: store i32 [[ADD13]], ptr [[TMP12]], align 4, !dbg [[DBG136]] 2022 // CHECK5-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB18]], i32 [[TMP21]], ptr @.gomp_critical_user_.reduction.var), !dbg [[DBG133]] 2023 // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]], !dbg [[DBG133]] 2024 // CHECK5: .omp.reduction.case2: 2025 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[E11]], align 4, !dbg [[DBG125]] 2026 // CHECK5-NEXT: [[TMP26:%.*]] = atomicrmw add ptr [[TMP12]], i32 [[TMP25]] monotonic, align 4, !dbg [[DBG133]] 2027 // CHECK5-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB18]], i32 [[TMP21]], ptr @.gomp_critical_user_.reduction.var), !dbg [[DBG133]] 2028 // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]], !dbg [[DBG133]] 2029 // CHECK5: .omp.reduction.default: 2030 // CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB20:[0-9]+]], i32 [[TMP21]]), !dbg [[DBG137:![0-9]+]] 2031 // CHECK5-NEXT: ret void, !dbg [[DBG137]] 2032 // 2033 // 2034 // CHECK5-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined.omp.reduction.reduction_func 2035 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR9:[0-9]+]] !dbg [[DBG138:![0-9]+]] { 2036 // CHECK5-NEXT: entry: 2037 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2038 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 2039 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2040 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 2041 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG139:![0-9]+]] 2042 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG139]] 2043 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG139]] 2044 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG139]] 2045 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG139]] 2046 // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG139]] 2047 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG140:![0-9]+]] 2048 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG140]] 2049 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]], !dbg [[DBG141:![0-9]+]] 2050 // CHECK5-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4, !dbg [[DBG141]] 2051 // CHECK5-NEXT: ret void, !dbg [[DBG140]] 2052 // 2053 // 2054 // CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassC2ERKS_ 2055 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG142:![0-9]+]] { 2056 // CHECK5-NEXT: entry: 2057 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2058 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 2059 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2060 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 2061 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2062 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG143:![0-9]+]] 2063 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG144:![0-9]+]] 2064 // CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG145:![0-9]+]] 2065 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A2]], align 4, !dbg [[DBG145]] 2066 // CHECK5-NEXT: store i32 [[TMP1]], ptr [[A]], align 4, !dbg [[DBG143]] 2067 // CHECK5-NEXT: ret void, !dbg [[DBG146:![0-9]+]] 2068 // 2069 // 2070 // CHECK5-LABEL: define {{[^@]+}}@_Z15parallel_singlev 2071 // CHECK5-SAME: () #[[ATTR2]] !dbg [[DBG147:![0-9]+]] { 2072 // CHECK5-NEXT: entry: 2073 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB28:[0-9]+]], i32 0, ptr @_Z15parallel_singlev.omp_outlined), !dbg [[DBG148:![0-9]+]] 2074 // CHECK5-NEXT: ret void, !dbg [[DBG149:![0-9]+]] 2075 // 2076 // 2077 // CHECK5-LABEL: define {{[^@]+}}@_Z15parallel_singlev.omp_outlined 2078 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR8]] personality ptr @__gxx_personality_v0 !dbg [[DBG150:![0-9]+]] { 2079 // CHECK5-NEXT: entry: 2080 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2081 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2082 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2083 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2084 // CHECK5-NEXT: invoke void @_Z3foov() 2085 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG151:![0-9]+]] 2086 // CHECK5: invoke.cont: 2087 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG152:![0-9]+]] 2088 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG152]] 2089 // CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB26:[0-9]+]], i32 [[TMP1]]), !dbg [[DBG152]] 2090 // CHECK5-NEXT: ret void, !dbg [[DBG152]] 2091 // CHECK5: terminate.lpad: 2092 // CHECK5-NEXT: [[TMP2:%.*]] = landingpad { ptr, i32 } 2093 // CHECK5-NEXT: catch ptr null, !dbg [[DBG151]] 2094 // CHECK5-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0, !dbg [[DBG151]] 2095 // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP3]]) #[[ATTR10]], !dbg [[DBG151]] 2096 // CHECK5-NEXT: unreachable, !dbg [[DBG151]] 2097 // 2098 // 2099 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_scope_codegen.cpp 2100 // CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG153:![0-9]+]] { 2101 // CHECK5-NEXT: entry: 2102 // CHECK5-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG154:![0-9]+]] 2103 // CHECK5-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG154]] 2104 // CHECK5-NEXT: ret void 2105 // 2106 // 2107 // CHECK6-LABEL: define {{[^@]+}}@_Z10array_funciPiP2St 2108 // CHECK6-SAME: (i32 noundef [[N:%.*]], ptr noundef [[A:%.*]], ptr noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] { 2109 // CHECK6-NEXT: entry: 2110 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2111 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 2112 // CHECK6-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 2113 // CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 2114 // CHECK6-NEXT: [[C:%.*]] = alloca i32, align 4 2115 // CHECK6-NEXT: [[B1:%.*]] = alloca i32, align 4 2116 // CHECK6-NEXT: [[A2:%.*]] = alloca ptr, align 8 2117 // CHECK6-NEXT: [[S3:%.*]] = alloca ptr, align 8 2118 // CHECK6-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 2119 // CHECK6-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4 2120 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 2121 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) 2122 // CHECK6-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2123 // CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 2124 // CHECK6-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 2125 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 2126 // CHECK6-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 2127 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, ptr [[B]], align 4 2128 // CHECK6-NEXT: store i32 [[TMP3]], ptr [[B1]], align 4 2129 // CHECK6-NEXT: [[TMP4:%.*]] = load ptr, ptr @omp_high_bw_mem_alloc, align 8 2130 // CHECK6-NEXT: [[DOTC__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP0]], i64 4, ptr [[TMP4]]) 2131 // CHECK6-NEXT: store i32 1, ptr [[DOTC__VOID_ADDR]], align 4 2132 // CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 2133 // CHECK6-NEXT: store ptr [[DOTC__VOID_ADDR]], ptr [[TMP5]], align 8 2134 // CHECK6-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB2:[0-9]+]], i32 [[TMP0]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_Z10array_funciPiP2St.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) 2135 // CHECK6-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 2136 // CHECK6-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 2137 // CHECK6-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 2138 // CHECK6-NEXT: ] 2139 // CHECK6: .omp.reduction.case1: 2140 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, ptr [[C]], align 4 2141 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTC__VOID_ADDR]], align 4 2142 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], [[TMP8]] 2143 // CHECK6-NEXT: store i32 [[MUL]], ptr [[C]], align 4 2144 // CHECK6-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP0]], ptr @.gomp_critical_user_.reduction.var) 2145 // CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 2146 // CHECK6: .omp.reduction.case2: 2147 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTC__VOID_ADDR]], align 4 2148 // CHECK6-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i32, ptr [[C]] monotonic, align 4 2149 // CHECK6-NEXT: br label [[ATOMIC_CONT:%.*]] 2150 // CHECK6: atomic_cont: 2151 // CHECK6-NEXT: [[TMP10:%.*]] = phi i32 [ [[ATOMIC_LOAD]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[TMP15:%.*]], [[ATOMIC_CONT]] ] 2152 // CHECK6-NEXT: store i32 [[TMP10]], ptr [[TMP]], align 4 2153 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP]], align 4 2154 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTC__VOID_ADDR]], align 4 2155 // CHECK6-NEXT: [[MUL4:%.*]] = mul nsw i32 [[TMP11]], [[TMP12]] 2156 // CHECK6-NEXT: store i32 [[MUL4]], ptr [[ATOMIC_TEMP]], align 4 2157 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 4 2158 // CHECK6-NEXT: [[TMP14:%.*]] = cmpxchg ptr [[C]], i32 [[TMP10]], i32 [[TMP13]] monotonic monotonic, align 4 2159 // CHECK6-NEXT: [[TMP15]] = extractvalue { i32, i1 } [[TMP14]], 0 2160 // CHECK6-NEXT: [[TMP16:%.*]] = extractvalue { i32, i1 } [[TMP14]], 1 2161 // CHECK6-NEXT: br i1 [[TMP16]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] 2162 // CHECK6: atomic_exit: 2163 // CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 2164 // CHECK6: .omp.reduction.default: 2165 // CHECK6-NEXT: [[TMP17:%.*]] = load ptr, ptr @omp_high_bw_mem_alloc, align 8 2166 // CHECK6-NEXT: call void @__kmpc_free(i32 [[TMP0]], ptr [[DOTC__VOID_ADDR]], ptr [[TMP17]]) 2167 // CHECK6-NEXT: ret void 2168 // 2169 // 2170 // CHECK6-LABEL: define {{[^@]+}}@_Z10array_funciPiP2St.omp.reduction.reduction_func 2171 // CHECK6-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { 2172 // CHECK6-NEXT: entry: 2173 // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2174 // CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 2175 // CHECK6-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2176 // CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 2177 // CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 2178 // CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 2179 // CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 2180 // CHECK6-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 2181 // CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 2182 // CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 2183 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 2184 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 2185 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], [[TMP9]] 2186 // CHECK6-NEXT: store i32 [[MUL]], ptr [[TMP7]], align 4 2187 // CHECK6-NEXT: ret void 2188 // 2189 // 2190 // CHECK6-LABEL: define {{[^@]+}}@main 2191 // CHECK6-SAME: () #[[ATTR4:[0-9]+]] { 2192 // CHECK6-NEXT: entry: 2193 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2194 // CHECK6-NEXT: [[N:%.*]] = alloca i32, align 4 2195 // CHECK6-NEXT: [[A:%.*]] = alloca [10 x i32], align 16 2196 // CHECK6-NEXT: [[S:%.*]] = alloca [2 x %struct.St], align 16 2197 // CHECK6-NEXT: store i32 0, ptr [[RETVAL]], align 4 2198 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.St], ptr [[S]], i32 0, i32 0 2199 // CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[ARRAY_BEGIN]], i64 2 2200 // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2201 // CHECK6: arrayctor.loop: 2202 // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2203 // CHECK6-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYCTOR_CUR]]) 2204 // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYCTOR_CUR]], i64 1 2205 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2206 // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2207 // CHECK6: arrayctor.cont: 2208 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 2209 // CHECK6-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 0 2210 // CHECK6-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [2 x %struct.St], ptr [[S]], i64 0, i64 0 2211 // CHECK6-NEXT: call void @_Z10array_funciPiP2St(i32 noundef [[TMP0]], ptr noundef [[ARRAYDECAY]], ptr noundef [[ARRAYDECAY1]]) 2212 // CHECK6-NEXT: store i32 0, ptr [[RETVAL]], align 4 2213 // CHECK6-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.St], ptr [[S]], i32 0, i32 0 2214 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAY_BEGIN2]], i64 2 2215 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2216 // CHECK6: arraydestroy.body: 2217 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2218 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2219 // CHECK6-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1:[0-9]+]] 2220 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 2221 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 2222 // CHECK6: arraydestroy.done3: 2223 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4 2224 // CHECK6-NEXT: ret i32 [[TMP2]] 2225 // 2226 // 2227 // CHECK6-LABEL: define {{[^@]+}}@_ZN2StC1Ev 2228 // CHECK6-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { 2229 // CHECK6-NEXT: entry: 2230 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2231 // CHECK6-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2232 // CHECK6-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2233 // CHECK6-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 2234 // CHECK6-NEXT: ret void 2235 // 2236 // 2237 // CHECK6-LABEL: define {{[^@]+}}@_ZN2StD1Ev 2238 // CHECK6-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { 2239 // CHECK6-NEXT: entry: 2240 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2241 // CHECK6-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2242 // CHECK6-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2243 // CHECK6-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR1]] 2244 // CHECK6-NEXT: ret void 2245 // 2246 // 2247 // CHECK6-LABEL: define {{[^@]+}}@_ZN2StC2Ev 2248 // CHECK6-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { 2249 // CHECK6-NEXT: entry: 2250 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2251 // CHECK6-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2252 // CHECK6-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2253 // CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 2254 // CHECK6-NEXT: store i32 0, ptr [[A]], align 4 2255 // CHECK6-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 2256 // CHECK6-NEXT: store i32 0, ptr [[B]], align 4 2257 // CHECK6-NEXT: ret void 2258 // 2259 // 2260 // CHECK6-LABEL: define {{[^@]+}}@_ZN2StD2Ev 2261 // CHECK6-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { 2262 // CHECK6-NEXT: entry: 2263 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2264 // CHECK6-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2265 // CHECK6-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2266 // CHECK6-NEXT: ret void 2267 // 2268