1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s 4 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 7 8 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 9 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s 10 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 12 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // expected-no-diagnostics 14 #ifndef HEADER 15 #define HEADER 16 17 enum omp_allocator_handle_t { 18 omp_null_allocator = 0, 19 omp_default_mem_alloc = 1, 20 omp_large_cap_mem_alloc = 2, 21 omp_const_mem_alloc = 3, 22 omp_high_bw_mem_alloc = 4, 23 omp_low_lat_mem_alloc = 5, 24 omp_cgroup_mem_alloc = 6, 25 omp_pteam_mem_alloc = 7, 26 omp_thread_mem_alloc = 8, 27 KMP_ALLOCATOR_MAX_HANDLE = __UINTPTR_MAX__ 28 }; 29 30 template <class T> 31 struct S { 32 T f; 33 S(T a) : f(a) {} 34 S() : f() {} 35 operator T() { return T(); } 36 ~S() {} 37 }; 38 39 volatile int g __attribute__((aligned(128))) = 1212; 40 41 struct SS { 42 int a; 43 int b : 4; 44 int &c; 45 SS(int &d) : a(0), b(0), c(d) { 46 #pragma omp parallel private(a, b, c) 47 #ifdef LAMBDA 48 [&]() { 49 ++this->a, --b, (this)->c /= 1; 50 #pragma omp parallel private(a, b, c) 51 ++(this)->a, --b, this->c /= 1; 52 }(); 53 #elif defined(BLOCKS) 54 ^{ 55 ++a; 56 --this->b; 57 (this)->c /= 1; 58 #pragma omp parallel private(a, b, c) 59 ++(this)->a, --b, this->c /= 1; 60 }(); 61 #else 62 ++this->a, --b, c /= 1; 63 #endif 64 } 65 }; 66 67 template<typename T> 68 struct SST { 69 T a; 70 SST() : a(T()) { 71 #pragma omp parallel private(a) allocate(omp_large_cap_mem_alloc:a) 72 #ifdef LAMBDA 73 [&]() { 74 [&]() { 75 ++this->a; 76 #pragma omp parallel private(a) 77 ++(this)->a; 78 }(); 79 }(); 80 #elif defined(BLOCKS) 81 ^{ 82 ^{ 83 ++a; 84 #pragma omp parallel private(a) 85 ++(this)->a; 86 }(); 87 }(); 88 #else 89 ++(this)->a; 90 #endif 91 } 92 }; 93 94 template <typename T> 95 T tmain() { 96 S<T> test; 97 SST<T> sst; 98 T t_var __attribute__((aligned(128))) = T(); 99 T vec[] __attribute__((aligned(128))) = {1, 2}; 100 S<T> s_arr[] __attribute__((aligned(128))) = {1, 2}; 101 S<T> var __attribute__((aligned(128))) (3); 102 #pragma omp parallel private(t_var, vec, s_arr, var) 103 { 104 vec[0] = t_var; 105 s_arr[0] = var; 106 } 107 return T(); 108 } 109 110 int main() { 111 static int sivar; 112 SS ss(sivar); 113 #ifdef LAMBDA 114 [&]() { 115 #pragma omp parallel private(g, sivar) 116 { 117 118 119 120 g = 1; 121 sivar = 2; 122 123 124 [&]() { 125 g = 2; 126 sivar = 4; 127 }(); 128 } 129 }(); 130 return 0; 131 #elif defined(BLOCKS) 132 ^{ 133 #pragma omp parallel private(g, sivar) 134 { 135 g = 1; 136 sivar = 20; 137 ^{ 138 g = 2; 139 sivar = 40; 140 }(); 141 } 142 }(); 143 return 0; 144 145 146 #else 147 S<float> test; 148 int t_var = 0; 149 int vec[] = {1, 2}; 150 S<float> s_arr[] = {1, 2}; 151 S<float> var(3); 152 #pragma omp parallel private(t_var, vec, s_arr, var, sivar) 153 { 154 vec[0] = t_var; 155 s_arr[0] = var; 156 sivar = 3; 157 } 158 return tmain<int>(); 159 #endif 160 } 161 162 163 164 165 166 167 168 #endif 169 170 // CHECK1-LABEL: define {{[^@]+}}@main 171 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 172 // CHECK1-NEXT: entry: 173 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 174 // CHECK1-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 175 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 176 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 177 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 178 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 179 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 180 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 181 // CHECK1-NEXT: call void @_ZN2SSC1ERi(ptr noundef nonnull align 8 dereferenceable(16) [[SS]], ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) 182 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 183 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 184 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false) 185 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00) 186 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1 187 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) 188 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], float noundef 3.000000e+00) 189 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @main.omp_outlined) 190 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 191 // CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 192 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] 193 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 194 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 195 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 196 // CHECK1: arraydestroy.body: 197 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 198 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 199 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 200 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 201 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 202 // CHECK1: arraydestroy.done1: 203 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 204 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 205 // CHECK1-NEXT: ret i32 [[TMP1]] 206 // 207 // 208 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 209 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 210 // CHECK1-NEXT: entry: 211 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 212 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 213 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 214 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 215 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 216 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 217 // CHECK1-NEXT: call void @_ZN2SSC2ERi(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]]) 218 // CHECK1-NEXT: ret void 219 // 220 // 221 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 222 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 223 // CHECK1-NEXT: entry: 224 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 225 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 226 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 227 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 228 // CHECK1-NEXT: ret void 229 // 230 // 231 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 232 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 233 // CHECK1-NEXT: entry: 234 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 235 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 236 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 237 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 238 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 239 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 240 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 241 // CHECK1-NEXT: ret void 242 // 243 // 244 // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined 245 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 246 // CHECK1-NEXT: entry: 247 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 248 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 249 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 250 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 251 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 252 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 253 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 254 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 255 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 256 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 257 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 258 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 259 // CHECK1: arrayctor.loop: 260 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 261 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 262 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 263 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 264 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 265 // CHECK1: arrayctor.cont: 266 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 267 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 268 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 269 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[ARRAYIDX]], align 4 270 // CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 271 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i64 4, i1 false) 272 // CHECK1-NEXT: store i32 3, ptr [[SIVAR]], align 4 273 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 274 // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 275 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2 276 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 277 // CHECK1: arraydestroy.body: 278 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 279 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 280 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 281 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 282 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 283 // CHECK1: arraydestroy.done3: 284 // CHECK1-NEXT: ret void 285 // 286 // 287 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 288 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 289 // CHECK1-NEXT: entry: 290 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 291 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 292 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 293 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 294 // CHECK1-NEXT: ret void 295 // 296 // 297 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 298 // CHECK1-SAME: () #[[ATTR1]] comdat { 299 // CHECK1-NEXT: entry: 300 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 301 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 302 // CHECK1-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 303 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 304 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 305 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 306 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 307 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 308 // CHECK1-NEXT: call void @_ZN3SSTIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[SST]]) 309 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 128 310 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VEC]], ptr align 128 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 311 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 312 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 313 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 314 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) 315 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @_Z5tmainIiET_v.omp_outlined) 316 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 317 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 318 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 319 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 320 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 321 // CHECK1: arraydestroy.body: 322 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 323 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 324 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 325 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 326 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 327 // CHECK1: arraydestroy.done1: 328 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 329 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 330 // CHECK1-NEXT: ret i32 [[TMP1]] 331 // 332 // 333 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 334 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 335 // CHECK1-NEXT: entry: 336 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 337 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 338 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 339 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 340 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 341 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 342 // CHECK1-NEXT: store i32 0, ptr [[A]], align 8 343 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 344 // CHECK1-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4 345 // CHECK1-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 346 // CHECK1-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 347 // CHECK1-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 348 // CHECK1-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 349 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 350 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 351 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]]) 352 // CHECK1-NEXT: ret void 353 // 354 // 355 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined 356 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR3]] { 357 // CHECK1-NEXT: entry: 358 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 359 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 360 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 361 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 362 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 363 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 364 // CHECK1-NEXT: [[C:%.*]] = alloca i32, align 4 365 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 366 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 367 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 368 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 369 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 370 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP]], align 8 371 // CHECK1-NEXT: store ptr [[C]], ptr [[_TMP1]], align 8 372 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 373 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 374 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 375 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4 376 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[B]], align 4 377 // CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 378 // CHECK1-NEXT: store i32 [[DEC]], ptr [[B]], align 4 379 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8 380 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 381 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 382 // CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP4]], align 4 383 // CHECK1-NEXT: ret void 384 // 385 // 386 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 387 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 388 // CHECK1-NEXT: entry: 389 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 390 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 391 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 392 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 393 // CHECK1-NEXT: store float 0.000000e+00, ptr [[F]], align 4 394 // CHECK1-NEXT: ret void 395 // 396 // 397 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 398 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 399 // CHECK1-NEXT: entry: 400 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 401 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 402 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 403 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 404 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 405 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 406 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 407 // CHECK1-NEXT: store float [[TMP0]], ptr [[F]], align 4 408 // CHECK1-NEXT: ret void 409 // 410 // 411 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 412 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 413 // CHECK1-NEXT: entry: 414 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 415 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 416 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 417 // CHECK1-NEXT: ret void 418 // 419 // 420 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 421 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 422 // CHECK1-NEXT: entry: 423 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 424 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 425 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 426 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 427 // CHECK1-NEXT: ret void 428 // 429 // 430 // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev 431 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 432 // CHECK1-NEXT: entry: 433 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 434 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 435 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 436 // CHECK1-NEXT: call void @_ZN3SSTIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 437 // CHECK1-NEXT: ret void 438 // 439 // 440 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 441 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 442 // CHECK1-NEXT: entry: 443 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 444 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 445 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 446 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 447 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 448 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 449 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 450 // CHECK1-NEXT: ret void 451 // 452 // 453 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined 454 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 455 // CHECK1-NEXT: entry: 456 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 457 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 458 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 459 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 460 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 461 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 462 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 463 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 464 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 465 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 466 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 467 // CHECK1: arrayctor.loop: 468 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 469 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 470 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 471 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 472 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 473 // CHECK1: arrayctor.cont: 474 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 475 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128 476 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 477 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[ARRAYIDX]], align 128 478 // CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 479 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[ARRAYIDX1]], ptr align 128 [[VAR]], i64 4, i1 false) 480 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 481 // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 482 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN2]], i64 2 483 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 484 // CHECK1: arraydestroy.body: 485 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 486 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 487 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 488 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 489 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 490 // CHECK1: arraydestroy.done3: 491 // CHECK1-NEXT: ret void 492 // 493 // 494 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 495 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 496 // CHECK1-NEXT: entry: 497 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 498 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 499 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 500 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 501 // CHECK1-NEXT: ret void 502 // 503 // 504 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 505 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 506 // CHECK1-NEXT: entry: 507 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 508 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 509 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 510 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 511 // CHECK1-NEXT: store i32 0, ptr [[F]], align 4 512 // CHECK1-NEXT: ret void 513 // 514 // 515 // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev 516 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 517 // CHECK1-NEXT: entry: 518 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 519 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 520 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 521 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[THIS1]], i32 0, i32 0 522 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 523 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_ZN3SSTIiEC2Ev.omp_outlined, ptr [[THIS1]]) 524 // CHECK1-NEXT: ret void 525 // 526 // 527 // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev.omp_outlined 528 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR3]] { 529 // CHECK1-NEXT: entry: 530 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 531 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 532 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 533 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 534 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 535 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 536 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 537 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 538 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 539 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 540 // CHECK1-NEXT: [[DOTA__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP2]], i64 4, ptr inttoptr (i64 2 to ptr)) 541 // CHECK1-NEXT: store ptr [[DOTA__VOID_ADDR]], ptr [[TMP]], align 8 542 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 543 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 544 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 545 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4 546 // CHECK1-NEXT: call void @__kmpc_free(i32 [[TMP2]], ptr [[DOTA__VOID_ADDR]], ptr inttoptr (i64 2 to ptr)) 547 // CHECK1-NEXT: ret void 548 // 549 // 550 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 551 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 552 // CHECK1-NEXT: entry: 553 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 554 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 555 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 556 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 557 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 558 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 559 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 560 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 561 // CHECK1-NEXT: ret void 562 // 563 // 564 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 565 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 566 // CHECK1-NEXT: entry: 567 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 568 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 569 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 570 // CHECK1-NEXT: ret void 571 // 572 // 573 // CHECK3-LABEL: define {{[^@]+}}@main 574 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 575 // CHECK3-NEXT: entry: 576 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 577 // CHECK3-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 578 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 579 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 580 // CHECK3-NEXT: call void @_ZN2SSC1ERi(ptr noundef nonnull align 8 dereferenceable(16) [[SS]], ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) 581 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 582 // CHECK3-NEXT: ret i32 0 583 // 584 // 585 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 586 // CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 587 // CHECK3-NEXT: entry: 588 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 589 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 590 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 591 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 592 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 593 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 594 // CHECK3-NEXT: call void @_ZN2SSC2ERi(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]]) 595 // CHECK3-NEXT: ret void 596 // 597 // 598 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 599 // CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 600 // CHECK3-NEXT: entry: 601 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 602 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 603 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 604 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 605 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 606 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 607 // CHECK3-NEXT: store i32 0, ptr [[A]], align 8 608 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 609 // CHECK3-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4 610 // CHECK3-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 611 // CHECK3-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 612 // CHECK3-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 613 // CHECK3-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 614 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 615 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 616 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]]) 617 // CHECK3-NEXT: ret void 618 // 619 // 620 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined 621 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { 622 // CHECK3-NEXT: entry: 623 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 624 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 625 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 626 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 627 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8 628 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 629 // CHECK3-NEXT: [[C:%.*]] = alloca i32, align 4 630 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 631 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 632 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 633 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 634 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 635 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 636 // CHECK3-NEXT: store ptr [[A]], ptr [[TMP]], align 8 637 // CHECK3-NEXT: store ptr [[C]], ptr [[_TMP1]], align 8 638 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 639 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 8 640 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 641 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 642 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 8 643 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 644 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP4]], align 8 645 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3 646 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8 647 // CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP5]], align 8 648 // CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) 649 // CHECK3-NEXT: ret void 650 // 651 // 652 // CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv 653 // CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR1]] align 2 { 654 // CHECK3-NEXT: entry: 655 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 656 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 657 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 658 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0 659 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 660 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 661 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 662 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 663 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 664 // CHECK3-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4 665 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2 666 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 667 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 668 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 669 // CHECK3-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4 670 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3 671 // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 672 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 673 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 674 // CHECK3-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4 675 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP1]]) 676 // CHECK3-NEXT: ret void 677 // 678 // 679 // CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined 680 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR2]] { 681 // CHECK3-NEXT: entry: 682 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 683 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 684 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 685 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 686 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8 687 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 688 // CHECK3-NEXT: [[C:%.*]] = alloca i32, align 4 689 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 690 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 691 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 692 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 693 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 694 // CHECK3-NEXT: store ptr [[A]], ptr [[TMP]], align 8 695 // CHECK3-NEXT: store ptr [[C]], ptr [[_TMP1]], align 8 696 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 697 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 698 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 699 // CHECK3-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4 700 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[B]], align 4 701 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 702 // CHECK3-NEXT: store i32 [[DEC]], ptr [[B]], align 4 703 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8 704 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 705 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 706 // CHECK3-NEXT: store i32 [[DIV]], ptr [[TMP4]], align 4 707 // CHECK3-NEXT: ret void 708 // 709 // 710 // CHECK4-LABEL: define {{[^@]+}}@main 711 // CHECK4-SAME: () #[[ATTR1:[0-9]+]] { 712 // CHECK4-NEXT: entry: 713 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 714 // CHECK4-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 715 // CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4 716 // CHECK4-NEXT: call void @_ZN2SSC1ERi(ptr noundef nonnull align 8 dereferenceable(16) [[SS]], ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) 717 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds nuw ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8 718 // CHECK4-NEXT: call void [[TMP0]](ptr noundef @__block_literal_global) 719 // CHECK4-NEXT: ret i32 0 720 // 721 // 722 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 723 // CHECK4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { 724 // CHECK4-NEXT: entry: 725 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 726 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 727 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 728 // CHECK4-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 729 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 730 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 731 // CHECK4-NEXT: call void @_ZN2SSC2ERi(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]]) 732 // CHECK4-NEXT: ret void 733 // 734 // 735 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke 736 // CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR3:[0-9]+]] { 737 // CHECK4-NEXT: entry: 738 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 739 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 740 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 741 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 742 // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @__main_block_invoke.omp_outlined) 743 // CHECK4-NEXT: ret void 744 // 745 // 746 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined 747 // CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4:[0-9]+]] { 748 // CHECK4-NEXT: entry: 749 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 750 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 751 // CHECK4-NEXT: [[G:%.*]] = alloca i32, align 128 752 // CHECK4-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 753 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, align 128 754 // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 755 // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 756 // CHECK4-NEXT: store i32 1, ptr [[G]], align 128 757 // CHECK4-NEXT: store i32 20, ptr [[SIVAR]], align 4 758 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 0 759 // CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 128 760 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 1 761 // CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8 762 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 2 763 // CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4 764 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 3 765 // CHECK4-NEXT: store ptr @g_block_invoke, ptr [[BLOCK_INVOKE]], align 16 766 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 4 767 // CHECK4-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 8 768 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 7 769 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, ptr [[G]], align 128 770 // CHECK4-NEXT: store volatile i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 128 771 // CHECK4-NEXT: [[BLOCK_CAPTURED1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 5 772 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIVAR]], align 4 773 // CHECK4-NEXT: store i32 [[TMP1]], ptr [[BLOCK_CAPTURED1]], align 32 774 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 775 // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 776 // CHECK4-NEXT: call void [[TMP3]](ptr noundef [[BLOCK]]) 777 // CHECK4-NEXT: ret void 778 // 779 // 780 // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke 781 // CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR3]] { 782 // CHECK4-NEXT: entry: 783 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 784 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 785 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 786 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 787 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7 788 // CHECK4-NEXT: store i32 2, ptr [[BLOCK_CAPTURE_ADDR]], align 128 789 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 790 // CHECK4-NEXT: store i32 40, ptr [[BLOCK_CAPTURE_ADDR1]], align 32 791 // CHECK4-NEXT: ret void 792 // 793 // 794 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 795 // CHECK4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { 796 // CHECK4-NEXT: entry: 797 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 798 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 799 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 800 // CHECK4-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 801 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 802 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 803 // CHECK4-NEXT: store i32 0, ptr [[A]], align 8 804 // CHECK4-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 805 // CHECK4-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4 806 // CHECK4-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 807 // CHECK4-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 808 // CHECK4-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 809 // CHECK4-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 810 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 811 // CHECK4-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 812 // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]]) 813 // CHECK4-NEXT: ret void 814 // 815 // 816 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined 817 // CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR4]] { 818 // CHECK4-NEXT: entry: 819 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 820 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 821 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 822 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 823 // CHECK4-NEXT: [[TMP:%.*]] = alloca ptr, align 8 824 // CHECK4-NEXT: [[B:%.*]] = alloca i32, align 4 825 // CHECK4-NEXT: [[C:%.*]] = alloca i32, align 4 826 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 827 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, align 8 828 // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 829 // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 830 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 831 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 832 // CHECK4-NEXT: store ptr [[A]], ptr [[TMP]], align 8 833 // CHECK4-NEXT: store ptr [[C]], ptr [[_TMP1]], align 8 834 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 0 835 // CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8 836 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 1 837 // CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8 838 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 2 839 // CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4 840 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 3 841 // CHECK4-NEXT: store ptr @g_block_invoke_2, ptr [[BLOCK_INVOKE]], align 8 842 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 4 843 // CHECK4-NEXT: store ptr @__block_descriptor_tmp.2, ptr [[BLOCK_DESCRIPTOR]], align 8 844 // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5 845 // CHECK4-NEXT: store ptr [[TMP0]], ptr [[BLOCK_CAPTURED_THIS_ADDR]], align 8 846 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 6 847 // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 848 // CHECK4-NEXT: store ptr [[TMP1]], ptr [[BLOCK_CAPTURED]], align 8 849 // CHECK4-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 8 850 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[B]], align 4 851 // CHECK4-NEXT: store i32 [[TMP2]], ptr [[BLOCK_CAPTURED2]], align 8 852 // CHECK4-NEXT: [[BLOCK_CAPTURED3:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 7 853 // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8 854 // CHECK4-NEXT: store ptr [[TMP3]], ptr [[BLOCK_CAPTURED3]], align 8 855 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 856 // CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 857 // CHECK4-NEXT: call void [[TMP5]](ptr noundef [[BLOCK]]) 858 // CHECK4-NEXT: ret void 859 // 860 // 861 // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke_2 862 // CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR3]] { 863 // CHECK4-NEXT: entry: 864 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 865 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 866 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 867 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 868 // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 869 // CHECK4-NEXT: [[THIS:%.*]] = load ptr, ptr [[BLOCK_CAPTURED_THIS]], align 8 870 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 871 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR]], align 8 872 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 873 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 874 // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP0]], align 4 875 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 8 876 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[BLOCK_CAPTURE_ADDR1]], align 8 877 // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 878 // CHECK4-NEXT: store i32 [[DEC]], ptr [[BLOCK_CAPTURE_ADDR1]], align 8 879 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7 880 // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR2]], align 8 881 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 882 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 883 // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP3]], align 4 884 // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @g_block_invoke_2.omp_outlined, ptr [[THIS]]) 885 // CHECK4-NEXT: ret void 886 // 887 // 888 // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke_2.omp_outlined 889 // CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR4]] { 890 // CHECK4-NEXT: entry: 891 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 892 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 893 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 894 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 895 // CHECK4-NEXT: [[TMP:%.*]] = alloca ptr, align 8 896 // CHECK4-NEXT: [[B:%.*]] = alloca i32, align 4 897 // CHECK4-NEXT: [[C:%.*]] = alloca i32, align 4 898 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 899 // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 900 // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 901 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 902 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 903 // CHECK4-NEXT: store ptr [[A]], ptr [[TMP]], align 8 904 // CHECK4-NEXT: store ptr [[C]], ptr [[_TMP1]], align 8 905 // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 906 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 907 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 908 // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4 909 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr [[B]], align 4 910 // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 911 // CHECK4-NEXT: store i32 [[DEC]], ptr [[B]], align 4 912 // CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8 913 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 914 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 915 // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP4]], align 4 916 // CHECK4-NEXT: ret void 917 // 918