1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // REQUIRES: powerpc-registered-target 3 // REQUIRES: nvptx-registered-target 4 5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc 7 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple nvptx64-nvidia-cuda -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK2 8 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple nvptx64-nvidia-cuda -fopenmp-targets=nvptx64-nvidia-cuda %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -emit-pch -o %t 9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple nvptx64-nvidia-cuda -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -o - | FileCheck %s --check-prefix=CHECK3 10 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple nvptx64-nvidia-cuda -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -o - | FileCheck %s --check-prefix=CHECK3 11 12 // expected-no-diagnostics 13 #ifndef HEADER 14 #define HEADER 15 16 template <typename T> 17 int foo(const T &t) { 18 #pragma omp target parallel 19 t(); 20 return 0; 21 } 22 23 struct S { 24 int a = 15; 25 int foo() { 26 auto &&L = [&]() { return a; }; 27 #pragma omp target 28 L(); 29 #pragma omp target parallel 30 L(); 31 return a + ::foo(L); 32 } 33 } s; 34 35 int main(int argc, char **argv) { 36 int &b = argc; 37 int &&c = 1; 38 int *d = &argc; 39 int a; 40 auto &&L = [&]() { return argc + b + c + reinterpret_cast<long int>(d) + a; }; 41 #pragma omp target firstprivate(argc) map(to : a) 42 L(); 43 #pragma omp target parallel 44 L(); 45 return argc + s.foo(); 46 } 47 48 #endif // HEADER 49 // CHECK1-LABEL: define {{[^@]+}}@main 50 // CHECK1-SAME: (i32 noundef signext [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 51 // CHECK1-NEXT: entry: 52 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 53 // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 54 // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8 55 // CHECK1-NEXT: [[B:%.*]] = alloca ptr, align 8 56 // CHECK1-NEXT: [[C:%.*]] = alloca ptr, align 8 57 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca i32, align 4 58 // CHECK1-NEXT: [[D:%.*]] = alloca ptr, align 8 59 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 60 // CHECK1-NEXT: [[L:%.*]] = alloca ptr, align 8 61 // CHECK1-NEXT: [[REF_TMP1:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 62 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 63 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 64 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 65 // CHECK1-NEXT: [[ARGC_CASTED:%.*]] = alloca i64, align 8 66 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [11 x ptr], align 8 67 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [11 x ptr], align 8 68 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [11 x ptr], align 8 69 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 70 // CHECK1-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8 71 // CHECK1-NEXT: [[_TMP5:%.*]] = alloca ptr, align 8 72 // CHECK1-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 73 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [11 x ptr], align 8 74 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [11 x ptr], align 8 75 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [11 x ptr], align 8 76 // CHECK1-NEXT: [[KERNEL_ARGS10:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 77 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 78 // CHECK1-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 79 // CHECK1-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 80 // CHECK1-NEXT: store ptr [[ARGC_ADDR]], ptr [[B]], align 8 81 // CHECK1-NEXT: store i32 1, ptr [[REF_TMP]], align 4 82 // CHECK1-NEXT: store ptr [[REF_TMP]], ptr [[C]], align 8 83 // CHECK1-NEXT: store ptr [[ARGC_ADDR]], ptr [[D]], align 8 84 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP1]], i32 0, i32 0 85 // CHECK1-NEXT: store ptr [[ARGC_ADDR]], ptr [[TMP0]], align 8 86 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP1]], i32 0, i32 1 87 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B]], align 8 88 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8 89 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP1]], i32 0, i32 2 90 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C]], align 8 91 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP3]], align 8 92 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP1]], i32 0, i32 3 93 // CHECK1-NEXT: store ptr [[D]], ptr [[TMP5]], align 8 94 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP1]], i32 0, i32 4 95 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP6]], align 8 96 // CHECK1-NEXT: store ptr [[REF_TMP1]], ptr [[L]], align 8 97 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B]], align 8 98 // CHECK1-NEXT: store ptr [[TMP7]], ptr [[TMP]], align 8 99 // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[C]], align 8 100 // CHECK1-NEXT: store ptr [[TMP8]], ptr [[_TMP2]], align 8 101 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[L]], align 8 102 // CHECK1-NEXT: store ptr [[TMP9]], ptr [[_TMP3]], align 8 103 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 104 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARGC_CASTED]], align 4 105 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[ARGC_CASTED]], align 8 106 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP]], align 8 107 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8 108 // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[D]], align 8 109 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP3]], align 8 110 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 0 111 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 0 112 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 113 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 1 114 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 1 115 // CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP20]], align 8 116 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 2 117 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 2 118 // CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8 119 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 3 120 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 3 121 // CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[TMP26]], align 8 122 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 4 123 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 4 124 // CHECK1-NEXT: [[TMP30:%.*]] = load ptr, ptr [[TMP29]], align 8 125 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 126 // CHECK1-NEXT: store i64 [[TMP11]], ptr [[TMP31]], align 8 127 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 128 // CHECK1-NEXT: store i64 [[TMP11]], ptr [[TMP32]], align 8 129 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 130 // CHECK1-NEXT: store ptr null, ptr [[TMP33]], align 8 131 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 132 // CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP34]], align 8 133 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 134 // CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP35]], align 8 135 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 136 // CHECK1-NEXT: store ptr null, ptr [[TMP36]], align 8 137 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 138 // CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP37]], align 8 139 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 140 // CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP38]], align 8 141 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 142 // CHECK1-NEXT: store ptr null, ptr [[TMP39]], align 8 143 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 144 // CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP40]], align 8 145 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 146 // CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP41]], align 8 147 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 148 // CHECK1-NEXT: store ptr null, ptr [[TMP42]], align 8 149 // CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 150 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP43]], align 8 151 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 152 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP44]], align 8 153 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 154 // CHECK1-NEXT: store ptr null, ptr [[TMP45]], align 8 155 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 156 // CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP46]], align 8 157 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5 158 // CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP47]], align 8 159 // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 160 // CHECK1-NEXT: store ptr null, ptr [[TMP48]], align 8 161 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 162 // CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP49]], align 8 163 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 6 164 // CHECK1-NEXT: store ptr [[TMP18]], ptr [[TMP50]], align 8 165 // CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 166 // CHECK1-NEXT: store ptr null, ptr [[TMP51]], align 8 167 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 168 // CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP52]], align 8 169 // CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 7 170 // CHECK1-NEXT: store ptr [[TMP21]], ptr [[TMP53]], align 8 171 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 172 // CHECK1-NEXT: store ptr null, ptr [[TMP54]], align 8 173 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 174 // CHECK1-NEXT: store ptr [[TMP22]], ptr [[TMP55]], align 8 175 // CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 8 176 // CHECK1-NEXT: store ptr [[TMP24]], ptr [[TMP56]], align 8 177 // CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8 178 // CHECK1-NEXT: store ptr null, ptr [[TMP57]], align 8 179 // CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 180 // CHECK1-NEXT: store ptr [[TMP25]], ptr [[TMP58]], align 8 181 // CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 9 182 // CHECK1-NEXT: store ptr [[TMP27]], ptr [[TMP59]], align 8 183 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 9 184 // CHECK1-NEXT: store ptr null, ptr [[TMP60]], align 8 185 // CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 10 186 // CHECK1-NEXT: store ptr [[TMP28]], ptr [[TMP61]], align 8 187 // CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 10 188 // CHECK1-NEXT: store ptr [[TMP30]], ptr [[TMP62]], align 8 189 // CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 10 190 // CHECK1-NEXT: store ptr null, ptr [[TMP63]], align 8 191 // CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 192 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 193 // CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 194 // CHECK1-NEXT: store i32 3, ptr [[TMP66]], align 4 195 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 196 // CHECK1-NEXT: store i32 11, ptr [[TMP67]], align 4 197 // CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 198 // CHECK1-NEXT: store ptr [[TMP64]], ptr [[TMP68]], align 8 199 // CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 200 // CHECK1-NEXT: store ptr [[TMP65]], ptr [[TMP69]], align 8 201 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 202 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP70]], align 8 203 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 204 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP71]], align 8 205 // CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 206 // CHECK1-NEXT: store ptr null, ptr [[TMP72]], align 8 207 // CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 208 // CHECK1-NEXT: store ptr null, ptr [[TMP73]], align 8 209 // CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 210 // CHECK1-NEXT: store i64 0, ptr [[TMP74]], align 8 211 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 212 // CHECK1-NEXT: store i64 0, ptr [[TMP75]], align 8 213 // CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 214 // CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP76]], align 4 215 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 216 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP77]], align 4 217 // CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 218 // CHECK1-NEXT: store i32 0, ptr [[TMP78]], align 4 219 // CHECK1-NEXT: [[TMP79:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.region_id, ptr [[KERNEL_ARGS]]) 220 // CHECK1-NEXT: [[TMP80:%.*]] = icmp ne i32 [[TMP79]], 0 221 // CHECK1-NEXT: br i1 [[TMP80]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 222 // CHECK1: omp_offload.failed: 223 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41(i64 [[TMP11]], ptr [[TMP12]], ptr [[TMP13]], ptr [[TMP14]], ptr [[A]], ptr [[TMP15]]) #[[ATTR4:[0-9]+]] 224 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 225 // CHECK1: omp_offload.cont: 226 // CHECK1-NEXT: [[TMP81:%.*]] = load ptr, ptr [[B]], align 8 227 // CHECK1-NEXT: store ptr [[TMP81]], ptr [[_TMP4]], align 8 228 // CHECK1-NEXT: [[TMP82:%.*]] = load ptr, ptr [[C]], align 8 229 // CHECK1-NEXT: store ptr [[TMP82]], ptr [[_TMP5]], align 8 230 // CHECK1-NEXT: [[TMP83:%.*]] = load ptr, ptr [[L]], align 8 231 // CHECK1-NEXT: store ptr [[TMP83]], ptr [[_TMP6]], align 8 232 // CHECK1-NEXT: [[TMP84:%.*]] = load ptr, ptr [[_TMP4]], align 8 233 // CHECK1-NEXT: [[TMP85:%.*]] = load ptr, ptr [[_TMP5]], align 8 234 // CHECK1-NEXT: [[TMP86:%.*]] = load ptr, ptr [[D]], align 8 235 // CHECK1-NEXT: [[TMP87:%.*]] = load ptr, ptr [[_TMP6]], align 8 236 // CHECK1-NEXT: [[TMP88:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 0 237 // CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 0 238 // CHECK1-NEXT: [[TMP90:%.*]] = load ptr, ptr [[TMP89]], align 8 239 // CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 1 240 // CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 1 241 // CHECK1-NEXT: [[TMP93:%.*]] = load ptr, ptr [[TMP92]], align 8 242 // CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 2 243 // CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 2 244 // CHECK1-NEXT: [[TMP96:%.*]] = load ptr, ptr [[TMP95]], align 8 245 // CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 3 246 // CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 3 247 // CHECK1-NEXT: [[TMP99:%.*]] = load ptr, ptr [[TMP98]], align 8 248 // CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 4 249 // CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 4 250 // CHECK1-NEXT: [[TMP102:%.*]] = load ptr, ptr [[TMP101]], align 8 251 // CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 252 // CHECK1-NEXT: store ptr [[ARGC_ADDR]], ptr [[TMP103]], align 8 253 // CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 254 // CHECK1-NEXT: store ptr [[ARGC_ADDR]], ptr [[TMP104]], align 8 255 // CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 256 // CHECK1-NEXT: store ptr null, ptr [[TMP105]], align 8 257 // CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 258 // CHECK1-NEXT: store ptr [[TMP84]], ptr [[TMP106]], align 8 259 // CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 260 // CHECK1-NEXT: store ptr [[TMP84]], ptr [[TMP107]], align 8 261 // CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 262 // CHECK1-NEXT: store ptr null, ptr [[TMP108]], align 8 263 // CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 2 264 // CHECK1-NEXT: store ptr [[TMP85]], ptr [[TMP109]], align 8 265 // CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 2 266 // CHECK1-NEXT: store ptr [[TMP85]], ptr [[TMP110]], align 8 267 // CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 2 268 // CHECK1-NEXT: store ptr null, ptr [[TMP111]], align 8 269 // CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 3 270 // CHECK1-NEXT: store ptr [[TMP86]], ptr [[TMP112]], align 8 271 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 3 272 // CHECK1-NEXT: store ptr [[TMP86]], ptr [[TMP113]], align 8 273 // CHECK1-NEXT: [[TMP114:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 3 274 // CHECK1-NEXT: store ptr null, ptr [[TMP114]], align 8 275 // CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 4 276 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP115]], align 8 277 // CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 4 278 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP116]], align 8 279 // CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 4 280 // CHECK1-NEXT: store ptr null, ptr [[TMP117]], align 8 281 // CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 5 282 // CHECK1-NEXT: store ptr [[TMP87]], ptr [[TMP118]], align 8 283 // CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 5 284 // CHECK1-NEXT: store ptr [[TMP87]], ptr [[TMP119]], align 8 285 // CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 5 286 // CHECK1-NEXT: store ptr null, ptr [[TMP120]], align 8 287 // CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 6 288 // CHECK1-NEXT: store ptr [[TMP88]], ptr [[TMP121]], align 8 289 // CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 6 290 // CHECK1-NEXT: store ptr [[TMP90]], ptr [[TMP122]], align 8 291 // CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 6 292 // CHECK1-NEXT: store ptr null, ptr [[TMP123]], align 8 293 // CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 7 294 // CHECK1-NEXT: store ptr [[TMP91]], ptr [[TMP124]], align 8 295 // CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 7 296 // CHECK1-NEXT: store ptr [[TMP93]], ptr [[TMP125]], align 8 297 // CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 7 298 // CHECK1-NEXT: store ptr null, ptr [[TMP126]], align 8 299 // CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 8 300 // CHECK1-NEXT: store ptr [[TMP94]], ptr [[TMP127]], align 8 301 // CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 8 302 // CHECK1-NEXT: store ptr [[TMP96]], ptr [[TMP128]], align 8 303 // CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 8 304 // CHECK1-NEXT: store ptr null, ptr [[TMP129]], align 8 305 // CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 9 306 // CHECK1-NEXT: store ptr [[TMP97]], ptr [[TMP130]], align 8 307 // CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 9 308 // CHECK1-NEXT: store ptr [[TMP99]], ptr [[TMP131]], align 8 309 // CHECK1-NEXT: [[TMP132:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 9 310 // CHECK1-NEXT: store ptr null, ptr [[TMP132]], align 8 311 // CHECK1-NEXT: [[TMP133:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 10 312 // CHECK1-NEXT: store ptr [[TMP100]], ptr [[TMP133]], align 8 313 // CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 10 314 // CHECK1-NEXT: store ptr [[TMP102]], ptr [[TMP134]], align 8 315 // CHECK1-NEXT: [[TMP135:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 10 316 // CHECK1-NEXT: store ptr null, ptr [[TMP135]], align 8 317 // CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 318 // CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 319 // CHECK1-NEXT: [[TMP138:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 0 320 // CHECK1-NEXT: store i32 3, ptr [[TMP138]], align 4 321 // CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 1 322 // CHECK1-NEXT: store i32 11, ptr [[TMP139]], align 4 323 // CHECK1-NEXT: [[TMP140:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 2 324 // CHECK1-NEXT: store ptr [[TMP136]], ptr [[TMP140]], align 8 325 // CHECK1-NEXT: [[TMP141:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 3 326 // CHECK1-NEXT: store ptr [[TMP137]], ptr [[TMP141]], align 8 327 // CHECK1-NEXT: [[TMP142:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 4 328 // CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP142]], align 8 329 // CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 5 330 // CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP143]], align 8 331 // CHECK1-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 6 332 // CHECK1-NEXT: store ptr null, ptr [[TMP144]], align 8 333 // CHECK1-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 7 334 // CHECK1-NEXT: store ptr null, ptr [[TMP145]], align 8 335 // CHECK1-NEXT: [[TMP146:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 8 336 // CHECK1-NEXT: store i64 0, ptr [[TMP146]], align 8 337 // CHECK1-NEXT: [[TMP147:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 9 338 // CHECK1-NEXT: store i64 0, ptr [[TMP147]], align 8 339 // CHECK1-NEXT: [[TMP148:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 10 340 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP148]], align 4 341 // CHECK1-NEXT: [[TMP149:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 11 342 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP149]], align 4 343 // CHECK1-NEXT: [[TMP150:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 12 344 // CHECK1-NEXT: store i32 0, ptr [[TMP150]], align 4 345 // CHECK1-NEXT: [[TMP151:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43.region_id, ptr [[KERNEL_ARGS10]]) 346 // CHECK1-NEXT: [[TMP152:%.*]] = icmp ne i32 [[TMP151]], 0 347 // CHECK1-NEXT: br i1 [[TMP152]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] 348 // CHECK1: omp_offload.failed11: 349 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43(ptr [[ARGC_ADDR]], ptr [[TMP84]], ptr [[TMP85]], ptr [[TMP86]], ptr [[A]], ptr [[TMP87]]) #[[ATTR4]] 350 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT12]] 351 // CHECK1: omp_offload.cont12: 352 // CHECK1-NEXT: [[TMP153:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 353 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN1S3fooEv(ptr noundef nonnull align 4 dereferenceable(4) @s) 354 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP153]], [[CALL]] 355 // CHECK1-NEXT: ret i32 [[ADD]] 356 // 357 // 358 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41 359 // CHECK1-SAME: (i64 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR1:[0-9]+]] { 360 // CHECK1-NEXT: entry: 361 // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 362 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 363 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 364 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 365 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 366 // CHECK1-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8 367 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 368 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 369 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 370 // CHECK1-NEXT: [[L3:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 371 // CHECK1-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8 372 // CHECK1-NEXT: [[B5:%.*]] = alloca i32, align 4 373 // CHECK1-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 374 // CHECK1-NEXT: [[C7:%.*]] = alloca i32, align 4 375 // CHECK1-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 376 // CHECK1-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8 377 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 378 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 379 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 380 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 381 // CHECK1-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8 382 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 383 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 8 384 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8 385 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[L_ADDR]], align 8 386 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 387 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8 388 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP2]], align 8 389 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP2]], align 8 390 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L3]], ptr align 8 [[TMP4]], i64 40, i1 false) 391 // CHECK1-NEXT: store ptr [[L3]], ptr [[_TMP4]], align 8 392 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 393 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 394 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[B5]], align 4 395 // CHECK1-NEXT: store ptr [[B5]], ptr [[_TMP6]], align 8 396 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 8 397 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 398 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[C7]], align 4 399 // CHECK1-NEXT: store ptr [[C7]], ptr [[_TMP8]], align 8 400 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8 401 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(40) [[TMP9]]) 402 // CHECK1-NEXT: ret void 403 // 404 // 405 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43 406 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR1]] { 407 // CHECK1-NEXT: entry: 408 // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8 409 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 410 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 411 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 412 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 413 // CHECK1-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8 414 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 415 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 416 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 417 // CHECK1-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 418 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 419 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 420 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 421 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 422 // CHECK1-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8 423 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8 424 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 425 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 426 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8 427 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[L_ADDR]], align 8 428 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 429 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 8 430 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP2]], align 8 431 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 432 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8 433 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 434 // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 435 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43.omp_outlined, ptr [[TMP0]], ptr [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], ptr [[TMP3]], ptr [[TMP8]]) 436 // CHECK1-NEXT: ret void 437 // 438 // 439 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43.omp_outlined 440 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR1]] { 441 // CHECK1-NEXT: entry: 442 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 443 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 444 // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8 445 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 446 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 447 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 448 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 449 // CHECK1-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8 450 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 451 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 452 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 453 // CHECK1-NEXT: [[L3:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 454 // CHECK1-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8 455 // CHECK1-NEXT: [[ARGC5:%.*]] = alloca i32, align 4 456 // CHECK1-NEXT: [[B6:%.*]] = alloca i32, align 4 457 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 458 // CHECK1-NEXT: [[C8:%.*]] = alloca i32, align 4 459 // CHECK1-NEXT: [[_TMP9:%.*]] = alloca ptr, align 8 460 // CHECK1-NEXT: [[A10:%.*]] = alloca i32, align 4 461 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 462 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 463 // CHECK1-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 464 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 465 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 466 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 467 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 468 // CHECK1-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8 469 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8 470 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 471 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 472 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8 473 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[L_ADDR]], align 8 474 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 475 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 8 476 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP2]], align 8 477 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP2]], align 8 478 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L3]], ptr align 8 [[TMP5]], i64 40, i1 false) 479 // CHECK1-NEXT: store ptr [[L3]], ptr [[_TMP4]], align 8 480 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4 481 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[ARGC5]], align 4 482 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8 483 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 484 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[B6]], align 4 485 // CHECK1-NEXT: store ptr [[B6]], ptr [[_TMP7]], align 8 486 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8 487 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 488 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[C8]], align 4 489 // CHECK1-NEXT: store ptr [[C8]], ptr [[_TMP9]], align 8 490 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP3]], align 4 491 // CHECK1-NEXT: store i32 [[TMP11]], ptr [[A10]], align 4 492 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8 493 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(40) [[TMP12]]) 494 // CHECK1-NEXT: ret void 495 // 496 // 497 // CHECK1-LABEL: define {{[^@]+}}@_ZN1S3fooEv 498 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR3:[0-9]+]] comdat { 499 // CHECK1-NEXT: entry: 500 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 501 // CHECK1-NEXT: [[L:%.*]] = alloca ptr, align 8 502 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 503 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 504 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 505 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 506 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 507 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 508 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 509 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [3 x ptr], align 8 510 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [3 x ptr], align 8 511 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [3 x ptr], align 8 512 // CHECK1-NEXT: [[KERNEL_ARGS6:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 513 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 514 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 515 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 516 // CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP0]], align 8 517 // CHECK1-NEXT: store ptr [[REF_TMP]], ptr [[L]], align 8 518 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L]], align 8 519 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 520 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 521 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[TMP2]], i32 0, i32 0 522 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[TMP2]], i32 0, i32 0 523 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 524 // CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP5]], align 8 525 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 526 // CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP6]], align 8 527 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 528 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 529 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 530 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 8 531 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 532 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP9]], align 8 533 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 534 // CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8 535 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 536 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP11]], align 8 537 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 538 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP12]], align 8 539 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 540 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8 541 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 542 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 543 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 544 // CHECK1-NEXT: store i32 3, ptr [[TMP16]], align 4 545 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 546 // CHECK1-NEXT: store i32 3, ptr [[TMP17]], align 4 547 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 548 // CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8 549 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 550 // CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8 551 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 552 // CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP20]], align 8 553 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 554 // CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP21]], align 8 555 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 556 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 557 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 558 // CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8 559 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 560 // CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 8 561 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 562 // CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 8 563 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 564 // CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP26]], align 4 565 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 566 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 567 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 568 // CHECK1-NEXT: store i32 0, ptr [[TMP28]], align 4 569 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27.region_id, ptr [[KERNEL_ARGS]]) 570 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 571 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 572 // CHECK1: omp_offload.failed: 573 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27(ptr [[THIS1]], ptr [[TMP2]]) #[[ATTR4]] 574 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 575 // CHECK1: omp_offload.cont: 576 // CHECK1-NEXT: [[TMP31:%.*]] = load ptr, ptr [[L]], align 8 577 // CHECK1-NEXT: store ptr [[TMP31]], ptr [[_TMP2]], align 8 578 // CHECK1-NEXT: [[TMP32:%.*]] = load ptr, ptr [[_TMP2]], align 8 579 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[TMP32]], i32 0, i32 0 580 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[TMP32]], i32 0, i32 0 581 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 582 // CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP35]], align 8 583 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 584 // CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP36]], align 8 585 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS5]], i64 0, i64 0 586 // CHECK1-NEXT: store ptr null, ptr [[TMP37]], align 8 587 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 1 588 // CHECK1-NEXT: store ptr [[TMP32]], ptr [[TMP38]], align 8 589 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS4]], i32 0, i32 1 590 // CHECK1-NEXT: store ptr [[TMP32]], ptr [[TMP39]], align 8 591 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS5]], i64 0, i64 1 592 // CHECK1-NEXT: store ptr null, ptr [[TMP40]], align 8 593 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 2 594 // CHECK1-NEXT: store ptr [[TMP33]], ptr [[TMP41]], align 8 595 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS4]], i32 0, i32 2 596 // CHECK1-NEXT: store ptr [[TMP34]], ptr [[TMP42]], align 8 597 // CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS5]], i64 0, i64 2 598 // CHECK1-NEXT: store ptr null, ptr [[TMP43]], align 8 599 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 600 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 601 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 0 602 // CHECK1-NEXT: store i32 3, ptr [[TMP46]], align 4 603 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 1 604 // CHECK1-NEXT: store i32 3, ptr [[TMP47]], align 4 605 // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 2 606 // CHECK1-NEXT: store ptr [[TMP44]], ptr [[TMP48]], align 8 607 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 3 608 // CHECK1-NEXT: store ptr [[TMP45]], ptr [[TMP49]], align 8 609 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 4 610 // CHECK1-NEXT: store ptr @.offload_sizes.5, ptr [[TMP50]], align 8 611 // CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 5 612 // CHECK1-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP51]], align 8 613 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 6 614 // CHECK1-NEXT: store ptr null, ptr [[TMP52]], align 8 615 // CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 7 616 // CHECK1-NEXT: store ptr null, ptr [[TMP53]], align 8 617 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 8 618 // CHECK1-NEXT: store i64 0, ptr [[TMP54]], align 8 619 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 9 620 // CHECK1-NEXT: store i64 0, ptr [[TMP55]], align 8 621 // CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 10 622 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP56]], align 4 623 // CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 11 624 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP57]], align 4 625 // CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 12 626 // CHECK1-NEXT: store i32 0, ptr [[TMP58]], align 4 627 // CHECK1-NEXT: [[TMP59:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29.region_id, ptr [[KERNEL_ARGS6]]) 628 // CHECK1-NEXT: [[TMP60:%.*]] = icmp ne i32 [[TMP59]], 0 629 // CHECK1-NEXT: br i1 [[TMP60]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 630 // CHECK1: omp_offload.failed7: 631 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29(ptr [[THIS1]], ptr [[TMP32]]) #[[ATTR4]] 632 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT8]] 633 // CHECK1: omp_offload.cont8: 634 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 635 // CHECK1-NEXT: [[TMP61:%.*]] = load i32, ptr [[A]], align 4 636 // CHECK1-NEXT: [[TMP62:%.*]] = load ptr, ptr [[L]], align 8 637 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooIZN1S3fooEvEUlvE_EiRKT_(ptr noundef nonnull align 8 dereferenceable(8) [[TMP62]]) 638 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP61]], [[CALL]] 639 // CHECK1-NEXT: ret i32 [[ADD]] 640 // 641 // 642 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27 643 // CHECK1-SAME: (ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR1]] { 644 // CHECK1-NEXT: entry: 645 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 646 // CHECK1-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8 647 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 648 // CHECK1-NEXT: [[L1:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 649 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 650 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 651 // CHECK1-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8 652 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 653 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L_ADDR]], align 8 654 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 655 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 656 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L1]], ptr align 8 [[TMP2]], i64 8, i1 false) 657 // CHECK1-NEXT: store ptr [[L1]], ptr [[_TMP2]], align 8 658 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP2]], align 8 659 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP3]]) 660 // CHECK1-NEXT: ret void 661 // 662 // 663 // CHECK1-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv 664 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR3]] comdat { 665 // CHECK1-NEXT: entry: 666 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 667 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 668 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 669 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0 670 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 671 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[TMP1]], i32 0, i32 0 672 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 673 // CHECK1-NEXT: ret i32 [[TMP2]] 674 // 675 // 676 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29 677 // CHECK1-SAME: (ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR1]] { 678 // CHECK1-NEXT: entry: 679 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 680 // CHECK1-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8 681 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 682 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 683 // CHECK1-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8 684 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 685 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L_ADDR]], align 8 686 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 687 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 688 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29.omp_outlined, ptr [[TMP0]], ptr [[TMP2]]) 689 // CHECK1-NEXT: ret void 690 // 691 // 692 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29.omp_outlined 693 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR1]] { 694 // CHECK1-NEXT: entry: 695 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 696 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 697 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 698 // CHECK1-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8 699 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 700 // CHECK1-NEXT: [[L1:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 701 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 702 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 703 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 704 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 705 // CHECK1-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8 706 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 707 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L_ADDR]], align 8 708 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 709 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 710 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L1]], ptr align 8 [[TMP2]], i64 8, i1 false) 711 // CHECK1-NEXT: store ptr [[L1]], ptr [[_TMP2]], align 8 712 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP2]], align 8 713 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP3]]) 714 // CHECK1-NEXT: ret void 715 // 716 // 717 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooIZN1S3fooEvEUlvE_EiRKT_ 718 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] comdat { 719 // CHECK1-NEXT: entry: 720 // CHECK1-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 8 721 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 722 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8 723 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8 724 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8 725 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 726 // CHECK1-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 8 727 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8 728 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 729 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 730 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[TMP1]], i32 0, i32 0 731 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[TMP1]], i32 0, i32 0 732 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 733 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP4]], align 8 734 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 735 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP5]], align 8 736 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 737 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 738 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 739 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP7]], align 8 740 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 741 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP8]], align 8 742 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 743 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 744 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 745 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 746 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 747 // CHECK1-NEXT: store i32 3, ptr [[TMP12]], align 4 748 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 749 // CHECK1-NEXT: store i32 2, ptr [[TMP13]], align 4 750 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 751 // CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP14]], align 8 752 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 753 // CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP15]], align 8 754 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 755 // CHECK1-NEXT: store ptr @.offload_sizes.7, ptr [[TMP16]], align 8 756 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 757 // CHECK1-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP17]], align 8 758 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 759 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 760 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 761 // CHECK1-NEXT: store ptr null, ptr [[TMP19]], align 8 762 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 763 // CHECK1-NEXT: store i64 0, ptr [[TMP20]], align 8 764 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 765 // CHECK1-NEXT: store i64 0, ptr [[TMP21]], align 8 766 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 767 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP22]], align 4 768 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 769 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP23]], align 4 770 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 771 // CHECK1-NEXT: store i32 0, ptr [[TMP24]], align 4 772 // CHECK1-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18.region_id, ptr [[KERNEL_ARGS]]) 773 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 774 // CHECK1-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 775 // CHECK1: omp_offload.failed: 776 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18(ptr [[TMP1]]) #[[ATTR4]] 777 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 778 // CHECK1: omp_offload.cont: 779 // CHECK1-NEXT: ret i32 0 780 // 781 // 782 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18 783 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR1]] { 784 // CHECK1-NEXT: entry: 785 // CHECK1-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 8 786 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 787 // CHECK1-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 8 788 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8 789 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 790 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 791 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18.omp_outlined, ptr [[TMP1]]) 792 // CHECK1-NEXT: ret void 793 // 794 // 795 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18.omp_outlined 796 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR1]] { 797 // CHECK1-NEXT: entry: 798 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 799 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 800 // CHECK1-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 8 801 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 802 // CHECK1-NEXT: [[T1:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 803 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 804 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 805 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 806 // CHECK1-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 8 807 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8 808 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 809 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 810 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[T1]], ptr align 8 [[TMP1]], i64 8, i1 false) 811 // CHECK1-NEXT: store ptr [[T1]], ptr [[_TMP2]], align 8 812 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 8 813 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP2]]) 814 // CHECK1-NEXT: ret void 815 // 816 // 817 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27 818 // CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0:[0-9]+]] { 819 // CHECK2-NEXT: entry: 820 // CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 821 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 822 // CHECK2-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8 823 // CHECK2-NEXT: [[TMP:%.*]] = alloca ptr, align 8 824 // CHECK2-NEXT: [[L1:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 825 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 826 // CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 827 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 828 // CHECK2-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8 829 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 830 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L_ADDR]], align 8 831 // CHECK2-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 832 // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27_kernel_environment, ptr [[DYN_PTR]]) 833 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1 834 // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 835 // CHECK2: user_code.entry: 836 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 837 // CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L1]], ptr align 8 [[TMP3]], i64 8, i1 false) 838 // CHECK2-NEXT: store ptr [[L1]], ptr [[_TMP2]], align 8 839 // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP2]], align 8 840 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP4]], i32 0, i32 0 841 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 842 // CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP2]], align 8 843 // CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP6]]) #[[ATTR7:[0-9]+]] 844 // CHECK2-NEXT: call void @__kmpc_target_deinit() 845 // CHECK2-NEXT: ret void 846 // CHECK2: worker.exit: 847 // CHECK2-NEXT: ret void 848 // 849 // 850 // CHECK2-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv 851 // CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { 852 // CHECK2-NEXT: entry: 853 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 854 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 855 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 856 // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON:%.*]], ptr [[THIS1]], i32 0, i32 0 857 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 858 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[TMP1]], i32 0, i32 0 859 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 860 // CHECK2-NEXT: ret i32 [[TMP2]] 861 // 862 // 863 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29 864 // CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR3:[0-9]+]] { 865 // CHECK2-NEXT: entry: 866 // CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 867 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 868 // CHECK2-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8 869 // CHECK2-NEXT: [[TMP:%.*]] = alloca ptr, align 8 870 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 8 871 // CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 872 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 873 // CHECK2-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8 874 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 875 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L_ADDR]], align 8 876 // CHECK2-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 877 // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29_kernel_environment, ptr [[DYN_PTR]]) 878 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1 879 // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 880 // CHECK2: user_code.entry: 881 // CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) 882 // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 883 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 884 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 885 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 886 // CHECK2-NEXT: store ptr [[TMP4]], ptr [[TMP6]], align 8 887 // CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2) 888 // CHECK2-NEXT: call void @__kmpc_target_deinit() 889 // CHECK2-NEXT: ret void 890 // CHECK2: worker.exit: 891 // CHECK2-NEXT: ret void 892 // 893 // 894 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29_omp_outlined 895 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR4:[0-9]+]] { 896 // CHECK2-NEXT: entry: 897 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 898 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 899 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 900 // CHECK2-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8 901 // CHECK2-NEXT: [[TMP:%.*]] = alloca ptr, align 8 902 // CHECK2-NEXT: [[L1:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 903 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 904 // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 905 // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 906 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 907 // CHECK2-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8 908 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 909 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L_ADDR]], align 8 910 // CHECK2-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 911 // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 912 // CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L1]], ptr align 8 [[TMP2]], i64 8, i1 false) 913 // CHECK2-NEXT: store ptr [[L1]], ptr [[_TMP2]], align 8 914 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP2]], align 8 915 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP3]], i32 0, i32 0 916 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 8 917 // CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP2]], align 8 918 // CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR7]] 919 // CHECK2-NEXT: ret void 920 // 921 // 922 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41 923 // CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0]] { 924 // CHECK2-NEXT: entry: 925 // CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 926 // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 927 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 928 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 929 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 930 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 931 // CHECK2-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8 932 // CHECK2-NEXT: [[TMP:%.*]] = alloca ptr, align 8 933 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 934 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 935 // CHECK2-NEXT: [[L3:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 936 // CHECK2-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8 937 // CHECK2-NEXT: [[B5:%.*]] = alloca i32, align 4 938 // CHECK2-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 939 // CHECK2-NEXT: [[C7:%.*]] = alloca i32, align 4 940 // CHECK2-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 941 // CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 942 // CHECK2-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8 943 // CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 944 // CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 945 // CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 946 // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 947 // CHECK2-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8 948 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 949 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 8 950 // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8 951 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[L_ADDR]], align 8 952 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 953 // CHECK2-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8 954 // CHECK2-NEXT: store ptr [[TMP3]], ptr [[_TMP2]], align 8 955 // CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_kernel_environment, ptr [[DYN_PTR]]) 956 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 957 // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 958 // CHECK2: user_code.entry: 959 // CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP2]], align 8 960 // CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L3]], ptr align 8 [[TMP5]], i64 40, i1 false) 961 // CHECK2-NEXT: store ptr [[L3]], ptr [[_TMP4]], align 8 962 // CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 963 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 964 // CHECK2-NEXT: store i32 [[TMP7]], ptr [[B5]], align 4 965 // CHECK2-NEXT: store ptr [[B5]], ptr [[_TMP6]], align 8 966 // CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8 967 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 968 // CHECK2-NEXT: store i32 [[TMP9]], ptr [[C7]], align 4 969 // CHECK2-NEXT: store ptr [[C7]], ptr [[_TMP8]], align 8 970 // CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP4]], align 8 971 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP10]], i32 0, i32 0 972 // CHECK2-NEXT: store ptr [[ARGC_ADDR]], ptr [[TMP11]], align 8 973 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP10]], i32 0, i32 1 974 // CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP6]], align 8 975 // CHECK2-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 976 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP10]], i32 0, i32 2 977 // CHECK2-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP8]], align 8 978 // CHECK2-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8 979 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP10]], i32 0, i32 3 980 // CHECK2-NEXT: store ptr [[D_ADDR]], ptr [[TMP16]], align 8 981 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP10]], i32 0, i32 4 982 // CHECK2-NEXT: store ptr [[TMP2]], ptr [[TMP17]], align 8 983 // CHECK2-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP4]], align 8 984 // CHECK2-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(40) [[TMP18]]) #[[ATTR7]] 985 // CHECK2-NEXT: call void @__kmpc_target_deinit() 986 // CHECK2-NEXT: ret void 987 // CHECK2: worker.exit: 988 // CHECK2-NEXT: ret void 989 // 990 // 991 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43 992 // CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3]] { 993 // CHECK2-NEXT: entry: 994 // CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 995 // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8 996 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 997 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 998 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 999 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 1000 // CHECK2-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8 1001 // CHECK2-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1002 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1003 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 1004 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [6 x ptr], align 8 1005 // CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 1006 // CHECK2-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 1007 // CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1008 // CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1009 // CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 1010 // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 1011 // CHECK2-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8 1012 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8 1013 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1014 // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1015 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8 1016 // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[L_ADDR]], align 8 1017 // CHECK2-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 1018 // CHECK2-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 8 1019 // CHECK2-NEXT: store ptr [[TMP4]], ptr [[_TMP2]], align 8 1020 // CHECK2-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43_kernel_environment, ptr [[DYN_PTR]]) 1021 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP5]], -1 1022 // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 1023 // CHECK2: user_code.entry: 1024 // CHECK2-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 1025 // CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8 1026 // CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8 1027 // CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[D_ADDR]], align 8 1028 // CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 1029 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 1030 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP11]], align 8 1031 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 1032 // CHECK2-NEXT: store ptr [[TMP7]], ptr [[TMP12]], align 8 1033 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2 1034 // CHECK2-NEXT: store ptr [[TMP8]], ptr [[TMP13]], align 8 1035 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3 1036 // CHECK2-NEXT: store ptr [[TMP9]], ptr [[TMP14]], align 8 1037 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4 1038 // CHECK2-NEXT: store ptr [[TMP3]], ptr [[TMP15]], align 8 1039 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 5 1040 // CHECK2-NEXT: store ptr [[TMP10]], ptr [[TMP16]], align 8 1041 // CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP6]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 6) 1042 // CHECK2-NEXT: call void @__kmpc_target_deinit() 1043 // CHECK2-NEXT: ret void 1044 // CHECK2: worker.exit: 1045 // CHECK2-NEXT: ret void 1046 // 1047 // 1048 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43_omp_outlined 1049 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR4]] { 1050 // CHECK2-NEXT: entry: 1051 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1052 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1053 // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8 1054 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1055 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1056 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 1057 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 1058 // CHECK2-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8 1059 // CHECK2-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1060 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1061 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 1062 // CHECK2-NEXT: [[L3:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 1063 // CHECK2-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8 1064 // CHECK2-NEXT: [[ARGC5:%.*]] = alloca i32, align 4 1065 // CHECK2-NEXT: [[B6:%.*]] = alloca i32, align 4 1066 // CHECK2-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 1067 // CHECK2-NEXT: [[C8:%.*]] = alloca i32, align 4 1068 // CHECK2-NEXT: [[_TMP9:%.*]] = alloca ptr, align 8 1069 // CHECK2-NEXT: [[A10:%.*]] = alloca i32, align 4 1070 // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1071 // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1072 // CHECK2-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 1073 // CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1074 // CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1075 // CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 1076 // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 1077 // CHECK2-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8 1078 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8 1079 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1080 // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1081 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8 1082 // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[L_ADDR]], align 8 1083 // CHECK2-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 1084 // CHECK2-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 8 1085 // CHECK2-NEXT: store ptr [[TMP4]], ptr [[_TMP2]], align 8 1086 // CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP2]], align 8 1087 // CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L3]], ptr align 8 [[TMP5]], i64 40, i1 false) 1088 // CHECK2-NEXT: store ptr [[L3]], ptr [[_TMP4]], align 8 1089 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4 1090 // CHECK2-NEXT: store i32 [[TMP6]], ptr [[ARGC5]], align 4 1091 // CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8 1092 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1093 // CHECK2-NEXT: store i32 [[TMP8]], ptr [[B6]], align 4 1094 // CHECK2-NEXT: store ptr [[B6]], ptr [[_TMP7]], align 8 1095 // CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8 1096 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 1097 // CHECK2-NEXT: store i32 [[TMP10]], ptr [[C8]], align 4 1098 // CHECK2-NEXT: store ptr [[C8]], ptr [[_TMP9]], align 8 1099 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP3]], align 4 1100 // CHECK2-NEXT: store i32 [[TMP11]], ptr [[A10]], align 4 1101 // CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8 1102 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP12]], i32 0, i32 0 1103 // CHECK2-NEXT: store ptr [[ARGC5]], ptr [[TMP13]], align 8 1104 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP12]], i32 0, i32 1 1105 // CHECK2-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8 1106 // CHECK2-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8 1107 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP12]], i32 0, i32 2 1108 // CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP9]], align 8 1109 // CHECK2-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8 1110 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP12]], i32 0, i32 3 1111 // CHECK2-NEXT: store ptr [[D_ADDR]], ptr [[TMP18]], align 8 1112 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP12]], i32 0, i32 4 1113 // CHECK2-NEXT: store ptr [[A10]], ptr [[TMP19]], align 8 1114 // CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP4]], align 8 1115 // CHECK2-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(40) [[TMP20]]) #[[ATTR7]] 1116 // CHECK2-NEXT: ret void 1117 // 1118 // 1119 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18 1120 // CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] { 1121 // CHECK2-NEXT: entry: 1122 // CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 1123 // CHECK2-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 8 1124 // CHECK2-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1125 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 8 1126 // CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 1127 // CHECK2-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 8 1128 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8 1129 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 1130 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18_kernel_environment, ptr [[DYN_PTR]]) 1131 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 1132 // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 1133 // CHECK2: user_code.entry: 1134 // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 1135 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 1136 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 1137 // CHECK2-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 1138 // CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 1) 1139 // CHECK2-NEXT: call void @__kmpc_target_deinit() 1140 // CHECK2-NEXT: ret void 1141 // CHECK2: worker.exit: 1142 // CHECK2-NEXT: ret void 1143 // 1144 // 1145 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18_omp_outlined 1146 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR4]] { 1147 // CHECK2-NEXT: entry: 1148 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1149 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1150 // CHECK2-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 8 1151 // CHECK2-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1152 // CHECK2-NEXT: [[T1:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 1153 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 1154 // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1155 // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1156 // CHECK2-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 8 1157 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8 1158 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 1159 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 1160 // CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[T1]], ptr align 8 [[TMP1]], i64 8, i1 false) 1161 // CHECK2-NEXT: store ptr [[T1]], ptr [[_TMP2]], align 8 1162 // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 8 1163 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP2]], align 8 1164 // CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP3]]) #[[ATTR7]] 1165 // CHECK2-NEXT: ret void 1166 // 1167 // 1168 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27 1169 // CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0:[0-9]+]] { 1170 // CHECK3-NEXT: entry: 1171 // CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 1172 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1173 // CHECK3-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8 1174 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1175 // CHECK3-NEXT: [[L1:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 1176 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 1177 // CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 1178 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1179 // CHECK3-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8 1180 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1181 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L_ADDR]], align 8 1182 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 1183 // CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27_kernel_environment, ptr [[DYN_PTR]]) 1184 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1 1185 // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 1186 // CHECK3: user_code.entry: 1187 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 1188 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L1]], ptr align 8 [[TMP3]], i64 8, i1 false) 1189 // CHECK3-NEXT: store ptr [[L1]], ptr [[_TMP2]], align 8 1190 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP2]], align 8 1191 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP4]], i32 0, i32 0 1192 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 1193 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP2]], align 8 1194 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP6]]) #[[ATTR7:[0-9]+]] 1195 // CHECK3-NEXT: call void @__kmpc_target_deinit() 1196 // CHECK3-NEXT: ret void 1197 // CHECK3: worker.exit: 1198 // CHECK3-NEXT: ret void 1199 // 1200 // 1201 // CHECK3-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv 1202 // CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { 1203 // CHECK3-NEXT: entry: 1204 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1205 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1206 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1207 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON:%.*]], ptr [[THIS1]], i32 0, i32 0 1208 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 1209 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[TMP1]], i32 0, i32 0 1210 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1211 // CHECK3-NEXT: ret i32 [[TMP2]] 1212 // 1213 // 1214 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29 1215 // CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR3:[0-9]+]] { 1216 // CHECK3-NEXT: entry: 1217 // CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 1218 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1219 // CHECK3-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8 1220 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1221 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 8 1222 // CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 1223 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1224 // CHECK3-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8 1225 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1226 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L_ADDR]], align 8 1227 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 1228 // CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29_kernel_environment, ptr [[DYN_PTR]]) 1229 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1 1230 // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 1231 // CHECK3: user_code.entry: 1232 // CHECK3-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) 1233 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 1234 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 1235 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 1236 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 1237 // CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP6]], align 8 1238 // CHECK3-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2) 1239 // CHECK3-NEXT: call void @__kmpc_target_deinit() 1240 // CHECK3-NEXT: ret void 1241 // CHECK3: worker.exit: 1242 // CHECK3-NEXT: ret void 1243 // 1244 // 1245 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29_omp_outlined 1246 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR4:[0-9]+]] { 1247 // CHECK3-NEXT: entry: 1248 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1249 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1250 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1251 // CHECK3-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8 1252 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1253 // CHECK3-NEXT: [[L1:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 1254 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 1255 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1256 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1257 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1258 // CHECK3-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8 1259 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1260 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L_ADDR]], align 8 1261 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 1262 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 1263 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L1]], ptr align 8 [[TMP2]], i64 8, i1 false) 1264 // CHECK3-NEXT: store ptr [[L1]], ptr [[_TMP2]], align 8 1265 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP2]], align 8 1266 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[TMP3]], i32 0, i32 0 1267 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 8 1268 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP2]], align 8 1269 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR7]] 1270 // CHECK3-NEXT: ret void 1271 // 1272 // 1273 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41 1274 // CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0]] { 1275 // CHECK3-NEXT: entry: 1276 // CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 1277 // CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 1278 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1279 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1280 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 1281 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 1282 // CHECK3-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8 1283 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1284 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1285 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 1286 // CHECK3-NEXT: [[L3:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 1287 // CHECK3-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8 1288 // CHECK3-NEXT: [[B5:%.*]] = alloca i32, align 4 1289 // CHECK3-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 1290 // CHECK3-NEXT: [[C7:%.*]] = alloca i32, align 4 1291 // CHECK3-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 1292 // CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 1293 // CHECK3-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8 1294 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1295 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1296 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 1297 // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 1298 // CHECK3-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8 1299 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1300 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1301 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8 1302 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[L_ADDR]], align 8 1303 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 1304 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8 1305 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[_TMP2]], align 8 1306 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_kernel_environment, ptr [[DYN_PTR]]) 1307 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 1308 // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 1309 // CHECK3: user_code.entry: 1310 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP2]], align 8 1311 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L3]], ptr align 8 [[TMP5]], i64 40, i1 false) 1312 // CHECK3-NEXT: store ptr [[L3]], ptr [[_TMP4]], align 8 1313 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 1314 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 1315 // CHECK3-NEXT: store i32 [[TMP7]], ptr [[B5]], align 4 1316 // CHECK3-NEXT: store ptr [[B5]], ptr [[_TMP6]], align 8 1317 // CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8 1318 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 1319 // CHECK3-NEXT: store i32 [[TMP9]], ptr [[C7]], align 4 1320 // CHECK3-NEXT: store ptr [[C7]], ptr [[_TMP8]], align 8 1321 // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP4]], align 8 1322 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP10]], i32 0, i32 0 1323 // CHECK3-NEXT: store ptr [[ARGC_ADDR]], ptr [[TMP11]], align 8 1324 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP10]], i32 0, i32 1 1325 // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP6]], align 8 1326 // CHECK3-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 1327 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP10]], i32 0, i32 2 1328 // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP8]], align 8 1329 // CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8 1330 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP10]], i32 0, i32 3 1331 // CHECK3-NEXT: store ptr [[D_ADDR]], ptr [[TMP16]], align 8 1332 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP10]], i32 0, i32 4 1333 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP17]], align 8 1334 // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP4]], align 8 1335 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(40) [[TMP18]]) #[[ATTR7]] 1336 // CHECK3-NEXT: call void @__kmpc_target_deinit() 1337 // CHECK3-NEXT: ret void 1338 // CHECK3: worker.exit: 1339 // CHECK3-NEXT: ret void 1340 // 1341 // 1342 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43 1343 // CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3]] { 1344 // CHECK3-NEXT: entry: 1345 // CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 1346 // CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8 1347 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1348 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1349 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 1350 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 1351 // CHECK3-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8 1352 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1353 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1354 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 1355 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [6 x ptr], align 8 1356 // CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 1357 // CHECK3-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 1358 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1359 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1360 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 1361 // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 1362 // CHECK3-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8 1363 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8 1364 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1365 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1366 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8 1367 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[L_ADDR]], align 8 1368 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 1369 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 8 1370 // CHECK3-NEXT: store ptr [[TMP4]], ptr [[_TMP2]], align 8 1371 // CHECK3-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43_kernel_environment, ptr [[DYN_PTR]]) 1372 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP5]], -1 1373 // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 1374 // CHECK3: user_code.entry: 1375 // CHECK3-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 1376 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8 1377 // CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8 1378 // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[D_ADDR]], align 8 1379 // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 1380 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 1381 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP11]], align 8 1382 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 1383 // CHECK3-NEXT: store ptr [[TMP7]], ptr [[TMP12]], align 8 1384 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2 1385 // CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP13]], align 8 1386 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3 1387 // CHECK3-NEXT: store ptr [[TMP9]], ptr [[TMP14]], align 8 1388 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4 1389 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP15]], align 8 1390 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 5 1391 // CHECK3-NEXT: store ptr [[TMP10]], ptr [[TMP16]], align 8 1392 // CHECK3-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP6]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 6) 1393 // CHECK3-NEXT: call void @__kmpc_target_deinit() 1394 // CHECK3-NEXT: ret void 1395 // CHECK3: worker.exit: 1396 // CHECK3-NEXT: ret void 1397 // 1398 // 1399 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43_omp_outlined 1400 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR4]] { 1401 // CHECK3-NEXT: entry: 1402 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1403 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1404 // CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8 1405 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1406 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1407 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 1408 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 1409 // CHECK3-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8 1410 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1411 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1412 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 1413 // CHECK3-NEXT: [[L3:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 1414 // CHECK3-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8 1415 // CHECK3-NEXT: [[ARGC5:%.*]] = alloca i32, align 4 1416 // CHECK3-NEXT: [[B6:%.*]] = alloca i32, align 4 1417 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 1418 // CHECK3-NEXT: [[C8:%.*]] = alloca i32, align 4 1419 // CHECK3-NEXT: [[_TMP9:%.*]] = alloca ptr, align 8 1420 // CHECK3-NEXT: [[A10:%.*]] = alloca i32, align 4 1421 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1422 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1423 // CHECK3-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 1424 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1425 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1426 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 1427 // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 1428 // CHECK3-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8 1429 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8 1430 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1431 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1432 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8 1433 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[L_ADDR]], align 8 1434 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 1435 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 8 1436 // CHECK3-NEXT: store ptr [[TMP4]], ptr [[_TMP2]], align 8 1437 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP2]], align 8 1438 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L3]], ptr align 8 [[TMP5]], i64 40, i1 false) 1439 // CHECK3-NEXT: store ptr [[L3]], ptr [[_TMP4]], align 8 1440 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4 1441 // CHECK3-NEXT: store i32 [[TMP6]], ptr [[ARGC5]], align 4 1442 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8 1443 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1444 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[B6]], align 4 1445 // CHECK3-NEXT: store ptr [[B6]], ptr [[_TMP7]], align 8 1446 // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8 1447 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 1448 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[C8]], align 4 1449 // CHECK3-NEXT: store ptr [[C8]], ptr [[_TMP9]], align 8 1450 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP3]], align 4 1451 // CHECK3-NEXT: store i32 [[TMP11]], ptr [[A10]], align 4 1452 // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8 1453 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP12]], i32 0, i32 0 1454 // CHECK3-NEXT: store ptr [[ARGC5]], ptr [[TMP13]], align 8 1455 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP12]], i32 0, i32 1 1456 // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8 1457 // CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8 1458 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP12]], i32 0, i32 2 1459 // CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP9]], align 8 1460 // CHECK3-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8 1461 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP12]], i32 0, i32 3 1462 // CHECK3-NEXT: store ptr [[D_ADDR]], ptr [[TMP18]], align 8 1463 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[TMP12]], i32 0, i32 4 1464 // CHECK3-NEXT: store ptr [[A10]], ptr [[TMP19]], align 8 1465 // CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP4]], align 8 1466 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(40) [[TMP20]]) #[[ATTR7]] 1467 // CHECK3-NEXT: ret void 1468 // 1469 // 1470 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18 1471 // CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] { 1472 // CHECK3-NEXT: entry: 1473 // CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 1474 // CHECK3-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 8 1475 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1476 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 8 1477 // CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 1478 // CHECK3-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 8 1479 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8 1480 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 1481 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18_kernel_environment, ptr [[DYN_PTR]]) 1482 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 1483 // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 1484 // CHECK3: user_code.entry: 1485 // CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 1486 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 1487 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 1488 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 1489 // CHECK3-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 1) 1490 // CHECK3-NEXT: call void @__kmpc_target_deinit() 1491 // CHECK3-NEXT: ret void 1492 // CHECK3: worker.exit: 1493 // CHECK3-NEXT: ret void 1494 // 1495 // 1496 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18_omp_outlined 1497 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR4]] { 1498 // CHECK3-NEXT: entry: 1499 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1500 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1501 // CHECK3-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 8 1502 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1503 // CHECK3-NEXT: [[T1:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 1504 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 1505 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1506 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1507 // CHECK3-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 8 1508 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8 1509 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 1510 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 1511 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[T1]], ptr align 8 [[TMP1]], i64 8, i1 false) 1512 // CHECK3-NEXT: store ptr [[T1]], ptr [[_TMP2]], align 8 1513 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 8 1514 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP2]], align 8 1515 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP3]]) #[[ATTR7]] 1516 // CHECK3-NEXT: ret void 1517 // 1518