xref: /llvm-project/clang/test/OpenMP/nested_loop_codegen.cpp (revision 8ab62da18d47fa0ce6aef9da50cca34a26ea775c) 
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 
3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1
4 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
5 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3
7 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
8 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -gno-column-info -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4
9 
10 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
11 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
12 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
13 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
16 // expected-no-diagnostics
17 #ifndef HEADER
18 #define HEADER
19 
20 int outline_decl() {
21   int i, k;
22   #pragma omp parallel
23   for(i=0; i<10; i++) {
24     #pragma omp loop
25     for(k=0; k<5; k++) {
26       k++;
27     }
28   }
29   return k;
30 }
31 
32 int inline_decl() {
33   int i, res;
34   #pragma omp parallel
35   for(i=0; i<10; i++) {
36     #pragma omp loop
37     for(int k=0; k<5; k++) {
38       res++;
39     }
40   }
41   return res;
42 }
43 
44 #endif
45 // CHECK1-LABEL: define {{[^@]+}}@_Z12outline_declv
46 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
47 // CHECK1-NEXT:  entry:
48 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
49 // CHECK1-NEXT:    [[K:%.*]] = alloca i32, align 4
50 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @_Z12outline_declv.omp_outlined, ptr [[I]])
51 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[K]], align 4
52 // CHECK1-NEXT:    ret i32 [[TMP0]]
53 //
54 //
55 // CHECK1-LABEL: define {{[^@]+}}@_Z12outline_declv.omp_outlined
56 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] {
57 // CHECK1-NEXT:  entry:
58 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
59 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
60 // CHECK1-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
61 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
62 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
63 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
64 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
65 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
66 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
67 // CHECK1-NEXT:    [[K:%.*]] = alloca i32, align 4
68 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
69 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
70 // CHECK1-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
71 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
72 // CHECK1-NEXT:    store i32 0, ptr [[TMP0]], align 4
73 // CHECK1-NEXT:    br label [[FOR_COND:%.*]]
74 // CHECK1:       for.cond:
75 // CHECK1:       for.body:
76 // CHECK1-NEXT     [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
77 // CHECK1-NEXT     [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
78 // CHECK1-NEXT     call void @__kmpc_for_static_init_4(ptr @1, i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
79 //CHECK1     cond.end:
80 //CHECK1     omp.inner.for.cond:
81 //CHECK1     omp.inner.for.body:
82 //CHECK1     omp.body.continue:
83 //CHECK1     omp.inner.for.inc:
84 //CHECK1     omp.inner.for.end:
85 //CHECK1     omp.loop.exit:
86 // CHECK1-NEXT     [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
87 // CHECK1-NEXT     [[TMP14:%.*]] = load i32, ptr [[TMP12]], align 4
88 // CHECK1-NEXT     call void @__kmpc_for_static_fini(ptr @1, i32 [[TMP14]])
89 // CHECK1-NEXT     [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
90 // CHECK1-NEXT     [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4
91 // CHECK1-NEXT     call void @__kmpc_barrier(ptr @2, i32 [[TMP16]])
92 //CHECK1     for.inc:
93 //CHECK1     for.end:
94 // CHECK1-NEXT     ret void
95 //
96 //
97 //
98 // CHECK1-LABEL: define {{[^@]+}}@_Z11inline_declv
99 // CHECK1-SAME: () #[[ATTR0]] {
100 // CHECK1-NEXT:  entry:
101 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
102 // CHECK1-NEXT:    [[RES:%.*]] = alloca i32, align 4
103 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @_Z11inline_declv.omp_outlined, ptr [[I]], ptr [[RES]])
104 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RES]], align 4
105 // CHECK1-NEXT:    ret i32 [[TMP0]]
106 //
107 //
108 // CHECK1-LABEL: define {{[^@]+}}@_Z11inline_declv.omp_outlined
109 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RES:%.*]]) #[[ATTR1]] {
110 // CHECK1-NEXT:  entry:
111 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
112 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
113 // CHECK1-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
114 // CHECK1-NEXT:    [[RES_ADDR:%.*]] = alloca ptr, align 8
115 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
116 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
117 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
118 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
119 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
120 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
121 // CHECK1:      for.cond:
122 // CHECK1:      for.body:
123 // CHECK1-NEXT:   store i32 0, ptr [[DOTOMP_LB]], align 4
124 // CHECK1-NEXT:   store i32 4, ptr [[DOTOMP_UB]], align 4
125 // CHECK1-NEXT:   store i32 1, ptr [[DOTOMP_STRIDE]], align 4
126 // CHECK1-NEXT:   store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
127 // CHECK1-NEXT:   [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
128 // CHECK1-NEXT:   [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
129 // CHECK1-NEXT:   call void @__kmpc_for_static_init_4(ptr @1, i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
130 // CHECK1:      omp.inner.for.cond:
131 // CHECK1:      omp.inner.for.body:
132 // CHECK1:      omp.body.continue:
133 // CHECK1:      omp.inner.for.inc:
134 // CHECK1:      omp.inner.for.end:
135 // CHECK1:      omp.loop.exit:
136 // CHECK1-NEXT:   [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
137 // CHECK1-NEXT:   [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
138 // CHECK1-NEXT:   call void @__kmpc_for_static_fini(ptr @1, i32 [[TMP14]])
139 // CHECK1-NEXT:   [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
140 // CHECK1-NEXT:   [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4
141 // CHECK1-NEXT:   call void @__kmpc_barrier(ptr @2, i32 [[TMP16]])
142 // CHECK1:     for.inc:
143 // CHECK1:     for.end:
144 // CHECK1-NEXT:   ret void
145 //
146 //
147 // CHECK2-LABEL: define {{[^@]+}}@_Z12outline_declv
148 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] {
149 // CHECK2-NEXT:  entry:
150 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
151 // CHECK2-NEXT:    [[K:%.*]] = alloca i32, align 4
152 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META12:![0-9]+]], metadata !DIExpression()), !dbg [[DBG13:![0-9]+]]
153 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[K]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]]
154 // CHECK2-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @_Z12outline_declv.omp_outlined, ptr [[I]]), !dbg [[DBG16:![0-9]+]]
155 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[K]], align 4, !dbg [[DBG17:![0-9]+]]
156 // CHECK2-NEXT:    ret i32 [[TMP0]], !dbg [[DBG18:![0-9]+]]
157 //
158 //
159 // CHECK2-LABEL: define {{[^@]+}}@_Z12outline_declv.omp_outlined_debug__
160 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR2:[0-9]+]] !dbg [[DBG19:![0-9]+]] {
161 // CHECK2-NEXT:  entry:
162 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
163 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
164 // CHECK2-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
165 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
166 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
167 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
168 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
169 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
170 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
171 // CHECK2-NEXT:    [[K:%.*]] = alloca i32, align 4
172 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
173 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META27:![0-9]+]], metadata !DIExpression()), !dbg [[DBG28:![0-9]+]]
174 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
175 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META29:![0-9]+]], metadata !DIExpression()), !dbg [[DBG28]]
176 // CHECK2-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
177 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[I_ADDR]], metadata [[META30:![0-9]+]], metadata !DIExpression()), !dbg [[DBG31:![0-9]+]]
178 // CHECK2:       for.body:
179 // CHECK2:         [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg !50
180 // CHECK2:         [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg !50
181 // CHECK2:         call void @__kmpc_for_static_init_4(ptr @1, i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg !51
182 // CHECK2:       omp.inner.for.cond:
183 // CHECK2:       omp.inner.for.body:
184 // CHECK2:       omp.body.continue:
185 // CHECK2:       omp.inner.for.inc:
186 // CHECK2:       omp.inner.for.end:
187 // CHECK2:       omp.loop.exit:
188 // CHECK2-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg !51
189 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg !51
190 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(ptr @3, i32 [[TMP13]]), !dbg !58
191 // CHECK2-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg !58
192 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4, !dbg !58
193 // CHECK2-NEXT:    call void @__kmpc_barrier(ptr @4, i32 [[TMP15]]), !dbg !58
194 // CHECK2:       for.inc:
195 // CHECK2:       for.end:
196 // CHECK2-NEXT:    ret void, !dbg [[DBG64:![0-9]+]]
197 //
198 //
199 // CHECK2-LABEL: define {{[^@]+}}@_Z12outline_declv.omp_outlined
200 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR2]] !dbg [[DBG65:![0-9]+]] {
201 // CHECK2-NEXT:  entry:
202 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
203 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
204 // CHECK2-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
205 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
206 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META66:![0-9]+]], metadata !DIExpression()), !dbg [[DBG67:![0-9]+]]
207 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
208 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META68:![0-9]+]], metadata !DIExpression()), !dbg [[DBG67]]
209 // CHECK2-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
210 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[I_ADDR]], metadata [[META69:![0-9]+]], metadata !DIExpression()), !dbg [[DBG67]]
211 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !dbg [[DBG70:![0-9]+]]
212 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG70]]
213 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG70]]
214 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !dbg [[DBG70]]
215 // CHECK2-NEXT:    call void @_Z12outline_declv.omp_outlined_debug__(ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3:[0-9]+]], !dbg [[DBG70]]
216 // CHECK2-NEXT:    ret void, !dbg [[DBG70]]
217 //
218 //
219 // CHECK2-LABEL: define {{[^@]+}}@_Z11inline_declv
220 // CHECK2-SAME: () #[[ATTR0]] !dbg [[DBG73:![0-9]+]] {
221 // CHECK2-NEXT:  entry:
222 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
223 // CHECK2-NEXT:    [[RES:%.*]] = alloca i32, align 4
224 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META74:![0-9]+]], metadata !DIExpression()), !dbg [[DBG75:![0-9]+]]
225 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META76:![0-9]+]], metadata !DIExpression()), !dbg [[DBG77:![0-9]+]]
226 // CHECK2-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 2, ptr @_Z11inline_declv.omp_outlined, ptr [[I]], ptr [[RES]]), !dbg [[DBG78:![0-9]+]]
227 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG79:![0-9]+]]
228 // CHECK2-NEXT:    ret i32 [[TMP0]], !dbg [[DBG80:![0-9]+]]
229 //
230 //
231 // CHECK2-LABEL: define {{[^@]+}}@_Z11inline_declv.omp_outlined_debug__
232 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RES:%.*]]) #[[ATTR2]] !dbg [[DBG81:![0-9]+]] {
233 // CHECK2-NEXT:  entry:
234 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
235 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
236 // CHECK2-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
237 // CHECK2-NEXT:    [[RES_ADDR:%.*]] = alloca ptr, align 8
238 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
239 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
240 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
241 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
242 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
243 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
244 // CHECK2-NEXT:    [[K:%.*]] = alloca i32, align 4
245 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
246 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META84:![0-9]+]], metadata !DIExpression()), !dbg [[DBG85:![0-9]+]]
247 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
248 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META86:![0-9]+]], metadata !DIExpression()), !dbg [[DBG85]]
249 // CHECK2-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
250 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[I_ADDR]], metadata [[META87:![0-9]+]], metadata !DIExpression()), !dbg [[DBG88:![0-9]+]]
251 // CHECK2-NEXT:    store ptr [[RES]], ptr [[RES_ADDR]], align 8
252 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES_ADDR]], metadata [[META89:![0-9]+]], metadata !DIExpression()), !dbg [[DBG90:![0-9]+]]
253 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !dbg [[DBG91:![0-9]+]]
254 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[RES_ADDR]], align 8, !dbg [[DBG91]]
255 // CHECK2-NEXT:    store i32 0, ptr [[TMP0]], align 4, !dbg [[DBG92:![0-9]+]]
256 // CHECK2-NEXT:    br label [[FOR_COND:%.*]], !dbg [[DBG94:![0-9]+]]
257 // CHECK2:       for.cond:
258 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG95:![0-9]+]]
259 // CHECK2-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 10, !dbg [[DBG97:![0-9]+]]
260 // CHECK2-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]], !dbg [[DBG98:![0-9]+]]
261 // CHECK2:       for.body:
262 // CHECK2:         [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG103:![0-9]+]]
263 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG103:![0-9]+]]
264 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(ptr @8, i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG103:![0-9]+]]
265 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG103:![0-9]+]]
266 // CHECK2-NEXT:    [[CMP1:%.*]] = icmp sgt i32 [[TMP5]], 4, !dbg [[DBG103:![0-9]+]]
267 // CHECK2:       omp.inner.for.cond:
268 // CHECK2:       omp.inner.for.body:
269 // CHECK2:       omp.body.continue:
270 // CHECK2:       omp.inner.for.inc:
271 // CHECK2:       omp.inner.for.end:
272 // CHECK2:       omp.loop.exit:
273 // CHECK2-NEXT:   [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg !111
274 // CHECK2-NEXT:   [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg !111
275 // CHECK2-NEXT:   call void @__kmpc_for_static_fini(ptr @10, i32 [[TMP14]]), !dbg !118
276 // CHECK2-NEXT:   [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg !118
277 // CHECK2-NEXT:   [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4, !dbg !118
278 // CHECK2-NEXT:   call void @__kmpc_barrier(ptr @11, i32 [[TMP16]]), !dbg !118
279 // CHECK2-NEXT    br label [[FOR_INC]], !dbg !119
280 // CHECK2:       for.inc:
281 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG112:![0-9]+]]
282 // CHECK2-NEXT:    [[INC4:%.*]] = add nsw i32 [[TMP17]], 1, !dbg [[DBG112]]
283 // CHECK2-NEXT:    store i32 [[INC4]], ptr [[TMP0]], align 4, !dbg [[DBG112]]
284 // CHECK2-NEXT:    br label [[FOR_COND]], !dbg [[DBG113:![0-9]+]], !llvm.loop [[DBG113:![0-9]+]]
285 // CHECK2:       for.end:
286 // CHECK2-NEXT:    ret void, !dbg [[DBG114:![0-9]+]]
287 //
288 //
289 // CHECK2-LABEL: define {{[^@]+}}@_Z11inline_declv.omp_outlined
290 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RES:%.*]]) #[[ATTR2]] !dbg [[DBG122:![0-9]+]] {
291 // CHECK2-NEXT:  entry:
292 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
293 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
294 // CHECK2-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
295 // CHECK2-NEXT:    [[RES_ADDR:%.*]] = alloca ptr, align 8
296 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
297 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META123:![0-9]+]], metadata !DIExpression()), !dbg [[DBG124:![0-9]+]]
298 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
299 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META125:![0-9]+]], metadata !DIExpression()), !dbg [[DBG124]]
300 // CHECK2-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
301 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[I_ADDR]], metadata [[META126:![0-9]+]], metadata !DIExpression()), !dbg [[DBG124]]
302 // CHECK2-NEXT:    store ptr [[RES]], ptr [[RES_ADDR]], align 8
303 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES_ADDR]], metadata [[META127:![0-9]+]], metadata !DIExpression()), !dbg [[DBG124]]
304 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !dbg [[DBG128:![0-9]+]]
305 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[RES_ADDR]], align 8, !dbg [[DBG128]]
306 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG128]]
307 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG128]]
308 // CHECK2-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !dbg [[DBG128]]
309 // CHECK2-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[RES_ADDR]], align 8, !dbg [[DBG128]]
310 // CHECK2-NEXT:    call void @_Z11inline_declv.omp_outlined_debug__(ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]], ptr [[TMP5]]) #[[ATTR3]], !dbg [[DBG128]]
311 // CHECK2-NEXT:    ret void, !dbg [[DBG128]]
312 //
313 //
314 // CHECK3-LABEL: define {{[^@]+}}@_Z12outline_declv
315 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
316 // CHECK3-NEXT:  entry:
317 // CHECK3-NEXT:    [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
318 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
319 // CHECK3-NEXT:    [[K:%.*]] = alloca i32, align 4
320 // CHECK3-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
321 // CHECK3-NEXT:    br label [[OMP_PARALLEL:%.*]]
322 // CHECK3:       omp_parallel:
323 // CHECK3-NEXT:    [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
324 // CHECK3-NEXT:    store ptr [[I]], ptr [[GEP_I]], align 8
325 // CHECK3-NEXT:    [[GEP_K:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
326 // CHECK3-NEXT:    store ptr [[K]], ptr [[GEP_K]], align 8
327 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_Z12outline_declv..omp_par, ptr [[STRUCTARG]])
328 // CHECK3-NEXT:    br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
329 // CHECK3:       omp.par.outlined.exit:
330 // CHECK3-NEXT:    br label [[OMP_PAR_EXIT_SPLIT:%.*]]
331 // CHECK3:       omp.par.exit.split:
332 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[K]], align 4
333 // CHECK3-NEXT:    ret i32 [[TMP0]]
334 //
335 //
336 // CHECK3-LABEL: define {{[^@]+}}@_Z12outline_declv..omp_par
337 // CHECK3-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] {
338 // CHECK3-NEXT:  omp.par.entry:
339 // CHECK3-NEXT:    [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 0
340 // CHECK3-NEXT:    [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
341 // CHECK3-NEXT:    [[GEP_K:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 1
342 // CHECK3-NEXT:    [[LOADGEP_K:%.*]] = load ptr, ptr [[GEP_K]], align 8
343 // CHECK3-NEXT:    [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
344 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4
345 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4
346 // CHECK3-NEXT:    [[TID:%.*]] = load i32, ptr [[TID_ADDR_LOCAL]], align 4
347 // CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
348 // CHECK3-NEXT:    [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 4
349 // CHECK3-NEXT:    [[DOTCOUNT_ADDR:%.*]] = alloca i32, align 4
350 // CHECK3-NEXT:    [[P_LASTITER:%.*]] = alloca i32, align 4
351 // CHECK3-NEXT:    [[P_LOWERBOUND:%.*]] = alloca i32, align 4
352 // CHECK3-NEXT:    [[P_UPPERBOUND:%.*]] = alloca i32, align 4
353 // CHECK3-NEXT:    [[P_STRIDE:%.*]] = alloca i32, align 4
354 // CHECK3-NEXT:    br label [[OMP_PAR_REGION:%.*]]
355 // CHECK3:       omp.par.region:
356 // CHECK3-NEXT:    store i32 0, ptr [[LOADGEP_I]], align 4
357 // CHECK3-NEXT:    br label [[FOR_COND:]]
358 // CHECK3:       for.cond:
359 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
360 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 10
361 // CHECK3-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
362 // CHECK3:       for.end:
363 // CHECK3-NEXT:    br label [[OMP_PAR_REGION_PARALLEL_AFTER:%.*]]
364 // CHECK3:       omp.par.region.parallel.after:
365 // CHECK3-NEXT:    br label [[OMP_PAR_PRE_FINALIZE:%.*]]
366 // CHECK3:       omp.par.pre_finalize:
367 // CHECK3-NEXT:    br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]]
368 // CHECK3:       for.body:
369 // CHECK3-NEXT:    store i32 0, ptr [[LOADGEP_K]], align 4
370 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
371 // CHECK3-NEXT:    store ptr [[LOADGEP_K]], ptr [[TMP3]], align 8
372 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[AGG_CAPTURED1]], i32 0, i32 0
373 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[LOADGEP_K]], align 4
374 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP4]], align 4
375 // CHECK3-NEXT:    call void @__captured_stmt(ptr [[DOTCOUNT_ADDR]], ptr [[AGG_CAPTURED]])
376 // CHECK3-NEXT:    [[DOTCOUNT:%.*]] = load i32, ptr [[DOTCOUNT_ADDR]], align 4
377 // CHECK3-NEXT:    br label [[OMP_LOOP_PREHEADER:%.*]]
378 // CHECK3:       omp_loop.preheader:
379 // CHECK3-NEXT:    store i32 0, ptr [[P_LOWERBOUND]], align 4
380 // CHECK3-NEXT:    [[TMP6:%.*]] = sub i32 [[DOTCOUNT]], 1
381 // CHECK3-NEXT:    store i32 [[TMP6]], ptr [[P_UPPERBOUND]], align 4
382 // CHECK3-NEXT:    store i32 1, ptr [[P_STRIDE]], align 4
383 // CHECK3-NEXT:    [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @1)
384 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4u(ptr @1, i32 [[OMP_GLOBAL_THREAD_NUM2]], i32 34, ptr [[P_LASTITER]], ptr [[P_LOWERBOUND]], ptr [[P_UPPERBOUND]], ptr [[P_STRIDE]], i32 1, i32 0)
385 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[P_LOWERBOUND]], align 4
386 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[P_UPPERBOUND]], align 4
387 // CHECK3-NEXT:    [[TMP9:%.*]] = sub i32 [[TMP8]], [[TMP7]]
388 // CHECK3-NEXT:    [[TMP10:%.*]] = add i32 [[TMP9]], 1
389 // CHECK3-NEXT:    br label [[OMP_LOOP_HEADER:%.*]]
390 // CHECK3:       omp_loop.header:
391 // CHECK3-NEXT:    [[OMP_LOOP_IV:%.*]] = phi i32 [ 0, [[OMP_LOOP_PREHEADER]] ], [ [[OMP_LOOP_NEXT:%.*]], [[OMP_LOOP_INC:%.*]] ]
392 // CHECK3-NEXT:    br label [[OMP_LOOP_COND:%.*]]
393 // CHECK3:       omp_loop.cond:
394 // CHECK3-NEXT:    [[OMP_LOOP_CMP:%.*]] = icmp ult i32 [[OMP_LOOP_IV]], [[TMP10]]
395 // CHECK3-NEXT:    br i1 [[OMP_LOOP_CMP]], label [[OMP_LOOP_BODY:%.*]], label [[OMP_LOOP_EXIT:%.*]]
396 // CHECK3:       omp_loop.exit:
397 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @1, i32 [[OMP_GLOBAL_THREAD_NUM2]])
398 // CHECK3-NEXT:    [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @1)
399 // CHECK3-NEXT:    call void @__kmpc_barrier(ptr @2, i32 [[OMP_GLOBAL_THREAD_NUM3]])
400 // CHECK3-NEXT:    br label [[OMP_LOOP_AFTER:%.*]]
401 // CHECK3:       omp_loop.after:
402 // CHECK3:       for.inc:
403 // CHECK3:       omp_loop.body:
404 // CHECK3-NEXT:    [[TMP12:%.*]] = add i32 [[OMP_LOOP_IV]], [[TMP7]]
405 // CHECK3-NEXT:    call void @__captured_stmt.1(ptr [[LOADGEP_K]], i32 [[TMP12]], ptr [[AGG_CAPTURED1]])
406 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[LOADGEP_K]], align 4
407 // CHECK3-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP13]], 1
408 // CHECK3-NEXT:    store i32 [[INC]], ptr [[LOADGEP_K]], align 4
409 // CHECK3-NEXT:    br label [[OMP_LOOP_INC]]
410 // CHECK3:       omp_loop.inc:
411 // CHECK3-NEXT:    [[OMP_LOOP_NEXT]] = add nuw i32 [[OMP_LOOP_IV]], 1
412 // CHECK3-NEXT:    br label [[OMP_LOOP_HEADER]]
413 // CHECK3:       omp.par.outlined.exit.exitStub:
414 // CHECK3-NEXT:    ret void
415 //
416 //
417 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt
418 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR3:[0-9]+]] {
419 // CHECK3-NEXT:  entry:
420 // CHECK3-NEXT:    [[DISTANCE_ADDR:%.*]] = alloca ptr, align 8
421 // CHECK3-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
422 // CHECK3-NEXT:    [[DOTSTART:%.*]] = alloca i32, align 4
423 // CHECK3-NEXT:    [[DOTSTOP:%.*]] = alloca i32, align 4
424 // CHECK3-NEXT:    [[DOTSTEP:%.*]] = alloca i32, align 4
425 // CHECK3-NEXT:    store ptr [[DISTANCE]], ptr [[DISTANCE_ADDR]], align 8
426 // CHECK3-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
427 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
428 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0
429 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
430 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
431 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[DOTSTART]], align 4
432 // CHECK3-NEXT:    store i32 5, ptr [[DOTSTOP]], align 4
433 // CHECK3-NEXT:    store i32 1, ptr [[DOTSTEP]], align 4
434 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTSTART]], align 4
435 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTSTOP]], align 4
436 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]]
437 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
438 // CHECK3:       cond.true:
439 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTSTOP]], align 4
440 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTSTART]], align 4
441 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[TMP7]]
442 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTSTEP]], align 4
443 // CHECK3-NEXT:    [[SUB1:%.*]] = sub i32 [[TMP8]], 1
444 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]]
445 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTSTEP]], align 4
446 // CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP9]]
447 // CHECK3-NEXT:    br label [[COND_END:%.*]]
448 // CHECK3:       cond.false:
449 // CHECK3-NEXT:    br label [[COND_END]]
450 // CHECK3:       cond.end:
451 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ]
452 // CHECK3-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8
453 // CHECK3-NEXT:    store i32 [[COND]], ptr [[TMP10]], align 4
454 // CHECK3-NEXT:    ret void
455 //
456 //
457 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt.1
458 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR3]] {
459 // CHECK3-NEXT:  entry:
460 // CHECK3-NEXT:    [[LOOPVAR_ADDR:%.*]] = alloca ptr, align 8
461 // CHECK3-NEXT:    [[LOGICAL_ADDR:%.*]] = alloca i32, align 4
462 // CHECK3-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
463 // CHECK3-NEXT:    store ptr [[LOOPVAR]], ptr [[LOOPVAR_ADDR]], align 8
464 // CHECK3-NEXT:    store i32 [[LOGICAL]], ptr [[LOGICAL_ADDR]], align 4
465 // CHECK3-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
466 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
467 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0
468 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
469 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4
470 // CHECK3-NEXT:    [[MUL:%.*]] = mul i32 1, [[TMP3]]
471 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]]
472 // CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8
473 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[TMP4]], align 4
474 // CHECK3-NEXT:    ret void
475 //
476 //
477 // CHECK3-LABEL: define {{[^@]+}}@_Z11inline_declv
478 // CHECK3-SAME: () #[[ATTR0]] {
479 // CHECK3-NEXT:  entry:
480 // CHECK3-NEXT:    [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
481 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
482 // CHECK3-NEXT:    [[RES:%.*]] = alloca i32, align 4
483 // CHECK3-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
484 // CHECK3-NEXT:    br label [[OMP_PARALLEL:%.*]]
485 // CHECK3:       omp_parallel:
486 // CHECK3-NEXT:    [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
487 // CHECK3-NEXT:    store ptr [[I]], ptr [[GEP_I]], align 8
488 // CHECK3-NEXT:    [[GEP_RES:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
489 // CHECK3-NEXT:    store ptr [[RES]], ptr [[GEP_RES]], align 8
490 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_Z11inline_declv..omp_par, ptr [[STRUCTARG]])
491 // CHECK3-NEXT:    br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
492 // CHECK3:       omp.par.outlined.exit:
493 // CHECK3-NEXT:    br label [[OMP_PAR_EXIT_SPLIT:%.*]]
494 // CHECK3:       omp.par.exit.split:
495 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RES]], align 4
496 // CHECK3-NEXT:    ret i32 [[TMP0]]
497 //
498 //
499 // CHECK3-LABEL: define {{[^@]+}}@_Z11inline_declv..omp_par
500 // CHECK3-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR1]] {
501 // CHECK3-NEXT:  omp.par.entry:
502 // CHECK3-NEXT:    [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 0
503 // CHECK3-NEXT:    [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
504 // CHECK3-NEXT:    [[GEP_RES:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 1
505 // CHECK3-NEXT:    [[LOADGEP_RES:%.*]] = load ptr, ptr [[GEP_RES]], align 8
506 // CHECK3-NEXT:    [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
507 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4
508 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4
509 // CHECK3-NEXT:    [[TID:%.*]] = load i32, ptr [[TID_ADDR_LOCAL]], align 4
510 // CHECK3-NEXT:    [[K:%.*]] = alloca i32, align 4
511 // CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8
512 // CHECK3-NEXT:    [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 4
513 // CHECK3-NEXT:    [[DOTCOUNT_ADDR:%.*]] = alloca i32, align 4
514 // CHECK3-NEXT:    [[P_LASTITER:%.*]] = alloca i32, align 4
515 // CHECK3-NEXT:    [[P_LOWERBOUND:%.*]] = alloca i32, align 4
516 // CHECK3-NEXT:    [[P_UPPERBOUND:%.*]] = alloca i32, align 4
517 // CHECK3-NEXT:    [[P_STRIDE:%.*]] = alloca i32, align 4
518 // CHECK3-NEXT:    br label [[OMP_PAR_REGION:%.*]]
519 // CHECK3:       omp.par.region:
520 // CHECK3:       for.cond:
521 // CHECK3:       for.end:
522 // CHECK3:       omp.par.region.parallel.after:
523 // CHECK3:       omp.par.pre_finalize:
524 // CHECK3:       for.body:
525 // CHECK3-NEXT:    store i32 0, ptr [[K]], align 4
526 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[AGG_CAPTURED]], i32 0, i32 0
527 // CHECK3-NEXT:    store ptr [[K]], ptr [[TMP3]], align 8
528 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED1]], i32 0, i32 0
529 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[K]], align 4
530 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP4]], align 4
531 // CHECK3-NEXT:    call void @__captured_stmt.2(ptr [[DOTCOUNT_ADDR]], ptr [[AGG_CAPTURED]])
532 // CHECK3-NEXT:    [[DOTCOUNT:%.*]] = load i32, ptr [[DOTCOUNT_ADDR]], align 4
533 // CHECK3-NEXT:    br label [[OMP_LOOP_PREHEADER:%.*]]
534 // CHECK3:       omp_loop.preheader:
535 // CHECK3:       omp_loop.header:
536 // CHECK3-NEXT:    [[OMP_LOOP_IV:%.*]] = phi i32 [ 0, [[OMP_LOOP_PREHEADER]] ], [ [[OMP_LOOP_NEXT:%.*]], [[OMP_LOOP_INC:%.*]] ]
537 // CHECK3-NEXT:    br label [[OMP_LOOP_COND:%.*]]
538 // CHECK3:       omp_loop.cond:
539 // CHECK3:       omp_loop.exit:
540 // CHECK3:       omp_loop.after:
541 // CHECK3:       for.inc:
542 // CHECK3:       omp_loop.body:
543 // CHECK3:       omp_loop.inc:
544 // CHECK3:       omp.par.outlined.exit.exitStub:
545 // CHECK3-NEXT:    ret void
546 //
547 //
548 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt.2
549 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR3]] {
550 // CHECK3-NEXT:  entry:
551 // CHECK3-NEXT:    [[DISTANCE_ADDR:%.*]] = alloca ptr, align 8
552 // CHECK3-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
553 // CHECK3-NEXT:    [[DOTSTART:%.*]] = alloca i32, align 4
554 // CHECK3-NEXT:    [[DOTSTOP:%.*]] = alloca i32, align 4
555 // CHECK3-NEXT:    [[DOTSTEP:%.*]] = alloca i32, align 4
556 // CHECK3-NEXT:    store ptr [[DISTANCE]], ptr [[DISTANCE_ADDR]], align 8
557 // CHECK3-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
558 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
559 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0
560 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
561 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
562 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[DOTSTART]], align 4
563 // CHECK3-NEXT:    store i32 5, ptr [[DOTSTOP]], align 4
564 // CHECK3-NEXT:    store i32 1, ptr [[DOTSTEP]], align 4
565 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTSTART]], align 4
566 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTSTOP]], align 4
567 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]]
568 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
569 // CHECK3:       cond.true:
570 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTSTOP]], align 4
571 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTSTART]], align 4
572 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[TMP7]]
573 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTSTEP]], align 4
574 // CHECK3-NEXT:    [[SUB1:%.*]] = sub i32 [[TMP8]], 1
575 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]]
576 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTSTEP]], align 4
577 // CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP9]]
578 // CHECK3-NEXT:    br label [[COND_END:%.*]]
579 // CHECK3:       cond.false:
580 // CHECK3-NEXT:    br label [[COND_END]]
581 // CHECK3:       cond.end:
582 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ]
583 // CHECK3-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8
584 // CHECK3-NEXT:    store i32 [[COND]], ptr [[TMP10]], align 4
585 // CHECK3-NEXT:    ret void
586 //
587 //
588 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt.3
589 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR3]] {
590 // CHECK3-NEXT:  entry:
591 // CHECK3-NEXT:    [[LOOPVAR_ADDR:%.*]] = alloca ptr, align 8
592 // CHECK3-NEXT:    [[LOGICAL_ADDR:%.*]] = alloca i32, align 4
593 // CHECK3-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
594 // CHECK3-NEXT:    store ptr [[LOOPVAR]], ptr [[LOOPVAR_ADDR]], align 8
595 // CHECK3-NEXT:    store i32 [[LOGICAL]], ptr [[LOGICAL_ADDR]], align 4
596 // CHECK3-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
597 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
598 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0
599 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
600 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4
601 // CHECK3-NEXT:    [[MUL:%.*]] = mul i32 1, [[TMP3]]
602 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]]
603 // CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8
604 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[TMP4]], align 4
605 // CHECK3-NEXT:    ret void
606 //
607 //
608 // CHECK4-LABEL: define {{[^@]+}}@_Z12outline_declv
609 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG8:![0-9]+]] {
610 // CHECK4-NEXT:  entry:
611 // CHECK4-NEXT:    [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
612 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
613 // CHECK4-NEXT:    [[K:%.*]] = alloca i32, align 4
614 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]]
615 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[K]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15]]
616 // CHECK4-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]), !dbg [[DBG17:![0-9]+]]
617 // CHECK4-NEXT:    br label [[OMP_PARALLEL:%.*]]
618 // CHECK4:       omp_parallel:
619 // CHECK4-NEXT:    [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
620 // CHECK4-NEXT:    store ptr [[I]], ptr [[GEP_I]], align 8
621 // CHECK4-NEXT:    [[GEP_K:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
622 // CHECK4-NEXT:    store ptr [[K]], ptr [[GEP_K]], align 8
623 // CHECK4-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_Z12outline_declv..omp_par, ptr [[STRUCTARG]]), !dbg [[DBG18:![0-9]+]]
624 // CHECK4-NEXT:    br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
625 // CHECK4:       omp.par.outlined.exit:
626 // CHECK4-NEXT:    br label [[OMP_PAR_EXIT_SPLIT:%.*]]
627 // CHECK4:       omp.par.exit.split:
628 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[K]], align 4, !dbg [[DBG20:![0-9]+]]
629 // CHECK4-NEXT:    ret i32 [[TMP0]], !dbg [[DBG20]]
630 //
631 //
632 // CHECK4-LABEL: define {{[^@]+}}@_Z12outline_declv..omp_par
633 // CHECK4-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] !dbg [[DBG21:![0-9]+]] {
634 // CHECK4-NEXT:  omp.par.entry:
635 // CHECK4-NEXT:    [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 0
636 // CHECK4-NEXT:    [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
637 // CHECK4-NEXT:    [[GEP_K:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 1
638 // CHECK4-NEXT:    [[LOADGEP_K:%.*]] = load ptr, ptr [[GEP_K]], align 8
639 // CHECK4-NEXT:    [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
640 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4
641 // CHECK4-NEXT:    store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4
642 // CHECK4-NEXT:    [[TID:%.*]] = load i32, ptr [[TID_ADDR_LOCAL]], align 4
643 // CHECK4-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
644 // CHECK4-NEXT:    [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 4
645 // CHECK4-NEXT:    [[DOTCOUNT_ADDR:%.*]] = alloca i32, align 4
646 // CHECK4-NEXT:    [[P_LASTITER:%.*]] = alloca i32, align 4
647 // CHECK4-NEXT:    [[P_LOWERBOUND:%.*]] = alloca i32, align 4
648 // CHECK4-NEXT:    [[P_UPPERBOUND:%.*]] = alloca i32, align 4
649 // CHECK4-NEXT:    [[P_STRIDE:%.*]] = alloca i32, align 4
650 // CHECK4-NEXT:    br label [[OMP_PAR_REGION:%.*]]
651 // CHECK4:       omp.par.region:
652 // CHECK4:       for.cond:
653 // CHECK4:       for.end:
654 // CHECK4:       omp.par.region.parallel.after:
655 // CHECK4:       omp.par.pre_finalize:
656 // CHECK4:       for.body:
657 // CHECK4:    store i32 0, ptr [[LOADGEP_K]], align 4, !dbg [[DBG28:![0-9]+]]
658 // CHECK4-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0, !dbg [[DBG28]]
659 // CHECK4-NEXT:    store ptr [[LOADGEP_K]], ptr [[TMP3]], align 8, !dbg [[DBG28]]
660 // CHECK4-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[AGG_CAPTURED1]], i32 0, i32 0, !dbg [[DBG28]]
661 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, ptr [[LOADGEP_K]], align 4, !dbg [[DBG32:![0-9]+]]
662 // CHECK4-NEXT:    store i32 [[TMP5]], ptr [[TMP4]], align 4, !dbg [[DBG28]]
663 // CHECK4-NEXT:    call void @__captured_stmt(ptr [[DOTCOUNT_ADDR]], ptr [[AGG_CAPTURED]]), !dbg [[DBG28]]
664 // CHECK4-NEXT:    [[DOTCOUNT:%.*]] = load i32, ptr [[DOTCOUNT_ADDR]], align 4, !dbg [[DBG28]]
665 // CHECK4-NEXT:    br label [[OMP_LOOP_PREHEADER:%.*]], !dbg [[DBG28]]
666 // CHECK4:       omp_loop.preheader:
667 // CHECK4-NEXT:    store i32 0, ptr [[P_LOWERBOUND]], align 4, !dbg [[DBG28]]
668 // CHECK4-NEXT:    [[TMP6:%.*]] = sub i32 [[DOTCOUNT]], 1, !dbg [[DBG28]]
669 // CHECK4-NEXT:    store i32 [[TMP6]], ptr [[P_UPPERBOUND]], align 4, !dbg [[DBG28]]
670 // CHECK4-NEXT:    store i32 1, ptr [[P_STRIDE]], align 4, !dbg [[DBG28]]
671 // CHECK4-NEXT:    [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @3), !dbg [[DBG28]]
672 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4u(ptr @3, i32 [[OMP_GLOBAL_THREAD_NUM2]], i32 34, ptr [[P_LASTITER]], ptr [[P_LOWERBOUND]], ptr [[P_UPPERBOUND]], ptr [[P_STRIDE]], i32 1, i32 0), !dbg [[DBG28]]
673 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, ptr [[P_LOWERBOUND]], align 4, !dbg [[DBG28]]
674 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, ptr [[P_UPPERBOUND]], align 4, !dbg [[DBG28]]
675 // CHECK4-NEXT:    [[TMP9:%.*]] = sub i32 [[TMP8]], [[TMP7]], !dbg [[DBG28]]
676 // CHECK4-NEXT:    [[TMP10:%.*]] = add i32 [[TMP9]], 1, !dbg [[DBG28]]
677 // CHECK4-NEXT:    br label [[OMP_LOOP_HEADER:%.*]], !dbg [[DBG28]]
678 // CHECK4:       omp_loop.header:
679 // CHECK4:       omp_loop.cond:
680 // CHECK4:       omp_loop.exit:
681 // CHECK4:         call void @__kmpc_for_static_fini(ptr @3, i32 [[OMP_GLOBAL_THREAD_NUM2]]), !dbg [[DBG28]]
682 // CHECK4-NEXT:    [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @3), !dbg [[DBG33:![0-9]+]]
683 // CHECK4-NEXT:    call void @__kmpc_barrier(ptr @4, i32 [[OMP_GLOBAL_THREAD_NUM3]]), !dbg [[DBG33]]
684 // CHECK4-NEXT:    br label [[OMP_LOOP_AFTER:%.*]], !dbg [[DBG28]]
685 // CHECK4:       omp_loop.after:
686 // CHECK4:       for.inc:
687 // CHECK4:       omp_loop.body:
688 // CHECK4:       omp_loop.inc:
689 // CHECK4:       omp.par.outlined.exit.exitStub:
690 // CHECK4-NEXT:    ret void
691 //
692 //
693 // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt
694 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR4:[0-9]+]] !dbg [[DBG38:![0-9]+]] {
695 // CHECK4-NEXT:  entry:
696 // CHECK4-NEXT:    [[DISTANCE_ADDR:%.*]] = alloca ptr, align 8
697 // CHECK4-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
698 // CHECK4-NEXT:    [[DOTSTART:%.*]] = alloca i32, align 4
699 // CHECK4-NEXT:    [[DOTSTOP:%.*]] = alloca i32, align 4
700 // CHECK4-NEXT:    [[DOTSTEP:%.*]] = alloca i32, align 4
701 // CHECK4-NEXT:    store ptr [[DISTANCE]], ptr [[DISTANCE_ADDR]], align 8
702 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DISTANCE_ADDR]], metadata [[META47:![0-9]+]], metadata !DIExpression()), !dbg [[DBG48:![0-9]+]]
703 // CHECK4-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
704 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[__CONTEXT_ADDR]], metadata [[META49:![0-9]+]], metadata !DIExpression()), !dbg [[DBG48]]
705 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
706 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTSTART]], metadata [[META50:![0-9]+]], metadata !DIExpression()), !dbg [[DBG52:![0-9]+]]
707 // CHECK4-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG53:![0-9]+]]
708 // CHECK4-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG53]]
709 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG53]]
710 // CHECK4-NEXT:    store i32 [[TMP3]], ptr [[DOTSTART]], align 4, !dbg [[DBG52]]
711 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTSTOP]], metadata [[META55:![0-9]+]], metadata !DIExpression()), !dbg [[DBG56:![0-9]+]]
712 // CHECK4-NEXT:    store i32 5, ptr [[DOTSTOP]], align 4, !dbg [[DBG56]]
713 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTSTEP]], metadata [[META57:![0-9]+]], metadata !DIExpression()), !dbg [[DBG56]]
714 // CHECK4-NEXT:    store i32 1, ptr [[DOTSTEP]], align 4, !dbg [[DBG56]]
715 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTSTART]], align 4, !dbg [[DBG56]]
716 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTSTOP]], align 4, !dbg [[DBG56]]
717 // CHECK4-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]], !dbg [[DBG56]]
718 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG56]]
719 // CHECK4:       cond.true:
720 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTSTOP]], align 4, !dbg [[DBG56]]
721 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTSTART]], align 4, !dbg [[DBG56]]
722 // CHECK4-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[TMP7]], !dbg [[DBG56]]
723 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTSTEP]], align 4, !dbg [[DBG56]]
724 // CHECK4-NEXT:    [[SUB1:%.*]] = sub i32 [[TMP8]], 1, !dbg [[DBG56]]
725 // CHECK4-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]], !dbg [[DBG56]]
726 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTSTEP]], align 4, !dbg [[DBG56]]
727 // CHECK4-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP9]], !dbg [[DBG56]]
728 // CHECK4-NEXT:    br label [[COND_END:%.*]], !dbg [[DBG56]]
729 // CHECK4:       cond.false:
730 // CHECK4-NEXT:    br label [[COND_END]], !dbg [[DBG56]]
731 // CHECK4:       cond.end:
732 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ], !dbg [[DBG56]]
733 // CHECK4-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8, !dbg [[DBG56]]
734 // CHECK4-NEXT:    store i32 [[COND]], ptr [[TMP10]], align 4, !dbg [[DBG56]]
735 // CHECK4-NEXT:    ret void, !dbg [[DBG58:![0-9]+]]
736 //
737 //
738 // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt.1
739 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR4]] !dbg [[DBG60:![0-9]+]] {
740 // CHECK4-NEXT:  entry:
741 // CHECK4-NEXT:    [[LOOPVAR_ADDR:%.*]] = alloca ptr, align 8
742 // CHECK4-NEXT:    [[LOGICAL_ADDR:%.*]] = alloca i32, align 4
743 // CHECK4-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
744 // CHECK4-NEXT:    store ptr [[LOOPVAR]], ptr [[LOOPVAR_ADDR]], align 8
745 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[LOOPVAR_ADDR]], metadata [[META68:![0-9]+]], metadata !DIExpression()), !dbg [[DBG69:![0-9]+]]
746 // CHECK4-NEXT:    store i32 [[LOGICAL]], ptr [[LOGICAL_ADDR]], align 4
747 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[LOGICAL_ADDR]], metadata [[META70:![0-9]+]], metadata !DIExpression()), !dbg [[DBG69]]
748 // CHECK4-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
749 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[__CONTEXT_ADDR]], metadata [[META71:![0-9]+]], metadata !DIExpression()), !dbg [[DBG69]]
750 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
751 // CHECK4-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG72:![0-9]+]]
752 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4, !dbg [[DBG72]]
753 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4, !dbg [[DBG74:![0-9]+]]
754 // CHECK4-NEXT:    [[MUL:%.*]] = mul i32 1, [[TMP3]], !dbg [[DBG74]]
755 // CHECK4-NEXT:    [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]], !dbg [[DBG74]]
756 // CHECK4-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8, !dbg [[DBG74]]
757 // CHECK4-NEXT:    store i32 [[ADD]], ptr [[TMP4]], align 4, !dbg [[DBG69]]
758 // CHECK4-NEXT:    ret void, !dbg [[DBG72]]
759 //
760 //
761 // CHECK4-LABEL: define {{[^@]+}}@_Z11inline_declv
762 // CHECK4-SAME: () #[[ATTR0]] !dbg [[DBG77:![0-9]+]] {
763 // CHECK4-NEXT:  entry:
764 // CHECK4-NEXT:    [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
765 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
766 // CHECK4-NEXT:    [[RES:%.*]] = alloca i32, align 4
767 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META78:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79:![0-9]+]]
768 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META80:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79]]
769 // CHECK4-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]), !dbg [[DBG81:![0-9]+]]
770 // CHECK4-NEXT:    br label [[OMP_PARALLEL:%.*]]
771 // CHECK4:       omp_parallel:
772 // CHECK4-NEXT:    [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
773 // CHECK4-NEXT:    store ptr [[I]], ptr [[GEP_I]], align 8
774 // CHECK4-NEXT:    [[GEP_RES:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
775 // CHECK4-NEXT:    store ptr [[RES]], ptr [[GEP_RES]], align 8
776 // CHECK4-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @_Z11inline_declv..omp_par, ptr [[STRUCTARG]]), !dbg [[DBG82:![0-9]+]]
777 // CHECK4-NEXT:    br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
778 // CHECK4:       omp.par.outlined.exit:
779 // CHECK4-NEXT:    br label [[OMP_PAR_EXIT_SPLIT:%.*]]
780 // CHECK4:       omp.par.exit.split:
781 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG84:![0-9]+]]
782 // CHECK4-NEXT:    ret i32 [[TMP0]], !dbg [[DBG84]]
783 //
784 //
785 // CHECK4-LABEL: define {{[^@]+}}@_Z11inline_declv..omp_par
786 // CHECK4-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG85:![0-9]+]] {
787 // CHECK4-NEXT:  omp.par.entry:
788 // CHECK4-NEXT:    [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 0
789 // CHECK4-NEXT:    [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
790 // CHECK4-NEXT:    [[GEP_RES:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 1
791 // CHECK4-NEXT:    [[LOADGEP_RES:%.*]] = load ptr, ptr [[GEP_RES]], align 8
792 // CHECK4-NEXT:    [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
793 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4
794 // CHECK4-NEXT:    store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4
795 // CHECK4-NEXT:    [[TID:%.*]] = load i32, ptr [[TID_ADDR_LOCAL]], align 4
796 // CHECK4-NEXT:    [[K:%.*]] = alloca i32, align 4
797 // CHECK4-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8
798 // CHECK4-NEXT:    [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 4
799 // CHECK4-NEXT:    [[DOTCOUNT_ADDR:%.*]] = alloca i32, align 4
800 // CHECK4-NEXT:    [[P_LASTITER:%.*]] = alloca i32, align 4
801 // CHECK4-NEXT:    [[P_LOWERBOUND:%.*]] = alloca i32, align 4
802 // CHECK4-NEXT:    [[P_UPPERBOUND:%.*]] = alloca i32, align 4
803 // CHECK4-NEXT:    [[P_STRIDE:%.*]] = alloca i32, align 4
804 // CHECK4-NEXT:    br label [[OMP_PAR_REGION:%.*]]
805 // CHECK4:       omp.par.region:
806 // CHECK4:       for.cond:
807 // CHECK4:       for.end:
808 // CHECK4:       omp.par.region.parallel.after:
809 // CHECK4:       omp.par.pre_finalize:
810 // CHECK4:       for.body:
811 // CHECK4:         store i32 [[TMP5]], ptr [[TMP4]], align 4, !dbg [[DBG95:![0-9]+]]
812 // CHECK4-NEXT:    call void @__captured_stmt.2(ptr [[DOTCOUNT_ADDR]], ptr [[AGG_CAPTURED]]), !dbg [[DBG95]]
813 // CHECK4:       omp_loop.preheader:
814 // CHECK4:       omp_loop.header:
815 // CHECK4:       omp_loop.cond:
816 // CHECK4:       omp_loop.exit:
817 // CHECK4:       omp_loop.after:
818 // CHECK4:       for.inc:
819 // CHECK4:       omp_loop.body:
820 // CHECK4-NEXT:    [[TMP12:%.*]] = add i32 [[OMP_LOOP_IV:%.*]], [[TMP7:%.*]], !dbg [[DBG98:![-9]+]]
821 // CHECK4:         call void @__captured_stmt.3(ptr [[K]], i32 [[TMP12]], ptr [[AGG_CAPTURED1]]), !dbg [[DBG96:![0-9]+]]
822 // CHECK4:       omp_loop.inc:
823 // CHECK4:       omp.par.outlined.exit.exitStub:
824 // CHECK4-NEXT:    ret void
825 //
826 //
827 // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt.2
828 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR4]] !dbg [[DBG101:![0-9]+]] {
829 // CHECK4-NEXT:  entry:
830 // CHECK4-NEXT:    [[DISTANCE_ADDR:%.*]] = alloca ptr, align 8
831 // CHECK4-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
832 // CHECK4-NEXT:    [[DOTSTART:%.*]] = alloca i32, align 4
833 // CHECK4-NEXT:    [[DOTSTOP:%.*]] = alloca i32, align 4
834 // CHECK4-NEXT:    [[DOTSTEP:%.*]] = alloca i32, align 4
835 // CHECK4-NEXT:    store ptr [[DISTANCE]], ptr [[DISTANCE_ADDR]], align 8
836 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DISTANCE_ADDR]], metadata [[META102:![0-9]+]], metadata !DIExpression()), !dbg [[DBG103:![0-9]+]]
837 // CHECK4-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
838 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[__CONTEXT_ADDR]], metadata [[META104:![0-9]+]], metadata !DIExpression()), !dbg [[DBG103]]
839 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
840 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTSTART]], metadata [[META105:![0-9]+]], metadata !DIExpression()), !dbg [[DBG107:![0-9]+]]
841 // CHECK4-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG108:![0-9]+]]
842 // CHECK4-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG108]]
843 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG108]]
844 // CHECK4-NEXT:    store i32 [[TMP3]], ptr [[DOTSTART]], align 4, !dbg [[DBG107]]
845 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTSTOP]], metadata [[META110:![0-9]+]], metadata !DIExpression()), !dbg [[DBG111:![0-9]+]]
846 // CHECK4-NEXT:    store i32 5, ptr [[DOTSTOP]], align 4, !dbg [[DBG111]]
847 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTSTEP]], metadata [[META112:![0-9]+]], metadata !DIExpression()), !dbg [[DBG111]]
848 // CHECK4-NEXT:    store i32 1, ptr [[DOTSTEP]], align 4, !dbg [[DBG111]]
849 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTSTART]], align 4, !dbg [[DBG111]]
850 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTSTOP]], align 4, !dbg [[DBG111]]
851 // CHECK4-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]], !dbg [[DBG111]]
852 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG111]]
853 // CHECK4:       cond.true:
854 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTSTOP]], align 4, !dbg [[DBG111]]
855 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTSTART]], align 4, !dbg [[DBG111]]
856 // CHECK4-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[TMP7]], !dbg [[DBG111]]
857 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTSTEP]], align 4, !dbg [[DBG111]]
858 // CHECK4-NEXT:    [[SUB1:%.*]] = sub i32 [[TMP8]], 1, !dbg [[DBG111]]
859 // CHECK4-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]], !dbg [[DBG111]]
860 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTSTEP]], align 4, !dbg [[DBG111]]
861 // CHECK4-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP9]], !dbg [[DBG111]]
862 // CHECK4-NEXT:    br label [[COND_END:%.*]], !dbg [[DBG111]]
863 // CHECK4:       cond.false:
864 // CHECK4-NEXT:    br label [[COND_END]], !dbg [[DBG111]]
865 // CHECK4:       cond.end:
866 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ], !dbg [[DBG111]]
867 // CHECK4-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8, !dbg [[DBG111]]
868 // CHECK4-NEXT:    store i32 [[COND]], ptr [[TMP10]], align 4, !dbg [[DBG111]]
869 // CHECK4-NEXT:    ret void, !dbg [[DBG113:![0-9]+]]
870 //
871 //
872 // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt.3
873 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR4]] !dbg [[DBG115:![0-9]+]] {
874 // CHECK4-NEXT:  entry:
875 // CHECK4-NEXT:    [[LOOPVAR_ADDR:%.*]] = alloca ptr, align 8
876 // CHECK4-NEXT:    [[LOGICAL_ADDR:%.*]] = alloca i32, align 4
877 // CHECK4-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
878 // CHECK4-NEXT:    store ptr [[LOOPVAR]], ptr [[LOOPVAR_ADDR]], align 8
879 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[LOOPVAR_ADDR]], metadata [[META116:![0-9]+]], metadata !DIExpression()), !dbg [[DBG117:![0-9]+]]
880 // CHECK4-NEXT:    store i32 [[LOGICAL]], ptr [[LOGICAL_ADDR]], align 4
881 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[LOGICAL_ADDR]], metadata [[META118:![0-9]+]], metadata !DIExpression()), !dbg [[DBG117]]
882 // CHECK4-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
883 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[__CONTEXT_ADDR]], metadata [[META119:![0-9]+]], metadata !DIExpression()), !dbg [[DBG117]]
884 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
885 // CHECK4-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG120:![0-9]+]]
886 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4, !dbg [[DBG120]]
887 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4, !dbg [[DBG122:![0-9]+]]
888 // CHECK4-NEXT:    [[MUL:%.*]] = mul i32 1, [[TMP3]], !dbg [[DBG122]]
889 // CHECK4-NEXT:    [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]], !dbg [[DBG122]]
890 // CHECK4-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8, !dbg [[DBG122]]
891 // CHECK4-NEXT:    store i32 [[ADD]], ptr [[TMP4]], align 4, !dbg [[DBG117]]
892 // CHECK4-NEXT:    ret void, !dbg [[DBG120]]
893 //
894