1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 5 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -gno-column-info -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 9 10 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 12 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 // expected-no-diagnostics 17 #ifndef HEADER 18 #define HEADER 19 20 int outline_decl() { 21 int i, k; 22 #pragma omp parallel 23 for(i=0; i<10; i++) { 24 #pragma omp loop 25 for(k=0; k<5; k++) { 26 k++; 27 } 28 } 29 return k; 30 } 31 32 int inline_decl() { 33 int i, res; 34 #pragma omp parallel 35 for(i=0; i<10; i++) { 36 #pragma omp loop 37 for(int k=0; k<5; k++) { 38 res++; 39 } 40 } 41 return res; 42 } 43 44 #endif 45 // CHECK1-NEXT [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 46 // CHECK1-NEXT [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 47 // CHECK1-NEXT call void @__kmpc_for_static_init_4(ptr @1, i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 48 //CHECK1 cond.end: 49 //CHECK1 omp.inner.for.cond: 50 //CHECK1 omp.inner.for.body: 51 //CHECK1 omp.body.continue: 52 //CHECK1 omp.inner.for.inc: 53 //CHECK1 omp.inner.for.end: 54 //CHECK1 omp.loop.exit: 55 // CHECK1-NEXT [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 56 // CHECK1-NEXT [[TMP14:%.*]] = load i32, ptr [[TMP12]], align 4 57 // CHECK1-NEXT call void @__kmpc_for_static_fini(ptr @1, i32 [[TMP14]]) 58 // CHECK1-NEXT [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 59 // CHECK1-NEXT [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 60 // CHECK1-NEXT call void @__kmpc_barrier(ptr @2, i32 [[TMP16]]) 61 //CHECK1 for.inc: 62 //CHECK1 for.end: 63 // CHECK1-NEXT ret void 64 // CHECK2-NEXT br label [[FOR_INC]], !dbg !119 65 // CHECK1-LABEL: define {{[^@]+}}@_Z12outline_declv 66 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 67 // CHECK1-NEXT: entry: 68 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 69 // CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4 70 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 1, ptr @_Z12outline_declv.omp_outlined, ptr [[I]]) 71 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[K]], align 4 72 // CHECK1-NEXT: ret i32 [[TMP0]] 73 // 74 // 75 // CHECK1-LABEL: define {{[^@]+}}@_Z12outline_declv.omp_outlined 76 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { 77 // CHECK1-NEXT: entry: 78 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 79 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 80 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8 81 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 82 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 83 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 84 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 85 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 86 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 87 // CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4 88 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 89 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 90 // CHECK1-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 8 91 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8 92 // CHECK1-NEXT: store i32 0, ptr [[TMP0]], align 4 93 // CHECK1-NEXT: br label [[FOR_COND:%.*]] 94 // CHECK1: for.cond: 95 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 96 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10 97 // CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 98 // CHECK1: for.body: 99 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 100 // CHECK1-NEXT: store i32 4, ptr [[DOTOMP_UB]], align 4 101 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 102 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 103 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 104 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 105 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 106 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 107 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP4]], 4 108 // CHECK1-NEXT: br i1 [[CMP1]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 109 // CHECK1: cond.true: 110 // CHECK1-NEXT: br label [[COND_END:%.*]] 111 // CHECK1: cond.false: 112 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 113 // CHECK1-NEXT: br label [[COND_END]] 114 // CHECK1: cond.end: 115 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 116 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 117 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 118 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 119 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 120 // CHECK1: omp.inner.for.cond: 121 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 122 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 123 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 124 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 125 // CHECK1: omp.inner.for.body: 126 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 127 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 128 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 129 // CHECK1-NEXT: store i32 [[ADD]], ptr [[K]], align 4 130 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[K]], align 4 131 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 132 // CHECK1-NEXT: store i32 [[INC]], ptr [[K]], align 4 133 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 134 // CHECK1: omp.body.continue: 135 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 136 // CHECK1: omp.inner.for.inc: 137 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 138 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 139 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 140 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 141 // CHECK1: omp.inner.for.end: 142 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 143 // CHECK1: omp.loop.exit: 144 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 145 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4 146 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP13]]) 147 // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 148 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 149 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP15]]) 150 // CHECK1-NEXT: br label [[FOR_INC:%.*]] 151 // CHECK1: for.inc: 152 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 153 // CHECK1-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP16]], 1 154 // CHECK1-NEXT: store i32 [[INC4]], ptr [[TMP0]], align 4 155 // CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 156 // CHECK1: for.end: 157 // CHECK1-NEXT: ret void 158 // 159 // 160 // CHECK1-LABEL: define {{[^@]+}}@_Z11inline_declv 161 // CHECK1-SAME: () #[[ATTR0]] { 162 // CHECK1-NEXT: entry: 163 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 164 // CHECK1-NEXT: [[RES:%.*]] = alloca i32, align 4 165 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @_Z11inline_declv.omp_outlined, ptr [[I]], ptr [[RES]]) 166 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[RES]], align 4 167 // CHECK1-NEXT: ret i32 [[TMP0]] 168 // 169 // 170 // CHECK1-LABEL: define {{[^@]+}}@_Z11inline_declv.omp_outlined 171 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RES:%.*]]) #[[ATTR1]] { 172 // CHECK1-NEXT: entry: 173 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 174 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 175 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8 176 // CHECK1-NEXT: [[RES_ADDR:%.*]] = alloca ptr, align 8 177 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 178 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 179 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 180 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 181 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 182 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 183 // CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4 184 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 185 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 186 // CHECK1-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 8 187 // CHECK1-NEXT: store ptr [[RES]], ptr [[RES_ADDR]], align 8 188 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8 189 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RES_ADDR]], align 8 190 // CHECK1-NEXT: store i32 0, ptr [[TMP0]], align 4 191 // CHECK1-NEXT: br label [[FOR_COND:%.*]] 192 // CHECK1: for.cond: 193 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4 194 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 10 195 // CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 196 // CHECK1: for.body: 197 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 198 // CHECK1-NEXT: store i32 4, ptr [[DOTOMP_UB]], align 4 199 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 200 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 201 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 202 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 203 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 204 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 205 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP5]], 4 206 // CHECK1-NEXT: br i1 [[CMP1]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 207 // CHECK1: cond.true: 208 // CHECK1-NEXT: br label [[COND_END:%.*]] 209 // CHECK1: cond.false: 210 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 211 // CHECK1-NEXT: br label [[COND_END]] 212 // CHECK1: cond.end: 213 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 214 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 215 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 216 // CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 217 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 218 // CHECK1: omp.inner.for.cond: 219 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 220 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 221 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 222 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 223 // CHECK1: omp.inner.for.body: 224 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 225 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 226 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 227 // CHECK1-NEXT: store i32 [[ADD]], ptr [[K]], align 4 228 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP1]], align 4 229 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 230 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4 231 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 232 // CHECK1: omp.body.continue: 233 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 234 // CHECK1: omp.inner.for.inc: 235 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 236 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 237 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 238 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 239 // CHECK1: omp.inner.for.end: 240 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 241 // CHECK1: omp.loop.exit: 242 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 243 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 244 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 245 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 246 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 247 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP16]]) 248 // CHECK1-NEXT: br label [[FOR_INC:%.*]] 249 // CHECK1: for.inc: 250 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP0]], align 4 251 // CHECK1-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP17]], 1 252 // CHECK1-NEXT: store i32 [[INC4]], ptr [[TMP0]], align 4 253 // CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 254 // CHECK1: for.end: 255 // CHECK1-NEXT: ret void 256 // 257 // 258 // CHECK2-LABEL: define {{[^@]+}}@_Z12outline_declv 259 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { 260 // CHECK2-NEXT: entry: 261 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 262 // CHECK2-NEXT: [[K:%.*]] = alloca i32, align 4 263 // CHECK2-NEXT: #dbg_declare(ptr [[I]], [[META12:![0-9]+]], !DIExpression(), [[META13:![0-9]+]]) 264 // CHECK2-NEXT: #dbg_declare(ptr [[K]], [[META14:![0-9]+]], !DIExpression(), [[META15:![0-9]+]]) 265 // CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB6:[0-9]+]], i32 1, ptr @_Z12outline_declv.omp_outlined, ptr [[I]]), !dbg [[DBG16:![0-9]+]] 266 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[K]], align 4, !dbg [[DBG17:![0-9]+]] 267 // CHECK2-NEXT: ret i32 [[TMP0]], !dbg [[DBG18:![0-9]+]] 268 // 269 // 270 // CHECK2-LABEL: define {{[^@]+}}@_Z12outline_declv.omp_outlined_debug__ 271 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] !dbg [[DBG19:![0-9]+]] { 272 // CHECK2-NEXT: entry: 273 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 274 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 275 // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8 276 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 277 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 278 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 279 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 280 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 281 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 282 // CHECK2-NEXT: [[K:%.*]] = alloca i32, align 4 283 // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 284 // CHECK2-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META27:![0-9]+]], !DIExpression(), [[META28:![0-9]+]]) 285 // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 286 // CHECK2-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META29:![0-9]+]], !DIExpression(), [[META28]]) 287 // CHECK2-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 8 288 // CHECK2-NEXT: #dbg_declare(ptr [[I_ADDR]], [[META30:![0-9]+]], !DIExpression(), [[META31:![0-9]+]]) 289 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !dbg [[DBG32:![0-9]+]] 290 // CHECK2-NEXT: store i32 0, ptr [[TMP0]], align 4, !dbg [[DBG33:![0-9]+]] 291 // CHECK2-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG35:![0-9]+]] 292 // CHECK2: for.cond: 293 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG36:![0-9]+]] 294 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10, !dbg [[DBG38:![0-9]+]] 295 // CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG39:![0-9]+]] 296 // CHECK2: for.body: 297 // CHECK2-NEXT: #dbg_declare(ptr [[DOTOMP_IV]], [[META40:![0-9]+]], !DIExpression(), [[META43:![0-9]+]]) 298 // CHECK2-NEXT: #dbg_declare(ptr [[DOTOMP_LB]], [[META44:![0-9]+]], !DIExpression(), [[META43]]) 299 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG45:![0-9]+]] 300 // CHECK2-NEXT: #dbg_declare(ptr [[DOTOMP_UB]], [[META46:![0-9]+]], !DIExpression(), [[META43]]) 301 // CHECK2-NEXT: store i32 4, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG45]] 302 // CHECK2-NEXT: #dbg_declare(ptr [[DOTOMP_STRIDE]], [[META47:![0-9]+]], !DIExpression(), [[META43]]) 303 // CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG45]] 304 // CHECK2-NEXT: #dbg_declare(ptr [[DOTOMP_IS_LAST]], [[META48:![0-9]+]], !DIExpression(), [[META43]]) 305 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG45]] 306 // CHECK2-NEXT: #dbg_declare(ptr [[K]], [[META49:![0-9]+]], !DIExpression(), [[META43]]) 307 // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG50:![0-9]+]] 308 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG50]] 309 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG51:![0-9]+]] 310 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG45]] 311 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP4]], 4, !dbg [[DBG45]] 312 // CHECK2-NEXT: br i1 [[CMP1]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG45]] 313 // CHECK2: cond.true: 314 // CHECK2-NEXT: br label [[COND_END:%.*]], !dbg [[DBG45]] 315 // CHECK2: cond.false: 316 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG45]] 317 // CHECK2-NEXT: br label [[COND_END]], !dbg [[DBG45]] 318 // CHECK2: cond.end: 319 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ], !dbg [[DBG45]] 320 // CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG45]] 321 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG45]] 322 // CHECK2-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG45]] 323 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG50]] 324 // CHECK2: omp.inner.for.cond: 325 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG45]] 326 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG45]] 327 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]], !dbg [[DBG52:![0-9]+]] 328 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG50]] 329 // CHECK2: omp.inner.for.body: 330 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG45]] 331 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1, !dbg [[DBG53:![0-9]+]] 332 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG53]] 333 // CHECK2-NEXT: store i32 [[ADD]], ptr [[K]], align 4, !dbg [[DBG53]] 334 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[K]], align 4, !dbg [[DBG54:![0-9]+]] 335 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1, !dbg [[DBG54]] 336 // CHECK2-NEXT: store i32 [[INC]], ptr [[K]], align 4, !dbg [[DBG54]] 337 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG56:![0-9]+]] 338 // CHECK2: omp.body.continue: 339 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG51]] 340 // CHECK2: omp.inner.for.inc: 341 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG45]] 342 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1, !dbg [[DBG52]] 343 // CHECK2-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG52]] 344 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG51]], !llvm.loop [[LOOP57:![0-9]+]] 345 // CHECK2: omp.inner.for.end: 346 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG51]] 347 // CHECK2: omp.loop.exit: 348 // CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG51]] 349 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG51]] 350 // CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3:[0-9]+]], i32 [[TMP13]]), !dbg [[DBG58:![0-9]+]] 351 // CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG58]] 352 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4, !dbg [[DBG58]] 353 // CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[TMP15]]), !dbg [[DBG58]] 354 // CHECK2-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG59:![0-9]+]] 355 // CHECK2: for.inc: 356 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG60:![0-9]+]] 357 // CHECK2-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP16]], 1, !dbg [[DBG60]] 358 // CHECK2-NEXT: store i32 [[INC4]], ptr [[TMP0]], align 4, !dbg [[DBG60]] 359 // CHECK2-NEXT: br label [[FOR_COND]], !dbg [[DBG61:![0-9]+]], !llvm.loop [[LOOP62:![0-9]+]] 360 // CHECK2: for.end: 361 // CHECK2-NEXT: ret void, !dbg [[DBG65:![0-9]+]] 362 // 363 // 364 // CHECK2-LABEL: define {{[^@]+}}@_Z12outline_declv.omp_outlined 365 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] !dbg [[DBG66:![0-9]+]] { 366 // CHECK2-NEXT: entry: 367 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 368 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 369 // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8 370 // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 371 // CHECK2-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META67:![0-9]+]], !DIExpression(), [[META68:![0-9]+]]) 372 // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 373 // CHECK2-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META69:![0-9]+]], !DIExpression(), [[META68]]) 374 // CHECK2-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 8 375 // CHECK2-NEXT: #dbg_declare(ptr [[I_ADDR]], [[META70:![0-9]+]], !DIExpression(), [[META68]]) 376 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !dbg [[DBG71:![0-9]+]] 377 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG71]] 378 // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG71]] 379 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !dbg [[DBG71]] 380 // CHECK2-NEXT: call void @_Z12outline_declv.omp_outlined_debug__(ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR2:[0-9]+]], !dbg [[DBG71]] 381 // CHECK2-NEXT: ret void, !dbg [[DBG71]] 382 // 383 // 384 // CHECK2-LABEL: define {{[^@]+}}@_Z11inline_declv 385 // CHECK2-SAME: () #[[ATTR0]] !dbg [[DBG74:![0-9]+]] { 386 // CHECK2-NEXT: entry: 387 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 388 // CHECK2-NEXT: [[RES:%.*]] = alloca i32, align 4 389 // CHECK2-NEXT: #dbg_declare(ptr [[I]], [[META75:![0-9]+]], !DIExpression(), [[META76:![0-9]+]]) 390 // CHECK2-NEXT: #dbg_declare(ptr [[RES]], [[META77:![0-9]+]], !DIExpression(), [[META78:![0-9]+]]) 391 // CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB13:[0-9]+]], i32 2, ptr @_Z11inline_declv.omp_outlined, ptr [[I]], ptr [[RES]]), !dbg [[DBG79:![0-9]+]] 392 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG80:![0-9]+]] 393 // CHECK2-NEXT: ret i32 [[TMP0]], !dbg [[DBG81:![0-9]+]] 394 // 395 // 396 // CHECK2-LABEL: define {{[^@]+}}@_Z11inline_declv.omp_outlined_debug__ 397 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RES:%.*]]) #[[ATTR1]] !dbg [[DBG82:![0-9]+]] { 398 // CHECK2-NEXT: entry: 399 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 400 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 401 // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8 402 // CHECK2-NEXT: [[RES_ADDR:%.*]] = alloca ptr, align 8 403 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 404 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 405 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 406 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 407 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 408 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 409 // CHECK2-NEXT: [[K:%.*]] = alloca i32, align 4 410 // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 411 // CHECK2-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META85:![0-9]+]], !DIExpression(), [[META86:![0-9]+]]) 412 // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 413 // CHECK2-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META87:![0-9]+]], !DIExpression(), [[META86]]) 414 // CHECK2-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 8 415 // CHECK2-NEXT: #dbg_declare(ptr [[I_ADDR]], [[META88:![0-9]+]], !DIExpression(), [[META89:![0-9]+]]) 416 // CHECK2-NEXT: store ptr [[RES]], ptr [[RES_ADDR]], align 8 417 // CHECK2-NEXT: #dbg_declare(ptr [[RES_ADDR]], [[META90:![0-9]+]], !DIExpression(), [[META91:![0-9]+]]) 418 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !dbg [[DBG92:![0-9]+]] 419 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RES_ADDR]], align 8, !dbg [[DBG92]] 420 // CHECK2-NEXT: store i32 0, ptr [[TMP0]], align 4, !dbg [[DBG93:![0-9]+]] 421 // CHECK2-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG95:![0-9]+]] 422 // CHECK2: for.cond: 423 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG96:![0-9]+]] 424 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 10, !dbg [[DBG98:![0-9]+]] 425 // CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG99:![0-9]+]] 426 // CHECK2: for.body: 427 // CHECK2-NEXT: #dbg_declare(ptr [[DOTOMP_IV]], [[META100:![0-9]+]], !DIExpression(), [[META103:![0-9]+]]) 428 // CHECK2-NEXT: #dbg_declare(ptr [[DOTOMP_LB]], [[META104:![0-9]+]], !DIExpression(), [[META103]]) 429 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG105:![0-9]+]] 430 // CHECK2-NEXT: #dbg_declare(ptr [[DOTOMP_UB]], [[META106:![0-9]+]], !DIExpression(), [[META103]]) 431 // CHECK2-NEXT: store i32 4, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG105]] 432 // CHECK2-NEXT: #dbg_declare(ptr [[DOTOMP_STRIDE]], [[META107:![0-9]+]], !DIExpression(), [[META103]]) 433 // CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG105]] 434 // CHECK2-NEXT: #dbg_declare(ptr [[DOTOMP_IS_LAST]], [[META108:![0-9]+]], !DIExpression(), [[META103]]) 435 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG105]] 436 // CHECK2-NEXT: #dbg_declare(ptr [[K]], [[META109:![0-9]+]], !DIExpression(), [[META103]]) 437 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG110:![0-9]+]] 438 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG110]] 439 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB8:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG111:![0-9]+]] 440 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG105]] 441 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP5]], 4, !dbg [[DBG105]] 442 // CHECK2-NEXT: br i1 [[CMP1]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG105]] 443 // CHECK2: cond.true: 444 // CHECK2-NEXT: br label [[COND_END:%.*]], !dbg [[DBG105]] 445 // CHECK2: cond.false: 446 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG105]] 447 // CHECK2-NEXT: br label [[COND_END]], !dbg [[DBG105]] 448 // CHECK2: cond.end: 449 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ], !dbg [[DBG105]] 450 // CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG105]] 451 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG105]] 452 // CHECK2-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG105]] 453 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG110]] 454 // CHECK2: omp.inner.for.cond: 455 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG105]] 456 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG105]] 457 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]], !dbg [[DBG112:![0-9]+]] 458 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG110]] 459 // CHECK2: omp.inner.for.body: 460 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG105]] 461 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1, !dbg [[DBG113:![0-9]+]] 462 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG113]] 463 // CHECK2-NEXT: store i32 [[ADD]], ptr [[K]], align 4, !dbg [[DBG113]] 464 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP1]], align 4, !dbg [[DBG114:![0-9]+]] 465 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1, !dbg [[DBG114]] 466 // CHECK2-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4, !dbg [[DBG114]] 467 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG116:![0-9]+]] 468 // CHECK2: omp.body.continue: 469 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG111]] 470 // CHECK2: omp.inner.for.inc: 471 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG105]] 472 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1, !dbg [[DBG112]] 473 // CHECK2-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG112]] 474 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG111]], !llvm.loop [[LOOP117:![0-9]+]] 475 // CHECK2: omp.inner.for.end: 476 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG111]] 477 // CHECK2: omp.loop.exit: 478 // CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG111]] 479 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG111]] 480 // CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB10:[0-9]+]], i32 [[TMP14]]), !dbg [[DBG118:![0-9]+]] 481 // CHECK2-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG118]] 482 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4, !dbg [[DBG118]] 483 // CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB11:[0-9]+]], i32 [[TMP16]]), !dbg [[DBG118]] 484 // CHECK2-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG119:![0-9]+]] 485 // CHECK2: for.inc: 486 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG120:![0-9]+]] 487 // CHECK2-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP17]], 1, !dbg [[DBG120]] 488 // CHECK2-NEXT: store i32 [[INC4]], ptr [[TMP0]], align 4, !dbg [[DBG120]] 489 // CHECK2-NEXT: br label [[FOR_COND]], !dbg [[DBG121:![0-9]+]], !llvm.loop [[LOOP122:![0-9]+]] 490 // CHECK2: for.end: 491 // CHECK2-NEXT: ret void, !dbg [[DBG124:![0-9]+]] 492 // 493 // 494 // CHECK2-LABEL: define {{[^@]+}}@_Z11inline_declv.omp_outlined 495 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RES:%.*]]) #[[ATTR1]] !dbg [[DBG125:![0-9]+]] { 496 // CHECK2-NEXT: entry: 497 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 498 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 499 // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8 500 // CHECK2-NEXT: [[RES_ADDR:%.*]] = alloca ptr, align 8 501 // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 502 // CHECK2-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META126:![0-9]+]], !DIExpression(), [[META127:![0-9]+]]) 503 // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 504 // CHECK2-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META128:![0-9]+]], !DIExpression(), [[META127]]) 505 // CHECK2-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 8 506 // CHECK2-NEXT: #dbg_declare(ptr [[I_ADDR]], [[META129:![0-9]+]], !DIExpression(), [[META127]]) 507 // CHECK2-NEXT: store ptr [[RES]], ptr [[RES_ADDR]], align 8 508 // CHECK2-NEXT: #dbg_declare(ptr [[RES_ADDR]], [[META130:![0-9]+]], !DIExpression(), [[META127]]) 509 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !dbg [[DBG131:![0-9]+]] 510 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RES_ADDR]], align 8, !dbg [[DBG131]] 511 // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG131]] 512 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG131]] 513 // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !dbg [[DBG131]] 514 // CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[RES_ADDR]], align 8, !dbg [[DBG131]] 515 // CHECK2-NEXT: call void @_Z11inline_declv.omp_outlined_debug__(ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]], ptr [[TMP5]]) #[[ATTR2]], !dbg [[DBG131]] 516 // CHECK2-NEXT: ret void, !dbg [[DBG131]] 517 // 518 // 519 // CHECK3-LABEL: define {{[^@]+}}@_Z12outline_declv 520 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 521 // CHECK3-NEXT: entry: 522 // CHECK3-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8 523 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 524 // CHECK3-NEXT: [[K:%.*]] = alloca i32, align 4 525 // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) 526 // CHECK3-NEXT: br label [[OMP_PARALLEL:%.*]] 527 // CHECK3: omp_parallel: 528 // CHECK3-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0 529 // CHECK3-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8 530 // CHECK3-NEXT: [[GEP_K:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1 531 // CHECK3-NEXT: store ptr [[K]], ptr [[GEP_K]], align 8 532 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_Z12outline_declv..omp_par, ptr [[STRUCTARG]]) 533 // CHECK3-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]] 534 // CHECK3: omp.par.outlined.exit: 535 // CHECK3-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]] 536 // CHECK3: omp.par.exit.split: 537 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[K]], align 4 538 // CHECK3-NEXT: ret i32 [[TMP0]] 539 // 540 // 541 // CHECK3-LABEL: define {{[^@]+}}@_Z12outline_declv..omp_par 542 // CHECK3-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] { 543 // CHECK3-NEXT: omp.par.entry: 544 // CHECK3-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 0 545 // CHECK3-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8 546 // CHECK3-NEXT: [[GEP_K:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 1 547 // CHECK3-NEXT: [[LOADGEP_K:%.*]] = load ptr, ptr [[GEP_K]], align 8 548 // CHECK3-NEXT: [[P_LASTITER:%.*]] = alloca i32, align 4 549 // CHECK3-NEXT: [[P_LOWERBOUND:%.*]] = alloca i32, align 4 550 // CHECK3-NEXT: [[P_UPPERBOUND:%.*]] = alloca i32, align 4 551 // CHECK3-NEXT: [[P_STRIDE:%.*]] = alloca i32, align 4 552 // CHECK3-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 553 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4 554 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4 555 // CHECK3-NEXT: [[TID:%.*]] = load i32, ptr [[TID_ADDR_LOCAL]], align 4 556 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 557 // CHECK3-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 4 558 // CHECK3-NEXT: [[DOTCOUNT_ADDR:%.*]] = alloca i32, align 4 559 // CHECK3-NEXT: br label [[OMP_PAR_REGION:%.*]] 560 // CHECK3: omp.par.region: 561 // CHECK3-NEXT: store i32 0, ptr [[LOADGEP_I]], align 4 562 // CHECK3-NEXT: br label [[FOR_COND:%.*]] 563 // CHECK3: for.cond: 564 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP_I]], align 4 565 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 10 566 // CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 567 // CHECK3: for.end: 568 // CHECK3-NEXT: br label [[OMP_PAR_REGION_PARALLEL_AFTER:%.*]] 569 // CHECK3: omp.par.region.parallel.after: 570 // CHECK3-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]] 571 // CHECK3: omp.par.pre_finalize: 572 // CHECK3-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]] 573 // CHECK3: for.body: 574 // CHECK3-NEXT: store i32 0, ptr [[LOADGEP_K]], align 4 575 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 576 // CHECK3-NEXT: store ptr [[LOADGEP_K]], ptr [[TMP3]], align 8 577 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_0]], ptr [[AGG_CAPTURED1]], i32 0, i32 0 578 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[LOADGEP_K]], align 4 579 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP4]], align 4 580 // CHECK3-NEXT: call void @__captured_stmt(ptr [[DOTCOUNT_ADDR]], ptr [[AGG_CAPTURED]]) 581 // CHECK3-NEXT: [[DOTCOUNT:%.*]] = load i32, ptr [[DOTCOUNT_ADDR]], align 4 582 // CHECK3-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]] 583 // CHECK3: omp_loop.preheader: 584 // CHECK3-NEXT: store i32 0, ptr [[P_LOWERBOUND]], align 4 585 // CHECK3-NEXT: [[TMP6:%.*]] = sub i32 [[DOTCOUNT]], 1 586 // CHECK3-NEXT: store i32 [[TMP6]], ptr [[P_UPPERBOUND]], align 4 587 // CHECK3-NEXT: store i32 1, ptr [[P_STRIDE]], align 4 588 // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 589 // CHECK3-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]], i32 34, ptr [[P_LASTITER]], ptr [[P_LOWERBOUND]], ptr [[P_UPPERBOUND]], ptr [[P_STRIDE]], i32 1, i32 0) 590 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[P_LOWERBOUND]], align 4 591 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[P_UPPERBOUND]], align 4 592 // CHECK3-NEXT: [[TMP9:%.*]] = sub i32 [[TMP8]], [[TMP7]] 593 // CHECK3-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], 1 594 // CHECK3-NEXT: br label [[OMP_LOOP_HEADER:%.*]] 595 // CHECK3: omp_loop.header: 596 // CHECK3-NEXT: [[OMP_LOOP_IV:%.*]] = phi i32 [ 0, [[OMP_LOOP_PREHEADER]] ], [ [[OMP_LOOP_NEXT:%.*]], [[OMP_LOOP_INC:%.*]] ] 597 // CHECK3-NEXT: br label [[OMP_LOOP_COND:%.*]] 598 // CHECK3: omp_loop.cond: 599 // CHECK3-NEXT: [[OMP_LOOP_CMP:%.*]] = icmp ult i32 [[OMP_LOOP_IV]], [[TMP10]] 600 // CHECK3-NEXT: br i1 [[OMP_LOOP_CMP]], label [[OMP_LOOP_BODY:%.*]], label [[OMP_LOOP_EXIT:%.*]] 601 // CHECK3: omp_loop.exit: 602 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) 603 // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 604 // CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM3]]) 605 // CHECK3-NEXT: br label [[OMP_LOOP_AFTER:%.*]] 606 // CHECK3: omp_loop.after: 607 // CHECK3-NEXT: br label [[FOR_INC:%.*]] 608 // CHECK3: for.inc: 609 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[LOADGEP_I]], align 4 610 // CHECK3-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP11]], 1 611 // CHECK3-NEXT: store i32 [[INC4]], ptr [[LOADGEP_I]], align 4 612 // CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 613 // CHECK3: omp_loop.body: 614 // CHECK3-NEXT: [[TMP12:%.*]] = add i32 [[OMP_LOOP_IV]], [[TMP7]] 615 // CHECK3-NEXT: call void @__captured_stmt.1(ptr [[LOADGEP_K]], i32 [[TMP12]], ptr [[AGG_CAPTURED1]]) 616 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[LOADGEP_K]], align 4 617 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 618 // CHECK3-NEXT: store i32 [[INC]], ptr [[LOADGEP_K]], align 4 619 // CHECK3-NEXT: br label [[OMP_LOOP_INC]] 620 // CHECK3: omp_loop.inc: 621 // CHECK3-NEXT: [[OMP_LOOP_NEXT]] = add nuw i32 [[OMP_LOOP_IV]], 1 622 // CHECK3-NEXT: br label [[OMP_LOOP_HEADER]] 623 // CHECK3: omp.par.outlined.exit.exitStub: 624 // CHECK3-NEXT: ret void 625 // 626 // 627 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt 628 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR3:[0-9]+]] { 629 // CHECK3-NEXT: entry: 630 // CHECK3-NEXT: [[DISTANCE_ADDR:%.*]] = alloca ptr, align 8 631 // CHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 632 // CHECK3-NEXT: [[DOTSTART:%.*]] = alloca i32, align 4 633 // CHECK3-NEXT: [[DOTSTOP:%.*]] = alloca i32, align 4 634 // CHECK3-NEXT: [[DOTSTEP:%.*]] = alloca i32, align 4 635 // CHECK3-NEXT: store ptr [[DISTANCE]], ptr [[DISTANCE_ADDR]], align 8 636 // CHECK3-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 637 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 638 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 639 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 640 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 641 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[DOTSTART]], align 4 642 // CHECK3-NEXT: store i32 5, ptr [[DOTSTOP]], align 4 643 // CHECK3-NEXT: store i32 1, ptr [[DOTSTEP]], align 4 644 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTSTART]], align 4 645 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTSTOP]], align 4 646 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] 647 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 648 // CHECK3: cond.true: 649 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSTOP]], align 4 650 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSTART]], align 4 651 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[TMP7]] 652 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTSTEP]], align 4 653 // CHECK3-NEXT: [[SUB1:%.*]] = sub i32 [[TMP8]], 1 654 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]] 655 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSTEP]], align 4 656 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP9]] 657 // CHECK3-NEXT: br label [[COND_END:%.*]] 658 // CHECK3: cond.false: 659 // CHECK3-NEXT: br label [[COND_END]] 660 // CHECK3: cond.end: 661 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ] 662 // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8 663 // CHECK3-NEXT: store i32 [[COND]], ptr [[TMP10]], align 4 664 // CHECK3-NEXT: ret void 665 // 666 // 667 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt.1 668 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR3]] { 669 // CHECK3-NEXT: entry: 670 // CHECK3-NEXT: [[LOOPVAR_ADDR:%.*]] = alloca ptr, align 8 671 // CHECK3-NEXT: [[LOGICAL_ADDR:%.*]] = alloca i32, align 4 672 // CHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 673 // CHECK3-NEXT: store ptr [[LOOPVAR]], ptr [[LOOPVAR_ADDR]], align 8 674 // CHECK3-NEXT: store i32 [[LOGICAL]], ptr [[LOGICAL_ADDR]], align 4 675 // CHECK3-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 676 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 677 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 678 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 679 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4 680 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 1, [[TMP3]] 681 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]] 682 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8 683 // CHECK3-NEXT: store i32 [[ADD]], ptr [[TMP4]], align 4 684 // CHECK3-NEXT: ret void 685 // 686 // 687 // CHECK3-LABEL: define {{[^@]+}}@_Z11inline_declv 688 // CHECK3-SAME: () #[[ATTR0]] { 689 // CHECK3-NEXT: entry: 690 // CHECK3-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8 691 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 692 // CHECK3-NEXT: [[RES:%.*]] = alloca i32, align 4 693 // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 694 // CHECK3-NEXT: br label [[OMP_PARALLEL:%.*]] 695 // CHECK3: omp_parallel: 696 // CHECK3-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0 697 // CHECK3-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8 698 // CHECK3-NEXT: [[GEP_RES:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1 699 // CHECK3-NEXT: store ptr [[RES]], ptr [[GEP_RES]], align 8 700 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_Z11inline_declv..omp_par, ptr [[STRUCTARG]]) 701 // CHECK3-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]] 702 // CHECK3: omp.par.outlined.exit: 703 // CHECK3-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]] 704 // CHECK3: omp.par.exit.split: 705 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[RES]], align 4 706 // CHECK3-NEXT: ret i32 [[TMP0]] 707 // 708 // 709 // CHECK3-LABEL: define {{[^@]+}}@_Z11inline_declv..omp_par 710 // CHECK3-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR1]] { 711 // CHECK3-NEXT: omp.par.entry: 712 // CHECK3-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 0 713 // CHECK3-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8 714 // CHECK3-NEXT: [[GEP_RES:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 1 715 // CHECK3-NEXT: [[LOADGEP_RES:%.*]] = load ptr, ptr [[GEP_RES]], align 8 716 // CHECK3-NEXT: [[P_LASTITER:%.*]] = alloca i32, align 4 717 // CHECK3-NEXT: [[P_LOWERBOUND:%.*]] = alloca i32, align 4 718 // CHECK3-NEXT: [[P_UPPERBOUND:%.*]] = alloca i32, align 4 719 // CHECK3-NEXT: [[P_STRIDE:%.*]] = alloca i32, align 4 720 // CHECK3-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 721 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4 722 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4 723 // CHECK3-NEXT: [[TID:%.*]] = load i32, ptr [[TID_ADDR_LOCAL]], align 4 724 // CHECK3-NEXT: [[K:%.*]] = alloca i32, align 4 725 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8 726 // CHECK3-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 4 727 // CHECK3-NEXT: [[DOTCOUNT_ADDR:%.*]] = alloca i32, align 4 728 // CHECK3-NEXT: br label [[OMP_PAR_REGION:%.*]] 729 // CHECK3: omp.par.region: 730 // CHECK3-NEXT: store i32 0, ptr [[LOADGEP_I]], align 4 731 // CHECK3-NEXT: br label [[FOR_COND:%.*]] 732 // CHECK3: for.cond: 733 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP_I]], align 4 734 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 10 735 // CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 736 // CHECK3: for.end: 737 // CHECK3-NEXT: br label [[OMP_PAR_REGION_PARALLEL_AFTER:%.*]] 738 // CHECK3: omp.par.region.parallel.after: 739 // CHECK3-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]] 740 // CHECK3: omp.par.pre_finalize: 741 // CHECK3-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]] 742 // CHECK3: for.body: 743 // CHECK3-NEXT: store i32 0, ptr [[K]], align 4 744 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[AGG_CAPTURED]], i32 0, i32 0 745 // CHECK3-NEXT: store ptr [[K]], ptr [[TMP3]], align 8 746 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED1]], i32 0, i32 0 747 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[K]], align 4 748 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP4]], align 4 749 // CHECK3-NEXT: call void @__captured_stmt.2(ptr [[DOTCOUNT_ADDR]], ptr [[AGG_CAPTURED]]) 750 // CHECK3-NEXT: [[DOTCOUNT:%.*]] = load i32, ptr [[DOTCOUNT_ADDR]], align 4 751 // CHECK3-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]] 752 // CHECK3: omp_loop.preheader: 753 // CHECK3-NEXT: store i32 0, ptr [[P_LOWERBOUND]], align 4 754 // CHECK3-NEXT: [[TMP6:%.*]] = sub i32 [[DOTCOUNT]], 1 755 // CHECK3-NEXT: store i32 [[TMP6]], ptr [[P_UPPERBOUND]], align 4 756 // CHECK3-NEXT: store i32 1, ptr [[P_STRIDE]], align 4 757 // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 758 // CHECK3-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]], i32 34, ptr [[P_LASTITER]], ptr [[P_LOWERBOUND]], ptr [[P_UPPERBOUND]], ptr [[P_STRIDE]], i32 1, i32 0) 759 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[P_LOWERBOUND]], align 4 760 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[P_UPPERBOUND]], align 4 761 // CHECK3-NEXT: [[TMP9:%.*]] = sub i32 [[TMP8]], [[TMP7]] 762 // CHECK3-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], 1 763 // CHECK3-NEXT: br label [[OMP_LOOP_HEADER:%.*]] 764 // CHECK3: omp_loop.header: 765 // CHECK3-NEXT: [[OMP_LOOP_IV:%.*]] = phi i32 [ 0, [[OMP_LOOP_PREHEADER]] ], [ [[OMP_LOOP_NEXT:%.*]], [[OMP_LOOP_INC:%.*]] ] 766 // CHECK3-NEXT: br label [[OMP_LOOP_COND:%.*]] 767 // CHECK3: omp_loop.cond: 768 // CHECK3-NEXT: [[OMP_LOOP_CMP:%.*]] = icmp ult i32 [[OMP_LOOP_IV]], [[TMP10]] 769 // CHECK3-NEXT: br i1 [[OMP_LOOP_CMP]], label [[OMP_LOOP_BODY:%.*]], label [[OMP_LOOP_EXIT:%.*]] 770 // CHECK3: omp_loop.exit: 771 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) 772 // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) 773 // CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM3]]) 774 // CHECK3-NEXT: br label [[OMP_LOOP_AFTER:%.*]] 775 // CHECK3: omp_loop.after: 776 // CHECK3-NEXT: br label [[FOR_INC:%.*]] 777 // CHECK3: for.inc: 778 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[LOADGEP_I]], align 4 779 // CHECK3-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP11]], 1 780 // CHECK3-NEXT: store i32 [[INC4]], ptr [[LOADGEP_I]], align 4 781 // CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 782 // CHECK3: omp_loop.body: 783 // CHECK3-NEXT: [[TMP12:%.*]] = add i32 [[OMP_LOOP_IV]], [[TMP7]] 784 // CHECK3-NEXT: call void @__captured_stmt.3(ptr [[K]], i32 [[TMP12]], ptr [[AGG_CAPTURED1]]) 785 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[LOADGEP_RES]], align 4 786 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 787 // CHECK3-NEXT: store i32 [[INC]], ptr [[LOADGEP_RES]], align 4 788 // CHECK3-NEXT: br label [[OMP_LOOP_INC]] 789 // CHECK3: omp_loop.inc: 790 // CHECK3-NEXT: [[OMP_LOOP_NEXT]] = add nuw i32 [[OMP_LOOP_IV]], 1 791 // CHECK3-NEXT: br label [[OMP_LOOP_HEADER]] 792 // CHECK3: omp.par.outlined.exit.exitStub: 793 // CHECK3-NEXT: ret void 794 // 795 // 796 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt.2 797 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR3]] { 798 // CHECK3-NEXT: entry: 799 // CHECK3-NEXT: [[DISTANCE_ADDR:%.*]] = alloca ptr, align 8 800 // CHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 801 // CHECK3-NEXT: [[DOTSTART:%.*]] = alloca i32, align 4 802 // CHECK3-NEXT: [[DOTSTOP:%.*]] = alloca i32, align 4 803 // CHECK3-NEXT: [[DOTSTEP:%.*]] = alloca i32, align 4 804 // CHECK3-NEXT: store ptr [[DISTANCE]], ptr [[DISTANCE_ADDR]], align 8 805 // CHECK3-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 806 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 807 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 808 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 809 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 810 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[DOTSTART]], align 4 811 // CHECK3-NEXT: store i32 5, ptr [[DOTSTOP]], align 4 812 // CHECK3-NEXT: store i32 1, ptr [[DOTSTEP]], align 4 813 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTSTART]], align 4 814 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTSTOP]], align 4 815 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] 816 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 817 // CHECK3: cond.true: 818 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSTOP]], align 4 819 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSTART]], align 4 820 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[TMP7]] 821 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTSTEP]], align 4 822 // CHECK3-NEXT: [[SUB1:%.*]] = sub i32 [[TMP8]], 1 823 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]] 824 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSTEP]], align 4 825 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP9]] 826 // CHECK3-NEXT: br label [[COND_END:%.*]] 827 // CHECK3: cond.false: 828 // CHECK3-NEXT: br label [[COND_END]] 829 // CHECK3: cond.end: 830 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ] 831 // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8 832 // CHECK3-NEXT: store i32 [[COND]], ptr [[TMP10]], align 4 833 // CHECK3-NEXT: ret void 834 // 835 // 836 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt.3 837 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR3]] { 838 // CHECK3-NEXT: entry: 839 // CHECK3-NEXT: [[LOOPVAR_ADDR:%.*]] = alloca ptr, align 8 840 // CHECK3-NEXT: [[LOGICAL_ADDR:%.*]] = alloca i32, align 4 841 // CHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 842 // CHECK3-NEXT: store ptr [[LOOPVAR]], ptr [[LOOPVAR_ADDR]], align 8 843 // CHECK3-NEXT: store i32 [[LOGICAL]], ptr [[LOGICAL_ADDR]], align 4 844 // CHECK3-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 845 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 846 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 847 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 848 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4 849 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 1, [[TMP3]] 850 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]] 851 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8 852 // CHECK3-NEXT: store i32 [[ADD]], ptr [[TMP4]], align 4 853 // CHECK3-NEXT: ret void 854 // 855 // 856 // CHECK4-LABEL: define {{[^@]+}}@_Z12outline_declv 857 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG8:![0-9]+]] { 858 // CHECK4-NEXT: entry: 859 // CHECK4-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8 860 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 861 // CHECK4-NEXT: [[K:%.*]] = alloca i32, align 4 862 // CHECK4-NEXT: #dbg_declare(ptr [[I]], [[META14:![0-9]+]], !DIExpression(), [[META15:![0-9]+]]) 863 // CHECK4-NEXT: #dbg_declare(ptr [[K]], [[META16:![0-9]+]], !DIExpression(), [[META15]]) 864 // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]), !dbg [[DBG17:![0-9]+]] 865 // CHECK4-NEXT: br label [[OMP_PARALLEL:%.*]] 866 // CHECK4: omp_parallel: 867 // CHECK4-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0 868 // CHECK4-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8 869 // CHECK4-NEXT: [[GEP_K:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1 870 // CHECK4-NEXT: store ptr [[K]], ptr [[GEP_K]], align 8 871 // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_Z12outline_declv..omp_par, ptr [[STRUCTARG]]), !dbg [[DBG18:![0-9]+]] 872 // CHECK4-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]] 873 // CHECK4: omp.par.outlined.exit: 874 // CHECK4-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]] 875 // CHECK4: omp.par.exit.split: 876 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, ptr [[K]], align 4, !dbg [[DBG20:![0-9]+]] 877 // CHECK4-NEXT: ret i32 [[TMP0]], !dbg [[DBG20]] 878 // 879 // 880 // CHECK4-LABEL: define {{[^@]+}}@_Z12outline_declv..omp_par 881 // CHECK4-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] !dbg [[DBG21:![0-9]+]] { 882 // CHECK4-NEXT: omp.par.entry: 883 // CHECK4-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 0 884 // CHECK4-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8 885 // CHECK4-NEXT: [[GEP_K:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 1 886 // CHECK4-NEXT: [[LOADGEP_K:%.*]] = load ptr, ptr [[GEP_K]], align 8 887 // CHECK4-NEXT: [[P_LASTITER:%.*]] = alloca i32, align 4 888 // CHECK4-NEXT: [[P_LOWERBOUND:%.*]] = alloca i32, align 4 889 // CHECK4-NEXT: [[P_UPPERBOUND:%.*]] = alloca i32, align 4 890 // CHECK4-NEXT: [[P_STRIDE:%.*]] = alloca i32, align 4 891 // CHECK4-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 892 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4 893 // CHECK4-NEXT: store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4 894 // CHECK4-NEXT: [[TID:%.*]] = load i32, ptr [[TID_ADDR_LOCAL]], align 4 895 // CHECK4-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 896 // CHECK4-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 4 897 // CHECK4-NEXT: [[DOTCOUNT_ADDR:%.*]] = alloca i32, align 4 898 // CHECK4-NEXT: br label [[OMP_PAR_REGION:%.*]] 899 // CHECK4: omp.par.region: 900 // CHECK4-NEXT: store i32 0, ptr [[LOADGEP_I]], align 4, !dbg [[DBG23:![0-9]+]] 901 // CHECK4-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG23]] 902 // CHECK4: for.cond: 903 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP_I]], align 4, !dbg [[DBG25:![0-9]+]] 904 // CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 10, !dbg [[DBG25]] 905 // CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG23]] 906 // CHECK4: for.end: 907 // CHECK4-NEXT: br label [[OMP_PAR_REGION_PARALLEL_AFTER:%.*]], !dbg [[DBG27:![0-9]+]] 908 // CHECK4: omp.par.region.parallel.after: 909 // CHECK4-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]] 910 // CHECK4: omp.par.pre_finalize: 911 // CHECK4-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]], !dbg [[DBG27]] 912 // CHECK4: for.body: 913 // CHECK4-NEXT: store i32 0, ptr [[LOADGEP_K]], align 4, !dbg [[DBG28:![0-9]+]] 914 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0, !dbg [[DBG28]] 915 // CHECK4-NEXT: store ptr [[LOADGEP_K]], ptr [[TMP3]], align 8, !dbg [[DBG28]] 916 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_0]], ptr [[AGG_CAPTURED1]], i32 0, i32 0, !dbg [[DBG28]] 917 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[LOADGEP_K]], align 4, !dbg [[DBG32:![0-9]+]] 918 // CHECK4-NEXT: store i32 [[TMP5]], ptr [[TMP4]], align 4, !dbg [[DBG28]] 919 // CHECK4-NEXT: call void @__captured_stmt(ptr [[DOTCOUNT_ADDR]], ptr [[AGG_CAPTURED]]), !dbg [[DBG28]] 920 // CHECK4-NEXT: [[DOTCOUNT:%.*]] = load i32, ptr [[DOTCOUNT_ADDR]], align 4, !dbg [[DBG28]] 921 // CHECK4-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]], !dbg [[DBG28]] 922 // CHECK4: omp_loop.preheader: 923 // CHECK4-NEXT: store i32 0, ptr [[P_LOWERBOUND]], align 4, !dbg [[DBG28]] 924 // CHECK4-NEXT: [[TMP6:%.*]] = sub i32 [[DOTCOUNT]], 1, !dbg [[DBG28]] 925 // CHECK4-NEXT: store i32 [[TMP6]], ptr [[P_UPPERBOUND]], align 4, !dbg [[DBG28]] 926 // CHECK4-NEXT: store i32 1, ptr [[P_STRIDE]], align 4, !dbg [[DBG28]] 927 // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]), !dbg [[DBG28]] 928 // CHECK4-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM2]], i32 34, ptr [[P_LASTITER]], ptr [[P_LOWERBOUND]], ptr [[P_UPPERBOUND]], ptr [[P_STRIDE]], i32 1, i32 0), !dbg [[DBG28]] 929 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[P_LOWERBOUND]], align 4, !dbg [[DBG28]] 930 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[P_UPPERBOUND]], align 4, !dbg [[DBG28]] 931 // CHECK4-NEXT: [[TMP9:%.*]] = sub i32 [[TMP8]], [[TMP7]], !dbg [[DBG28]] 932 // CHECK4-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], 1, !dbg [[DBG28]] 933 // CHECK4-NEXT: br label [[OMP_LOOP_HEADER:%.*]], !dbg [[DBG28]] 934 // CHECK4: omp_loop.header: 935 // CHECK4-NEXT: [[OMP_LOOP_IV:%.*]] = phi i32 [ 0, [[OMP_LOOP_PREHEADER]] ], [ [[OMP_LOOP_NEXT:%.*]], [[OMP_LOOP_INC:%.*]] ], !dbg [[DBG28]] 936 // CHECK4-NEXT: br label [[OMP_LOOP_COND:%.*]], !dbg [[DBG28]] 937 // CHECK4: omp_loop.cond: 938 // CHECK4-NEXT: [[OMP_LOOP_CMP:%.*]] = icmp ult i32 [[OMP_LOOP_IV]], [[TMP10]], !dbg [[DBG28]] 939 // CHECK4-NEXT: br i1 [[OMP_LOOP_CMP]], label [[OMP_LOOP_BODY:%.*]], label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG28]] 940 // CHECK4: omp_loop.exit: 941 // CHECK4-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM2]]), !dbg [[DBG28]] 942 // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]]), !dbg [[DBG33:![0-9]+]] 943 // CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM3]]), !dbg [[DBG33]] 944 // CHECK4-NEXT: br label [[OMP_LOOP_AFTER:%.*]], !dbg [[DBG28]] 945 // CHECK4: omp_loop.after: 946 // CHECK4-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG34:![0-9]+]] 947 // CHECK4: for.inc: 948 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[LOADGEP_I]], align 4, !dbg [[DBG25]] 949 // CHECK4-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP11]], 1, !dbg [[DBG25]] 950 // CHECK4-NEXT: store i32 [[INC4]], ptr [[LOADGEP_I]], align 4, !dbg [[DBG25]] 951 // CHECK4-NEXT: br label [[FOR_COND]], !dbg [[DBG25]], !llvm.loop [[LOOP35:![0-9]+]] 952 // CHECK4: omp_loop.body: 953 // CHECK4-NEXT: [[TMP12:%.*]] = add i32 [[OMP_LOOP_IV]], [[TMP7]], !dbg [[DBG33]] 954 // CHECK4-NEXT: call void @__captured_stmt.1(ptr [[LOADGEP_K]], i32 [[TMP12]], ptr [[AGG_CAPTURED1]]), !dbg [[DBG28]] 955 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, ptr [[LOADGEP_K]], align 4, !dbg [[DBG37:![0-9]+]] 956 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1, !dbg [[DBG37]] 957 // CHECK4-NEXT: store i32 [[INC]], ptr [[LOADGEP_K]], align 4, !dbg [[DBG37]] 958 // CHECK4-NEXT: br label [[OMP_LOOP_INC]], !dbg [[DBG28]] 959 // CHECK4: omp_loop.inc: 960 // CHECK4-NEXT: [[OMP_LOOP_NEXT]] = add nuw i32 [[OMP_LOOP_IV]], 1, !dbg [[DBG28]] 961 // CHECK4-NEXT: br label [[OMP_LOOP_HEADER]], !dbg [[DBG28]] 962 // CHECK4: omp.par.outlined.exit.exitStub: 963 // CHECK4-NEXT: ret void 964 // 965 // 966 // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt 967 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR3:[0-9]+]] !dbg [[DBG39:![0-9]+]] { 968 // CHECK4-NEXT: entry: 969 // CHECK4-NEXT: [[DISTANCE_ADDR:%.*]] = alloca ptr, align 8 970 // CHECK4-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 971 // CHECK4-NEXT: [[DOTSTART:%.*]] = alloca i32, align 4 972 // CHECK4-NEXT: [[DOTSTOP:%.*]] = alloca i32, align 4 973 // CHECK4-NEXT: [[DOTSTEP:%.*]] = alloca i32, align 4 974 // CHECK4-NEXT: store ptr [[DISTANCE]], ptr [[DISTANCE_ADDR]], align 8 975 // CHECK4-NEXT: #dbg_declare(ptr [[DISTANCE_ADDR]], [[META47:![0-9]+]], !DIExpression(), [[META48:![0-9]+]]) 976 // CHECK4-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 977 // CHECK4-NEXT: #dbg_declare(ptr [[__CONTEXT_ADDR]], [[META49:![0-9]+]], !DIExpression(), [[META48]]) 978 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 979 // CHECK4-NEXT: #dbg_declare(ptr [[DOTSTART]], [[META50:![0-9]+]], !DIExpression(), [[META52:![0-9]+]]) 980 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG53:![0-9]+]] 981 // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG53]] 982 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG53]] 983 // CHECK4-NEXT: store i32 [[TMP3]], ptr [[DOTSTART]], align 4, !dbg [[META52]] 984 // CHECK4-NEXT: #dbg_declare(ptr [[DOTSTOP]], [[META55:![0-9]+]], !DIExpression(), [[META56:![0-9]+]]) 985 // CHECK4-NEXT: store i32 5, ptr [[DOTSTOP]], align 4, !dbg [[META56]] 986 // CHECK4-NEXT: #dbg_declare(ptr [[DOTSTEP]], [[META57:![0-9]+]], !DIExpression(), [[META56]]) 987 // CHECK4-NEXT: store i32 1, ptr [[DOTSTEP]], align 4, !dbg [[META56]] 988 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTSTART]], align 4, !dbg [[META56]] 989 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTSTOP]], align 4, !dbg [[META56]] 990 // CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]], !dbg [[META56]] 991 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[META56]] 992 // CHECK4: cond.true: 993 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSTOP]], align 4, !dbg [[META56]] 994 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSTART]], align 4, !dbg [[META56]] 995 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[TMP7]], !dbg [[META56]] 996 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTSTEP]], align 4, !dbg [[META56]] 997 // CHECK4-NEXT: [[SUB1:%.*]] = sub i32 [[TMP8]], 1, !dbg [[META56]] 998 // CHECK4-NEXT: [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]], !dbg [[META56]] 999 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSTEP]], align 4, !dbg [[META56]] 1000 // CHECK4-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP9]], !dbg [[META56]] 1001 // CHECK4-NEXT: br label [[COND_END:%.*]], !dbg [[META56]] 1002 // CHECK4: cond.false: 1003 // CHECK4-NEXT: br label [[COND_END]], !dbg [[META56]] 1004 // CHECK4: cond.end: 1005 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ], !dbg [[META56]] 1006 // CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8, !dbg [[META56]] 1007 // CHECK4-NEXT: store i32 [[COND]], ptr [[TMP10]], align 4, !dbg [[META56]] 1008 // CHECK4-NEXT: ret void, !dbg [[DBG58:![0-9]+]] 1009 // 1010 // 1011 // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt.1 1012 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR3]] !dbg [[DBG60:![0-9]+]] { 1013 // CHECK4-NEXT: entry: 1014 // CHECK4-NEXT: [[LOOPVAR_ADDR:%.*]] = alloca ptr, align 8 1015 // CHECK4-NEXT: [[LOGICAL_ADDR:%.*]] = alloca i32, align 4 1016 // CHECK4-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 1017 // CHECK4-NEXT: store ptr [[LOOPVAR]], ptr [[LOOPVAR_ADDR]], align 8 1018 // CHECK4-NEXT: #dbg_declare(ptr [[LOOPVAR_ADDR]], [[META68:![0-9]+]], !DIExpression(), [[META69:![0-9]+]]) 1019 // CHECK4-NEXT: store i32 [[LOGICAL]], ptr [[LOGICAL_ADDR]], align 4 1020 // CHECK4-NEXT: #dbg_declare(ptr [[LOGICAL_ADDR]], [[META70:![0-9]+]], !DIExpression(), [[META69]]) 1021 // CHECK4-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 1022 // CHECK4-NEXT: #dbg_declare(ptr [[__CONTEXT_ADDR]], [[META71:![0-9]+]], !DIExpression(), [[META69]]) 1023 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 1024 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG72:![0-9]+]] 1025 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4, !dbg [[DBG72]] 1026 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4, !dbg [[DBG74:![0-9]+]] 1027 // CHECK4-NEXT: [[MUL:%.*]] = mul i32 1, [[TMP3]], !dbg [[DBG74]] 1028 // CHECK4-NEXT: [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]], !dbg [[DBG74]] 1029 // CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8, !dbg [[DBG74]] 1030 // CHECK4-NEXT: store i32 [[ADD]], ptr [[TMP4]], align 4, !dbg [[META69]] 1031 // CHECK4-NEXT: ret void, !dbg [[DBG72]] 1032 // 1033 // 1034 // CHECK4-LABEL: define {{[^@]+}}@_Z11inline_declv 1035 // CHECK4-SAME: () #[[ATTR0]] !dbg [[DBG77:![0-9]+]] { 1036 // CHECK4-NEXT: entry: 1037 // CHECK4-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8 1038 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 1039 // CHECK4-NEXT: [[RES:%.*]] = alloca i32, align 4 1040 // CHECK4-NEXT: #dbg_declare(ptr [[I]], [[META78:![0-9]+]], !DIExpression(), [[META79:![0-9]+]]) 1041 // CHECK4-NEXT: #dbg_declare(ptr [[RES]], [[META80:![0-9]+]], !DIExpression(), [[META79]]) 1042 // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6:[0-9]+]]), !dbg [[DBG81:![0-9]+]] 1043 // CHECK4-NEXT: br label [[OMP_PARALLEL:%.*]] 1044 // CHECK4: omp_parallel: 1045 // CHECK4-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0 1046 // CHECK4-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8 1047 // CHECK4-NEXT: [[GEP_RES:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1 1048 // CHECK4-NEXT: store ptr [[RES]], ptr [[GEP_RES]], align 8 1049 // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB6]], i32 1, ptr @_Z11inline_declv..omp_par, ptr [[STRUCTARG]]), !dbg [[DBG82:![0-9]+]] 1050 // CHECK4-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]] 1051 // CHECK4: omp.par.outlined.exit: 1052 // CHECK4-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]] 1053 // CHECK4: omp.par.exit.split: 1054 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG84:![0-9]+]] 1055 // CHECK4-NEXT: ret i32 [[TMP0]], !dbg [[DBG84]] 1056 // 1057 // 1058 // CHECK4-LABEL: define {{[^@]+}}@_Z11inline_declv..omp_par 1059 // CHECK4-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG85:![0-9]+]] { 1060 // CHECK4-NEXT: omp.par.entry: 1061 // CHECK4-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 0 1062 // CHECK4-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8 1063 // CHECK4-NEXT: [[GEP_RES:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 1 1064 // CHECK4-NEXT: [[LOADGEP_RES:%.*]] = load ptr, ptr [[GEP_RES]], align 8 1065 // CHECK4-NEXT: [[P_LASTITER:%.*]] = alloca i32, align 4 1066 // CHECK4-NEXT: [[P_LOWERBOUND:%.*]] = alloca i32, align 4 1067 // CHECK4-NEXT: [[P_UPPERBOUND:%.*]] = alloca i32, align 4 1068 // CHECK4-NEXT: [[P_STRIDE:%.*]] = alloca i32, align 4 1069 // CHECK4-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 1070 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4 1071 // CHECK4-NEXT: store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4 1072 // CHECK4-NEXT: [[TID:%.*]] = load i32, ptr [[TID_ADDR_LOCAL]], align 4 1073 // CHECK4-NEXT: [[K:%.*]] = alloca i32, align 4 1074 // CHECK4-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8 1075 // CHECK4-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 4 1076 // CHECK4-NEXT: [[DOTCOUNT_ADDR:%.*]] = alloca i32, align 4 1077 // CHECK4-NEXT: br label [[OMP_PAR_REGION:%.*]] 1078 // CHECK4: omp.par.region: 1079 // CHECK4-NEXT: store i32 0, ptr [[LOADGEP_I]], align 4, !dbg [[DBG86:![0-9]+]] 1080 // CHECK4-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG86]] 1081 // CHECK4: for.cond: 1082 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP_I]], align 4, !dbg [[DBG88:![0-9]+]] 1083 // CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 10, !dbg [[DBG88]] 1084 // CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG86]] 1085 // CHECK4: for.end: 1086 // CHECK4-NEXT: br label [[OMP_PAR_REGION_PARALLEL_AFTER:%.*]], !dbg [[DBG90:![0-9]+]] 1087 // CHECK4: omp.par.region.parallel.after: 1088 // CHECK4-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]] 1089 // CHECK4: omp.par.pre_finalize: 1090 // CHECK4-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]], !dbg [[DBG90]] 1091 // CHECK4: for.body: 1092 // CHECK4-NEXT: #dbg_declare(ptr [[K]], [[META91:![0-9]+]], !DIExpression(), [[META95:![0-9]+]]) 1093 // CHECK4-NEXT: store i32 0, ptr [[K]], align 4, !dbg [[META95]] 1094 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[AGG_CAPTURED]], i32 0, i32 0, !dbg [[META95]] 1095 // CHECK4-NEXT: store ptr [[K]], ptr [[TMP3]], align 8, !dbg [[META95]] 1096 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED1]], i32 0, i32 0, !dbg [[META95]] 1097 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[K]], align 4, !dbg [[DBG96:![0-9]+]] 1098 // CHECK4-NEXT: store i32 [[TMP5]], ptr [[TMP4]], align 4, !dbg [[META95]] 1099 // CHECK4-NEXT: call void @__captured_stmt.2(ptr [[DOTCOUNT_ADDR]], ptr [[AGG_CAPTURED]]), !dbg [[META95]] 1100 // CHECK4-NEXT: [[DOTCOUNT:%.*]] = load i32, ptr [[DOTCOUNT_ADDR]], align 4, !dbg [[META95]] 1101 // CHECK4-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]], !dbg [[META95]] 1102 // CHECK4: omp_loop.preheader: 1103 // CHECK4-NEXT: store i32 0, ptr [[P_LOWERBOUND]], align 4, !dbg [[META95]] 1104 // CHECK4-NEXT: [[TMP6:%.*]] = sub i32 [[DOTCOUNT]], 1, !dbg [[META95]] 1105 // CHECK4-NEXT: store i32 [[TMP6]], ptr [[P_UPPERBOUND]], align 4, !dbg [[META95]] 1106 // CHECK4-NEXT: store i32 1, ptr [[P_STRIDE]], align 4, !dbg [[META95]] 1107 // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8:[0-9]+]]), !dbg [[META95]] 1108 // CHECK4-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB8]], i32 [[OMP_GLOBAL_THREAD_NUM2]], i32 34, ptr [[P_LASTITER]], ptr [[P_LOWERBOUND]], ptr [[P_UPPERBOUND]], ptr [[P_STRIDE]], i32 1, i32 0), !dbg [[META95]] 1109 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[P_LOWERBOUND]], align 4, !dbg [[META95]] 1110 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[P_UPPERBOUND]], align 4, !dbg [[META95]] 1111 // CHECK4-NEXT: [[TMP9:%.*]] = sub i32 [[TMP8]], [[TMP7]], !dbg [[META95]] 1112 // CHECK4-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], 1, !dbg [[META95]] 1113 // CHECK4-NEXT: br label [[OMP_LOOP_HEADER:%.*]], !dbg [[META95]] 1114 // CHECK4: omp_loop.header: 1115 // CHECK4-NEXT: [[OMP_LOOP_IV:%.*]] = phi i32 [ 0, [[OMP_LOOP_PREHEADER]] ], [ [[OMP_LOOP_NEXT:%.*]], [[OMP_LOOP_INC:%.*]] ], !dbg [[META95]] 1116 // CHECK4-NEXT: br label [[OMP_LOOP_COND:%.*]], !dbg [[META95]] 1117 // CHECK4: omp_loop.cond: 1118 // CHECK4-NEXT: [[OMP_LOOP_CMP:%.*]] = icmp ult i32 [[OMP_LOOP_IV]], [[TMP10]], !dbg [[META95]] 1119 // CHECK4-NEXT: br i1 [[OMP_LOOP_CMP]], label [[OMP_LOOP_BODY:%.*]], label [[OMP_LOOP_EXIT:%.*]], !dbg [[META95]] 1120 // CHECK4: omp_loop.exit: 1121 // CHECK4-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB8]], i32 [[OMP_GLOBAL_THREAD_NUM2]]), !dbg [[META95]] 1122 // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8]]), !dbg [[DBG97:![0-9]+]] 1123 // CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB9:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM3]]), !dbg [[DBG97]] 1124 // CHECK4-NEXT: br label [[OMP_LOOP_AFTER:%.*]], !dbg [[META95]] 1125 // CHECK4: omp_loop.after: 1126 // CHECK4-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG98:![0-9]+]] 1127 // CHECK4: for.inc: 1128 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[LOADGEP_I]], align 4, !dbg [[DBG88]] 1129 // CHECK4-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP11]], 1, !dbg [[DBG88]] 1130 // CHECK4-NEXT: store i32 [[INC4]], ptr [[LOADGEP_I]], align 4, !dbg [[DBG88]] 1131 // CHECK4-NEXT: br label [[FOR_COND]], !dbg [[DBG88]], !llvm.loop [[LOOP99:![0-9]+]] 1132 // CHECK4: omp_loop.body: 1133 // CHECK4-NEXT: [[TMP12:%.*]] = add i32 [[OMP_LOOP_IV]], [[TMP7]], !dbg [[DBG97]] 1134 // CHECK4-NEXT: call void @__captured_stmt.3(ptr [[K]], i32 [[TMP12]], ptr [[AGG_CAPTURED1]]), !dbg [[META95]] 1135 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, ptr [[LOADGEP_RES]], align 4, !dbg [[DBG100:![0-9]+]] 1136 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1, !dbg [[DBG100]] 1137 // CHECK4-NEXT: store i32 [[INC]], ptr [[LOADGEP_RES]], align 4, !dbg [[DBG100]] 1138 // CHECK4-NEXT: br label [[OMP_LOOP_INC]], !dbg [[META95]] 1139 // CHECK4: omp_loop.inc: 1140 // CHECK4-NEXT: [[OMP_LOOP_NEXT]] = add nuw i32 [[OMP_LOOP_IV]], 1, !dbg [[META95]] 1141 // CHECK4-NEXT: br label [[OMP_LOOP_HEADER]], !dbg [[META95]] 1142 // CHECK4: omp.par.outlined.exit.exitStub: 1143 // CHECK4-NEXT: ret void 1144 // 1145 // 1146 // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt.2 1147 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR3]] !dbg [[DBG102:![0-9]+]] { 1148 // CHECK4-NEXT: entry: 1149 // CHECK4-NEXT: [[DISTANCE_ADDR:%.*]] = alloca ptr, align 8 1150 // CHECK4-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 1151 // CHECK4-NEXT: [[DOTSTART:%.*]] = alloca i32, align 4 1152 // CHECK4-NEXT: [[DOTSTOP:%.*]] = alloca i32, align 4 1153 // CHECK4-NEXT: [[DOTSTEP:%.*]] = alloca i32, align 4 1154 // CHECK4-NEXT: store ptr [[DISTANCE]], ptr [[DISTANCE_ADDR]], align 8 1155 // CHECK4-NEXT: #dbg_declare(ptr [[DISTANCE_ADDR]], [[META103:![0-9]+]], !DIExpression(), [[META104:![0-9]+]]) 1156 // CHECK4-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 1157 // CHECK4-NEXT: #dbg_declare(ptr [[__CONTEXT_ADDR]], [[META105:![0-9]+]], !DIExpression(), [[META104]]) 1158 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 1159 // CHECK4-NEXT: #dbg_declare(ptr [[DOTSTART]], [[META106:![0-9]+]], !DIExpression(), [[META108:![0-9]+]]) 1160 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG109:![0-9]+]] 1161 // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG109]] 1162 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG109]] 1163 // CHECK4-NEXT: store i32 [[TMP3]], ptr [[DOTSTART]], align 4, !dbg [[META108]] 1164 // CHECK4-NEXT: #dbg_declare(ptr [[DOTSTOP]], [[META111:![0-9]+]], !DIExpression(), [[META112:![0-9]+]]) 1165 // CHECK4-NEXT: store i32 5, ptr [[DOTSTOP]], align 4, !dbg [[META112]] 1166 // CHECK4-NEXT: #dbg_declare(ptr [[DOTSTEP]], [[META113:![0-9]+]], !DIExpression(), [[META112]]) 1167 // CHECK4-NEXT: store i32 1, ptr [[DOTSTEP]], align 4, !dbg [[META112]] 1168 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTSTART]], align 4, !dbg [[META112]] 1169 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTSTOP]], align 4, !dbg [[META112]] 1170 // CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]], !dbg [[META112]] 1171 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[META112]] 1172 // CHECK4: cond.true: 1173 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSTOP]], align 4, !dbg [[META112]] 1174 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSTART]], align 4, !dbg [[META112]] 1175 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[TMP7]], !dbg [[META112]] 1176 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTSTEP]], align 4, !dbg [[META112]] 1177 // CHECK4-NEXT: [[SUB1:%.*]] = sub i32 [[TMP8]], 1, !dbg [[META112]] 1178 // CHECK4-NEXT: [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]], !dbg [[META112]] 1179 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSTEP]], align 4, !dbg [[META112]] 1180 // CHECK4-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP9]], !dbg [[META112]] 1181 // CHECK4-NEXT: br label [[COND_END:%.*]], !dbg [[META112]] 1182 // CHECK4: cond.false: 1183 // CHECK4-NEXT: br label [[COND_END]], !dbg [[META112]] 1184 // CHECK4: cond.end: 1185 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ], !dbg [[META112]] 1186 // CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8, !dbg [[META112]] 1187 // CHECK4-NEXT: store i32 [[COND]], ptr [[TMP10]], align 4, !dbg [[META112]] 1188 // CHECK4-NEXT: ret void, !dbg [[DBG114:![0-9]+]] 1189 // 1190 // 1191 // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt.3 1192 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR3]] !dbg [[DBG116:![0-9]+]] { 1193 // CHECK4-NEXT: entry: 1194 // CHECK4-NEXT: [[LOOPVAR_ADDR:%.*]] = alloca ptr, align 8 1195 // CHECK4-NEXT: [[LOGICAL_ADDR:%.*]] = alloca i32, align 4 1196 // CHECK4-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 1197 // CHECK4-NEXT: store ptr [[LOOPVAR]], ptr [[LOOPVAR_ADDR]], align 8 1198 // CHECK4-NEXT: #dbg_declare(ptr [[LOOPVAR_ADDR]], [[META117:![0-9]+]], !DIExpression(), [[META118:![0-9]+]]) 1199 // CHECK4-NEXT: store i32 [[LOGICAL]], ptr [[LOGICAL_ADDR]], align 4 1200 // CHECK4-NEXT: #dbg_declare(ptr [[LOGICAL_ADDR]], [[META119:![0-9]+]], !DIExpression(), [[META118]]) 1201 // CHECK4-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 1202 // CHECK4-NEXT: #dbg_declare(ptr [[__CONTEXT_ADDR]], [[META120:![0-9]+]], !DIExpression(), [[META118]]) 1203 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 1204 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG121:![0-9]+]] 1205 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4, !dbg [[DBG121]] 1206 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4, !dbg [[DBG123:![0-9]+]] 1207 // CHECK4-NEXT: [[MUL:%.*]] = mul i32 1, [[TMP3]], !dbg [[DBG123]] 1208 // CHECK4-NEXT: [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]], !dbg [[DBG123]] 1209 // CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8, !dbg [[DBG123]] 1210 // CHECK4-NEXT: store i32 [[ADD]], ptr [[TMP4]], align 4, !dbg [[META118]] 1211 // CHECK4-NEXT: ret void, !dbg [[DBG121]] 1212 // 1213