xref: /llvm-project/clang/test/OpenMP/nested_loop_codegen.cpp (revision 782c59a4eef0bca8546b0cfbb1e48a9fcd044c93) 
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 
3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1
4 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
5 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3
7 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
8 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -gno-column-info -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4
9 
10 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
11 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
12 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
13 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
16 // expected-no-diagnostics
17 #ifndef HEADER
18 #define HEADER
19 
20 int outline_decl() {
21   int i, k;
22   #pragma omp parallel
23   for(i=0; i<10; i++) {
24     #pragma omp loop
25     for(k=0; k<5; k++) {
26       k++;
27     }
28   }
29   return k;
30 }
31 
32 int inline_decl() {
33   int i, res;
34   #pragma omp parallel
35   for(i=0; i<10; i++) {
36     #pragma omp loop
37     for(int k=0; k<5; k++) {
38       res++;
39     }
40   }
41   return res;
42 }
43 
44 #endif
45 // CHECK1-LABEL: define {{[^@]+}}@_Z12outline_declv
46 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
47 // CHECK1-NEXT:  entry:
48 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
49 // CHECK1-NEXT:    [[K:%.*]] = alloca i32, align 4
50 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @_Z12outline_declv.omp_outlined, ptr [[I]])
51 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[K]], align 4
52 // CHECK1-NEXT:    ret i32 [[TMP0]]
53 //
54 //
55 // CHECK1-LABEL: define {{[^@]+}}@_Z12outline_declv.omp_outlined
56 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] {
57 // CHECK1-NEXT:  entry:
58 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
59 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
60 // CHECK1-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
61 // CHECK1-NEXT:    [[K:%.*]] = alloca i32, align 4
62 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
63 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
64 // CHECK1-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
65 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
66 // CHECK1-NEXT:    store i32 0, ptr [[TMP0]], align 4
67 // CHECK1-NEXT:    br label [[FOR_COND:%.*]]
68 // CHECK1:       for.cond:
69 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
70 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10
71 // CHECK1-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]]
72 // CHECK1:       for.body:
73 // CHECK1-NEXT:    store i32 0, ptr [[K]], align 4
74 // CHECK1-NEXT:    br label [[FOR_COND1:%.*]]
75 // CHECK1:       for.cond1:
76 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[K]], align 4
77 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[TMP2]], 5
78 // CHECK1-NEXT:    br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]]
79 // CHECK1:       for.body3:
80 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[K]], align 4
81 // CHECK1-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP3]], 1
82 // CHECK1-NEXT:    store i32 [[INC]], ptr [[K]], align 4
83 // CHECK1-NEXT:    br label [[FOR_INC:%.*]]
84 // CHECK1:       for.inc:
85 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[K]], align 4
86 // CHECK1-NEXT:    [[INC4:%.*]] = add nsw i32 [[TMP4]], 1
87 // CHECK1-NEXT:    store i32 [[INC4]], ptr [[K]], align 4
88 // CHECK1-NEXT:    br label [[FOR_COND1]], !llvm.loop [[LOOP3:![0-9]+]]
89 // CHECK1:       for.end:
90 // CHECK1-NEXT:    br label [[FOR_INC5:%.*]]
91 // CHECK1:       for.inc5:
92 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
93 // CHECK1-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP5]], 1
94 // CHECK1-NEXT:    store i32 [[INC6]], ptr [[TMP0]], align 4
95 // CHECK1-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
96 // CHECK1:       for.end7:
97 // CHECK1-NEXT:    ret void
98 //
99 //
100 // CHECK1-LABEL: define {{[^@]+}}@_Z11inline_declv
101 // CHECK1-SAME: () #[[ATTR0]] {
102 // CHECK1-NEXT:  entry:
103 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
104 // CHECK1-NEXT:    [[RES:%.*]] = alloca i32, align 4
105 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @_Z11inline_declv.omp_outlined, ptr [[I]], ptr [[RES]])
106 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RES]], align 4
107 // CHECK1-NEXT:    ret i32 [[TMP0]]
108 //
109 //
110 // CHECK1-LABEL: define {{[^@]+}}@_Z11inline_declv.omp_outlined
111 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RES:%.*]]) #[[ATTR1]] {
112 // CHECK1-NEXT:  entry:
113 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
114 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
115 // CHECK1-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
116 // CHECK1-NEXT:    [[RES_ADDR:%.*]] = alloca ptr, align 8
117 // CHECK1-NEXT:    [[K:%.*]] = alloca i32, align 4
118 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
119 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
120 // CHECK1-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
121 // CHECK1-NEXT:    store ptr [[RES]], ptr [[RES_ADDR]], align 8
122 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
123 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[RES_ADDR]], align 8
124 // CHECK1-NEXT:    store i32 0, ptr [[TMP0]], align 4
125 // CHECK1-NEXT:    br label [[FOR_COND:%.*]]
126 // CHECK1:       for.cond:
127 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4
128 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 10
129 // CHECK1-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]]
130 // CHECK1:       for.body:
131 // CHECK1-NEXT:    store i32 0, ptr [[K]], align 4
132 // CHECK1-NEXT:    br label [[FOR_COND1:%.*]]
133 // CHECK1:       for.cond1:
134 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[K]], align 4
135 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[TMP3]], 5
136 // CHECK1-NEXT:    br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]]
137 // CHECK1:       for.body3:
138 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4
139 // CHECK1-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
140 // CHECK1-NEXT:    store i32 [[INC]], ptr [[TMP1]], align 4
141 // CHECK1-NEXT:    br label [[FOR_INC:%.*]]
142 // CHECK1:       for.inc:
143 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[K]], align 4
144 // CHECK1-NEXT:    [[INC4:%.*]] = add nsw i32 [[TMP5]], 1
145 // CHECK1-NEXT:    store i32 [[INC4]], ptr [[K]], align 4
146 // CHECK1-NEXT:    br label [[FOR_COND1]], !llvm.loop [[LOOP8:![0-9]+]]
147 // CHECK1:       for.end:
148 // CHECK1-NEXT:    br label [[FOR_INC5:%.*]]
149 // CHECK1:       for.inc5:
150 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4
151 // CHECK1-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP6]], 1
152 // CHECK1-NEXT:    store i32 [[INC6]], ptr [[TMP0]], align 4
153 // CHECK1-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
154 // CHECK1:       for.end7:
155 // CHECK1-NEXT:    ret void
156 //
157 //
158 // CHECK2-LABEL: define {{[^@]+}}@_Z12outline_declv
159 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] {
160 // CHECK2-NEXT:  entry:
161 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
162 // CHECK2-NEXT:    [[K:%.*]] = alloca i32, align 4
163 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META12:![0-9]+]], metadata !DIExpression()), !dbg [[DBG13:![0-9]+]]
164 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[K]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]]
165 // CHECK2-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @_Z12outline_declv.omp_outlined, ptr [[I]]), !dbg [[DBG16:![0-9]+]]
166 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[K]], align 4, !dbg [[DBG17:![0-9]+]]
167 // CHECK2-NEXT:    ret i32 [[TMP0]], !dbg [[DBG18:![0-9]+]]
168 //
169 //
170 // CHECK2-LABEL: define {{[^@]+}}@_Z12outline_declv.omp_outlined_debug__
171 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR2:[0-9]+]] !dbg [[DBG19:![0-9]+]] {
172 // CHECK2-NEXT:  entry:
173 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
174 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
175 // CHECK2-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
176 // CHECK2-NEXT:    [[K:%.*]] = alloca i32, align 4
177 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
178 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META27:![0-9]+]], metadata !DIExpression()), !dbg [[DBG28:![0-9]+]]
179 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
180 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META29:![0-9]+]], metadata !DIExpression()), !dbg [[DBG28]]
181 // CHECK2-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
182 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[I_ADDR]], metadata [[META30:![0-9]+]], metadata !DIExpression()), !dbg [[DBG31:![0-9]+]]
183 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !dbg [[DBG32:![0-9]+]]
184 // CHECK2-NEXT:    store i32 0, ptr [[TMP0]], align 4, !dbg [[DBG33:![0-9]+]]
185 // CHECK2-NEXT:    br label [[FOR_COND:%.*]], !dbg [[DBG35:![0-9]+]]
186 // CHECK2:       for.cond:
187 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG36:![0-9]+]]
188 // CHECK2-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10, !dbg [[DBG38:![0-9]+]]
189 // CHECK2-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]], !dbg [[DBG39:![0-9]+]]
190 // CHECK2:       for.body:
191 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[K]], metadata [[META40:![0-9]+]], metadata !DIExpression()), !dbg [[DBG43:![0-9]+]]
192 // CHECK2-NEXT:    store i32 0, ptr [[K]], align 4, !dbg [[DBG44:![0-9]+]]
193 // CHECK2-NEXT:    br label [[FOR_COND1:%.*]], !dbg [[DBG46:![0-9]+]]
194 // CHECK2:       for.cond1:
195 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[K]], align 4, !dbg [[DBG47:![0-9]+]]
196 // CHECK2-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[TMP2]], 5, !dbg [[DBG49:![0-9]+]]
197 // CHECK2-NEXT:    br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]], !dbg [[DBG50:![0-9]+]]
198 // CHECK2:       for.body3:
199 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[K]], align 4, !dbg [[DBG51:![0-9]+]]
200 // CHECK2-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP3]], 1, !dbg [[DBG51]]
201 // CHECK2-NEXT:    store i32 [[INC]], ptr [[K]], align 4, !dbg [[DBG51]]
202 // CHECK2-NEXT:    br label [[FOR_INC:%.*]], !dbg [[DBG53:![0-9]+]]
203 // CHECK2:       for.inc:
204 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[K]], align 4, !dbg [[DBG54:![0-9]+]]
205 // CHECK2-NEXT:    [[INC4:%.*]] = add nsw i32 [[TMP4]], 1, !dbg [[DBG54]]
206 // CHECK2-NEXT:    store i32 [[INC4]], ptr [[K]], align 4, !dbg [[DBG54]]
207 // CHECK2-NEXT:    br label [[FOR_COND1]], !dbg [[DBG55:![0-9]+]], !llvm.loop [[LOOP56:![0-9]+]]
208 // CHECK2:       for.end:
209 // CHECK2-NEXT:    br label [[FOR_INC5:%.*]], !dbg [[DBG59:![0-9]+]]
210 // CHECK2:       for.inc5:
211 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG60:![0-9]+]]
212 // CHECK2-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP5]], 1, !dbg [[DBG60]]
213 // CHECK2-NEXT:    store i32 [[INC6]], ptr [[TMP0]], align 4, !dbg [[DBG60]]
214 // CHECK2-NEXT:    br label [[FOR_COND]], !dbg [[DBG61:![0-9]+]], !llvm.loop [[LOOP62:![0-9]+]]
215 // CHECK2:       for.end7:
216 // CHECK2-NEXT:    ret void, !dbg [[DBG64:![0-9]+]]
217 //
218 //
219 // CHECK2-LABEL: define {{[^@]+}}@_Z12outline_declv.omp_outlined
220 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR2]] !dbg [[DBG65:![0-9]+]] {
221 // CHECK2-NEXT:  entry:
222 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
223 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
224 // CHECK2-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
225 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
226 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META66:![0-9]+]], metadata !DIExpression()), !dbg [[DBG67:![0-9]+]]
227 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
228 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META68:![0-9]+]], metadata !DIExpression()), !dbg [[DBG67]]
229 // CHECK2-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
230 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[I_ADDR]], metadata [[META69:![0-9]+]], metadata !DIExpression()), !dbg [[DBG67]]
231 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !dbg [[DBG70:![0-9]+]]
232 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG70]]
233 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG70]]
234 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !dbg [[DBG70]]
235 // CHECK2-NEXT:    call void @_Z12outline_declv.omp_outlined_debug__(ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3:[0-9]+]], !dbg [[DBG70]]
236 // CHECK2-NEXT:    ret void, !dbg [[DBG70]]
237 //
238 //
239 // CHECK2-LABEL: define {{[^@]+}}@_Z11inline_declv
240 // CHECK2-SAME: () #[[ATTR0]] !dbg [[DBG73:![0-9]+]] {
241 // CHECK2-NEXT:  entry:
242 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
243 // CHECK2-NEXT:    [[RES:%.*]] = alloca i32, align 4
244 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META74:![0-9]+]], metadata !DIExpression()), !dbg [[DBG75:![0-9]+]]
245 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META76:![0-9]+]], metadata !DIExpression()), !dbg [[DBG77:![0-9]+]]
246 // CHECK2-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 2, ptr @_Z11inline_declv.omp_outlined, ptr [[I]], ptr [[RES]]), !dbg [[DBG78:![0-9]+]]
247 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG79:![0-9]+]]
248 // CHECK2-NEXT:    ret i32 [[TMP0]], !dbg [[DBG80:![0-9]+]]
249 //
250 //
251 // CHECK2-LABEL: define {{[^@]+}}@_Z11inline_declv.omp_outlined_debug__
252 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RES:%.*]]) #[[ATTR2]] !dbg [[DBG81:![0-9]+]] {
253 // CHECK2-NEXT:  entry:
254 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
255 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
256 // CHECK2-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
257 // CHECK2-NEXT:    [[RES_ADDR:%.*]] = alloca ptr, align 8
258 // CHECK2-NEXT:    [[K:%.*]] = alloca i32, align 4
259 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
260 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META84:![0-9]+]], metadata !DIExpression()), !dbg [[DBG85:![0-9]+]]
261 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
262 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META86:![0-9]+]], metadata !DIExpression()), !dbg [[DBG85]]
263 // CHECK2-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
264 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[I_ADDR]], metadata [[META87:![0-9]+]], metadata !DIExpression()), !dbg [[DBG88:![0-9]+]]
265 // CHECK2-NEXT:    store ptr [[RES]], ptr [[RES_ADDR]], align 8
266 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES_ADDR]], metadata [[META89:![0-9]+]], metadata !DIExpression()), !dbg [[DBG90:![0-9]+]]
267 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !dbg [[DBG91:![0-9]+]]
268 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[RES_ADDR]], align 8, !dbg [[DBG91]]
269 // CHECK2-NEXT:    store i32 0, ptr [[TMP0]], align 4, !dbg [[DBG92:![0-9]+]]
270 // CHECK2-NEXT:    br label [[FOR_COND:%.*]], !dbg [[DBG94:![0-9]+]]
271 // CHECK2:       for.cond:
272 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG95:![0-9]+]]
273 // CHECK2-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 10, !dbg [[DBG97:![0-9]+]]
274 // CHECK2-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]], !dbg [[DBG98:![0-9]+]]
275 // CHECK2:       for.body:
276 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[K]], metadata [[META99:![0-9]+]], metadata !DIExpression()), !dbg [[DBG103:![0-9]+]]
277 // CHECK2-NEXT:    store i32 0, ptr [[K]], align 4, !dbg [[DBG103]]
278 // CHECK2-NEXT:    br label [[FOR_COND1:%.*]], !dbg [[DBG104:![0-9]+]]
279 // CHECK2:       for.cond1:
280 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[K]], align 4, !dbg [[DBG105:![0-9]+]]
281 // CHECK2-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[TMP3]], 5, !dbg [[DBG107:![0-9]+]]
282 // CHECK2-NEXT:    br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]], !dbg [[DBG108:![0-9]+]]
283 // CHECK2:       for.body3:
284 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4, !dbg [[DBG109:![0-9]+]]
285 // CHECK2-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1, !dbg [[DBG109]]
286 // CHECK2-NEXT:    store i32 [[INC]], ptr [[TMP1]], align 4, !dbg [[DBG109]]
287 // CHECK2-NEXT:    br label [[FOR_INC:%.*]], !dbg [[DBG111:![0-9]+]]
288 // CHECK2:       for.inc:
289 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[K]], align 4, !dbg [[DBG112:![0-9]+]]
290 // CHECK2-NEXT:    [[INC4:%.*]] = add nsw i32 [[TMP5]], 1, !dbg [[DBG112]]
291 // CHECK2-NEXT:    store i32 [[INC4]], ptr [[K]], align 4, !dbg [[DBG112]]
292 // CHECK2-NEXT:    br label [[FOR_COND1]], !dbg [[DBG113:![0-9]+]], !llvm.loop [[LOOP114:![0-9]+]]
293 // CHECK2:       for.end:
294 // CHECK2-NEXT:    br label [[FOR_INC5:%.*]], !dbg [[DBG116:![0-9]+]]
295 // CHECK2:       for.inc5:
296 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG117:![0-9]+]]
297 // CHECK2-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP6]], 1, !dbg [[DBG117]]
298 // CHECK2-NEXT:    store i32 [[INC6]], ptr [[TMP0]], align 4, !dbg [[DBG117]]
299 // CHECK2-NEXT:    br label [[FOR_COND]], !dbg [[DBG118:![0-9]+]], !llvm.loop [[LOOP119:![0-9]+]]
300 // CHECK2:       for.end7:
301 // CHECK2-NEXT:    ret void, !dbg [[DBG121:![0-9]+]]
302 //
303 //
304 // CHECK2-LABEL: define {{[^@]+}}@_Z11inline_declv.omp_outlined
305 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RES:%.*]]) #[[ATTR2]] !dbg [[DBG122:![0-9]+]] {
306 // CHECK2-NEXT:  entry:
307 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
308 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
309 // CHECK2-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
310 // CHECK2-NEXT:    [[RES_ADDR:%.*]] = alloca ptr, align 8
311 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
312 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META123:![0-9]+]], metadata !DIExpression()), !dbg [[DBG124:![0-9]+]]
313 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
314 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META125:![0-9]+]], metadata !DIExpression()), !dbg [[DBG124]]
315 // CHECK2-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
316 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[I_ADDR]], metadata [[META126:![0-9]+]], metadata !DIExpression()), !dbg [[DBG124]]
317 // CHECK2-NEXT:    store ptr [[RES]], ptr [[RES_ADDR]], align 8
318 // CHECK2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES_ADDR]], metadata [[META127:![0-9]+]], metadata !DIExpression()), !dbg [[DBG124]]
319 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !dbg [[DBG128:![0-9]+]]
320 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[RES_ADDR]], align 8, !dbg [[DBG128]]
321 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG128]]
322 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG128]]
323 // CHECK2-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !dbg [[DBG128]]
324 // CHECK2-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[RES_ADDR]], align 8, !dbg [[DBG128]]
325 // CHECK2-NEXT:    call void @_Z11inline_declv.omp_outlined_debug__(ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]], ptr [[TMP5]]) #[[ATTR3]], !dbg [[DBG128]]
326 // CHECK2-NEXT:    ret void, !dbg [[DBG128]]
327 //
328 //
329 // CHECK3-LABEL: define {{[^@]+}}@_Z12outline_declv
330 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
331 // CHECK3-NEXT:  entry:
332 // CHECK3-NEXT:    [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
333 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
334 // CHECK3-NEXT:    [[K:%.*]] = alloca i32, align 4
335 // CHECK3-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
336 // CHECK3-NEXT:    br label [[OMP_PARALLEL:%.*]]
337 // CHECK3:       omp_parallel:
338 // CHECK3-NEXT:    [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
339 // CHECK3-NEXT:    store ptr [[I]], ptr [[GEP_I]], align 8
340 // CHECK3-NEXT:    [[GEP_K:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
341 // CHECK3-NEXT:    store ptr [[K]], ptr [[GEP_K]], align 8
342 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_Z12outline_declv..omp_par, ptr [[STRUCTARG]])
343 // CHECK3-NEXT:    br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
344 // CHECK3:       omp.par.outlined.exit:
345 // CHECK3-NEXT:    br label [[OMP_PAR_EXIT_SPLIT:%.*]]
346 // CHECK3:       omp.par.exit.split:
347 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[K]], align 4
348 // CHECK3-NEXT:    ret i32 [[TMP0]]
349 //
350 //
351 // CHECK3-LABEL: define {{[^@]+}}@_Z12outline_declv..omp_par
352 // CHECK3-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] {
353 // CHECK3-NEXT:  omp.par.entry:
354 // CHECK3-NEXT:    [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 0
355 // CHECK3-NEXT:    [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
356 // CHECK3-NEXT:    [[GEP_K:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 1
357 // CHECK3-NEXT:    [[LOADGEP_K:%.*]] = load ptr, ptr [[GEP_K]], align 8
358 // CHECK3-NEXT:    [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
359 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4
360 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4
361 // CHECK3-NEXT:    [[TID:%.*]] = load i32, ptr [[TID_ADDR_LOCAL]], align 4
362 // CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
363 // CHECK3-NEXT:    [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 4
364 // CHECK3-NEXT:    [[DOTCOUNT_ADDR:%.*]] = alloca i32, align 4
365 // CHECK3-NEXT:    br label [[OMP_PAR_REGION:%.*]]
366 // CHECK3:       omp.par.region:
367 // CHECK3-NEXT:    store i32 0, ptr [[LOADGEP_I]], align 4
368 // CHECK3-NEXT:    br label [[FOR_COND:%.*]]
369 // CHECK3:       for.cond:
370 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
371 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 10
372 // CHECK3-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
373 // CHECK3:       for.end:
374 // CHECK3-NEXT:    br label [[OMP_PAR_REGION_PARALLEL_AFTER:%.*]]
375 // CHECK3:       omp.par.region.parallel.after:
376 // CHECK3-NEXT:    br label [[OMP_PAR_PRE_FINALIZE:%.*]]
377 // CHECK3:       omp.par.pre_finalize:
378 // CHECK3-NEXT:    br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]]
379 // CHECK3:       for.body:
380 // CHECK3-NEXT:    store i32 0, ptr [[LOADGEP_K]], align 4
381 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
382 // CHECK3-NEXT:    store ptr [[LOADGEP_K]], ptr [[TMP3]], align 8
383 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[AGG_CAPTURED1]], i32 0, i32 0
384 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[LOADGEP_K]], align 4
385 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP4]], align 4
386 // CHECK3-NEXT:    call void @__captured_stmt(ptr [[DOTCOUNT_ADDR]], ptr [[AGG_CAPTURED]])
387 // CHECK3-NEXT:    [[DOTCOUNT:%.*]] = load i32, ptr [[DOTCOUNT_ADDR]], align 4
388 // CHECK3-NEXT:    br label [[OMP_LOOP_PREHEADER:%.*]]
389 // CHECK3:       omp_loop.preheader:
390 // CHECK3-NEXT:    br label [[OMP_LOOP_HEADER:%.*]]
391 // CHECK3:       omp_loop.header:
392 // CHECK3-NEXT:    [[OMP_LOOP_IV:%.*]] = phi i32 [ 0, [[OMP_LOOP_PREHEADER]] ], [ [[OMP_LOOP_NEXT:%.*]], [[OMP_LOOP_INC:%.*]] ]
393 // CHECK3-NEXT:    br label [[OMP_LOOP_COND:%.*]]
394 // CHECK3:       omp_loop.cond:
395 // CHECK3-NEXT:    [[OMP_LOOP_CMP:%.*]] = icmp ult i32 [[OMP_LOOP_IV]], [[DOTCOUNT]]
396 // CHECK3-NEXT:    br i1 [[OMP_LOOP_CMP]], label [[OMP_LOOP_BODY:%.*]], label [[OMP_LOOP_EXIT:%.*]]
397 // CHECK3:       omp_loop.exit:
398 // CHECK3-NEXT:    br label [[OMP_LOOP_AFTER:%.*]]
399 // CHECK3:       omp_loop.after:
400 // CHECK3-NEXT:    br label [[FOR_INC:%.*]]
401 // CHECK3:       for.inc:
402 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
403 // CHECK3-NEXT:    [[INC2:%.*]] = add nsw i32 [[TMP6]], 1
404 // CHECK3-NEXT:    store i32 [[INC2]], ptr [[LOADGEP_I]], align 4
405 // CHECK3-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
406 // CHECK3:       omp_loop.body:
407 // CHECK3-NEXT:    call void @__captured_stmt.1(ptr [[LOADGEP_K]], i32 [[OMP_LOOP_IV]], ptr [[AGG_CAPTURED1]])
408 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[LOADGEP_K]], align 4
409 // CHECK3-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
410 // CHECK3-NEXT:    store i32 [[INC]], ptr [[LOADGEP_K]], align 4
411 // CHECK3-NEXT:    br label [[OMP_LOOP_INC]]
412 // CHECK3:       omp_loop.inc:
413 // CHECK3-NEXT:    [[OMP_LOOP_NEXT]] = add nuw i32 [[OMP_LOOP_IV]], 1
414 // CHECK3-NEXT:    br label [[OMP_LOOP_HEADER]]
415 // CHECK3:       omp.par.outlined.exit.exitStub:
416 // CHECK3-NEXT:    ret void
417 //
418 //
419 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt
420 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR3:[0-9]+]] {
421 // CHECK3-NEXT:  entry:
422 // CHECK3-NEXT:    [[DISTANCE_ADDR:%.*]] = alloca ptr, align 8
423 // CHECK3-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
424 // CHECK3-NEXT:    [[DOTSTART:%.*]] = alloca i32, align 4
425 // CHECK3-NEXT:    [[DOTSTOP:%.*]] = alloca i32, align 4
426 // CHECK3-NEXT:    [[DOTSTEP:%.*]] = alloca i32, align 4
427 // CHECK3-NEXT:    store ptr [[DISTANCE]], ptr [[DISTANCE_ADDR]], align 8
428 // CHECK3-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
429 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
430 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0
431 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
432 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
433 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[DOTSTART]], align 4
434 // CHECK3-NEXT:    store i32 5, ptr [[DOTSTOP]], align 4
435 // CHECK3-NEXT:    store i32 1, ptr [[DOTSTEP]], align 4
436 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTSTART]], align 4
437 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTSTOP]], align 4
438 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]]
439 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
440 // CHECK3:       cond.true:
441 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTSTOP]], align 4
442 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTSTART]], align 4
443 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[TMP7]]
444 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTSTEP]], align 4
445 // CHECK3-NEXT:    [[SUB1:%.*]] = sub i32 [[TMP8]], 1
446 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]]
447 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTSTEP]], align 4
448 // CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP9]]
449 // CHECK3-NEXT:    br label [[COND_END:%.*]]
450 // CHECK3:       cond.false:
451 // CHECK3-NEXT:    br label [[COND_END]]
452 // CHECK3:       cond.end:
453 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ]
454 // CHECK3-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8
455 // CHECK3-NEXT:    store i32 [[COND]], ptr [[TMP10]], align 4
456 // CHECK3-NEXT:    ret void
457 //
458 //
459 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt.1
460 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR3]] {
461 // CHECK3-NEXT:  entry:
462 // CHECK3-NEXT:    [[LOOPVAR_ADDR:%.*]] = alloca ptr, align 8
463 // CHECK3-NEXT:    [[LOGICAL_ADDR:%.*]] = alloca i32, align 4
464 // CHECK3-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
465 // CHECK3-NEXT:    store ptr [[LOOPVAR]], ptr [[LOOPVAR_ADDR]], align 8
466 // CHECK3-NEXT:    store i32 [[LOGICAL]], ptr [[LOGICAL_ADDR]], align 4
467 // CHECK3-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
468 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
469 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0
470 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
471 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4
472 // CHECK3-NEXT:    [[MUL:%.*]] = mul i32 1, [[TMP3]]
473 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]]
474 // CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8
475 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[TMP4]], align 4
476 // CHECK3-NEXT:    ret void
477 //
478 //
479 // CHECK3-LABEL: define {{[^@]+}}@_Z11inline_declv
480 // CHECK3-SAME: () #[[ATTR0]] {
481 // CHECK3-NEXT:  entry:
482 // CHECK3-NEXT:    [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
483 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
484 // CHECK3-NEXT:    [[RES:%.*]] = alloca i32, align 4
485 // CHECK3-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
486 // CHECK3-NEXT:    br label [[OMP_PARALLEL:%.*]]
487 // CHECK3:       omp_parallel:
488 // CHECK3-NEXT:    [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
489 // CHECK3-NEXT:    store ptr [[I]], ptr [[GEP_I]], align 8
490 // CHECK3-NEXT:    [[GEP_RES:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
491 // CHECK3-NEXT:    store ptr [[RES]], ptr [[GEP_RES]], align 8
492 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_Z11inline_declv..omp_par, ptr [[STRUCTARG]])
493 // CHECK3-NEXT:    br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
494 // CHECK3:       omp.par.outlined.exit:
495 // CHECK3-NEXT:    br label [[OMP_PAR_EXIT_SPLIT:%.*]]
496 // CHECK3:       omp.par.exit.split:
497 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RES]], align 4
498 // CHECK3-NEXT:    ret i32 [[TMP0]]
499 //
500 //
501 // CHECK3-LABEL: define {{[^@]+}}@_Z11inline_declv..omp_par
502 // CHECK3-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR1]] {
503 // CHECK3-NEXT:  omp.par.entry:
504 // CHECK3-NEXT:    [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 0
505 // CHECK3-NEXT:    [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
506 // CHECK3-NEXT:    [[GEP_RES:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 1
507 // CHECK3-NEXT:    [[LOADGEP_RES:%.*]] = load ptr, ptr [[GEP_RES]], align 8
508 // CHECK3-NEXT:    [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
509 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4
510 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4
511 // CHECK3-NEXT:    [[TID:%.*]] = load i32, ptr [[TID_ADDR_LOCAL]], align 4
512 // CHECK3-NEXT:    [[K:%.*]] = alloca i32, align 4
513 // CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8
514 // CHECK3-NEXT:    [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 4
515 // CHECK3-NEXT:    [[DOTCOUNT_ADDR:%.*]] = alloca i32, align 4
516 // CHECK3-NEXT:    br label [[OMP_PAR_REGION:%.*]]
517 // CHECK3:       omp.par.region:
518 // CHECK3-NEXT:    store i32 0, ptr [[LOADGEP_I]], align 4
519 // CHECK3-NEXT:    br label [[FOR_COND:%.*]]
520 // CHECK3:       for.cond:
521 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
522 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 10
523 // CHECK3-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
524 // CHECK3:       for.end:
525 // CHECK3-NEXT:    br label [[OMP_PAR_REGION_PARALLEL_AFTER:%.*]]
526 // CHECK3:       omp.par.region.parallel.after:
527 // CHECK3-NEXT:    br label [[OMP_PAR_PRE_FINALIZE:%.*]]
528 // CHECK3:       omp.par.pre_finalize:
529 // CHECK3-NEXT:    br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]]
530 // CHECK3:       for.body:
531 // CHECK3-NEXT:    store i32 0, ptr [[K]], align 4
532 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[AGG_CAPTURED]], i32 0, i32 0
533 // CHECK3-NEXT:    store ptr [[K]], ptr [[TMP3]], align 8
534 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED1]], i32 0, i32 0
535 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[K]], align 4
536 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP4]], align 4
537 // CHECK3-NEXT:    call void @__captured_stmt.2(ptr [[DOTCOUNT_ADDR]], ptr [[AGG_CAPTURED]])
538 // CHECK3-NEXT:    [[DOTCOUNT:%.*]] = load i32, ptr [[DOTCOUNT_ADDR]], align 4
539 // CHECK3-NEXT:    br label [[OMP_LOOP_PREHEADER:%.*]]
540 // CHECK3:       omp_loop.preheader:
541 // CHECK3-NEXT:    br label [[OMP_LOOP_HEADER:%.*]]
542 // CHECK3:       omp_loop.header:
543 // CHECK3-NEXT:    [[OMP_LOOP_IV:%.*]] = phi i32 [ 0, [[OMP_LOOP_PREHEADER]] ], [ [[OMP_LOOP_NEXT:%.*]], [[OMP_LOOP_INC:%.*]] ]
544 // CHECK3-NEXT:    br label [[OMP_LOOP_COND:%.*]]
545 // CHECK3:       omp_loop.cond:
546 // CHECK3-NEXT:    [[OMP_LOOP_CMP:%.*]] = icmp ult i32 [[OMP_LOOP_IV]], [[DOTCOUNT]]
547 // CHECK3-NEXT:    br i1 [[OMP_LOOP_CMP]], label [[OMP_LOOP_BODY:%.*]], label [[OMP_LOOP_EXIT:%.*]]
548 // CHECK3:       omp_loop.exit:
549 // CHECK3-NEXT:    br label [[OMP_LOOP_AFTER:%.*]]
550 // CHECK3:       omp_loop.after:
551 // CHECK3-NEXT:    br label [[FOR_INC:%.*]]
552 // CHECK3:       for.inc:
553 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
554 // CHECK3-NEXT:    [[INC2:%.*]] = add nsw i32 [[TMP6]], 1
555 // CHECK3-NEXT:    store i32 [[INC2]], ptr [[LOADGEP_I]], align 4
556 // CHECK3-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
557 // CHECK3:       omp_loop.body:
558 // CHECK3-NEXT:    call void @__captured_stmt.3(ptr [[K]], i32 [[OMP_LOOP_IV]], ptr [[AGG_CAPTURED1]])
559 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[LOADGEP_RES]], align 4
560 // CHECK3-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
561 // CHECK3-NEXT:    store i32 [[INC]], ptr [[LOADGEP_RES]], align 4
562 // CHECK3-NEXT:    br label [[OMP_LOOP_INC]]
563 // CHECK3:       omp_loop.inc:
564 // CHECK3-NEXT:    [[OMP_LOOP_NEXT]] = add nuw i32 [[OMP_LOOP_IV]], 1
565 // CHECK3-NEXT:    br label [[OMP_LOOP_HEADER]]
566 // CHECK3:       omp.par.outlined.exit.exitStub:
567 // CHECK3-NEXT:    ret void
568 //
569 //
570 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt.2
571 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR3]] {
572 // CHECK3-NEXT:  entry:
573 // CHECK3-NEXT:    [[DISTANCE_ADDR:%.*]] = alloca ptr, align 8
574 // CHECK3-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
575 // CHECK3-NEXT:    [[DOTSTART:%.*]] = alloca i32, align 4
576 // CHECK3-NEXT:    [[DOTSTOP:%.*]] = alloca i32, align 4
577 // CHECK3-NEXT:    [[DOTSTEP:%.*]] = alloca i32, align 4
578 // CHECK3-NEXT:    store ptr [[DISTANCE]], ptr [[DISTANCE_ADDR]], align 8
579 // CHECK3-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
580 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
581 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0
582 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
583 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
584 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[DOTSTART]], align 4
585 // CHECK3-NEXT:    store i32 5, ptr [[DOTSTOP]], align 4
586 // CHECK3-NEXT:    store i32 1, ptr [[DOTSTEP]], align 4
587 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTSTART]], align 4
588 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTSTOP]], align 4
589 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]]
590 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
591 // CHECK3:       cond.true:
592 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTSTOP]], align 4
593 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTSTART]], align 4
594 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[TMP7]]
595 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTSTEP]], align 4
596 // CHECK3-NEXT:    [[SUB1:%.*]] = sub i32 [[TMP8]], 1
597 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]]
598 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTSTEP]], align 4
599 // CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP9]]
600 // CHECK3-NEXT:    br label [[COND_END:%.*]]
601 // CHECK3:       cond.false:
602 // CHECK3-NEXT:    br label [[COND_END]]
603 // CHECK3:       cond.end:
604 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ]
605 // CHECK3-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8
606 // CHECK3-NEXT:    store i32 [[COND]], ptr [[TMP10]], align 4
607 // CHECK3-NEXT:    ret void
608 //
609 //
610 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt.3
611 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR3]] {
612 // CHECK3-NEXT:  entry:
613 // CHECK3-NEXT:    [[LOOPVAR_ADDR:%.*]] = alloca ptr, align 8
614 // CHECK3-NEXT:    [[LOGICAL_ADDR:%.*]] = alloca i32, align 4
615 // CHECK3-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
616 // CHECK3-NEXT:    store ptr [[LOOPVAR]], ptr [[LOOPVAR_ADDR]], align 8
617 // CHECK3-NEXT:    store i32 [[LOGICAL]], ptr [[LOGICAL_ADDR]], align 4
618 // CHECK3-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
619 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
620 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0
621 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
622 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4
623 // CHECK3-NEXT:    [[MUL:%.*]] = mul i32 1, [[TMP3]]
624 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]]
625 // CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8
626 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[TMP4]], align 4
627 // CHECK3-NEXT:    ret void
628 //
629 //
630 // CHECK4-LABEL: define {{[^@]+}}@_Z12outline_declv
631 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG8:![0-9]+]] {
632 // CHECK4-NEXT:  entry:
633 // CHECK4-NEXT:    [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
634 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
635 // CHECK4-NEXT:    [[K:%.*]] = alloca i32, align 4
636 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]]
637 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[K]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15]]
638 // CHECK4-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]), !dbg [[DBG17:![0-9]+]]
639 // CHECK4-NEXT:    br label [[OMP_PARALLEL:%.*]]
640 // CHECK4:       omp_parallel:
641 // CHECK4-NEXT:    [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
642 // CHECK4-NEXT:    store ptr [[I]], ptr [[GEP_I]], align 8
643 // CHECK4-NEXT:    [[GEP_K:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
644 // CHECK4-NEXT:    store ptr [[K]], ptr [[GEP_K]], align 8
645 // CHECK4-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_Z12outline_declv..omp_par, ptr [[STRUCTARG]]), !dbg [[DBG18:![0-9]+]]
646 // CHECK4-NEXT:    br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
647 // CHECK4:       omp.par.outlined.exit:
648 // CHECK4-NEXT:    br label [[OMP_PAR_EXIT_SPLIT:%.*]]
649 // CHECK4:       omp.par.exit.split:
650 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[K]], align 4, !dbg [[DBG20:![0-9]+]]
651 // CHECK4-NEXT:    ret i32 [[TMP0]], !dbg [[DBG20]]
652 //
653 //
654 // CHECK4-LABEL: define {{[^@]+}}@_Z12outline_declv..omp_par
655 // CHECK4-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] !dbg [[DBG21:![0-9]+]] {
656 // CHECK4-NEXT:  omp.par.entry:
657 // CHECK4-NEXT:    [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 0
658 // CHECK4-NEXT:    [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
659 // CHECK4-NEXT:    [[GEP_K:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 1
660 // CHECK4-NEXT:    [[LOADGEP_K:%.*]] = load ptr, ptr [[GEP_K]], align 8
661 // CHECK4-NEXT:    [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
662 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4
663 // CHECK4-NEXT:    store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4
664 // CHECK4-NEXT:    [[TID:%.*]] = load i32, ptr [[TID_ADDR_LOCAL]], align 4
665 // CHECK4-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
666 // CHECK4-NEXT:    [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 4
667 // CHECK4-NEXT:    [[DOTCOUNT_ADDR:%.*]] = alloca i32, align 4
668 // CHECK4-NEXT:    br label [[OMP_PAR_REGION:%.*]]
669 // CHECK4:       omp.par.region:
670 // CHECK4-NEXT:    store i32 0, ptr [[LOADGEP_I]], align 4, !dbg [[DBG23:![0-9]+]]
671 // CHECK4-NEXT:    br label [[FOR_COND:%.*]], !dbg [[DBG23]]
672 // CHECK4:       for.cond:
673 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, ptr [[LOADGEP_I]], align 4, !dbg [[DBG25:![0-9]+]]
674 // CHECK4-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 10, !dbg [[DBG25]]
675 // CHECK4-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG23]]
676 // CHECK4:       for.end:
677 // CHECK4-NEXT:    br label [[OMP_PAR_REGION_PARALLEL_AFTER:%.*]], !dbg [[DBG27:![0-9]+]]
678 // CHECK4:       omp.par.region.parallel.after:
679 // CHECK4-NEXT:    br label [[OMP_PAR_PRE_FINALIZE:%.*]]
680 // CHECK4:       omp.par.pre_finalize:
681 // CHECK4-NEXT:    br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]], !dbg [[DBG27]]
682 // CHECK4:       for.body:
683 // CHECK4-NEXT:    store i32 0, ptr [[LOADGEP_K]], align 4, !dbg [[DBG28:![0-9]+]]
684 // CHECK4-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0, !dbg [[DBG28]]
685 // CHECK4-NEXT:    store ptr [[LOADGEP_K]], ptr [[TMP3]], align 8, !dbg [[DBG28]]
686 // CHECK4-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[AGG_CAPTURED1]], i32 0, i32 0, !dbg [[DBG28]]
687 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, ptr [[LOADGEP_K]], align 4, !dbg [[DBG32:![0-9]+]]
688 // CHECK4-NEXT:    store i32 [[TMP5]], ptr [[TMP4]], align 4, !dbg [[DBG28]]
689 // CHECK4-NEXT:    call void @__captured_stmt(ptr [[DOTCOUNT_ADDR]], ptr [[AGG_CAPTURED]]), !dbg [[DBG28]]
690 // CHECK4-NEXT:    [[DOTCOUNT:%.*]] = load i32, ptr [[DOTCOUNT_ADDR]], align 4, !dbg [[DBG28]]
691 // CHECK4-NEXT:    br label [[OMP_LOOP_PREHEADER:%.*]], !dbg [[DBG28]]
692 // CHECK4:       omp_loop.preheader:
693 // CHECK4-NEXT:    br label [[OMP_LOOP_HEADER:%.*]], !dbg [[DBG28]]
694 // CHECK4:       omp_loop.header:
695 // CHECK4-NEXT:    [[OMP_LOOP_IV:%.*]] = phi i32 [ 0, [[OMP_LOOP_PREHEADER]] ], [ [[OMP_LOOP_NEXT:%.*]], [[OMP_LOOP_INC:%.*]] ], !dbg [[DBG28]]
696 // CHECK4-NEXT:    br label [[OMP_LOOP_COND:%.*]], !dbg [[DBG28]]
697 // CHECK4:       omp_loop.cond:
698 // CHECK4-NEXT:    [[OMP_LOOP_CMP:%.*]] = icmp ult i32 [[OMP_LOOP_IV]], [[DOTCOUNT]], !dbg [[DBG28]]
699 // CHECK4-NEXT:    br i1 [[OMP_LOOP_CMP]], label [[OMP_LOOP_BODY:%.*]], label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG28]]
700 // CHECK4:       omp_loop.exit:
701 // CHECK4-NEXT:    br label [[OMP_LOOP_AFTER:%.*]], !dbg [[DBG28]]
702 // CHECK4:       omp_loop.after:
703 // CHECK4-NEXT:    br label [[FOR_INC:%.*]], !dbg [[DBG33:![0-9]+]]
704 // CHECK4:       for.inc:
705 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, ptr [[LOADGEP_I]], align 4, !dbg [[DBG25]]
706 // CHECK4-NEXT:    [[INC2:%.*]] = add nsw i32 [[TMP6]], 1, !dbg [[DBG25]]
707 // CHECK4-NEXT:    store i32 [[INC2]], ptr [[LOADGEP_I]], align 4, !dbg [[DBG25]]
708 // CHECK4-NEXT:    br label [[FOR_COND]], !dbg [[DBG25]], !llvm.loop [[LOOP34:![0-9]+]]
709 // CHECK4:       omp_loop.body:
710 // CHECK4-NEXT:    call void @__captured_stmt.1(ptr [[LOADGEP_K]], i32 [[OMP_LOOP_IV]], ptr [[AGG_CAPTURED1]]), !dbg [[DBG28]]
711 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, ptr [[LOADGEP_K]], align 4, !dbg [[DBG36:![0-9]+]]
712 // CHECK4-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1, !dbg [[DBG36]]
713 // CHECK4-NEXT:    store i32 [[INC]], ptr [[LOADGEP_K]], align 4, !dbg [[DBG36]]
714 // CHECK4-NEXT:    br label [[OMP_LOOP_INC]], !dbg [[DBG28]]
715 // CHECK4:       omp_loop.inc:
716 // CHECK4-NEXT:    [[OMP_LOOP_NEXT]] = add nuw i32 [[OMP_LOOP_IV]], 1, !dbg [[DBG28]]
717 // CHECK4-NEXT:    br label [[OMP_LOOP_HEADER]], !dbg [[DBG28]]
718 // CHECK4:       omp.par.outlined.exit.exitStub:
719 // CHECK4-NEXT:    ret void
720 //
721 //
722 // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt
723 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR4:[0-9]+]] !dbg [[DBG38:![0-9]+]] {
724 // CHECK4-NEXT:  entry:
725 // CHECK4-NEXT:    [[DISTANCE_ADDR:%.*]] = alloca ptr, align 8
726 // CHECK4-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
727 // CHECK4-NEXT:    [[DOTSTART:%.*]] = alloca i32, align 4
728 // CHECK4-NEXT:    [[DOTSTOP:%.*]] = alloca i32, align 4
729 // CHECK4-NEXT:    [[DOTSTEP:%.*]] = alloca i32, align 4
730 // CHECK4-NEXT:    store ptr [[DISTANCE]], ptr [[DISTANCE_ADDR]], align 8
731 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DISTANCE_ADDR]], metadata [[META47:![0-9]+]], metadata !DIExpression()), !dbg [[DBG48:![0-9]+]]
732 // CHECK4-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
733 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[__CONTEXT_ADDR]], metadata [[META49:![0-9]+]], metadata !DIExpression()), !dbg [[DBG48]]
734 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
735 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTSTART]], metadata [[META50:![0-9]+]], metadata !DIExpression()), !dbg [[DBG52:![0-9]+]]
736 // CHECK4-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG53:![0-9]+]]
737 // CHECK4-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG53]]
738 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG53]]
739 // CHECK4-NEXT:    store i32 [[TMP3]], ptr [[DOTSTART]], align 4, !dbg [[DBG52]]
740 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTSTOP]], metadata [[META55:![0-9]+]], metadata !DIExpression()), !dbg [[DBG56:![0-9]+]]
741 // CHECK4-NEXT:    store i32 5, ptr [[DOTSTOP]], align 4, !dbg [[DBG56]]
742 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTSTEP]], metadata [[META57:![0-9]+]], metadata !DIExpression()), !dbg [[DBG56]]
743 // CHECK4-NEXT:    store i32 1, ptr [[DOTSTEP]], align 4, !dbg [[DBG56]]
744 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTSTART]], align 4, !dbg [[DBG56]]
745 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTSTOP]], align 4, !dbg [[DBG56]]
746 // CHECK4-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]], !dbg [[DBG56]]
747 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG56]]
748 // CHECK4:       cond.true:
749 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTSTOP]], align 4, !dbg [[DBG56]]
750 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTSTART]], align 4, !dbg [[DBG56]]
751 // CHECK4-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[TMP7]], !dbg [[DBG56]]
752 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTSTEP]], align 4, !dbg [[DBG56]]
753 // CHECK4-NEXT:    [[SUB1:%.*]] = sub i32 [[TMP8]], 1, !dbg [[DBG56]]
754 // CHECK4-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]], !dbg [[DBG56]]
755 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTSTEP]], align 4, !dbg [[DBG56]]
756 // CHECK4-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP9]], !dbg [[DBG56]]
757 // CHECK4-NEXT:    br label [[COND_END:%.*]], !dbg [[DBG56]]
758 // CHECK4:       cond.false:
759 // CHECK4-NEXT:    br label [[COND_END]], !dbg [[DBG56]]
760 // CHECK4:       cond.end:
761 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ], !dbg [[DBG56]]
762 // CHECK4-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8, !dbg [[DBG56]]
763 // CHECK4-NEXT:    store i32 [[COND]], ptr [[TMP10]], align 4, !dbg [[DBG56]]
764 // CHECK4-NEXT:    ret void, !dbg [[DBG58:![0-9]+]]
765 //
766 //
767 // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt.1
768 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR4]] !dbg [[DBG60:![0-9]+]] {
769 // CHECK4-NEXT:  entry:
770 // CHECK4-NEXT:    [[LOOPVAR_ADDR:%.*]] = alloca ptr, align 8
771 // CHECK4-NEXT:    [[LOGICAL_ADDR:%.*]] = alloca i32, align 4
772 // CHECK4-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
773 // CHECK4-NEXT:    store ptr [[LOOPVAR]], ptr [[LOOPVAR_ADDR]], align 8
774 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[LOOPVAR_ADDR]], metadata [[META68:![0-9]+]], metadata !DIExpression()), !dbg [[DBG69:![0-9]+]]
775 // CHECK4-NEXT:    store i32 [[LOGICAL]], ptr [[LOGICAL_ADDR]], align 4
776 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[LOGICAL_ADDR]], metadata [[META70:![0-9]+]], metadata !DIExpression()), !dbg [[DBG69]]
777 // CHECK4-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
778 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[__CONTEXT_ADDR]], metadata [[META71:![0-9]+]], metadata !DIExpression()), !dbg [[DBG69]]
779 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
780 // CHECK4-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG72:![0-9]+]]
781 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4, !dbg [[DBG72]]
782 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4, !dbg [[DBG74:![0-9]+]]
783 // CHECK4-NEXT:    [[MUL:%.*]] = mul i32 1, [[TMP3]], !dbg [[DBG74]]
784 // CHECK4-NEXT:    [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]], !dbg [[DBG74]]
785 // CHECK4-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8, !dbg [[DBG74]]
786 // CHECK4-NEXT:    store i32 [[ADD]], ptr [[TMP4]], align 4, !dbg [[DBG69]]
787 // CHECK4-NEXT:    ret void, !dbg [[DBG72]]
788 //
789 //
790 // CHECK4-LABEL: define {{[^@]+}}@_Z11inline_declv
791 // CHECK4-SAME: () #[[ATTR0]] !dbg [[DBG77:![0-9]+]] {
792 // CHECK4-NEXT:  entry:
793 // CHECK4-NEXT:    [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
794 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
795 // CHECK4-NEXT:    [[RES:%.*]] = alloca i32, align 4
796 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META78:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79:![0-9]+]]
797 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META80:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79]]
798 // CHECK4-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]), !dbg [[DBG81:![0-9]+]]
799 // CHECK4-NEXT:    br label [[OMP_PARALLEL:%.*]]
800 // CHECK4:       omp_parallel:
801 // CHECK4-NEXT:    [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
802 // CHECK4-NEXT:    store ptr [[I]], ptr [[GEP_I]], align 8
803 // CHECK4-NEXT:    [[GEP_RES:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
804 // CHECK4-NEXT:    store ptr [[RES]], ptr [[GEP_RES]], align 8
805 // CHECK4-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @_Z11inline_declv..omp_par, ptr [[STRUCTARG]]), !dbg [[DBG82:![0-9]+]]
806 // CHECK4-NEXT:    br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
807 // CHECK4:       omp.par.outlined.exit:
808 // CHECK4-NEXT:    br label [[OMP_PAR_EXIT_SPLIT:%.*]]
809 // CHECK4:       omp.par.exit.split:
810 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG84:![0-9]+]]
811 // CHECK4-NEXT:    ret i32 [[TMP0]], !dbg [[DBG84]]
812 //
813 //
814 // CHECK4-LABEL: define {{[^@]+}}@_Z11inline_declv..omp_par
815 // CHECK4-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG85:![0-9]+]] {
816 // CHECK4-NEXT:  omp.par.entry:
817 // CHECK4-NEXT:    [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 0
818 // CHECK4-NEXT:    [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
819 // CHECK4-NEXT:    [[GEP_RES:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 1
820 // CHECK4-NEXT:    [[LOADGEP_RES:%.*]] = load ptr, ptr [[GEP_RES]], align 8
821 // CHECK4-NEXT:    [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
822 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4
823 // CHECK4-NEXT:    store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4
824 // CHECK4-NEXT:    [[TID:%.*]] = load i32, ptr [[TID_ADDR_LOCAL]], align 4
825 // CHECK4-NEXT:    [[K:%.*]] = alloca i32, align 4
826 // CHECK4-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8
827 // CHECK4-NEXT:    [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 4
828 // CHECK4-NEXT:    [[DOTCOUNT_ADDR:%.*]] = alloca i32, align 4
829 // CHECK4-NEXT:    br label [[OMP_PAR_REGION:%.*]]
830 // CHECK4:       omp.par.region:
831 // CHECK4-NEXT:    store i32 0, ptr [[LOADGEP_I]], align 4, !dbg [[DBG86:![0-9]+]]
832 // CHECK4-NEXT:    br label [[FOR_COND:%.*]], !dbg [[DBG86]]
833 // CHECK4:       for.cond:
834 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, ptr [[LOADGEP_I]], align 4, !dbg [[DBG88:![0-9]+]]
835 // CHECK4-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 10, !dbg [[DBG88]]
836 // CHECK4-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG86]]
837 // CHECK4:       for.end:
838 // CHECK4-NEXT:    br label [[OMP_PAR_REGION_PARALLEL_AFTER:%.*]], !dbg [[DBG90:![0-9]+]]
839 // CHECK4:       omp.par.region.parallel.after:
840 // CHECK4-NEXT:    br label [[OMP_PAR_PRE_FINALIZE:%.*]]
841 // CHECK4:       omp.par.pre_finalize:
842 // CHECK4-NEXT:    br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]], !dbg [[DBG90]]
843 // CHECK4:       for.body:
844 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[K]], metadata [[META91:![0-9]+]], metadata !DIExpression()), !dbg [[DBG95:![0-9]+]]
845 // CHECK4-NEXT:    store i32 0, ptr [[K]], align 4, !dbg [[DBG95]]
846 // CHECK4-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[AGG_CAPTURED]], i32 0, i32 0, !dbg [[DBG95]]
847 // CHECK4-NEXT:    store ptr [[K]], ptr [[TMP3]], align 8, !dbg [[DBG95]]
848 // CHECK4-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED1]], i32 0, i32 0, !dbg [[DBG95]]
849 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, ptr [[K]], align 4, !dbg [[DBG96:![0-9]+]]
850 // CHECK4-NEXT:    store i32 [[TMP5]], ptr [[TMP4]], align 4, !dbg [[DBG95]]
851 // CHECK4-NEXT:    call void @__captured_stmt.2(ptr [[DOTCOUNT_ADDR]], ptr [[AGG_CAPTURED]]), !dbg [[DBG95]]
852 // CHECK4-NEXT:    [[DOTCOUNT:%.*]] = load i32, ptr [[DOTCOUNT_ADDR]], align 4, !dbg [[DBG95]]
853 // CHECK4-NEXT:    br label [[OMP_LOOP_PREHEADER:%.*]], !dbg [[DBG95]]
854 // CHECK4:       omp_loop.preheader:
855 // CHECK4-NEXT:    br label [[OMP_LOOP_HEADER:%.*]], !dbg [[DBG95]]
856 // CHECK4:       omp_loop.header:
857 // CHECK4-NEXT:    [[OMP_LOOP_IV:%.*]] = phi i32 [ 0, [[OMP_LOOP_PREHEADER]] ], [ [[OMP_LOOP_NEXT:%.*]], [[OMP_LOOP_INC:%.*]] ], !dbg [[DBG95]]
858 // CHECK4-NEXT:    br label [[OMP_LOOP_COND:%.*]], !dbg [[DBG95]]
859 // CHECK4:       omp_loop.cond:
860 // CHECK4-NEXT:    [[OMP_LOOP_CMP:%.*]] = icmp ult i32 [[OMP_LOOP_IV]], [[DOTCOUNT]], !dbg [[DBG95]]
861 // CHECK4-NEXT:    br i1 [[OMP_LOOP_CMP]], label [[OMP_LOOP_BODY:%.*]], label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG95]]
862 // CHECK4:       omp_loop.exit:
863 // CHECK4-NEXT:    br label [[OMP_LOOP_AFTER:%.*]], !dbg [[DBG95]]
864 // CHECK4:       omp_loop.after:
865 // CHECK4-NEXT:    br label [[FOR_INC:%.*]], !dbg [[DBG97:![0-9]+]]
866 // CHECK4:       for.inc:
867 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, ptr [[LOADGEP_I]], align 4, !dbg [[DBG88]]
868 // CHECK4-NEXT:    [[INC2:%.*]] = add nsw i32 [[TMP6]], 1, !dbg [[DBG88]]
869 // CHECK4-NEXT:    store i32 [[INC2]], ptr [[LOADGEP_I]], align 4, !dbg [[DBG88]]
870 // CHECK4-NEXT:    br label [[FOR_COND]], !dbg [[DBG88]], !llvm.loop [[LOOP98:![0-9]+]]
871 // CHECK4:       omp_loop.body:
872 // CHECK4-NEXT:    call void @__captured_stmt.3(ptr [[K]], i32 [[OMP_LOOP_IV]], ptr [[AGG_CAPTURED1]]), !dbg [[DBG95]]
873 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, ptr [[LOADGEP_RES]], align 4, !dbg [[DBG99:![0-9]+]]
874 // CHECK4-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1, !dbg [[DBG99]]
875 // CHECK4-NEXT:    store i32 [[INC]], ptr [[LOADGEP_RES]], align 4, !dbg [[DBG99]]
876 // CHECK4-NEXT:    br label [[OMP_LOOP_INC]], !dbg [[DBG95]]
877 // CHECK4:       omp_loop.inc:
878 // CHECK4-NEXT:    [[OMP_LOOP_NEXT]] = add nuw i32 [[OMP_LOOP_IV]], 1, !dbg [[DBG95]]
879 // CHECK4-NEXT:    br label [[OMP_LOOP_HEADER]], !dbg [[DBG95]]
880 // CHECK4:       omp.par.outlined.exit.exitStub:
881 // CHECK4-NEXT:    ret void
882 //
883 //
884 // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt.2
885 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR4]] !dbg [[DBG101:![0-9]+]] {
886 // CHECK4-NEXT:  entry:
887 // CHECK4-NEXT:    [[DISTANCE_ADDR:%.*]] = alloca ptr, align 8
888 // CHECK4-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
889 // CHECK4-NEXT:    [[DOTSTART:%.*]] = alloca i32, align 4
890 // CHECK4-NEXT:    [[DOTSTOP:%.*]] = alloca i32, align 4
891 // CHECK4-NEXT:    [[DOTSTEP:%.*]] = alloca i32, align 4
892 // CHECK4-NEXT:    store ptr [[DISTANCE]], ptr [[DISTANCE_ADDR]], align 8
893 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DISTANCE_ADDR]], metadata [[META102:![0-9]+]], metadata !DIExpression()), !dbg [[DBG103:![0-9]+]]
894 // CHECK4-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
895 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[__CONTEXT_ADDR]], metadata [[META104:![0-9]+]], metadata !DIExpression()), !dbg [[DBG103]]
896 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
897 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTSTART]], metadata [[META105:![0-9]+]], metadata !DIExpression()), !dbg [[DBG107:![0-9]+]]
898 // CHECK4-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG108:![0-9]+]]
899 // CHECK4-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG108]]
900 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG108]]
901 // CHECK4-NEXT:    store i32 [[TMP3]], ptr [[DOTSTART]], align 4, !dbg [[DBG107]]
902 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTSTOP]], metadata [[META110:![0-9]+]], metadata !DIExpression()), !dbg [[DBG111:![0-9]+]]
903 // CHECK4-NEXT:    store i32 5, ptr [[DOTSTOP]], align 4, !dbg [[DBG111]]
904 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTSTEP]], metadata [[META112:![0-9]+]], metadata !DIExpression()), !dbg [[DBG111]]
905 // CHECK4-NEXT:    store i32 1, ptr [[DOTSTEP]], align 4, !dbg [[DBG111]]
906 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTSTART]], align 4, !dbg [[DBG111]]
907 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTSTOP]], align 4, !dbg [[DBG111]]
908 // CHECK4-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]], !dbg [[DBG111]]
909 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG111]]
910 // CHECK4:       cond.true:
911 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTSTOP]], align 4, !dbg [[DBG111]]
912 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTSTART]], align 4, !dbg [[DBG111]]
913 // CHECK4-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[TMP7]], !dbg [[DBG111]]
914 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTSTEP]], align 4, !dbg [[DBG111]]
915 // CHECK4-NEXT:    [[SUB1:%.*]] = sub i32 [[TMP8]], 1, !dbg [[DBG111]]
916 // CHECK4-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]], !dbg [[DBG111]]
917 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTSTEP]], align 4, !dbg [[DBG111]]
918 // CHECK4-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP9]], !dbg [[DBG111]]
919 // CHECK4-NEXT:    br label [[COND_END:%.*]], !dbg [[DBG111]]
920 // CHECK4:       cond.false:
921 // CHECK4-NEXT:    br label [[COND_END]], !dbg [[DBG111]]
922 // CHECK4:       cond.end:
923 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ], !dbg [[DBG111]]
924 // CHECK4-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8, !dbg [[DBG111]]
925 // CHECK4-NEXT:    store i32 [[COND]], ptr [[TMP10]], align 4, !dbg [[DBG111]]
926 // CHECK4-NEXT:    ret void, !dbg [[DBG113:![0-9]+]]
927 //
928 //
929 // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt.3
930 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR4]] !dbg [[DBG115:![0-9]+]] {
931 // CHECK4-NEXT:  entry:
932 // CHECK4-NEXT:    [[LOOPVAR_ADDR:%.*]] = alloca ptr, align 8
933 // CHECK4-NEXT:    [[LOGICAL_ADDR:%.*]] = alloca i32, align 4
934 // CHECK4-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
935 // CHECK4-NEXT:    store ptr [[LOOPVAR]], ptr [[LOOPVAR_ADDR]], align 8
936 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[LOOPVAR_ADDR]], metadata [[META116:![0-9]+]], metadata !DIExpression()), !dbg [[DBG117:![0-9]+]]
937 // CHECK4-NEXT:    store i32 [[LOGICAL]], ptr [[LOGICAL_ADDR]], align 4
938 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[LOGICAL_ADDR]], metadata [[META118:![0-9]+]], metadata !DIExpression()), !dbg [[DBG117]]
939 // CHECK4-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
940 // CHECK4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[__CONTEXT_ADDR]], metadata [[META119:![0-9]+]], metadata !DIExpression()), !dbg [[DBG117]]
941 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
942 // CHECK4-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG120:![0-9]+]]
943 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4, !dbg [[DBG120]]
944 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4, !dbg [[DBG122:![0-9]+]]
945 // CHECK4-NEXT:    [[MUL:%.*]] = mul i32 1, [[TMP3]], !dbg [[DBG122]]
946 // CHECK4-NEXT:    [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]], !dbg [[DBG122]]
947 // CHECK4-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8, !dbg [[DBG122]]
948 // CHECK4-NEXT:    store i32 [[ADD]], ptr [[TMP4]], align 4, !dbg [[DBG117]]
949 // CHECK4-NEXT:    ret void, !dbg [[DBG120]]
950 //
951