1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 3 // expected-no-diagnostics 4 5 // Check code generation 6 // RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -std=c++20 -fclang-abi-compat=latest -fopenmp -fopenmp-version=60 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 7 8 // Check same results after serialization round-trip 9 // FIXME: They should be exactly the same but currently differ in function order 10 // RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -std=c++20 -fclang-abi-compat=latest -fopenmp -fopenmp-version=60 -emit-pch -o %t %s 11 // RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -std=c++20 -fclang-abi-compat=latest -fopenmp -fopenmp-version=60 -include-pch %t -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK2 12 13 #ifndef HEADER 14 #define HEADER 15 16 // placeholder for loop body code. 17 extern "C" void body(...) {} 18 19 20 extern "C" void foo1(int start, int end, int step) { 21 int i; 22 #pragma omp interchange permutation(1) 23 for (i = start; i < end; i += step) 24 body(i); 25 } 26 27 28 extern "C" void foo2(int start1, int start2, int end1, int end2, int step1, int step2) { 29 #pragma omp interchange 30 for (int i = start1; i < end1; i += step1) 31 for (int j = start2; j < end2; j += step2) 32 body(i, j); 33 } 34 35 36 extern "C" void foo3() { 37 #pragma omp for 38 #pragma omp interchange 39 for (int i = 7; i < 17; i += 3) 40 for (int j = 7; j < 17; j += 3) 41 body(i, j); 42 } 43 44 45 extern "C" void foo4() { 46 #pragma omp for collapse(2) 47 for (int k = 7; k < 17; k += 3) 48 #pragma omp interchange 49 for (int i = 7; i < 17; i += 3) 50 for (int j = 7; j < 17; j += 3) 51 body(i, j); 52 } 53 54 55 extern "C" void foo5() { 56 #pragma omp for collapse(3) 57 for (int i = 7; i < 17; i += 3) 58 #pragma omp interchange permutation(1) 59 for (int j = 7; j < 17; j += 3) 60 for (int k = 7; k < 17; k += 3) 61 body(i, j, k); 62 } 63 64 65 extern "C" void foo6() { 66 #pragma omp for collapse(4) 67 for (int i = 7; i < 17; i += 3) 68 #pragma omp interchange 69 for (int j = 7; j < 17; j += 3) 70 for (int k = 7; k < 17; k += 3) 71 for (int l = 7; l < 17; l += 3) 72 body(i, j, k, l); 73 } 74 75 76 extern "C" void foo7() { 77 #pragma omp interchange permutation(2,3,4,1) 78 for (int i = 7; i < 17; i += 3) 79 for (int j = 7; j < 17; j += 3) 80 for (int k = 7; k < 17; k += 3) 81 for (int l = 7; l < 17; l += 3) 82 body(i, j, k, l); 83 } 84 85 86 template<int TILESIZE> 87 void foo8(int start, int end, int step) { 88 #pragma omp for collapse(4) 89 for (int i = start; i < end; i += step) 90 #pragma omp interchange permutation(1) 91 for (int j = start; j < end; j += step) 92 #pragma omp tile sizes(TILESIZE) 93 for (int k = start; k < end; k += step) 94 body(i, j, k); 95 } 96 97 // Also test instantiating the template. 98 extern "C" void tfoo8() { 99 foo8<32>(0, 42, 1); 100 foo8<64>(0, 42, 3); 101 } 102 103 104 extern "C" void foo9() { 105 double arr[128]; 106 #pragma omp interchange 107 for (double c = 42; auto && v : arr) 108 for (int i = 0; i < 42; i += 2) 109 body(c, v, i); 110 } 111 112 113 extern "C" void foo10() { 114 double A[128], B[16]; 115 #pragma omp for collapse(4) 116 for (int i = 0; i < 128; ++i) 117 #pragma omp interchange 118 for (double c = 42; auto aa : A) 119 for (double d = 42; auto &bb : B) 120 for (int j = 0; j < 128; ++j) 121 body(i, c, aa, d, bb, j); 122 } 123 124 #endif /* HEADER */ 125 126 // CHECK1-LABEL: define {{[^@]+}}@body 127 // CHECK1-SAME: (...) #[[ATTR0:[0-9]+]] { 128 // CHECK1-NEXT: entry: 129 // CHECK1-NEXT: ret void 130 // 131 // 132 // CHECK1-LABEL: define {{[^@]+}}@foo1 133 // CHECK1-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] { 134 // CHECK1-NEXT: entry: 135 // CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4 136 // CHECK1-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4 137 // CHECK1-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4 138 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 139 // CHECK1-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4 140 // CHECK1-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4 141 // CHECK1-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 4 142 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[START_ADDR]], align 4 143 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[I]], align 4 144 // CHECK1-NEXT: br label [[FOR_COND:%.*]] 145 // CHECK1: for.cond: 146 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4 147 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 4 148 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] 149 // CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 150 // CHECK1: for.body: 151 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[I]], align 4 152 // CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP3]]) 153 // CHECK1-NEXT: br label [[FOR_INC:%.*]] 154 // CHECK1: for.inc: 155 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 156 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4 157 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 158 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 159 // CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 160 // CHECK1: for.end: 161 // CHECK1-NEXT: ret void 162 // 163 // 164 // CHECK1-LABEL: define {{[^@]+}}@foo2 165 // CHECK1-SAME: (i32 noundef [[START1:%.*]], i32 noundef [[START2:%.*]], i32 noundef [[END1:%.*]], i32 noundef [[END2:%.*]], i32 noundef [[STEP1:%.*]], i32 noundef [[STEP2:%.*]]) #[[ATTR0]] { 166 // CHECK1-NEXT: entry: 167 // CHECK1-NEXT: [[START1_ADDR:%.*]] = alloca i32, align 4 168 // CHECK1-NEXT: [[START2_ADDR:%.*]] = alloca i32, align 4 169 // CHECK1-NEXT: [[END1_ADDR:%.*]] = alloca i32, align 4 170 // CHECK1-NEXT: [[END2_ADDR:%.*]] = alloca i32, align 4 171 // CHECK1-NEXT: [[STEP1_ADDR:%.*]] = alloca i32, align 4 172 // CHECK1-NEXT: [[STEP2_ADDR:%.*]] = alloca i32, align 4 173 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 174 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 175 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 176 // CHECK1-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 4 177 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 178 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 179 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 180 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4 181 // CHECK1-NEXT: [[DOTNEW_STEP7:%.*]] = alloca i32, align 4 182 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4 183 // CHECK1-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4 184 // CHECK1-NEXT: [[DOTPERMUTED_1_IV_I:%.*]] = alloca i32, align 4 185 // CHECK1-NEXT: store i32 [[START1]], ptr [[START1_ADDR]], align 4 186 // CHECK1-NEXT: store i32 [[START2]], ptr [[START2_ADDR]], align 4 187 // CHECK1-NEXT: store i32 [[END1]], ptr [[END1_ADDR]], align 4 188 // CHECK1-NEXT: store i32 [[END2]], ptr [[END2_ADDR]], align 4 189 // CHECK1-NEXT: store i32 [[STEP1]], ptr [[STEP1_ADDR]], align 4 190 // CHECK1-NEXT: store i32 [[STEP2]], ptr [[STEP2_ADDR]], align 4 191 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[START1_ADDR]], align 4 192 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[I]], align 4 193 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[START1_ADDR]], align 4 194 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 195 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[END1_ADDR]], align 4 196 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 197 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP1_ADDR]], align 4 198 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 4 199 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 200 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 201 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP4]], [[TMP5]] 202 // CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 203 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 204 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], [[TMP6]] 205 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 206 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP7]] 207 // CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 208 // CHECK1-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4 209 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[START2_ADDR]], align 4 210 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[J]], align 4 211 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[START2_ADDR]], align 4 212 // CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_5]], align 4 213 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[END2_ADDR]], align 4 214 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_6]], align 4 215 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[STEP2_ADDR]], align 4 216 // CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTNEW_STEP7]], align 4 217 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 218 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 219 // CHECK1-NEXT: [[SUB9:%.*]] = sub i32 [[TMP12]], [[TMP13]] 220 // CHECK1-NEXT: [[SUB10:%.*]] = sub i32 [[SUB9]], 1 221 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 222 // CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[SUB10]], [[TMP14]] 223 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 224 // CHECK1-NEXT: [[DIV12:%.*]] = udiv i32 [[ADD11]], [[TMP15]] 225 // CHECK1-NEXT: [[SUB13:%.*]] = sub i32 [[DIV12]], 1 226 // CHECK1-NEXT: store i32 [[SUB13]], ptr [[DOTCAPTURE_EXPR_8]], align 4 227 // CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_0_IV_J]], align 4 228 // CHECK1-NEXT: br label [[FOR_COND:%.*]] 229 // CHECK1: for.cond: 230 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 231 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4 232 // CHECK1-NEXT: [[ADD14:%.*]] = add i32 [[TMP17]], 1 233 // CHECK1-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP16]], [[ADD14]] 234 // CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END24:%.*]] 235 // CHECK1: for.body: 236 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 237 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 238 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 239 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], [[TMP20]] 240 // CHECK1-NEXT: [[ADD15:%.*]] = add i32 [[TMP18]], [[MUL]] 241 // CHECK1-NEXT: store i32 [[ADD15]], ptr [[J]], align 4 242 // CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_I]], align 4 243 // CHECK1-NEXT: br label [[FOR_COND16:%.*]] 244 // CHECK1: for.cond16: 245 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 246 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 247 // CHECK1-NEXT: [[ADD17:%.*]] = add i32 [[TMP22]], 1 248 // CHECK1-NEXT: [[CMP18:%.*]] = icmp ult i32 [[TMP21]], [[ADD17]] 249 // CHECK1-NEXT: br i1 [[CMP18]], label [[FOR_BODY19:%.*]], label [[FOR_END:%.*]] 250 // CHECK1: for.body19: 251 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 252 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 253 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 254 // CHECK1-NEXT: [[MUL20:%.*]] = mul i32 [[TMP24]], [[TMP25]] 255 // CHECK1-NEXT: [[ADD21:%.*]] = add i32 [[TMP23]], [[MUL20]] 256 // CHECK1-NEXT: store i32 [[ADD21]], ptr [[I]], align 4 257 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[I]], align 4 258 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[J]], align 4 259 // CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP26]], i32 noundef [[TMP27]]) 260 // CHECK1-NEXT: br label [[FOR_INC:%.*]] 261 // CHECK1: for.inc: 262 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 263 // CHECK1-NEXT: [[INC:%.*]] = add i32 [[TMP28]], 1 264 // CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4 265 // CHECK1-NEXT: br label [[FOR_COND16]], !llvm.loop [[LOOP5:![0-9]+]] 266 // CHECK1: for.end: 267 // CHECK1-NEXT: br label [[FOR_INC22:%.*]] 268 // CHECK1: for.inc22: 269 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 270 // CHECK1-NEXT: [[INC23:%.*]] = add i32 [[TMP29]], 1 271 // CHECK1-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4 272 // CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 273 // CHECK1: for.end24: 274 // CHECK1-NEXT: ret void 275 // 276 // 277 // CHECK1-LABEL: define {{[^@]+}}@foo3 278 // CHECK1-SAME: () #[[ATTR0]] { 279 // CHECK1-NEXT: entry: 280 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 281 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 282 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 283 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 284 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 285 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 286 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 287 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 288 // CHECK1-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4 289 // CHECK1-NEXT: [[DOTPERMUTED_1_IV_I:%.*]] = alloca i32, align 4 290 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 291 // CHECK1-NEXT: store i32 7, ptr [[I]], align 4 292 // CHECK1-NEXT: store i32 7, ptr [[J]], align 4 293 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 294 // CHECK1-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 295 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 296 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 297 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 298 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 299 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 3 300 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 301 // CHECK1: cond.true: 302 // CHECK1-NEXT: br label [[COND_END:%.*]] 303 // CHECK1: cond.false: 304 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 305 // CHECK1-NEXT: br label [[COND_END]] 306 // CHECK1: cond.end: 307 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] 308 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 309 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 310 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 311 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 312 // CHECK1: omp.inner.for.cond: 313 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 314 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 315 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 316 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 317 // CHECK1: omp.inner.for.body: 318 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 319 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 320 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 321 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTPERMUTED_0_IV_J]], align 4 322 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 323 // CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP7]], 3 324 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 7, [[MUL2]] 325 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[J]], align 4 326 // CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_I]], align 4 327 // CHECK1-NEXT: br label [[FOR_COND:%.*]] 328 // CHECK1: for.cond: 329 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 330 // CHECK1-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP8]], 4 331 // CHECK1-NEXT: br i1 [[CMP4]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 332 // CHECK1: for.body: 333 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 334 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[TMP9]], 3 335 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 7, [[MUL5]] 336 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[I]], align 4 337 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 338 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[J]], align 4 339 // CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP10]], i32 noundef [[TMP11]]) 340 // CHECK1-NEXT: br label [[FOR_INC:%.*]] 341 // CHECK1: for.inc: 342 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 343 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 344 // CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4 345 // CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 346 // CHECK1: for.end: 347 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 348 // CHECK1: omp.body.continue: 349 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 350 // CHECK1: omp.inner.for.inc: 351 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 352 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP13]], 1 353 // CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4 354 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 355 // CHECK1: omp.inner.for.end: 356 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 357 // CHECK1: omp.loop.exit: 358 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) 359 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP0]]) 360 // CHECK1-NEXT: ret void 361 // 362 // 363 // CHECK1-LABEL: define {{[^@]+}}@foo4 364 // CHECK1-SAME: () #[[ATTR0]] { 365 // CHECK1-NEXT: entry: 366 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 367 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 368 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 369 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 370 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 371 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 372 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 373 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 374 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 375 // CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4 376 // CHECK1-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4 377 // CHECK1-NEXT: [[DOTPERMUTED_1_IV_I:%.*]] = alloca i32, align 4 378 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 379 // CHECK1-NEXT: store i32 7, ptr [[I]], align 4 380 // CHECK1-NEXT: store i32 7, ptr [[J]], align 4 381 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 382 // CHECK1-NEXT: store i32 15, ptr [[DOTOMP_UB]], align 4 383 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 384 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 385 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 386 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 387 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 15 388 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 389 // CHECK1: cond.true: 390 // CHECK1-NEXT: br label [[COND_END:%.*]] 391 // CHECK1: cond.false: 392 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 393 // CHECK1-NEXT: br label [[COND_END]] 394 // CHECK1: cond.end: 395 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 15, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] 396 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 397 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 398 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 399 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 400 // CHECK1: omp.inner.for.cond: 401 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 402 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 403 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 404 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 405 // CHECK1: omp.inner.for.body: 406 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 407 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 4 408 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 3 409 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]] 410 // CHECK1-NEXT: store i32 [[ADD]], ptr [[K]], align 4 411 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 412 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 413 // CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP8]], 4 414 // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 4 415 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL4]] 416 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 417 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 418 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTPERMUTED_0_IV_J]], align 4 419 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 420 // CHECK1-NEXT: [[MUL7:%.*]] = mul nsw i32 [[TMP9]], 3 421 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 7, [[MUL7]] 422 // CHECK1-NEXT: store i32 [[ADD8]], ptr [[J]], align 4 423 // CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_I]], align 4 424 // CHECK1-NEXT: br label [[FOR_COND:%.*]] 425 // CHECK1: for.cond: 426 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 427 // CHECK1-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP10]], 4 428 // CHECK1-NEXT: br i1 [[CMP9]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 429 // CHECK1: for.body: 430 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 431 // CHECK1-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP11]], 3 432 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 7, [[MUL10]] 433 // CHECK1-NEXT: store i32 [[ADD11]], ptr [[I]], align 4 434 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 435 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[J]], align 4 436 // CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP12]], i32 noundef [[TMP13]]) 437 // CHECK1-NEXT: br label [[FOR_INC:%.*]] 438 // CHECK1: for.inc: 439 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 440 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 441 // CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4 442 // CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 443 // CHECK1: for.end: 444 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 445 // CHECK1: omp.body.continue: 446 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 447 // CHECK1: omp.inner.for.inc: 448 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 449 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP15]], 1 450 // CHECK1-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4 451 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 452 // CHECK1: omp.inner.for.end: 453 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 454 // CHECK1: omp.loop.exit: 455 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) 456 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) 457 // CHECK1-NEXT: ret void 458 // 459 // 460 // CHECK1-LABEL: define {{[^@]+}}@foo5 461 // CHECK1-SAME: () #[[ATTR0]] { 462 // CHECK1-NEXT: entry: 463 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 464 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 465 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 466 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 467 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 468 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 469 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 470 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 471 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 472 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 473 // CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4 474 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 475 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 476 // CHECK1-NEXT: store i32 63, ptr [[DOTOMP_UB]], align 4 477 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 478 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 479 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 480 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 481 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 63 482 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 483 // CHECK1: cond.true: 484 // CHECK1-NEXT: br label [[COND_END:%.*]] 485 // CHECK1: cond.false: 486 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 487 // CHECK1-NEXT: br label [[COND_END]] 488 // CHECK1: cond.end: 489 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 63, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] 490 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 491 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 492 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 493 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 494 // CHECK1: omp.inner.for.cond: 495 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 496 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 497 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 498 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 499 // CHECK1: omp.inner.for.body: 500 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 501 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 16 502 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 3 503 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]] 504 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 505 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 506 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 507 // CHECK1-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP8]], 16 508 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 16 509 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL5]] 510 // CHECK1-NEXT: [[DIV6:%.*]] = sdiv i32 [[SUB]], 4 511 // CHECK1-NEXT: [[MUL7:%.*]] = mul nsw i32 [[DIV6]], 3 512 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 7, [[MUL7]] 513 // CHECK1-NEXT: store i32 [[ADD8]], ptr [[J]], align 4 514 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 515 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 516 // CHECK1-NEXT: [[DIV9:%.*]] = sdiv i32 [[TMP10]], 16 517 // CHECK1-NEXT: [[MUL10:%.*]] = mul nsw i32 [[DIV9]], 16 518 // CHECK1-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP9]], [[MUL10]] 519 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 520 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 521 // CHECK1-NEXT: [[DIV12:%.*]] = sdiv i32 [[TMP12]], 16 522 // CHECK1-NEXT: [[MUL13:%.*]] = mul nsw i32 [[DIV12]], 16 523 // CHECK1-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP11]], [[MUL13]] 524 // CHECK1-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 4 525 // CHECK1-NEXT: [[MUL16:%.*]] = mul nsw i32 [[DIV15]], 4 526 // CHECK1-NEXT: [[SUB17:%.*]] = sub nsw i32 [[SUB11]], [[MUL16]] 527 // CHECK1-NEXT: [[MUL18:%.*]] = mul nsw i32 [[SUB17]], 3 528 // CHECK1-NEXT: [[ADD19:%.*]] = add nsw i32 7, [[MUL18]] 529 // CHECK1-NEXT: store i32 [[ADD19]], ptr [[K]], align 4 530 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 531 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4 532 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[K]], align 4 533 // CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP13]], i32 noundef [[TMP14]], i32 noundef [[TMP15]]) 534 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 535 // CHECK1: omp.body.continue: 536 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 537 // CHECK1: omp.inner.for.inc: 538 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 539 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP16]], 1 540 // CHECK1-NEXT: store i32 [[ADD20]], ptr [[DOTOMP_IV]], align 4 541 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 542 // CHECK1: omp.inner.for.end: 543 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 544 // CHECK1: omp.loop.exit: 545 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) 546 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) 547 // CHECK1-NEXT: ret void 548 // 549 // 550 // CHECK1-LABEL: define {{[^@]+}}@foo6 551 // CHECK1-SAME: () #[[ATTR0]] { 552 // CHECK1-NEXT: entry: 553 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 554 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 555 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 556 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 557 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 558 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 559 // CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4 560 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 561 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 562 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 563 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 564 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 565 // CHECK1-NEXT: [[DOTPERMUTED_0_IV_K:%.*]] = alloca i32, align 4 566 // CHECK1-NEXT: [[DOTPERMUTED_1_IV_J:%.*]] = alloca i32, align 4 567 // CHECK1-NEXT: [[L:%.*]] = alloca i32, align 4 568 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 569 // CHECK1-NEXT: store i32 7, ptr [[J]], align 4 570 // CHECK1-NEXT: store i32 7, ptr [[K]], align 4 571 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 572 // CHECK1-NEXT: store i32 255, ptr [[DOTOMP_UB]], align 4 573 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 574 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 575 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 576 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 577 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 255 578 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 579 // CHECK1: cond.true: 580 // CHECK1-NEXT: br label [[COND_END:%.*]] 581 // CHECK1: cond.false: 582 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 583 // CHECK1-NEXT: br label [[COND_END]] 584 // CHECK1: cond.end: 585 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 255, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] 586 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 587 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 588 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 589 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 590 // CHECK1: omp.inner.for.cond: 591 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 592 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 593 // CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 594 // CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 595 // CHECK1: omp.inner.for.body: 596 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 597 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 64 598 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 3 599 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]] 600 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 601 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 602 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 603 // CHECK1-NEXT: [[DIV5:%.*]] = sdiv i32 [[TMP8]], 64 604 // CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[DIV5]], 64 605 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL6]] 606 // CHECK1-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB]], 16 607 // CHECK1-NEXT: [[MUL8:%.*]] = mul nsw i32 [[DIV7]], 1 608 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]] 609 // CHECK1-NEXT: store i32 [[ADD9]], ptr [[DOTPERMUTED_0_IV_K]], align 4 610 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 611 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 612 // CHECK1-NEXT: [[DIV10:%.*]] = sdiv i32 [[TMP10]], 64 613 // CHECK1-NEXT: [[MUL11:%.*]] = mul nsw i32 [[DIV10]], 64 614 // CHECK1-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP9]], [[MUL11]] 615 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 616 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 617 // CHECK1-NEXT: [[DIV13:%.*]] = sdiv i32 [[TMP12]], 64 618 // CHECK1-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 64 619 // CHECK1-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP11]], [[MUL14]] 620 // CHECK1-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 16 621 // CHECK1-NEXT: [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 16 622 // CHECK1-NEXT: [[SUB18:%.*]] = sub nsw i32 [[SUB12]], [[MUL17]] 623 // CHECK1-NEXT: [[DIV19:%.*]] = sdiv i32 [[SUB18]], 4 624 // CHECK1-NEXT: [[MUL20:%.*]] = mul nsw i32 [[DIV19]], 1 625 // CHECK1-NEXT: [[ADD21:%.*]] = add nsw i32 0, [[MUL20]] 626 // CHECK1-NEXT: store i32 [[ADD21]], ptr [[DOTPERMUTED_1_IV_J]], align 4 627 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 628 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 629 // CHECK1-NEXT: [[DIV22:%.*]] = sdiv i32 [[TMP14]], 64 630 // CHECK1-NEXT: [[MUL23:%.*]] = mul nsw i32 [[DIV22]], 64 631 // CHECK1-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP13]], [[MUL23]] 632 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 633 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 634 // CHECK1-NEXT: [[DIV25:%.*]] = sdiv i32 [[TMP16]], 64 635 // CHECK1-NEXT: [[MUL26:%.*]] = mul nsw i32 [[DIV25]], 64 636 // CHECK1-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP15]], [[MUL26]] 637 // CHECK1-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 16 638 // CHECK1-NEXT: [[MUL29:%.*]] = mul nsw i32 [[DIV28]], 16 639 // CHECK1-NEXT: [[SUB30:%.*]] = sub nsw i32 [[SUB24]], [[MUL29]] 640 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 641 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 642 // CHECK1-NEXT: [[DIV31:%.*]] = sdiv i32 [[TMP18]], 64 643 // CHECK1-NEXT: [[MUL32:%.*]] = mul nsw i32 [[DIV31]], 64 644 // CHECK1-NEXT: [[SUB33:%.*]] = sub nsw i32 [[TMP17]], [[MUL32]] 645 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 646 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 647 // CHECK1-NEXT: [[DIV34:%.*]] = sdiv i32 [[TMP20]], 64 648 // CHECK1-NEXT: [[MUL35:%.*]] = mul nsw i32 [[DIV34]], 64 649 // CHECK1-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP19]], [[MUL35]] 650 // CHECK1-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 16 651 // CHECK1-NEXT: [[MUL38:%.*]] = mul nsw i32 [[DIV37]], 16 652 // CHECK1-NEXT: [[SUB39:%.*]] = sub nsw i32 [[SUB33]], [[MUL38]] 653 // CHECK1-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 4 654 // CHECK1-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 4 655 // CHECK1-NEXT: [[SUB42:%.*]] = sub nsw i32 [[SUB30]], [[MUL41]] 656 // CHECK1-NEXT: [[MUL43:%.*]] = mul nsw i32 [[SUB42]], 3 657 // CHECK1-NEXT: [[ADD44:%.*]] = add nsw i32 7, [[MUL43]] 658 // CHECK1-NEXT: store i32 [[ADD44]], ptr [[L]], align 4 659 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_K]], align 4 660 // CHECK1-NEXT: [[MUL45:%.*]] = mul nsw i32 [[TMP21]], 3 661 // CHECK1-NEXT: [[ADD46:%.*]] = add nsw i32 7, [[MUL45]] 662 // CHECK1-NEXT: store i32 [[ADD46]], ptr [[K]], align 4 663 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_J]], align 4 664 // CHECK1-NEXT: [[MUL47:%.*]] = mul nsw i32 [[TMP22]], 3 665 // CHECK1-NEXT: [[ADD48:%.*]] = add nsw i32 7, [[MUL47]] 666 // CHECK1-NEXT: store i32 [[ADD48]], ptr [[J]], align 4 667 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4 668 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[J]], align 4 669 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[K]], align 4 670 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[L]], align 4 671 // CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP23]], i32 noundef [[TMP24]], i32 noundef [[TMP25]], i32 noundef [[TMP26]]) 672 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 673 // CHECK1: omp.body.continue: 674 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 675 // CHECK1: omp.inner.for.inc: 676 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 677 // CHECK1-NEXT: [[ADD49:%.*]] = add nsw i32 [[TMP27]], 1 678 // CHECK1-NEXT: store i32 [[ADD49]], ptr [[DOTOMP_IV]], align 4 679 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 680 // CHECK1: omp.inner.for.end: 681 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 682 // CHECK1: omp.loop.exit: 683 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) 684 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) 685 // CHECK1-NEXT: ret void 686 // 687 // 688 // CHECK1-LABEL: define {{[^@]+}}@foo7 689 // CHECK1-SAME: () #[[ATTR0]] { 690 // CHECK1-NEXT: entry: 691 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 692 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 693 // CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4 694 // CHECK1-NEXT: [[L:%.*]] = alloca i32, align 4 695 // CHECK1-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4 696 // CHECK1-NEXT: [[DOTPERMUTED_1_IV_K:%.*]] = alloca i32, align 4 697 // CHECK1-NEXT: [[DOTPERMUTED_2_IV_L:%.*]] = alloca i32, align 4 698 // CHECK1-NEXT: [[DOTPERMUTED_3_IV_I:%.*]] = alloca i32, align 4 699 // CHECK1-NEXT: store i32 7, ptr [[I]], align 4 700 // CHECK1-NEXT: store i32 7, ptr [[J]], align 4 701 // CHECK1-NEXT: store i32 7, ptr [[K]], align 4 702 // CHECK1-NEXT: store i32 7, ptr [[L]], align 4 703 // CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_0_IV_J]], align 4 704 // CHECK1-NEXT: br label [[FOR_COND:%.*]] 705 // CHECK1: for.cond: 706 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 707 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 4 708 // CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END24:%.*]] 709 // CHECK1: for.body: 710 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 711 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 3 712 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]] 713 // CHECK1-NEXT: store i32 [[ADD]], ptr [[J]], align 4 714 // CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_K]], align 4 715 // CHECK1-NEXT: br label [[FOR_COND1:%.*]] 716 // CHECK1: for.cond1: 717 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 4 718 // CHECK1-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP2]], 4 719 // CHECK1-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END21:%.*]] 720 // CHECK1: for.body3: 721 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 4 722 // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[TMP3]], 3 723 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 7, [[MUL4]] 724 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[K]], align 4 725 // CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_2_IV_L]], align 4 726 // CHECK1-NEXT: br label [[FOR_COND6:%.*]] 727 // CHECK1: for.cond6: 728 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 4 729 // CHECK1-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP4]], 4 730 // CHECK1-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END18:%.*]] 731 // CHECK1: for.body8: 732 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 4 733 // CHECK1-NEXT: [[MUL9:%.*]] = mul nsw i32 [[TMP5]], 3 734 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 7, [[MUL9]] 735 // CHECK1-NEXT: store i32 [[ADD10]], ptr [[L]], align 4 736 // CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_3_IV_I]], align 4 737 // CHECK1-NEXT: br label [[FOR_COND11:%.*]] 738 // CHECK1: for.cond11: 739 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 4 740 // CHECK1-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP6]], 4 741 // CHECK1-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END:%.*]] 742 // CHECK1: for.body13: 743 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 4 744 // CHECK1-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP7]], 3 745 // CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 7, [[MUL14]] 746 // CHECK1-NEXT: store i32 [[ADD15]], ptr [[I]], align 4 747 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4 748 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[J]], align 4 749 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[K]], align 4 750 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[L]], align 4 751 // CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP8]], i32 noundef [[TMP9]], i32 noundef [[TMP10]], i32 noundef [[TMP11]]) 752 // CHECK1-NEXT: br label [[FOR_INC:%.*]] 753 // CHECK1: for.inc: 754 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 4 755 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 756 // CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_3_IV_I]], align 4 757 // CHECK1-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP9:![0-9]+]] 758 // CHECK1: for.end: 759 // CHECK1-NEXT: br label [[FOR_INC16:%.*]] 760 // CHECK1: for.inc16: 761 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 4 762 // CHECK1-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 763 // CHECK1-NEXT: store i32 [[INC17]], ptr [[DOTPERMUTED_2_IV_L]], align 4 764 // CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP10:![0-9]+]] 765 // CHECK1: for.end18: 766 // CHECK1-NEXT: br label [[FOR_INC19:%.*]] 767 // CHECK1: for.inc19: 768 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 4 769 // CHECK1-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP14]], 1 770 // CHECK1-NEXT: store i32 [[INC20]], ptr [[DOTPERMUTED_1_IV_K]], align 4 771 // CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]] 772 // CHECK1: for.end21: 773 // CHECK1-NEXT: br label [[FOR_INC22:%.*]] 774 // CHECK1: for.inc22: 775 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 776 // CHECK1-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1 777 // CHECK1-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4 778 // CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 779 // CHECK1: for.end24: 780 // CHECK1-NEXT: ret void 781 // 782 // 783 // CHECK1-LABEL: define {{[^@]+}}@tfoo8 784 // CHECK1-SAME: () #[[ATTR0]] { 785 // CHECK1-NEXT: entry: 786 // CHECK1-NEXT: call void @_Z4foo8ILi32EEviii(i32 noundef 0, i32 noundef 42, i32 noundef 1) 787 // CHECK1-NEXT: call void @_Z4foo8ILi64EEviii(i32 noundef 0, i32 noundef 42, i32 noundef 3) 788 // CHECK1-NEXT: ret void 789 // 790 // 791 // CHECK1-LABEL: define {{[^@]+}}@_Z4foo8ILi32EEviii 792 // CHECK1-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] comdat { 793 // CHECK1-NEXT: entry: 794 // CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4 795 // CHECK1-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4 796 // CHECK1-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4 797 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 798 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 799 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 800 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 801 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 802 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 803 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 804 // CHECK1-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 4 805 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 806 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4 807 // CHECK1-NEXT: [[DOTNEW_STEP7:%.*]] = alloca i32, align 4 808 // CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4 809 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4 810 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 811 // CHECK1-NEXT: [[DOTNEW_STEP10:%.*]] = alloca i32, align 4 812 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 813 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 4 814 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4 815 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 816 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 8 817 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 818 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 819 // CHECK1-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 4 820 // CHECK1-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4 821 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 822 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 823 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 824 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 825 // CHECK1-NEXT: [[I49:%.*]] = alloca i32, align 4 826 // CHECK1-NEXT: [[J50:%.*]] = alloca i32, align 4 827 // CHECK1-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 4 828 // CHECK1-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 4 829 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 830 // CHECK1-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4 831 // CHECK1-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4 832 // CHECK1-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 4 833 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[START_ADDR]], align 4 834 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 835 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 4 836 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_4]], align 4 837 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 838 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 4 839 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[START_ADDR]], align 4 840 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_5]], align 4 841 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[END_ADDR]], align 4 842 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_6]], align 4 843 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 844 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTNEW_STEP7]], align 4 845 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[START_ADDR]], align 4 846 // CHECK1-NEXT: store i32 [[TMP7]], ptr [[K]], align 4 847 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[START_ADDR]], align 4 848 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_8]], align 4 849 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[END_ADDR]], align 4 850 // CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_9]], align 4 851 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 852 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTNEW_STEP10]], align 4 853 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_9]], align 4 854 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4 855 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP11]], [[TMP12]] 856 // CHECK1-NEXT: [[SUB12:%.*]] = sub i32 [[SUB]], 1 857 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 858 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB12]], [[TMP13]] 859 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 860 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP14]] 861 // CHECK1-NEXT: [[SUB13:%.*]] = sub i32 [[DIV]], 1 862 // CHECK1-NEXT: store i32 [[SUB13]], ptr [[DOTCAPTURE_EXPR_11]], align 4 863 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 864 // CHECK1-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], 1 865 // CHECK1-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 4 866 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 4 867 // CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 4 868 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 869 // CHECK1-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 1 870 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 4 871 // CHECK1-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 32 872 // CHECK1-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]] 873 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 874 // CHECK1: cond.true: 875 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 876 // CHECK1-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 1 877 // CHECK1-NEXT: br label [[COND_END:%.*]] 878 // CHECK1: cond.false: 879 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 4 880 // CHECK1-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 32 881 // CHECK1-NEXT: br label [[COND_END]] 882 // CHECK1: cond.end: 883 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ] 884 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 4 885 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 886 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 887 // CHECK1-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]] 888 // CHECK1-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 1 889 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 890 // CHECK1-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]] 891 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 892 // CHECK1-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]] 893 // CHECK1-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i64 894 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 895 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 896 // CHECK1-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]] 897 // CHECK1-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 1 898 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 899 // CHECK1-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]] 900 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 901 // CHECK1-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]] 902 // CHECK1-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i64 903 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]] 904 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 905 // CHECK1-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -31 906 // CHECK1-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 32 907 // CHECK1-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i64 908 // CHECK1-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]] 909 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 910 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 911 // CHECK1-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]] 912 // CHECK1-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 1 913 // CHECK1-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 1 914 // CHECK1-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 1 915 // CHECK1-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i64 916 // CHECK1-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]] 917 // CHECK1-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 1 918 // CHECK1-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 8 919 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 920 // CHECK1-NEXT: store i32 [[TMP32]], ptr [[I]], align 4 921 // CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 922 // CHECK1-NEXT: store i32 [[TMP33]], ptr [[J]], align 4 923 // CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 4 924 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 925 // CHECK1-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 4 926 // CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 927 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 928 // CHECK1-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]] 929 // CHECK1-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 930 // CHECK1: land.lhs.true: 931 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 932 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 933 // CHECK1-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]] 934 // CHECK1-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]] 935 // CHECK1: land.lhs.true45: 936 // CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 937 // CHECK1-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]] 938 // CHECK1-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]] 939 // CHECK1: land.lhs.true47: 940 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 941 // CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 942 // CHECK1-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]] 943 // CHECK1-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 944 // CHECK1: omp.precond.then: 945 // CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 946 // CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 947 // CHECK1-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 8 948 // CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 949 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 950 // CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 951 // CHECK1-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 952 // CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 953 // CHECK1-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]] 954 // CHECK1-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]] 955 // CHECK1: cond.true54: 956 // CHECK1-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 957 // CHECK1-NEXT: br label [[COND_END56:%.*]] 958 // CHECK1: cond.false55: 959 // CHECK1-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 960 // CHECK1-NEXT: br label [[COND_END56]] 961 // CHECK1: cond.end56: 962 // CHECK1-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ] 963 // CHECK1-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 8 964 // CHECK1-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 965 // CHECK1-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 8 966 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 967 // CHECK1: omp.inner.for.cond: 968 // CHECK1-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 969 // CHECK1-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 970 // CHECK1-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]] 971 // CHECK1-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 972 // CHECK1: omp.inner.for.body: 973 // CHECK1-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 974 // CHECK1-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i64 975 // CHECK1-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 976 // CHECK1-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 977 // CHECK1-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 978 // CHECK1-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]] 979 // CHECK1-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 1 980 // CHECK1-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 981 // CHECK1-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]] 982 // CHECK1-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 983 // CHECK1-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]] 984 // CHECK1-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]] 985 // CHECK1-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 986 // CHECK1-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -31 987 // CHECK1-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 32 988 // CHECK1-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]] 989 // CHECK1-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 990 // CHECK1-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 991 // CHECK1-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]] 992 // CHECK1-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 1 993 // CHECK1-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 1 994 // CHECK1-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 1 995 // CHECK1-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]] 996 // CHECK1-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i64 997 // CHECK1-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]] 998 // CHECK1-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 999 // CHECK1-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i64 1000 // CHECK1-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]] 1001 // CHECK1-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]] 1002 // CHECK1-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i32 1003 // CHECK1-NEXT: store i32 [[CONV78]], ptr [[I49]], align 4 1004 // CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1005 // CHECK1-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i64 1006 // CHECK1-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1007 // CHECK1-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1008 // CHECK1-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1009 // CHECK1-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1010 // CHECK1-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]] 1011 // CHECK1-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 1 1012 // CHECK1-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1013 // CHECK1-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]] 1014 // CHECK1-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1015 // CHECK1-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]] 1016 // CHECK1-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]] 1017 // CHECK1-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1018 // CHECK1-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -31 1019 // CHECK1-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 32 1020 // CHECK1-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]] 1021 // CHECK1-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1022 // CHECK1-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1023 // CHECK1-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]] 1024 // CHECK1-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 1 1025 // CHECK1-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 1 1026 // CHECK1-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 1 1027 // CHECK1-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]] 1028 // CHECK1-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i64 1029 // CHECK1-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]] 1030 // CHECK1-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1031 // CHECK1-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1032 // CHECK1-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]] 1033 // CHECK1-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 1 1034 // CHECK1-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1035 // CHECK1-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]] 1036 // CHECK1-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1037 // CHECK1-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]] 1038 // CHECK1-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]] 1039 // CHECK1-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1040 // CHECK1-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -31 1041 // CHECK1-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 32 1042 // CHECK1-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]] 1043 // CHECK1-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1044 // CHECK1-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1045 // CHECK1-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]] 1046 // CHECK1-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 1 1047 // CHECK1-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 1 1048 // CHECK1-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 1 1049 // CHECK1-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]] 1050 // CHECK1-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i64 1051 // CHECK1-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]] 1052 // CHECK1-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]] 1053 // CHECK1-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1054 // CHECK1-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -31 1055 // CHECK1-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 32 1056 // CHECK1-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]] 1057 // CHECK1-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1058 // CHECK1-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1059 // CHECK1-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]] 1060 // CHECK1-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 1 1061 // CHECK1-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 1 1062 // CHECK1-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 1 1063 // CHECK1-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]] 1064 // CHECK1-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i64 1065 // CHECK1-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]] 1066 // CHECK1-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1067 // CHECK1-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i64 1068 // CHECK1-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]] 1069 // CHECK1-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]] 1070 // CHECK1-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i32 1071 // CHECK1-NEXT: store i32 [[CONV124]], ptr [[J50]], align 4 1072 // CHECK1-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1073 // CHECK1-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1074 // CHECK1-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1075 // CHECK1-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1076 // CHECK1-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]] 1077 // CHECK1-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 1 1078 // CHECK1-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1079 // CHECK1-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]] 1080 // CHECK1-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1081 // CHECK1-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]] 1082 // CHECK1-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]] 1083 // CHECK1-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1084 // CHECK1-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -31 1085 // CHECK1-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 32 1086 // CHECK1-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]] 1087 // CHECK1-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1088 // CHECK1-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1089 // CHECK1-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]] 1090 // CHECK1-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 1 1091 // CHECK1-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 1 1092 // CHECK1-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 1 1093 // CHECK1-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]] 1094 // CHECK1-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i64 1095 // CHECK1-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]] 1096 // CHECK1-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1097 // CHECK1-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1098 // CHECK1-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]] 1099 // CHECK1-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 1 1100 // CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1101 // CHECK1-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]] 1102 // CHECK1-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1103 // CHECK1-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]] 1104 // CHECK1-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]] 1105 // CHECK1-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1106 // CHECK1-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -31 1107 // CHECK1-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 32 1108 // CHECK1-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]] 1109 // CHECK1-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1110 // CHECK1-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1111 // CHECK1-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]] 1112 // CHECK1-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 1 1113 // CHECK1-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 1 1114 // CHECK1-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 1 1115 // CHECK1-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]] 1116 // CHECK1-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i64 1117 // CHECK1-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]] 1118 // CHECK1-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]] 1119 // CHECK1-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1120 // CHECK1-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1121 // CHECK1-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1122 // CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1123 // CHECK1-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]] 1124 // CHECK1-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 1 1125 // CHECK1-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1126 // CHECK1-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]] 1127 // CHECK1-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1128 // CHECK1-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]] 1129 // CHECK1-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]] 1130 // CHECK1-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1131 // CHECK1-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -31 1132 // CHECK1-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 32 1133 // CHECK1-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]] 1134 // CHECK1-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1135 // CHECK1-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1136 // CHECK1-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]] 1137 // CHECK1-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 1 1138 // CHECK1-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 1 1139 // CHECK1-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 1 1140 // CHECK1-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]] 1141 // CHECK1-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i64 1142 // CHECK1-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]] 1143 // CHECK1-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1144 // CHECK1-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1145 // CHECK1-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]] 1146 // CHECK1-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 1 1147 // CHECK1-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1148 // CHECK1-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]] 1149 // CHECK1-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1150 // CHECK1-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]] 1151 // CHECK1-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]] 1152 // CHECK1-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1153 // CHECK1-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -31 1154 // CHECK1-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 32 1155 // CHECK1-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]] 1156 // CHECK1-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1157 // CHECK1-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1158 // CHECK1-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]] 1159 // CHECK1-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 1 1160 // CHECK1-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 1 1161 // CHECK1-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 1 1162 // CHECK1-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]] 1163 // CHECK1-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i64 1164 // CHECK1-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]] 1165 // CHECK1-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]] 1166 // CHECK1-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1167 // CHECK1-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -31 1168 // CHECK1-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 32 1169 // CHECK1-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]] 1170 // CHECK1-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1171 // CHECK1-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1172 // CHECK1-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]] 1173 // CHECK1-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 1 1174 // CHECK1-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 1 1175 // CHECK1-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 1 1176 // CHECK1-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]] 1177 // CHECK1-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i64 1178 // CHECK1-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]] 1179 // CHECK1-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1180 // CHECK1-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -31 1181 // CHECK1-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 32 1182 // CHECK1-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]] 1183 // CHECK1-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1184 // CHECK1-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1185 // CHECK1-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]] 1186 // CHECK1-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 1 1187 // CHECK1-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 1 1188 // CHECK1-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 1 1189 // CHECK1-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]] 1190 // CHECK1-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i64 1191 // CHECK1-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]] 1192 // CHECK1-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]] 1193 // CHECK1-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1194 // CHECK1-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1195 // CHECK1-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]] 1196 // CHECK1-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 1 1197 // CHECK1-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 1 1198 // CHECK1-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 1 1199 // CHECK1-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]] 1200 // CHECK1-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i64 1201 // CHECK1-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]] 1202 // CHECK1-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 32 1203 // CHECK1-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]] 1204 // CHECK1-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i32 1205 // CHECK1-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 4 1206 // CHECK1-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1207 // CHECK1-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i64 1208 // CHECK1-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1209 // CHECK1-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1210 // CHECK1-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1211 // CHECK1-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1212 // CHECK1-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]] 1213 // CHECK1-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 1 1214 // CHECK1-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1215 // CHECK1-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]] 1216 // CHECK1-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1217 // CHECK1-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]] 1218 // CHECK1-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]] 1219 // CHECK1-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1220 // CHECK1-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -31 1221 // CHECK1-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 32 1222 // CHECK1-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]] 1223 // CHECK1-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1224 // CHECK1-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1225 // CHECK1-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]] 1226 // CHECK1-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 1 1227 // CHECK1-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 1 1228 // CHECK1-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 1 1229 // CHECK1-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]] 1230 // CHECK1-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i64 1231 // CHECK1-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]] 1232 // CHECK1-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1233 // CHECK1-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1234 // CHECK1-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]] 1235 // CHECK1-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 1 1236 // CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1237 // CHECK1-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]] 1238 // CHECK1-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1239 // CHECK1-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]] 1240 // CHECK1-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]] 1241 // CHECK1-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1242 // CHECK1-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -31 1243 // CHECK1-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 32 1244 // CHECK1-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]] 1245 // CHECK1-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1246 // CHECK1-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1247 // CHECK1-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]] 1248 // CHECK1-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 1 1249 // CHECK1-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 1 1250 // CHECK1-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 1 1251 // CHECK1-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]] 1252 // CHECK1-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i64 1253 // CHECK1-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]] 1254 // CHECK1-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]] 1255 // CHECK1-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1256 // CHECK1-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1257 // CHECK1-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1258 // CHECK1-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1259 // CHECK1-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]] 1260 // CHECK1-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 1 1261 // CHECK1-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1262 // CHECK1-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]] 1263 // CHECK1-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1264 // CHECK1-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]] 1265 // CHECK1-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]] 1266 // CHECK1-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1267 // CHECK1-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -31 1268 // CHECK1-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 32 1269 // CHECK1-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]] 1270 // CHECK1-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1271 // CHECK1-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1272 // CHECK1-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]] 1273 // CHECK1-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 1 1274 // CHECK1-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 1 1275 // CHECK1-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 1 1276 // CHECK1-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]] 1277 // CHECK1-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i64 1278 // CHECK1-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]] 1279 // CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1280 // CHECK1-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1281 // CHECK1-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]] 1282 // CHECK1-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 1 1283 // CHECK1-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1284 // CHECK1-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]] 1285 // CHECK1-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1286 // CHECK1-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]] 1287 // CHECK1-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]] 1288 // CHECK1-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1289 // CHECK1-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -31 1290 // CHECK1-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 32 1291 // CHECK1-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]] 1292 // CHECK1-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1293 // CHECK1-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1294 // CHECK1-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]] 1295 // CHECK1-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 1 1296 // CHECK1-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 1 1297 // CHECK1-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 1 1298 // CHECK1-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]] 1299 // CHECK1-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i64 1300 // CHECK1-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]] 1301 // CHECK1-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]] 1302 // CHECK1-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1303 // CHECK1-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -31 1304 // CHECK1-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 32 1305 // CHECK1-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]] 1306 // CHECK1-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1307 // CHECK1-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1308 // CHECK1-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]] 1309 // CHECK1-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 1 1310 // CHECK1-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 1 1311 // CHECK1-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 1 1312 // CHECK1-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]] 1313 // CHECK1-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i64 1314 // CHECK1-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]] 1315 // CHECK1-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1316 // CHECK1-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -31 1317 // CHECK1-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 32 1318 // CHECK1-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]] 1319 // CHECK1-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1320 // CHECK1-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1321 // CHECK1-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]] 1322 // CHECK1-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 1 1323 // CHECK1-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 1 1324 // CHECK1-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 1 1325 // CHECK1-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]] 1326 // CHECK1-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i64 1327 // CHECK1-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]] 1328 // CHECK1-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]] 1329 // CHECK1-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1330 // CHECK1-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1331 // CHECK1-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1332 // CHECK1-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1333 // CHECK1-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]] 1334 // CHECK1-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 1 1335 // CHECK1-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1336 // CHECK1-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]] 1337 // CHECK1-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1338 // CHECK1-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]] 1339 // CHECK1-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]] 1340 // CHECK1-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1341 // CHECK1-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -31 1342 // CHECK1-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 32 1343 // CHECK1-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]] 1344 // CHECK1-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1345 // CHECK1-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1346 // CHECK1-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]] 1347 // CHECK1-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 1 1348 // CHECK1-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 1 1349 // CHECK1-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 1 1350 // CHECK1-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]] 1351 // CHECK1-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i64 1352 // CHECK1-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]] 1353 // CHECK1-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1354 // CHECK1-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1355 // CHECK1-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]] 1356 // CHECK1-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 1 1357 // CHECK1-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1358 // CHECK1-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]] 1359 // CHECK1-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1360 // CHECK1-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]] 1361 // CHECK1-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]] 1362 // CHECK1-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1363 // CHECK1-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -31 1364 // CHECK1-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 32 1365 // CHECK1-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]] 1366 // CHECK1-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1367 // CHECK1-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1368 // CHECK1-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]] 1369 // CHECK1-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 1 1370 // CHECK1-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 1 1371 // CHECK1-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 1 1372 // CHECK1-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]] 1373 // CHECK1-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i64 1374 // CHECK1-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]] 1375 // CHECK1-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]] 1376 // CHECK1-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1377 // CHECK1-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1378 // CHECK1-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1379 // CHECK1-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1380 // CHECK1-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]] 1381 // CHECK1-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 1 1382 // CHECK1-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1383 // CHECK1-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]] 1384 // CHECK1-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1385 // CHECK1-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]] 1386 // CHECK1-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]] 1387 // CHECK1-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1388 // CHECK1-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -31 1389 // CHECK1-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 32 1390 // CHECK1-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]] 1391 // CHECK1-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1392 // CHECK1-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1393 // CHECK1-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]] 1394 // CHECK1-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 1 1395 // CHECK1-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 1 1396 // CHECK1-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 1 1397 // CHECK1-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]] 1398 // CHECK1-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i64 1399 // CHECK1-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]] 1400 // CHECK1-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1401 // CHECK1-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1402 // CHECK1-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]] 1403 // CHECK1-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 1 1404 // CHECK1-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1405 // CHECK1-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]] 1406 // CHECK1-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1407 // CHECK1-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]] 1408 // CHECK1-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]] 1409 // CHECK1-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1410 // CHECK1-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -31 1411 // CHECK1-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 32 1412 // CHECK1-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]] 1413 // CHECK1-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1414 // CHECK1-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1415 // CHECK1-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]] 1416 // CHECK1-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 1 1417 // CHECK1-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 1 1418 // CHECK1-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 1 1419 // CHECK1-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]] 1420 // CHECK1-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i64 1421 // CHECK1-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]] 1422 // CHECK1-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]] 1423 // CHECK1-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1424 // CHECK1-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -31 1425 // CHECK1-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 32 1426 // CHECK1-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]] 1427 // CHECK1-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1428 // CHECK1-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1429 // CHECK1-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]] 1430 // CHECK1-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 1 1431 // CHECK1-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 1 1432 // CHECK1-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 1 1433 // CHECK1-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]] 1434 // CHECK1-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i64 1435 // CHECK1-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]] 1436 // CHECK1-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1437 // CHECK1-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -31 1438 // CHECK1-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 32 1439 // CHECK1-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]] 1440 // CHECK1-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1441 // CHECK1-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1442 // CHECK1-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]] 1443 // CHECK1-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 1 1444 // CHECK1-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 1 1445 // CHECK1-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 1 1446 // CHECK1-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]] 1447 // CHECK1-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i64 1448 // CHECK1-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]] 1449 // CHECK1-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]] 1450 // CHECK1-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1451 // CHECK1-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1452 // CHECK1-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]] 1453 // CHECK1-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 1 1454 // CHECK1-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 1 1455 // CHECK1-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 1 1456 // CHECK1-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]] 1457 // CHECK1-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i64 1458 // CHECK1-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]] 1459 // CHECK1-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1460 // CHECK1-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1461 // CHECK1-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]] 1462 // CHECK1-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 1 1463 // CHECK1-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 1 1464 // CHECK1-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 1 1465 // CHECK1-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]] 1466 // CHECK1-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i64 1467 // CHECK1-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]] 1468 // CHECK1-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]] 1469 // CHECK1-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 1 1470 // CHECK1-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]] 1471 // CHECK1-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i32 1472 // CHECK1-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 4 1473 // CHECK1-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4 1474 // CHECK1-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 4 1475 // CHECK1-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 1476 // CHECK1-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]] 1477 // CHECK1-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]] 1478 // CHECK1-NEXT: store i32 [[ADD404]], ptr [[K]], align 4 1479 // CHECK1-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 4 1480 // CHECK1-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 4 1481 // CHECK1-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 4 1482 // CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]]) 1483 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1484 // CHECK1: omp.body.continue: 1485 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1486 // CHECK1: omp.inner.for.inc: 1487 // CHECK1-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1488 // CHECK1-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 1 1489 // CHECK1-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 8 1490 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1491 // CHECK1: omp.inner.for.end: 1492 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1493 // CHECK1: omp.loop.exit: 1494 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) 1495 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 1496 // CHECK1: omp.precond.end: 1497 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) 1498 // CHECK1-NEXT: ret void 1499 // 1500 // 1501 // CHECK1-LABEL: define {{[^@]+}}@_Z4foo8ILi64EEviii 1502 // CHECK1-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] comdat { 1503 // CHECK1-NEXT: entry: 1504 // CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4 1505 // CHECK1-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4 1506 // CHECK1-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4 1507 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1508 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1509 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1510 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 1511 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 1512 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1513 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 1514 // CHECK1-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 4 1515 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 1516 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4 1517 // CHECK1-NEXT: [[DOTNEW_STEP7:%.*]] = alloca i32, align 4 1518 // CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4 1519 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4 1520 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 1521 // CHECK1-NEXT: [[DOTNEW_STEP10:%.*]] = alloca i32, align 4 1522 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 1523 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 4 1524 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4 1525 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 1526 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 8 1527 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1528 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 1529 // CHECK1-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 4 1530 // CHECK1-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4 1531 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1532 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1533 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1534 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1535 // CHECK1-NEXT: [[I49:%.*]] = alloca i32, align 4 1536 // CHECK1-NEXT: [[J50:%.*]] = alloca i32, align 4 1537 // CHECK1-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 4 1538 // CHECK1-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 4 1539 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 1540 // CHECK1-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4 1541 // CHECK1-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4 1542 // CHECK1-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 4 1543 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[START_ADDR]], align 4 1544 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 1545 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 4 1546 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_4]], align 4 1547 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 1548 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 4 1549 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[START_ADDR]], align 4 1550 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_5]], align 4 1551 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[END_ADDR]], align 4 1552 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_6]], align 4 1553 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 1554 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTNEW_STEP7]], align 4 1555 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[START_ADDR]], align 4 1556 // CHECK1-NEXT: store i32 [[TMP7]], ptr [[K]], align 4 1557 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[START_ADDR]], align 4 1558 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_8]], align 4 1559 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[END_ADDR]], align 4 1560 // CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_9]], align 4 1561 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 1562 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTNEW_STEP10]], align 4 1563 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_9]], align 4 1564 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4 1565 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP11]], [[TMP12]] 1566 // CHECK1-NEXT: [[SUB12:%.*]] = sub i32 [[SUB]], 1 1567 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 1568 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB12]], [[TMP13]] 1569 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 1570 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP14]] 1571 // CHECK1-NEXT: [[SUB13:%.*]] = sub i32 [[DIV]], 1 1572 // CHECK1-NEXT: store i32 [[SUB13]], ptr [[DOTCAPTURE_EXPR_11]], align 4 1573 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 1574 // CHECK1-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], 1 1575 // CHECK1-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 4 1576 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 4 1577 // CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 4 1578 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 1579 // CHECK1-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 1 1580 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 4 1581 // CHECK1-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 64 1582 // CHECK1-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]] 1583 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1584 // CHECK1: cond.true: 1585 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 1586 // CHECK1-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 1 1587 // CHECK1-NEXT: br label [[COND_END:%.*]] 1588 // CHECK1: cond.false: 1589 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 4 1590 // CHECK1-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 64 1591 // CHECK1-NEXT: br label [[COND_END]] 1592 // CHECK1: cond.end: 1593 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ] 1594 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 4 1595 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 1596 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1597 // CHECK1-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]] 1598 // CHECK1-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 1 1599 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 1600 // CHECK1-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]] 1601 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 1602 // CHECK1-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]] 1603 // CHECK1-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i64 1604 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1605 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1606 // CHECK1-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]] 1607 // CHECK1-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 1 1608 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1609 // CHECK1-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]] 1610 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1611 // CHECK1-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]] 1612 // CHECK1-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i64 1613 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]] 1614 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1615 // CHECK1-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -63 1616 // CHECK1-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 64 1617 // CHECK1-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i64 1618 // CHECK1-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]] 1619 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1620 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1621 // CHECK1-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]] 1622 // CHECK1-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 1 1623 // CHECK1-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 1 1624 // CHECK1-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 1 1625 // CHECK1-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i64 1626 // CHECK1-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]] 1627 // CHECK1-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 1 1628 // CHECK1-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 8 1629 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1630 // CHECK1-NEXT: store i32 [[TMP32]], ptr [[I]], align 4 1631 // CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1632 // CHECK1-NEXT: store i32 [[TMP33]], ptr [[J]], align 4 1633 // CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 4 1634 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1635 // CHECK1-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 4 1636 // CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1637 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 1638 // CHECK1-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]] 1639 // CHECK1-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 1640 // CHECK1: land.lhs.true: 1641 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1642 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1643 // CHECK1-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]] 1644 // CHECK1-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]] 1645 // CHECK1: land.lhs.true45: 1646 // CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1647 // CHECK1-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]] 1648 // CHECK1-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]] 1649 // CHECK1: land.lhs.true47: 1650 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1651 // CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1652 // CHECK1-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]] 1653 // CHECK1-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 1654 // CHECK1: omp.precond.then: 1655 // CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 1656 // CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 1657 // CHECK1-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 8 1658 // CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 1659 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1660 // CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 1661 // CHECK1-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 1662 // CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 1663 // CHECK1-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]] 1664 // CHECK1-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]] 1665 // CHECK1: cond.true54: 1666 // CHECK1-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 1667 // CHECK1-NEXT: br label [[COND_END56:%.*]] 1668 // CHECK1: cond.false55: 1669 // CHECK1-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 1670 // CHECK1-NEXT: br label [[COND_END56]] 1671 // CHECK1: cond.end56: 1672 // CHECK1-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ] 1673 // CHECK1-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 8 1674 // CHECK1-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 1675 // CHECK1-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 8 1676 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1677 // CHECK1: omp.inner.for.cond: 1678 // CHECK1-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1679 // CHECK1-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 1680 // CHECK1-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]] 1681 // CHECK1-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1682 // CHECK1: omp.inner.for.body: 1683 // CHECK1-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1684 // CHECK1-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i64 1685 // CHECK1-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1686 // CHECK1-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1687 // CHECK1-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1688 // CHECK1-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]] 1689 // CHECK1-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 1 1690 // CHECK1-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1691 // CHECK1-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]] 1692 // CHECK1-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1693 // CHECK1-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]] 1694 // CHECK1-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]] 1695 // CHECK1-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1696 // CHECK1-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -63 1697 // CHECK1-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 64 1698 // CHECK1-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]] 1699 // CHECK1-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1700 // CHECK1-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1701 // CHECK1-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]] 1702 // CHECK1-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 1 1703 // CHECK1-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 1 1704 // CHECK1-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 1 1705 // CHECK1-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]] 1706 // CHECK1-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i64 1707 // CHECK1-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]] 1708 // CHECK1-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 1709 // CHECK1-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i64 1710 // CHECK1-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]] 1711 // CHECK1-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]] 1712 // CHECK1-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i32 1713 // CHECK1-NEXT: store i32 [[CONV78]], ptr [[I49]], align 4 1714 // CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1715 // CHECK1-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i64 1716 // CHECK1-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1717 // CHECK1-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1718 // CHECK1-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1719 // CHECK1-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1720 // CHECK1-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]] 1721 // CHECK1-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 1 1722 // CHECK1-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1723 // CHECK1-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]] 1724 // CHECK1-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1725 // CHECK1-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]] 1726 // CHECK1-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]] 1727 // CHECK1-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1728 // CHECK1-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -63 1729 // CHECK1-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 64 1730 // CHECK1-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]] 1731 // CHECK1-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1732 // CHECK1-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1733 // CHECK1-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]] 1734 // CHECK1-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 1 1735 // CHECK1-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 1 1736 // CHECK1-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 1 1737 // CHECK1-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]] 1738 // CHECK1-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i64 1739 // CHECK1-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]] 1740 // CHECK1-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1741 // CHECK1-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1742 // CHECK1-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]] 1743 // CHECK1-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 1 1744 // CHECK1-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1745 // CHECK1-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]] 1746 // CHECK1-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1747 // CHECK1-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]] 1748 // CHECK1-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]] 1749 // CHECK1-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1750 // CHECK1-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -63 1751 // CHECK1-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 64 1752 // CHECK1-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]] 1753 // CHECK1-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1754 // CHECK1-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1755 // CHECK1-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]] 1756 // CHECK1-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 1 1757 // CHECK1-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 1 1758 // CHECK1-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 1 1759 // CHECK1-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]] 1760 // CHECK1-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i64 1761 // CHECK1-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]] 1762 // CHECK1-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]] 1763 // CHECK1-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1764 // CHECK1-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -63 1765 // CHECK1-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 64 1766 // CHECK1-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]] 1767 // CHECK1-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1768 // CHECK1-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1769 // CHECK1-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]] 1770 // CHECK1-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 1 1771 // CHECK1-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 1 1772 // CHECK1-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 1 1773 // CHECK1-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]] 1774 // CHECK1-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i64 1775 // CHECK1-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]] 1776 // CHECK1-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1777 // CHECK1-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i64 1778 // CHECK1-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]] 1779 // CHECK1-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]] 1780 // CHECK1-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i32 1781 // CHECK1-NEXT: store i32 [[CONV124]], ptr [[J50]], align 4 1782 // CHECK1-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1783 // CHECK1-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1784 // CHECK1-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1785 // CHECK1-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1786 // CHECK1-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]] 1787 // CHECK1-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 1 1788 // CHECK1-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1789 // CHECK1-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]] 1790 // CHECK1-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1791 // CHECK1-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]] 1792 // CHECK1-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]] 1793 // CHECK1-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1794 // CHECK1-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -63 1795 // CHECK1-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 64 1796 // CHECK1-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]] 1797 // CHECK1-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1798 // CHECK1-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1799 // CHECK1-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]] 1800 // CHECK1-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 1 1801 // CHECK1-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 1 1802 // CHECK1-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 1 1803 // CHECK1-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]] 1804 // CHECK1-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i64 1805 // CHECK1-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]] 1806 // CHECK1-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1807 // CHECK1-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1808 // CHECK1-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]] 1809 // CHECK1-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 1 1810 // CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1811 // CHECK1-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]] 1812 // CHECK1-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1813 // CHECK1-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]] 1814 // CHECK1-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]] 1815 // CHECK1-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1816 // CHECK1-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -63 1817 // CHECK1-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 64 1818 // CHECK1-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]] 1819 // CHECK1-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1820 // CHECK1-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1821 // CHECK1-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]] 1822 // CHECK1-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 1 1823 // CHECK1-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 1 1824 // CHECK1-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 1 1825 // CHECK1-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]] 1826 // CHECK1-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i64 1827 // CHECK1-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]] 1828 // CHECK1-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]] 1829 // CHECK1-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1830 // CHECK1-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1831 // CHECK1-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1832 // CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1833 // CHECK1-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]] 1834 // CHECK1-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 1 1835 // CHECK1-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1836 // CHECK1-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]] 1837 // CHECK1-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1838 // CHECK1-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]] 1839 // CHECK1-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]] 1840 // CHECK1-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1841 // CHECK1-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -63 1842 // CHECK1-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 64 1843 // CHECK1-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]] 1844 // CHECK1-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1845 // CHECK1-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1846 // CHECK1-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]] 1847 // CHECK1-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 1 1848 // CHECK1-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 1 1849 // CHECK1-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 1 1850 // CHECK1-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]] 1851 // CHECK1-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i64 1852 // CHECK1-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]] 1853 // CHECK1-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1854 // CHECK1-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1855 // CHECK1-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]] 1856 // CHECK1-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 1 1857 // CHECK1-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1858 // CHECK1-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]] 1859 // CHECK1-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1860 // CHECK1-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]] 1861 // CHECK1-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]] 1862 // CHECK1-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1863 // CHECK1-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -63 1864 // CHECK1-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 64 1865 // CHECK1-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]] 1866 // CHECK1-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1867 // CHECK1-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1868 // CHECK1-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]] 1869 // CHECK1-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 1 1870 // CHECK1-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 1 1871 // CHECK1-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 1 1872 // CHECK1-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]] 1873 // CHECK1-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i64 1874 // CHECK1-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]] 1875 // CHECK1-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]] 1876 // CHECK1-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1877 // CHECK1-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -63 1878 // CHECK1-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 64 1879 // CHECK1-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]] 1880 // CHECK1-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1881 // CHECK1-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1882 // CHECK1-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]] 1883 // CHECK1-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 1 1884 // CHECK1-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 1 1885 // CHECK1-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 1 1886 // CHECK1-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]] 1887 // CHECK1-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i64 1888 // CHECK1-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]] 1889 // CHECK1-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1890 // CHECK1-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -63 1891 // CHECK1-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 64 1892 // CHECK1-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]] 1893 // CHECK1-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1894 // CHECK1-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1895 // CHECK1-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]] 1896 // CHECK1-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 1 1897 // CHECK1-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 1 1898 // CHECK1-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 1 1899 // CHECK1-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]] 1900 // CHECK1-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i64 1901 // CHECK1-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]] 1902 // CHECK1-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]] 1903 // CHECK1-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1904 // CHECK1-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1905 // CHECK1-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]] 1906 // CHECK1-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 1 1907 // CHECK1-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 1 1908 // CHECK1-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 1 1909 // CHECK1-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]] 1910 // CHECK1-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i64 1911 // CHECK1-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]] 1912 // CHECK1-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 64 1913 // CHECK1-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]] 1914 // CHECK1-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i32 1915 // CHECK1-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 4 1916 // CHECK1-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1917 // CHECK1-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i64 1918 // CHECK1-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1919 // CHECK1-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1920 // CHECK1-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1921 // CHECK1-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1922 // CHECK1-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]] 1923 // CHECK1-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 1 1924 // CHECK1-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1925 // CHECK1-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]] 1926 // CHECK1-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1927 // CHECK1-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]] 1928 // CHECK1-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]] 1929 // CHECK1-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1930 // CHECK1-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -63 1931 // CHECK1-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 64 1932 // CHECK1-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]] 1933 // CHECK1-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1934 // CHECK1-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1935 // CHECK1-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]] 1936 // CHECK1-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 1 1937 // CHECK1-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 1 1938 // CHECK1-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 1 1939 // CHECK1-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]] 1940 // CHECK1-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i64 1941 // CHECK1-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]] 1942 // CHECK1-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1943 // CHECK1-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1944 // CHECK1-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]] 1945 // CHECK1-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 1 1946 // CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1947 // CHECK1-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]] 1948 // CHECK1-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1949 // CHECK1-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]] 1950 // CHECK1-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]] 1951 // CHECK1-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1952 // CHECK1-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -63 1953 // CHECK1-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 64 1954 // CHECK1-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]] 1955 // CHECK1-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1956 // CHECK1-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1957 // CHECK1-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]] 1958 // CHECK1-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 1 1959 // CHECK1-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 1 1960 // CHECK1-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 1 1961 // CHECK1-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]] 1962 // CHECK1-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i64 1963 // CHECK1-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]] 1964 // CHECK1-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]] 1965 // CHECK1-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1966 // CHECK1-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 1967 // CHECK1-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1968 // CHECK1-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1969 // CHECK1-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]] 1970 // CHECK1-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 1 1971 // CHECK1-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1972 // CHECK1-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]] 1973 // CHECK1-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1974 // CHECK1-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]] 1975 // CHECK1-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]] 1976 // CHECK1-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1977 // CHECK1-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -63 1978 // CHECK1-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 64 1979 // CHECK1-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]] 1980 // CHECK1-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 1981 // CHECK1-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 1982 // CHECK1-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]] 1983 // CHECK1-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 1 1984 // CHECK1-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 1 1985 // CHECK1-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 1 1986 // CHECK1-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]] 1987 // CHECK1-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i64 1988 // CHECK1-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]] 1989 // CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 1990 // CHECK1-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 1991 // CHECK1-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]] 1992 // CHECK1-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 1 1993 // CHECK1-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1994 // CHECK1-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]] 1995 // CHECK1-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 1996 // CHECK1-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]] 1997 // CHECK1-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]] 1998 // CHECK1-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 1999 // CHECK1-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -63 2000 // CHECK1-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 64 2001 // CHECK1-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]] 2002 // CHECK1-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 2003 // CHECK1-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 2004 // CHECK1-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]] 2005 // CHECK1-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 1 2006 // CHECK1-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 1 2007 // CHECK1-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 1 2008 // CHECK1-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]] 2009 // CHECK1-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i64 2010 // CHECK1-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]] 2011 // CHECK1-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]] 2012 // CHECK1-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 2013 // CHECK1-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -63 2014 // CHECK1-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 64 2015 // CHECK1-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]] 2016 // CHECK1-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 2017 // CHECK1-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 2018 // CHECK1-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]] 2019 // CHECK1-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 1 2020 // CHECK1-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 1 2021 // CHECK1-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 1 2022 // CHECK1-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]] 2023 // CHECK1-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i64 2024 // CHECK1-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]] 2025 // CHECK1-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 2026 // CHECK1-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -63 2027 // CHECK1-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 64 2028 // CHECK1-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]] 2029 // CHECK1-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 2030 // CHECK1-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 2031 // CHECK1-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]] 2032 // CHECK1-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 1 2033 // CHECK1-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 1 2034 // CHECK1-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 1 2035 // CHECK1-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]] 2036 // CHECK1-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i64 2037 // CHECK1-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]] 2038 // CHECK1-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]] 2039 // CHECK1-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2040 // CHECK1-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2041 // CHECK1-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 2042 // CHECK1-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 2043 // CHECK1-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]] 2044 // CHECK1-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 1 2045 // CHECK1-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 2046 // CHECK1-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]] 2047 // CHECK1-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 2048 // CHECK1-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]] 2049 // CHECK1-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]] 2050 // CHECK1-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 2051 // CHECK1-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -63 2052 // CHECK1-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 64 2053 // CHECK1-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]] 2054 // CHECK1-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 2055 // CHECK1-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 2056 // CHECK1-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]] 2057 // CHECK1-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 1 2058 // CHECK1-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 1 2059 // CHECK1-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 1 2060 // CHECK1-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]] 2061 // CHECK1-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i64 2062 // CHECK1-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]] 2063 // CHECK1-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 2064 // CHECK1-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 2065 // CHECK1-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]] 2066 // CHECK1-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 1 2067 // CHECK1-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 2068 // CHECK1-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]] 2069 // CHECK1-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 2070 // CHECK1-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]] 2071 // CHECK1-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]] 2072 // CHECK1-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 2073 // CHECK1-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -63 2074 // CHECK1-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 64 2075 // CHECK1-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]] 2076 // CHECK1-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 2077 // CHECK1-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 2078 // CHECK1-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]] 2079 // CHECK1-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 1 2080 // CHECK1-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 1 2081 // CHECK1-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 1 2082 // CHECK1-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]] 2083 // CHECK1-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i64 2084 // CHECK1-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]] 2085 // CHECK1-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]] 2086 // CHECK1-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2087 // CHECK1-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2088 // CHECK1-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 2089 // CHECK1-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 2090 // CHECK1-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]] 2091 // CHECK1-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 1 2092 // CHECK1-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 2093 // CHECK1-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]] 2094 // CHECK1-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 2095 // CHECK1-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]] 2096 // CHECK1-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]] 2097 // CHECK1-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 2098 // CHECK1-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -63 2099 // CHECK1-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 64 2100 // CHECK1-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]] 2101 // CHECK1-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 2102 // CHECK1-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 2103 // CHECK1-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]] 2104 // CHECK1-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 1 2105 // CHECK1-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 1 2106 // CHECK1-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 1 2107 // CHECK1-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]] 2108 // CHECK1-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i64 2109 // CHECK1-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]] 2110 // CHECK1-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 2111 // CHECK1-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 2112 // CHECK1-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]] 2113 // CHECK1-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 1 2114 // CHECK1-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 2115 // CHECK1-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]] 2116 // CHECK1-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 2117 // CHECK1-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]] 2118 // CHECK1-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]] 2119 // CHECK1-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 2120 // CHECK1-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -63 2121 // CHECK1-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 64 2122 // CHECK1-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]] 2123 // CHECK1-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 2124 // CHECK1-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 2125 // CHECK1-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]] 2126 // CHECK1-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 1 2127 // CHECK1-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 1 2128 // CHECK1-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 1 2129 // CHECK1-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]] 2130 // CHECK1-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i64 2131 // CHECK1-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]] 2132 // CHECK1-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]] 2133 // CHECK1-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 2134 // CHECK1-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -63 2135 // CHECK1-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 64 2136 // CHECK1-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]] 2137 // CHECK1-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 2138 // CHECK1-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 2139 // CHECK1-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]] 2140 // CHECK1-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 1 2141 // CHECK1-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 1 2142 // CHECK1-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 1 2143 // CHECK1-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]] 2144 // CHECK1-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i64 2145 // CHECK1-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]] 2146 // CHECK1-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 2147 // CHECK1-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -63 2148 // CHECK1-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 64 2149 // CHECK1-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]] 2150 // CHECK1-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 2151 // CHECK1-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 2152 // CHECK1-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]] 2153 // CHECK1-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 1 2154 // CHECK1-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 1 2155 // CHECK1-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 1 2156 // CHECK1-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]] 2157 // CHECK1-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i64 2158 // CHECK1-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]] 2159 // CHECK1-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]] 2160 // CHECK1-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 2161 // CHECK1-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 2162 // CHECK1-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]] 2163 // CHECK1-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 1 2164 // CHECK1-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 1 2165 // CHECK1-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 1 2166 // CHECK1-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]] 2167 // CHECK1-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i64 2168 // CHECK1-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]] 2169 // CHECK1-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 2170 // CHECK1-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 2171 // CHECK1-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]] 2172 // CHECK1-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 1 2173 // CHECK1-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 1 2174 // CHECK1-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 1 2175 // CHECK1-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]] 2176 // CHECK1-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i64 2177 // CHECK1-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]] 2178 // CHECK1-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]] 2179 // CHECK1-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 1 2180 // CHECK1-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]] 2181 // CHECK1-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i32 2182 // CHECK1-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 4 2183 // CHECK1-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4 2184 // CHECK1-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 4 2185 // CHECK1-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 2186 // CHECK1-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]] 2187 // CHECK1-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]] 2188 // CHECK1-NEXT: store i32 [[ADD404]], ptr [[K]], align 4 2189 // CHECK1-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 4 2190 // CHECK1-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 4 2191 // CHECK1-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 4 2192 // CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]]) 2193 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2194 // CHECK1: omp.body.continue: 2195 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2196 // CHECK1: omp.inner.for.inc: 2197 // CHECK1-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2198 // CHECK1-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 1 2199 // CHECK1-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 8 2200 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 2201 // CHECK1: omp.inner.for.end: 2202 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2203 // CHECK1: omp.loop.exit: 2204 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) 2205 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 2206 // CHECK1: omp.precond.end: 2207 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) 2208 // CHECK1-NEXT: ret void 2209 // 2210 // 2211 // CHECK1-LABEL: define {{[^@]+}}@foo9 2212 // CHECK1-SAME: () #[[ATTR0]] { 2213 // CHECK1-NEXT: entry: 2214 // CHECK1-NEXT: [[ARR:%.*]] = alloca [128 x double], align 16 2215 // CHECK1-NEXT: [[C:%.*]] = alloca double, align 8 2216 // CHECK1-NEXT: [[__RANGE2:%.*]] = alloca ptr, align 8 2217 // CHECK1-NEXT: [[__END2:%.*]] = alloca ptr, align 8 2218 // CHECK1-NEXT: [[__BEGIN2:%.*]] = alloca ptr, align 8 2219 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 8 2220 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca ptr, align 8 2221 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 2222 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 2223 // CHECK1-NEXT: [[DOTPERMUTED_0_IV_I:%.*]] = alloca i32, align 4 2224 // CHECK1-NEXT: [[DOTPERMUTED_1_IV___BEGIN2:%.*]] = alloca i64, align 8 2225 // CHECK1-NEXT: [[V:%.*]] = alloca ptr, align 8 2226 // CHECK1-NEXT: store double 4.200000e+01, ptr [[C]], align 8 2227 // CHECK1-NEXT: store ptr [[ARR]], ptr [[__RANGE2]], align 8 2228 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8 2229 // CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP0]], i64 0, i64 0 2230 // CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 128 2231 // CHECK1-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 8 2232 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8 2233 // CHECK1-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 0 2234 // CHECK1-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 8 2235 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8 2236 // CHECK1-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 0 2237 // CHECK1-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 8 2238 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 8 2239 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTCAPTURE_EXPR_3]], align 8 2240 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_3]], align 8 2241 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8 2242 // CHECK1-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP4]] to i64 2243 // CHECK1-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i64 2244 // CHECK1-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] 2245 // CHECK1-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 8 2246 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 2247 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 2248 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 2249 // CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i64 [[DIV]], 1 2250 // CHECK1-NEXT: store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 8 2251 // CHECK1-NEXT: store i32 0, ptr [[I]], align 4 2252 // CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_0_IV_I]], align 4 2253 // CHECK1-NEXT: br label [[FOR_COND:%.*]] 2254 // CHECK1: for.cond: 2255 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 4 2256 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 21 2257 // CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END15:%.*]] 2258 // CHECK1: for.body: 2259 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 4 2260 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 2 2261 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL]] 2262 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[I]], align 4 2263 // CHECK1-NEXT: store i64 0, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8 2264 // CHECK1-NEXT: br label [[FOR_COND7:%.*]] 2265 // CHECK1: for.cond7: 2266 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8 2267 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 8 2268 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP9]], 1 2269 // CHECK1-NEXT: [[CMP9:%.*]] = icmp slt i64 [[TMP8]], [[ADD8]] 2270 // CHECK1-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END:%.*]] 2271 // CHECK1: for.body10: 2272 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8 2273 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8 2274 // CHECK1-NEXT: [[MUL11:%.*]] = mul nsw i64 [[TMP11]], 1 2275 // CHECK1-NEXT: [[ADD_PTR12:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i64 [[MUL11]] 2276 // CHECK1-NEXT: store ptr [[ADD_PTR12]], ptr [[__BEGIN2]], align 8 2277 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[__BEGIN2]], align 8 2278 // CHECK1-NEXT: store ptr [[TMP12]], ptr [[V]], align 8 2279 // CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[C]], align 8 2280 // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[V]], align 8 2281 // CHECK1-NEXT: [[TMP15:%.*]] = load double, ptr [[TMP14]], align 8 2282 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 2283 // CHECK1-NEXT: call void (...) @body(double noundef [[TMP13]], double noundef [[TMP15]], i32 noundef [[TMP16]]) 2284 // CHECK1-NEXT: br label [[FOR_INC:%.*]] 2285 // CHECK1: for.inc: 2286 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8 2287 // CHECK1-NEXT: [[INC:%.*]] = add nsw i64 [[TMP17]], 1 2288 // CHECK1-NEXT: store i64 [[INC]], ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8 2289 // CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP13:![0-9]+]] 2290 // CHECK1: for.end: 2291 // CHECK1-NEXT: br label [[FOR_INC13:%.*]] 2292 // CHECK1: for.inc13: 2293 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 4 2294 // CHECK1-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP18]], 1 2295 // CHECK1-NEXT: store i32 [[INC14]], ptr [[DOTPERMUTED_0_IV_I]], align 4 2296 // CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 2297 // CHECK1: for.end15: 2298 // CHECK1-NEXT: ret void 2299 // 2300 // 2301 // CHECK1-LABEL: define {{[^@]+}}@foo10 2302 // CHECK1-SAME: () #[[ATTR0]] { 2303 // CHECK1-NEXT: entry: 2304 // CHECK1-NEXT: [[A:%.*]] = alloca [128 x double], align 16 2305 // CHECK1-NEXT: [[B:%.*]] = alloca [16 x double], align 16 2306 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2307 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 2308 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i64, align 8 2309 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i64, align 8 2310 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 2311 // CHECK1-NEXT: [[C:%.*]] = alloca double, align 8 2312 // CHECK1-NEXT: [[__RANGE3:%.*]] = alloca ptr, align 8 2313 // CHECK1-NEXT: [[__END3:%.*]] = alloca ptr, align 8 2314 // CHECK1-NEXT: [[__BEGIN3:%.*]] = alloca ptr, align 8 2315 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 8 2316 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca ptr, align 8 2317 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_7:%.*]] = alloca i64, align 8 2318 // CHECK1-NEXT: [[D:%.*]] = alloca double, align 8 2319 // CHECK1-NEXT: [[__RANGE4:%.*]] = alloca ptr, align 8 2320 // CHECK1-NEXT: [[__END4:%.*]] = alloca ptr, align 8 2321 // CHECK1-NEXT: [[__BEGIN4:%.*]] = alloca ptr, align 8 2322 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_12:%.*]] = alloca ptr, align 8 2323 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca ptr, align 8 2324 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_15:%.*]] = alloca i64, align 8 2325 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i64, align 8 2326 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i64, align 8 2327 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i64, align 8 2328 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 2329 // CHECK1-NEXT: [[DOTPERMUTED_0_IV___BEGIN4:%.*]] = alloca i64, align 8 2330 // CHECK1-NEXT: [[DOTPERMUTED_1_IV___BEGIN3:%.*]] = alloca i64, align 8 2331 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 2332 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2333 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2334 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2335 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2336 // CHECK1-NEXT: [[I37:%.*]] = alloca i32, align 4 2337 // CHECK1-NEXT: [[DOTPERMUTED_0_IV___BEGIN438:%.*]] = alloca i64, align 8 2338 // CHECK1-NEXT: [[DOTPERMUTED_1_IV___BEGIN339:%.*]] = alloca i64, align 8 2339 // CHECK1-NEXT: [[J40:%.*]] = alloca i32, align 4 2340 // CHECK1-NEXT: [[BB:%.*]] = alloca ptr, align 8 2341 // CHECK1-NEXT: [[AA:%.*]] = alloca double, align 8 2342 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 2343 // CHECK1-NEXT: store double 4.200000e+01, ptr [[C]], align 8 2344 // CHECK1-NEXT: store ptr [[A]], ptr [[__RANGE3]], align 8 2345 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE3]], align 8 2346 // CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 0 2347 // CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 128 2348 // CHECK1-NEXT: store ptr [[ADD_PTR]], ptr [[__END3]], align 8 2349 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE3]], align 8 2350 // CHECK1-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 0 2351 // CHECK1-NEXT: store ptr [[ARRAYDECAY4]], ptr [[__BEGIN3]], align 8 2352 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__RANGE3]], align 8 2353 // CHECK1-NEXT: [[ARRAYDECAY5:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP3]], i64 0, i64 0 2354 // CHECK1-NEXT: store ptr [[ARRAYDECAY5]], ptr [[DOTCAPTURE_EXPR_]], align 8 2355 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__END3]], align 8 2356 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[DOTCAPTURE_EXPR_6]], align 8 2357 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 8 2358 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8 2359 // CHECK1-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i64 2360 // CHECK1-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP6]] to i64 2361 // CHECK1-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] 2362 // CHECK1-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 8 2363 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 2364 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 2365 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 2366 // CHECK1-NEXT: [[SUB8:%.*]] = sub nsw i64 [[DIV]], 1 2367 // CHECK1-NEXT: store i64 [[SUB8]], ptr [[DOTCAPTURE_EXPR_7]], align 8 2368 // CHECK1-NEXT: store double 4.200000e+01, ptr [[D]], align 8 2369 // CHECK1-NEXT: store ptr [[B]], ptr [[__RANGE4]], align 8 2370 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[__RANGE4]], align 8 2371 // CHECK1-NEXT: [[ARRAYDECAY9:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP7]], i64 0, i64 0 2372 // CHECK1-NEXT: [[ADD_PTR10:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY9]], i64 16 2373 // CHECK1-NEXT: store ptr [[ADD_PTR10]], ptr [[__END4]], align 8 2374 // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__RANGE4]], align 8 2375 // CHECK1-NEXT: [[ARRAYDECAY11:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP8]], i64 0, i64 0 2376 // CHECK1-NEXT: store ptr [[ARRAYDECAY11]], ptr [[__BEGIN4]], align 8 2377 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__RANGE4]], align 8 2378 // CHECK1-NEXT: [[ARRAYDECAY13:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP9]], i64 0, i64 0 2379 // CHECK1-NEXT: store ptr [[ARRAYDECAY13]], ptr [[DOTCAPTURE_EXPR_12]], align 8 2380 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[__END4]], align 8 2381 // CHECK1-NEXT: store ptr [[TMP10]], ptr [[DOTCAPTURE_EXPR_14]], align 8 2382 // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_14]], align 8 2383 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_12]], align 8 2384 // CHECK1-NEXT: [[SUB_PTR_LHS_CAST16:%.*]] = ptrtoint ptr [[TMP11]] to i64 2385 // CHECK1-NEXT: [[SUB_PTR_RHS_CAST17:%.*]] = ptrtoint ptr [[TMP12]] to i64 2386 // CHECK1-NEXT: [[SUB_PTR_SUB18:%.*]] = sub i64 [[SUB_PTR_LHS_CAST16]], [[SUB_PTR_RHS_CAST17]] 2387 // CHECK1-NEXT: [[SUB_PTR_DIV19:%.*]] = sdiv exact i64 [[SUB_PTR_SUB18]], 8 2388 // CHECK1-NEXT: [[SUB20:%.*]] = sub nsw i64 [[SUB_PTR_DIV19]], 1 2389 // CHECK1-NEXT: [[ADD21:%.*]] = add nsw i64 [[SUB20]], 1 2390 // CHECK1-NEXT: [[DIV22:%.*]] = sdiv i64 [[ADD21]], 1 2391 // CHECK1-NEXT: [[SUB23:%.*]] = sub nsw i64 [[DIV22]], 1 2392 // CHECK1-NEXT: store i64 [[SUB23]], ptr [[DOTCAPTURE_EXPR_15]], align 8 2393 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_15]], align 8 2394 // CHECK1-NEXT: [[ADD25:%.*]] = add nsw i64 [[TMP13]], 1 2395 // CHECK1-NEXT: store i64 [[ADD25]], ptr [[DOTCAPTURE_EXPR_24]], align 8 2396 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_7]], align 8 2397 // CHECK1-NEXT: [[ADD27:%.*]] = add nsw i64 [[TMP14]], 1 2398 // CHECK1-NEXT: store i64 [[ADD27]], ptr [[DOTCAPTURE_EXPR_26]], align 8 2399 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2400 // CHECK1-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP15]], 0 2401 // CHECK1-NEXT: [[DIV30:%.*]] = sdiv i64 [[SUB29]], 1 2402 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 128, [[DIV30]] 2403 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2404 // CHECK1-NEXT: [[SUB31:%.*]] = sub nsw i64 [[TMP16]], 0 2405 // CHECK1-NEXT: [[DIV32:%.*]] = sdiv i64 [[SUB31]], 1 2406 // CHECK1-NEXT: [[MUL33:%.*]] = mul nsw i64 [[MUL]], [[DIV32]] 2407 // CHECK1-NEXT: [[MUL34:%.*]] = mul nsw i64 [[MUL33]], 128 2408 // CHECK1-NEXT: [[SUB35:%.*]] = sub nsw i64 [[MUL34]], 1 2409 // CHECK1-NEXT: store i64 [[SUB35]], ptr [[DOTCAPTURE_EXPR_28]], align 8 2410 // CHECK1-NEXT: store i32 0, ptr [[I]], align 4 2411 // CHECK1-NEXT: store i64 0, ptr [[DOTPERMUTED_0_IV___BEGIN4]], align 8 2412 // CHECK1-NEXT: store i64 0, ptr [[DOTPERMUTED_1_IV___BEGIN3]], align 8 2413 // CHECK1-NEXT: store i32 0, ptr [[J]], align 4 2414 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2415 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i64 0, [[TMP17]] 2416 // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 2417 // CHECK1: land.lhs.true: 2418 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2419 // CHECK1-NEXT: [[CMP36:%.*]] = icmp slt i64 0, [[TMP18]] 2420 // CHECK1-NEXT: br i1 [[CMP36]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 2421 // CHECK1: omp.precond.then: 2422 // CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 2423 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_28]], align 8 2424 // CHECK1-NEXT: store i64 [[TMP19]], ptr [[DOTOMP_UB]], align 8 2425 // CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 2426 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2427 // CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 2428 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 2429 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_28]], align 8 2430 // CHECK1-NEXT: [[CMP41:%.*]] = icmp sgt i64 [[TMP20]], [[TMP21]] 2431 // CHECK1-NEXT: br i1 [[CMP41]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2432 // CHECK1: cond.true: 2433 // CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_28]], align 8 2434 // CHECK1-NEXT: br label [[COND_END:%.*]] 2435 // CHECK1: cond.false: 2436 // CHECK1-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 2437 // CHECK1-NEXT: br label [[COND_END]] 2438 // CHECK1: cond.end: 2439 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE]] ], [ [[TMP23]], [[COND_FALSE]] ] 2440 // CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 2441 // CHECK1-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 2442 // CHECK1-NEXT: store i64 [[TMP24]], ptr [[DOTOMP_IV]], align 8 2443 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2444 // CHECK1: omp.inner.for.cond: 2445 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2446 // CHECK1-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 2447 // CHECK1-NEXT: [[CMP42:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]] 2448 // CHECK1-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2449 // CHECK1: omp.inner.for.body: 2450 // CHECK1-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2451 // CHECK1-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2452 // CHECK1-NEXT: [[SUB43:%.*]] = sub nsw i64 [[TMP28]], 0 2453 // CHECK1-NEXT: [[DIV44:%.*]] = sdiv i64 [[SUB43]], 1 2454 // CHECK1-NEXT: [[MUL45:%.*]] = mul nsw i64 1, [[DIV44]] 2455 // CHECK1-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2456 // CHECK1-NEXT: [[SUB46:%.*]] = sub nsw i64 [[TMP29]], 0 2457 // CHECK1-NEXT: [[DIV47:%.*]] = sdiv i64 [[SUB46]], 1 2458 // CHECK1-NEXT: [[MUL48:%.*]] = mul nsw i64 [[MUL45]], [[DIV47]] 2459 // CHECK1-NEXT: [[MUL49:%.*]] = mul nsw i64 [[MUL48]], 128 2460 // CHECK1-NEXT: [[DIV50:%.*]] = sdiv i64 [[TMP27]], [[MUL49]] 2461 // CHECK1-NEXT: [[MUL51:%.*]] = mul nsw i64 [[DIV50]], 1 2462 // CHECK1-NEXT: [[ADD52:%.*]] = add nsw i64 0, [[MUL51]] 2463 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[ADD52]] to i32 2464 // CHECK1-NEXT: store i32 [[CONV]], ptr [[I37]], align 4 2465 // CHECK1-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2466 // CHECK1-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2467 // CHECK1-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2468 // CHECK1-NEXT: [[SUB53:%.*]] = sub nsw i64 [[TMP32]], 0 2469 // CHECK1-NEXT: [[DIV54:%.*]] = sdiv i64 [[SUB53]], 1 2470 // CHECK1-NEXT: [[MUL55:%.*]] = mul nsw i64 1, [[DIV54]] 2471 // CHECK1-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2472 // CHECK1-NEXT: [[SUB56:%.*]] = sub nsw i64 [[TMP33]], 0 2473 // CHECK1-NEXT: [[DIV57:%.*]] = sdiv i64 [[SUB56]], 1 2474 // CHECK1-NEXT: [[MUL58:%.*]] = mul nsw i64 [[MUL55]], [[DIV57]] 2475 // CHECK1-NEXT: [[MUL59:%.*]] = mul nsw i64 [[MUL58]], 128 2476 // CHECK1-NEXT: [[DIV60:%.*]] = sdiv i64 [[TMP31]], [[MUL59]] 2477 // CHECK1-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2478 // CHECK1-NEXT: [[SUB61:%.*]] = sub nsw i64 [[TMP34]], 0 2479 // CHECK1-NEXT: [[DIV62:%.*]] = sdiv i64 [[SUB61]], 1 2480 // CHECK1-NEXT: [[MUL63:%.*]] = mul nsw i64 1, [[DIV62]] 2481 // CHECK1-NEXT: [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2482 // CHECK1-NEXT: [[SUB64:%.*]] = sub nsw i64 [[TMP35]], 0 2483 // CHECK1-NEXT: [[DIV65:%.*]] = sdiv i64 [[SUB64]], 1 2484 // CHECK1-NEXT: [[MUL66:%.*]] = mul nsw i64 [[MUL63]], [[DIV65]] 2485 // CHECK1-NEXT: [[MUL67:%.*]] = mul nsw i64 [[MUL66]], 128 2486 // CHECK1-NEXT: [[MUL68:%.*]] = mul nsw i64 [[DIV60]], [[MUL67]] 2487 // CHECK1-NEXT: [[SUB69:%.*]] = sub nsw i64 [[TMP30]], [[MUL68]] 2488 // CHECK1-NEXT: [[TMP36:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2489 // CHECK1-NEXT: [[SUB70:%.*]] = sub nsw i64 [[TMP36]], 0 2490 // CHECK1-NEXT: [[DIV71:%.*]] = sdiv i64 [[SUB70]], 1 2491 // CHECK1-NEXT: [[MUL72:%.*]] = mul nsw i64 1, [[DIV71]] 2492 // CHECK1-NEXT: [[MUL73:%.*]] = mul nsw i64 [[MUL72]], 128 2493 // CHECK1-NEXT: [[DIV74:%.*]] = sdiv i64 [[SUB69]], [[MUL73]] 2494 // CHECK1-NEXT: [[MUL75:%.*]] = mul nsw i64 [[DIV74]], 1 2495 // CHECK1-NEXT: [[ADD76:%.*]] = add nsw i64 0, [[MUL75]] 2496 // CHECK1-NEXT: store i64 [[ADD76]], ptr [[DOTPERMUTED_0_IV___BEGIN438]], align 8 2497 // CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2498 // CHECK1-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2499 // CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2500 // CHECK1-NEXT: [[SUB77:%.*]] = sub nsw i64 [[TMP39]], 0 2501 // CHECK1-NEXT: [[DIV78:%.*]] = sdiv i64 [[SUB77]], 1 2502 // CHECK1-NEXT: [[MUL79:%.*]] = mul nsw i64 1, [[DIV78]] 2503 // CHECK1-NEXT: [[TMP40:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2504 // CHECK1-NEXT: [[SUB80:%.*]] = sub nsw i64 [[TMP40]], 0 2505 // CHECK1-NEXT: [[DIV81:%.*]] = sdiv i64 [[SUB80]], 1 2506 // CHECK1-NEXT: [[MUL82:%.*]] = mul nsw i64 [[MUL79]], [[DIV81]] 2507 // CHECK1-NEXT: [[MUL83:%.*]] = mul nsw i64 [[MUL82]], 128 2508 // CHECK1-NEXT: [[DIV84:%.*]] = sdiv i64 [[TMP38]], [[MUL83]] 2509 // CHECK1-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2510 // CHECK1-NEXT: [[SUB85:%.*]] = sub nsw i64 [[TMP41]], 0 2511 // CHECK1-NEXT: [[DIV86:%.*]] = sdiv i64 [[SUB85]], 1 2512 // CHECK1-NEXT: [[MUL87:%.*]] = mul nsw i64 1, [[DIV86]] 2513 // CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2514 // CHECK1-NEXT: [[SUB88:%.*]] = sub nsw i64 [[TMP42]], 0 2515 // CHECK1-NEXT: [[DIV89:%.*]] = sdiv i64 [[SUB88]], 1 2516 // CHECK1-NEXT: [[MUL90:%.*]] = mul nsw i64 [[MUL87]], [[DIV89]] 2517 // CHECK1-NEXT: [[MUL91:%.*]] = mul nsw i64 [[MUL90]], 128 2518 // CHECK1-NEXT: [[MUL92:%.*]] = mul nsw i64 [[DIV84]], [[MUL91]] 2519 // CHECK1-NEXT: [[SUB93:%.*]] = sub nsw i64 [[TMP37]], [[MUL92]] 2520 // CHECK1-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2521 // CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2522 // CHECK1-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2523 // CHECK1-NEXT: [[SUB94:%.*]] = sub nsw i64 [[TMP45]], 0 2524 // CHECK1-NEXT: [[DIV95:%.*]] = sdiv i64 [[SUB94]], 1 2525 // CHECK1-NEXT: [[MUL96:%.*]] = mul nsw i64 1, [[DIV95]] 2526 // CHECK1-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2527 // CHECK1-NEXT: [[SUB97:%.*]] = sub nsw i64 [[TMP46]], 0 2528 // CHECK1-NEXT: [[DIV98:%.*]] = sdiv i64 [[SUB97]], 1 2529 // CHECK1-NEXT: [[MUL99:%.*]] = mul nsw i64 [[MUL96]], [[DIV98]] 2530 // CHECK1-NEXT: [[MUL100:%.*]] = mul nsw i64 [[MUL99]], 128 2531 // CHECK1-NEXT: [[DIV101:%.*]] = sdiv i64 [[TMP44]], [[MUL100]] 2532 // CHECK1-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2533 // CHECK1-NEXT: [[SUB102:%.*]] = sub nsw i64 [[TMP47]], 0 2534 // CHECK1-NEXT: [[DIV103:%.*]] = sdiv i64 [[SUB102]], 1 2535 // CHECK1-NEXT: [[MUL104:%.*]] = mul nsw i64 1, [[DIV103]] 2536 // CHECK1-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2537 // CHECK1-NEXT: [[SUB105:%.*]] = sub nsw i64 [[TMP48]], 0 2538 // CHECK1-NEXT: [[DIV106:%.*]] = sdiv i64 [[SUB105]], 1 2539 // CHECK1-NEXT: [[MUL107:%.*]] = mul nsw i64 [[MUL104]], [[DIV106]] 2540 // CHECK1-NEXT: [[MUL108:%.*]] = mul nsw i64 [[MUL107]], 128 2541 // CHECK1-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV101]], [[MUL108]] 2542 // CHECK1-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP43]], [[MUL109]] 2543 // CHECK1-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2544 // CHECK1-NEXT: [[SUB111:%.*]] = sub nsw i64 [[TMP49]], 0 2545 // CHECK1-NEXT: [[DIV112:%.*]] = sdiv i64 [[SUB111]], 1 2546 // CHECK1-NEXT: [[MUL113:%.*]] = mul nsw i64 1, [[DIV112]] 2547 // CHECK1-NEXT: [[MUL114:%.*]] = mul nsw i64 [[MUL113]], 128 2548 // CHECK1-NEXT: [[DIV115:%.*]] = sdiv i64 [[SUB110]], [[MUL114]] 2549 // CHECK1-NEXT: [[TMP50:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2550 // CHECK1-NEXT: [[SUB116:%.*]] = sub nsw i64 [[TMP50]], 0 2551 // CHECK1-NEXT: [[DIV117:%.*]] = sdiv i64 [[SUB116]], 1 2552 // CHECK1-NEXT: [[MUL118:%.*]] = mul nsw i64 1, [[DIV117]] 2553 // CHECK1-NEXT: [[MUL119:%.*]] = mul nsw i64 [[MUL118]], 128 2554 // CHECK1-NEXT: [[MUL120:%.*]] = mul nsw i64 [[DIV115]], [[MUL119]] 2555 // CHECK1-NEXT: [[SUB121:%.*]] = sub nsw i64 [[SUB93]], [[MUL120]] 2556 // CHECK1-NEXT: [[DIV122:%.*]] = sdiv i64 [[SUB121]], 128 2557 // CHECK1-NEXT: [[MUL123:%.*]] = mul nsw i64 [[DIV122]], 1 2558 // CHECK1-NEXT: [[ADD124:%.*]] = add nsw i64 0, [[MUL123]] 2559 // CHECK1-NEXT: store i64 [[ADD124]], ptr [[DOTPERMUTED_1_IV___BEGIN339]], align 8 2560 // CHECK1-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2561 // CHECK1-NEXT: [[TMP52:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2562 // CHECK1-NEXT: [[TMP53:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2563 // CHECK1-NEXT: [[SUB125:%.*]] = sub nsw i64 [[TMP53]], 0 2564 // CHECK1-NEXT: [[DIV126:%.*]] = sdiv i64 [[SUB125]], 1 2565 // CHECK1-NEXT: [[MUL127:%.*]] = mul nsw i64 1, [[DIV126]] 2566 // CHECK1-NEXT: [[TMP54:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2567 // CHECK1-NEXT: [[SUB128:%.*]] = sub nsw i64 [[TMP54]], 0 2568 // CHECK1-NEXT: [[DIV129:%.*]] = sdiv i64 [[SUB128]], 1 2569 // CHECK1-NEXT: [[MUL130:%.*]] = mul nsw i64 [[MUL127]], [[DIV129]] 2570 // CHECK1-NEXT: [[MUL131:%.*]] = mul nsw i64 [[MUL130]], 128 2571 // CHECK1-NEXT: [[DIV132:%.*]] = sdiv i64 [[TMP52]], [[MUL131]] 2572 // CHECK1-NEXT: [[TMP55:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2573 // CHECK1-NEXT: [[SUB133:%.*]] = sub nsw i64 [[TMP55]], 0 2574 // CHECK1-NEXT: [[DIV134:%.*]] = sdiv i64 [[SUB133]], 1 2575 // CHECK1-NEXT: [[MUL135:%.*]] = mul nsw i64 1, [[DIV134]] 2576 // CHECK1-NEXT: [[TMP56:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2577 // CHECK1-NEXT: [[SUB136:%.*]] = sub nsw i64 [[TMP56]], 0 2578 // CHECK1-NEXT: [[DIV137:%.*]] = sdiv i64 [[SUB136]], 1 2579 // CHECK1-NEXT: [[MUL138:%.*]] = mul nsw i64 [[MUL135]], [[DIV137]] 2580 // CHECK1-NEXT: [[MUL139:%.*]] = mul nsw i64 [[MUL138]], 128 2581 // CHECK1-NEXT: [[MUL140:%.*]] = mul nsw i64 [[DIV132]], [[MUL139]] 2582 // CHECK1-NEXT: [[SUB141:%.*]] = sub nsw i64 [[TMP51]], [[MUL140]] 2583 // CHECK1-NEXT: [[TMP57:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2584 // CHECK1-NEXT: [[TMP58:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2585 // CHECK1-NEXT: [[TMP59:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2586 // CHECK1-NEXT: [[SUB142:%.*]] = sub nsw i64 [[TMP59]], 0 2587 // CHECK1-NEXT: [[DIV143:%.*]] = sdiv i64 [[SUB142]], 1 2588 // CHECK1-NEXT: [[MUL144:%.*]] = mul nsw i64 1, [[DIV143]] 2589 // CHECK1-NEXT: [[TMP60:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2590 // CHECK1-NEXT: [[SUB145:%.*]] = sub nsw i64 [[TMP60]], 0 2591 // CHECK1-NEXT: [[DIV146:%.*]] = sdiv i64 [[SUB145]], 1 2592 // CHECK1-NEXT: [[MUL147:%.*]] = mul nsw i64 [[MUL144]], [[DIV146]] 2593 // CHECK1-NEXT: [[MUL148:%.*]] = mul nsw i64 [[MUL147]], 128 2594 // CHECK1-NEXT: [[DIV149:%.*]] = sdiv i64 [[TMP58]], [[MUL148]] 2595 // CHECK1-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2596 // CHECK1-NEXT: [[SUB150:%.*]] = sub nsw i64 [[TMP61]], 0 2597 // CHECK1-NEXT: [[DIV151:%.*]] = sdiv i64 [[SUB150]], 1 2598 // CHECK1-NEXT: [[MUL152:%.*]] = mul nsw i64 1, [[DIV151]] 2599 // CHECK1-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2600 // CHECK1-NEXT: [[SUB153:%.*]] = sub nsw i64 [[TMP62]], 0 2601 // CHECK1-NEXT: [[DIV154:%.*]] = sdiv i64 [[SUB153]], 1 2602 // CHECK1-NEXT: [[MUL155:%.*]] = mul nsw i64 [[MUL152]], [[DIV154]] 2603 // CHECK1-NEXT: [[MUL156:%.*]] = mul nsw i64 [[MUL155]], 128 2604 // CHECK1-NEXT: [[MUL157:%.*]] = mul nsw i64 [[DIV149]], [[MUL156]] 2605 // CHECK1-NEXT: [[SUB158:%.*]] = sub nsw i64 [[TMP57]], [[MUL157]] 2606 // CHECK1-NEXT: [[TMP63:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2607 // CHECK1-NEXT: [[SUB159:%.*]] = sub nsw i64 [[TMP63]], 0 2608 // CHECK1-NEXT: [[DIV160:%.*]] = sdiv i64 [[SUB159]], 1 2609 // CHECK1-NEXT: [[MUL161:%.*]] = mul nsw i64 1, [[DIV160]] 2610 // CHECK1-NEXT: [[MUL162:%.*]] = mul nsw i64 [[MUL161]], 128 2611 // CHECK1-NEXT: [[DIV163:%.*]] = sdiv i64 [[SUB158]], [[MUL162]] 2612 // CHECK1-NEXT: [[TMP64:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2613 // CHECK1-NEXT: [[SUB164:%.*]] = sub nsw i64 [[TMP64]], 0 2614 // CHECK1-NEXT: [[DIV165:%.*]] = sdiv i64 [[SUB164]], 1 2615 // CHECK1-NEXT: [[MUL166:%.*]] = mul nsw i64 1, [[DIV165]] 2616 // CHECK1-NEXT: [[MUL167:%.*]] = mul nsw i64 [[MUL166]], 128 2617 // CHECK1-NEXT: [[MUL168:%.*]] = mul nsw i64 [[DIV163]], [[MUL167]] 2618 // CHECK1-NEXT: [[SUB169:%.*]] = sub nsw i64 [[SUB141]], [[MUL168]] 2619 // CHECK1-NEXT: [[TMP65:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2620 // CHECK1-NEXT: [[TMP66:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2621 // CHECK1-NEXT: [[TMP67:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2622 // CHECK1-NEXT: [[SUB170:%.*]] = sub nsw i64 [[TMP67]], 0 2623 // CHECK1-NEXT: [[DIV171:%.*]] = sdiv i64 [[SUB170]], 1 2624 // CHECK1-NEXT: [[MUL172:%.*]] = mul nsw i64 1, [[DIV171]] 2625 // CHECK1-NEXT: [[TMP68:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2626 // CHECK1-NEXT: [[SUB173:%.*]] = sub nsw i64 [[TMP68]], 0 2627 // CHECK1-NEXT: [[DIV174:%.*]] = sdiv i64 [[SUB173]], 1 2628 // CHECK1-NEXT: [[MUL175:%.*]] = mul nsw i64 [[MUL172]], [[DIV174]] 2629 // CHECK1-NEXT: [[MUL176:%.*]] = mul nsw i64 [[MUL175]], 128 2630 // CHECK1-NEXT: [[DIV177:%.*]] = sdiv i64 [[TMP66]], [[MUL176]] 2631 // CHECK1-NEXT: [[TMP69:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2632 // CHECK1-NEXT: [[SUB178:%.*]] = sub nsw i64 [[TMP69]], 0 2633 // CHECK1-NEXT: [[DIV179:%.*]] = sdiv i64 [[SUB178]], 1 2634 // CHECK1-NEXT: [[MUL180:%.*]] = mul nsw i64 1, [[DIV179]] 2635 // CHECK1-NEXT: [[TMP70:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2636 // CHECK1-NEXT: [[SUB181:%.*]] = sub nsw i64 [[TMP70]], 0 2637 // CHECK1-NEXT: [[DIV182:%.*]] = sdiv i64 [[SUB181]], 1 2638 // CHECK1-NEXT: [[MUL183:%.*]] = mul nsw i64 [[MUL180]], [[DIV182]] 2639 // CHECK1-NEXT: [[MUL184:%.*]] = mul nsw i64 [[MUL183]], 128 2640 // CHECK1-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV177]], [[MUL184]] 2641 // CHECK1-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP65]], [[MUL185]] 2642 // CHECK1-NEXT: [[TMP71:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2643 // CHECK1-NEXT: [[TMP72:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2644 // CHECK1-NEXT: [[TMP73:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2645 // CHECK1-NEXT: [[SUB187:%.*]] = sub nsw i64 [[TMP73]], 0 2646 // CHECK1-NEXT: [[DIV188:%.*]] = sdiv i64 [[SUB187]], 1 2647 // CHECK1-NEXT: [[MUL189:%.*]] = mul nsw i64 1, [[DIV188]] 2648 // CHECK1-NEXT: [[TMP74:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2649 // CHECK1-NEXT: [[SUB190:%.*]] = sub nsw i64 [[TMP74]], 0 2650 // CHECK1-NEXT: [[DIV191:%.*]] = sdiv i64 [[SUB190]], 1 2651 // CHECK1-NEXT: [[MUL192:%.*]] = mul nsw i64 [[MUL189]], [[DIV191]] 2652 // CHECK1-NEXT: [[MUL193:%.*]] = mul nsw i64 [[MUL192]], 128 2653 // CHECK1-NEXT: [[DIV194:%.*]] = sdiv i64 [[TMP72]], [[MUL193]] 2654 // CHECK1-NEXT: [[TMP75:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2655 // CHECK1-NEXT: [[SUB195:%.*]] = sub nsw i64 [[TMP75]], 0 2656 // CHECK1-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB195]], 1 2657 // CHECK1-NEXT: [[MUL197:%.*]] = mul nsw i64 1, [[DIV196]] 2658 // CHECK1-NEXT: [[TMP76:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2659 // CHECK1-NEXT: [[SUB198:%.*]] = sub nsw i64 [[TMP76]], 0 2660 // CHECK1-NEXT: [[DIV199:%.*]] = sdiv i64 [[SUB198]], 1 2661 // CHECK1-NEXT: [[MUL200:%.*]] = mul nsw i64 [[MUL197]], [[DIV199]] 2662 // CHECK1-NEXT: [[MUL201:%.*]] = mul nsw i64 [[MUL200]], 128 2663 // CHECK1-NEXT: [[MUL202:%.*]] = mul nsw i64 [[DIV194]], [[MUL201]] 2664 // CHECK1-NEXT: [[SUB203:%.*]] = sub nsw i64 [[TMP71]], [[MUL202]] 2665 // CHECK1-NEXT: [[TMP77:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2666 // CHECK1-NEXT: [[SUB204:%.*]] = sub nsw i64 [[TMP77]], 0 2667 // CHECK1-NEXT: [[DIV205:%.*]] = sdiv i64 [[SUB204]], 1 2668 // CHECK1-NEXT: [[MUL206:%.*]] = mul nsw i64 1, [[DIV205]] 2669 // CHECK1-NEXT: [[MUL207:%.*]] = mul nsw i64 [[MUL206]], 128 2670 // CHECK1-NEXT: [[DIV208:%.*]] = sdiv i64 [[SUB203]], [[MUL207]] 2671 // CHECK1-NEXT: [[TMP78:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2672 // CHECK1-NEXT: [[SUB209:%.*]] = sub nsw i64 [[TMP78]], 0 2673 // CHECK1-NEXT: [[DIV210:%.*]] = sdiv i64 [[SUB209]], 1 2674 // CHECK1-NEXT: [[MUL211:%.*]] = mul nsw i64 1, [[DIV210]] 2675 // CHECK1-NEXT: [[MUL212:%.*]] = mul nsw i64 [[MUL211]], 128 2676 // CHECK1-NEXT: [[MUL213:%.*]] = mul nsw i64 [[DIV208]], [[MUL212]] 2677 // CHECK1-NEXT: [[SUB214:%.*]] = sub nsw i64 [[SUB186]], [[MUL213]] 2678 // CHECK1-NEXT: [[DIV215:%.*]] = sdiv i64 [[SUB214]], 128 2679 // CHECK1-NEXT: [[MUL216:%.*]] = mul nsw i64 [[DIV215]], 128 2680 // CHECK1-NEXT: [[SUB217:%.*]] = sub nsw i64 [[SUB169]], [[MUL216]] 2681 // CHECK1-NEXT: [[MUL218:%.*]] = mul nsw i64 [[SUB217]], 1 2682 // CHECK1-NEXT: [[ADD219:%.*]] = add nsw i64 0, [[MUL218]] 2683 // CHECK1-NEXT: [[CONV220:%.*]] = trunc i64 [[ADD219]] to i32 2684 // CHECK1-NEXT: store i32 [[CONV220]], ptr [[J40]], align 4 2685 // CHECK1-NEXT: [[TMP79:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_12]], align 8 2686 // CHECK1-NEXT: [[TMP80:%.*]] = load i64, ptr [[DOTPERMUTED_0_IV___BEGIN438]], align 8 2687 // CHECK1-NEXT: [[MUL221:%.*]] = mul nsw i64 [[TMP80]], 1 2688 // CHECK1-NEXT: [[ADD_PTR222:%.*]] = getelementptr inbounds double, ptr [[TMP79]], i64 [[MUL221]] 2689 // CHECK1-NEXT: store ptr [[ADD_PTR222]], ptr [[__BEGIN4]], align 8 2690 // CHECK1-NEXT: [[TMP81:%.*]] = load ptr, ptr [[__BEGIN4]], align 8 2691 // CHECK1-NEXT: store ptr [[TMP81]], ptr [[BB]], align 8 2692 // CHECK1-NEXT: [[TMP82:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8 2693 // CHECK1-NEXT: [[TMP83:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN339]], align 8 2694 // CHECK1-NEXT: [[MUL223:%.*]] = mul nsw i64 [[TMP83]], 1 2695 // CHECK1-NEXT: [[ADD_PTR224:%.*]] = getelementptr inbounds double, ptr [[TMP82]], i64 [[MUL223]] 2696 // CHECK1-NEXT: store ptr [[ADD_PTR224]], ptr [[__BEGIN3]], align 8 2697 // CHECK1-NEXT: [[TMP84:%.*]] = load ptr, ptr [[__BEGIN3]], align 8 2698 // CHECK1-NEXT: [[TMP85:%.*]] = load double, ptr [[TMP84]], align 8 2699 // CHECK1-NEXT: store double [[TMP85]], ptr [[AA]], align 8 2700 // CHECK1-NEXT: [[TMP86:%.*]] = load i32, ptr [[I37]], align 4 2701 // CHECK1-NEXT: [[TMP87:%.*]] = load double, ptr [[C]], align 8 2702 // CHECK1-NEXT: [[TMP88:%.*]] = load double, ptr [[AA]], align 8 2703 // CHECK1-NEXT: [[TMP89:%.*]] = load double, ptr [[D]], align 8 2704 // CHECK1-NEXT: [[TMP90:%.*]] = load ptr, ptr [[BB]], align 8 2705 // CHECK1-NEXT: [[TMP91:%.*]] = load double, ptr [[TMP90]], align 8 2706 // CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[J40]], align 4 2707 // CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP86]], double noundef [[TMP87]], double noundef [[TMP88]], double noundef [[TMP89]], double noundef [[TMP91]], i32 noundef [[TMP92]]) 2708 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2709 // CHECK1: omp.body.continue: 2710 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2711 // CHECK1: omp.inner.for.inc: 2712 // CHECK1-NEXT: [[TMP93:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2713 // CHECK1-NEXT: [[ADD225:%.*]] = add nsw i64 [[TMP93]], 1 2714 // CHECK1-NEXT: store i64 [[ADD225]], ptr [[DOTOMP_IV]], align 8 2715 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 2716 // CHECK1: omp.inner.for.end: 2717 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2718 // CHECK1: omp.loop.exit: 2719 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) 2720 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 2721 // CHECK1: omp.precond.end: 2722 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) 2723 // CHECK1-NEXT: ret void 2724 // 2725 // 2726 // CHECK2-LABEL: define {{[^@]+}}@body 2727 // CHECK2-SAME: (...) #[[ATTR0:[0-9]+]] { 2728 // CHECK2-NEXT: entry: 2729 // CHECK2-NEXT: ret void 2730 // 2731 // 2732 // CHECK2-LABEL: define {{[^@]+}}@foo1 2733 // CHECK2-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] { 2734 // CHECK2-NEXT: entry: 2735 // CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4 2736 // CHECK2-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4 2737 // CHECK2-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4 2738 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 2739 // CHECK2-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4 2740 // CHECK2-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4 2741 // CHECK2-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 4 2742 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[START_ADDR]], align 4 2743 // CHECK2-NEXT: store i32 [[TMP0]], ptr [[I]], align 4 2744 // CHECK2-NEXT: br label [[FOR_COND:%.*]] 2745 // CHECK2: for.cond: 2746 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4 2747 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 4 2748 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] 2749 // CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 2750 // CHECK2: for.body: 2751 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[I]], align 4 2752 // CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP3]]) 2753 // CHECK2-NEXT: br label [[FOR_INC:%.*]] 2754 // CHECK2: for.inc: 2755 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 2756 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4 2757 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 2758 // CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4 2759 // CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 2760 // CHECK2: for.end: 2761 // CHECK2-NEXT: ret void 2762 // 2763 // 2764 // CHECK2-LABEL: define {{[^@]+}}@foo10 2765 // CHECK2-SAME: () #[[ATTR0]] { 2766 // CHECK2-NEXT: entry: 2767 // CHECK2-NEXT: [[A:%.*]] = alloca [128 x double], align 16 2768 // CHECK2-NEXT: [[B:%.*]] = alloca [16 x double], align 16 2769 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2770 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 2771 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i64, align 8 2772 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca i64, align 8 2773 // CHECK2-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 2774 // CHECK2-NEXT: [[C:%.*]] = alloca double, align 8 2775 // CHECK2-NEXT: [[__RANGE3:%.*]] = alloca ptr, align 8 2776 // CHECK2-NEXT: [[__END3:%.*]] = alloca ptr, align 8 2777 // CHECK2-NEXT: [[__BEGIN3:%.*]] = alloca ptr, align 8 2778 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 8 2779 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca ptr, align 8 2780 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_7:%.*]] = alloca i64, align 8 2781 // CHECK2-NEXT: [[D:%.*]] = alloca double, align 8 2782 // CHECK2-NEXT: [[__RANGE4:%.*]] = alloca ptr, align 8 2783 // CHECK2-NEXT: [[__END4:%.*]] = alloca ptr, align 8 2784 // CHECK2-NEXT: [[__BEGIN4:%.*]] = alloca ptr, align 8 2785 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_12:%.*]] = alloca ptr, align 8 2786 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca ptr, align 8 2787 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_15:%.*]] = alloca i64, align 8 2788 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i64, align 8 2789 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i64, align 8 2790 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i64, align 8 2791 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 2792 // CHECK2-NEXT: [[DOTPERMUTED_0_IV___BEGIN4:%.*]] = alloca i64, align 8 2793 // CHECK2-NEXT: [[DOTPERMUTED_1_IV___BEGIN3:%.*]] = alloca i64, align 8 2794 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4 2795 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2796 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2797 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2798 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2799 // CHECK2-NEXT: [[I37:%.*]] = alloca i32, align 4 2800 // CHECK2-NEXT: [[DOTPERMUTED_0_IV___BEGIN438:%.*]] = alloca i64, align 8 2801 // CHECK2-NEXT: [[DOTPERMUTED_1_IV___BEGIN339:%.*]] = alloca i64, align 8 2802 // CHECK2-NEXT: [[J40:%.*]] = alloca i32, align 4 2803 // CHECK2-NEXT: [[BB:%.*]] = alloca ptr, align 8 2804 // CHECK2-NEXT: [[AA:%.*]] = alloca double, align 8 2805 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 2806 // CHECK2-NEXT: store double 4.200000e+01, ptr [[C]], align 8 2807 // CHECK2-NEXT: store ptr [[A]], ptr [[__RANGE3]], align 8 2808 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE3]], align 8 2809 // CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 0 2810 // CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 128 2811 // CHECK2-NEXT: store ptr [[ADD_PTR]], ptr [[__END3]], align 8 2812 // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE3]], align 8 2813 // CHECK2-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 0 2814 // CHECK2-NEXT: store ptr [[ARRAYDECAY4]], ptr [[__BEGIN3]], align 8 2815 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__RANGE3]], align 8 2816 // CHECK2-NEXT: [[ARRAYDECAY5:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP3]], i64 0, i64 0 2817 // CHECK2-NEXT: store ptr [[ARRAYDECAY5]], ptr [[DOTCAPTURE_EXPR_]], align 8 2818 // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__END3]], align 8 2819 // CHECK2-NEXT: store ptr [[TMP4]], ptr [[DOTCAPTURE_EXPR_6]], align 8 2820 // CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 8 2821 // CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8 2822 // CHECK2-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i64 2823 // CHECK2-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP6]] to i64 2824 // CHECK2-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] 2825 // CHECK2-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 8 2826 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 2827 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 2828 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 2829 // CHECK2-NEXT: [[SUB8:%.*]] = sub nsw i64 [[DIV]], 1 2830 // CHECK2-NEXT: store i64 [[SUB8]], ptr [[DOTCAPTURE_EXPR_7]], align 8 2831 // CHECK2-NEXT: store double 4.200000e+01, ptr [[D]], align 8 2832 // CHECK2-NEXT: store ptr [[B]], ptr [[__RANGE4]], align 8 2833 // CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[__RANGE4]], align 8 2834 // CHECK2-NEXT: [[ARRAYDECAY9:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP7]], i64 0, i64 0 2835 // CHECK2-NEXT: [[ADD_PTR10:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY9]], i64 16 2836 // CHECK2-NEXT: store ptr [[ADD_PTR10]], ptr [[__END4]], align 8 2837 // CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__RANGE4]], align 8 2838 // CHECK2-NEXT: [[ARRAYDECAY11:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP8]], i64 0, i64 0 2839 // CHECK2-NEXT: store ptr [[ARRAYDECAY11]], ptr [[__BEGIN4]], align 8 2840 // CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__RANGE4]], align 8 2841 // CHECK2-NEXT: [[ARRAYDECAY13:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP9]], i64 0, i64 0 2842 // CHECK2-NEXT: store ptr [[ARRAYDECAY13]], ptr [[DOTCAPTURE_EXPR_12]], align 8 2843 // CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[__END4]], align 8 2844 // CHECK2-NEXT: store ptr [[TMP10]], ptr [[DOTCAPTURE_EXPR_14]], align 8 2845 // CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_14]], align 8 2846 // CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_12]], align 8 2847 // CHECK2-NEXT: [[SUB_PTR_LHS_CAST16:%.*]] = ptrtoint ptr [[TMP11]] to i64 2848 // CHECK2-NEXT: [[SUB_PTR_RHS_CAST17:%.*]] = ptrtoint ptr [[TMP12]] to i64 2849 // CHECK2-NEXT: [[SUB_PTR_SUB18:%.*]] = sub i64 [[SUB_PTR_LHS_CAST16]], [[SUB_PTR_RHS_CAST17]] 2850 // CHECK2-NEXT: [[SUB_PTR_DIV19:%.*]] = sdiv exact i64 [[SUB_PTR_SUB18]], 8 2851 // CHECK2-NEXT: [[SUB20:%.*]] = sub nsw i64 [[SUB_PTR_DIV19]], 1 2852 // CHECK2-NEXT: [[ADD21:%.*]] = add nsw i64 [[SUB20]], 1 2853 // CHECK2-NEXT: [[DIV22:%.*]] = sdiv i64 [[ADD21]], 1 2854 // CHECK2-NEXT: [[SUB23:%.*]] = sub nsw i64 [[DIV22]], 1 2855 // CHECK2-NEXT: store i64 [[SUB23]], ptr [[DOTCAPTURE_EXPR_15]], align 8 2856 // CHECK2-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_15]], align 8 2857 // CHECK2-NEXT: [[ADD25:%.*]] = add nsw i64 [[TMP13]], 1 2858 // CHECK2-NEXT: store i64 [[ADD25]], ptr [[DOTCAPTURE_EXPR_24]], align 8 2859 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_7]], align 8 2860 // CHECK2-NEXT: [[ADD27:%.*]] = add nsw i64 [[TMP14]], 1 2861 // CHECK2-NEXT: store i64 [[ADD27]], ptr [[DOTCAPTURE_EXPR_26]], align 8 2862 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2863 // CHECK2-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP15]], 0 2864 // CHECK2-NEXT: [[DIV30:%.*]] = sdiv i64 [[SUB29]], 1 2865 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 128, [[DIV30]] 2866 // CHECK2-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2867 // CHECK2-NEXT: [[SUB31:%.*]] = sub nsw i64 [[TMP16]], 0 2868 // CHECK2-NEXT: [[DIV32:%.*]] = sdiv i64 [[SUB31]], 1 2869 // CHECK2-NEXT: [[MUL33:%.*]] = mul nsw i64 [[MUL]], [[DIV32]] 2870 // CHECK2-NEXT: [[MUL34:%.*]] = mul nsw i64 [[MUL33]], 128 2871 // CHECK2-NEXT: [[SUB35:%.*]] = sub nsw i64 [[MUL34]], 1 2872 // CHECK2-NEXT: store i64 [[SUB35]], ptr [[DOTCAPTURE_EXPR_28]], align 8 2873 // CHECK2-NEXT: store i32 0, ptr [[I]], align 4 2874 // CHECK2-NEXT: store i64 0, ptr [[DOTPERMUTED_0_IV___BEGIN4]], align 8 2875 // CHECK2-NEXT: store i64 0, ptr [[DOTPERMUTED_1_IV___BEGIN3]], align 8 2876 // CHECK2-NEXT: store i32 0, ptr [[J]], align 4 2877 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2878 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i64 0, [[TMP17]] 2879 // CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 2880 // CHECK2: land.lhs.true: 2881 // CHECK2-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2882 // CHECK2-NEXT: [[CMP36:%.*]] = icmp slt i64 0, [[TMP18]] 2883 // CHECK2-NEXT: br i1 [[CMP36]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 2884 // CHECK2: omp.precond.then: 2885 // CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 2886 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_28]], align 8 2887 // CHECK2-NEXT: store i64 [[TMP19]], ptr [[DOTOMP_UB]], align 8 2888 // CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 2889 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2890 // CHECK2-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 2891 // CHECK2-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 2892 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_28]], align 8 2893 // CHECK2-NEXT: [[CMP41:%.*]] = icmp sgt i64 [[TMP20]], [[TMP21]] 2894 // CHECK2-NEXT: br i1 [[CMP41]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2895 // CHECK2: cond.true: 2896 // CHECK2-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_28]], align 8 2897 // CHECK2-NEXT: br label [[COND_END:%.*]] 2898 // CHECK2: cond.false: 2899 // CHECK2-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 2900 // CHECK2-NEXT: br label [[COND_END]] 2901 // CHECK2: cond.end: 2902 // CHECK2-NEXT: [[COND:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE]] ], [ [[TMP23]], [[COND_FALSE]] ] 2903 // CHECK2-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 2904 // CHECK2-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 2905 // CHECK2-NEXT: store i64 [[TMP24]], ptr [[DOTOMP_IV]], align 8 2906 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2907 // CHECK2: omp.inner.for.cond: 2908 // CHECK2-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2909 // CHECK2-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 2910 // CHECK2-NEXT: [[CMP42:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]] 2911 // CHECK2-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2912 // CHECK2: omp.inner.for.body: 2913 // CHECK2-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2914 // CHECK2-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2915 // CHECK2-NEXT: [[SUB43:%.*]] = sub nsw i64 [[TMP28]], 0 2916 // CHECK2-NEXT: [[DIV44:%.*]] = sdiv i64 [[SUB43]], 1 2917 // CHECK2-NEXT: [[MUL45:%.*]] = mul nsw i64 1, [[DIV44]] 2918 // CHECK2-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2919 // CHECK2-NEXT: [[SUB46:%.*]] = sub nsw i64 [[TMP29]], 0 2920 // CHECK2-NEXT: [[DIV47:%.*]] = sdiv i64 [[SUB46]], 1 2921 // CHECK2-NEXT: [[MUL48:%.*]] = mul nsw i64 [[MUL45]], [[DIV47]] 2922 // CHECK2-NEXT: [[MUL49:%.*]] = mul nsw i64 [[MUL48]], 128 2923 // CHECK2-NEXT: [[DIV50:%.*]] = sdiv i64 [[TMP27]], [[MUL49]] 2924 // CHECK2-NEXT: [[MUL51:%.*]] = mul nsw i64 [[DIV50]], 1 2925 // CHECK2-NEXT: [[ADD52:%.*]] = add nsw i64 0, [[MUL51]] 2926 // CHECK2-NEXT: [[CONV:%.*]] = trunc i64 [[ADD52]] to i32 2927 // CHECK2-NEXT: store i32 [[CONV]], ptr [[I37]], align 4 2928 // CHECK2-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2929 // CHECK2-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2930 // CHECK2-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2931 // CHECK2-NEXT: [[SUB53:%.*]] = sub nsw i64 [[TMP32]], 0 2932 // CHECK2-NEXT: [[DIV54:%.*]] = sdiv i64 [[SUB53]], 1 2933 // CHECK2-NEXT: [[MUL55:%.*]] = mul nsw i64 1, [[DIV54]] 2934 // CHECK2-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2935 // CHECK2-NEXT: [[SUB56:%.*]] = sub nsw i64 [[TMP33]], 0 2936 // CHECK2-NEXT: [[DIV57:%.*]] = sdiv i64 [[SUB56]], 1 2937 // CHECK2-NEXT: [[MUL58:%.*]] = mul nsw i64 [[MUL55]], [[DIV57]] 2938 // CHECK2-NEXT: [[MUL59:%.*]] = mul nsw i64 [[MUL58]], 128 2939 // CHECK2-NEXT: [[DIV60:%.*]] = sdiv i64 [[TMP31]], [[MUL59]] 2940 // CHECK2-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2941 // CHECK2-NEXT: [[SUB61:%.*]] = sub nsw i64 [[TMP34]], 0 2942 // CHECK2-NEXT: [[DIV62:%.*]] = sdiv i64 [[SUB61]], 1 2943 // CHECK2-NEXT: [[MUL63:%.*]] = mul nsw i64 1, [[DIV62]] 2944 // CHECK2-NEXT: [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2945 // CHECK2-NEXT: [[SUB64:%.*]] = sub nsw i64 [[TMP35]], 0 2946 // CHECK2-NEXT: [[DIV65:%.*]] = sdiv i64 [[SUB64]], 1 2947 // CHECK2-NEXT: [[MUL66:%.*]] = mul nsw i64 [[MUL63]], [[DIV65]] 2948 // CHECK2-NEXT: [[MUL67:%.*]] = mul nsw i64 [[MUL66]], 128 2949 // CHECK2-NEXT: [[MUL68:%.*]] = mul nsw i64 [[DIV60]], [[MUL67]] 2950 // CHECK2-NEXT: [[SUB69:%.*]] = sub nsw i64 [[TMP30]], [[MUL68]] 2951 // CHECK2-NEXT: [[TMP36:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2952 // CHECK2-NEXT: [[SUB70:%.*]] = sub nsw i64 [[TMP36]], 0 2953 // CHECK2-NEXT: [[DIV71:%.*]] = sdiv i64 [[SUB70]], 1 2954 // CHECK2-NEXT: [[MUL72:%.*]] = mul nsw i64 1, [[DIV71]] 2955 // CHECK2-NEXT: [[MUL73:%.*]] = mul nsw i64 [[MUL72]], 128 2956 // CHECK2-NEXT: [[DIV74:%.*]] = sdiv i64 [[SUB69]], [[MUL73]] 2957 // CHECK2-NEXT: [[MUL75:%.*]] = mul nsw i64 [[DIV74]], 1 2958 // CHECK2-NEXT: [[ADD76:%.*]] = add nsw i64 0, [[MUL75]] 2959 // CHECK2-NEXT: store i64 [[ADD76]], ptr [[DOTPERMUTED_0_IV___BEGIN438]], align 8 2960 // CHECK2-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2961 // CHECK2-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2962 // CHECK2-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2963 // CHECK2-NEXT: [[SUB77:%.*]] = sub nsw i64 [[TMP39]], 0 2964 // CHECK2-NEXT: [[DIV78:%.*]] = sdiv i64 [[SUB77]], 1 2965 // CHECK2-NEXT: [[MUL79:%.*]] = mul nsw i64 1, [[DIV78]] 2966 // CHECK2-NEXT: [[TMP40:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2967 // CHECK2-NEXT: [[SUB80:%.*]] = sub nsw i64 [[TMP40]], 0 2968 // CHECK2-NEXT: [[DIV81:%.*]] = sdiv i64 [[SUB80]], 1 2969 // CHECK2-NEXT: [[MUL82:%.*]] = mul nsw i64 [[MUL79]], [[DIV81]] 2970 // CHECK2-NEXT: [[MUL83:%.*]] = mul nsw i64 [[MUL82]], 128 2971 // CHECK2-NEXT: [[DIV84:%.*]] = sdiv i64 [[TMP38]], [[MUL83]] 2972 // CHECK2-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2973 // CHECK2-NEXT: [[SUB85:%.*]] = sub nsw i64 [[TMP41]], 0 2974 // CHECK2-NEXT: [[DIV86:%.*]] = sdiv i64 [[SUB85]], 1 2975 // CHECK2-NEXT: [[MUL87:%.*]] = mul nsw i64 1, [[DIV86]] 2976 // CHECK2-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2977 // CHECK2-NEXT: [[SUB88:%.*]] = sub nsw i64 [[TMP42]], 0 2978 // CHECK2-NEXT: [[DIV89:%.*]] = sdiv i64 [[SUB88]], 1 2979 // CHECK2-NEXT: [[MUL90:%.*]] = mul nsw i64 [[MUL87]], [[DIV89]] 2980 // CHECK2-NEXT: [[MUL91:%.*]] = mul nsw i64 [[MUL90]], 128 2981 // CHECK2-NEXT: [[MUL92:%.*]] = mul nsw i64 [[DIV84]], [[MUL91]] 2982 // CHECK2-NEXT: [[SUB93:%.*]] = sub nsw i64 [[TMP37]], [[MUL92]] 2983 // CHECK2-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2984 // CHECK2-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 2985 // CHECK2-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2986 // CHECK2-NEXT: [[SUB94:%.*]] = sub nsw i64 [[TMP45]], 0 2987 // CHECK2-NEXT: [[DIV95:%.*]] = sdiv i64 [[SUB94]], 1 2988 // CHECK2-NEXT: [[MUL96:%.*]] = mul nsw i64 1, [[DIV95]] 2989 // CHECK2-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 2990 // CHECK2-NEXT: [[SUB97:%.*]] = sub nsw i64 [[TMP46]], 0 2991 // CHECK2-NEXT: [[DIV98:%.*]] = sdiv i64 [[SUB97]], 1 2992 // CHECK2-NEXT: [[MUL99:%.*]] = mul nsw i64 [[MUL96]], [[DIV98]] 2993 // CHECK2-NEXT: [[MUL100:%.*]] = mul nsw i64 [[MUL99]], 128 2994 // CHECK2-NEXT: [[DIV101:%.*]] = sdiv i64 [[TMP44]], [[MUL100]] 2995 // CHECK2-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 2996 // CHECK2-NEXT: [[SUB102:%.*]] = sub nsw i64 [[TMP47]], 0 2997 // CHECK2-NEXT: [[DIV103:%.*]] = sdiv i64 [[SUB102]], 1 2998 // CHECK2-NEXT: [[MUL104:%.*]] = mul nsw i64 1, [[DIV103]] 2999 // CHECK2-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 3000 // CHECK2-NEXT: [[SUB105:%.*]] = sub nsw i64 [[TMP48]], 0 3001 // CHECK2-NEXT: [[DIV106:%.*]] = sdiv i64 [[SUB105]], 1 3002 // CHECK2-NEXT: [[MUL107:%.*]] = mul nsw i64 [[MUL104]], [[DIV106]] 3003 // CHECK2-NEXT: [[MUL108:%.*]] = mul nsw i64 [[MUL107]], 128 3004 // CHECK2-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV101]], [[MUL108]] 3005 // CHECK2-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP43]], [[MUL109]] 3006 // CHECK2-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 3007 // CHECK2-NEXT: [[SUB111:%.*]] = sub nsw i64 [[TMP49]], 0 3008 // CHECK2-NEXT: [[DIV112:%.*]] = sdiv i64 [[SUB111]], 1 3009 // CHECK2-NEXT: [[MUL113:%.*]] = mul nsw i64 1, [[DIV112]] 3010 // CHECK2-NEXT: [[MUL114:%.*]] = mul nsw i64 [[MUL113]], 128 3011 // CHECK2-NEXT: [[DIV115:%.*]] = sdiv i64 [[SUB110]], [[MUL114]] 3012 // CHECK2-NEXT: [[TMP50:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 3013 // CHECK2-NEXT: [[SUB116:%.*]] = sub nsw i64 [[TMP50]], 0 3014 // CHECK2-NEXT: [[DIV117:%.*]] = sdiv i64 [[SUB116]], 1 3015 // CHECK2-NEXT: [[MUL118:%.*]] = mul nsw i64 1, [[DIV117]] 3016 // CHECK2-NEXT: [[MUL119:%.*]] = mul nsw i64 [[MUL118]], 128 3017 // CHECK2-NEXT: [[MUL120:%.*]] = mul nsw i64 [[DIV115]], [[MUL119]] 3018 // CHECK2-NEXT: [[SUB121:%.*]] = sub nsw i64 [[SUB93]], [[MUL120]] 3019 // CHECK2-NEXT: [[DIV122:%.*]] = sdiv i64 [[SUB121]], 128 3020 // CHECK2-NEXT: [[MUL123:%.*]] = mul nsw i64 [[DIV122]], 1 3021 // CHECK2-NEXT: [[ADD124:%.*]] = add nsw i64 0, [[MUL123]] 3022 // CHECK2-NEXT: store i64 [[ADD124]], ptr [[DOTPERMUTED_1_IV___BEGIN339]], align 8 3023 // CHECK2-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 3024 // CHECK2-NEXT: [[TMP52:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 3025 // CHECK2-NEXT: [[TMP53:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 3026 // CHECK2-NEXT: [[SUB125:%.*]] = sub nsw i64 [[TMP53]], 0 3027 // CHECK2-NEXT: [[DIV126:%.*]] = sdiv i64 [[SUB125]], 1 3028 // CHECK2-NEXT: [[MUL127:%.*]] = mul nsw i64 1, [[DIV126]] 3029 // CHECK2-NEXT: [[TMP54:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 3030 // CHECK2-NEXT: [[SUB128:%.*]] = sub nsw i64 [[TMP54]], 0 3031 // CHECK2-NEXT: [[DIV129:%.*]] = sdiv i64 [[SUB128]], 1 3032 // CHECK2-NEXT: [[MUL130:%.*]] = mul nsw i64 [[MUL127]], [[DIV129]] 3033 // CHECK2-NEXT: [[MUL131:%.*]] = mul nsw i64 [[MUL130]], 128 3034 // CHECK2-NEXT: [[DIV132:%.*]] = sdiv i64 [[TMP52]], [[MUL131]] 3035 // CHECK2-NEXT: [[TMP55:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 3036 // CHECK2-NEXT: [[SUB133:%.*]] = sub nsw i64 [[TMP55]], 0 3037 // CHECK2-NEXT: [[DIV134:%.*]] = sdiv i64 [[SUB133]], 1 3038 // CHECK2-NEXT: [[MUL135:%.*]] = mul nsw i64 1, [[DIV134]] 3039 // CHECK2-NEXT: [[TMP56:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 3040 // CHECK2-NEXT: [[SUB136:%.*]] = sub nsw i64 [[TMP56]], 0 3041 // CHECK2-NEXT: [[DIV137:%.*]] = sdiv i64 [[SUB136]], 1 3042 // CHECK2-NEXT: [[MUL138:%.*]] = mul nsw i64 [[MUL135]], [[DIV137]] 3043 // CHECK2-NEXT: [[MUL139:%.*]] = mul nsw i64 [[MUL138]], 128 3044 // CHECK2-NEXT: [[MUL140:%.*]] = mul nsw i64 [[DIV132]], [[MUL139]] 3045 // CHECK2-NEXT: [[SUB141:%.*]] = sub nsw i64 [[TMP51]], [[MUL140]] 3046 // CHECK2-NEXT: [[TMP57:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 3047 // CHECK2-NEXT: [[TMP58:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 3048 // CHECK2-NEXT: [[TMP59:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 3049 // CHECK2-NEXT: [[SUB142:%.*]] = sub nsw i64 [[TMP59]], 0 3050 // CHECK2-NEXT: [[DIV143:%.*]] = sdiv i64 [[SUB142]], 1 3051 // CHECK2-NEXT: [[MUL144:%.*]] = mul nsw i64 1, [[DIV143]] 3052 // CHECK2-NEXT: [[TMP60:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 3053 // CHECK2-NEXT: [[SUB145:%.*]] = sub nsw i64 [[TMP60]], 0 3054 // CHECK2-NEXT: [[DIV146:%.*]] = sdiv i64 [[SUB145]], 1 3055 // CHECK2-NEXT: [[MUL147:%.*]] = mul nsw i64 [[MUL144]], [[DIV146]] 3056 // CHECK2-NEXT: [[MUL148:%.*]] = mul nsw i64 [[MUL147]], 128 3057 // CHECK2-NEXT: [[DIV149:%.*]] = sdiv i64 [[TMP58]], [[MUL148]] 3058 // CHECK2-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 3059 // CHECK2-NEXT: [[SUB150:%.*]] = sub nsw i64 [[TMP61]], 0 3060 // CHECK2-NEXT: [[DIV151:%.*]] = sdiv i64 [[SUB150]], 1 3061 // CHECK2-NEXT: [[MUL152:%.*]] = mul nsw i64 1, [[DIV151]] 3062 // CHECK2-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 3063 // CHECK2-NEXT: [[SUB153:%.*]] = sub nsw i64 [[TMP62]], 0 3064 // CHECK2-NEXT: [[DIV154:%.*]] = sdiv i64 [[SUB153]], 1 3065 // CHECK2-NEXT: [[MUL155:%.*]] = mul nsw i64 [[MUL152]], [[DIV154]] 3066 // CHECK2-NEXT: [[MUL156:%.*]] = mul nsw i64 [[MUL155]], 128 3067 // CHECK2-NEXT: [[MUL157:%.*]] = mul nsw i64 [[DIV149]], [[MUL156]] 3068 // CHECK2-NEXT: [[SUB158:%.*]] = sub nsw i64 [[TMP57]], [[MUL157]] 3069 // CHECK2-NEXT: [[TMP63:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 3070 // CHECK2-NEXT: [[SUB159:%.*]] = sub nsw i64 [[TMP63]], 0 3071 // CHECK2-NEXT: [[DIV160:%.*]] = sdiv i64 [[SUB159]], 1 3072 // CHECK2-NEXT: [[MUL161:%.*]] = mul nsw i64 1, [[DIV160]] 3073 // CHECK2-NEXT: [[MUL162:%.*]] = mul nsw i64 [[MUL161]], 128 3074 // CHECK2-NEXT: [[DIV163:%.*]] = sdiv i64 [[SUB158]], [[MUL162]] 3075 // CHECK2-NEXT: [[TMP64:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 3076 // CHECK2-NEXT: [[SUB164:%.*]] = sub nsw i64 [[TMP64]], 0 3077 // CHECK2-NEXT: [[DIV165:%.*]] = sdiv i64 [[SUB164]], 1 3078 // CHECK2-NEXT: [[MUL166:%.*]] = mul nsw i64 1, [[DIV165]] 3079 // CHECK2-NEXT: [[MUL167:%.*]] = mul nsw i64 [[MUL166]], 128 3080 // CHECK2-NEXT: [[MUL168:%.*]] = mul nsw i64 [[DIV163]], [[MUL167]] 3081 // CHECK2-NEXT: [[SUB169:%.*]] = sub nsw i64 [[SUB141]], [[MUL168]] 3082 // CHECK2-NEXT: [[TMP65:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 3083 // CHECK2-NEXT: [[TMP66:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 3084 // CHECK2-NEXT: [[TMP67:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 3085 // CHECK2-NEXT: [[SUB170:%.*]] = sub nsw i64 [[TMP67]], 0 3086 // CHECK2-NEXT: [[DIV171:%.*]] = sdiv i64 [[SUB170]], 1 3087 // CHECK2-NEXT: [[MUL172:%.*]] = mul nsw i64 1, [[DIV171]] 3088 // CHECK2-NEXT: [[TMP68:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 3089 // CHECK2-NEXT: [[SUB173:%.*]] = sub nsw i64 [[TMP68]], 0 3090 // CHECK2-NEXT: [[DIV174:%.*]] = sdiv i64 [[SUB173]], 1 3091 // CHECK2-NEXT: [[MUL175:%.*]] = mul nsw i64 [[MUL172]], [[DIV174]] 3092 // CHECK2-NEXT: [[MUL176:%.*]] = mul nsw i64 [[MUL175]], 128 3093 // CHECK2-NEXT: [[DIV177:%.*]] = sdiv i64 [[TMP66]], [[MUL176]] 3094 // CHECK2-NEXT: [[TMP69:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 3095 // CHECK2-NEXT: [[SUB178:%.*]] = sub nsw i64 [[TMP69]], 0 3096 // CHECK2-NEXT: [[DIV179:%.*]] = sdiv i64 [[SUB178]], 1 3097 // CHECK2-NEXT: [[MUL180:%.*]] = mul nsw i64 1, [[DIV179]] 3098 // CHECK2-NEXT: [[TMP70:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 3099 // CHECK2-NEXT: [[SUB181:%.*]] = sub nsw i64 [[TMP70]], 0 3100 // CHECK2-NEXT: [[DIV182:%.*]] = sdiv i64 [[SUB181]], 1 3101 // CHECK2-NEXT: [[MUL183:%.*]] = mul nsw i64 [[MUL180]], [[DIV182]] 3102 // CHECK2-NEXT: [[MUL184:%.*]] = mul nsw i64 [[MUL183]], 128 3103 // CHECK2-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV177]], [[MUL184]] 3104 // CHECK2-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP65]], [[MUL185]] 3105 // CHECK2-NEXT: [[TMP71:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 3106 // CHECK2-NEXT: [[TMP72:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 3107 // CHECK2-NEXT: [[TMP73:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 3108 // CHECK2-NEXT: [[SUB187:%.*]] = sub nsw i64 [[TMP73]], 0 3109 // CHECK2-NEXT: [[DIV188:%.*]] = sdiv i64 [[SUB187]], 1 3110 // CHECK2-NEXT: [[MUL189:%.*]] = mul nsw i64 1, [[DIV188]] 3111 // CHECK2-NEXT: [[TMP74:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 3112 // CHECK2-NEXT: [[SUB190:%.*]] = sub nsw i64 [[TMP74]], 0 3113 // CHECK2-NEXT: [[DIV191:%.*]] = sdiv i64 [[SUB190]], 1 3114 // CHECK2-NEXT: [[MUL192:%.*]] = mul nsw i64 [[MUL189]], [[DIV191]] 3115 // CHECK2-NEXT: [[MUL193:%.*]] = mul nsw i64 [[MUL192]], 128 3116 // CHECK2-NEXT: [[DIV194:%.*]] = sdiv i64 [[TMP72]], [[MUL193]] 3117 // CHECK2-NEXT: [[TMP75:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8 3118 // CHECK2-NEXT: [[SUB195:%.*]] = sub nsw i64 [[TMP75]], 0 3119 // CHECK2-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB195]], 1 3120 // CHECK2-NEXT: [[MUL197:%.*]] = mul nsw i64 1, [[DIV196]] 3121 // CHECK2-NEXT: [[TMP76:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 3122 // CHECK2-NEXT: [[SUB198:%.*]] = sub nsw i64 [[TMP76]], 0 3123 // CHECK2-NEXT: [[DIV199:%.*]] = sdiv i64 [[SUB198]], 1 3124 // CHECK2-NEXT: [[MUL200:%.*]] = mul nsw i64 [[MUL197]], [[DIV199]] 3125 // CHECK2-NEXT: [[MUL201:%.*]] = mul nsw i64 [[MUL200]], 128 3126 // CHECK2-NEXT: [[MUL202:%.*]] = mul nsw i64 [[DIV194]], [[MUL201]] 3127 // CHECK2-NEXT: [[SUB203:%.*]] = sub nsw i64 [[TMP71]], [[MUL202]] 3128 // CHECK2-NEXT: [[TMP77:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 3129 // CHECK2-NEXT: [[SUB204:%.*]] = sub nsw i64 [[TMP77]], 0 3130 // CHECK2-NEXT: [[DIV205:%.*]] = sdiv i64 [[SUB204]], 1 3131 // CHECK2-NEXT: [[MUL206:%.*]] = mul nsw i64 1, [[DIV205]] 3132 // CHECK2-NEXT: [[MUL207:%.*]] = mul nsw i64 [[MUL206]], 128 3133 // CHECK2-NEXT: [[DIV208:%.*]] = sdiv i64 [[SUB203]], [[MUL207]] 3134 // CHECK2-NEXT: [[TMP78:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8 3135 // CHECK2-NEXT: [[SUB209:%.*]] = sub nsw i64 [[TMP78]], 0 3136 // CHECK2-NEXT: [[DIV210:%.*]] = sdiv i64 [[SUB209]], 1 3137 // CHECK2-NEXT: [[MUL211:%.*]] = mul nsw i64 1, [[DIV210]] 3138 // CHECK2-NEXT: [[MUL212:%.*]] = mul nsw i64 [[MUL211]], 128 3139 // CHECK2-NEXT: [[MUL213:%.*]] = mul nsw i64 [[DIV208]], [[MUL212]] 3140 // CHECK2-NEXT: [[SUB214:%.*]] = sub nsw i64 [[SUB186]], [[MUL213]] 3141 // CHECK2-NEXT: [[DIV215:%.*]] = sdiv i64 [[SUB214]], 128 3142 // CHECK2-NEXT: [[MUL216:%.*]] = mul nsw i64 [[DIV215]], 128 3143 // CHECK2-NEXT: [[SUB217:%.*]] = sub nsw i64 [[SUB169]], [[MUL216]] 3144 // CHECK2-NEXT: [[MUL218:%.*]] = mul nsw i64 [[SUB217]], 1 3145 // CHECK2-NEXT: [[ADD219:%.*]] = add nsw i64 0, [[MUL218]] 3146 // CHECK2-NEXT: [[CONV220:%.*]] = trunc i64 [[ADD219]] to i32 3147 // CHECK2-NEXT: store i32 [[CONV220]], ptr [[J40]], align 4 3148 // CHECK2-NEXT: [[TMP79:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_12]], align 8 3149 // CHECK2-NEXT: [[TMP80:%.*]] = load i64, ptr [[DOTPERMUTED_0_IV___BEGIN438]], align 8 3150 // CHECK2-NEXT: [[MUL221:%.*]] = mul nsw i64 [[TMP80]], 1 3151 // CHECK2-NEXT: [[ADD_PTR222:%.*]] = getelementptr inbounds double, ptr [[TMP79]], i64 [[MUL221]] 3152 // CHECK2-NEXT: store ptr [[ADD_PTR222]], ptr [[__BEGIN4]], align 8 3153 // CHECK2-NEXT: [[TMP81:%.*]] = load ptr, ptr [[__BEGIN4]], align 8 3154 // CHECK2-NEXT: store ptr [[TMP81]], ptr [[BB]], align 8 3155 // CHECK2-NEXT: [[TMP82:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8 3156 // CHECK2-NEXT: [[TMP83:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN339]], align 8 3157 // CHECK2-NEXT: [[MUL223:%.*]] = mul nsw i64 [[TMP83]], 1 3158 // CHECK2-NEXT: [[ADD_PTR224:%.*]] = getelementptr inbounds double, ptr [[TMP82]], i64 [[MUL223]] 3159 // CHECK2-NEXT: store ptr [[ADD_PTR224]], ptr [[__BEGIN3]], align 8 3160 // CHECK2-NEXT: [[TMP84:%.*]] = load ptr, ptr [[__BEGIN3]], align 8 3161 // CHECK2-NEXT: [[TMP85:%.*]] = load double, ptr [[TMP84]], align 8 3162 // CHECK2-NEXT: store double [[TMP85]], ptr [[AA]], align 8 3163 // CHECK2-NEXT: [[TMP86:%.*]] = load i32, ptr [[I37]], align 4 3164 // CHECK2-NEXT: [[TMP87:%.*]] = load double, ptr [[C]], align 8 3165 // CHECK2-NEXT: [[TMP88:%.*]] = load double, ptr [[AA]], align 8 3166 // CHECK2-NEXT: [[TMP89:%.*]] = load double, ptr [[D]], align 8 3167 // CHECK2-NEXT: [[TMP90:%.*]] = load ptr, ptr [[BB]], align 8 3168 // CHECK2-NEXT: [[TMP91:%.*]] = load double, ptr [[TMP90]], align 8 3169 // CHECK2-NEXT: [[TMP92:%.*]] = load i32, ptr [[J40]], align 4 3170 // CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP86]], double noundef [[TMP87]], double noundef [[TMP88]], double noundef [[TMP89]], double noundef [[TMP91]], i32 noundef [[TMP92]]) 3171 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3172 // CHECK2: omp.body.continue: 3173 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3174 // CHECK2: omp.inner.for.inc: 3175 // CHECK2-NEXT: [[TMP93:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 3176 // CHECK2-NEXT: [[ADD225:%.*]] = add nsw i64 [[TMP93]], 1 3177 // CHECK2-NEXT: store i64 [[ADD225]], ptr [[DOTOMP_IV]], align 8 3178 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 3179 // CHECK2: omp.inner.for.end: 3180 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3181 // CHECK2: omp.loop.exit: 3182 // CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) 3183 // CHECK2-NEXT: br label [[OMP_PRECOND_END]] 3184 // CHECK2: omp.precond.end: 3185 // CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP0]]) 3186 // CHECK2-NEXT: ret void 3187 // 3188 // 3189 // CHECK2-LABEL: define {{[^@]+}}@foo2 3190 // CHECK2-SAME: (i32 noundef [[START1:%.*]], i32 noundef [[START2:%.*]], i32 noundef [[END1:%.*]], i32 noundef [[END2:%.*]], i32 noundef [[STEP1:%.*]], i32 noundef [[STEP2:%.*]]) #[[ATTR0]] { 3191 // CHECK2-NEXT: entry: 3192 // CHECK2-NEXT: [[START1_ADDR:%.*]] = alloca i32, align 4 3193 // CHECK2-NEXT: [[START2_ADDR:%.*]] = alloca i32, align 4 3194 // CHECK2-NEXT: [[END1_ADDR:%.*]] = alloca i32, align 4 3195 // CHECK2-NEXT: [[END2_ADDR:%.*]] = alloca i32, align 4 3196 // CHECK2-NEXT: [[STEP1_ADDR:%.*]] = alloca i32, align 4 3197 // CHECK2-NEXT: [[STEP2_ADDR:%.*]] = alloca i32, align 4 3198 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 3199 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3200 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3201 // CHECK2-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 4 3202 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3203 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4 3204 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 3205 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4 3206 // CHECK2-NEXT: [[DOTNEW_STEP7:%.*]] = alloca i32, align 4 3207 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4 3208 // CHECK2-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4 3209 // CHECK2-NEXT: [[DOTPERMUTED_1_IV_I:%.*]] = alloca i32, align 4 3210 // CHECK2-NEXT: store i32 [[START1]], ptr [[START1_ADDR]], align 4 3211 // CHECK2-NEXT: store i32 [[START2]], ptr [[START2_ADDR]], align 4 3212 // CHECK2-NEXT: store i32 [[END1]], ptr [[END1_ADDR]], align 4 3213 // CHECK2-NEXT: store i32 [[END2]], ptr [[END2_ADDR]], align 4 3214 // CHECK2-NEXT: store i32 [[STEP1]], ptr [[STEP1_ADDR]], align 4 3215 // CHECK2-NEXT: store i32 [[STEP2]], ptr [[STEP2_ADDR]], align 4 3216 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[START1_ADDR]], align 4 3217 // CHECK2-NEXT: store i32 [[TMP0]], ptr [[I]], align 4 3218 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[START1_ADDR]], align 4 3219 // CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 3220 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[END1_ADDR]], align 4 3221 // CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 3222 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP1_ADDR]], align 4 3223 // CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 4 3224 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 3225 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 3226 // CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP4]], [[TMP5]] 3227 // CHECK2-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 3228 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 3229 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], [[TMP6]] 3230 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 3231 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP7]] 3232 // CHECK2-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 3233 // CHECK2-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4 3234 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[START2_ADDR]], align 4 3235 // CHECK2-NEXT: store i32 [[TMP8]], ptr [[J]], align 4 3236 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[START2_ADDR]], align 4 3237 // CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_5]], align 4 3238 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[END2_ADDR]], align 4 3239 // CHECK2-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_6]], align 4 3240 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[STEP2_ADDR]], align 4 3241 // CHECK2-NEXT: store i32 [[TMP11]], ptr [[DOTNEW_STEP7]], align 4 3242 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 3243 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 3244 // CHECK2-NEXT: [[SUB9:%.*]] = sub i32 [[TMP12]], [[TMP13]] 3245 // CHECK2-NEXT: [[SUB10:%.*]] = sub i32 [[SUB9]], 1 3246 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 3247 // CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[SUB10]], [[TMP14]] 3248 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 3249 // CHECK2-NEXT: [[DIV12:%.*]] = udiv i32 [[ADD11]], [[TMP15]] 3250 // CHECK2-NEXT: [[SUB13:%.*]] = sub i32 [[DIV12]], 1 3251 // CHECK2-NEXT: store i32 [[SUB13]], ptr [[DOTCAPTURE_EXPR_8]], align 4 3252 // CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_0_IV_J]], align 4 3253 // CHECK2-NEXT: br label [[FOR_COND:%.*]] 3254 // CHECK2: for.cond: 3255 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 3256 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4 3257 // CHECK2-NEXT: [[ADD14:%.*]] = add i32 [[TMP17]], 1 3258 // CHECK2-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP16]], [[ADD14]] 3259 // CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END24:%.*]] 3260 // CHECK2: for.body: 3261 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 3262 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 3263 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 3264 // CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], [[TMP20]] 3265 // CHECK2-NEXT: [[ADD15:%.*]] = add i32 [[TMP18]], [[MUL]] 3266 // CHECK2-NEXT: store i32 [[ADD15]], ptr [[J]], align 4 3267 // CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_I]], align 4 3268 // CHECK2-NEXT: br label [[FOR_COND16:%.*]] 3269 // CHECK2: for.cond16: 3270 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 3271 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 3272 // CHECK2-NEXT: [[ADD17:%.*]] = add i32 [[TMP22]], 1 3273 // CHECK2-NEXT: [[CMP18:%.*]] = icmp ult i32 [[TMP21]], [[ADD17]] 3274 // CHECK2-NEXT: br i1 [[CMP18]], label [[FOR_BODY19:%.*]], label [[FOR_END:%.*]] 3275 // CHECK2: for.body19: 3276 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 3277 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 3278 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 3279 // CHECK2-NEXT: [[MUL20:%.*]] = mul i32 [[TMP24]], [[TMP25]] 3280 // CHECK2-NEXT: [[ADD21:%.*]] = add i32 [[TMP23]], [[MUL20]] 3281 // CHECK2-NEXT: store i32 [[ADD21]], ptr [[I]], align 4 3282 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[I]], align 4 3283 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[J]], align 4 3284 // CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP26]], i32 noundef [[TMP27]]) 3285 // CHECK2-NEXT: br label [[FOR_INC:%.*]] 3286 // CHECK2: for.inc: 3287 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 3288 // CHECK2-NEXT: [[INC:%.*]] = add i32 [[TMP28]], 1 3289 // CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4 3290 // CHECK2-NEXT: br label [[FOR_COND16]], !llvm.loop [[LOOP5:![0-9]+]] 3291 // CHECK2: for.end: 3292 // CHECK2-NEXT: br label [[FOR_INC22:%.*]] 3293 // CHECK2: for.inc22: 3294 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 3295 // CHECK2-NEXT: [[INC23:%.*]] = add i32 [[TMP29]], 1 3296 // CHECK2-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4 3297 // CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 3298 // CHECK2: for.end24: 3299 // CHECK2-NEXT: ret void 3300 // 3301 // 3302 // CHECK2-LABEL: define {{[^@]+}}@foo3 3303 // CHECK2-SAME: () #[[ATTR0]] { 3304 // CHECK2-NEXT: entry: 3305 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3306 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 3307 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 3308 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4 3309 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3310 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3311 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3312 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3313 // CHECK2-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4 3314 // CHECK2-NEXT: [[DOTPERMUTED_1_IV_I:%.*]] = alloca i32, align 4 3315 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 3316 // CHECK2-NEXT: store i32 7, ptr [[I]], align 4 3317 // CHECK2-NEXT: store i32 7, ptr [[J]], align 4 3318 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3319 // CHECK2-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4 3320 // CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3321 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3322 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3323 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3324 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 3 3325 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3326 // CHECK2: cond.true: 3327 // CHECK2-NEXT: br label [[COND_END:%.*]] 3328 // CHECK2: cond.false: 3329 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3330 // CHECK2-NEXT: br label [[COND_END]] 3331 // CHECK2: cond.end: 3332 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] 3333 // CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3334 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3335 // CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 3336 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3337 // CHECK2: omp.inner.for.cond: 3338 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3339 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3340 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 3341 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3342 // CHECK2: omp.inner.for.body: 3343 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3344 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 3345 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3346 // CHECK2-NEXT: store i32 [[ADD]], ptr [[DOTPERMUTED_0_IV_J]], align 4 3347 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 3348 // CHECK2-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP7]], 3 3349 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 7, [[MUL2]] 3350 // CHECK2-NEXT: store i32 [[ADD3]], ptr [[J]], align 4 3351 // CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_I]], align 4 3352 // CHECK2-NEXT: br label [[FOR_COND:%.*]] 3353 // CHECK2: for.cond: 3354 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 3355 // CHECK2-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP8]], 4 3356 // CHECK2-NEXT: br i1 [[CMP4]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3357 // CHECK2: for.body: 3358 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 3359 // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[TMP9]], 3 3360 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 7, [[MUL5]] 3361 // CHECK2-NEXT: store i32 [[ADD6]], ptr [[I]], align 4 3362 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 3363 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[J]], align 4 3364 // CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP10]], i32 noundef [[TMP11]]) 3365 // CHECK2-NEXT: br label [[FOR_INC:%.*]] 3366 // CHECK2: for.inc: 3367 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 3368 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 3369 // CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4 3370 // CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 3371 // CHECK2: for.end: 3372 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3373 // CHECK2: omp.body.continue: 3374 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3375 // CHECK2: omp.inner.for.inc: 3376 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3377 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP13]], 1 3378 // CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4 3379 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 3380 // CHECK2: omp.inner.for.end: 3381 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3382 // CHECK2: omp.loop.exit: 3383 // CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) 3384 // CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) 3385 // CHECK2-NEXT: ret void 3386 // 3387 // 3388 // CHECK2-LABEL: define {{[^@]+}}@foo4 3389 // CHECK2-SAME: () #[[ATTR0]] { 3390 // CHECK2-NEXT: entry: 3391 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3392 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 3393 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3394 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 3395 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4 3396 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3397 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3398 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3399 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3400 // CHECK2-NEXT: [[K:%.*]] = alloca i32, align 4 3401 // CHECK2-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4 3402 // CHECK2-NEXT: [[DOTPERMUTED_1_IV_I:%.*]] = alloca i32, align 4 3403 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 3404 // CHECK2-NEXT: store i32 7, ptr [[I]], align 4 3405 // CHECK2-NEXT: store i32 7, ptr [[J]], align 4 3406 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3407 // CHECK2-NEXT: store i32 15, ptr [[DOTOMP_UB]], align 4 3408 // CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3409 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3410 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3411 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3412 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 15 3413 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3414 // CHECK2: cond.true: 3415 // CHECK2-NEXT: br label [[COND_END:%.*]] 3416 // CHECK2: cond.false: 3417 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3418 // CHECK2-NEXT: br label [[COND_END]] 3419 // CHECK2: cond.end: 3420 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 15, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] 3421 // CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3422 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3423 // CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 3424 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3425 // CHECK2: omp.inner.for.cond: 3426 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3427 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3428 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 3429 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3430 // CHECK2: omp.inner.for.body: 3431 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3432 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 4 3433 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 3 3434 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]] 3435 // CHECK2-NEXT: store i32 [[ADD]], ptr [[K]], align 4 3436 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3437 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3438 // CHECK2-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP8]], 4 3439 // CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 4 3440 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL4]] 3441 // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 3442 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 3443 // CHECK2-NEXT: store i32 [[ADD6]], ptr [[DOTPERMUTED_0_IV_J]], align 4 3444 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 3445 // CHECK2-NEXT: [[MUL7:%.*]] = mul nsw i32 [[TMP9]], 3 3446 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 7, [[MUL7]] 3447 // CHECK2-NEXT: store i32 [[ADD8]], ptr [[J]], align 4 3448 // CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_I]], align 4 3449 // CHECK2-NEXT: br label [[FOR_COND:%.*]] 3450 // CHECK2: for.cond: 3451 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 3452 // CHECK2-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP10]], 4 3453 // CHECK2-NEXT: br i1 [[CMP9]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3454 // CHECK2: for.body: 3455 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 3456 // CHECK2-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP11]], 3 3457 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 7, [[MUL10]] 3458 // CHECK2-NEXT: store i32 [[ADD11]], ptr [[I]], align 4 3459 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 3460 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[J]], align 4 3461 // CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP12]], i32 noundef [[TMP13]]) 3462 // CHECK2-NEXT: br label [[FOR_INC:%.*]] 3463 // CHECK2: for.inc: 3464 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 3465 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 3466 // CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4 3467 // CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 3468 // CHECK2: for.end: 3469 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3470 // CHECK2: omp.body.continue: 3471 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3472 // CHECK2: omp.inner.for.inc: 3473 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3474 // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP15]], 1 3475 // CHECK2-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4 3476 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 3477 // CHECK2: omp.inner.for.end: 3478 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3479 // CHECK2: omp.loop.exit: 3480 // CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) 3481 // CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) 3482 // CHECK2-NEXT: ret void 3483 // 3484 // 3485 // CHECK2-LABEL: define {{[^@]+}}@foo5 3486 // CHECK2-SAME: () #[[ATTR0]] { 3487 // CHECK2-NEXT: entry: 3488 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3489 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 3490 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3491 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 3492 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3493 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3494 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3495 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3496 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 3497 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4 3498 // CHECK2-NEXT: [[K:%.*]] = alloca i32, align 4 3499 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 3500 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3501 // CHECK2-NEXT: store i32 63, ptr [[DOTOMP_UB]], align 4 3502 // CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3503 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3504 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3505 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3506 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 63 3507 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3508 // CHECK2: cond.true: 3509 // CHECK2-NEXT: br label [[COND_END:%.*]] 3510 // CHECK2: cond.false: 3511 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3512 // CHECK2-NEXT: br label [[COND_END]] 3513 // CHECK2: cond.end: 3514 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 63, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] 3515 // CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3516 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3517 // CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 3518 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3519 // CHECK2: omp.inner.for.cond: 3520 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3521 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3522 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 3523 // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3524 // CHECK2: omp.inner.for.body: 3525 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3526 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 16 3527 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 3 3528 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]] 3529 // CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4 3530 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3531 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3532 // CHECK2-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP8]], 16 3533 // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 16 3534 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL5]] 3535 // CHECK2-NEXT: [[DIV6:%.*]] = sdiv i32 [[SUB]], 4 3536 // CHECK2-NEXT: [[MUL7:%.*]] = mul nsw i32 [[DIV6]], 3 3537 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 7, [[MUL7]] 3538 // CHECK2-NEXT: store i32 [[ADD8]], ptr [[J]], align 4 3539 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3540 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3541 // CHECK2-NEXT: [[DIV9:%.*]] = sdiv i32 [[TMP10]], 16 3542 // CHECK2-NEXT: [[MUL10:%.*]] = mul nsw i32 [[DIV9]], 16 3543 // CHECK2-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP9]], [[MUL10]] 3544 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3545 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3546 // CHECK2-NEXT: [[DIV12:%.*]] = sdiv i32 [[TMP12]], 16 3547 // CHECK2-NEXT: [[MUL13:%.*]] = mul nsw i32 [[DIV12]], 16 3548 // CHECK2-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP11]], [[MUL13]] 3549 // CHECK2-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 4 3550 // CHECK2-NEXT: [[MUL16:%.*]] = mul nsw i32 [[DIV15]], 4 3551 // CHECK2-NEXT: [[SUB17:%.*]] = sub nsw i32 [[SUB11]], [[MUL16]] 3552 // CHECK2-NEXT: [[MUL18:%.*]] = mul nsw i32 [[SUB17]], 3 3553 // CHECK2-NEXT: [[ADD19:%.*]] = add nsw i32 7, [[MUL18]] 3554 // CHECK2-NEXT: store i32 [[ADD19]], ptr [[K]], align 4 3555 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 3556 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4 3557 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[K]], align 4 3558 // CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP13]], i32 noundef [[TMP14]], i32 noundef [[TMP15]]) 3559 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3560 // CHECK2: omp.body.continue: 3561 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3562 // CHECK2: omp.inner.for.inc: 3563 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3564 // CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP16]], 1 3565 // CHECK2-NEXT: store i32 [[ADD20]], ptr [[DOTOMP_IV]], align 4 3566 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 3567 // CHECK2: omp.inner.for.end: 3568 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3569 // CHECK2: omp.loop.exit: 3570 // CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) 3571 // CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) 3572 // CHECK2-NEXT: ret void 3573 // 3574 // 3575 // CHECK2-LABEL: define {{[^@]+}}@foo6 3576 // CHECK2-SAME: () #[[ATTR0]] { 3577 // CHECK2-NEXT: entry: 3578 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3579 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 3580 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3581 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 3582 // CHECK2-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 3583 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4 3584 // CHECK2-NEXT: [[K:%.*]] = alloca i32, align 4 3585 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3586 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3587 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3588 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3589 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 3590 // CHECK2-NEXT: [[DOTPERMUTED_0_IV_K:%.*]] = alloca i32, align 4 3591 // CHECK2-NEXT: [[DOTPERMUTED_1_IV_J:%.*]] = alloca i32, align 4 3592 // CHECK2-NEXT: [[L:%.*]] = alloca i32, align 4 3593 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 3594 // CHECK2-NEXT: store i32 7, ptr [[J]], align 4 3595 // CHECK2-NEXT: store i32 7, ptr [[K]], align 4 3596 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3597 // CHECK2-NEXT: store i32 255, ptr [[DOTOMP_UB]], align 4 3598 // CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3599 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3600 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3601 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3602 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 255 3603 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3604 // CHECK2: cond.true: 3605 // CHECK2-NEXT: br label [[COND_END:%.*]] 3606 // CHECK2: cond.false: 3607 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3608 // CHECK2-NEXT: br label [[COND_END]] 3609 // CHECK2: cond.end: 3610 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 255, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] 3611 // CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3612 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3613 // CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 3614 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3615 // CHECK2: omp.inner.for.cond: 3616 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3617 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3618 // CHECK2-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 3619 // CHECK2-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3620 // CHECK2: omp.inner.for.body: 3621 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3622 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 64 3623 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 3 3624 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]] 3625 // CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4 3626 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3627 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3628 // CHECK2-NEXT: [[DIV5:%.*]] = sdiv i32 [[TMP8]], 64 3629 // CHECK2-NEXT: [[MUL6:%.*]] = mul nsw i32 [[DIV5]], 64 3630 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL6]] 3631 // CHECK2-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB]], 16 3632 // CHECK2-NEXT: [[MUL8:%.*]] = mul nsw i32 [[DIV7]], 1 3633 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]] 3634 // CHECK2-NEXT: store i32 [[ADD9]], ptr [[DOTPERMUTED_0_IV_K]], align 4 3635 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3636 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3637 // CHECK2-NEXT: [[DIV10:%.*]] = sdiv i32 [[TMP10]], 64 3638 // CHECK2-NEXT: [[MUL11:%.*]] = mul nsw i32 [[DIV10]], 64 3639 // CHECK2-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP9]], [[MUL11]] 3640 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3641 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3642 // CHECK2-NEXT: [[DIV13:%.*]] = sdiv i32 [[TMP12]], 64 3643 // CHECK2-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 64 3644 // CHECK2-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP11]], [[MUL14]] 3645 // CHECK2-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 16 3646 // CHECK2-NEXT: [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 16 3647 // CHECK2-NEXT: [[SUB18:%.*]] = sub nsw i32 [[SUB12]], [[MUL17]] 3648 // CHECK2-NEXT: [[DIV19:%.*]] = sdiv i32 [[SUB18]], 4 3649 // CHECK2-NEXT: [[MUL20:%.*]] = mul nsw i32 [[DIV19]], 1 3650 // CHECK2-NEXT: [[ADD21:%.*]] = add nsw i32 0, [[MUL20]] 3651 // CHECK2-NEXT: store i32 [[ADD21]], ptr [[DOTPERMUTED_1_IV_J]], align 4 3652 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3653 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3654 // CHECK2-NEXT: [[DIV22:%.*]] = sdiv i32 [[TMP14]], 64 3655 // CHECK2-NEXT: [[MUL23:%.*]] = mul nsw i32 [[DIV22]], 64 3656 // CHECK2-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP13]], [[MUL23]] 3657 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3658 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3659 // CHECK2-NEXT: [[DIV25:%.*]] = sdiv i32 [[TMP16]], 64 3660 // CHECK2-NEXT: [[MUL26:%.*]] = mul nsw i32 [[DIV25]], 64 3661 // CHECK2-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP15]], [[MUL26]] 3662 // CHECK2-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 16 3663 // CHECK2-NEXT: [[MUL29:%.*]] = mul nsw i32 [[DIV28]], 16 3664 // CHECK2-NEXT: [[SUB30:%.*]] = sub nsw i32 [[SUB24]], [[MUL29]] 3665 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3666 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3667 // CHECK2-NEXT: [[DIV31:%.*]] = sdiv i32 [[TMP18]], 64 3668 // CHECK2-NEXT: [[MUL32:%.*]] = mul nsw i32 [[DIV31]], 64 3669 // CHECK2-NEXT: [[SUB33:%.*]] = sub nsw i32 [[TMP17]], [[MUL32]] 3670 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3671 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3672 // CHECK2-NEXT: [[DIV34:%.*]] = sdiv i32 [[TMP20]], 64 3673 // CHECK2-NEXT: [[MUL35:%.*]] = mul nsw i32 [[DIV34]], 64 3674 // CHECK2-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP19]], [[MUL35]] 3675 // CHECK2-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 16 3676 // CHECK2-NEXT: [[MUL38:%.*]] = mul nsw i32 [[DIV37]], 16 3677 // CHECK2-NEXT: [[SUB39:%.*]] = sub nsw i32 [[SUB33]], [[MUL38]] 3678 // CHECK2-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 4 3679 // CHECK2-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 4 3680 // CHECK2-NEXT: [[SUB42:%.*]] = sub nsw i32 [[SUB30]], [[MUL41]] 3681 // CHECK2-NEXT: [[MUL43:%.*]] = mul nsw i32 [[SUB42]], 3 3682 // CHECK2-NEXT: [[ADD44:%.*]] = add nsw i32 7, [[MUL43]] 3683 // CHECK2-NEXT: store i32 [[ADD44]], ptr [[L]], align 4 3684 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_K]], align 4 3685 // CHECK2-NEXT: [[MUL45:%.*]] = mul nsw i32 [[TMP21]], 3 3686 // CHECK2-NEXT: [[ADD46:%.*]] = add nsw i32 7, [[MUL45]] 3687 // CHECK2-NEXT: store i32 [[ADD46]], ptr [[K]], align 4 3688 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_J]], align 4 3689 // CHECK2-NEXT: [[MUL47:%.*]] = mul nsw i32 [[TMP22]], 3 3690 // CHECK2-NEXT: [[ADD48:%.*]] = add nsw i32 7, [[MUL47]] 3691 // CHECK2-NEXT: store i32 [[ADD48]], ptr [[J]], align 4 3692 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4 3693 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[J]], align 4 3694 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[K]], align 4 3695 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[L]], align 4 3696 // CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP23]], i32 noundef [[TMP24]], i32 noundef [[TMP25]], i32 noundef [[TMP26]]) 3697 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3698 // CHECK2: omp.body.continue: 3699 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3700 // CHECK2: omp.inner.for.inc: 3701 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3702 // CHECK2-NEXT: [[ADD49:%.*]] = add nsw i32 [[TMP27]], 1 3703 // CHECK2-NEXT: store i32 [[ADD49]], ptr [[DOTOMP_IV]], align 4 3704 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 3705 // CHECK2: omp.inner.for.end: 3706 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3707 // CHECK2: omp.loop.exit: 3708 // CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) 3709 // CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) 3710 // CHECK2-NEXT: ret void 3711 // 3712 // 3713 // CHECK2-LABEL: define {{[^@]+}}@foo7 3714 // CHECK2-SAME: () #[[ATTR0]] { 3715 // CHECK2-NEXT: entry: 3716 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 3717 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4 3718 // CHECK2-NEXT: [[K:%.*]] = alloca i32, align 4 3719 // CHECK2-NEXT: [[L:%.*]] = alloca i32, align 4 3720 // CHECK2-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4 3721 // CHECK2-NEXT: [[DOTPERMUTED_1_IV_K:%.*]] = alloca i32, align 4 3722 // CHECK2-NEXT: [[DOTPERMUTED_2_IV_L:%.*]] = alloca i32, align 4 3723 // CHECK2-NEXT: [[DOTPERMUTED_3_IV_I:%.*]] = alloca i32, align 4 3724 // CHECK2-NEXT: store i32 7, ptr [[I]], align 4 3725 // CHECK2-NEXT: store i32 7, ptr [[J]], align 4 3726 // CHECK2-NEXT: store i32 7, ptr [[K]], align 4 3727 // CHECK2-NEXT: store i32 7, ptr [[L]], align 4 3728 // CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_0_IV_J]], align 4 3729 // CHECK2-NEXT: br label [[FOR_COND:%.*]] 3730 // CHECK2: for.cond: 3731 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 3732 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 4 3733 // CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END24:%.*]] 3734 // CHECK2: for.body: 3735 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 3736 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 3 3737 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]] 3738 // CHECK2-NEXT: store i32 [[ADD]], ptr [[J]], align 4 3739 // CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_K]], align 4 3740 // CHECK2-NEXT: br label [[FOR_COND1:%.*]] 3741 // CHECK2: for.cond1: 3742 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 4 3743 // CHECK2-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP2]], 4 3744 // CHECK2-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END21:%.*]] 3745 // CHECK2: for.body3: 3746 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 4 3747 // CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[TMP3]], 3 3748 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 7, [[MUL4]] 3749 // CHECK2-NEXT: store i32 [[ADD5]], ptr [[K]], align 4 3750 // CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_2_IV_L]], align 4 3751 // CHECK2-NEXT: br label [[FOR_COND6:%.*]] 3752 // CHECK2: for.cond6: 3753 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 4 3754 // CHECK2-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP4]], 4 3755 // CHECK2-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END18:%.*]] 3756 // CHECK2: for.body8: 3757 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 4 3758 // CHECK2-NEXT: [[MUL9:%.*]] = mul nsw i32 [[TMP5]], 3 3759 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 7, [[MUL9]] 3760 // CHECK2-NEXT: store i32 [[ADD10]], ptr [[L]], align 4 3761 // CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_3_IV_I]], align 4 3762 // CHECK2-NEXT: br label [[FOR_COND11:%.*]] 3763 // CHECK2: for.cond11: 3764 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 4 3765 // CHECK2-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP6]], 4 3766 // CHECK2-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END:%.*]] 3767 // CHECK2: for.body13: 3768 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 4 3769 // CHECK2-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP7]], 3 3770 // CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 7, [[MUL14]] 3771 // CHECK2-NEXT: store i32 [[ADD15]], ptr [[I]], align 4 3772 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4 3773 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[J]], align 4 3774 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[K]], align 4 3775 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[L]], align 4 3776 // CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP8]], i32 noundef [[TMP9]], i32 noundef [[TMP10]], i32 noundef [[TMP11]]) 3777 // CHECK2-NEXT: br label [[FOR_INC:%.*]] 3778 // CHECK2: for.inc: 3779 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 4 3780 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 3781 // CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_3_IV_I]], align 4 3782 // CHECK2-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP9:![0-9]+]] 3783 // CHECK2: for.end: 3784 // CHECK2-NEXT: br label [[FOR_INC16:%.*]] 3785 // CHECK2: for.inc16: 3786 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 4 3787 // CHECK2-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 3788 // CHECK2-NEXT: store i32 [[INC17]], ptr [[DOTPERMUTED_2_IV_L]], align 4 3789 // CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP10:![0-9]+]] 3790 // CHECK2: for.end18: 3791 // CHECK2-NEXT: br label [[FOR_INC19:%.*]] 3792 // CHECK2: for.inc19: 3793 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 4 3794 // CHECK2-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP14]], 1 3795 // CHECK2-NEXT: store i32 [[INC20]], ptr [[DOTPERMUTED_1_IV_K]], align 4 3796 // CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]] 3797 // CHECK2: for.end21: 3798 // CHECK2-NEXT: br label [[FOR_INC22:%.*]] 3799 // CHECK2: for.inc22: 3800 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 3801 // CHECK2-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1 3802 // CHECK2-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4 3803 // CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 3804 // CHECK2: for.end24: 3805 // CHECK2-NEXT: ret void 3806 // 3807 // 3808 // CHECK2-LABEL: define {{[^@]+}}@foo9 3809 // CHECK2-SAME: () #[[ATTR0]] { 3810 // CHECK2-NEXT: entry: 3811 // CHECK2-NEXT: [[ARR:%.*]] = alloca [128 x double], align 16 3812 // CHECK2-NEXT: [[C:%.*]] = alloca double, align 8 3813 // CHECK2-NEXT: [[__RANGE2:%.*]] = alloca ptr, align 8 3814 // CHECK2-NEXT: [[__END2:%.*]] = alloca ptr, align 8 3815 // CHECK2-NEXT: [[__BEGIN2:%.*]] = alloca ptr, align 8 3816 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 8 3817 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca ptr, align 8 3818 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 3819 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 3820 // CHECK2-NEXT: [[DOTPERMUTED_0_IV_I:%.*]] = alloca i32, align 4 3821 // CHECK2-NEXT: [[DOTPERMUTED_1_IV___BEGIN2:%.*]] = alloca i64, align 8 3822 // CHECK2-NEXT: [[V:%.*]] = alloca ptr, align 8 3823 // CHECK2-NEXT: store double 4.200000e+01, ptr [[C]], align 8 3824 // CHECK2-NEXT: store ptr [[ARR]], ptr [[__RANGE2]], align 8 3825 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8 3826 // CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP0]], i64 0, i64 0 3827 // CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 128 3828 // CHECK2-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 8 3829 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8 3830 // CHECK2-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 0 3831 // CHECK2-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 8 3832 // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8 3833 // CHECK2-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 0 3834 // CHECK2-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 8 3835 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 8 3836 // CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTCAPTURE_EXPR_3]], align 8 3837 // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_3]], align 8 3838 // CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8 3839 // CHECK2-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP4]] to i64 3840 // CHECK2-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i64 3841 // CHECK2-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] 3842 // CHECK2-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 8 3843 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 3844 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 3845 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 3846 // CHECK2-NEXT: [[SUB5:%.*]] = sub nsw i64 [[DIV]], 1 3847 // CHECK2-NEXT: store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 8 3848 // CHECK2-NEXT: store i32 0, ptr [[I]], align 4 3849 // CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_0_IV_I]], align 4 3850 // CHECK2-NEXT: br label [[FOR_COND:%.*]] 3851 // CHECK2: for.cond: 3852 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 4 3853 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 21 3854 // CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END15:%.*]] 3855 // CHECK2: for.body: 3856 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 4 3857 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 2 3858 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL]] 3859 // CHECK2-NEXT: store i32 [[ADD6]], ptr [[I]], align 4 3860 // CHECK2-NEXT: store i64 0, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8 3861 // CHECK2-NEXT: br label [[FOR_COND7:%.*]] 3862 // CHECK2: for.cond7: 3863 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8 3864 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 8 3865 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP9]], 1 3866 // CHECK2-NEXT: [[CMP9:%.*]] = icmp slt i64 [[TMP8]], [[ADD8]] 3867 // CHECK2-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END:%.*]] 3868 // CHECK2: for.body10: 3869 // CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8 3870 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8 3871 // CHECK2-NEXT: [[MUL11:%.*]] = mul nsw i64 [[TMP11]], 1 3872 // CHECK2-NEXT: [[ADD_PTR12:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i64 [[MUL11]] 3873 // CHECK2-NEXT: store ptr [[ADD_PTR12]], ptr [[__BEGIN2]], align 8 3874 // CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[__BEGIN2]], align 8 3875 // CHECK2-NEXT: store ptr [[TMP12]], ptr [[V]], align 8 3876 // CHECK2-NEXT: [[TMP13:%.*]] = load double, ptr [[C]], align 8 3877 // CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[V]], align 8 3878 // CHECK2-NEXT: [[TMP15:%.*]] = load double, ptr [[TMP14]], align 8 3879 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 3880 // CHECK2-NEXT: call void (...) @body(double noundef [[TMP13]], double noundef [[TMP15]], i32 noundef [[TMP16]]) 3881 // CHECK2-NEXT: br label [[FOR_INC:%.*]] 3882 // CHECK2: for.inc: 3883 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8 3884 // CHECK2-NEXT: [[INC:%.*]] = add nsw i64 [[TMP17]], 1 3885 // CHECK2-NEXT: store i64 [[INC]], ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8 3886 // CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP13:![0-9]+]] 3887 // CHECK2: for.end: 3888 // CHECK2-NEXT: br label [[FOR_INC13:%.*]] 3889 // CHECK2: for.inc13: 3890 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 4 3891 // CHECK2-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP18]], 1 3892 // CHECK2-NEXT: store i32 [[INC14]], ptr [[DOTPERMUTED_0_IV_I]], align 4 3893 // CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 3894 // CHECK2: for.end15: 3895 // CHECK2-NEXT: ret void 3896 // 3897 // 3898 // CHECK2-LABEL: define {{[^@]+}}@tfoo8 3899 // CHECK2-SAME: () #[[ATTR0]] { 3900 // CHECK2-NEXT: entry: 3901 // CHECK2-NEXT: call void @_Z4foo8ILi32EEviii(i32 noundef 0, i32 noundef 42, i32 noundef 1) 3902 // CHECK2-NEXT: call void @_Z4foo8ILi64EEviii(i32 noundef 0, i32 noundef 42, i32 noundef 3) 3903 // CHECK2-NEXT: ret void 3904 // 3905 // 3906 // CHECK2-LABEL: define {{[^@]+}}@_Z4foo8ILi32EEviii 3907 // CHECK2-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] comdat { 3908 // CHECK2-NEXT: entry: 3909 // CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4 3910 // CHECK2-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4 3911 // CHECK2-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4 3912 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3913 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 3914 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3915 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 3916 // CHECK2-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 3917 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3918 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 3919 // CHECK2-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 4 3920 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 3921 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4 3922 // CHECK2-NEXT: [[DOTNEW_STEP7:%.*]] = alloca i32, align 4 3923 // CHECK2-NEXT: [[K:%.*]] = alloca i32, align 4 3924 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4 3925 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 3926 // CHECK2-NEXT: [[DOTNEW_STEP10:%.*]] = alloca i32, align 4 3927 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 3928 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 4 3929 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4 3930 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 3931 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 8 3932 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 3933 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4 3934 // CHECK2-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 4 3935 // CHECK2-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4 3936 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3937 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3938 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3939 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3940 // CHECK2-NEXT: [[I49:%.*]] = alloca i32, align 4 3941 // CHECK2-NEXT: [[J50:%.*]] = alloca i32, align 4 3942 // CHECK2-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 4 3943 // CHECK2-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 4 3944 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 3945 // CHECK2-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4 3946 // CHECK2-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4 3947 // CHECK2-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 4 3948 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[START_ADDR]], align 4 3949 // CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 3950 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 4 3951 // CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_4]], align 4 3952 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 3953 // CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 4 3954 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[START_ADDR]], align 4 3955 // CHECK2-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_5]], align 4 3956 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[END_ADDR]], align 4 3957 // CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_6]], align 4 3958 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 3959 // CHECK2-NEXT: store i32 [[TMP6]], ptr [[DOTNEW_STEP7]], align 4 3960 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[START_ADDR]], align 4 3961 // CHECK2-NEXT: store i32 [[TMP7]], ptr [[K]], align 4 3962 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[START_ADDR]], align 4 3963 // CHECK2-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_8]], align 4 3964 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[END_ADDR]], align 4 3965 // CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_9]], align 4 3966 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 3967 // CHECK2-NEXT: store i32 [[TMP10]], ptr [[DOTNEW_STEP10]], align 4 3968 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_9]], align 4 3969 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4 3970 // CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP11]], [[TMP12]] 3971 // CHECK2-NEXT: [[SUB12:%.*]] = sub i32 [[SUB]], 1 3972 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 3973 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB12]], [[TMP13]] 3974 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 3975 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP14]] 3976 // CHECK2-NEXT: [[SUB13:%.*]] = sub i32 [[DIV]], 1 3977 // CHECK2-NEXT: store i32 [[SUB13]], ptr [[DOTCAPTURE_EXPR_11]], align 4 3978 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 3979 // CHECK2-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], 1 3980 // CHECK2-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 4 3981 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 4 3982 // CHECK2-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 4 3983 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 3984 // CHECK2-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 1 3985 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 4 3986 // CHECK2-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 32 3987 // CHECK2-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]] 3988 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3989 // CHECK2: cond.true: 3990 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 3991 // CHECK2-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 1 3992 // CHECK2-NEXT: br label [[COND_END:%.*]] 3993 // CHECK2: cond.false: 3994 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 4 3995 // CHECK2-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 32 3996 // CHECK2-NEXT: br label [[COND_END]] 3997 // CHECK2: cond.end: 3998 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ] 3999 // CHECK2-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 4 4000 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 4001 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 4002 // CHECK2-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]] 4003 // CHECK2-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 1 4004 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 4005 // CHECK2-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]] 4006 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 4007 // CHECK2-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]] 4008 // CHECK2-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i64 4009 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4010 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4011 // CHECK2-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]] 4012 // CHECK2-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 1 4013 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4014 // CHECK2-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]] 4015 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4016 // CHECK2-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]] 4017 // CHECK2-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i64 4018 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]] 4019 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4020 // CHECK2-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -31 4021 // CHECK2-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 32 4022 // CHECK2-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i64 4023 // CHECK2-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]] 4024 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4025 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4026 // CHECK2-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]] 4027 // CHECK2-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 1 4028 // CHECK2-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 1 4029 // CHECK2-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 1 4030 // CHECK2-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i64 4031 // CHECK2-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]] 4032 // CHECK2-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 1 4033 // CHECK2-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 8 4034 // CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 4035 // CHECK2-NEXT: store i32 [[TMP32]], ptr [[I]], align 4 4036 // CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4037 // CHECK2-NEXT: store i32 [[TMP33]], ptr [[J]], align 4 4038 // CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 4 4039 // CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4040 // CHECK2-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 4 4041 // CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 4042 // CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 4043 // CHECK2-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]] 4044 // CHECK2-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 4045 // CHECK2: land.lhs.true: 4046 // CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4047 // CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4048 // CHECK2-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]] 4049 // CHECK2-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]] 4050 // CHECK2: land.lhs.true45: 4051 // CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4052 // CHECK2-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]] 4053 // CHECK2-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]] 4054 // CHECK2: land.lhs.true47: 4055 // CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4056 // CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4057 // CHECK2-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]] 4058 // CHECK2-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 4059 // CHECK2: omp.precond.then: 4060 // CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 4061 // CHECK2-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 4062 // CHECK2-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 8 4063 // CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 4064 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4065 // CHECK2-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 4066 // CHECK2-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 4067 // CHECK2-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 4068 // CHECK2-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]] 4069 // CHECK2-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]] 4070 // CHECK2: cond.true54: 4071 // CHECK2-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 4072 // CHECK2-NEXT: br label [[COND_END56:%.*]] 4073 // CHECK2: cond.false55: 4074 // CHECK2-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 4075 // CHECK2-NEXT: br label [[COND_END56]] 4076 // CHECK2: cond.end56: 4077 // CHECK2-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ] 4078 // CHECK2-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 8 4079 // CHECK2-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 4080 // CHECK2-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 8 4081 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4082 // CHECK2: omp.inner.for.cond: 4083 // CHECK2-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4084 // CHECK2-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 4085 // CHECK2-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]] 4086 // CHECK2-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4087 // CHECK2: omp.inner.for.body: 4088 // CHECK2-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 4089 // CHECK2-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i64 4090 // CHECK2-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4091 // CHECK2-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4092 // CHECK2-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4093 // CHECK2-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]] 4094 // CHECK2-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 1 4095 // CHECK2-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4096 // CHECK2-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]] 4097 // CHECK2-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4098 // CHECK2-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]] 4099 // CHECK2-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]] 4100 // CHECK2-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4101 // CHECK2-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -31 4102 // CHECK2-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 32 4103 // CHECK2-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]] 4104 // CHECK2-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4105 // CHECK2-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4106 // CHECK2-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]] 4107 // CHECK2-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 1 4108 // CHECK2-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 1 4109 // CHECK2-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 1 4110 // CHECK2-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]] 4111 // CHECK2-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i64 4112 // CHECK2-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]] 4113 // CHECK2-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 4114 // CHECK2-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i64 4115 // CHECK2-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]] 4116 // CHECK2-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]] 4117 // CHECK2-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i32 4118 // CHECK2-NEXT: store i32 [[CONV78]], ptr [[I49]], align 4 4119 // CHECK2-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4120 // CHECK2-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i64 4121 // CHECK2-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4122 // CHECK2-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4123 // CHECK2-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4124 // CHECK2-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4125 // CHECK2-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]] 4126 // CHECK2-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 1 4127 // CHECK2-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4128 // CHECK2-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]] 4129 // CHECK2-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4130 // CHECK2-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]] 4131 // CHECK2-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]] 4132 // CHECK2-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4133 // CHECK2-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -31 4134 // CHECK2-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 32 4135 // CHECK2-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]] 4136 // CHECK2-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4137 // CHECK2-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4138 // CHECK2-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]] 4139 // CHECK2-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 1 4140 // CHECK2-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 1 4141 // CHECK2-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 1 4142 // CHECK2-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]] 4143 // CHECK2-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i64 4144 // CHECK2-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]] 4145 // CHECK2-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4146 // CHECK2-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4147 // CHECK2-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]] 4148 // CHECK2-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 1 4149 // CHECK2-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4150 // CHECK2-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]] 4151 // CHECK2-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4152 // CHECK2-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]] 4153 // CHECK2-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]] 4154 // CHECK2-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4155 // CHECK2-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -31 4156 // CHECK2-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 32 4157 // CHECK2-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]] 4158 // CHECK2-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4159 // CHECK2-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4160 // CHECK2-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]] 4161 // CHECK2-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 1 4162 // CHECK2-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 1 4163 // CHECK2-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 1 4164 // CHECK2-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]] 4165 // CHECK2-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i64 4166 // CHECK2-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]] 4167 // CHECK2-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]] 4168 // CHECK2-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4169 // CHECK2-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -31 4170 // CHECK2-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 32 4171 // CHECK2-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]] 4172 // CHECK2-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4173 // CHECK2-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4174 // CHECK2-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]] 4175 // CHECK2-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 1 4176 // CHECK2-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 1 4177 // CHECK2-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 1 4178 // CHECK2-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]] 4179 // CHECK2-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i64 4180 // CHECK2-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]] 4181 // CHECK2-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4182 // CHECK2-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i64 4183 // CHECK2-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]] 4184 // CHECK2-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]] 4185 // CHECK2-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i32 4186 // CHECK2-NEXT: store i32 [[CONV124]], ptr [[J50]], align 4 4187 // CHECK2-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4188 // CHECK2-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4189 // CHECK2-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4190 // CHECK2-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4191 // CHECK2-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]] 4192 // CHECK2-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 1 4193 // CHECK2-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4194 // CHECK2-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]] 4195 // CHECK2-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4196 // CHECK2-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]] 4197 // CHECK2-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]] 4198 // CHECK2-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4199 // CHECK2-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -31 4200 // CHECK2-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 32 4201 // CHECK2-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]] 4202 // CHECK2-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4203 // CHECK2-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4204 // CHECK2-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]] 4205 // CHECK2-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 1 4206 // CHECK2-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 1 4207 // CHECK2-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 1 4208 // CHECK2-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]] 4209 // CHECK2-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i64 4210 // CHECK2-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]] 4211 // CHECK2-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4212 // CHECK2-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4213 // CHECK2-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]] 4214 // CHECK2-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 1 4215 // CHECK2-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4216 // CHECK2-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]] 4217 // CHECK2-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4218 // CHECK2-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]] 4219 // CHECK2-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]] 4220 // CHECK2-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4221 // CHECK2-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -31 4222 // CHECK2-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 32 4223 // CHECK2-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]] 4224 // CHECK2-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4225 // CHECK2-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4226 // CHECK2-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]] 4227 // CHECK2-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 1 4228 // CHECK2-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 1 4229 // CHECK2-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 1 4230 // CHECK2-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]] 4231 // CHECK2-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i64 4232 // CHECK2-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]] 4233 // CHECK2-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]] 4234 // CHECK2-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4235 // CHECK2-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4236 // CHECK2-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4237 // CHECK2-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4238 // CHECK2-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]] 4239 // CHECK2-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 1 4240 // CHECK2-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4241 // CHECK2-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]] 4242 // CHECK2-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4243 // CHECK2-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]] 4244 // CHECK2-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]] 4245 // CHECK2-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4246 // CHECK2-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -31 4247 // CHECK2-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 32 4248 // CHECK2-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]] 4249 // CHECK2-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4250 // CHECK2-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4251 // CHECK2-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]] 4252 // CHECK2-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 1 4253 // CHECK2-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 1 4254 // CHECK2-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 1 4255 // CHECK2-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]] 4256 // CHECK2-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i64 4257 // CHECK2-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]] 4258 // CHECK2-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4259 // CHECK2-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4260 // CHECK2-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]] 4261 // CHECK2-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 1 4262 // CHECK2-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4263 // CHECK2-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]] 4264 // CHECK2-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4265 // CHECK2-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]] 4266 // CHECK2-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]] 4267 // CHECK2-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4268 // CHECK2-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -31 4269 // CHECK2-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 32 4270 // CHECK2-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]] 4271 // CHECK2-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4272 // CHECK2-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4273 // CHECK2-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]] 4274 // CHECK2-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 1 4275 // CHECK2-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 1 4276 // CHECK2-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 1 4277 // CHECK2-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]] 4278 // CHECK2-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i64 4279 // CHECK2-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]] 4280 // CHECK2-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]] 4281 // CHECK2-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4282 // CHECK2-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -31 4283 // CHECK2-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 32 4284 // CHECK2-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]] 4285 // CHECK2-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4286 // CHECK2-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4287 // CHECK2-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]] 4288 // CHECK2-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 1 4289 // CHECK2-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 1 4290 // CHECK2-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 1 4291 // CHECK2-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]] 4292 // CHECK2-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i64 4293 // CHECK2-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]] 4294 // CHECK2-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4295 // CHECK2-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -31 4296 // CHECK2-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 32 4297 // CHECK2-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]] 4298 // CHECK2-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4299 // CHECK2-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4300 // CHECK2-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]] 4301 // CHECK2-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 1 4302 // CHECK2-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 1 4303 // CHECK2-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 1 4304 // CHECK2-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]] 4305 // CHECK2-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i64 4306 // CHECK2-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]] 4307 // CHECK2-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]] 4308 // CHECK2-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4309 // CHECK2-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4310 // CHECK2-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]] 4311 // CHECK2-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 1 4312 // CHECK2-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 1 4313 // CHECK2-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 1 4314 // CHECK2-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]] 4315 // CHECK2-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i64 4316 // CHECK2-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]] 4317 // CHECK2-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 32 4318 // CHECK2-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]] 4319 // CHECK2-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i32 4320 // CHECK2-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 4 4321 // CHECK2-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4322 // CHECK2-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i64 4323 // CHECK2-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4324 // CHECK2-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4325 // CHECK2-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4326 // CHECK2-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4327 // CHECK2-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]] 4328 // CHECK2-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 1 4329 // CHECK2-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4330 // CHECK2-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]] 4331 // CHECK2-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4332 // CHECK2-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]] 4333 // CHECK2-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]] 4334 // CHECK2-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4335 // CHECK2-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -31 4336 // CHECK2-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 32 4337 // CHECK2-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]] 4338 // CHECK2-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4339 // CHECK2-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4340 // CHECK2-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]] 4341 // CHECK2-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 1 4342 // CHECK2-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 1 4343 // CHECK2-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 1 4344 // CHECK2-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]] 4345 // CHECK2-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i64 4346 // CHECK2-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]] 4347 // CHECK2-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4348 // CHECK2-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4349 // CHECK2-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]] 4350 // CHECK2-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 1 4351 // CHECK2-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4352 // CHECK2-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]] 4353 // CHECK2-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4354 // CHECK2-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]] 4355 // CHECK2-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]] 4356 // CHECK2-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4357 // CHECK2-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -31 4358 // CHECK2-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 32 4359 // CHECK2-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]] 4360 // CHECK2-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4361 // CHECK2-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4362 // CHECK2-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]] 4363 // CHECK2-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 1 4364 // CHECK2-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 1 4365 // CHECK2-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 1 4366 // CHECK2-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]] 4367 // CHECK2-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i64 4368 // CHECK2-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]] 4369 // CHECK2-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]] 4370 // CHECK2-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4371 // CHECK2-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4372 // CHECK2-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4373 // CHECK2-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4374 // CHECK2-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]] 4375 // CHECK2-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 1 4376 // CHECK2-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4377 // CHECK2-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]] 4378 // CHECK2-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4379 // CHECK2-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]] 4380 // CHECK2-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]] 4381 // CHECK2-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4382 // CHECK2-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -31 4383 // CHECK2-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 32 4384 // CHECK2-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]] 4385 // CHECK2-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4386 // CHECK2-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4387 // CHECK2-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]] 4388 // CHECK2-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 1 4389 // CHECK2-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 1 4390 // CHECK2-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 1 4391 // CHECK2-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]] 4392 // CHECK2-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i64 4393 // CHECK2-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]] 4394 // CHECK2-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4395 // CHECK2-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4396 // CHECK2-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]] 4397 // CHECK2-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 1 4398 // CHECK2-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4399 // CHECK2-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]] 4400 // CHECK2-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4401 // CHECK2-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]] 4402 // CHECK2-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]] 4403 // CHECK2-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4404 // CHECK2-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -31 4405 // CHECK2-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 32 4406 // CHECK2-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]] 4407 // CHECK2-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4408 // CHECK2-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4409 // CHECK2-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]] 4410 // CHECK2-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 1 4411 // CHECK2-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 1 4412 // CHECK2-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 1 4413 // CHECK2-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]] 4414 // CHECK2-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i64 4415 // CHECK2-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]] 4416 // CHECK2-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]] 4417 // CHECK2-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4418 // CHECK2-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -31 4419 // CHECK2-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 32 4420 // CHECK2-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]] 4421 // CHECK2-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4422 // CHECK2-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4423 // CHECK2-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]] 4424 // CHECK2-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 1 4425 // CHECK2-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 1 4426 // CHECK2-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 1 4427 // CHECK2-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]] 4428 // CHECK2-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i64 4429 // CHECK2-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]] 4430 // CHECK2-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4431 // CHECK2-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -31 4432 // CHECK2-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 32 4433 // CHECK2-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]] 4434 // CHECK2-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4435 // CHECK2-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4436 // CHECK2-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]] 4437 // CHECK2-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 1 4438 // CHECK2-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 1 4439 // CHECK2-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 1 4440 // CHECK2-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]] 4441 // CHECK2-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i64 4442 // CHECK2-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]] 4443 // CHECK2-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]] 4444 // CHECK2-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4445 // CHECK2-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4446 // CHECK2-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4447 // CHECK2-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4448 // CHECK2-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]] 4449 // CHECK2-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 1 4450 // CHECK2-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4451 // CHECK2-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]] 4452 // CHECK2-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4453 // CHECK2-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]] 4454 // CHECK2-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]] 4455 // CHECK2-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4456 // CHECK2-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -31 4457 // CHECK2-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 32 4458 // CHECK2-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]] 4459 // CHECK2-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4460 // CHECK2-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4461 // CHECK2-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]] 4462 // CHECK2-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 1 4463 // CHECK2-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 1 4464 // CHECK2-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 1 4465 // CHECK2-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]] 4466 // CHECK2-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i64 4467 // CHECK2-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]] 4468 // CHECK2-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4469 // CHECK2-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4470 // CHECK2-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]] 4471 // CHECK2-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 1 4472 // CHECK2-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4473 // CHECK2-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]] 4474 // CHECK2-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4475 // CHECK2-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]] 4476 // CHECK2-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]] 4477 // CHECK2-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4478 // CHECK2-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -31 4479 // CHECK2-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 32 4480 // CHECK2-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]] 4481 // CHECK2-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4482 // CHECK2-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4483 // CHECK2-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]] 4484 // CHECK2-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 1 4485 // CHECK2-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 1 4486 // CHECK2-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 1 4487 // CHECK2-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]] 4488 // CHECK2-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i64 4489 // CHECK2-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]] 4490 // CHECK2-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]] 4491 // CHECK2-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4492 // CHECK2-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4493 // CHECK2-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4494 // CHECK2-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4495 // CHECK2-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]] 4496 // CHECK2-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 1 4497 // CHECK2-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4498 // CHECK2-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]] 4499 // CHECK2-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4500 // CHECK2-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]] 4501 // CHECK2-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]] 4502 // CHECK2-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4503 // CHECK2-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -31 4504 // CHECK2-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 32 4505 // CHECK2-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]] 4506 // CHECK2-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4507 // CHECK2-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4508 // CHECK2-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]] 4509 // CHECK2-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 1 4510 // CHECK2-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 1 4511 // CHECK2-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 1 4512 // CHECK2-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]] 4513 // CHECK2-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i64 4514 // CHECK2-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]] 4515 // CHECK2-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4516 // CHECK2-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4517 // CHECK2-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]] 4518 // CHECK2-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 1 4519 // CHECK2-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4520 // CHECK2-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]] 4521 // CHECK2-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4522 // CHECK2-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]] 4523 // CHECK2-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]] 4524 // CHECK2-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4525 // CHECK2-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -31 4526 // CHECK2-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 32 4527 // CHECK2-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]] 4528 // CHECK2-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4529 // CHECK2-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4530 // CHECK2-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]] 4531 // CHECK2-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 1 4532 // CHECK2-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 1 4533 // CHECK2-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 1 4534 // CHECK2-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]] 4535 // CHECK2-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i64 4536 // CHECK2-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]] 4537 // CHECK2-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]] 4538 // CHECK2-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4539 // CHECK2-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -31 4540 // CHECK2-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 32 4541 // CHECK2-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]] 4542 // CHECK2-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4543 // CHECK2-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4544 // CHECK2-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]] 4545 // CHECK2-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 1 4546 // CHECK2-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 1 4547 // CHECK2-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 1 4548 // CHECK2-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]] 4549 // CHECK2-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i64 4550 // CHECK2-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]] 4551 // CHECK2-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4552 // CHECK2-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -31 4553 // CHECK2-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 32 4554 // CHECK2-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]] 4555 // CHECK2-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4556 // CHECK2-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4557 // CHECK2-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]] 4558 // CHECK2-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 1 4559 // CHECK2-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 1 4560 // CHECK2-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 1 4561 // CHECK2-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]] 4562 // CHECK2-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i64 4563 // CHECK2-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]] 4564 // CHECK2-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]] 4565 // CHECK2-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4566 // CHECK2-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4567 // CHECK2-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]] 4568 // CHECK2-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 1 4569 // CHECK2-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 1 4570 // CHECK2-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 1 4571 // CHECK2-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]] 4572 // CHECK2-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i64 4573 // CHECK2-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]] 4574 // CHECK2-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4575 // CHECK2-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4576 // CHECK2-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]] 4577 // CHECK2-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 1 4578 // CHECK2-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 1 4579 // CHECK2-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 1 4580 // CHECK2-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]] 4581 // CHECK2-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i64 4582 // CHECK2-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]] 4583 // CHECK2-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]] 4584 // CHECK2-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 1 4585 // CHECK2-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]] 4586 // CHECK2-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i32 4587 // CHECK2-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 4 4588 // CHECK2-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4 4589 // CHECK2-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 4 4590 // CHECK2-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 4591 // CHECK2-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]] 4592 // CHECK2-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]] 4593 // CHECK2-NEXT: store i32 [[ADD404]], ptr [[K]], align 4 4594 // CHECK2-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 4 4595 // CHECK2-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 4 4596 // CHECK2-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 4 4597 // CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]]) 4598 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4599 // CHECK2: omp.body.continue: 4600 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4601 // CHECK2: omp.inner.for.inc: 4602 // CHECK2-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4603 // CHECK2-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 1 4604 // CHECK2-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 8 4605 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 4606 // CHECK2: omp.inner.for.end: 4607 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4608 // CHECK2: omp.loop.exit: 4609 // CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) 4610 // CHECK2-NEXT: br label [[OMP_PRECOND_END]] 4611 // CHECK2: omp.precond.end: 4612 // CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) 4613 // CHECK2-NEXT: ret void 4614 // 4615 // 4616 // CHECK2-LABEL: define {{[^@]+}}@_Z4foo8ILi64EEviii 4617 // CHECK2-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] comdat { 4618 // CHECK2-NEXT: entry: 4619 // CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4 4620 // CHECK2-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4 4621 // CHECK2-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4 4622 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4623 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 4624 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 4625 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 4626 // CHECK2-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 4627 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 4628 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 4629 // CHECK2-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 4 4630 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 4631 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4 4632 // CHECK2-NEXT: [[DOTNEW_STEP7:%.*]] = alloca i32, align 4 4633 // CHECK2-NEXT: [[K:%.*]] = alloca i32, align 4 4634 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4 4635 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 4636 // CHECK2-NEXT: [[DOTNEW_STEP10:%.*]] = alloca i32, align 4 4637 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 4638 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 4 4639 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4 4640 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 4641 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 8 4642 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 4643 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4 4644 // CHECK2-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 4 4645 // CHECK2-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4 4646 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4647 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4648 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4649 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4650 // CHECK2-NEXT: [[I49:%.*]] = alloca i32, align 4 4651 // CHECK2-NEXT: [[J50:%.*]] = alloca i32, align 4 4652 // CHECK2-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 4 4653 // CHECK2-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 4 4654 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 4655 // CHECK2-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4 4656 // CHECK2-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4 4657 // CHECK2-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 4 4658 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[START_ADDR]], align 4 4659 // CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 4660 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 4 4661 // CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_4]], align 4 4662 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 4663 // CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 4 4664 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[START_ADDR]], align 4 4665 // CHECK2-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_5]], align 4 4666 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[END_ADDR]], align 4 4667 // CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_6]], align 4 4668 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 4669 // CHECK2-NEXT: store i32 [[TMP6]], ptr [[DOTNEW_STEP7]], align 4 4670 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[START_ADDR]], align 4 4671 // CHECK2-NEXT: store i32 [[TMP7]], ptr [[K]], align 4 4672 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[START_ADDR]], align 4 4673 // CHECK2-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_8]], align 4 4674 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[END_ADDR]], align 4 4675 // CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_9]], align 4 4676 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 4677 // CHECK2-NEXT: store i32 [[TMP10]], ptr [[DOTNEW_STEP10]], align 4 4678 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_9]], align 4 4679 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4 4680 // CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP11]], [[TMP12]] 4681 // CHECK2-NEXT: [[SUB12:%.*]] = sub i32 [[SUB]], 1 4682 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 4683 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB12]], [[TMP13]] 4684 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 4685 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP14]] 4686 // CHECK2-NEXT: [[SUB13:%.*]] = sub i32 [[DIV]], 1 4687 // CHECK2-NEXT: store i32 [[SUB13]], ptr [[DOTCAPTURE_EXPR_11]], align 4 4688 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 4689 // CHECK2-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], 1 4690 // CHECK2-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 4 4691 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 4 4692 // CHECK2-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 4 4693 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 4694 // CHECK2-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 1 4695 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 4 4696 // CHECK2-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 64 4697 // CHECK2-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]] 4698 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4699 // CHECK2: cond.true: 4700 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 4701 // CHECK2-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 1 4702 // CHECK2-NEXT: br label [[COND_END:%.*]] 4703 // CHECK2: cond.false: 4704 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 4 4705 // CHECK2-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 64 4706 // CHECK2-NEXT: br label [[COND_END]] 4707 // CHECK2: cond.end: 4708 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ] 4709 // CHECK2-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 4 4710 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 4711 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 4712 // CHECK2-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]] 4713 // CHECK2-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 1 4714 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 4715 // CHECK2-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]] 4716 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 4717 // CHECK2-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]] 4718 // CHECK2-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i64 4719 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4720 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4721 // CHECK2-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]] 4722 // CHECK2-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 1 4723 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4724 // CHECK2-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]] 4725 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4726 // CHECK2-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]] 4727 // CHECK2-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i64 4728 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]] 4729 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4730 // CHECK2-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -63 4731 // CHECK2-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 64 4732 // CHECK2-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i64 4733 // CHECK2-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]] 4734 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4735 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4736 // CHECK2-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]] 4737 // CHECK2-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 1 4738 // CHECK2-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 1 4739 // CHECK2-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 1 4740 // CHECK2-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i64 4741 // CHECK2-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]] 4742 // CHECK2-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 1 4743 // CHECK2-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 8 4744 // CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 4745 // CHECK2-NEXT: store i32 [[TMP32]], ptr [[I]], align 4 4746 // CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4747 // CHECK2-NEXT: store i32 [[TMP33]], ptr [[J]], align 4 4748 // CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 4 4749 // CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4750 // CHECK2-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 4 4751 // CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 4752 // CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 4753 // CHECK2-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]] 4754 // CHECK2-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 4755 // CHECK2: land.lhs.true: 4756 // CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4757 // CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4758 // CHECK2-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]] 4759 // CHECK2-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]] 4760 // CHECK2: land.lhs.true45: 4761 // CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4762 // CHECK2-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]] 4763 // CHECK2-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]] 4764 // CHECK2: land.lhs.true47: 4765 // CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4766 // CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4767 // CHECK2-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]] 4768 // CHECK2-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 4769 // CHECK2: omp.precond.then: 4770 // CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 4771 // CHECK2-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 4772 // CHECK2-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 8 4773 // CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 4774 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4775 // CHECK2-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) 4776 // CHECK2-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 4777 // CHECK2-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 4778 // CHECK2-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]] 4779 // CHECK2-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]] 4780 // CHECK2: cond.true54: 4781 // CHECK2-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 4782 // CHECK2-NEXT: br label [[COND_END56:%.*]] 4783 // CHECK2: cond.false55: 4784 // CHECK2-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 4785 // CHECK2-NEXT: br label [[COND_END56]] 4786 // CHECK2: cond.end56: 4787 // CHECK2-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ] 4788 // CHECK2-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 8 4789 // CHECK2-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 4790 // CHECK2-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 8 4791 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4792 // CHECK2: omp.inner.for.cond: 4793 // CHECK2-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4794 // CHECK2-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 4795 // CHECK2-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]] 4796 // CHECK2-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4797 // CHECK2: omp.inner.for.body: 4798 // CHECK2-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 4799 // CHECK2-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i64 4800 // CHECK2-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4801 // CHECK2-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4802 // CHECK2-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4803 // CHECK2-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]] 4804 // CHECK2-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 1 4805 // CHECK2-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4806 // CHECK2-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]] 4807 // CHECK2-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4808 // CHECK2-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]] 4809 // CHECK2-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]] 4810 // CHECK2-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4811 // CHECK2-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -63 4812 // CHECK2-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 64 4813 // CHECK2-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]] 4814 // CHECK2-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4815 // CHECK2-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4816 // CHECK2-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]] 4817 // CHECK2-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 1 4818 // CHECK2-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 1 4819 // CHECK2-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 1 4820 // CHECK2-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]] 4821 // CHECK2-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i64 4822 // CHECK2-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]] 4823 // CHECK2-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 4824 // CHECK2-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i64 4825 // CHECK2-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]] 4826 // CHECK2-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]] 4827 // CHECK2-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i32 4828 // CHECK2-NEXT: store i32 [[CONV78]], ptr [[I49]], align 4 4829 // CHECK2-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4830 // CHECK2-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i64 4831 // CHECK2-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4832 // CHECK2-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4833 // CHECK2-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4834 // CHECK2-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4835 // CHECK2-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]] 4836 // CHECK2-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 1 4837 // CHECK2-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4838 // CHECK2-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]] 4839 // CHECK2-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4840 // CHECK2-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]] 4841 // CHECK2-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]] 4842 // CHECK2-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4843 // CHECK2-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -63 4844 // CHECK2-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 64 4845 // CHECK2-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]] 4846 // CHECK2-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4847 // CHECK2-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4848 // CHECK2-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]] 4849 // CHECK2-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 1 4850 // CHECK2-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 1 4851 // CHECK2-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 1 4852 // CHECK2-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]] 4853 // CHECK2-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i64 4854 // CHECK2-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]] 4855 // CHECK2-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4856 // CHECK2-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4857 // CHECK2-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]] 4858 // CHECK2-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 1 4859 // CHECK2-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4860 // CHECK2-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]] 4861 // CHECK2-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4862 // CHECK2-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]] 4863 // CHECK2-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]] 4864 // CHECK2-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4865 // CHECK2-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -63 4866 // CHECK2-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 64 4867 // CHECK2-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]] 4868 // CHECK2-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4869 // CHECK2-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4870 // CHECK2-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]] 4871 // CHECK2-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 1 4872 // CHECK2-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 1 4873 // CHECK2-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 1 4874 // CHECK2-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]] 4875 // CHECK2-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i64 4876 // CHECK2-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]] 4877 // CHECK2-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]] 4878 // CHECK2-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4879 // CHECK2-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -63 4880 // CHECK2-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 64 4881 // CHECK2-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]] 4882 // CHECK2-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4883 // CHECK2-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4884 // CHECK2-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]] 4885 // CHECK2-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 1 4886 // CHECK2-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 1 4887 // CHECK2-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 1 4888 // CHECK2-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]] 4889 // CHECK2-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i64 4890 // CHECK2-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]] 4891 // CHECK2-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4892 // CHECK2-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i64 4893 // CHECK2-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]] 4894 // CHECK2-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]] 4895 // CHECK2-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i32 4896 // CHECK2-NEXT: store i32 [[CONV124]], ptr [[J50]], align 4 4897 // CHECK2-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4898 // CHECK2-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4899 // CHECK2-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4900 // CHECK2-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4901 // CHECK2-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]] 4902 // CHECK2-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 1 4903 // CHECK2-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4904 // CHECK2-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]] 4905 // CHECK2-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4906 // CHECK2-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]] 4907 // CHECK2-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]] 4908 // CHECK2-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4909 // CHECK2-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -63 4910 // CHECK2-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 64 4911 // CHECK2-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]] 4912 // CHECK2-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4913 // CHECK2-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4914 // CHECK2-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]] 4915 // CHECK2-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 1 4916 // CHECK2-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 1 4917 // CHECK2-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 1 4918 // CHECK2-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]] 4919 // CHECK2-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i64 4920 // CHECK2-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]] 4921 // CHECK2-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4922 // CHECK2-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4923 // CHECK2-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]] 4924 // CHECK2-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 1 4925 // CHECK2-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4926 // CHECK2-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]] 4927 // CHECK2-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4928 // CHECK2-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]] 4929 // CHECK2-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]] 4930 // CHECK2-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4931 // CHECK2-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -63 4932 // CHECK2-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 64 4933 // CHECK2-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]] 4934 // CHECK2-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4935 // CHECK2-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4936 // CHECK2-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]] 4937 // CHECK2-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 1 4938 // CHECK2-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 1 4939 // CHECK2-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 1 4940 // CHECK2-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]] 4941 // CHECK2-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i64 4942 // CHECK2-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]] 4943 // CHECK2-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]] 4944 // CHECK2-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4945 // CHECK2-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 4946 // CHECK2-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4947 // CHECK2-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4948 // CHECK2-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]] 4949 // CHECK2-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 1 4950 // CHECK2-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4951 // CHECK2-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]] 4952 // CHECK2-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4953 // CHECK2-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]] 4954 // CHECK2-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]] 4955 // CHECK2-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4956 // CHECK2-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -63 4957 // CHECK2-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 64 4958 // CHECK2-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]] 4959 // CHECK2-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4960 // CHECK2-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4961 // CHECK2-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]] 4962 // CHECK2-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 1 4963 // CHECK2-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 1 4964 // CHECK2-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 1 4965 // CHECK2-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]] 4966 // CHECK2-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i64 4967 // CHECK2-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]] 4968 // CHECK2-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 4969 // CHECK2-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 4970 // CHECK2-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]] 4971 // CHECK2-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 1 4972 // CHECK2-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4973 // CHECK2-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]] 4974 // CHECK2-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 4975 // CHECK2-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]] 4976 // CHECK2-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]] 4977 // CHECK2-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4978 // CHECK2-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -63 4979 // CHECK2-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 64 4980 // CHECK2-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]] 4981 // CHECK2-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4982 // CHECK2-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4983 // CHECK2-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]] 4984 // CHECK2-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 1 4985 // CHECK2-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 1 4986 // CHECK2-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 1 4987 // CHECK2-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]] 4988 // CHECK2-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i64 4989 // CHECK2-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]] 4990 // CHECK2-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]] 4991 // CHECK2-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 4992 // CHECK2-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -63 4993 // CHECK2-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 64 4994 // CHECK2-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]] 4995 // CHECK2-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 4996 // CHECK2-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 4997 // CHECK2-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]] 4998 // CHECK2-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 1 4999 // CHECK2-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 1 5000 // CHECK2-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 1 5001 // CHECK2-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]] 5002 // CHECK2-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i64 5003 // CHECK2-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]] 5004 // CHECK2-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 5005 // CHECK2-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -63 5006 // CHECK2-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 64 5007 // CHECK2-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]] 5008 // CHECK2-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 5009 // CHECK2-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 5010 // CHECK2-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]] 5011 // CHECK2-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 1 5012 // CHECK2-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 1 5013 // CHECK2-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 1 5014 // CHECK2-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]] 5015 // CHECK2-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i64 5016 // CHECK2-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]] 5017 // CHECK2-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]] 5018 // CHECK2-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 5019 // CHECK2-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 5020 // CHECK2-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]] 5021 // CHECK2-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 1 5022 // CHECK2-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 1 5023 // CHECK2-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 1 5024 // CHECK2-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]] 5025 // CHECK2-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i64 5026 // CHECK2-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]] 5027 // CHECK2-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 64 5028 // CHECK2-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]] 5029 // CHECK2-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i32 5030 // CHECK2-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 4 5031 // CHECK2-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 5032 // CHECK2-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i64 5033 // CHECK2-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 5034 // CHECK2-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 5035 // CHECK2-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 5036 // CHECK2-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 5037 // CHECK2-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]] 5038 // CHECK2-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 1 5039 // CHECK2-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 5040 // CHECK2-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]] 5041 // CHECK2-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 5042 // CHECK2-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]] 5043 // CHECK2-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]] 5044 // CHECK2-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 5045 // CHECK2-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -63 5046 // CHECK2-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 64 5047 // CHECK2-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]] 5048 // CHECK2-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 5049 // CHECK2-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 5050 // CHECK2-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]] 5051 // CHECK2-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 1 5052 // CHECK2-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 1 5053 // CHECK2-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 1 5054 // CHECK2-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]] 5055 // CHECK2-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i64 5056 // CHECK2-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]] 5057 // CHECK2-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 5058 // CHECK2-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 5059 // CHECK2-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]] 5060 // CHECK2-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 1 5061 // CHECK2-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 5062 // CHECK2-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]] 5063 // CHECK2-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 5064 // CHECK2-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]] 5065 // CHECK2-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]] 5066 // CHECK2-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 5067 // CHECK2-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -63 5068 // CHECK2-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 64 5069 // CHECK2-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]] 5070 // CHECK2-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 5071 // CHECK2-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 5072 // CHECK2-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]] 5073 // CHECK2-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 1 5074 // CHECK2-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 1 5075 // CHECK2-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 1 5076 // CHECK2-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]] 5077 // CHECK2-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i64 5078 // CHECK2-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]] 5079 // CHECK2-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]] 5080 // CHECK2-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 5081 // CHECK2-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 5082 // CHECK2-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 5083 // CHECK2-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 5084 // CHECK2-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]] 5085 // CHECK2-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 1 5086 // CHECK2-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 5087 // CHECK2-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]] 5088 // CHECK2-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 5089 // CHECK2-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]] 5090 // CHECK2-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]] 5091 // CHECK2-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 5092 // CHECK2-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -63 5093 // CHECK2-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 64 5094 // CHECK2-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]] 5095 // CHECK2-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 5096 // CHECK2-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 5097 // CHECK2-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]] 5098 // CHECK2-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 1 5099 // CHECK2-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 1 5100 // CHECK2-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 1 5101 // CHECK2-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]] 5102 // CHECK2-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i64 5103 // CHECK2-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]] 5104 // CHECK2-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 5105 // CHECK2-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 5106 // CHECK2-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]] 5107 // CHECK2-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 1 5108 // CHECK2-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 5109 // CHECK2-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]] 5110 // CHECK2-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 5111 // CHECK2-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]] 5112 // CHECK2-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]] 5113 // CHECK2-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 5114 // CHECK2-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -63 5115 // CHECK2-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 64 5116 // CHECK2-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]] 5117 // CHECK2-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 5118 // CHECK2-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 5119 // CHECK2-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]] 5120 // CHECK2-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 1 5121 // CHECK2-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 1 5122 // CHECK2-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 1 5123 // CHECK2-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]] 5124 // CHECK2-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i64 5125 // CHECK2-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]] 5126 // CHECK2-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]] 5127 // CHECK2-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 5128 // CHECK2-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -63 5129 // CHECK2-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 64 5130 // CHECK2-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]] 5131 // CHECK2-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 5132 // CHECK2-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 5133 // CHECK2-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]] 5134 // CHECK2-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 1 5135 // CHECK2-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 1 5136 // CHECK2-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 1 5137 // CHECK2-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]] 5138 // CHECK2-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i64 5139 // CHECK2-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]] 5140 // CHECK2-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 5141 // CHECK2-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -63 5142 // CHECK2-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 64 5143 // CHECK2-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]] 5144 // CHECK2-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 5145 // CHECK2-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 5146 // CHECK2-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]] 5147 // CHECK2-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 1 5148 // CHECK2-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 1 5149 // CHECK2-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 1 5150 // CHECK2-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]] 5151 // CHECK2-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i64 5152 // CHECK2-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]] 5153 // CHECK2-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]] 5154 // CHECK2-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 5155 // CHECK2-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 5156 // CHECK2-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 5157 // CHECK2-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 5158 // CHECK2-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]] 5159 // CHECK2-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 1 5160 // CHECK2-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 5161 // CHECK2-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]] 5162 // CHECK2-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 5163 // CHECK2-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]] 5164 // CHECK2-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]] 5165 // CHECK2-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 5166 // CHECK2-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -63 5167 // CHECK2-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 64 5168 // CHECK2-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]] 5169 // CHECK2-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 5170 // CHECK2-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 5171 // CHECK2-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]] 5172 // CHECK2-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 1 5173 // CHECK2-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 1 5174 // CHECK2-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 1 5175 // CHECK2-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]] 5176 // CHECK2-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i64 5177 // CHECK2-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]] 5178 // CHECK2-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 5179 // CHECK2-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 5180 // CHECK2-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]] 5181 // CHECK2-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 1 5182 // CHECK2-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 5183 // CHECK2-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]] 5184 // CHECK2-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 5185 // CHECK2-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]] 5186 // CHECK2-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]] 5187 // CHECK2-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 5188 // CHECK2-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -63 5189 // CHECK2-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 64 5190 // CHECK2-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]] 5191 // CHECK2-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 5192 // CHECK2-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 5193 // CHECK2-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]] 5194 // CHECK2-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 1 5195 // CHECK2-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 1 5196 // CHECK2-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 1 5197 // CHECK2-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]] 5198 // CHECK2-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i64 5199 // CHECK2-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]] 5200 // CHECK2-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]] 5201 // CHECK2-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 5202 // CHECK2-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 5203 // CHECK2-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 5204 // CHECK2-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 5205 // CHECK2-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]] 5206 // CHECK2-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 1 5207 // CHECK2-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 5208 // CHECK2-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]] 5209 // CHECK2-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 5210 // CHECK2-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]] 5211 // CHECK2-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]] 5212 // CHECK2-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 5213 // CHECK2-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -63 5214 // CHECK2-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 64 5215 // CHECK2-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]] 5216 // CHECK2-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 5217 // CHECK2-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 5218 // CHECK2-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]] 5219 // CHECK2-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 1 5220 // CHECK2-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 1 5221 // CHECK2-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 1 5222 // CHECK2-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]] 5223 // CHECK2-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i64 5224 // CHECK2-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]] 5225 // CHECK2-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 5226 // CHECK2-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 5227 // CHECK2-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]] 5228 // CHECK2-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 1 5229 // CHECK2-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 5230 // CHECK2-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]] 5231 // CHECK2-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 5232 // CHECK2-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]] 5233 // CHECK2-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]] 5234 // CHECK2-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 5235 // CHECK2-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -63 5236 // CHECK2-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 64 5237 // CHECK2-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]] 5238 // CHECK2-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 5239 // CHECK2-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 5240 // CHECK2-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]] 5241 // CHECK2-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 1 5242 // CHECK2-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 1 5243 // CHECK2-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 1 5244 // CHECK2-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]] 5245 // CHECK2-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i64 5246 // CHECK2-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]] 5247 // CHECK2-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]] 5248 // CHECK2-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 5249 // CHECK2-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -63 5250 // CHECK2-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 64 5251 // CHECK2-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]] 5252 // CHECK2-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 5253 // CHECK2-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 5254 // CHECK2-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]] 5255 // CHECK2-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 1 5256 // CHECK2-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 1 5257 // CHECK2-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 1 5258 // CHECK2-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]] 5259 // CHECK2-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i64 5260 // CHECK2-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]] 5261 // CHECK2-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 5262 // CHECK2-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -63 5263 // CHECK2-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 64 5264 // CHECK2-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]] 5265 // CHECK2-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 5266 // CHECK2-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 5267 // CHECK2-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]] 5268 // CHECK2-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 1 5269 // CHECK2-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 1 5270 // CHECK2-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 1 5271 // CHECK2-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]] 5272 // CHECK2-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i64 5273 // CHECK2-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]] 5274 // CHECK2-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]] 5275 // CHECK2-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 5276 // CHECK2-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 5277 // CHECK2-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]] 5278 // CHECK2-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 1 5279 // CHECK2-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 1 5280 // CHECK2-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 1 5281 // CHECK2-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]] 5282 // CHECK2-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i64 5283 // CHECK2-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]] 5284 // CHECK2-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 5285 // CHECK2-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 5286 // CHECK2-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]] 5287 // CHECK2-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 1 5288 // CHECK2-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 1 5289 // CHECK2-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 1 5290 // CHECK2-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]] 5291 // CHECK2-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i64 5292 // CHECK2-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]] 5293 // CHECK2-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]] 5294 // CHECK2-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 1 5295 // CHECK2-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]] 5296 // CHECK2-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i32 5297 // CHECK2-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 4 5298 // CHECK2-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4 5299 // CHECK2-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 4 5300 // CHECK2-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 5301 // CHECK2-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]] 5302 // CHECK2-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]] 5303 // CHECK2-NEXT: store i32 [[ADD404]], ptr [[K]], align 4 5304 // CHECK2-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 4 5305 // CHECK2-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 4 5306 // CHECK2-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 4 5307 // CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]]) 5308 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5309 // CHECK2: omp.body.continue: 5310 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5311 // CHECK2: omp.inner.for.inc: 5312 // CHECK2-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 5313 // CHECK2-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 1 5314 // CHECK2-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 8 5315 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 5316 // CHECK2: omp.inner.for.end: 5317 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5318 // CHECK2: omp.loop.exit: 5319 // CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) 5320 // CHECK2-NEXT: br label [[OMP_PRECOND_END]] 5321 // CHECK2: omp.precond.end: 5322 // CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) 5323 // CHECK2-NEXT: ret void 5324 5325