1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 9 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -DOMP5 | FileCheck %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -DOMP5 11 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -DOMP5| FileCheck %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -DOMP5 14 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 19 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 20 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 21 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 22 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -DOMP5 | FileCheck %s --check-prefix=CHECK13 23 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -DOMP5 24 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK13 25 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -DOMP5 | FileCheck %s --check-prefix=CHECK15 26 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -DOMP5 27 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK15 28 29 // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region) 30 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 31 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17 32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 33 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 34 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 35 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK19 36 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 37 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 38 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -DOMP5 39 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK21 40 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -DOMP5 41 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK21 42 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -DOMP5 43 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK23 44 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -DOMP5 45 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK23 46 47 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 48 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 49 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 50 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 51 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 52 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 53 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 54 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 55 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -DOMP5 56 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK13 57 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -DOMP5 58 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK13 59 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -DOMP5 60 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK15 61 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -DOMP5 62 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK15 63 64 // expected-no-diagnostics 65 #ifndef HEADER 66 #define HEADER 67 68 69 void without_schedule_clause(float *a, float *b, float *c, float *d) { 70 #pragma omp target 71 #pragma omp teams 72 #ifdef OMP5 73 #pragma omp distribute simd simdlen(8) aligned(a) if(true) 74 #else 75 #pragma omp distribute simd simdlen(8) aligned(a) 76 #endif // OMP5 77 for (int i = 33; i < 32000000; i += 7) { 78 a[i] = b[i] * c[i] * d[i]; 79 } 80 } 81 82 // ... loop body ... 83 84 85 void static_not_chunked(float *a, float *b, float *c, float *d) { 86 #pragma omp target 87 #pragma omp teams 88 #ifdef OMP5 89 #pragma omp distribute simd dist_schedule(static) safelen(32) if(simd: true) nontemporal(a, b) 90 #else 91 #pragma omp distribute simd dist_schedule(static) safelen(32) 92 #endif // OMP5 93 for (int i = 32000000; i > 33; i += -7) { 94 a[i] = b[i] * c[i] * d[i]; 95 } 96 } 97 98 // ... loop body ... 99 100 101 102 void static_chunked(float *a, float *b, float *c, float *d) { 103 #pragma omp target 104 #pragma omp teams 105 #pragma omp distribute simd dist_schedule(static, 5) 106 for (unsigned i = 131071; i <= 2147483647; i += 127) { 107 a[i] = b[i] * c[i] * d[i]; 108 } 109 } 110 111 // ... loop body ... 112 113 void test_precond() { 114 char a = 0; char i; 115 #pragma omp target 116 #pragma omp teams 117 #ifdef OMP5 118 #pragma omp distribute simd linear(i) if(a) nontemporal(i) 119 #else 120 #pragma omp distribute simd linear(i) 121 #endif // OMP5 122 for(i = a; i < 10; ++i); 123 } 124 125 // a is passed as a parameter to the outlined functions 126 // ..many loads of %0.. 127 128 // no templates for now, as these require special handling in target regions and/or declare target 129 130 131 template <typename T> 132 T ftemplate() { 133 short aa = 0; 134 135 #pragma omp target 136 #pragma omp teams 137 #pragma omp distribute simd dist_schedule(static, aa) 138 for (int i = 0; i < 100; i++) { 139 } 140 return T(); 141 } 142 143 int fint(void) { return ftemplate<int>(); } 144 145 #endif 146 147 // CHECK1-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 148 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 149 // CHECK1-NEXT: entry: 150 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 151 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 152 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 153 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 154 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 155 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 156 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 157 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 158 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 159 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 160 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 161 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 162 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 163 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 164 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 165 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 166 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 167 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 168 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 8 169 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 170 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 171 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 172 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 173 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 174 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8 175 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 176 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 8 177 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 178 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 179 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 180 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 8 181 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 182 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP11]], align 8 183 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 184 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 185 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 186 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 8 187 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 188 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 8 189 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 190 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 191 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 192 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 193 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 194 // CHECK1-NEXT: store i32 3, ptr [[TMP18]], align 4 195 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 196 // CHECK1-NEXT: store i32 4, ptr [[TMP19]], align 4 197 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 198 // CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 8 199 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 200 // CHECK1-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 8 201 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 202 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP22]], align 8 203 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 204 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP23]], align 8 205 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 206 // CHECK1-NEXT: store ptr null, ptr [[TMP24]], align 8 207 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 208 // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 209 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 210 // CHECK1-NEXT: store i64 4571424, ptr [[TMP26]], align 8 211 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 212 // CHECK1-NEXT: store i64 0, ptr [[TMP27]], align 8 213 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 214 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 215 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 216 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4 217 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 218 // CHECK1-NEXT: store i32 0, ptr [[TMP30]], align 4 219 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, ptr [[KERNEL_ARGS]]) 220 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 221 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 222 // CHECK1: omp_offload.failed: 223 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3:[0-9]+]] 224 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 225 // CHECK1: omp_offload.cont: 226 // CHECK1-NEXT: ret void 227 // 228 // 229 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 230 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { 231 // CHECK1-NEXT: entry: 232 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 233 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 234 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 235 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 236 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 237 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 238 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 239 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 240 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 241 // CHECK1-NEXT: ret void 242 // 243 // 244 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined 245 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 246 // CHECK1-NEXT: entry: 247 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 248 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 249 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 250 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 251 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 252 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 253 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 254 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 255 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 256 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 257 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 258 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 259 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 260 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 261 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 262 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 263 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 264 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 265 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 266 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 267 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 268 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 269 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 270 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP0]], align 8 271 // CHECK1-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[TMP4]], i64 16) ] 272 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 273 // CHECK1-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 274 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 275 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 276 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 277 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 278 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 279 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 280 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 281 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 282 // CHECK1: cond.true: 283 // CHECK1-NEXT: br label [[COND_END:%.*]] 284 // CHECK1: cond.false: 285 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 286 // CHECK1-NEXT: br label [[COND_END]] 287 // CHECK1: cond.end: 288 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 289 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 290 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 291 // CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 292 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 293 // CHECK1: omp.inner.for.cond: 294 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]] 295 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]] 296 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 297 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 298 // CHECK1: omp.inner.for.body: 299 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 300 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 301 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 302 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 303 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP8]] 304 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 305 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 306 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM]] 307 // CHECK1-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]] 308 // CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP8]] 309 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 310 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64 311 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM2]] 312 // CHECK1-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP8]] 313 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]] 314 // CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP8]] 315 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 316 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64 317 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i64 [[IDXPROM5]] 318 // CHECK1-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP8]] 319 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]] 320 // CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP8]] 321 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 322 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64 323 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[IDXPROM8]] 324 // CHECK1-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP8]] 325 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 326 // CHECK1: omp.body.continue: 327 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 328 // CHECK1: omp.inner.for.inc: 329 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 330 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 331 // CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 332 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 333 // CHECK1: omp.inner.for.end: 334 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 335 // CHECK1: omp.loop.exit: 336 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP6]]) 337 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 338 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 339 // CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 340 // CHECK1: .omp.final.then: 341 // CHECK1-NEXT: store i32 32000001, ptr [[I]], align 4 342 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 343 // CHECK1: .omp.final.done: 344 // CHECK1-NEXT: ret void 345 // 346 // 347 // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 348 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 349 // CHECK1-NEXT: entry: 350 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 351 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 352 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 353 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 354 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 355 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 356 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 357 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 358 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 359 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 360 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 361 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 362 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 363 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 364 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 365 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 366 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 367 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 368 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 8 369 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 370 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 371 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 372 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 373 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 374 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8 375 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 376 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 8 377 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 378 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 379 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 380 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 8 381 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 382 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP11]], align 8 383 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 384 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 385 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 386 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 8 387 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 388 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 8 389 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 390 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 391 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 392 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 393 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 394 // CHECK1-NEXT: store i32 3, ptr [[TMP18]], align 4 395 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 396 // CHECK1-NEXT: store i32 4, ptr [[TMP19]], align 4 397 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 398 // CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 8 399 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 400 // CHECK1-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 8 401 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 402 // CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP22]], align 8 403 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 404 // CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP23]], align 8 405 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 406 // CHECK1-NEXT: store ptr null, ptr [[TMP24]], align 8 407 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 408 // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 409 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 410 // CHECK1-NEXT: store i64 4571424, ptr [[TMP26]], align 8 411 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 412 // CHECK1-NEXT: store i64 0, ptr [[TMP27]], align 8 413 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 414 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 415 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 416 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4 417 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 418 // CHECK1-NEXT: store i32 0, ptr [[TMP30]], align 4 419 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, ptr [[KERNEL_ARGS]]) 420 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 421 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 422 // CHECK1: omp_offload.failed: 423 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]] 424 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 425 // CHECK1: omp_offload.cont: 426 // CHECK1-NEXT: ret void 427 // 428 // 429 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 430 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] { 431 // CHECK1-NEXT: entry: 432 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 433 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 434 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 435 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 436 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 437 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 438 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 439 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 440 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 441 // CHECK1-NEXT: ret void 442 // 443 // 444 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined 445 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 446 // CHECK1-NEXT: entry: 447 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 448 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 449 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 450 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 451 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 452 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 453 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 454 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 455 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 456 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 457 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 458 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 459 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 460 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 461 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 462 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 463 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 464 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 465 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 466 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 467 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 468 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 469 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 470 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 471 // CHECK1-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 472 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 473 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 474 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 475 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 476 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 477 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 478 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 479 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 480 // CHECK1: cond.true: 481 // CHECK1-NEXT: br label [[COND_END:%.*]] 482 // CHECK1: cond.false: 483 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 484 // CHECK1-NEXT: br label [[COND_END]] 485 // CHECK1: cond.end: 486 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 487 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 488 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 489 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 490 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 491 // CHECK1: omp.inner.for.cond: 492 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 493 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 494 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 495 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 496 // CHECK1: omp.inner.for.body: 497 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 498 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 499 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 500 // CHECK1-NEXT: store i32 [[SUB]], ptr [[I]], align 4 501 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8 502 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 503 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 504 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]] 505 // CHECK1-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4 506 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8 507 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 508 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 509 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]] 510 // CHECK1-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 511 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 512 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8 513 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 514 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 515 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]] 516 // CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4 517 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 518 // CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8 519 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 520 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 521 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]] 522 // CHECK1-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4 523 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 524 // CHECK1: omp.body.continue: 525 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 526 // CHECK1: omp.inner.for.inc: 527 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 528 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 529 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 530 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 531 // CHECK1: omp.inner.for.end: 532 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 533 // CHECK1: omp.loop.exit: 534 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 535 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 536 // CHECK1-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 537 // CHECK1-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 538 // CHECK1: .omp.final.then: 539 // CHECK1-NEXT: store i32 32, ptr [[I]], align 4 540 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 541 // CHECK1: .omp.final.done: 542 // CHECK1-NEXT: ret void 543 // 544 // 545 // CHECK1-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 546 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 547 // CHECK1-NEXT: entry: 548 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 549 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 550 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 551 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 552 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 553 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 554 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 555 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 556 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 557 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 558 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 559 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 560 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 561 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 562 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 563 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 564 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 565 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 566 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 8 567 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 568 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 569 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 570 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 571 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 572 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8 573 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 574 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 8 575 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 576 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 577 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 578 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 8 579 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 580 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP11]], align 8 581 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 582 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 583 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 584 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 8 585 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 586 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 8 587 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 588 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 589 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 590 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 591 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 592 // CHECK1-NEXT: store i32 3, ptr [[TMP18]], align 4 593 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 594 // CHECK1-NEXT: store i32 4, ptr [[TMP19]], align 4 595 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 596 // CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 8 597 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 598 // CHECK1-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 8 599 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 600 // CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP22]], align 8 601 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 602 // CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP23]], align 8 603 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 604 // CHECK1-NEXT: store ptr null, ptr [[TMP24]], align 8 605 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 606 // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 607 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 608 // CHECK1-NEXT: store i64 16908289, ptr [[TMP26]], align 8 609 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 610 // CHECK1-NEXT: store i64 0, ptr [[TMP27]], align 8 611 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 612 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 613 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 614 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4 615 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 616 // CHECK1-NEXT: store i32 0, ptr [[TMP30]], align 4 617 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, ptr [[KERNEL_ARGS]]) 618 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 619 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 620 // CHECK1: omp_offload.failed: 621 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]] 622 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 623 // CHECK1: omp_offload.cont: 624 // CHECK1-NEXT: ret void 625 // 626 // 627 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 628 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] { 629 // CHECK1-NEXT: entry: 630 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 631 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 632 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 633 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 634 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 635 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 636 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 637 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 638 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 639 // CHECK1-NEXT: ret void 640 // 641 // 642 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined 643 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 644 // CHECK1-NEXT: entry: 645 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 646 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 647 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 648 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 649 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 650 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 651 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 652 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 653 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 654 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 655 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 656 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 657 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 658 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 659 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 660 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 661 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 662 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 663 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 664 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 665 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 666 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 667 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 668 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 669 // CHECK1-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4 670 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 671 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 672 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 673 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 674 // CHECK1-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5) 675 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 676 // CHECK1: omp.dispatch.cond: 677 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 678 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 679 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 680 // CHECK1: cond.true: 681 // CHECK1-NEXT: br label [[COND_END:%.*]] 682 // CHECK1: cond.false: 683 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 684 // CHECK1-NEXT: br label [[COND_END]] 685 // CHECK1: cond.end: 686 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 687 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 688 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 689 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 690 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 691 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 692 // CHECK1-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 693 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 694 // CHECK1: omp.dispatch.body: 695 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 696 // CHECK1: omp.inner.for.cond: 697 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]] 698 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP17]] 699 // CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 700 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 701 // CHECK1: omp.inner.for.body: 702 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 703 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 704 // CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 705 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 706 // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP17]] 707 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 708 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 709 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[IDXPROM]] 710 // CHECK1-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]] 711 // CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP17]] 712 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 713 // CHECK1-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 714 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[IDXPROM3]] 715 // CHECK1-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP17]] 716 // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 717 // CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP17]] 718 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 719 // CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 720 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[IDXPROM6]] 721 // CHECK1-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP17]] 722 // CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 723 // CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP17]] 724 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] 725 // CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 726 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP23]], i64 [[IDXPROM9]] 727 // CHECK1-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP17]] 728 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 729 // CHECK1: omp.body.continue: 730 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 731 // CHECK1: omp.inner.for.inc: 732 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 733 // CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 734 // CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] 735 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 736 // CHECK1: omp.inner.for.end: 737 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 738 // CHECK1: omp.dispatch.inc: 739 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 740 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 741 // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 742 // CHECK1-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 4 743 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 744 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 745 // CHECK1-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 746 // CHECK1-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 4 747 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 748 // CHECK1: omp.dispatch.end: 749 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 750 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 751 // CHECK1-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 752 // CHECK1-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 753 // CHECK1: .omp.final.then: 754 // CHECK1-NEXT: store i32 -2147483522, ptr [[I]], align 4 755 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 756 // CHECK1: .omp.final.done: 757 // CHECK1-NEXT: ret void 758 // 759 // 760 // CHECK1-LABEL: define {{[^@]+}}@_Z12test_precondv 761 // CHECK1-SAME: () #[[ATTR0]] { 762 // CHECK1-NEXT: entry: 763 // CHECK1-NEXT: [[A:%.*]] = alloca i8, align 1 764 // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1 765 // CHECK1-NEXT: [[I_CASTED:%.*]] = alloca i64, align 8 766 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 767 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8 768 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8 769 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8 770 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 771 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 772 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 773 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 774 // CHECK1-NEXT: store i8 0, ptr [[A]], align 1 775 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, ptr [[I]], align 1 776 // CHECK1-NEXT: store i8 [[TMP0]], ptr [[I_CASTED]], align 1 777 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[I_CASTED]], align 8 778 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 779 // CHECK1-NEXT: store i8 [[TMP2]], ptr [[A_CASTED]], align 1 780 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 8 781 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 782 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP4]], align 8 783 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 784 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 785 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 786 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 787 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 788 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP7]], align 8 789 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 790 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 8 791 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 792 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 793 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 794 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 795 // CHECK1-NEXT: [[TMP12:%.*]] = load i8, ptr [[A]], align 1 796 // CHECK1-NEXT: store i8 [[TMP12]], ptr [[DOTCAPTURE_EXPR_]], align 1 797 // CHECK1-NEXT: [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 798 // CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP13]] to i32 799 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 800 // CHECK1-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 801 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 802 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 803 // CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 804 // CHECK1-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 805 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 806 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1 807 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[ADD4]] to i64 808 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 809 // CHECK1-NEXT: store i32 3, ptr [[TMP16]], align 4 810 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 811 // CHECK1-NEXT: store i32 2, ptr [[TMP17]], align 4 812 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 813 // CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP18]], align 8 814 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 815 // CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP19]], align 8 816 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 817 // CHECK1-NEXT: store ptr @.offload_sizes.5, ptr [[TMP20]], align 8 818 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 819 // CHECK1-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP21]], align 8 820 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 821 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 822 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 823 // CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8 824 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 825 // CHECK1-NEXT: store i64 [[TMP15]], ptr [[TMP24]], align 8 826 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 827 // CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 8 828 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 829 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 830 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 831 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4 832 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 833 // CHECK1-NEXT: store i32 0, ptr [[TMP28]], align 4 834 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, ptr [[KERNEL_ARGS]]) 835 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 836 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 837 // CHECK1: omp_offload.failed: 838 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i64 [[TMP1]], i64 [[TMP3]]) #[[ATTR3]] 839 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 840 // CHECK1: omp_offload.cont: 841 // CHECK1-NEXT: ret void 842 // 843 // 844 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 845 // CHECK1-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 846 // CHECK1-NEXT: entry: 847 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 848 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 849 // CHECK1-NEXT: store i64 [[I]], ptr [[I_ADDR]], align 8 850 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 851 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]]) 852 // CHECK1-NEXT: ret void 853 // 854 // 855 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined 856 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 857 // CHECK1-NEXT: entry: 858 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 859 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 860 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8 861 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 862 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 863 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 864 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 865 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 866 // CHECK1-NEXT: [[I4:%.*]] = alloca i8, align 1 867 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 868 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 869 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 870 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 871 // CHECK1-NEXT: [[I6:%.*]] = alloca i8, align 1 872 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 873 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 874 // CHECK1-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 8 875 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 876 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8 877 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 878 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1 879 // CHECK1-NEXT: store i8 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 1 880 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 881 // CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 882 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 883 // CHECK1-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 884 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 885 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 886 // CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 887 // CHECK1-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 888 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 889 // CHECK1-NEXT: store i8 [[TMP4]], ptr [[I4]], align 1 890 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 891 // CHECK1-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 892 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 893 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 894 // CHECK1: omp.precond.then: 895 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 896 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 897 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4 898 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 899 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 900 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 901 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 902 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 903 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 904 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 905 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] 906 // CHECK1-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 907 // CHECK1: cond.true: 908 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 909 // CHECK1-NEXT: br label [[COND_END:%.*]] 910 // CHECK1: cond.false: 911 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 912 // CHECK1-NEXT: br label [[COND_END]] 913 // CHECK1: cond.end: 914 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 915 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 916 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 917 // CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 918 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 919 // CHECK1: omp.inner.for.cond: 920 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] 921 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] 922 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 923 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 924 // CHECK1: omp.inner.for.body: 925 // CHECK1-NEXT: [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP20]] 926 // CHECK1-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32 927 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 928 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 929 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 930 // CHECK1-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 931 // CHECK1-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP20]] 932 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 933 // CHECK1: omp.body.continue: 934 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 935 // CHECK1: omp.inner.for.inc: 936 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 937 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1 938 // CHECK1-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 939 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 940 // CHECK1: omp.inner.for.end: 941 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 942 // CHECK1: omp.loop.exit: 943 // CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 944 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 945 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) 946 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 947 // CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 948 // CHECK1-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 949 // CHECK1: .omp.final.then: 950 // CHECK1-NEXT: [[TMP23:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 951 // CHECK1-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32 952 // CHECK1-NEXT: [[TMP24:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 953 // CHECK1-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32 954 // CHECK1-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]] 955 // CHECK1-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1 956 // CHECK1-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1 957 // CHECK1-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1 958 // CHECK1-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1 959 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]] 960 // CHECK1-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 961 // CHECK1-NEXT: store i8 [[CONV21]], ptr [[TMP0]], align 1 962 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 963 // CHECK1: .omp.final.done: 964 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 965 // CHECK1: omp.precond.end: 966 // CHECK1-NEXT: ret void 967 // 968 // 969 // CHECK1-LABEL: define {{[^@]+}}@_Z4fintv 970 // CHECK1-SAME: () #[[ATTR0]] { 971 // CHECK1-NEXT: entry: 972 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() 973 // CHECK1-NEXT: ret i32 [[CALL]] 974 // 975 // 976 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 977 // CHECK1-SAME: () #[[ATTR0]] comdat { 978 // CHECK1-NEXT: entry: 979 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 980 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 981 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 982 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 983 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 984 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 985 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 986 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 987 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA]], align 2 988 // CHECK1-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 989 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 990 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 991 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8 992 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 993 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8 994 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 995 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 996 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 997 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 998 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 999 // CHECK1-NEXT: store i32 3, ptr [[TMP7]], align 4 1000 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1001 // CHECK1-NEXT: store i32 1, ptr [[TMP8]], align 4 1002 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1003 // CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8 1004 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1005 // CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8 1006 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1007 // CHECK1-NEXT: store ptr @.offload_sizes.7, ptr [[TMP11]], align 8 1008 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1009 // CHECK1-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP12]], align 8 1010 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1011 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8 1012 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1013 // CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8 1014 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1015 // CHECK1-NEXT: store i64 100, ptr [[TMP15]], align 8 1016 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1017 // CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8 1018 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1019 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 1020 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1021 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4 1022 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1023 // CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4 1024 // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, ptr [[KERNEL_ARGS]]) 1025 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 1026 // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1027 // CHECK1: omp_offload.failed: 1028 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i64 [[TMP1]]) #[[ATTR3]] 1029 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1030 // CHECK1: omp_offload.cont: 1031 // CHECK1-NEXT: ret i32 0 1032 // 1033 // 1034 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 1035 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR1]] { 1036 // CHECK1-NEXT: entry: 1037 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1038 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1039 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]]) 1040 // CHECK1-NEXT: ret void 1041 // 1042 // 1043 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined 1044 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 1045 // CHECK1-NEXT: entry: 1046 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1047 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1048 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8 1049 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1050 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1051 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1052 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1053 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1054 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1055 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1056 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1057 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1058 // CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8 1059 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8 1060 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1061 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 1062 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1063 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1064 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2 1065 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 1066 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1067 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 1068 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 1069 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1070 // CHECK1: omp.dispatch.cond: 1071 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1072 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 1073 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1074 // CHECK1: cond.true: 1075 // CHECK1-NEXT: br label [[COND_END:%.*]] 1076 // CHECK1: cond.false: 1077 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1078 // CHECK1-NEXT: br label [[COND_END]] 1079 // CHECK1: cond.end: 1080 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1081 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1082 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1083 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 1084 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1085 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1086 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1087 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1088 // CHECK1: omp.dispatch.body: 1089 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1090 // CHECK1: omp.inner.for.cond: 1091 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] 1092 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] 1093 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1094 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1095 // CHECK1: omp.inner.for.body: 1096 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 1097 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 1098 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1099 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] 1100 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1101 // CHECK1: omp.body.continue: 1102 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1103 // CHECK1: omp.inner.for.inc: 1104 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 1105 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 1106 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 1107 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] 1108 // CHECK1: omp.inner.for.end: 1109 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1110 // CHECK1: omp.dispatch.inc: 1111 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1112 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1113 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 1114 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4 1115 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1116 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1117 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 1118 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4 1119 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1120 // CHECK1: omp.dispatch.end: 1121 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 1122 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1123 // CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 1124 // CHECK1-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1125 // CHECK1: .omp.final.then: 1126 // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 1127 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1128 // CHECK1: .omp.final.done: 1129 // CHECK1-NEXT: ret void 1130 // 1131 // 1132 // CHECK3-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 1133 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 1134 // CHECK3-NEXT: entry: 1135 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 1136 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 1137 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 1138 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 1139 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 1140 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 1141 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 1142 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1143 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1144 // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 1145 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 1146 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 1147 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 1148 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 1149 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 1150 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 1151 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 1152 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1153 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 4 1154 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1155 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 4 1156 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1157 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1158 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1159 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 4 1160 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1161 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 4 1162 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1163 // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 1164 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1165 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 4 1166 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1167 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP11]], align 4 1168 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1169 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 1170 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1171 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 4 1172 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1173 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 4 1174 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1175 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 1176 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1177 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1178 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1179 // CHECK3-NEXT: store i32 3, ptr [[TMP18]], align 4 1180 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1181 // CHECK3-NEXT: store i32 4, ptr [[TMP19]], align 4 1182 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1183 // CHECK3-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 4 1184 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1185 // CHECK3-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 4 1186 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1187 // CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP22]], align 4 1188 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1189 // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP23]], align 4 1190 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1191 // CHECK3-NEXT: store ptr null, ptr [[TMP24]], align 4 1192 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1193 // CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4 1194 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1195 // CHECK3-NEXT: store i64 4571424, ptr [[TMP26]], align 8 1196 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1197 // CHECK3-NEXT: store i64 0, ptr [[TMP27]], align 8 1198 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1199 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 1200 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1201 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4 1202 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1203 // CHECK3-NEXT: store i32 0, ptr [[TMP30]], align 4 1204 // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, ptr [[KERNEL_ARGS]]) 1205 // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1206 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1207 // CHECK3: omp_offload.failed: 1208 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3:[0-9]+]] 1209 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1210 // CHECK3: omp_offload.cont: 1211 // CHECK3-NEXT: ret void 1212 // 1213 // 1214 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 1215 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { 1216 // CHECK3-NEXT: entry: 1217 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 1218 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 1219 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 1220 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 1221 // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 1222 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 1223 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 1224 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 1225 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 1226 // CHECK3-NEXT: ret void 1227 // 1228 // 1229 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined 1230 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 1231 // CHECK3-NEXT: entry: 1232 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1233 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1234 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 1235 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 1236 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 1237 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 1238 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1239 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1240 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1241 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1242 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1243 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1244 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1245 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1246 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1247 // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 1248 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 1249 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 1250 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 1251 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 1252 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 1253 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 1254 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 1255 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP0]], align 4 1256 // CHECK3-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[TMP4]], i32 16) ] 1257 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1258 // CHECK3-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 1259 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1260 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1261 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1262 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 1263 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1264 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1265 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 1266 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1267 // CHECK3: cond.true: 1268 // CHECK3-NEXT: br label [[COND_END:%.*]] 1269 // CHECK3: cond.false: 1270 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1271 // CHECK3-NEXT: br label [[COND_END]] 1272 // CHECK3: cond.end: 1273 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 1274 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1275 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1276 // CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 1277 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1278 // CHECK3: omp.inner.for.cond: 1279 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] 1280 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 1281 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 1282 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1283 // CHECK3: omp.inner.for.body: 1284 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 1285 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 1286 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 1287 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 1288 // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP9]] 1289 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 1290 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i32 [[TMP14]] 1291 // CHECK3-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] 1292 // CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP9]] 1293 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 1294 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i32 [[TMP17]] 1295 // CHECK3-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP9]] 1296 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]] 1297 // CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP9]] 1298 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 1299 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i32 [[TMP20]] 1300 // CHECK3-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP9]] 1301 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]] 1302 // CHECK3-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP9]] 1303 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 1304 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i32 [[TMP23]] 1305 // CHECK3-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP9]] 1306 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1307 // CHECK3: omp.body.continue: 1308 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1309 // CHECK3: omp.inner.for.inc: 1310 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 1311 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1 1312 // CHECK3-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 1313 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 1314 // CHECK3: omp.inner.for.end: 1315 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1316 // CHECK3: omp.loop.exit: 1317 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP6]]) 1318 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1319 // CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 1320 // CHECK3-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1321 // CHECK3: .omp.final.then: 1322 // CHECK3-NEXT: store i32 32000001, ptr [[I]], align 4 1323 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1324 // CHECK3: .omp.final.done: 1325 // CHECK3-NEXT: ret void 1326 // 1327 // 1328 // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 1329 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 1330 // CHECK3-NEXT: entry: 1331 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 1332 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 1333 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 1334 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 1335 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 1336 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 1337 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 1338 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1339 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1340 // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 1341 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 1342 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 1343 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 1344 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 1345 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 1346 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 1347 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 1348 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1349 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 4 1350 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1351 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 4 1352 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1353 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1354 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1355 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 4 1356 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1357 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 4 1358 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1359 // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 1360 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1361 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 4 1362 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1363 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP11]], align 4 1364 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1365 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 1366 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1367 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 4 1368 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1369 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 4 1370 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1371 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 1372 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1373 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1374 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1375 // CHECK3-NEXT: store i32 3, ptr [[TMP18]], align 4 1376 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1377 // CHECK3-NEXT: store i32 4, ptr [[TMP19]], align 4 1378 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1379 // CHECK3-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 4 1380 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1381 // CHECK3-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 4 1382 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1383 // CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP22]], align 4 1384 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1385 // CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP23]], align 4 1386 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1387 // CHECK3-NEXT: store ptr null, ptr [[TMP24]], align 4 1388 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1389 // CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4 1390 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1391 // CHECK3-NEXT: store i64 4571424, ptr [[TMP26]], align 8 1392 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1393 // CHECK3-NEXT: store i64 0, ptr [[TMP27]], align 8 1394 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1395 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 1396 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1397 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4 1398 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1399 // CHECK3-NEXT: store i32 0, ptr [[TMP30]], align 4 1400 // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, ptr [[KERNEL_ARGS]]) 1401 // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1402 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1403 // CHECK3: omp_offload.failed: 1404 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]] 1405 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1406 // CHECK3: omp_offload.cont: 1407 // CHECK3-NEXT: ret void 1408 // 1409 // 1410 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 1411 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] { 1412 // CHECK3-NEXT: entry: 1413 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 1414 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 1415 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 1416 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 1417 // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 1418 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 1419 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 1420 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 1421 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 1422 // CHECK3-NEXT: ret void 1423 // 1424 // 1425 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined 1426 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 1427 // CHECK3-NEXT: entry: 1428 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1429 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1430 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 1431 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 1432 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 1433 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 1434 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1435 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1436 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1437 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1438 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1439 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1440 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1441 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1442 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1443 // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 1444 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 1445 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 1446 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 1447 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 1448 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 1449 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 1450 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 1451 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1452 // CHECK3-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 1453 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1454 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1455 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1456 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 1457 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1458 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1459 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 1460 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1461 // CHECK3: cond.true: 1462 // CHECK3-NEXT: br label [[COND_END:%.*]] 1463 // CHECK3: cond.false: 1464 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1465 // CHECK3-NEXT: br label [[COND_END]] 1466 // CHECK3: cond.end: 1467 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1468 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1469 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1470 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 1471 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1472 // CHECK3: omp.inner.for.cond: 1473 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1474 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1475 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1476 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1477 // CHECK3: omp.inner.for.body: 1478 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1479 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 1480 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 1481 // CHECK3-NEXT: store i32 [[SUB]], ptr [[I]], align 4 1482 // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 4 1483 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 1484 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 [[TMP13]] 1485 // CHECK3-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4 1486 // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 4 1487 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 1488 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i32 [[TMP16]] 1489 // CHECK3-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX2]], align 4 1490 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 1491 // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 4 1492 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 1493 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i32 [[TMP19]] 1494 // CHECK3-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX4]], align 4 1495 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 1496 // CHECK3-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 4 1497 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 1498 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i32 [[TMP22]] 1499 // CHECK3-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4 1500 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1501 // CHECK3: omp.body.continue: 1502 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1503 // CHECK3: omp.inner.for.inc: 1504 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1505 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 1506 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 1507 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 1508 // CHECK3: omp.inner.for.end: 1509 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1510 // CHECK3: omp.loop.exit: 1511 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 1512 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1513 // CHECK3-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 1514 // CHECK3-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1515 // CHECK3: .omp.final.then: 1516 // CHECK3-NEXT: store i32 32, ptr [[I]], align 4 1517 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1518 // CHECK3: .omp.final.done: 1519 // CHECK3-NEXT: ret void 1520 // 1521 // 1522 // CHECK3-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 1523 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 1524 // CHECK3-NEXT: entry: 1525 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 1526 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 1527 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 1528 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 1529 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 1530 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 1531 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 1532 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1533 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1534 // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 1535 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 1536 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 1537 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 1538 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 1539 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 1540 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 1541 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 1542 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1543 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 4 1544 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1545 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 4 1546 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1547 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1548 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1549 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 4 1550 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1551 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 4 1552 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1553 // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 1554 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1555 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 4 1556 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1557 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP11]], align 4 1558 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1559 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 1560 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1561 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 4 1562 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1563 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 4 1564 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1565 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 1566 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1567 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1568 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1569 // CHECK3-NEXT: store i32 3, ptr [[TMP18]], align 4 1570 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1571 // CHECK3-NEXT: store i32 4, ptr [[TMP19]], align 4 1572 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1573 // CHECK3-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 4 1574 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1575 // CHECK3-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 4 1576 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1577 // CHECK3-NEXT: store ptr @.offload_sizes.3, ptr [[TMP22]], align 4 1578 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1579 // CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP23]], align 4 1580 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1581 // CHECK3-NEXT: store ptr null, ptr [[TMP24]], align 4 1582 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1583 // CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4 1584 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1585 // CHECK3-NEXT: store i64 16908289, ptr [[TMP26]], align 8 1586 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1587 // CHECK3-NEXT: store i64 0, ptr [[TMP27]], align 8 1588 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1589 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 1590 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1591 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4 1592 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1593 // CHECK3-NEXT: store i32 0, ptr [[TMP30]], align 4 1594 // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, ptr [[KERNEL_ARGS]]) 1595 // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1596 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1597 // CHECK3: omp_offload.failed: 1598 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]] 1599 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1600 // CHECK3: omp_offload.cont: 1601 // CHECK3-NEXT: ret void 1602 // 1603 // 1604 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 1605 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] { 1606 // CHECK3-NEXT: entry: 1607 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 1608 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 1609 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 1610 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 1611 // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 1612 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 1613 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 1614 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 1615 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 1616 // CHECK3-NEXT: ret void 1617 // 1618 // 1619 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined 1620 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 1621 // CHECK3-NEXT: entry: 1622 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1623 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1624 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 1625 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 1626 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 1627 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 1628 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1629 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1630 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1631 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1632 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1633 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1634 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1635 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1636 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1637 // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 1638 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 1639 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 1640 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 1641 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 1642 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 1643 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 1644 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 1645 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1646 // CHECK3-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4 1647 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1648 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1649 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1650 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 1651 // CHECK3-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5) 1652 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1653 // CHECK3: omp.dispatch.cond: 1654 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1655 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 1656 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1657 // CHECK3: cond.true: 1658 // CHECK3-NEXT: br label [[COND_END:%.*]] 1659 // CHECK3: cond.false: 1660 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1661 // CHECK3-NEXT: br label [[COND_END]] 1662 // CHECK3: cond.end: 1663 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1664 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1665 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1666 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 1667 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1668 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1669 // CHECK3-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 1670 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1671 // CHECK3: omp.dispatch.body: 1672 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1673 // CHECK3: omp.inner.for.cond: 1674 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] 1675 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] 1676 // CHECK3-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 1677 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1678 // CHECK3: omp.inner.for.body: 1679 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 1680 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 1681 // CHECK3-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 1682 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 1683 // CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP18]] 1684 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 1685 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i32 [[TMP15]] 1686 // CHECK3-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] 1687 // CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP18]] 1688 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 1689 // CHECK3-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i32 [[TMP18]] 1690 // CHECK3-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP18]] 1691 // CHECK3-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] 1692 // CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP18]] 1693 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 1694 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i32 [[TMP21]] 1695 // CHECK3-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP18]] 1696 // CHECK3-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] 1697 // CHECK3-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP18]] 1698 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 1699 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP23]], i32 [[TMP24]] 1700 // CHECK3-NEXT: store float [[MUL6]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP18]] 1701 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1702 // CHECK3: omp.body.continue: 1703 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1704 // CHECK3: omp.inner.for.inc: 1705 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 1706 // CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 1707 // CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 1708 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 1709 // CHECK3: omp.inner.for.end: 1710 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1711 // CHECK3: omp.dispatch.inc: 1712 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1713 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1714 // CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] 1715 // CHECK3-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_LB]], align 4 1716 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1717 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1718 // CHECK3-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] 1719 // CHECK3-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_UB]], align 4 1720 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 1721 // CHECK3: omp.dispatch.end: 1722 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 1723 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1724 // CHECK3-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 1725 // CHECK3-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1726 // CHECK3: .omp.final.then: 1727 // CHECK3-NEXT: store i32 -2147483522, ptr [[I]], align 4 1728 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1729 // CHECK3: .omp.final.done: 1730 // CHECK3-NEXT: ret void 1731 // 1732 // 1733 // CHECK3-LABEL: define {{[^@]+}}@_Z12test_precondv 1734 // CHECK3-SAME: () #[[ATTR0]] { 1735 // CHECK3-NEXT: entry: 1736 // CHECK3-NEXT: [[A:%.*]] = alloca i8, align 1 1737 // CHECK3-NEXT: [[I:%.*]] = alloca i8, align 1 1738 // CHECK3-NEXT: [[I_CASTED:%.*]] = alloca i32, align 4 1739 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1740 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 4 1741 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 4 1742 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 4 1743 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 1744 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1745 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1746 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1747 // CHECK3-NEXT: store i8 0, ptr [[A]], align 1 1748 // CHECK3-NEXT: [[TMP0:%.*]] = load i8, ptr [[I]], align 1 1749 // CHECK3-NEXT: store i8 [[TMP0]], ptr [[I_CASTED]], align 1 1750 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[I_CASTED]], align 4 1751 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 1752 // CHECK3-NEXT: store i8 [[TMP2]], ptr [[A_CASTED]], align 1 1753 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 4 1754 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1755 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP4]], align 4 1756 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1757 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 1758 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1759 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 1760 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1761 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP7]], align 4 1762 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1763 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 4 1764 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1765 // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 1766 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1767 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1768 // CHECK3-NEXT: [[TMP12:%.*]] = load i8, ptr [[A]], align 1 1769 // CHECK3-NEXT: store i8 [[TMP12]], ptr [[DOTCAPTURE_EXPR_]], align 1 1770 // CHECK3-NEXT: [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 1771 // CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP13]] to i32 1772 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 1773 // CHECK3-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 1774 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 1775 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1776 // CHECK3-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 1777 // CHECK3-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 1778 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 1779 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1 1780 // CHECK3-NEXT: [[TMP15:%.*]] = zext i32 [[ADD4]] to i64 1781 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1782 // CHECK3-NEXT: store i32 3, ptr [[TMP16]], align 4 1783 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1784 // CHECK3-NEXT: store i32 2, ptr [[TMP17]], align 4 1785 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1786 // CHECK3-NEXT: store ptr [[TMP10]], ptr [[TMP18]], align 4 1787 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1788 // CHECK3-NEXT: store ptr [[TMP11]], ptr [[TMP19]], align 4 1789 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1790 // CHECK3-NEXT: store ptr @.offload_sizes.5, ptr [[TMP20]], align 4 1791 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1792 // CHECK3-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP21]], align 4 1793 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1794 // CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 4 1795 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1796 // CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 4 1797 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1798 // CHECK3-NEXT: store i64 [[TMP15]], ptr [[TMP24]], align 8 1799 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1800 // CHECK3-NEXT: store i64 0, ptr [[TMP25]], align 8 1801 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1802 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 1803 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1804 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4 1805 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1806 // CHECK3-NEXT: store i32 0, ptr [[TMP28]], align 4 1807 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, ptr [[KERNEL_ARGS]]) 1808 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 1809 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1810 // CHECK3: omp_offload.failed: 1811 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i32 [[TMP1]], i32 [[TMP3]]) #[[ATTR3]] 1812 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1813 // CHECK3: omp_offload.cont: 1814 // CHECK3-NEXT: ret void 1815 // 1816 // 1817 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 1818 // CHECK3-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 1819 // CHECK3-NEXT: entry: 1820 // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 1821 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1822 // CHECK3-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 1823 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1824 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]]) 1825 // CHECK3-NEXT: ret void 1826 // 1827 // 1828 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined 1829 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 1830 // CHECK3-NEXT: entry: 1831 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1832 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1833 // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 4 1834 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 1835 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1836 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 1837 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1838 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1839 // CHECK3-NEXT: [[I4:%.*]] = alloca i8, align 1 1840 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1841 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1842 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1843 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1844 // CHECK3-NEXT: [[I6:%.*]] = alloca i8, align 1 1845 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1846 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1847 // CHECK3-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 4 1848 // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 1849 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 4 1850 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4 1851 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1 1852 // CHECK3-NEXT: store i8 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 1 1853 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 1854 // CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 1855 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 1856 // CHECK3-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 1857 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 1858 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1859 // CHECK3-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 1860 // CHECK3-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 1861 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 1862 // CHECK3-NEXT: store i8 [[TMP4]], ptr [[I4]], align 1 1863 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 1864 // CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 1865 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 1866 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1867 // CHECK3: omp.precond.then: 1868 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1869 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 1870 // CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4 1871 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1872 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1873 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1874 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1875 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1876 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1877 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 1878 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] 1879 // CHECK3-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1880 // CHECK3: cond.true: 1881 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 1882 // CHECK3-NEXT: br label [[COND_END:%.*]] 1883 // CHECK3: cond.false: 1884 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1885 // CHECK3-NEXT: br label [[COND_END]] 1886 // CHECK3: cond.end: 1887 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 1888 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1889 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1890 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 1891 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1892 // CHECK3: omp.inner.for.cond: 1893 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] 1894 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] 1895 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 1896 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1897 // CHECK3: omp.inner.for.body: 1898 // CHECK3-NEXT: [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP21]] 1899 // CHECK3-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32 1900 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 1901 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 1902 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 1903 // CHECK3-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 1904 // CHECK3-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP21]] 1905 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1906 // CHECK3: omp.body.continue: 1907 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1908 // CHECK3: omp.inner.for.inc: 1909 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 1910 // CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1 1911 // CHECK3-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 1912 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 1913 // CHECK3: omp.inner.for.end: 1914 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1915 // CHECK3: omp.loop.exit: 1916 // CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1917 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 1918 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) 1919 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1920 // CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 1921 // CHECK3-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1922 // CHECK3: .omp.final.then: 1923 // CHECK3-NEXT: [[TMP23:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 1924 // CHECK3-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32 1925 // CHECK3-NEXT: [[TMP24:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 1926 // CHECK3-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32 1927 // CHECK3-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]] 1928 // CHECK3-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1 1929 // CHECK3-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1 1930 // CHECK3-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1 1931 // CHECK3-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1 1932 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]] 1933 // CHECK3-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 1934 // CHECK3-NEXT: store i8 [[CONV21]], ptr [[TMP0]], align 1 1935 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1936 // CHECK3: .omp.final.done: 1937 // CHECK3-NEXT: br label [[OMP_PRECOND_END]] 1938 // CHECK3: omp.precond.end: 1939 // CHECK3-NEXT: ret void 1940 // 1941 // 1942 // CHECK3-LABEL: define {{[^@]+}}@_Z4fintv 1943 // CHECK3-SAME: () #[[ATTR0]] { 1944 // CHECK3-NEXT: entry: 1945 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() 1946 // CHECK3-NEXT: ret i32 [[CALL]] 1947 // 1948 // 1949 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 1950 // CHECK3-SAME: () #[[ATTR0]] comdat { 1951 // CHECK3-NEXT: entry: 1952 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 1953 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 1954 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 1955 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 1956 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 1957 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1958 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1959 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 1960 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA]], align 2 1961 // CHECK3-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 1962 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 1963 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1964 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4 1965 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1966 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4 1967 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1968 // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 1969 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1970 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1971 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1972 // CHECK3-NEXT: store i32 3, ptr [[TMP7]], align 4 1973 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1974 // CHECK3-NEXT: store i32 1, ptr [[TMP8]], align 4 1975 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1976 // CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4 1977 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1978 // CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4 1979 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1980 // CHECK3-NEXT: store ptr @.offload_sizes.7, ptr [[TMP11]], align 4 1981 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1982 // CHECK3-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP12]], align 4 1983 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1984 // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4 1985 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1986 // CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4 1987 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1988 // CHECK3-NEXT: store i64 100, ptr [[TMP15]], align 8 1989 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1990 // CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8 1991 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1992 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 1993 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1994 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4 1995 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1996 // CHECK3-NEXT: store i32 0, ptr [[TMP19]], align 4 1997 // CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, ptr [[KERNEL_ARGS]]) 1998 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 1999 // CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2000 // CHECK3: omp_offload.failed: 2001 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i32 [[TMP1]]) #[[ATTR3]] 2002 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2003 // CHECK3: omp_offload.cont: 2004 // CHECK3-NEXT: ret i32 0 2005 // 2006 // 2007 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 2008 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR1]] { 2009 // CHECK3-NEXT: entry: 2010 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2011 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2012 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]]) 2013 // CHECK3-NEXT: ret void 2014 // 2015 // 2016 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined 2017 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 2018 // CHECK3-NEXT: entry: 2019 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2020 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2021 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4 2022 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2023 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2024 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2025 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2026 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2027 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2028 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2029 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2030 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2031 // CHECK3-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4 2032 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4 2033 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2034 // CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 2035 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2036 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2037 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2 2038 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 2039 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2040 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 2041 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 2042 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2043 // CHECK3: omp.dispatch.cond: 2044 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2045 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 2046 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2047 // CHECK3: cond.true: 2048 // CHECK3-NEXT: br label [[COND_END:%.*]] 2049 // CHECK3: cond.false: 2050 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2051 // CHECK3-NEXT: br label [[COND_END]] 2052 // CHECK3: cond.end: 2053 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2054 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2055 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2056 // CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 2057 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2058 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2059 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2060 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2061 // CHECK3: omp.dispatch.body: 2062 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2063 // CHECK3: omp.inner.for.cond: 2064 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] 2065 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]] 2066 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2067 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2068 // CHECK3: omp.inner.for.body: 2069 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 2070 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 2071 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2072 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] 2073 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2074 // CHECK3: omp.body.continue: 2075 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2076 // CHECK3: omp.inner.for.inc: 2077 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 2078 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 2079 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 2080 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 2081 // CHECK3: omp.inner.for.end: 2082 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2083 // CHECK3: omp.dispatch.inc: 2084 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2085 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2086 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 2087 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4 2088 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2089 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2090 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 2091 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4 2092 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2093 // CHECK3: omp.dispatch.end: 2094 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 2095 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2096 // CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 2097 // CHECK3-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2098 // CHECK3: .omp.final.then: 2099 // CHECK3-NEXT: store i32 100, ptr [[I]], align 4 2100 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2101 // CHECK3: .omp.final.done: 2102 // CHECK3-NEXT: ret void 2103 // 2104 // 2105 // CHECK5-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 2106 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 2107 // CHECK5-NEXT: entry: 2108 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 2109 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 2110 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 2111 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 2112 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 2113 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 2114 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 2115 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2116 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2117 // CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 2118 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 2119 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 2120 // CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 2121 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 2122 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 2123 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 2124 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 2125 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2126 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 8 2127 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2128 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 2129 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2130 // CHECK5-NEXT: store ptr null, ptr [[TMP6]], align 8 2131 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2132 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8 2133 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2134 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 8 2135 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2136 // CHECK5-NEXT: store ptr null, ptr [[TMP9]], align 8 2137 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2138 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 8 2139 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2140 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP11]], align 8 2141 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2142 // CHECK5-NEXT: store ptr null, ptr [[TMP12]], align 8 2143 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2144 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 8 2145 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2146 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 8 2147 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 2148 // CHECK5-NEXT: store ptr null, ptr [[TMP15]], align 8 2149 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2150 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2151 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2152 // CHECK5-NEXT: store i32 3, ptr [[TMP18]], align 4 2153 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2154 // CHECK5-NEXT: store i32 4, ptr [[TMP19]], align 4 2155 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2156 // CHECK5-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 8 2157 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2158 // CHECK5-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 8 2159 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2160 // CHECK5-NEXT: store ptr @.offload_sizes, ptr [[TMP22]], align 8 2161 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2162 // CHECK5-NEXT: store ptr @.offload_maptypes, ptr [[TMP23]], align 8 2163 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 2164 // CHECK5-NEXT: store ptr null, ptr [[TMP24]], align 8 2165 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 2166 // CHECK5-NEXT: store ptr null, ptr [[TMP25]], align 8 2167 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 2168 // CHECK5-NEXT: store i64 4571424, ptr [[TMP26]], align 8 2169 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 2170 // CHECK5-NEXT: store i64 0, ptr [[TMP27]], align 8 2171 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 2172 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 2173 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 2174 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4 2175 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 2176 // CHECK5-NEXT: store i32 0, ptr [[TMP30]], align 4 2177 // CHECK5-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, ptr [[KERNEL_ARGS]]) 2178 // CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 2179 // CHECK5-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2180 // CHECK5: omp_offload.failed: 2181 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3:[0-9]+]] 2182 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 2183 // CHECK5: omp_offload.cont: 2184 // CHECK5-NEXT: ret void 2185 // 2186 // 2187 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 2188 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { 2189 // CHECK5-NEXT: entry: 2190 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 2191 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 2192 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 2193 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 2194 // CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 2195 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 2196 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 2197 // CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 2198 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 2199 // CHECK5-NEXT: ret void 2200 // 2201 // 2202 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined 2203 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 2204 // CHECK5-NEXT: entry: 2205 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2206 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2207 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 2208 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 2209 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 2210 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 2211 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2212 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2213 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2214 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2215 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2216 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2217 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2218 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2219 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2220 // CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 2221 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 2222 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 2223 // CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 2224 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 2225 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 2226 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 2227 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 2228 // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP0]], align 8 2229 // CHECK5-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[TMP4]], i64 16) ] 2230 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2231 // CHECK5-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 2232 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2233 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2234 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2235 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 2236 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2237 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2238 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 2239 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2240 // CHECK5: cond.true: 2241 // CHECK5-NEXT: br label [[COND_END:%.*]] 2242 // CHECK5: cond.false: 2243 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2244 // CHECK5-NEXT: br label [[COND_END]] 2245 // CHECK5: cond.end: 2246 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 2247 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2248 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2249 // CHECK5-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 2250 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2251 // CHECK5: omp.inner.for.cond: 2252 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]] 2253 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]] 2254 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 2255 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2256 // CHECK5: omp.inner.for.body: 2257 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 2258 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 2259 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 2260 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 2261 // CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP8]] 2262 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 2263 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 2264 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM]] 2265 // CHECK5-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]] 2266 // CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP8]] 2267 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 2268 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64 2269 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM2]] 2270 // CHECK5-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP8]] 2271 // CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]] 2272 // CHECK5-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP8]] 2273 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 2274 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64 2275 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i64 [[IDXPROM5]] 2276 // CHECK5-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP8]] 2277 // CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]] 2278 // CHECK5-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP8]] 2279 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] 2280 // CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64 2281 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[IDXPROM8]] 2282 // CHECK5-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP8]] 2283 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2284 // CHECK5: omp.body.continue: 2285 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2286 // CHECK5: omp.inner.for.inc: 2287 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 2288 // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 2289 // CHECK5-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] 2290 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 2291 // CHECK5: omp.inner.for.end: 2292 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2293 // CHECK5: omp.loop.exit: 2294 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP6]]) 2295 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2296 // CHECK5-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 2297 // CHECK5-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2298 // CHECK5: .omp.final.then: 2299 // CHECK5-NEXT: store i32 32000001, ptr [[I]], align 4 2300 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2301 // CHECK5: .omp.final.done: 2302 // CHECK5-NEXT: ret void 2303 // 2304 // 2305 // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 2306 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 2307 // CHECK5-NEXT: entry: 2308 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 2309 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 2310 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 2311 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 2312 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 2313 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 2314 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 2315 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2316 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2317 // CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 2318 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 2319 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 2320 // CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 2321 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 2322 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 2323 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 2324 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 2325 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2326 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 8 2327 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2328 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 2329 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2330 // CHECK5-NEXT: store ptr null, ptr [[TMP6]], align 8 2331 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2332 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8 2333 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2334 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 8 2335 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2336 // CHECK5-NEXT: store ptr null, ptr [[TMP9]], align 8 2337 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2338 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 8 2339 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2340 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP11]], align 8 2341 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2342 // CHECK5-NEXT: store ptr null, ptr [[TMP12]], align 8 2343 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2344 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 8 2345 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2346 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 8 2347 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 2348 // CHECK5-NEXT: store ptr null, ptr [[TMP15]], align 8 2349 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2350 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2351 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2352 // CHECK5-NEXT: store i32 3, ptr [[TMP18]], align 4 2353 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2354 // CHECK5-NEXT: store i32 4, ptr [[TMP19]], align 4 2355 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2356 // CHECK5-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 8 2357 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2358 // CHECK5-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 8 2359 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2360 // CHECK5-NEXT: store ptr @.offload_sizes.1, ptr [[TMP22]], align 8 2361 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2362 // CHECK5-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP23]], align 8 2363 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 2364 // CHECK5-NEXT: store ptr null, ptr [[TMP24]], align 8 2365 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 2366 // CHECK5-NEXT: store ptr null, ptr [[TMP25]], align 8 2367 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 2368 // CHECK5-NEXT: store i64 4571424, ptr [[TMP26]], align 8 2369 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 2370 // CHECK5-NEXT: store i64 0, ptr [[TMP27]], align 8 2371 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 2372 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 2373 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 2374 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4 2375 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 2376 // CHECK5-NEXT: store i32 0, ptr [[TMP30]], align 4 2377 // CHECK5-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, ptr [[KERNEL_ARGS]]) 2378 // CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 2379 // CHECK5-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2380 // CHECK5: omp_offload.failed: 2381 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]] 2382 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 2383 // CHECK5: omp_offload.cont: 2384 // CHECK5-NEXT: ret void 2385 // 2386 // 2387 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 2388 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] { 2389 // CHECK5-NEXT: entry: 2390 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 2391 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 2392 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 2393 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 2394 // CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 2395 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 2396 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 2397 // CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 2398 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 2399 // CHECK5-NEXT: ret void 2400 // 2401 // 2402 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined 2403 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 2404 // CHECK5-NEXT: entry: 2405 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2406 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2407 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 2408 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 2409 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 2410 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 2411 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2412 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2413 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2414 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2415 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2416 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2417 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2418 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2419 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2420 // CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 2421 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 2422 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 2423 // CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 2424 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 2425 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 2426 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 2427 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 2428 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2429 // CHECK5-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 2430 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2431 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2432 // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2433 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 2434 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2435 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2436 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 2437 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2438 // CHECK5: cond.true: 2439 // CHECK5-NEXT: br label [[COND_END:%.*]] 2440 // CHECK5: cond.false: 2441 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2442 // CHECK5-NEXT: br label [[COND_END]] 2443 // CHECK5: cond.end: 2444 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2445 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2446 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2447 // CHECK5-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 2448 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2449 // CHECK5: omp.inner.for.cond: 2450 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2451 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2452 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2453 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2454 // CHECK5: omp.inner.for.body: 2455 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2456 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 2457 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 2458 // CHECK5-NEXT: store i32 [[SUB]], ptr [[I]], align 4 2459 // CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8, !nontemporal [[META15:![0-9]+]] 2460 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 2461 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 2462 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]] 2463 // CHECK5-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4 2464 // CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8 2465 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 2466 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 2467 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]] 2468 // CHECK5-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 2469 // CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 2470 // CHECK5-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8 2471 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 2472 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 2473 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]] 2474 // CHECK5-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4 2475 // CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 2476 // CHECK5-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8, !nontemporal [[META15]] 2477 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 2478 // CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 2479 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]] 2480 // CHECK5-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4 2481 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2482 // CHECK5: omp.body.continue: 2483 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2484 // CHECK5: omp.inner.for.inc: 2485 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2486 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 2487 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 2488 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 2489 // CHECK5: omp.inner.for.end: 2490 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2491 // CHECK5: omp.loop.exit: 2492 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 2493 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2494 // CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 2495 // CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2496 // CHECK5: .omp.final.then: 2497 // CHECK5-NEXT: store i32 32, ptr [[I]], align 4 2498 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2499 // CHECK5: .omp.final.done: 2500 // CHECK5-NEXT: ret void 2501 // 2502 // 2503 // CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 2504 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 2505 // CHECK5-NEXT: entry: 2506 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 2507 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 2508 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 2509 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 2510 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 2511 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 2512 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 2513 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2514 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2515 // CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 2516 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 2517 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 2518 // CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 2519 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 2520 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 2521 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 2522 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 2523 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2524 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 8 2525 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2526 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 2527 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2528 // CHECK5-NEXT: store ptr null, ptr [[TMP6]], align 8 2529 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2530 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8 2531 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2532 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 8 2533 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2534 // CHECK5-NEXT: store ptr null, ptr [[TMP9]], align 8 2535 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2536 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 8 2537 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2538 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP11]], align 8 2539 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2540 // CHECK5-NEXT: store ptr null, ptr [[TMP12]], align 8 2541 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2542 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 8 2543 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2544 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 8 2545 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 2546 // CHECK5-NEXT: store ptr null, ptr [[TMP15]], align 8 2547 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2548 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2549 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2550 // CHECK5-NEXT: store i32 3, ptr [[TMP18]], align 4 2551 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2552 // CHECK5-NEXT: store i32 4, ptr [[TMP19]], align 4 2553 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2554 // CHECK5-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 8 2555 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2556 // CHECK5-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 8 2557 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2558 // CHECK5-NEXT: store ptr @.offload_sizes.3, ptr [[TMP22]], align 8 2559 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2560 // CHECK5-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP23]], align 8 2561 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 2562 // CHECK5-NEXT: store ptr null, ptr [[TMP24]], align 8 2563 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 2564 // CHECK5-NEXT: store ptr null, ptr [[TMP25]], align 8 2565 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 2566 // CHECK5-NEXT: store i64 16908289, ptr [[TMP26]], align 8 2567 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 2568 // CHECK5-NEXT: store i64 0, ptr [[TMP27]], align 8 2569 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 2570 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 2571 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 2572 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4 2573 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 2574 // CHECK5-NEXT: store i32 0, ptr [[TMP30]], align 4 2575 // CHECK5-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, ptr [[KERNEL_ARGS]]) 2576 // CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 2577 // CHECK5-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2578 // CHECK5: omp_offload.failed: 2579 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]] 2580 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 2581 // CHECK5: omp_offload.cont: 2582 // CHECK5-NEXT: ret void 2583 // 2584 // 2585 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 2586 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] { 2587 // CHECK5-NEXT: entry: 2588 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 2589 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 2590 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 2591 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 2592 // CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 2593 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 2594 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 2595 // CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 2596 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 2597 // CHECK5-NEXT: ret void 2598 // 2599 // 2600 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined 2601 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 2602 // CHECK5-NEXT: entry: 2603 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2604 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2605 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 2606 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 2607 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 2608 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 2609 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2610 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2611 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2612 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2613 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2614 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2615 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2616 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2617 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2618 // CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 2619 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 2620 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 2621 // CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 2622 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 2623 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 2624 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 2625 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 2626 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2627 // CHECK5-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4 2628 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2629 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2630 // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2631 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 2632 // CHECK5-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5) 2633 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2634 // CHECK5: omp.dispatch.cond: 2635 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2636 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 2637 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2638 // CHECK5: cond.true: 2639 // CHECK5-NEXT: br label [[COND_END:%.*]] 2640 // CHECK5: cond.false: 2641 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2642 // CHECK5-NEXT: br label [[COND_END]] 2643 // CHECK5: cond.end: 2644 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2645 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2646 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2647 // CHECK5-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 2648 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2649 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2650 // CHECK5-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 2651 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2652 // CHECK5: omp.dispatch.body: 2653 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2654 // CHECK5: omp.inner.for.cond: 2655 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] 2656 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] 2657 // CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 2658 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2659 // CHECK5: omp.inner.for.body: 2660 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 2661 // CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 2662 // CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 2663 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 2664 // CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP18]] 2665 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 2666 // CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 2667 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[IDXPROM]] 2668 // CHECK5-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] 2669 // CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP18]] 2670 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 2671 // CHECK5-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 2672 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[IDXPROM3]] 2673 // CHECK5-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP18]] 2674 // CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 2675 // CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP18]] 2676 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 2677 // CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 2678 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[IDXPROM6]] 2679 // CHECK5-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP18]] 2680 // CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 2681 // CHECK5-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP18]] 2682 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 2683 // CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 2684 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP23]], i64 [[IDXPROM9]] 2685 // CHECK5-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP18]] 2686 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2687 // CHECK5: omp.body.continue: 2688 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2689 // CHECK5: omp.inner.for.inc: 2690 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 2691 // CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 2692 // CHECK5-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 2693 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 2694 // CHECK5: omp.inner.for.end: 2695 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2696 // CHECK5: omp.dispatch.inc: 2697 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2698 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2699 // CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 2700 // CHECK5-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 4 2701 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2702 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2703 // CHECK5-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 2704 // CHECK5-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 4 2705 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] 2706 // CHECK5: omp.dispatch.end: 2707 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 2708 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2709 // CHECK5-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 2710 // CHECK5-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2711 // CHECK5: .omp.final.then: 2712 // CHECK5-NEXT: store i32 -2147483522, ptr [[I]], align 4 2713 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2714 // CHECK5: .omp.final.done: 2715 // CHECK5-NEXT: ret void 2716 // 2717 // 2718 // CHECK5-LABEL: define {{[^@]+}}@_Z12test_precondv 2719 // CHECK5-SAME: () #[[ATTR0]] { 2720 // CHECK5-NEXT: entry: 2721 // CHECK5-NEXT: [[A:%.*]] = alloca i8, align 1 2722 // CHECK5-NEXT: [[I:%.*]] = alloca i8, align 1 2723 // CHECK5-NEXT: [[I_CASTED:%.*]] = alloca i64, align 8 2724 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2725 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8 2726 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8 2727 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8 2728 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1 2729 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2730 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2731 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2732 // CHECK5-NEXT: store i8 0, ptr [[A]], align 1 2733 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, ptr [[I]], align 1 2734 // CHECK5-NEXT: store i8 [[TMP0]], ptr [[I_CASTED]], align 1 2735 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[I_CASTED]], align 8 2736 // CHECK5-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 2737 // CHECK5-NEXT: store i8 [[TMP2]], ptr [[A_CASTED]], align 1 2738 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 8 2739 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2740 // CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP4]], align 8 2741 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2742 // CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 2743 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2744 // CHECK5-NEXT: store ptr null, ptr [[TMP6]], align 8 2745 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2746 // CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP7]], align 8 2747 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2748 // CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 8 2749 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2750 // CHECK5-NEXT: store ptr null, ptr [[TMP9]], align 8 2751 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2752 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2753 // CHECK5-NEXT: [[TMP12:%.*]] = load i8, ptr [[A]], align 1 2754 // CHECK5-NEXT: store i8 [[TMP12]], ptr [[DOTCAPTURE_EXPR_]], align 1 2755 // CHECK5-NEXT: [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 2756 // CHECK5-NEXT: [[CONV:%.*]] = sext i8 [[TMP13]] to i32 2757 // CHECK5-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 2758 // CHECK5-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 2759 // CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 2760 // CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2761 // CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 2762 // CHECK5-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 2763 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 2764 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1 2765 // CHECK5-NEXT: [[TMP15:%.*]] = zext i32 [[ADD4]] to i64 2766 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2767 // CHECK5-NEXT: store i32 3, ptr [[TMP16]], align 4 2768 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2769 // CHECK5-NEXT: store i32 2, ptr [[TMP17]], align 4 2770 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2771 // CHECK5-NEXT: store ptr [[TMP10]], ptr [[TMP18]], align 8 2772 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2773 // CHECK5-NEXT: store ptr [[TMP11]], ptr [[TMP19]], align 8 2774 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2775 // CHECK5-NEXT: store ptr @.offload_sizes.5, ptr [[TMP20]], align 8 2776 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2777 // CHECK5-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP21]], align 8 2778 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 2779 // CHECK5-NEXT: store ptr null, ptr [[TMP22]], align 8 2780 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 2781 // CHECK5-NEXT: store ptr null, ptr [[TMP23]], align 8 2782 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 2783 // CHECK5-NEXT: store i64 [[TMP15]], ptr [[TMP24]], align 8 2784 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 2785 // CHECK5-NEXT: store i64 0, ptr [[TMP25]], align 8 2786 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 2787 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 2788 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 2789 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4 2790 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 2791 // CHECK5-NEXT: store i32 0, ptr [[TMP28]], align 4 2792 // CHECK5-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, ptr [[KERNEL_ARGS]]) 2793 // CHECK5-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 2794 // CHECK5-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2795 // CHECK5: omp_offload.failed: 2796 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i64 [[TMP1]], i64 [[TMP3]]) #[[ATTR3]] 2797 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 2798 // CHECK5: omp_offload.cont: 2799 // CHECK5-NEXT: ret void 2800 // 2801 // 2802 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 2803 // CHECK5-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 2804 // CHECK5-NEXT: entry: 2805 // CHECK5-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 2806 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2807 // CHECK5-NEXT: store i64 [[I]], ptr [[I_ADDR]], align 8 2808 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 2809 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]]) 2810 // CHECK5-NEXT: ret void 2811 // 2812 // 2813 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined 2814 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 2815 // CHECK5-NEXT: entry: 2816 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2817 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2818 // CHECK5-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8 2819 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 2820 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2821 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1 2822 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2823 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2824 // CHECK5-NEXT: [[I4:%.*]] = alloca i8, align 1 2825 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2826 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2827 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2828 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2829 // CHECK5-NEXT: [[I6:%.*]] = alloca i8, align 1 2830 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2831 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2832 // CHECK5-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 8 2833 // CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 2834 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8 2835 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 2836 // CHECK5-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1 2837 // CHECK5-NEXT: store i8 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 1 2838 // CHECK5-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 2839 // CHECK5-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 2840 // CHECK5-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 2841 // CHECK5-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 2842 // CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 2843 // CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2844 // CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 2845 // CHECK5-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 2846 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 2847 // CHECK5-NEXT: store i8 [[TMP4]], ptr [[I4]], align 1 2848 // CHECK5-NEXT: [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 2849 // CHECK5-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 2850 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 2851 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 2852 // CHECK5: omp.precond.then: 2853 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2854 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 2855 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4 2856 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2857 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2858 // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2859 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 2860 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2861 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2862 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 2863 // CHECK5-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] 2864 // CHECK5-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2865 // CHECK5: cond.true: 2866 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 2867 // CHECK5-NEXT: br label [[COND_END:%.*]] 2868 // CHECK5: cond.false: 2869 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2870 // CHECK5-NEXT: br label [[COND_END]] 2871 // CHECK5: cond.end: 2872 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 2873 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2874 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2875 // CHECK5-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 2876 // CHECK5-NEXT: [[TMP14:%.*]] = load i8, ptr [[TMP1]], align 1 2877 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0 2878 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2879 // CHECK5: omp_if.then: 2880 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2881 // CHECK5: omp.inner.for.cond: 2882 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] 2883 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] 2884 // CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 2885 // CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2886 // CHECK5: omp.inner.for.body: 2887 // CHECK5-NEXT: [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP21]] 2888 // CHECK5-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32 2889 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 2890 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 2891 // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 2892 // CHECK5-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 2893 // CHECK5-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal [[META15]], !llvm.access.group [[ACC_GRP21]] 2894 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2895 // CHECK5: omp.body.continue: 2896 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2897 // CHECK5: omp.inner.for.inc: 2898 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 2899 // CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 2900 // CHECK5-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 2901 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 2902 // CHECK5: omp.inner.for.end: 2903 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 2904 // CHECK5: omp_if.else: 2905 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 2906 // CHECK5: omp.inner.for.cond13: 2907 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2908 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2909 // CHECK5-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] 2910 // CHECK5-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]] 2911 // CHECK5: omp.inner.for.body15: 2912 // CHECK5-NEXT: [[TMP22:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 2913 // CHECK5-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32 2914 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2915 // CHECK5-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1 2916 // CHECK5-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]] 2917 // CHECK5-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 2918 // CHECK5-NEXT: store i8 [[CONV19]], ptr [[I6]], align 1 2919 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]] 2920 // CHECK5: omp.body.continue20: 2921 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]] 2922 // CHECK5: omp.inner.for.inc21: 2923 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2924 // CHECK5-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1 2925 // CHECK5-NEXT: store i32 [[ADD22]], ptr [[DOTOMP_IV]], align 4 2926 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP24:![0-9]+]] 2927 // CHECK5: omp.inner.for.end23: 2928 // CHECK5-NEXT: br label [[OMP_IF_END]] 2929 // CHECK5: omp_if.end: 2930 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2931 // CHECK5: omp.loop.exit: 2932 // CHECK5-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2933 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 2934 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]]) 2935 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2936 // CHECK5-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 2937 // CHECK5-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2938 // CHECK5: .omp.final.then: 2939 // CHECK5-NEXT: [[TMP29:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 2940 // CHECK5-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32 2941 // CHECK5-NEXT: [[TMP30:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 2942 // CHECK5-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32 2943 // CHECK5-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]] 2944 // CHECK5-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1 2945 // CHECK5-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1 2946 // CHECK5-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1 2947 // CHECK5-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1 2948 // CHECK5-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]] 2949 // CHECK5-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8 2950 // CHECK5-NEXT: store i8 [[CONV32]], ptr [[TMP0]], align 1 2951 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2952 // CHECK5: .omp.final.done: 2953 // CHECK5-NEXT: br label [[OMP_PRECOND_END]] 2954 // CHECK5: omp.precond.end: 2955 // CHECK5-NEXT: ret void 2956 // 2957 // 2958 // CHECK5-LABEL: define {{[^@]+}}@_Z4fintv 2959 // CHECK5-SAME: () #[[ATTR0]] { 2960 // CHECK5-NEXT: entry: 2961 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() 2962 // CHECK5-NEXT: ret i32 [[CALL]] 2963 // 2964 // 2965 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 2966 // CHECK5-SAME: () #[[ATTR0]] comdat { 2967 // CHECK5-NEXT: entry: 2968 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 2969 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2970 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 2971 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 2972 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 2973 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2974 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2975 // CHECK5-NEXT: store i16 0, ptr [[AA]], align 2 2976 // CHECK5-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA]], align 2 2977 // CHECK5-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 2978 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 2979 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2980 // CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8 2981 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2982 // CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8 2983 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2984 // CHECK5-NEXT: store ptr null, ptr [[TMP4]], align 8 2985 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2986 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2987 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2988 // CHECK5-NEXT: store i32 3, ptr [[TMP7]], align 4 2989 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2990 // CHECK5-NEXT: store i32 1, ptr [[TMP8]], align 4 2991 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2992 // CHECK5-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8 2993 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2994 // CHECK5-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8 2995 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2996 // CHECK5-NEXT: store ptr @.offload_sizes.7, ptr [[TMP11]], align 8 2997 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2998 // CHECK5-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP12]], align 8 2999 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3000 // CHECK5-NEXT: store ptr null, ptr [[TMP13]], align 8 3001 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3002 // CHECK5-NEXT: store ptr null, ptr [[TMP14]], align 8 3003 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3004 // CHECK5-NEXT: store i64 100, ptr [[TMP15]], align 8 3005 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 3006 // CHECK5-NEXT: store i64 0, ptr [[TMP16]], align 8 3007 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 3008 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 3009 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 3010 // CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4 3011 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 3012 // CHECK5-NEXT: store i32 0, ptr [[TMP19]], align 4 3013 // CHECK5-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, ptr [[KERNEL_ARGS]]) 3014 // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 3015 // CHECK5-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3016 // CHECK5: omp_offload.failed: 3017 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i64 [[TMP1]]) #[[ATTR3]] 3018 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 3019 // CHECK5: omp_offload.cont: 3020 // CHECK5-NEXT: ret i32 0 3021 // 3022 // 3023 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 3024 // CHECK5-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR1]] { 3025 // CHECK5-NEXT: entry: 3026 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3027 // CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 3028 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]]) 3029 // CHECK5-NEXT: ret void 3030 // 3031 // 3032 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined 3033 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 3034 // CHECK5-NEXT: entry: 3035 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3036 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3037 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8 3038 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3039 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 3040 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3041 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3042 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3043 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3044 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3045 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3046 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3047 // CHECK5-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8 3048 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8 3049 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3050 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 3051 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3052 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3053 // CHECK5-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2 3054 // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 3055 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3056 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 3057 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 3058 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3059 // CHECK5: omp.dispatch.cond: 3060 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3061 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 3062 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3063 // CHECK5: cond.true: 3064 // CHECK5-NEXT: br label [[COND_END:%.*]] 3065 // CHECK5: cond.false: 3066 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3067 // CHECK5-NEXT: br label [[COND_END]] 3068 // CHECK5: cond.end: 3069 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 3070 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3071 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3072 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 3073 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3074 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3075 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 3076 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3077 // CHECK5: omp.dispatch.body: 3078 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3079 // CHECK5: omp.inner.for.cond: 3080 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] 3081 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] 3082 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 3083 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3084 // CHECK5: omp.inner.for.body: 3085 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 3086 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 3087 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3088 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] 3089 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3090 // CHECK5: omp.body.continue: 3091 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3092 // CHECK5: omp.inner.for.inc: 3093 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 3094 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 3095 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 3096 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] 3097 // CHECK5: omp.inner.for.end: 3098 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3099 // CHECK5: omp.dispatch.inc: 3100 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3101 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 3102 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 3103 // CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4 3104 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3105 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 3106 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 3107 // CHECK5-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4 3108 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] 3109 // CHECK5: omp.dispatch.end: 3110 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 3111 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3112 // CHECK5-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 3113 // CHECK5-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3114 // CHECK5: .omp.final.then: 3115 // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 3116 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 3117 // CHECK5: .omp.final.done: 3118 // CHECK5-NEXT: ret void 3119 // 3120 // 3121 // CHECK7-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 3122 // CHECK7-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 3123 // CHECK7-NEXT: entry: 3124 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 3125 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3126 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3127 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 3128 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 3129 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 3130 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 3131 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 3132 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3133 // CHECK7-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 3134 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3135 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3136 // CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 3137 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 3138 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3139 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 3140 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 3141 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3142 // CHECK7-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 4 3143 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3144 // CHECK7-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 4 3145 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3146 // CHECK7-NEXT: store ptr null, ptr [[TMP6]], align 4 3147 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3148 // CHECK7-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 4 3149 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3150 // CHECK7-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 4 3151 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3152 // CHECK7-NEXT: store ptr null, ptr [[TMP9]], align 4 3153 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3154 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 4 3155 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3156 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP11]], align 4 3157 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3158 // CHECK7-NEXT: store ptr null, ptr [[TMP12]], align 4 3159 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3160 // CHECK7-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 4 3161 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3162 // CHECK7-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 4 3163 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3164 // CHECK7-NEXT: store ptr null, ptr [[TMP15]], align 4 3165 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3166 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3167 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3168 // CHECK7-NEXT: store i32 3, ptr [[TMP18]], align 4 3169 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3170 // CHECK7-NEXT: store i32 4, ptr [[TMP19]], align 4 3171 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3172 // CHECK7-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 4 3173 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3174 // CHECK7-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 4 3175 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3176 // CHECK7-NEXT: store ptr @.offload_sizes, ptr [[TMP22]], align 4 3177 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3178 // CHECK7-NEXT: store ptr @.offload_maptypes, ptr [[TMP23]], align 4 3179 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3180 // CHECK7-NEXT: store ptr null, ptr [[TMP24]], align 4 3181 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3182 // CHECK7-NEXT: store ptr null, ptr [[TMP25]], align 4 3183 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3184 // CHECK7-NEXT: store i64 4571424, ptr [[TMP26]], align 8 3185 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 3186 // CHECK7-NEXT: store i64 0, ptr [[TMP27]], align 8 3187 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 3188 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 3189 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 3190 // CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4 3191 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 3192 // CHECK7-NEXT: store i32 0, ptr [[TMP30]], align 4 3193 // CHECK7-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, ptr [[KERNEL_ARGS]]) 3194 // CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 3195 // CHECK7-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3196 // CHECK7: omp_offload.failed: 3197 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3:[0-9]+]] 3198 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 3199 // CHECK7: omp_offload.cont: 3200 // CHECK7-NEXT: ret void 3201 // 3202 // 3203 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 3204 // CHECK7-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { 3205 // CHECK7-NEXT: entry: 3206 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 3207 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3208 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3209 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 3210 // CHECK7-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 3211 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3212 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3213 // CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 3214 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 3215 // CHECK7-NEXT: ret void 3216 // 3217 // 3218 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined 3219 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 3220 // CHECK7-NEXT: entry: 3221 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3222 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3223 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 3224 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3225 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3226 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 3227 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3228 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 3229 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3230 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3231 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3232 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3233 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 3234 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3235 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3236 // CHECK7-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 3237 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3238 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3239 // CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 3240 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 3241 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3242 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 3243 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 3244 // CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP0]], align 4 3245 // CHECK7-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[TMP4]], i32 16) ] 3246 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3247 // CHECK7-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 3248 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3249 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3250 // CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3251 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 3252 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3253 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3254 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 3255 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3256 // CHECK7: cond.true: 3257 // CHECK7-NEXT: br label [[COND_END:%.*]] 3258 // CHECK7: cond.false: 3259 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3260 // CHECK7-NEXT: br label [[COND_END]] 3261 // CHECK7: cond.end: 3262 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 3263 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3264 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3265 // CHECK7-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 3266 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3267 // CHECK7: omp.inner.for.cond: 3268 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] 3269 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 3270 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 3271 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3272 // CHECK7: omp.inner.for.body: 3273 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 3274 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 3275 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 3276 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 3277 // CHECK7-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP9]] 3278 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 3279 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i32 [[TMP14]] 3280 // CHECK7-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] 3281 // CHECK7-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP9]] 3282 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 3283 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i32 [[TMP17]] 3284 // CHECK7-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP9]] 3285 // CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]] 3286 // CHECK7-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP9]] 3287 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 3288 // CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i32 [[TMP20]] 3289 // CHECK7-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP9]] 3290 // CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]] 3291 // CHECK7-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP9]] 3292 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 3293 // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i32 [[TMP23]] 3294 // CHECK7-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP9]] 3295 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3296 // CHECK7: omp.body.continue: 3297 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3298 // CHECK7: omp.inner.for.inc: 3299 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 3300 // CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1 3301 // CHECK7-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 3302 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 3303 // CHECK7: omp.inner.for.end: 3304 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3305 // CHECK7: omp.loop.exit: 3306 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP6]]) 3307 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3308 // CHECK7-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 3309 // CHECK7-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3310 // CHECK7: .omp.final.then: 3311 // CHECK7-NEXT: store i32 32000001, ptr [[I]], align 4 3312 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 3313 // CHECK7: .omp.final.done: 3314 // CHECK7-NEXT: ret void 3315 // 3316 // 3317 // CHECK7-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 3318 // CHECK7-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 3319 // CHECK7-NEXT: entry: 3320 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 3321 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3322 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3323 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 3324 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 3325 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 3326 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 3327 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 3328 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3329 // CHECK7-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 3330 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3331 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3332 // CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 3333 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 3334 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3335 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 3336 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 3337 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3338 // CHECK7-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 4 3339 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3340 // CHECK7-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 4 3341 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3342 // CHECK7-NEXT: store ptr null, ptr [[TMP6]], align 4 3343 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3344 // CHECK7-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 4 3345 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3346 // CHECK7-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 4 3347 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3348 // CHECK7-NEXT: store ptr null, ptr [[TMP9]], align 4 3349 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3350 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 4 3351 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3352 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP11]], align 4 3353 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3354 // CHECK7-NEXT: store ptr null, ptr [[TMP12]], align 4 3355 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3356 // CHECK7-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 4 3357 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3358 // CHECK7-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 4 3359 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3360 // CHECK7-NEXT: store ptr null, ptr [[TMP15]], align 4 3361 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3362 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3363 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3364 // CHECK7-NEXT: store i32 3, ptr [[TMP18]], align 4 3365 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3366 // CHECK7-NEXT: store i32 4, ptr [[TMP19]], align 4 3367 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3368 // CHECK7-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 4 3369 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3370 // CHECK7-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 4 3371 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3372 // CHECK7-NEXT: store ptr @.offload_sizes.1, ptr [[TMP22]], align 4 3373 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3374 // CHECK7-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP23]], align 4 3375 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3376 // CHECK7-NEXT: store ptr null, ptr [[TMP24]], align 4 3377 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3378 // CHECK7-NEXT: store ptr null, ptr [[TMP25]], align 4 3379 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3380 // CHECK7-NEXT: store i64 4571424, ptr [[TMP26]], align 8 3381 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 3382 // CHECK7-NEXT: store i64 0, ptr [[TMP27]], align 8 3383 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 3384 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 3385 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 3386 // CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4 3387 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 3388 // CHECK7-NEXT: store i32 0, ptr [[TMP30]], align 4 3389 // CHECK7-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, ptr [[KERNEL_ARGS]]) 3390 // CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 3391 // CHECK7-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3392 // CHECK7: omp_offload.failed: 3393 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]] 3394 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 3395 // CHECK7: omp_offload.cont: 3396 // CHECK7-NEXT: ret void 3397 // 3398 // 3399 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 3400 // CHECK7-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] { 3401 // CHECK7-NEXT: entry: 3402 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 3403 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3404 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3405 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 3406 // CHECK7-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 3407 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3408 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3409 // CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 3410 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 3411 // CHECK7-NEXT: ret void 3412 // 3413 // 3414 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined 3415 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 3416 // CHECK7-NEXT: entry: 3417 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3418 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3419 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 3420 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3421 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3422 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 3423 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3424 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 3425 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3426 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3427 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3428 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3429 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 3430 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3431 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3432 // CHECK7-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 3433 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3434 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3435 // CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 3436 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 3437 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3438 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 3439 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 3440 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3441 // CHECK7-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 3442 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3443 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3444 // CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3445 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 3446 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3447 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3448 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 3449 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3450 // CHECK7: cond.true: 3451 // CHECK7-NEXT: br label [[COND_END:%.*]] 3452 // CHECK7: cond.false: 3453 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3454 // CHECK7-NEXT: br label [[COND_END]] 3455 // CHECK7: cond.end: 3456 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3457 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3458 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3459 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 3460 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3461 // CHECK7: omp.inner.for.cond: 3462 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3463 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3464 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 3465 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3466 // CHECK7: omp.inner.for.body: 3467 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3468 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 3469 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 3470 // CHECK7-NEXT: store i32 [[SUB]], ptr [[I]], align 4 3471 // CHECK7-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 4, !nontemporal [[META16:![0-9]+]] 3472 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 3473 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 [[TMP13]] 3474 // CHECK7-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4 3475 // CHECK7-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 4 3476 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 3477 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i32 [[TMP16]] 3478 // CHECK7-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX2]], align 4 3479 // CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 3480 // CHECK7-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 4 3481 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 3482 // CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i32 [[TMP19]] 3483 // CHECK7-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX4]], align 4 3484 // CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 3485 // CHECK7-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 4, !nontemporal [[META16]] 3486 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 3487 // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i32 [[TMP22]] 3488 // CHECK7-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4 3489 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3490 // CHECK7: omp.body.continue: 3491 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3492 // CHECK7: omp.inner.for.inc: 3493 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3494 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 3495 // CHECK7-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 3496 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] 3497 // CHECK7: omp.inner.for.end: 3498 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3499 // CHECK7: omp.loop.exit: 3500 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 3501 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3502 // CHECK7-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 3503 // CHECK7-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3504 // CHECK7: .omp.final.then: 3505 // CHECK7-NEXT: store i32 32, ptr [[I]], align 4 3506 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 3507 // CHECK7: .omp.final.done: 3508 // CHECK7-NEXT: ret void 3509 // 3510 // 3511 // CHECK7-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 3512 // CHECK7-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 3513 // CHECK7-NEXT: entry: 3514 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 3515 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3516 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3517 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 3518 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 3519 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 3520 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 3521 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 3522 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3523 // CHECK7-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 3524 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3525 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3526 // CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 3527 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 3528 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3529 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 3530 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 3531 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3532 // CHECK7-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 4 3533 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3534 // CHECK7-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 4 3535 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3536 // CHECK7-NEXT: store ptr null, ptr [[TMP6]], align 4 3537 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3538 // CHECK7-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 4 3539 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3540 // CHECK7-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 4 3541 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3542 // CHECK7-NEXT: store ptr null, ptr [[TMP9]], align 4 3543 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3544 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 4 3545 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3546 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP11]], align 4 3547 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3548 // CHECK7-NEXT: store ptr null, ptr [[TMP12]], align 4 3549 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3550 // CHECK7-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 4 3551 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3552 // CHECK7-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 4 3553 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3554 // CHECK7-NEXT: store ptr null, ptr [[TMP15]], align 4 3555 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3556 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3557 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3558 // CHECK7-NEXT: store i32 3, ptr [[TMP18]], align 4 3559 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3560 // CHECK7-NEXT: store i32 4, ptr [[TMP19]], align 4 3561 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3562 // CHECK7-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 4 3563 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3564 // CHECK7-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 4 3565 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3566 // CHECK7-NEXT: store ptr @.offload_sizes.3, ptr [[TMP22]], align 4 3567 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3568 // CHECK7-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP23]], align 4 3569 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3570 // CHECK7-NEXT: store ptr null, ptr [[TMP24]], align 4 3571 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3572 // CHECK7-NEXT: store ptr null, ptr [[TMP25]], align 4 3573 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3574 // CHECK7-NEXT: store i64 16908289, ptr [[TMP26]], align 8 3575 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 3576 // CHECK7-NEXT: store i64 0, ptr [[TMP27]], align 8 3577 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 3578 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 3579 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 3580 // CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4 3581 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 3582 // CHECK7-NEXT: store i32 0, ptr [[TMP30]], align 4 3583 // CHECK7-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, ptr [[KERNEL_ARGS]]) 3584 // CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 3585 // CHECK7-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3586 // CHECK7: omp_offload.failed: 3587 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]] 3588 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 3589 // CHECK7: omp_offload.cont: 3590 // CHECK7-NEXT: ret void 3591 // 3592 // 3593 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 3594 // CHECK7-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] { 3595 // CHECK7-NEXT: entry: 3596 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 3597 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3598 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3599 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 3600 // CHECK7-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 3601 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3602 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3603 // CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 3604 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 3605 // CHECK7-NEXT: ret void 3606 // 3607 // 3608 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined 3609 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 3610 // CHECK7-NEXT: entry: 3611 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3612 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3613 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 3614 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3615 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3616 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 3617 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3618 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 3619 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3620 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3621 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3622 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3623 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 3624 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3625 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3626 // CHECK7-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 3627 // CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3628 // CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3629 // CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 3630 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 3631 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3632 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 3633 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 3634 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3635 // CHECK7-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4 3636 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3637 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3638 // CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3639 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 3640 // CHECK7-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5) 3641 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3642 // CHECK7: omp.dispatch.cond: 3643 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3644 // CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 3645 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3646 // CHECK7: cond.true: 3647 // CHECK7-NEXT: br label [[COND_END:%.*]] 3648 // CHECK7: cond.false: 3649 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3650 // CHECK7-NEXT: br label [[COND_END]] 3651 // CHECK7: cond.end: 3652 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3653 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3654 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3655 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 3656 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3657 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3658 // CHECK7-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 3659 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3660 // CHECK7: omp.dispatch.body: 3661 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3662 // CHECK7: omp.inner.for.cond: 3663 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] 3664 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] 3665 // CHECK7-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 3666 // CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3667 // CHECK7: omp.inner.for.body: 3668 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] 3669 // CHECK7-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 3670 // CHECK7-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 3671 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 3672 // CHECK7-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP19]] 3673 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 3674 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i32 [[TMP15]] 3675 // CHECK7-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] 3676 // CHECK7-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP19]] 3677 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 3678 // CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i32 [[TMP18]] 3679 // CHECK7-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP19]] 3680 // CHECK7-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] 3681 // CHECK7-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP19]] 3682 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 3683 // CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i32 [[TMP21]] 3684 // CHECK7-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP19]] 3685 // CHECK7-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] 3686 // CHECK7-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP19]] 3687 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 3688 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP23]], i32 [[TMP24]] 3689 // CHECK7-NEXT: store float [[MUL6]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP19]] 3690 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3691 // CHECK7: omp.body.continue: 3692 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3693 // CHECK7: omp.inner.for.inc: 3694 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] 3695 // CHECK7-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 3696 // CHECK7-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] 3697 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 3698 // CHECK7: omp.inner.for.end: 3699 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3700 // CHECK7: omp.dispatch.inc: 3701 // CHECK7-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3702 // CHECK7-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 3703 // CHECK7-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] 3704 // CHECK7-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_LB]], align 4 3705 // CHECK7-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3706 // CHECK7-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 3707 // CHECK7-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] 3708 // CHECK7-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_UB]], align 4 3709 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] 3710 // CHECK7: omp.dispatch.end: 3711 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 3712 // CHECK7-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3713 // CHECK7-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 3714 // CHECK7-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3715 // CHECK7: .omp.final.then: 3716 // CHECK7-NEXT: store i32 -2147483522, ptr [[I]], align 4 3717 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 3718 // CHECK7: .omp.final.done: 3719 // CHECK7-NEXT: ret void 3720 // 3721 // 3722 // CHECK7-LABEL: define {{[^@]+}}@_Z12test_precondv 3723 // CHECK7-SAME: () #[[ATTR0]] { 3724 // CHECK7-NEXT: entry: 3725 // CHECK7-NEXT: [[A:%.*]] = alloca i8, align 1 3726 // CHECK7-NEXT: [[I:%.*]] = alloca i8, align 1 3727 // CHECK7-NEXT: [[I_CASTED:%.*]] = alloca i32, align 4 3728 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3729 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 4 3730 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 4 3731 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 4 3732 // CHECK7-NEXT: [[TMP:%.*]] = alloca i8, align 1 3733 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 3734 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3735 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3736 // CHECK7-NEXT: store i8 0, ptr [[A]], align 1 3737 // CHECK7-NEXT: [[TMP0:%.*]] = load i8, ptr [[I]], align 1 3738 // CHECK7-NEXT: store i8 [[TMP0]], ptr [[I_CASTED]], align 1 3739 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[I_CASTED]], align 4 3740 // CHECK7-NEXT: [[TMP2:%.*]] = load i8, ptr [[A]], align 1 3741 // CHECK7-NEXT: store i8 [[TMP2]], ptr [[A_CASTED]], align 1 3742 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 4 3743 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3744 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP4]], align 4 3745 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3746 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 3747 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3748 // CHECK7-NEXT: store ptr null, ptr [[TMP6]], align 4 3749 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3750 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP7]], align 4 3751 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3752 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 4 3753 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3754 // CHECK7-NEXT: store ptr null, ptr [[TMP9]], align 4 3755 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3756 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3757 // CHECK7-NEXT: [[TMP12:%.*]] = load i8, ptr [[A]], align 1 3758 // CHECK7-NEXT: store i8 [[TMP12]], ptr [[DOTCAPTURE_EXPR_]], align 1 3759 // CHECK7-NEXT: [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 3760 // CHECK7-NEXT: [[CONV:%.*]] = sext i8 [[TMP13]] to i32 3761 // CHECK7-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 3762 // CHECK7-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 3763 // CHECK7-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 3764 // CHECK7-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3765 // CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 3766 // CHECK7-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 3767 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 3768 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1 3769 // CHECK7-NEXT: [[TMP15:%.*]] = zext i32 [[ADD4]] to i64 3770 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3771 // CHECK7-NEXT: store i32 3, ptr [[TMP16]], align 4 3772 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3773 // CHECK7-NEXT: store i32 2, ptr [[TMP17]], align 4 3774 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3775 // CHECK7-NEXT: store ptr [[TMP10]], ptr [[TMP18]], align 4 3776 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3777 // CHECK7-NEXT: store ptr [[TMP11]], ptr [[TMP19]], align 4 3778 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3779 // CHECK7-NEXT: store ptr @.offload_sizes.5, ptr [[TMP20]], align 4 3780 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3781 // CHECK7-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP21]], align 4 3782 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3783 // CHECK7-NEXT: store ptr null, ptr [[TMP22]], align 4 3784 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3785 // CHECK7-NEXT: store ptr null, ptr [[TMP23]], align 4 3786 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3787 // CHECK7-NEXT: store i64 [[TMP15]], ptr [[TMP24]], align 8 3788 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 3789 // CHECK7-NEXT: store i64 0, ptr [[TMP25]], align 8 3790 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 3791 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 3792 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 3793 // CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4 3794 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 3795 // CHECK7-NEXT: store i32 0, ptr [[TMP28]], align 4 3796 // CHECK7-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, ptr [[KERNEL_ARGS]]) 3797 // CHECK7-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 3798 // CHECK7-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3799 // CHECK7: omp_offload.failed: 3800 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i32 [[TMP1]], i32 [[TMP3]]) #[[ATTR3]] 3801 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 3802 // CHECK7: omp_offload.cont: 3803 // CHECK7-NEXT: ret void 3804 // 3805 // 3806 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 3807 // CHECK7-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 3808 // CHECK7-NEXT: entry: 3809 // CHECK7-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 3810 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3811 // CHECK7-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 3812 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3813 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]]) 3814 // CHECK7-NEXT: ret void 3815 // 3816 // 3817 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined 3818 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 3819 // CHECK7-NEXT: entry: 3820 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3821 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3822 // CHECK7-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 4 3823 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 3824 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3825 // CHECK7-NEXT: [[TMP:%.*]] = alloca i8, align 1 3826 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 3827 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3828 // CHECK7-NEXT: [[I4:%.*]] = alloca i8, align 1 3829 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3830 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3831 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3832 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3833 // CHECK7-NEXT: [[I6:%.*]] = alloca i8, align 1 3834 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3835 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3836 // CHECK7-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 4 3837 // CHECK7-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 3838 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 4 3839 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4 3840 // CHECK7-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1 3841 // CHECK7-NEXT: store i8 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 1 3842 // CHECK7-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 3843 // CHECK7-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 3844 // CHECK7-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 3845 // CHECK7-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 3846 // CHECK7-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 3847 // CHECK7-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3848 // CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 3849 // CHECK7-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 3850 // CHECK7-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 3851 // CHECK7-NEXT: store i8 [[TMP4]], ptr [[I4]], align 1 3852 // CHECK7-NEXT: [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 3853 // CHECK7-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 3854 // CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 3855 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 3856 // CHECK7: omp.precond.then: 3857 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3858 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 3859 // CHECK7-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4 3860 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3861 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3862 // CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3863 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 3864 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3865 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3866 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 3867 // CHECK7-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] 3868 // CHECK7-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3869 // CHECK7: cond.true: 3870 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 3871 // CHECK7-NEXT: br label [[COND_END:%.*]] 3872 // CHECK7: cond.false: 3873 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3874 // CHECK7-NEXT: br label [[COND_END]] 3875 // CHECK7: cond.end: 3876 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 3877 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3878 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3879 // CHECK7-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 3880 // CHECK7-NEXT: [[TMP14:%.*]] = load i8, ptr [[TMP1]], align 1 3881 // CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0 3882 // CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3883 // CHECK7: omp_if.then: 3884 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3885 // CHECK7: omp.inner.for.cond: 3886 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]] 3887 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]] 3888 // CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 3889 // CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3890 // CHECK7: omp.inner.for.body: 3891 // CHECK7-NEXT: [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP22]] 3892 // CHECK7-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32 3893 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] 3894 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 3895 // CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 3896 // CHECK7-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 3897 // CHECK7-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal [[META16]], !llvm.access.group [[ACC_GRP22]] 3898 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3899 // CHECK7: omp.body.continue: 3900 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3901 // CHECK7: omp.inner.for.inc: 3902 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] 3903 // CHECK7-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 3904 // CHECK7-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] 3905 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] 3906 // CHECK7: omp.inner.for.end: 3907 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 3908 // CHECK7: omp_if.else: 3909 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 3910 // CHECK7: omp.inner.for.cond13: 3911 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3912 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3913 // CHECK7-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] 3914 // CHECK7-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]] 3915 // CHECK7: omp.inner.for.body15: 3916 // CHECK7-NEXT: [[TMP22:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 3917 // CHECK7-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32 3918 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3919 // CHECK7-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1 3920 // CHECK7-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]] 3921 // CHECK7-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 3922 // CHECK7-NEXT: store i8 [[CONV19]], ptr [[I6]], align 1 3923 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]] 3924 // CHECK7: omp.body.continue20: 3925 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]] 3926 // CHECK7: omp.inner.for.inc21: 3927 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3928 // CHECK7-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1 3929 // CHECK7-NEXT: store i32 [[ADD22]], ptr [[DOTOMP_IV]], align 4 3930 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP25:![0-9]+]] 3931 // CHECK7: omp.inner.for.end23: 3932 // CHECK7-NEXT: br label [[OMP_IF_END]] 3933 // CHECK7: omp_if.end: 3934 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3935 // CHECK7: omp.loop.exit: 3936 // CHECK7-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3937 // CHECK7-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 3938 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]]) 3939 // CHECK7-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 3940 // CHECK7-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 3941 // CHECK7-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3942 // CHECK7: .omp.final.then: 3943 // CHECK7-NEXT: [[TMP29:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 3944 // CHECK7-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32 3945 // CHECK7-NEXT: [[TMP30:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 3946 // CHECK7-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32 3947 // CHECK7-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]] 3948 // CHECK7-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1 3949 // CHECK7-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1 3950 // CHECK7-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1 3951 // CHECK7-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1 3952 // CHECK7-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]] 3953 // CHECK7-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8 3954 // CHECK7-NEXT: store i8 [[CONV32]], ptr [[TMP0]], align 1 3955 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 3956 // CHECK7: .omp.final.done: 3957 // CHECK7-NEXT: br label [[OMP_PRECOND_END]] 3958 // CHECK7: omp.precond.end: 3959 // CHECK7-NEXT: ret void 3960 // 3961 // 3962 // CHECK7-LABEL: define {{[^@]+}}@_Z4fintv 3963 // CHECK7-SAME: () #[[ATTR0]] { 3964 // CHECK7-NEXT: entry: 3965 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() 3966 // CHECK7-NEXT: ret i32 [[CALL]] 3967 // 3968 // 3969 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 3970 // CHECK7-SAME: () #[[ATTR0]] comdat { 3971 // CHECK7-NEXT: entry: 3972 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 3973 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3974 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 3975 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 3976 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 3977 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 3978 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3979 // CHECK7-NEXT: store i16 0, ptr [[AA]], align 2 3980 // CHECK7-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA]], align 2 3981 // CHECK7-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 3982 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3983 // CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3984 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4 3985 // CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3986 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4 3987 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3988 // CHECK7-NEXT: store ptr null, ptr [[TMP4]], align 4 3989 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3990 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3991 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3992 // CHECK7-NEXT: store i32 3, ptr [[TMP7]], align 4 3993 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3994 // CHECK7-NEXT: store i32 1, ptr [[TMP8]], align 4 3995 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3996 // CHECK7-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4 3997 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3998 // CHECK7-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4 3999 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 4000 // CHECK7-NEXT: store ptr @.offload_sizes.7, ptr [[TMP11]], align 4 4001 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 4002 // CHECK7-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP12]], align 4 4003 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 4004 // CHECK7-NEXT: store ptr null, ptr [[TMP13]], align 4 4005 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 4006 // CHECK7-NEXT: store ptr null, ptr [[TMP14]], align 4 4007 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 4008 // CHECK7-NEXT: store i64 100, ptr [[TMP15]], align 8 4009 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 4010 // CHECK7-NEXT: store i64 0, ptr [[TMP16]], align 8 4011 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 4012 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 4013 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 4014 // CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4 4015 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 4016 // CHECK7-NEXT: store i32 0, ptr [[TMP19]], align 4 4017 // CHECK7-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, ptr [[KERNEL_ARGS]]) 4018 // CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 4019 // CHECK7-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4020 // CHECK7: omp_offload.failed: 4021 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i32 [[TMP1]]) #[[ATTR3]] 4022 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 4023 // CHECK7: omp_offload.cont: 4024 // CHECK7-NEXT: ret i32 0 4025 // 4026 // 4027 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 4028 // CHECK7-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR1]] { 4029 // CHECK7-NEXT: entry: 4030 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4031 // CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4032 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]]) 4033 // CHECK7-NEXT: ret void 4034 // 4035 // 4036 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined 4037 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 4038 // CHECK7-NEXT: entry: 4039 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4040 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4041 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4 4042 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4043 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 4044 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4045 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4046 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4047 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4048 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 4049 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4050 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4051 // CHECK7-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4 4052 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4 4053 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4054 // CHECK7-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 4055 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4056 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4057 // CHECK7-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2 4058 // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 4059 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 4060 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 4061 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 4062 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4063 // CHECK7: omp.dispatch.cond: 4064 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4065 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 4066 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4067 // CHECK7: cond.true: 4068 // CHECK7-NEXT: br label [[COND_END:%.*]] 4069 // CHECK7: cond.false: 4070 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4071 // CHECK7-NEXT: br label [[COND_END]] 4072 // CHECK7: cond.end: 4073 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 4074 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4075 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4076 // CHECK7-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 4077 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4078 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4079 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 4080 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4081 // CHECK7: omp.dispatch.body: 4082 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4083 // CHECK7: omp.inner.for.cond: 4084 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] 4085 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] 4086 // CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 4087 // CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4088 // CHECK7: omp.inner.for.body: 4089 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 4090 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 4091 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4092 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] 4093 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4094 // CHECK7: omp.body.continue: 4095 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4096 // CHECK7: omp.inner.for.inc: 4097 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 4098 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 4099 // CHECK7-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 4100 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 4101 // CHECK7: omp.inner.for.end: 4102 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4103 // CHECK7: omp.dispatch.inc: 4104 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4105 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 4106 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 4107 // CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4 4108 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4109 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 4110 // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 4111 // CHECK7-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4 4112 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] 4113 // CHECK7: omp.dispatch.end: 4114 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 4115 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 4116 // CHECK7-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 4117 // CHECK7-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4118 // CHECK7: .omp.final.then: 4119 // CHECK7-NEXT: store i32 100, ptr [[I]], align 4 4120 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 4121 // CHECK7: .omp.final.done: 4122 // CHECK7-NEXT: ret void 4123 // 4124 // 4125 // CHECK9-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 4126 // CHECK9-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 4127 // CHECK9-NEXT: entry: 4128 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 4129 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4130 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4131 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 4132 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 4133 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4134 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4135 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4136 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 4137 // CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 4138 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4139 // CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4140 // CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 4141 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4142 // CHECK9-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 4143 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4144 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 4145 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 4146 // CHECK9-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[TMP1]], i64 16) ] 4147 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4148 // CHECK9: omp.inner.for.cond: 4149 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 4150 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 4151 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 4152 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4153 // CHECK9: omp.inner.for.body: 4154 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 4155 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 4156 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 4157 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 4158 // CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !llvm.access.group [[ACC_GRP2]] 4159 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 4160 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 4161 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i64 [[IDXPROM]] 4162 // CHECK9-NEXT: [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] 4163 // CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !llvm.access.group [[ACC_GRP2]] 4164 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 4165 // CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 4166 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i64 [[IDXPROM1]] 4167 // CHECK9-NEXT: [[TMP10:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP2]] 4168 // CHECK9-NEXT: [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]] 4169 // CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !llvm.access.group [[ACC_GRP2]] 4170 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 4171 // CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 4172 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[IDXPROM4]] 4173 // CHECK9-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP2]] 4174 // CHECK9-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]] 4175 // CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !llvm.access.group [[ACC_GRP2]] 4176 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 4177 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64 4178 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM7]] 4179 // CHECK9-NEXT: store float [[MUL6]], ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP2]] 4180 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4181 // CHECK9: omp.body.continue: 4182 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4183 // CHECK9: omp.inner.for.inc: 4184 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 4185 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1 4186 // CHECK9-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 4187 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 4188 // CHECK9: omp.inner.for.end: 4189 // CHECK9-NEXT: store i32 32000001, ptr [[I]], align 4 4190 // CHECK9-NEXT: ret void 4191 // 4192 // 4193 // CHECK9-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 4194 // CHECK9-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 4195 // CHECK9-NEXT: entry: 4196 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 4197 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4198 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4199 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 4200 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 4201 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4202 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4203 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4204 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 4205 // CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 4206 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4207 // CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4208 // CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 4209 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4210 // CHECK9-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 4211 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4212 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 4213 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4214 // CHECK9: omp.inner.for.cond: 4215 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4216 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4217 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 4218 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4219 // CHECK9: omp.inner.for.body: 4220 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4221 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7 4222 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 4223 // CHECK9-NEXT: store i32 [[SUB]], ptr [[I]], align 4 4224 // CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 8 4225 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4 4226 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 4227 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 [[IDXPROM]] 4228 // CHECK9-NEXT: [[TMP6:%.*]] = load float, ptr [[ARRAYIDX]], align 4 4229 // CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4230 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4 4231 // CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 4232 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i64 [[IDXPROM1]] 4233 // CHECK9-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX2]], align 4 4234 // CHECK9-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]] 4235 // CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[D_ADDR]], align 8 4236 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 4237 // CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 4238 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP10]], i64 [[IDXPROM4]] 4239 // CHECK9-NEXT: [[TMP12:%.*]] = load float, ptr [[ARRAYIDX5]], align 4 4240 // CHECK9-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]] 4241 // CHECK9-NEXT: [[TMP13:%.*]] = load ptr, ptr [[A_ADDR]], align 8 4242 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 4243 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 4244 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM7]] 4245 // CHECK9-NEXT: store float [[MUL6]], ptr [[ARRAYIDX8]], align 4 4246 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4247 // CHECK9: omp.body.continue: 4248 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4249 // CHECK9: omp.inner.for.inc: 4250 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4251 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 4252 // CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 4253 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 4254 // CHECK9: omp.inner.for.end: 4255 // CHECK9-NEXT: store i32 32, ptr [[I]], align 4 4256 // CHECK9-NEXT: ret void 4257 // 4258 // 4259 // CHECK9-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 4260 // CHECK9-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 4261 // CHECK9-NEXT: entry: 4262 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 4263 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4264 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4265 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 4266 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 4267 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4268 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4269 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4270 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 4271 // CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 4272 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4273 // CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4274 // CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 4275 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4276 // CHECK9-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4 4277 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4278 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 4279 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4280 // CHECK9: omp.inner.for.cond: 4281 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] 4282 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 4283 // CHECK9-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]] 4284 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4285 // CHECK9: omp.inner.for.body: 4286 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 4287 // CHECK9-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127 4288 // CHECK9-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 4289 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 4290 // CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !llvm.access.group [[ACC_GRP9]] 4291 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 4292 // CHECK9-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64 4293 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP4]], i64 [[IDXPROM]] 4294 // CHECK9-NEXT: [[TMP6:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] 4295 // CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !llvm.access.group [[ACC_GRP9]] 4296 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 4297 // CHECK9-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64 4298 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP7]], i64 [[IDXPROM1]] 4299 // CHECK9-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP9]] 4300 // CHECK9-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]] 4301 // CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !llvm.access.group [[ACC_GRP9]] 4302 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 4303 // CHECK9-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64 4304 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds nuw float, ptr [[TMP10]], i64 [[IDXPROM4]] 4305 // CHECK9-NEXT: [[TMP12:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP9]] 4306 // CHECK9-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]] 4307 // CHECK9-NEXT: [[TMP13:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !llvm.access.group [[ACC_GRP9]] 4308 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 4309 // CHECK9-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64 4310 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw float, ptr [[TMP13]], i64 [[IDXPROM7]] 4311 // CHECK9-NEXT: store float [[MUL6]], ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP9]] 4312 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4313 // CHECK9: omp.body.continue: 4314 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4315 // CHECK9: omp.inner.for.inc: 4316 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 4317 // CHECK9-NEXT: [[ADD9:%.*]] = add i32 [[TMP15]], 1 4318 // CHECK9-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 4319 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 4320 // CHECK9: omp.inner.for.end: 4321 // CHECK9-NEXT: store i32 -2147483522, ptr [[I]], align 4 4322 // CHECK9-NEXT: ret void 4323 // 4324 // 4325 // CHECK9-LABEL: define {{[^@]+}}@_Z12test_precondv 4326 // CHECK9-SAME: () #[[ATTR0]] { 4327 // CHECK9-NEXT: entry: 4328 // CHECK9-NEXT: [[A:%.*]] = alloca i8, align 1 4329 // CHECK9-NEXT: [[I:%.*]] = alloca i8, align 1 4330 // CHECK9-NEXT: [[TMP:%.*]] = alloca i8, align 1 4331 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4332 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 4333 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4334 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4335 // CHECK9-NEXT: [[I4:%.*]] = alloca i8, align 1 4336 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4337 // CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1 4338 // CHECK9-NEXT: [[I6:%.*]] = alloca i8, align 1 4339 // CHECK9-NEXT: [[I7:%.*]] = alloca i8, align 1 4340 // CHECK9-NEXT: store i8 0, ptr [[A]], align 1 4341 // CHECK9-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 4342 // CHECK9-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 1 4343 // CHECK9-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4344 // CHECK9-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 4345 // CHECK9-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 4346 // CHECK9-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 4347 // CHECK9-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 4348 // CHECK9-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4349 // CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 4350 // CHECK9-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 4351 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4352 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 4353 // CHECK9-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 4354 // CHECK9-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4355 // CHECK9-NEXT: store i8 [[TMP3]], ptr [[I4]], align 1 4356 // CHECK9-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4357 // CHECK9-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 4358 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 4359 // CHECK9-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 4360 // CHECK9: simd.if.then: 4361 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4362 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 4363 // CHECK9-NEXT: [[TMP6:%.*]] = load i8, ptr [[I]], align 1 4364 // CHECK9-NEXT: store i8 [[TMP6]], ptr [[DOTLINEAR_START]], align 1 4365 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4366 // CHECK9: omp.inner.for.cond: 4367 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 4368 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] 4369 // CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 4370 // CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4371 // CHECK9: omp.inner.for.body: 4372 // CHECK9-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP12]] 4373 // CHECK9-NEXT: [[CONV9:%.*]] = sext i8 [[TMP9]] to i32 4374 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 4375 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 4376 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 4377 // CHECK9-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 4378 // CHECK9-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP12]] 4379 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4380 // CHECK9: omp.body.continue: 4381 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4382 // CHECK9: omp.inner.for.inc: 4383 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 4384 // CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1 4385 // CHECK9-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 4386 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 4387 // CHECK9: omp.inner.for.end: 4388 // CHECK9-NEXT: [[TMP12:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4389 // CHECK9-NEXT: [[CONV13:%.*]] = sext i8 [[TMP12]] to i32 4390 // CHECK9-NEXT: [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4391 // CHECK9-NEXT: [[CONV14:%.*]] = sext i8 [[TMP13]] to i32 4392 // CHECK9-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]] 4393 // CHECK9-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1 4394 // CHECK9-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1 4395 // CHECK9-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1 4396 // CHECK9-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1 4397 // CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]] 4398 // CHECK9-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 4399 // CHECK9-NEXT: store i8 [[CONV21]], ptr [[I]], align 1 4400 // CHECK9-NEXT: br label [[SIMD_IF_END]] 4401 // CHECK9: simd.if.end: 4402 // CHECK9-NEXT: ret void 4403 // 4404 // 4405 // CHECK9-LABEL: define {{[^@]+}}@_Z4fintv 4406 // CHECK9-SAME: () #[[ATTR0]] { 4407 // CHECK9-NEXT: entry: 4408 // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() 4409 // CHECK9-NEXT: ret i32 [[CALL]] 4410 // 4411 // 4412 // CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 4413 // CHECK9-SAME: () #[[ATTR0]] comdat { 4414 // CHECK9-NEXT: entry: 4415 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 4416 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 4417 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4418 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4419 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4420 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 4421 // CHECK9-NEXT: store i16 0, ptr [[AA]], align 2 4422 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4423 // CHECK9-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 4424 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4425 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 4426 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4427 // CHECK9: omp.inner.for.cond: 4428 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] 4429 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP15]] 4430 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 4431 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4432 // CHECK9: omp.inner.for.body: 4433 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 4434 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 4435 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4436 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] 4437 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4438 // CHECK9: omp.body.continue: 4439 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4440 // CHECK9: omp.inner.for.inc: 4441 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 4442 // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 4443 // CHECK9-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] 4444 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 4445 // CHECK9: omp.inner.for.end: 4446 // CHECK9-NEXT: store i32 100, ptr [[I]], align 4 4447 // CHECK9-NEXT: ret i32 0 4448 // 4449 // 4450 // CHECK11-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 4451 // CHECK11-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 4452 // CHECK11-NEXT: entry: 4453 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 4454 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 4455 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 4456 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 4457 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4458 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4459 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4460 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4461 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 4462 // CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 4463 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 4464 // CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 4465 // CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 4466 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4467 // CHECK11-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 4468 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4469 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 4470 // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4 4471 // CHECK11-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[TMP1]], i32 16) ] 4472 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4473 // CHECK11: omp.inner.for.cond: 4474 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 4475 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 4476 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 4477 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4478 // CHECK11: omp.inner.for.body: 4479 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 4480 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 4481 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 4482 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 4483 // CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP3]] 4484 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 4485 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i32 [[TMP6]] 4486 // CHECK11-NEXT: [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] 4487 // CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !llvm.access.group [[ACC_GRP3]] 4488 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 4489 // CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i32 [[TMP9]] 4490 // CHECK11-NEXT: [[TMP10:%.*]] = load float, ptr [[ARRAYIDX1]], align 4, !llvm.access.group [[ACC_GRP3]] 4491 // CHECK11-NEXT: [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]] 4492 // CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !llvm.access.group [[ACC_GRP3]] 4493 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 4494 // CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i32 [[TMP12]] 4495 // CHECK11-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP3]] 4496 // CHECK11-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]] 4497 // CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP3]] 4498 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 4499 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i32 [[TMP15]] 4500 // CHECK11-NEXT: store float [[MUL4]], ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP3]] 4501 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4502 // CHECK11: omp.body.continue: 4503 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4504 // CHECK11: omp.inner.for.inc: 4505 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 4506 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 4507 // CHECK11-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 4508 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 4509 // CHECK11: omp.inner.for.end: 4510 // CHECK11-NEXT: store i32 32000001, ptr [[I]], align 4 4511 // CHECK11-NEXT: ret void 4512 // 4513 // 4514 // CHECK11-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 4515 // CHECK11-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 4516 // CHECK11-NEXT: entry: 4517 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 4518 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 4519 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 4520 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 4521 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4522 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4523 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4524 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4525 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 4526 // CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 4527 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 4528 // CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 4529 // CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 4530 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4531 // CHECK11-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 4532 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4533 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 4534 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4535 // CHECK11: omp.inner.for.cond: 4536 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4537 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4538 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 4539 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4540 // CHECK11: omp.inner.for.body: 4541 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4542 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7 4543 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 4544 // CHECK11-NEXT: store i32 [[SUB]], ptr [[I]], align 4 4545 // CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 4 4546 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4 4547 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i32 [[TMP5]] 4548 // CHECK11-NEXT: [[TMP6:%.*]] = load float, ptr [[ARRAYIDX]], align 4 4549 // CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 4 4550 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4 4551 // CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i32 [[TMP8]] 4552 // CHECK11-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX1]], align 4 4553 // CHECK11-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]] 4554 // CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[D_ADDR]], align 4 4555 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 4556 // CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP10]], i32 [[TMP11]] 4557 // CHECK11-NEXT: [[TMP12:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 4558 // CHECK11-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]] 4559 // CHECK11-NEXT: [[TMP13:%.*]] = load ptr, ptr [[A_ADDR]], align 4 4560 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 4561 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i32 [[TMP14]] 4562 // CHECK11-NEXT: store float [[MUL4]], ptr [[ARRAYIDX5]], align 4 4563 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4564 // CHECK11: omp.body.continue: 4565 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4566 // CHECK11: omp.inner.for.inc: 4567 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4568 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 4569 // CHECK11-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 4570 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 4571 // CHECK11: omp.inner.for.end: 4572 // CHECK11-NEXT: store i32 32, ptr [[I]], align 4 4573 // CHECK11-NEXT: ret void 4574 // 4575 // 4576 // CHECK11-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 4577 // CHECK11-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 4578 // CHECK11-NEXT: entry: 4579 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 4580 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 4581 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 4582 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 4583 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4584 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4585 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4586 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4587 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 4588 // CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 4589 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 4590 // CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 4591 // CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 4592 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4593 // CHECK11-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4 4594 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4595 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 4596 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4597 // CHECK11: omp.inner.for.cond: 4598 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 4599 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 4600 // CHECK11-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]] 4601 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4602 // CHECK11: omp.inner.for.body: 4603 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 4604 // CHECK11-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127 4605 // CHECK11-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 4606 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 4607 // CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]] 4608 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 4609 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP4]], i32 [[TMP5]] 4610 // CHECK11-NEXT: [[TMP6:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] 4611 // CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]] 4612 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 4613 // CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw float, ptr [[TMP7]], i32 [[TMP8]] 4614 // CHECK11-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX1]], align 4, !llvm.access.group [[ACC_GRP10]] 4615 // CHECK11-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]] 4616 // CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]] 4617 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 4618 // CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw float, ptr [[TMP10]], i32 [[TMP11]] 4619 // CHECK11-NEXT: [[TMP12:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP10]] 4620 // CHECK11-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]] 4621 // CHECK11-NEXT: [[TMP13:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]] 4622 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 4623 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds nuw float, ptr [[TMP13]], i32 [[TMP14]] 4624 // CHECK11-NEXT: store float [[MUL4]], ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP10]] 4625 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4626 // CHECK11: omp.body.continue: 4627 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4628 // CHECK11: omp.inner.for.inc: 4629 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 4630 // CHECK11-NEXT: [[ADD6:%.*]] = add i32 [[TMP15]], 1 4631 // CHECK11-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 4632 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 4633 // CHECK11: omp.inner.for.end: 4634 // CHECK11-NEXT: store i32 -2147483522, ptr [[I]], align 4 4635 // CHECK11-NEXT: ret void 4636 // 4637 // 4638 // CHECK11-LABEL: define {{[^@]+}}@_Z12test_precondv 4639 // CHECK11-SAME: () #[[ATTR0]] { 4640 // CHECK11-NEXT: entry: 4641 // CHECK11-NEXT: [[A:%.*]] = alloca i8, align 1 4642 // CHECK11-NEXT: [[I:%.*]] = alloca i8, align 1 4643 // CHECK11-NEXT: [[TMP:%.*]] = alloca i8, align 1 4644 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4645 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 4646 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4647 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4648 // CHECK11-NEXT: [[I4:%.*]] = alloca i8, align 1 4649 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4650 // CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1 4651 // CHECK11-NEXT: [[I6:%.*]] = alloca i8, align 1 4652 // CHECK11-NEXT: [[I7:%.*]] = alloca i8, align 1 4653 // CHECK11-NEXT: store i8 0, ptr [[A]], align 1 4654 // CHECK11-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 4655 // CHECK11-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 1 4656 // CHECK11-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4657 // CHECK11-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 4658 // CHECK11-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 4659 // CHECK11-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 4660 // CHECK11-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 4661 // CHECK11-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4662 // CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 4663 // CHECK11-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 4664 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4665 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 4666 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 4667 // CHECK11-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4668 // CHECK11-NEXT: store i8 [[TMP3]], ptr [[I4]], align 1 4669 // CHECK11-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4670 // CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 4671 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 4672 // CHECK11-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 4673 // CHECK11: simd.if.then: 4674 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4675 // CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 4676 // CHECK11-NEXT: [[TMP6:%.*]] = load i8, ptr [[I]], align 1 4677 // CHECK11-NEXT: store i8 [[TMP6]], ptr [[DOTLINEAR_START]], align 1 4678 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4679 // CHECK11: omp.inner.for.cond: 4680 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] 4681 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] 4682 // CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 4683 // CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4684 // CHECK11: omp.inner.for.body: 4685 // CHECK11-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP13]] 4686 // CHECK11-NEXT: [[CONV9:%.*]] = sext i8 [[TMP9]] to i32 4687 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] 4688 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 4689 // CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 4690 // CHECK11-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 4691 // CHECK11-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP13]] 4692 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4693 // CHECK11: omp.body.continue: 4694 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4695 // CHECK11: omp.inner.for.inc: 4696 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] 4697 // CHECK11-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1 4698 // CHECK11-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] 4699 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 4700 // CHECK11: omp.inner.for.end: 4701 // CHECK11-NEXT: [[TMP12:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4702 // CHECK11-NEXT: [[CONV13:%.*]] = sext i8 [[TMP12]] to i32 4703 // CHECK11-NEXT: [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4704 // CHECK11-NEXT: [[CONV14:%.*]] = sext i8 [[TMP13]] to i32 4705 // CHECK11-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]] 4706 // CHECK11-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1 4707 // CHECK11-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1 4708 // CHECK11-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1 4709 // CHECK11-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1 4710 // CHECK11-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]] 4711 // CHECK11-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 4712 // CHECK11-NEXT: store i8 [[CONV21]], ptr [[I]], align 1 4713 // CHECK11-NEXT: br label [[SIMD_IF_END]] 4714 // CHECK11: simd.if.end: 4715 // CHECK11-NEXT: ret void 4716 // 4717 // 4718 // CHECK11-LABEL: define {{[^@]+}}@_Z4fintv 4719 // CHECK11-SAME: () #[[ATTR0]] { 4720 // CHECK11-NEXT: entry: 4721 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() 4722 // CHECK11-NEXT: ret i32 [[CALL]] 4723 // 4724 // 4725 // CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 4726 // CHECK11-SAME: () #[[ATTR0]] comdat { 4727 // CHECK11-NEXT: entry: 4728 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 4729 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4730 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4731 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4732 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4733 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 4734 // CHECK11-NEXT: store i16 0, ptr [[AA]], align 2 4735 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4736 // CHECK11-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 4737 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4738 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 4739 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4740 // CHECK11: omp.inner.for.cond: 4741 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] 4742 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]] 4743 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 4744 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4745 // CHECK11: omp.inner.for.body: 4746 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] 4747 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 4748 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4749 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]] 4750 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4751 // CHECK11: omp.body.continue: 4752 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4753 // CHECK11: omp.inner.for.inc: 4754 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] 4755 // CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 4756 // CHECK11-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] 4757 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] 4758 // CHECK11: omp.inner.for.end: 4759 // CHECK11-NEXT: store i32 100, ptr [[I]], align 4 4760 // CHECK11-NEXT: ret i32 0 4761 // 4762 // 4763 // CHECK13-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 4764 // CHECK13-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 4765 // CHECK13-NEXT: entry: 4766 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 4767 // CHECK13-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4768 // CHECK13-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4769 // CHECK13-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 4770 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 4771 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4772 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4773 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4774 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 4775 // CHECK13-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 4776 // CHECK13-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4777 // CHECK13-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4778 // CHECK13-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 4779 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4780 // CHECK13-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 4781 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4782 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 4783 // CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 4784 // CHECK13-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[TMP1]], i64 16) ] 4785 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4786 // CHECK13: omp.inner.for.cond: 4787 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 4788 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 4789 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 4790 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4791 // CHECK13: omp.inner.for.body: 4792 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 4793 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 4794 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 4795 // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 4796 // CHECK13-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !llvm.access.group [[ACC_GRP2]] 4797 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 4798 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 4799 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i64 [[IDXPROM]] 4800 // CHECK13-NEXT: [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] 4801 // CHECK13-NEXT: [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !llvm.access.group [[ACC_GRP2]] 4802 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 4803 // CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 4804 // CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i64 [[IDXPROM1]] 4805 // CHECK13-NEXT: [[TMP10:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP2]] 4806 // CHECK13-NEXT: [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]] 4807 // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !llvm.access.group [[ACC_GRP2]] 4808 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 4809 // CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 4810 // CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[IDXPROM4]] 4811 // CHECK13-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP2]] 4812 // CHECK13-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]] 4813 // CHECK13-NEXT: [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !llvm.access.group [[ACC_GRP2]] 4814 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 4815 // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64 4816 // CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM7]] 4817 // CHECK13-NEXT: store float [[MUL6]], ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP2]] 4818 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4819 // CHECK13: omp.body.continue: 4820 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4821 // CHECK13: omp.inner.for.inc: 4822 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 4823 // CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1 4824 // CHECK13-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 4825 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 4826 // CHECK13: omp.inner.for.end: 4827 // CHECK13-NEXT: store i32 32000001, ptr [[I]], align 4 4828 // CHECK13-NEXT: ret void 4829 // 4830 // 4831 // CHECK13-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 4832 // CHECK13-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 4833 // CHECK13-NEXT: entry: 4834 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 4835 // CHECK13-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4836 // CHECK13-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4837 // CHECK13-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 4838 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 4839 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4840 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4841 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4842 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 4843 // CHECK13-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 4844 // CHECK13-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4845 // CHECK13-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4846 // CHECK13-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 4847 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4848 // CHECK13-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 4849 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4850 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 4851 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4852 // CHECK13: omp.inner.for.cond: 4853 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4854 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4855 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 4856 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4857 // CHECK13: omp.inner.for.body: 4858 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4859 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7 4860 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 4861 // CHECK13-NEXT: store i32 [[SUB]], ptr [[I]], align 4 4862 // CHECK13-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nontemporal [[META7:![0-9]+]] 4863 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4 4864 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 4865 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 [[IDXPROM]] 4866 // CHECK13-NEXT: [[TMP6:%.*]] = load float, ptr [[ARRAYIDX]], align 4 4867 // CHECK13-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4868 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4 4869 // CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 4870 // CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i64 [[IDXPROM1]] 4871 // CHECK13-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX2]], align 4 4872 // CHECK13-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]] 4873 // CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[D_ADDR]], align 8 4874 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 4875 // CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 4876 // CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP10]], i64 [[IDXPROM4]] 4877 // CHECK13-NEXT: [[TMP12:%.*]] = load float, ptr [[ARRAYIDX5]], align 4 4878 // CHECK13-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]] 4879 // CHECK13-NEXT: [[TMP13:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nontemporal [[META7]] 4880 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 4881 // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 4882 // CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM7]] 4883 // CHECK13-NEXT: store float [[MUL6]], ptr [[ARRAYIDX8]], align 4 4884 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4885 // CHECK13: omp.body.continue: 4886 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4887 // CHECK13: omp.inner.for.inc: 4888 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4889 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 4890 // CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 4891 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 4892 // CHECK13: omp.inner.for.end: 4893 // CHECK13-NEXT: store i32 32, ptr [[I]], align 4 4894 // CHECK13-NEXT: ret void 4895 // 4896 // 4897 // CHECK13-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 4898 // CHECK13-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 4899 // CHECK13-NEXT: entry: 4900 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 4901 // CHECK13-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4902 // CHECK13-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4903 // CHECK13-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 4904 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 4905 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4906 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4907 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4908 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 4909 // CHECK13-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 4910 // CHECK13-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4911 // CHECK13-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4912 // CHECK13-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 4913 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4914 // CHECK13-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4 4915 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4916 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 4917 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4918 // CHECK13: omp.inner.for.cond: 4919 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 4920 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 4921 // CHECK13-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]] 4922 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4923 // CHECK13: omp.inner.for.body: 4924 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 4925 // CHECK13-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127 4926 // CHECK13-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 4927 // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 4928 // CHECK13-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !llvm.access.group [[ACC_GRP10]] 4929 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 4930 // CHECK13-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64 4931 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP4]], i64 [[IDXPROM]] 4932 // CHECK13-NEXT: [[TMP6:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] 4933 // CHECK13-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !llvm.access.group [[ACC_GRP10]] 4934 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 4935 // CHECK13-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64 4936 // CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP7]], i64 [[IDXPROM1]] 4937 // CHECK13-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP10]] 4938 // CHECK13-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]] 4939 // CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !llvm.access.group [[ACC_GRP10]] 4940 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 4941 // CHECK13-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64 4942 // CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds nuw float, ptr [[TMP10]], i64 [[IDXPROM4]] 4943 // CHECK13-NEXT: [[TMP12:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP10]] 4944 // CHECK13-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]] 4945 // CHECK13-NEXT: [[TMP13:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !llvm.access.group [[ACC_GRP10]] 4946 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 4947 // CHECK13-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64 4948 // CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw float, ptr [[TMP13]], i64 [[IDXPROM7]] 4949 // CHECK13-NEXT: store float [[MUL6]], ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP10]] 4950 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4951 // CHECK13: omp.body.continue: 4952 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4953 // CHECK13: omp.inner.for.inc: 4954 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 4955 // CHECK13-NEXT: [[ADD9:%.*]] = add i32 [[TMP15]], 1 4956 // CHECK13-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 4957 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 4958 // CHECK13: omp.inner.for.end: 4959 // CHECK13-NEXT: store i32 -2147483522, ptr [[I]], align 4 4960 // CHECK13-NEXT: ret void 4961 // 4962 // 4963 // CHECK13-LABEL: define {{[^@]+}}@_Z12test_precondv 4964 // CHECK13-SAME: () #[[ATTR0]] { 4965 // CHECK13-NEXT: entry: 4966 // CHECK13-NEXT: [[A:%.*]] = alloca i8, align 1 4967 // CHECK13-NEXT: [[I:%.*]] = alloca i8, align 1 4968 // CHECK13-NEXT: [[TMP:%.*]] = alloca i8, align 1 4969 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4970 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 4971 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4972 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4973 // CHECK13-NEXT: [[I4:%.*]] = alloca i8, align 1 4974 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4975 // CHECK13-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1 4976 // CHECK13-NEXT: [[I6:%.*]] = alloca i8, align 1 4977 // CHECK13-NEXT: [[I7:%.*]] = alloca i8, align 1 4978 // CHECK13-NEXT: store i8 0, ptr [[A]], align 1 4979 // CHECK13-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 4980 // CHECK13-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 1 4981 // CHECK13-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4982 // CHECK13-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 4983 // CHECK13-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 4984 // CHECK13-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 4985 // CHECK13-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 4986 // CHECK13-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4987 // CHECK13-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 4988 // CHECK13-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 4989 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4990 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 4991 // CHECK13-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 4992 // CHECK13-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4993 // CHECK13-NEXT: store i8 [[TMP3]], ptr [[I4]], align 1 4994 // CHECK13-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 4995 // CHECK13-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 4996 // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 4997 // CHECK13-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 4998 // CHECK13: simd.if.then: 4999 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5000 // CHECK13-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 5001 // CHECK13-NEXT: [[TMP6:%.*]] = load i8, ptr [[I]], align 1 5002 // CHECK13-NEXT: store i8 [[TMP6]], ptr [[DOTLINEAR_START]], align 1 5003 // CHECK13-NEXT: [[TMP7:%.*]] = load i8, ptr [[A]], align 1 5004 // CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0 5005 // CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5006 // CHECK13: omp_if.then: 5007 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5008 // CHECK13: omp.inner.for.cond: 5009 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] 5010 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] 5011 // CHECK13-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 5012 // CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5013 // CHECK13: omp.inner.for.body: 5014 // CHECK13-NEXT: [[TMP10:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP13]] 5015 // CHECK13-NEXT: [[CONV9:%.*]] = sext i8 [[TMP10]] to i32 5016 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] 5017 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 5018 // CHECK13-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 5019 // CHECK13-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 5020 // CHECK13-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal [[META7]], !llvm.access.group [[ACC_GRP13]] 5021 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5022 // CHECK13: omp.body.continue: 5023 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5024 // CHECK13: omp.inner.for.inc: 5025 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] 5026 // CHECK13-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1 5027 // CHECK13-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] 5028 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 5029 // CHECK13: omp.inner.for.end: 5030 // CHECK13-NEXT: br label [[OMP_IF_END:%.*]] 5031 // CHECK13: omp_if.else: 5032 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 5033 // CHECK13: omp.inner.for.cond13: 5034 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5035 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5036 // CHECK13-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 5037 // CHECK13-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]] 5038 // CHECK13: omp.inner.for.body15: 5039 // CHECK13-NEXT: [[TMP15:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 5040 // CHECK13-NEXT: [[CONV16:%.*]] = sext i8 [[TMP15]] to i32 5041 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5042 // CHECK13-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1 5043 // CHECK13-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]] 5044 // CHECK13-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 5045 // CHECK13-NEXT: store i8 [[CONV19]], ptr [[I6]], align 1 5046 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]] 5047 // CHECK13: omp.body.continue20: 5048 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]] 5049 // CHECK13: omp.inner.for.inc21: 5050 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5051 // CHECK13-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1 5052 // CHECK13-NEXT: store i32 [[ADD22]], ptr [[DOTOMP_IV]], align 4 5053 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP16:![0-9]+]] 5054 // CHECK13: omp.inner.for.end23: 5055 // CHECK13-NEXT: br label [[OMP_IF_END]] 5056 // CHECK13: omp_if.end: 5057 // CHECK13-NEXT: [[TMP18:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 5058 // CHECK13-NEXT: [[CONV24:%.*]] = sext i8 [[TMP18]] to i32 5059 // CHECK13-NEXT: [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 5060 // CHECK13-NEXT: [[CONV25:%.*]] = sext i8 [[TMP19]] to i32 5061 // CHECK13-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]] 5062 // CHECK13-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1 5063 // CHECK13-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1 5064 // CHECK13-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1 5065 // CHECK13-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1 5066 // CHECK13-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]] 5067 // CHECK13-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8 5068 // CHECK13-NEXT: store i8 [[CONV32]], ptr [[I]], align 1 5069 // CHECK13-NEXT: br label [[SIMD_IF_END]] 5070 // CHECK13: simd.if.end: 5071 // CHECK13-NEXT: ret void 5072 // 5073 // 5074 // CHECK13-LABEL: define {{[^@]+}}@_Z4fintv 5075 // CHECK13-SAME: () #[[ATTR0]] { 5076 // CHECK13-NEXT: entry: 5077 // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() 5078 // CHECK13-NEXT: ret i32 [[CALL]] 5079 // 5080 // 5081 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 5082 // CHECK13-SAME: () #[[ATTR0]] comdat { 5083 // CHECK13-NEXT: entry: 5084 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 5085 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 5086 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5087 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5088 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5089 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 5090 // CHECK13-NEXT: store i16 0, ptr [[AA]], align 2 5091 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5092 // CHECK13-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 5093 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5094 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 5095 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5096 // CHECK13: omp.inner.for.cond: 5097 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] 5098 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] 5099 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 5100 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5101 // CHECK13: omp.inner.for.body: 5102 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 5103 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 5104 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 5105 // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 5106 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5107 // CHECK13: omp.body.continue: 5108 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5109 // CHECK13: omp.inner.for.inc: 5110 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 5111 // CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 5112 // CHECK13-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 5113 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 5114 // CHECK13: omp.inner.for.end: 5115 // CHECK13-NEXT: store i32 100, ptr [[I]], align 4 5116 // CHECK13-NEXT: ret i32 0 5117 // 5118 // 5119 // CHECK15-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 5120 // CHECK15-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 5121 // CHECK15-NEXT: entry: 5122 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 5123 // CHECK15-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 5124 // CHECK15-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 5125 // CHECK15-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 5126 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 5127 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5128 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5129 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5130 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 5131 // CHECK15-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 5132 // CHECK15-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 5133 // CHECK15-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 5134 // CHECK15-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 5135 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5136 // CHECK15-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 5137 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5138 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 5139 // CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4 5140 // CHECK15-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[TMP1]], i32 16) ] 5141 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5142 // CHECK15: omp.inner.for.cond: 5143 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 5144 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 5145 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 5146 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5147 // CHECK15: omp.inner.for.body: 5148 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 5149 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 5150 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 5151 // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 5152 // CHECK15-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP3]] 5153 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 5154 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i32 [[TMP6]] 5155 // CHECK15-NEXT: [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] 5156 // CHECK15-NEXT: [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !llvm.access.group [[ACC_GRP3]] 5157 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 5158 // CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i32 [[TMP9]] 5159 // CHECK15-NEXT: [[TMP10:%.*]] = load float, ptr [[ARRAYIDX1]], align 4, !llvm.access.group [[ACC_GRP3]] 5160 // CHECK15-NEXT: [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]] 5161 // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !llvm.access.group [[ACC_GRP3]] 5162 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 5163 // CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i32 [[TMP12]] 5164 // CHECK15-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP3]] 5165 // CHECK15-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]] 5166 // CHECK15-NEXT: [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP3]] 5167 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 5168 // CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i32 [[TMP15]] 5169 // CHECK15-NEXT: store float [[MUL4]], ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP3]] 5170 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5171 // CHECK15: omp.body.continue: 5172 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5173 // CHECK15: omp.inner.for.inc: 5174 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 5175 // CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 5176 // CHECK15-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 5177 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 5178 // CHECK15: omp.inner.for.end: 5179 // CHECK15-NEXT: store i32 32000001, ptr [[I]], align 4 5180 // CHECK15-NEXT: ret void 5181 // 5182 // 5183 // CHECK15-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 5184 // CHECK15-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 5185 // CHECK15-NEXT: entry: 5186 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 5187 // CHECK15-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 5188 // CHECK15-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 5189 // CHECK15-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 5190 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 5191 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5192 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5193 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5194 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 5195 // CHECK15-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 5196 // CHECK15-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 5197 // CHECK15-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 5198 // CHECK15-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 5199 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5200 // CHECK15-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 5201 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5202 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 5203 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5204 // CHECK15: omp.inner.for.cond: 5205 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5206 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5207 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 5208 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5209 // CHECK15: omp.inner.for.body: 5210 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5211 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7 5212 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 5213 // CHECK15-NEXT: store i32 [[SUB]], ptr [[I]], align 4 5214 // CHECK15-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nontemporal [[META8:![0-9]+]] 5215 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4 5216 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i32 [[TMP5]] 5217 // CHECK15-NEXT: [[TMP6:%.*]] = load float, ptr [[ARRAYIDX]], align 4 5218 // CHECK15-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 4 5219 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4 5220 // CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i32 [[TMP8]] 5221 // CHECK15-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX1]], align 4 5222 // CHECK15-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]] 5223 // CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[D_ADDR]], align 4 5224 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 5225 // CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP10]], i32 [[TMP11]] 5226 // CHECK15-NEXT: [[TMP12:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 5227 // CHECK15-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]] 5228 // CHECK15-NEXT: [[TMP13:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nontemporal [[META8]] 5229 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 5230 // CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i32 [[TMP14]] 5231 // CHECK15-NEXT: store float [[MUL4]], ptr [[ARRAYIDX5]], align 4 5232 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5233 // CHECK15: omp.body.continue: 5234 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5235 // CHECK15: omp.inner.for.inc: 5236 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5237 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 5238 // CHECK15-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 5239 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 5240 // CHECK15: omp.inner.for.end: 5241 // CHECK15-NEXT: store i32 32, ptr [[I]], align 4 5242 // CHECK15-NEXT: ret void 5243 // 5244 // 5245 // CHECK15-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 5246 // CHECK15-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 5247 // CHECK15-NEXT: entry: 5248 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 5249 // CHECK15-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 5250 // CHECK15-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 5251 // CHECK15-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 5252 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 5253 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5254 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5255 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5256 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 5257 // CHECK15-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 5258 // CHECK15-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 5259 // CHECK15-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 5260 // CHECK15-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 5261 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5262 // CHECK15-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4 5263 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5264 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 5265 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5266 // CHECK15: omp.inner.for.cond: 5267 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 5268 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 5269 // CHECK15-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]] 5270 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5271 // CHECK15: omp.inner.for.body: 5272 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 5273 // CHECK15-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127 5274 // CHECK15-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 5275 // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 5276 // CHECK15-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP11]] 5277 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 5278 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP4]], i32 [[TMP5]] 5279 // CHECK15-NEXT: [[TMP6:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] 5280 // CHECK15-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !llvm.access.group [[ACC_GRP11]] 5281 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 5282 // CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw float, ptr [[TMP7]], i32 [[TMP8]] 5283 // CHECK15-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX1]], align 4, !llvm.access.group [[ACC_GRP11]] 5284 // CHECK15-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]] 5285 // CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !llvm.access.group [[ACC_GRP11]] 5286 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 5287 // CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw float, ptr [[TMP10]], i32 [[TMP11]] 5288 // CHECK15-NEXT: [[TMP12:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP11]] 5289 // CHECK15-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]] 5290 // CHECK15-NEXT: [[TMP13:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP11]] 5291 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 5292 // CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds nuw float, ptr [[TMP13]], i32 [[TMP14]] 5293 // CHECK15-NEXT: store float [[MUL4]], ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP11]] 5294 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5295 // CHECK15: omp.body.continue: 5296 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5297 // CHECK15: omp.inner.for.inc: 5298 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 5299 // CHECK15-NEXT: [[ADD6:%.*]] = add i32 [[TMP15]], 1 5300 // CHECK15-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 5301 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 5302 // CHECK15: omp.inner.for.end: 5303 // CHECK15-NEXT: store i32 -2147483522, ptr [[I]], align 4 5304 // CHECK15-NEXT: ret void 5305 // 5306 // 5307 // CHECK15-LABEL: define {{[^@]+}}@_Z12test_precondv 5308 // CHECK15-SAME: () #[[ATTR0]] { 5309 // CHECK15-NEXT: entry: 5310 // CHECK15-NEXT: [[A:%.*]] = alloca i8, align 1 5311 // CHECK15-NEXT: [[I:%.*]] = alloca i8, align 1 5312 // CHECK15-NEXT: [[TMP:%.*]] = alloca i8, align 1 5313 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 5314 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 5315 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5316 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5317 // CHECK15-NEXT: [[I4:%.*]] = alloca i8, align 1 5318 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5319 // CHECK15-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1 5320 // CHECK15-NEXT: [[I6:%.*]] = alloca i8, align 1 5321 // CHECK15-NEXT: [[I7:%.*]] = alloca i8, align 1 5322 // CHECK15-NEXT: store i8 0, ptr [[A]], align 1 5323 // CHECK15-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 5324 // CHECK15-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 1 5325 // CHECK15-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 5326 // CHECK15-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 5327 // CHECK15-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 5328 // CHECK15-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 5329 // CHECK15-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 5330 // CHECK15-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 5331 // CHECK15-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 5332 // CHECK15-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 5333 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5334 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 5335 // CHECK15-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 5336 // CHECK15-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 5337 // CHECK15-NEXT: store i8 [[TMP3]], ptr [[I4]], align 1 5338 // CHECK15-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 5339 // CHECK15-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 5340 // CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 5341 // CHECK15-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 5342 // CHECK15: simd.if.then: 5343 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5344 // CHECK15-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 5345 // CHECK15-NEXT: [[TMP6:%.*]] = load i8, ptr [[I]], align 1 5346 // CHECK15-NEXT: store i8 [[TMP6]], ptr [[DOTLINEAR_START]], align 1 5347 // CHECK15-NEXT: [[TMP7:%.*]] = load i8, ptr [[A]], align 1 5348 // CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0 5349 // CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5350 // CHECK15: omp_if.then: 5351 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5352 // CHECK15: omp.inner.for.cond: 5353 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]] 5354 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]] 5355 // CHECK15-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 5356 // CHECK15-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5357 // CHECK15: omp.inner.for.body: 5358 // CHECK15-NEXT: [[TMP10:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP14]] 5359 // CHECK15-NEXT: [[CONV9:%.*]] = sext i8 [[TMP10]] to i32 5360 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 5361 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 5362 // CHECK15-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 5363 // CHECK15-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 5364 // CHECK15-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal [[META8]], !llvm.access.group [[ACC_GRP14]] 5365 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5366 // CHECK15: omp.body.continue: 5367 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5368 // CHECK15: omp.inner.for.inc: 5369 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 5370 // CHECK15-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1 5371 // CHECK15-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 5372 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 5373 // CHECK15: omp.inner.for.end: 5374 // CHECK15-NEXT: br label [[OMP_IF_END:%.*]] 5375 // CHECK15: omp_if.else: 5376 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 5377 // CHECK15: omp.inner.for.cond13: 5378 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5379 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5380 // CHECK15-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 5381 // CHECK15-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]] 5382 // CHECK15: omp.inner.for.body15: 5383 // CHECK15-NEXT: [[TMP15:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 5384 // CHECK15-NEXT: [[CONV16:%.*]] = sext i8 [[TMP15]] to i32 5385 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5386 // CHECK15-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1 5387 // CHECK15-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]] 5388 // CHECK15-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 5389 // CHECK15-NEXT: store i8 [[CONV19]], ptr [[I6]], align 1 5390 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]] 5391 // CHECK15: omp.body.continue20: 5392 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]] 5393 // CHECK15: omp.inner.for.inc21: 5394 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5395 // CHECK15-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1 5396 // CHECK15-NEXT: store i32 [[ADD22]], ptr [[DOTOMP_IV]], align 4 5397 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP17:![0-9]+]] 5398 // CHECK15: omp.inner.for.end23: 5399 // CHECK15-NEXT: br label [[OMP_IF_END]] 5400 // CHECK15: omp_if.end: 5401 // CHECK15-NEXT: [[TMP18:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 5402 // CHECK15-NEXT: [[CONV24:%.*]] = sext i8 [[TMP18]] to i32 5403 // CHECK15-NEXT: [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 5404 // CHECK15-NEXT: [[CONV25:%.*]] = sext i8 [[TMP19]] to i32 5405 // CHECK15-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]] 5406 // CHECK15-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1 5407 // CHECK15-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1 5408 // CHECK15-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1 5409 // CHECK15-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1 5410 // CHECK15-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]] 5411 // CHECK15-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8 5412 // CHECK15-NEXT: store i8 [[CONV32]], ptr [[I]], align 1 5413 // CHECK15-NEXT: br label [[SIMD_IF_END]] 5414 // CHECK15: simd.if.end: 5415 // CHECK15-NEXT: ret void 5416 // 5417 // 5418 // CHECK15-LABEL: define {{[^@]+}}@_Z4fintv 5419 // CHECK15-SAME: () #[[ATTR0]] { 5420 // CHECK15-NEXT: entry: 5421 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() 5422 // CHECK15-NEXT: ret i32 [[CALL]] 5423 // 5424 // 5425 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 5426 // CHECK15-SAME: () #[[ATTR0]] comdat { 5427 // CHECK15-NEXT: entry: 5428 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 5429 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 5430 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5431 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5432 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5433 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 5434 // CHECK15-NEXT: store i16 0, ptr [[AA]], align 2 5435 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5436 // CHECK15-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 5437 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5438 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 5439 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5440 // CHECK15: omp.inner.for.cond: 5441 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] 5442 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] 5443 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 5444 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5445 // CHECK15: omp.inner.for.body: 5446 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] 5447 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 5448 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 5449 // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 5450 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5451 // CHECK15: omp.body.continue: 5452 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5453 // CHECK15: omp.inner.for.inc: 5454 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] 5455 // CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 5456 // CHECK15-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] 5457 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 5458 // CHECK15: omp.inner.for.end: 5459 // CHECK15-NEXT: store i32 100, ptr [[I]], align 4 5460 // CHECK15-NEXT: ret i32 0 5461 // 5462 // 5463 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 5464 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 5465 // CHECK17-NEXT: entry: 5466 // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 5467 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 5468 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 5469 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 5470 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 5471 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 5472 // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 5473 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 5474 // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 5475 // CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 5476 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 5477 // CHECK17-NEXT: ret void 5478 // 5479 // 5480 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined 5481 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 5482 // CHECK17-NEXT: entry: 5483 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 5484 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 5485 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 5486 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 5487 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 5488 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 5489 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5490 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 5491 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5492 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5493 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5494 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5495 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 5496 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 5497 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 5498 // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 5499 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 5500 // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 5501 // CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 5502 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 5503 // CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 5504 // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 5505 // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 5506 // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP0]], align 8 5507 // CHECK17-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[TMP4]], i64 16) ] 5508 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5509 // CHECK17-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 5510 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 5511 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5512 // CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 5513 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 5514 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 5515 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5516 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 5517 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5518 // CHECK17: cond.true: 5519 // CHECK17-NEXT: br label [[COND_END:%.*]] 5520 // CHECK17: cond.false: 5521 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5522 // CHECK17-NEXT: br label [[COND_END]] 5523 // CHECK17: cond.end: 5524 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 5525 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 5526 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5527 // CHECK17-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 5528 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5529 // CHECK17: omp.inner.for.cond: 5530 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] 5531 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 5532 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 5533 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5534 // CHECK17: omp.inner.for.body: 5535 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 5536 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 5537 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 5538 // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 5539 // CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP9]] 5540 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 5541 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 5542 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM]] 5543 // CHECK17-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] 5544 // CHECK17-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP9]] 5545 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 5546 // CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64 5547 // CHECK17-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM2]] 5548 // CHECK17-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP9]] 5549 // CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]] 5550 // CHECK17-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP9]] 5551 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 5552 // CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64 5553 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i64 [[IDXPROM5]] 5554 // CHECK17-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP9]] 5555 // CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]] 5556 // CHECK17-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP9]] 5557 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 5558 // CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64 5559 // CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[IDXPROM8]] 5560 // CHECK17-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP9]] 5561 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5562 // CHECK17: omp.body.continue: 5563 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5564 // CHECK17: omp.inner.for.inc: 5565 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 5566 // CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 5567 // CHECK17-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 5568 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 5569 // CHECK17: omp.inner.for.end: 5570 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5571 // CHECK17: omp.loop.exit: 5572 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP6]]) 5573 // CHECK17-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5574 // CHECK17-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 5575 // CHECK17-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5576 // CHECK17: .omp.final.then: 5577 // CHECK17-NEXT: store i32 32000001, ptr [[I]], align 4 5578 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 5579 // CHECK17: .omp.final.done: 5580 // CHECK17-NEXT: ret void 5581 // 5582 // 5583 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 5584 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 5585 // CHECK17-NEXT: entry: 5586 // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 5587 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 5588 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 5589 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 5590 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 5591 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 5592 // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 5593 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 5594 // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 5595 // CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 5596 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 5597 // CHECK17-NEXT: ret void 5598 // 5599 // 5600 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined 5601 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 5602 // CHECK17-NEXT: entry: 5603 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 5604 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 5605 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 5606 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 5607 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 5608 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 5609 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5610 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 5611 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5612 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5613 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5614 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5615 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 5616 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 5617 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 5618 // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 5619 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 5620 // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 5621 // CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 5622 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 5623 // CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 5624 // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 5625 // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 5626 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5627 // CHECK17-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 5628 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 5629 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5630 // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 5631 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 5632 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 5633 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5634 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 5635 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5636 // CHECK17: cond.true: 5637 // CHECK17-NEXT: br label [[COND_END:%.*]] 5638 // CHECK17: cond.false: 5639 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5640 // CHECK17-NEXT: br label [[COND_END]] 5641 // CHECK17: cond.end: 5642 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 5643 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 5644 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5645 // CHECK17-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 5646 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5647 // CHECK17: omp.inner.for.cond: 5648 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5649 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5650 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 5651 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5652 // CHECK17: omp.inner.for.body: 5653 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5654 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 5655 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 5656 // CHECK17-NEXT: store i32 [[SUB]], ptr [[I]], align 4 5657 // CHECK17-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8 5658 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 5659 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 5660 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]] 5661 // CHECK17-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4 5662 // CHECK17-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8 5663 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 5664 // CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 5665 // CHECK17-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]] 5666 // CHECK17-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 5667 // CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 5668 // CHECK17-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8 5669 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 5670 // CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 5671 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]] 5672 // CHECK17-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4 5673 // CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 5674 // CHECK17-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8 5675 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 5676 // CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 5677 // CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]] 5678 // CHECK17-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4 5679 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5680 // CHECK17: omp.body.continue: 5681 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5682 // CHECK17: omp.inner.for.inc: 5683 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5684 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 5685 // CHECK17-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 5686 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 5687 // CHECK17: omp.inner.for.end: 5688 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5689 // CHECK17: omp.loop.exit: 5690 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 5691 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5692 // CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 5693 // CHECK17-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5694 // CHECK17: .omp.final.then: 5695 // CHECK17-NEXT: store i32 32, ptr [[I]], align 4 5696 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 5697 // CHECK17: .omp.final.done: 5698 // CHECK17-NEXT: ret void 5699 // 5700 // 5701 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 5702 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 5703 // CHECK17-NEXT: entry: 5704 // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 5705 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 5706 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 5707 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 5708 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 5709 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 5710 // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 5711 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 5712 // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 5713 // CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 5714 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 5715 // CHECK17-NEXT: ret void 5716 // 5717 // 5718 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined 5719 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 5720 // CHECK17-NEXT: entry: 5721 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 5722 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 5723 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 5724 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 5725 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 5726 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 5727 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5728 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 5729 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5730 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5731 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5732 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5733 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 5734 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 5735 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 5736 // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 5737 // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 5738 // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 5739 // CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 5740 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 5741 // CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 5742 // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 5743 // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 5744 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5745 // CHECK17-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4 5746 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 5747 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5748 // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 5749 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 5750 // CHECK17-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5) 5751 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 5752 // CHECK17: omp.dispatch.cond: 5753 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5754 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 5755 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5756 // CHECK17: cond.true: 5757 // CHECK17-NEXT: br label [[COND_END:%.*]] 5758 // CHECK17: cond.false: 5759 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5760 // CHECK17-NEXT: br label [[COND_END]] 5761 // CHECK17: cond.end: 5762 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 5763 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 5764 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5765 // CHECK17-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 5766 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5767 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5768 // CHECK17-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 5769 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 5770 // CHECK17: omp.dispatch.body: 5771 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5772 // CHECK17: omp.inner.for.cond: 5773 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] 5774 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] 5775 // CHECK17-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 5776 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5777 // CHECK17: omp.inner.for.body: 5778 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 5779 // CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 5780 // CHECK17-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 5781 // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 5782 // CHECK17-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP18]] 5783 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 5784 // CHECK17-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 5785 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[IDXPROM]] 5786 // CHECK17-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] 5787 // CHECK17-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP18]] 5788 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 5789 // CHECK17-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 5790 // CHECK17-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[IDXPROM3]] 5791 // CHECK17-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP18]] 5792 // CHECK17-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 5793 // CHECK17-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP18]] 5794 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 5795 // CHECK17-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 5796 // CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[IDXPROM6]] 5797 // CHECK17-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP18]] 5798 // CHECK17-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 5799 // CHECK17-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP18]] 5800 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] 5801 // CHECK17-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 5802 // CHECK17-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP23]], i64 [[IDXPROM9]] 5803 // CHECK17-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP18]] 5804 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5805 // CHECK17: omp.body.continue: 5806 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5807 // CHECK17: omp.inner.for.inc: 5808 // CHECK17-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 5809 // CHECK17-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 5810 // CHECK17-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] 5811 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 5812 // CHECK17: omp.inner.for.end: 5813 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 5814 // CHECK17: omp.dispatch.inc: 5815 // CHECK17-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5816 // CHECK17-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 5817 // CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 5818 // CHECK17-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 4 5819 // CHECK17-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5820 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 5821 // CHECK17-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 5822 // CHECK17-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 4 5823 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 5824 // CHECK17: omp.dispatch.end: 5825 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 5826 // CHECK17-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5827 // CHECK17-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 5828 // CHECK17-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5829 // CHECK17: .omp.final.then: 5830 // CHECK17-NEXT: store i32 -2147483522, ptr [[I]], align 4 5831 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 5832 // CHECK17: .omp.final.done: 5833 // CHECK17-NEXT: ret void 5834 // 5835 // 5836 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 5837 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 5838 // CHECK17-NEXT: entry: 5839 // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 5840 // CHECK17-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 5841 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5842 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 5843 // CHECK17-NEXT: store i64 [[I]], ptr [[I_ADDR]], align 8 5844 // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 5845 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]]) 5846 // CHECK17-NEXT: ret void 5847 // 5848 // 5849 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined 5850 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { 5851 // CHECK17-NEXT: entry: 5852 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 5853 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 5854 // CHECK17-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8 5855 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 5856 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5857 // CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1 5858 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 5859 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 5860 // CHECK17-NEXT: [[I4:%.*]] = alloca i8, align 1 5861 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5862 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5863 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5864 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5865 // CHECK17-NEXT: [[I6:%.*]] = alloca i8, align 1 5866 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 5867 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 5868 // CHECK17-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 8 5869 // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 5870 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8 5871 // CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 5872 // CHECK17-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1 5873 // CHECK17-NEXT: store i8 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 1 5874 // CHECK17-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 5875 // CHECK17-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 5876 // CHECK17-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 5877 // CHECK17-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 5878 // CHECK17-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 5879 // CHECK17-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 5880 // CHECK17-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 5881 // CHECK17-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 5882 // CHECK17-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 5883 // CHECK17-NEXT: store i8 [[TMP4]], ptr [[I4]], align 1 5884 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 5885 // CHECK17-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 5886 // CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 5887 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 5888 // CHECK17: omp.precond.then: 5889 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5890 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 5891 // CHECK17-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4 5892 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 5893 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5894 // CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 5895 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 5896 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 5897 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5898 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 5899 // CHECK17-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] 5900 // CHECK17-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5901 // CHECK17: cond.true: 5902 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 5903 // CHECK17-NEXT: br label [[COND_END:%.*]] 5904 // CHECK17: cond.false: 5905 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5906 // CHECK17-NEXT: br label [[COND_END]] 5907 // CHECK17: cond.end: 5908 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 5909 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 5910 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5911 // CHECK17-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 5912 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5913 // CHECK17: omp.inner.for.cond: 5914 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] 5915 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] 5916 // CHECK17-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 5917 // CHECK17-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5918 // CHECK17: omp.inner.for.body: 5919 // CHECK17-NEXT: [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP21]] 5920 // CHECK17-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32 5921 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 5922 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 5923 // CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 5924 // CHECK17-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 5925 // CHECK17-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP21]] 5926 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5927 // CHECK17: omp.body.continue: 5928 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5929 // CHECK17: omp.inner.for.inc: 5930 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 5931 // CHECK17-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1 5932 // CHECK17-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 5933 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 5934 // CHECK17: omp.inner.for.end: 5935 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5936 // CHECK17: omp.loop.exit: 5937 // CHECK17-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 5938 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 5939 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) 5940 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 5941 // CHECK17-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 5942 // CHECK17-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5943 // CHECK17: .omp.final.then: 5944 // CHECK17-NEXT: [[TMP23:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 5945 // CHECK17-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32 5946 // CHECK17-NEXT: [[TMP24:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 5947 // CHECK17-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32 5948 // CHECK17-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]] 5949 // CHECK17-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1 5950 // CHECK17-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1 5951 // CHECK17-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1 5952 // CHECK17-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1 5953 // CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]] 5954 // CHECK17-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 5955 // CHECK17-NEXT: store i8 [[CONV21]], ptr [[TMP0]], align 1 5956 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 5957 // CHECK17: .omp.final.done: 5958 // CHECK17-NEXT: br label [[OMP_PRECOND_END]] 5959 // CHECK17: omp.precond.end: 5960 // CHECK17-NEXT: ret void 5961 // 5962 // 5963 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 5964 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 5965 // CHECK17-NEXT: entry: 5966 // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 5967 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5968 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 5969 // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 5970 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]]) 5971 // CHECK17-NEXT: ret void 5972 // 5973 // 5974 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined 5975 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { 5976 // CHECK17-NEXT: entry: 5977 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 5978 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 5979 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8 5980 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5981 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 5982 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5983 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5984 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5985 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5986 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 5987 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 5988 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 5989 // CHECK17-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8 5990 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8 5991 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5992 // CHECK17-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 5993 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 5994 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5995 // CHECK17-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2 5996 // CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 5997 // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 5998 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 5999 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 6000 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6001 // CHECK17: omp.dispatch.cond: 6002 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6003 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 6004 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6005 // CHECK17: cond.true: 6006 // CHECK17-NEXT: br label [[COND_END:%.*]] 6007 // CHECK17: cond.false: 6008 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6009 // CHECK17-NEXT: br label [[COND_END]] 6010 // CHECK17: cond.end: 6011 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 6012 // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 6013 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6014 // CHECK17-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 6015 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 6016 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6017 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 6018 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6019 // CHECK17: omp.dispatch.body: 6020 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6021 // CHECK17: omp.inner.for.cond: 6022 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] 6023 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]] 6024 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 6025 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6026 // CHECK17: omp.inner.for.body: 6027 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 6028 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 6029 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 6030 // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] 6031 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6032 // CHECK17: omp.body.continue: 6033 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6034 // CHECK17: omp.inner.for.inc: 6035 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 6036 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 6037 // CHECK17-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 6038 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 6039 // CHECK17: omp.inner.for.end: 6040 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6041 // CHECK17: omp.dispatch.inc: 6042 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6043 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 6044 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 6045 // CHECK17-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4 6046 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6047 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 6048 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 6049 // CHECK17-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4 6050 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 6051 // CHECK17: omp.dispatch.end: 6052 // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 6053 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 6054 // CHECK17-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 6055 // CHECK17-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6056 // CHECK17: .omp.final.then: 6057 // CHECK17-NEXT: store i32 100, ptr [[I]], align 4 6058 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 6059 // CHECK17: .omp.final.done: 6060 // CHECK17-NEXT: ret void 6061 // 6062 // 6063 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 6064 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 6065 // CHECK19-NEXT: entry: 6066 // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 6067 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 6068 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6069 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 6070 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 6071 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 6072 // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 6073 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6074 // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 6075 // CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 6076 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 6077 // CHECK19-NEXT: ret void 6078 // 6079 // 6080 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined 6081 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 6082 // CHECK19-NEXT: entry: 6083 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 6084 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 6085 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 6086 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6087 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 6088 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 6089 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6090 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 6091 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6092 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6093 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6094 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6095 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 6096 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 6097 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 6098 // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 6099 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6100 // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 6101 // CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 6102 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 6103 // CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 6104 // CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 6105 // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 6106 // CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP0]], align 4 6107 // CHECK19-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[TMP4]], i32 16) ] 6108 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 6109 // CHECK19-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 6110 // CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 6111 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 6112 // CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6113 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 6114 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 6115 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6116 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 6117 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6118 // CHECK19: cond.true: 6119 // CHECK19-NEXT: br label [[COND_END:%.*]] 6120 // CHECK19: cond.false: 6121 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6122 // CHECK19-NEXT: br label [[COND_END]] 6123 // CHECK19: cond.end: 6124 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 6125 // CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 6126 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6127 // CHECK19-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 6128 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6129 // CHECK19: omp.inner.for.cond: 6130 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 6131 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 6132 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 6133 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6134 // CHECK19: omp.inner.for.body: 6135 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 6136 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 6137 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 6138 // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 6139 // CHECK19-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP10]] 6140 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 6141 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i32 [[TMP14]] 6142 // CHECK19-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] 6143 // CHECK19-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP10]] 6144 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 6145 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i32 [[TMP17]] 6146 // CHECK19-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP10]] 6147 // CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]] 6148 // CHECK19-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP10]] 6149 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 6150 // CHECK19-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i32 [[TMP20]] 6151 // CHECK19-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP10]] 6152 // CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]] 6153 // CHECK19-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP10]] 6154 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 6155 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i32 [[TMP23]] 6156 // CHECK19-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP10]] 6157 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6158 // CHECK19: omp.body.continue: 6159 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6160 // CHECK19: omp.inner.for.inc: 6161 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 6162 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1 6163 // CHECK19-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 6164 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 6165 // CHECK19: omp.inner.for.end: 6166 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6167 // CHECK19: omp.loop.exit: 6168 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP6]]) 6169 // CHECK19-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 6170 // CHECK19-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 6171 // CHECK19-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6172 // CHECK19: .omp.final.then: 6173 // CHECK19-NEXT: store i32 32000001, ptr [[I]], align 4 6174 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 6175 // CHECK19: .omp.final.done: 6176 // CHECK19-NEXT: ret void 6177 // 6178 // 6179 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 6180 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 6181 // CHECK19-NEXT: entry: 6182 // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 6183 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 6184 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6185 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 6186 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 6187 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 6188 // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 6189 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6190 // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 6191 // CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 6192 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 6193 // CHECK19-NEXT: ret void 6194 // 6195 // 6196 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined 6197 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 6198 // CHECK19-NEXT: entry: 6199 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 6200 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 6201 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 6202 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6203 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 6204 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 6205 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6206 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 6207 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6208 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6209 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6210 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6211 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 6212 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 6213 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 6214 // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 6215 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6216 // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 6217 // CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 6218 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 6219 // CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 6220 // CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 6221 // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 6222 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 6223 // CHECK19-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 6224 // CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 6225 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 6226 // CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6227 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 6228 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 6229 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6230 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 6231 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6232 // CHECK19: cond.true: 6233 // CHECK19-NEXT: br label [[COND_END:%.*]] 6234 // CHECK19: cond.false: 6235 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6236 // CHECK19-NEXT: br label [[COND_END]] 6237 // CHECK19: cond.end: 6238 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 6239 // CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 6240 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6241 // CHECK19-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 6242 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6243 // CHECK19: omp.inner.for.cond: 6244 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 6245 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6246 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 6247 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6248 // CHECK19: omp.inner.for.body: 6249 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 6250 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 6251 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 6252 // CHECK19-NEXT: store i32 [[SUB]], ptr [[I]], align 4 6253 // CHECK19-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 4 6254 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 6255 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 [[TMP13]] 6256 // CHECK19-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4 6257 // CHECK19-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 4 6258 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 6259 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i32 [[TMP16]] 6260 // CHECK19-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX2]], align 4 6261 // CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 6262 // CHECK19-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 4 6263 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 6264 // CHECK19-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i32 [[TMP19]] 6265 // CHECK19-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX4]], align 4 6266 // CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 6267 // CHECK19-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 4 6268 // CHECK19-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 6269 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i32 [[TMP22]] 6270 // CHECK19-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4 6271 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6272 // CHECK19: omp.body.continue: 6273 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6274 // CHECK19: omp.inner.for.inc: 6275 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 6276 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 6277 // CHECK19-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 6278 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] 6279 // CHECK19: omp.inner.for.end: 6280 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6281 // CHECK19: omp.loop.exit: 6282 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 6283 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 6284 // CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 6285 // CHECK19-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6286 // CHECK19: .omp.final.then: 6287 // CHECK19-NEXT: store i32 32, ptr [[I]], align 4 6288 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 6289 // CHECK19: .omp.final.done: 6290 // CHECK19-NEXT: ret void 6291 // 6292 // 6293 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 6294 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 6295 // CHECK19-NEXT: entry: 6296 // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 6297 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 6298 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6299 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 6300 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 6301 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 6302 // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 6303 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6304 // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 6305 // CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 6306 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 6307 // CHECK19-NEXT: ret void 6308 // 6309 // 6310 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined 6311 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 6312 // CHECK19-NEXT: entry: 6313 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 6314 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 6315 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 6316 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 6317 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 6318 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 6319 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6320 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 6321 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6322 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6323 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6324 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6325 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 6326 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 6327 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 6328 // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 6329 // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 6330 // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 6331 // CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 6332 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 6333 // CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 6334 // CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 6335 // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 6336 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 6337 // CHECK19-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4 6338 // CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 6339 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 6340 // CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6341 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 6342 // CHECK19-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5) 6343 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6344 // CHECK19: omp.dispatch.cond: 6345 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6346 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 6347 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6348 // CHECK19: cond.true: 6349 // CHECK19-NEXT: br label [[COND_END:%.*]] 6350 // CHECK19: cond.false: 6351 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6352 // CHECK19-NEXT: br label [[COND_END]] 6353 // CHECK19: cond.end: 6354 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 6355 // CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 6356 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6357 // CHECK19-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 6358 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 6359 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6360 // CHECK19-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 6361 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6362 // CHECK19: omp.dispatch.body: 6363 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6364 // CHECK19: omp.inner.for.cond: 6365 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] 6366 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] 6367 // CHECK19-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 6368 // CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6369 // CHECK19: omp.inner.for.body: 6370 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] 6371 // CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 6372 // CHECK19-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 6373 // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 6374 // CHECK19-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP19]] 6375 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 6376 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i32 [[TMP15]] 6377 // CHECK19-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] 6378 // CHECK19-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP19]] 6379 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 6380 // CHECK19-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i32 [[TMP18]] 6381 // CHECK19-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP19]] 6382 // CHECK19-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] 6383 // CHECK19-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP19]] 6384 // CHECK19-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 6385 // CHECK19-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i32 [[TMP21]] 6386 // CHECK19-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP19]] 6387 // CHECK19-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] 6388 // CHECK19-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP19]] 6389 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 6390 // CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP23]], i32 [[TMP24]] 6391 // CHECK19-NEXT: store float [[MUL6]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP19]] 6392 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6393 // CHECK19: omp.body.continue: 6394 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6395 // CHECK19: omp.inner.for.inc: 6396 // CHECK19-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] 6397 // CHECK19-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 6398 // CHECK19-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] 6399 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 6400 // CHECK19: omp.inner.for.end: 6401 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6402 // CHECK19: omp.dispatch.inc: 6403 // CHECK19-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6404 // CHECK19-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 6405 // CHECK19-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] 6406 // CHECK19-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_LB]], align 4 6407 // CHECK19-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6408 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 6409 // CHECK19-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] 6410 // CHECK19-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_UB]], align 4 6411 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 6412 // CHECK19: omp.dispatch.end: 6413 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 6414 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 6415 // CHECK19-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 6416 // CHECK19-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6417 // CHECK19: .omp.final.then: 6418 // CHECK19-NEXT: store i32 -2147483522, ptr [[I]], align 4 6419 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 6420 // CHECK19: .omp.final.done: 6421 // CHECK19-NEXT: ret void 6422 // 6423 // 6424 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 6425 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 6426 // CHECK19-NEXT: entry: 6427 // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 6428 // CHECK19-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 6429 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6430 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 6431 // CHECK19-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 6432 // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 6433 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]]) 6434 // CHECK19-NEXT: ret void 6435 // 6436 // 6437 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined 6438 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { 6439 // CHECK19-NEXT: entry: 6440 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 6441 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 6442 // CHECK19-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 4 6443 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 6444 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6445 // CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1 6446 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 6447 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 6448 // CHECK19-NEXT: [[I4:%.*]] = alloca i8, align 1 6449 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6450 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6451 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6452 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6453 // CHECK19-NEXT: [[I6:%.*]] = alloca i8, align 1 6454 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 6455 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 6456 // CHECK19-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 4 6457 // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 6458 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 4 6459 // CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4 6460 // CHECK19-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1 6461 // CHECK19-NEXT: store i8 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 1 6462 // CHECK19-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 6463 // CHECK19-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 6464 // CHECK19-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 6465 // CHECK19-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 6466 // CHECK19-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 6467 // CHECK19-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 6468 // CHECK19-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 6469 // CHECK19-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 6470 // CHECK19-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 6471 // CHECK19-NEXT: store i8 [[TMP4]], ptr [[I4]], align 1 6472 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 6473 // CHECK19-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 6474 // CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 6475 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 6476 // CHECK19: omp.precond.then: 6477 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 6478 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 6479 // CHECK19-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4 6480 // CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 6481 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 6482 // CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6483 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 6484 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 6485 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6486 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 6487 // CHECK19-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] 6488 // CHECK19-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6489 // CHECK19: cond.true: 6490 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 6491 // CHECK19-NEXT: br label [[COND_END:%.*]] 6492 // CHECK19: cond.false: 6493 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6494 // CHECK19-NEXT: br label [[COND_END]] 6495 // CHECK19: cond.end: 6496 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 6497 // CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 6498 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6499 // CHECK19-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 6500 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6501 // CHECK19: omp.inner.for.cond: 6502 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]] 6503 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]] 6504 // CHECK19-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 6505 // CHECK19-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6506 // CHECK19: omp.inner.for.body: 6507 // CHECK19-NEXT: [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP22]] 6508 // CHECK19-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32 6509 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] 6510 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 6511 // CHECK19-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 6512 // CHECK19-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 6513 // CHECK19-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP22]] 6514 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6515 // CHECK19: omp.body.continue: 6516 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6517 // CHECK19: omp.inner.for.inc: 6518 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] 6519 // CHECK19-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1 6520 // CHECK19-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] 6521 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] 6522 // CHECK19: omp.inner.for.end: 6523 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6524 // CHECK19: omp.loop.exit: 6525 // CHECK19-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6526 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 6527 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) 6528 // CHECK19-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 6529 // CHECK19-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 6530 // CHECK19-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6531 // CHECK19: .omp.final.then: 6532 // CHECK19-NEXT: [[TMP23:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 6533 // CHECK19-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32 6534 // CHECK19-NEXT: [[TMP24:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 6535 // CHECK19-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32 6536 // CHECK19-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]] 6537 // CHECK19-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1 6538 // CHECK19-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1 6539 // CHECK19-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1 6540 // CHECK19-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1 6541 // CHECK19-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]] 6542 // CHECK19-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 6543 // CHECK19-NEXT: store i8 [[CONV21]], ptr [[TMP0]], align 1 6544 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 6545 // CHECK19: .omp.final.done: 6546 // CHECK19-NEXT: br label [[OMP_PRECOND_END]] 6547 // CHECK19: omp.precond.end: 6548 // CHECK19-NEXT: ret void 6549 // 6550 // 6551 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 6552 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 6553 // CHECK19-NEXT: entry: 6554 // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 6555 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6556 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 6557 // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 6558 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]]) 6559 // CHECK19-NEXT: ret void 6560 // 6561 // 6562 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined 6563 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { 6564 // CHECK19-NEXT: entry: 6565 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 6566 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 6567 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4 6568 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6569 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 6570 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6571 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6572 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6573 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6574 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 6575 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 6576 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 6577 // CHECK19-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4 6578 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4 6579 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 6580 // CHECK19-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 6581 // CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 6582 // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 6583 // CHECK19-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2 6584 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 6585 // CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 6586 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 6587 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 6588 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6589 // CHECK19: omp.dispatch.cond: 6590 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6591 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 6592 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6593 // CHECK19: cond.true: 6594 // CHECK19-NEXT: br label [[COND_END:%.*]] 6595 // CHECK19: cond.false: 6596 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6597 // CHECK19-NEXT: br label [[COND_END]] 6598 // CHECK19: cond.end: 6599 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 6600 // CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 6601 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6602 // CHECK19-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 6603 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 6604 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6605 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 6606 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6607 // CHECK19: omp.dispatch.body: 6608 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6609 // CHECK19: omp.inner.for.cond: 6610 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]] 6611 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]] 6612 // CHECK19-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 6613 // CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6614 // CHECK19: omp.inner.for.body: 6615 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] 6616 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 6617 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 6618 // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] 6619 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6620 // CHECK19: omp.body.continue: 6621 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6622 // CHECK19: omp.inner.for.inc: 6623 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] 6624 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 6625 // CHECK19-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] 6626 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] 6627 // CHECK19: omp.inner.for.end: 6628 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6629 // CHECK19: omp.dispatch.inc: 6630 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6631 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 6632 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 6633 // CHECK19-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4 6634 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6635 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 6636 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 6637 // CHECK19-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4 6638 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 6639 // CHECK19: omp.dispatch.end: 6640 // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 6641 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 6642 // CHECK19-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 6643 // CHECK19-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6644 // CHECK19: .omp.final.then: 6645 // CHECK19-NEXT: store i32 100, ptr [[I]], align 4 6646 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 6647 // CHECK19: .omp.final.done: 6648 // CHECK19-NEXT: ret void 6649 // 6650 // 6651 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 6652 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 6653 // CHECK21-NEXT: entry: 6654 // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 6655 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 6656 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 6657 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 6658 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 6659 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 6660 // CHECK21-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 6661 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 6662 // CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 6663 // CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 6664 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 6665 // CHECK21-NEXT: ret void 6666 // 6667 // 6668 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined 6669 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 6670 // CHECK21-NEXT: entry: 6671 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 6672 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 6673 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 6674 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 6675 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 6676 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 6677 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6678 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 6679 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6680 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6681 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6682 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6683 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 6684 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 6685 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 6686 // CHECK21-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 6687 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 6688 // CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 6689 // CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 6690 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 6691 // CHECK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 6692 // CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 6693 // CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 6694 // CHECK21-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP0]], align 8 6695 // CHECK21-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[TMP4]], i64 16) ] 6696 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 6697 // CHECK21-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 6698 // CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 6699 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 6700 // CHECK21-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 6701 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 6702 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 6703 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6704 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 6705 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6706 // CHECK21: cond.true: 6707 // CHECK21-NEXT: br label [[COND_END:%.*]] 6708 // CHECK21: cond.false: 6709 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6710 // CHECK21-NEXT: br label [[COND_END]] 6711 // CHECK21: cond.end: 6712 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 6713 // CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 6714 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6715 // CHECK21-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 6716 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6717 // CHECK21: omp.inner.for.cond: 6718 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] 6719 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] 6720 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 6721 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6722 // CHECK21: omp.inner.for.body: 6723 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 6724 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 6725 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 6726 // CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 6727 // CHECK21-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP9]] 6728 // CHECK21-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 6729 // CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 6730 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM]] 6731 // CHECK21-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] 6732 // CHECK21-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP9]] 6733 // CHECK21-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 6734 // CHECK21-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64 6735 // CHECK21-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM2]] 6736 // CHECK21-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP9]] 6737 // CHECK21-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]] 6738 // CHECK21-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP9]] 6739 // CHECK21-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 6740 // CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64 6741 // CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i64 [[IDXPROM5]] 6742 // CHECK21-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP9]] 6743 // CHECK21-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]] 6744 // CHECK21-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP9]] 6745 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] 6746 // CHECK21-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64 6747 // CHECK21-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[IDXPROM8]] 6748 // CHECK21-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP9]] 6749 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6750 // CHECK21: omp.body.continue: 6751 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6752 // CHECK21: omp.inner.for.inc: 6753 // CHECK21-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 6754 // CHECK21-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 6755 // CHECK21-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] 6756 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 6757 // CHECK21: omp.inner.for.end: 6758 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6759 // CHECK21: omp.loop.exit: 6760 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP6]]) 6761 // CHECK21-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 6762 // CHECK21-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 6763 // CHECK21-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6764 // CHECK21: .omp.final.then: 6765 // CHECK21-NEXT: store i32 32000001, ptr [[I]], align 4 6766 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 6767 // CHECK21: .omp.final.done: 6768 // CHECK21-NEXT: ret void 6769 // 6770 // 6771 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 6772 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 6773 // CHECK21-NEXT: entry: 6774 // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 6775 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 6776 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 6777 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 6778 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 6779 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 6780 // CHECK21-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 6781 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 6782 // CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 6783 // CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 6784 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 6785 // CHECK21-NEXT: ret void 6786 // 6787 // 6788 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined 6789 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 6790 // CHECK21-NEXT: entry: 6791 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 6792 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 6793 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 6794 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 6795 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 6796 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 6797 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6798 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 6799 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6800 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6801 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6802 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6803 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 6804 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 6805 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 6806 // CHECK21-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 6807 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 6808 // CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 6809 // CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 6810 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 6811 // CHECK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 6812 // CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 6813 // CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 6814 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 6815 // CHECK21-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 6816 // CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 6817 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 6818 // CHECK21-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 6819 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 6820 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 6821 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6822 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 6823 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6824 // CHECK21: cond.true: 6825 // CHECK21-NEXT: br label [[COND_END:%.*]] 6826 // CHECK21: cond.false: 6827 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6828 // CHECK21-NEXT: br label [[COND_END]] 6829 // CHECK21: cond.end: 6830 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 6831 // CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 6832 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6833 // CHECK21-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 6834 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6835 // CHECK21: omp.inner.for.cond: 6836 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 6837 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6838 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 6839 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6840 // CHECK21: omp.inner.for.body: 6841 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 6842 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 6843 // CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 6844 // CHECK21-NEXT: store i32 [[SUB]], ptr [[I]], align 4 6845 // CHECK21-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8, !nontemporal [[META16:![0-9]+]] 6846 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 6847 // CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 6848 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]] 6849 // CHECK21-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4 6850 // CHECK21-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8 6851 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 6852 // CHECK21-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 6853 // CHECK21-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]] 6854 // CHECK21-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 6855 // CHECK21-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 6856 // CHECK21-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8 6857 // CHECK21-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 6858 // CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 6859 // CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]] 6860 // CHECK21-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4 6861 // CHECK21-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 6862 // CHECK21-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8, !nontemporal [[META16]] 6863 // CHECK21-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 6864 // CHECK21-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 6865 // CHECK21-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]] 6866 // CHECK21-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4 6867 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6868 // CHECK21: omp.body.continue: 6869 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6870 // CHECK21: omp.inner.for.inc: 6871 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 6872 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 6873 // CHECK21-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 6874 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] 6875 // CHECK21: omp.inner.for.end: 6876 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6877 // CHECK21: omp.loop.exit: 6878 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 6879 // CHECK21-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 6880 // CHECK21-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 6881 // CHECK21-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6882 // CHECK21: .omp.final.then: 6883 // CHECK21-NEXT: store i32 32, ptr [[I]], align 4 6884 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 6885 // CHECK21: .omp.final.done: 6886 // CHECK21-NEXT: ret void 6887 // 6888 // 6889 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 6890 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 6891 // CHECK21-NEXT: entry: 6892 // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 6893 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 6894 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 6895 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 6896 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 6897 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 6898 // CHECK21-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 6899 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 6900 // CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 6901 // CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 6902 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 6903 // CHECK21-NEXT: ret void 6904 // 6905 // 6906 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined 6907 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 6908 // CHECK21-NEXT: entry: 6909 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 6910 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 6911 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 6912 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 6913 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 6914 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 6915 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6916 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 6917 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6918 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6919 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6920 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6921 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 6922 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 6923 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 6924 // CHECK21-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 6925 // CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 6926 // CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 6927 // CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 6928 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 6929 // CHECK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 6930 // CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 6931 // CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 6932 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 6933 // CHECK21-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4 6934 // CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 6935 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 6936 // CHECK21-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 6937 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 6938 // CHECK21-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5) 6939 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6940 // CHECK21: omp.dispatch.cond: 6941 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6942 // CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 6943 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6944 // CHECK21: cond.true: 6945 // CHECK21-NEXT: br label [[COND_END:%.*]] 6946 // CHECK21: cond.false: 6947 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6948 // CHECK21-NEXT: br label [[COND_END]] 6949 // CHECK21: cond.end: 6950 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 6951 // CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 6952 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 6953 // CHECK21-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 6954 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 6955 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 6956 // CHECK21-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 6957 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6958 // CHECK21: omp.dispatch.body: 6959 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6960 // CHECK21: omp.inner.for.cond: 6961 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] 6962 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] 6963 // CHECK21-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 6964 // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6965 // CHECK21: omp.inner.for.body: 6966 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] 6967 // CHECK21-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 6968 // CHECK21-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 6969 // CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 6970 // CHECK21-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP19]] 6971 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 6972 // CHECK21-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 6973 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[IDXPROM]] 6974 // CHECK21-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] 6975 // CHECK21-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP19]] 6976 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 6977 // CHECK21-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 6978 // CHECK21-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[IDXPROM3]] 6979 // CHECK21-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP19]] 6980 // CHECK21-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 6981 // CHECK21-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP19]] 6982 // CHECK21-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 6983 // CHECK21-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 6984 // CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[IDXPROM6]] 6985 // CHECK21-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP19]] 6986 // CHECK21-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 6987 // CHECK21-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP19]] 6988 // CHECK21-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] 6989 // CHECK21-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 6990 // CHECK21-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP23]], i64 [[IDXPROM9]] 6991 // CHECK21-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP19]] 6992 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6993 // CHECK21: omp.body.continue: 6994 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6995 // CHECK21: omp.inner.for.inc: 6996 // CHECK21-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] 6997 // CHECK21-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 6998 // CHECK21-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] 6999 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 7000 // CHECK21: omp.inner.for.end: 7001 // CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 7002 // CHECK21: omp.dispatch.inc: 7003 // CHECK21-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 7004 // CHECK21-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 7005 // CHECK21-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 7006 // CHECK21-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 4 7007 // CHECK21-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7008 // CHECK21-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 7009 // CHECK21-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 7010 // CHECK21-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 4 7011 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND]] 7012 // CHECK21: omp.dispatch.end: 7013 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 7014 // CHECK21-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 7015 // CHECK21-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 7016 // CHECK21-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 7017 // CHECK21: .omp.final.then: 7018 // CHECK21-NEXT: store i32 -2147483522, ptr [[I]], align 4 7019 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 7020 // CHECK21: .omp.final.done: 7021 // CHECK21-NEXT: ret void 7022 // 7023 // 7024 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 7025 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 7026 // CHECK21-NEXT: entry: 7027 // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 7028 // CHECK21-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 7029 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7030 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 7031 // CHECK21-NEXT: store i64 [[I]], ptr [[I_ADDR]], align 8 7032 // CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 7033 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]]) 7034 // CHECK21-NEXT: ret void 7035 // 7036 // 7037 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined 7038 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { 7039 // CHECK21-NEXT: entry: 7040 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 7041 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 7042 // CHECK21-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8 7043 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 7044 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7045 // CHECK21-NEXT: [[TMP:%.*]] = alloca i8, align 1 7046 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 7047 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 7048 // CHECK21-NEXT: [[I4:%.*]] = alloca i8, align 1 7049 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7050 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7051 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7052 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7053 // CHECK21-NEXT: [[I6:%.*]] = alloca i8, align 1 7054 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 7055 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 7056 // CHECK21-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 8 7057 // CHECK21-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 7058 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8 7059 // CHECK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 7060 // CHECK21-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1 7061 // CHECK21-NEXT: store i8 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 1 7062 // CHECK21-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 7063 // CHECK21-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 7064 // CHECK21-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 7065 // CHECK21-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 7066 // CHECK21-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 7067 // CHECK21-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 7068 // CHECK21-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 7069 // CHECK21-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 7070 // CHECK21-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 7071 // CHECK21-NEXT: store i8 [[TMP4]], ptr [[I4]], align 1 7072 // CHECK21-NEXT: [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 7073 // CHECK21-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 7074 // CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 7075 // CHECK21-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 7076 // CHECK21: omp.precond.then: 7077 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 7078 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 7079 // CHECK21-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4 7080 // CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 7081 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 7082 // CHECK21-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 7083 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 7084 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 7085 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7086 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 7087 // CHECK21-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] 7088 // CHECK21-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7089 // CHECK21: cond.true: 7090 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 7091 // CHECK21-NEXT: br label [[COND_END:%.*]] 7092 // CHECK21: cond.false: 7093 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7094 // CHECK21-NEXT: br label [[COND_END]] 7095 // CHECK21: cond.end: 7096 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 7097 // CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 7098 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 7099 // CHECK21-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 7100 // CHECK21-NEXT: [[TMP14:%.*]] = load i8, ptr [[TMP1]], align 1 7101 // CHECK21-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0 7102 // CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 7103 // CHECK21: omp_if.then: 7104 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7105 // CHECK21: omp.inner.for.cond: 7106 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]] 7107 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]] 7108 // CHECK21-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 7109 // CHECK21-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7110 // CHECK21: omp.inner.for.body: 7111 // CHECK21-NEXT: [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP22]] 7112 // CHECK21-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32 7113 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] 7114 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 7115 // CHECK21-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 7116 // CHECK21-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 7117 // CHECK21-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal [[META16]], !llvm.access.group [[ACC_GRP22]] 7118 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7119 // CHECK21: omp.body.continue: 7120 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7121 // CHECK21: omp.inner.for.inc: 7122 // CHECK21-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] 7123 // CHECK21-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 7124 // CHECK21-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] 7125 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] 7126 // CHECK21: omp.inner.for.end: 7127 // CHECK21-NEXT: br label [[OMP_IF_END:%.*]] 7128 // CHECK21: omp_if.else: 7129 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 7130 // CHECK21: omp.inner.for.cond13: 7131 // CHECK21-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 7132 // CHECK21-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7133 // CHECK21-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] 7134 // CHECK21-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]] 7135 // CHECK21: omp.inner.for.body15: 7136 // CHECK21-NEXT: [[TMP22:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 7137 // CHECK21-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32 7138 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 7139 // CHECK21-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1 7140 // CHECK21-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]] 7141 // CHECK21-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 7142 // CHECK21-NEXT: store i8 [[CONV19]], ptr [[I6]], align 1 7143 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]] 7144 // CHECK21: omp.body.continue20: 7145 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]] 7146 // CHECK21: omp.inner.for.inc21: 7147 // CHECK21-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 7148 // CHECK21-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1 7149 // CHECK21-NEXT: store i32 [[ADD22]], ptr [[DOTOMP_IV]], align 4 7150 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP25:![0-9]+]] 7151 // CHECK21: omp.inner.for.end23: 7152 // CHECK21-NEXT: br label [[OMP_IF_END]] 7153 // CHECK21: omp_if.end: 7154 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7155 // CHECK21: omp.loop.exit: 7156 // CHECK21-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 7157 // CHECK21-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 7158 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]]) 7159 // CHECK21-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 7160 // CHECK21-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 7161 // CHECK21-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 7162 // CHECK21: .omp.final.then: 7163 // CHECK21-NEXT: [[TMP29:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 7164 // CHECK21-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32 7165 // CHECK21-NEXT: [[TMP30:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 7166 // CHECK21-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32 7167 // CHECK21-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]] 7168 // CHECK21-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1 7169 // CHECK21-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1 7170 // CHECK21-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1 7171 // CHECK21-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1 7172 // CHECK21-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]] 7173 // CHECK21-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8 7174 // CHECK21-NEXT: store i8 [[CONV32]], ptr [[TMP0]], align 1 7175 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 7176 // CHECK21: .omp.final.done: 7177 // CHECK21-NEXT: br label [[OMP_PRECOND_END]] 7178 // CHECK21: omp.precond.end: 7179 // CHECK21-NEXT: ret void 7180 // 7181 // 7182 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 7183 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 7184 // CHECK21-NEXT: entry: 7185 // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 7186 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7187 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 7188 // CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 7189 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]]) 7190 // CHECK21-NEXT: ret void 7191 // 7192 // 7193 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined 7194 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { 7195 // CHECK21-NEXT: entry: 7196 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 7197 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 7198 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8 7199 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7200 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 7201 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7202 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7203 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7204 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7205 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 7206 // CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 7207 // CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 7208 // CHECK21-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8 7209 // CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8 7210 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 7211 // CHECK21-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 7212 // CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 7213 // CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 7214 // CHECK21-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2 7215 // CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 7216 // CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 7217 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 7218 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 7219 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 7220 // CHECK21: omp.dispatch.cond: 7221 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7222 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 7223 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7224 // CHECK21: cond.true: 7225 // CHECK21-NEXT: br label [[COND_END:%.*]] 7226 // CHECK21: cond.false: 7227 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7228 // CHECK21-NEXT: br label [[COND_END]] 7229 // CHECK21: cond.end: 7230 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 7231 // CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 7232 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 7233 // CHECK21-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 7234 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 7235 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7236 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 7237 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 7238 // CHECK21: omp.dispatch.body: 7239 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7240 // CHECK21: omp.inner.for.cond: 7241 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] 7242 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] 7243 // CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 7244 // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7245 // CHECK21: omp.inner.for.body: 7246 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 7247 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 7248 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 7249 // CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] 7250 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7251 // CHECK21: omp.body.continue: 7252 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7253 // CHECK21: omp.inner.for.inc: 7254 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 7255 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 7256 // CHECK21-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 7257 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 7258 // CHECK21: omp.inner.for.end: 7259 // CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 7260 // CHECK21: omp.dispatch.inc: 7261 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 7262 // CHECK21-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 7263 // CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 7264 // CHECK21-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4 7265 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7266 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 7267 // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 7268 // CHECK21-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4 7269 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND]] 7270 // CHECK21: omp.dispatch.end: 7271 // CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 7272 // CHECK21-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 7273 // CHECK21-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 7274 // CHECK21-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 7275 // CHECK21: .omp.final.then: 7276 // CHECK21-NEXT: store i32 100, ptr [[I]], align 4 7277 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 7278 // CHECK21: .omp.final.done: 7279 // CHECK21-NEXT: ret void 7280 // 7281 // 7282 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 7283 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 7284 // CHECK23-NEXT: entry: 7285 // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 7286 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 7287 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 7288 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 7289 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 7290 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 7291 // CHECK23-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 7292 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 7293 // CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 7294 // CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 7295 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 7296 // CHECK23-NEXT: ret void 7297 // 7298 // 7299 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined 7300 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 7301 // CHECK23-NEXT: entry: 7302 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 7303 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 7304 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 7305 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 7306 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 7307 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 7308 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7309 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 7310 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7311 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7312 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7313 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7314 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 7315 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 7316 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 7317 // CHECK23-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 7318 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 7319 // CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 7320 // CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 7321 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 7322 // CHECK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 7323 // CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 7324 // CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 7325 // CHECK23-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP0]], align 4 7326 // CHECK23-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[TMP4]], i32 16) ] 7327 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 7328 // CHECK23-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 7329 // CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 7330 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 7331 // CHECK23-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 7332 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 7333 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 7334 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7335 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 7336 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7337 // CHECK23: cond.true: 7338 // CHECK23-NEXT: br label [[COND_END:%.*]] 7339 // CHECK23: cond.false: 7340 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7341 // CHECK23-NEXT: br label [[COND_END]] 7342 // CHECK23: cond.end: 7343 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 7344 // CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 7345 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 7346 // CHECK23-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 7347 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7348 // CHECK23: omp.inner.for.cond: 7349 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 7350 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 7351 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 7352 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7353 // CHECK23: omp.inner.for.body: 7354 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 7355 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 7356 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 7357 // CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 7358 // CHECK23-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP10]] 7359 // CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 7360 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i32 [[TMP14]] 7361 // CHECK23-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] 7362 // CHECK23-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP10]] 7363 // CHECK23-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 7364 // CHECK23-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i32 [[TMP17]] 7365 // CHECK23-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP10]] 7366 // CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]] 7367 // CHECK23-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP10]] 7368 // CHECK23-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 7369 // CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i32 [[TMP20]] 7370 // CHECK23-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP10]] 7371 // CHECK23-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]] 7372 // CHECK23-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP10]] 7373 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 7374 // CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i32 [[TMP23]] 7375 // CHECK23-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP10]] 7376 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7377 // CHECK23: omp.body.continue: 7378 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7379 // CHECK23: omp.inner.for.inc: 7380 // CHECK23-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 7381 // CHECK23-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1 7382 // CHECK23-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 7383 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 7384 // CHECK23: omp.inner.for.end: 7385 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7386 // CHECK23: omp.loop.exit: 7387 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP6]]) 7388 // CHECK23-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 7389 // CHECK23-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 7390 // CHECK23-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 7391 // CHECK23: .omp.final.then: 7392 // CHECK23-NEXT: store i32 32000001, ptr [[I]], align 4 7393 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 7394 // CHECK23: .omp.final.done: 7395 // CHECK23-NEXT: ret void 7396 // 7397 // 7398 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 7399 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 7400 // CHECK23-NEXT: entry: 7401 // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 7402 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 7403 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 7404 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 7405 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 7406 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 7407 // CHECK23-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 7408 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 7409 // CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 7410 // CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 7411 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 7412 // CHECK23-NEXT: ret void 7413 // 7414 // 7415 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined 7416 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 7417 // CHECK23-NEXT: entry: 7418 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 7419 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 7420 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 7421 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 7422 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 7423 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 7424 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7425 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 7426 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7427 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7428 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7429 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7430 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 7431 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 7432 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 7433 // CHECK23-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 7434 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 7435 // CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 7436 // CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 7437 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 7438 // CHECK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 7439 // CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 7440 // CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 7441 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 7442 // CHECK23-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 7443 // CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 7444 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 7445 // CHECK23-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 7446 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 7447 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 7448 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7449 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 7450 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7451 // CHECK23: cond.true: 7452 // CHECK23-NEXT: br label [[COND_END:%.*]] 7453 // CHECK23: cond.false: 7454 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7455 // CHECK23-NEXT: br label [[COND_END]] 7456 // CHECK23: cond.end: 7457 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 7458 // CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 7459 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 7460 // CHECK23-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 7461 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7462 // CHECK23: omp.inner.for.cond: 7463 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 7464 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7465 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 7466 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7467 // CHECK23: omp.inner.for.body: 7468 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 7469 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 7470 // CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 7471 // CHECK23-NEXT: store i32 [[SUB]], ptr [[I]], align 4 7472 // CHECK23-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 4, !nontemporal [[META17:![0-9]+]] 7473 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 7474 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 [[TMP13]] 7475 // CHECK23-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4 7476 // CHECK23-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 4 7477 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 7478 // CHECK23-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i32 [[TMP16]] 7479 // CHECK23-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX2]], align 4 7480 // CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 7481 // CHECK23-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 4 7482 // CHECK23-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 7483 // CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i32 [[TMP19]] 7484 // CHECK23-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX4]], align 4 7485 // CHECK23-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 7486 // CHECK23-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 4, !nontemporal [[META17]] 7487 // CHECK23-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 7488 // CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i32 [[TMP22]] 7489 // CHECK23-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4 7490 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7491 // CHECK23: omp.body.continue: 7492 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7493 // CHECK23: omp.inner.for.inc: 7494 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 7495 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 7496 // CHECK23-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 7497 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 7498 // CHECK23: omp.inner.for.end: 7499 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7500 // CHECK23: omp.loop.exit: 7501 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 7502 // CHECK23-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 7503 // CHECK23-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 7504 // CHECK23-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 7505 // CHECK23: .omp.final.then: 7506 // CHECK23-NEXT: store i32 32, ptr [[I]], align 4 7507 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 7508 // CHECK23: .omp.final.done: 7509 // CHECK23-NEXT: ret void 7510 // 7511 // 7512 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 7513 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { 7514 // CHECK23-NEXT: entry: 7515 // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 7516 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 7517 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 7518 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 7519 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 7520 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 7521 // CHECK23-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 7522 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 7523 // CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 7524 // CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 7525 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) 7526 // CHECK23-NEXT: ret void 7527 // 7528 // 7529 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined 7530 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 7531 // CHECK23-NEXT: entry: 7532 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 7533 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 7534 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 7535 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 7536 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 7537 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 7538 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7539 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 7540 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7541 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7542 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7543 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7544 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 7545 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 7546 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 7547 // CHECK23-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 7548 // CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 7549 // CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 7550 // CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 7551 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 7552 // CHECK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 7553 // CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 7554 // CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 7555 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 7556 // CHECK23-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4 7557 // CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 7558 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 7559 // CHECK23-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 7560 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 7561 // CHECK23-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5) 7562 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 7563 // CHECK23: omp.dispatch.cond: 7564 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7565 // CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 7566 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7567 // CHECK23: cond.true: 7568 // CHECK23-NEXT: br label [[COND_END:%.*]] 7569 // CHECK23: cond.false: 7570 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7571 // CHECK23-NEXT: br label [[COND_END]] 7572 // CHECK23: cond.end: 7573 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 7574 // CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 7575 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 7576 // CHECK23-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 7577 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 7578 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7579 // CHECK23-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 7580 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 7581 // CHECK23: omp.dispatch.body: 7582 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7583 // CHECK23: omp.inner.for.cond: 7584 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] 7585 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] 7586 // CHECK23-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 7587 // CHECK23-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7588 // CHECK23: omp.inner.for.body: 7589 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 7590 // CHECK23-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 7591 // CHECK23-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 7592 // CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]] 7593 // CHECK23-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP20]] 7594 // CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]] 7595 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i32 [[TMP15]] 7596 // CHECK23-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP20]] 7597 // CHECK23-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP20]] 7598 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]] 7599 // CHECK23-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i32 [[TMP18]] 7600 // CHECK23-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP20]] 7601 // CHECK23-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] 7602 // CHECK23-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP20]] 7603 // CHECK23-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]] 7604 // CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i32 [[TMP21]] 7605 // CHECK23-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP20]] 7606 // CHECK23-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] 7607 // CHECK23-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP20]] 7608 // CHECK23-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]] 7609 // CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP23]], i32 [[TMP24]] 7610 // CHECK23-NEXT: store float [[MUL6]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP20]] 7611 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7612 // CHECK23: omp.body.continue: 7613 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7614 // CHECK23: omp.inner.for.inc: 7615 // CHECK23-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 7616 // CHECK23-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 7617 // CHECK23-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 7618 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 7619 // CHECK23: omp.inner.for.end: 7620 // CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 7621 // CHECK23: omp.dispatch.inc: 7622 // CHECK23-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 7623 // CHECK23-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 7624 // CHECK23-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] 7625 // CHECK23-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_LB]], align 4 7626 // CHECK23-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7627 // CHECK23-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 7628 // CHECK23-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] 7629 // CHECK23-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_UB]], align 4 7630 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND]] 7631 // CHECK23: omp.dispatch.end: 7632 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 7633 // CHECK23-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 7634 // CHECK23-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 7635 // CHECK23-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 7636 // CHECK23: .omp.final.then: 7637 // CHECK23-NEXT: store i32 -2147483522, ptr [[I]], align 4 7638 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 7639 // CHECK23: .omp.final.done: 7640 // CHECK23-NEXT: ret void 7641 // 7642 // 7643 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 7644 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 7645 // CHECK23-NEXT: entry: 7646 // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 7647 // CHECK23-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 7648 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7649 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 7650 // CHECK23-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 7651 // CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 7652 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]]) 7653 // CHECK23-NEXT: ret void 7654 // 7655 // 7656 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined 7657 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { 7658 // CHECK23-NEXT: entry: 7659 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 7660 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 7661 // CHECK23-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 4 7662 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 7663 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7664 // CHECK23-NEXT: [[TMP:%.*]] = alloca i8, align 1 7665 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 7666 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 7667 // CHECK23-NEXT: [[I4:%.*]] = alloca i8, align 1 7668 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7669 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7670 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7671 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7672 // CHECK23-NEXT: [[I6:%.*]] = alloca i8, align 1 7673 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 7674 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 7675 // CHECK23-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 4 7676 // CHECK23-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 7677 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 4 7678 // CHECK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4 7679 // CHECK23-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1 7680 // CHECK23-NEXT: store i8 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 1 7681 // CHECK23-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 7682 // CHECK23-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 7683 // CHECK23-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 7684 // CHECK23-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 7685 // CHECK23-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 7686 // CHECK23-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 7687 // CHECK23-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 7688 // CHECK23-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 7689 // CHECK23-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 7690 // CHECK23-NEXT: store i8 [[TMP4]], ptr [[I4]], align 1 7691 // CHECK23-NEXT: [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 7692 // CHECK23-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 7693 // CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 7694 // CHECK23-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 7695 // CHECK23: omp.precond.then: 7696 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 7697 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 7698 // CHECK23-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4 7699 // CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 7700 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 7701 // CHECK23-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 7702 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 7703 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 7704 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7705 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 7706 // CHECK23-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] 7707 // CHECK23-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7708 // CHECK23: cond.true: 7709 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 7710 // CHECK23-NEXT: br label [[COND_END:%.*]] 7711 // CHECK23: cond.false: 7712 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7713 // CHECK23-NEXT: br label [[COND_END]] 7714 // CHECK23: cond.end: 7715 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 7716 // CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 7717 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 7718 // CHECK23-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 7719 // CHECK23-NEXT: [[TMP14:%.*]] = load i8, ptr [[TMP1]], align 1 7720 // CHECK23-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0 7721 // CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 7722 // CHECK23: omp_if.then: 7723 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7724 // CHECK23: omp.inner.for.cond: 7725 // CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] 7726 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] 7727 // CHECK23-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 7728 // CHECK23-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7729 // CHECK23: omp.inner.for.body: 7730 // CHECK23-NEXT: [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP23]] 7731 // CHECK23-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32 7732 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 7733 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 7734 // CHECK23-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 7735 // CHECK23-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 7736 // CHECK23-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal [[META17]], !llvm.access.group [[ACC_GRP23]] 7737 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7738 // CHECK23: omp.body.continue: 7739 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7740 // CHECK23: omp.inner.for.inc: 7741 // CHECK23-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 7742 // CHECK23-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 7743 // CHECK23-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 7744 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] 7745 // CHECK23: omp.inner.for.end: 7746 // CHECK23-NEXT: br label [[OMP_IF_END:%.*]] 7747 // CHECK23: omp_if.else: 7748 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 7749 // CHECK23: omp.inner.for.cond13: 7750 // CHECK23-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 7751 // CHECK23-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7752 // CHECK23-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] 7753 // CHECK23-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]] 7754 // CHECK23: omp.inner.for.body15: 7755 // CHECK23-NEXT: [[TMP22:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 7756 // CHECK23-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32 7757 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 7758 // CHECK23-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1 7759 // CHECK23-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]] 7760 // CHECK23-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 7761 // CHECK23-NEXT: store i8 [[CONV19]], ptr [[I6]], align 1 7762 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]] 7763 // CHECK23: omp.body.continue20: 7764 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]] 7765 // CHECK23: omp.inner.for.inc21: 7766 // CHECK23-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 7767 // CHECK23-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1 7768 // CHECK23-NEXT: store i32 [[ADD22]], ptr [[DOTOMP_IV]], align 4 7769 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP26:![0-9]+]] 7770 // CHECK23: omp.inner.for.end23: 7771 // CHECK23-NEXT: br label [[OMP_IF_END]] 7772 // CHECK23: omp_if.end: 7773 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7774 // CHECK23: omp.loop.exit: 7775 // CHECK23-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 7776 // CHECK23-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 7777 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]]) 7778 // CHECK23-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 7779 // CHECK23-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 7780 // CHECK23-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 7781 // CHECK23: .omp.final.then: 7782 // CHECK23-NEXT: [[TMP29:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 7783 // CHECK23-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32 7784 // CHECK23-NEXT: [[TMP30:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 7785 // CHECK23-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32 7786 // CHECK23-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]] 7787 // CHECK23-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1 7788 // CHECK23-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1 7789 // CHECK23-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1 7790 // CHECK23-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1 7791 // CHECK23-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]] 7792 // CHECK23-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8 7793 // CHECK23-NEXT: store i8 [[CONV32]], ptr [[TMP0]], align 1 7794 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 7795 // CHECK23: .omp.final.done: 7796 // CHECK23-NEXT: br label [[OMP_PRECOND_END]] 7797 // CHECK23: omp.precond.end: 7798 // CHECK23-NEXT: ret void 7799 // 7800 // 7801 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 7802 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 7803 // CHECK23-NEXT: entry: 7804 // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 7805 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7806 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 7807 // CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 7808 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]]) 7809 // CHECK23-NEXT: ret void 7810 // 7811 // 7812 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined 7813 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { 7814 // CHECK23-NEXT: entry: 7815 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 7816 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 7817 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4 7818 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7819 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 7820 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7821 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7822 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7823 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7824 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 7825 // CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 7826 // CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 7827 // CHECK23-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4 7828 // CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4 7829 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 7830 // CHECK23-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 7831 // CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 7832 // CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 7833 // CHECK23-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2 7834 // CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 7835 // CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 7836 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 7837 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 7838 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 7839 // CHECK23: omp.dispatch.cond: 7840 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7841 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 7842 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7843 // CHECK23: cond.true: 7844 // CHECK23-NEXT: br label [[COND_END:%.*]] 7845 // CHECK23: cond.false: 7846 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7847 // CHECK23-NEXT: br label [[COND_END]] 7848 // CHECK23: cond.end: 7849 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 7850 // CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 7851 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 7852 // CHECK23-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 7853 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 7854 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7855 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 7856 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 7857 // CHECK23: omp.dispatch.body: 7858 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7859 // CHECK23: omp.inner.for.cond: 7860 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]] 7861 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]] 7862 // CHECK23-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 7863 // CHECK23-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7864 // CHECK23: omp.inner.for.body: 7865 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] 7866 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 7867 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 7868 // CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] 7869 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7870 // CHECK23: omp.body.continue: 7871 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7872 // CHECK23: omp.inner.for.inc: 7873 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] 7874 // CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 7875 // CHECK23-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] 7876 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] 7877 // CHECK23: omp.inner.for.end: 7878 // CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 7879 // CHECK23: omp.dispatch.inc: 7880 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 7881 // CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 7882 // CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 7883 // CHECK23-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4 7884 // CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 7885 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 7886 // CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 7887 // CHECK23-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4 7888 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND]] 7889 // CHECK23: omp.dispatch.end: 7890 // CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) 7891 // CHECK23-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 7892 // CHECK23-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 7893 // CHECK23-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 7894 // CHECK23: .omp.final.then: 7895 // CHECK23-NEXT: store i32 100, ptr [[I]], align 4 7896 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 7897 // CHECK23: .omp.final.done: 7898 // CHECK23-NEXT: ret void 7899 // 7900