xref: /llvm-project/clang/test/OpenMP/distribute_parallel_for_simd_proc_bind_codegen.cpp (revision 94473f4db6a6f5f12d7c4081455b5b596094eac5) 
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // add -fopenmp-targets
3 
4 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
6 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
7 
8 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
9 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
10 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
11 // expected-no-diagnostics
12 #ifndef HEADER
13 #define HEADER
14 
15 typedef __INTPTR_TYPE__ intptr_t;
16 
17 
18 void foo();
19 
20 struct S {
21   intptr_t a, b, c;
22   S(intptr_t a) : a(a) {}
23   operator char() { return a; }
24   ~S() {}
25 };
26 
27 template <typename T>
28 T tmain() {
29 #pragma omp target
30 #pragma omp teams
31 #pragma omp distribute parallel for simd proc_bind(master)
32   for(int i = 0; i < 1000; i++) {}
33   return T();
34 }
35 
36 int main() {
37 #pragma omp target
38 #pragma omp teams
39 #pragma omp distribute parallel for simd proc_bind(spread)
40   for(int i = 0; i < 1000; i++) {}
41 #pragma omp target
42 #pragma omp teams
43 #pragma omp distribute parallel for simd proc_bind(close)
44   for(int i = 0; i < 1000; i++) {}
45   return tmain<int>();
46 }
47 
48 
49 
50 
51 
52 
53 
54 
55 #endif
56 // CHECK1-LABEL: define {{[^@]+}}@main
57 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
58 // CHECK1-NEXT:  entry:
59 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
60 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
61 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
62 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
63 // CHECK1-NEXT:    [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
64 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
65 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
66 // CHECK1-NEXT:    store i32 3, ptr [[TMP0]], align 4
67 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
68 // CHECK1-NEXT:    store i32 0, ptr [[TMP1]], align 4
69 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
70 // CHECK1-NEXT:    store ptr null, ptr [[TMP2]], align 8
71 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
72 // CHECK1-NEXT:    store ptr null, ptr [[TMP3]], align 8
73 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
74 // CHECK1-NEXT:    store ptr null, ptr [[TMP4]], align 8
75 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
76 // CHECK1-NEXT:    store ptr null, ptr [[TMP5]], align 8
77 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
78 // CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8
79 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
80 // CHECK1-NEXT:    store ptr null, ptr [[TMP7]], align 8
81 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
82 // CHECK1-NEXT:    store i64 1000, ptr [[TMP8]], align 8
83 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
84 // CHECK1-NEXT:    store i64 0, ptr [[TMP9]], align 8
85 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
86 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
87 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
88 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
89 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
90 // CHECK1-NEXT:    store i32 0, ptr [[TMP12]], align 4
91 // CHECK1-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.region_id, ptr [[KERNEL_ARGS]])
92 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
93 // CHECK1-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
94 // CHECK1:       omp_offload.failed:
95 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37() #[[ATTR2:[0-9]+]]
96 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
97 // CHECK1:       omp_offload.cont:
98 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0
99 // CHECK1-NEXT:    store i32 3, ptr [[TMP15]], align 4
100 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1
101 // CHECK1-NEXT:    store i32 0, ptr [[TMP16]], align 4
102 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2
103 // CHECK1-NEXT:    store ptr null, ptr [[TMP17]], align 8
104 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3
105 // CHECK1-NEXT:    store ptr null, ptr [[TMP18]], align 8
106 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4
107 // CHECK1-NEXT:    store ptr null, ptr [[TMP19]], align 8
108 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5
109 // CHECK1-NEXT:    store ptr null, ptr [[TMP20]], align 8
110 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6
111 // CHECK1-NEXT:    store ptr null, ptr [[TMP21]], align 8
112 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7
113 // CHECK1-NEXT:    store ptr null, ptr [[TMP22]], align 8
114 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8
115 // CHECK1-NEXT:    store i64 1000, ptr [[TMP23]], align 8
116 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9
117 // CHECK1-NEXT:    store i64 0, ptr [[TMP24]], align 8
118 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10
119 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4
120 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11
121 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
122 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12
123 // CHECK1-NEXT:    store i32 0, ptr [[TMP27]], align 4
124 // CHECK1-NEXT:    [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.region_id, ptr [[KERNEL_ARGS2]])
125 // CHECK1-NEXT:    [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
126 // CHECK1-NEXT:    br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
127 // CHECK1:       omp_offload.failed3:
128 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41() #[[ATTR2]]
129 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT4]]
130 // CHECK1:       omp_offload.cont4:
131 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
132 // CHECK1-NEXT:    ret i32 [[CALL]]
133 //
134 //
135 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37
136 // CHECK1-SAME: () #[[ATTR1:[0-9]+]] {
137 // CHECK1-NEXT:  entry:
138 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.omp_outlined)
139 // CHECK1-NEXT:    ret void
140 //
141 //
142 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.omp_outlined
143 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
144 // CHECK1-NEXT:  entry:
145 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
146 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
147 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
148 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
149 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
150 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
151 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
152 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
153 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
154 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
155 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
156 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
157 // CHECK1-NEXT:    store i32 999, ptr [[DOTOMP_COMB_UB]], align 4
158 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
159 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
160 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
161 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
162 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
163 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
164 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 999
165 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
166 // CHECK1:       cond.true:
167 // CHECK1-NEXT:    br label [[COND_END:%.*]]
168 // CHECK1:       cond.false:
169 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
170 // CHECK1-NEXT:    br label [[COND_END]]
171 // CHECK1:       cond.end:
172 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
173 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
174 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
175 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
176 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
177 // CHECK1:       omp.inner.for.cond:
178 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
179 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
180 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
181 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
182 // CHECK1:       omp.inner.for.body:
183 // CHECK1-NEXT:    call void @__kmpc_push_proc_bind(ptr @[[GLOB3]], i32 [[TMP1]], i32 4), !llvm.access.group [[ACC_GRP6]]
184 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP6]]
185 // CHECK1-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
186 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
187 // CHECK1-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
188 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP6]]
189 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
190 // CHECK1:       omp.inner.for.inc:
191 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
192 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP6]]
193 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
194 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
195 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
196 // CHECK1:       omp.inner.for.end:
197 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
198 // CHECK1:       omp.loop.exit:
199 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
200 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
201 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
202 // CHECK1-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
203 // CHECK1:       .omp.final.then:
204 // CHECK1-NEXT:    store i32 1000, ptr [[I]], align 4
205 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
206 // CHECK1:       .omp.final.done:
207 // CHECK1-NEXT:    ret void
208 //
209 //
210 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.omp_outlined.omp_outlined
211 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] {
212 // CHECK1-NEXT:  entry:
213 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
214 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
215 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
216 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
217 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
218 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
219 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
220 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
221 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
222 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
223 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
224 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
225 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
226 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
227 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
228 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
229 // CHECK1-NEXT:    store i32 999, ptr [[DOTOMP_UB]], align 4
230 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
231 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
232 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
233 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
234 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
235 // CHECK1-NEXT:    store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
236 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
237 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
238 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
239 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
240 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
241 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
242 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 999
243 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
244 // CHECK1:       cond.true:
245 // CHECK1-NEXT:    br label [[COND_END:%.*]]
246 // CHECK1:       cond.false:
247 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
248 // CHECK1-NEXT:    br label [[COND_END]]
249 // CHECK1:       cond.end:
250 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
251 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
252 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
253 // CHECK1-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
254 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
255 // CHECK1:       omp.inner.for.cond:
256 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]
257 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]]
258 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
259 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
260 // CHECK1:       omp.inner.for.body:
261 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
262 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
263 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
264 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
265 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
266 // CHECK1:       omp.body.continue:
267 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
268 // CHECK1:       omp.inner.for.inc:
269 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
270 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
271 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
272 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
273 // CHECK1:       omp.inner.for.end:
274 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
275 // CHECK1:       omp.loop.exit:
276 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]])
277 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
278 // CHECK1-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
279 // CHECK1-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
280 // CHECK1:       .omp.final.then:
281 // CHECK1-NEXT:    store i32 1000, ptr [[I]], align 4
282 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
283 // CHECK1:       .omp.final.done:
284 // CHECK1-NEXT:    ret void
285 //
286 //
287 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41
288 // CHECK1-SAME: () #[[ATTR1]] {
289 // CHECK1-NEXT:  entry:
290 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.omp_outlined)
291 // CHECK1-NEXT:    ret void
292 //
293 //
294 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.omp_outlined
295 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
296 // CHECK1-NEXT:  entry:
297 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
298 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
299 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
300 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
301 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
302 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
303 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
304 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
305 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
306 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
307 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
308 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
309 // CHECK1-NEXT:    store i32 999, ptr [[DOTOMP_COMB_UB]], align 4
310 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
311 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
312 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
313 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
314 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
315 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
316 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 999
317 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
318 // CHECK1:       cond.true:
319 // CHECK1-NEXT:    br label [[COND_END:%.*]]
320 // CHECK1:       cond.false:
321 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
322 // CHECK1-NEXT:    br label [[COND_END]]
323 // CHECK1:       cond.end:
324 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
325 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
326 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
327 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
328 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
329 // CHECK1:       omp.inner.for.cond:
330 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]]
331 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]]
332 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
333 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
334 // CHECK1:       omp.inner.for.body:
335 // CHECK1-NEXT:    call void @__kmpc_push_proc_bind(ptr @[[GLOB3]], i32 [[TMP1]], i32 3), !llvm.access.group [[ACC_GRP15]]
336 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]]
337 // CHECK1-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
338 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]]
339 // CHECK1-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
340 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP15]]
341 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
342 // CHECK1:       omp.inner.for.inc:
343 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]
344 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]]
345 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
346 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]
347 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
348 // CHECK1:       omp.inner.for.end:
349 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
350 // CHECK1:       omp.loop.exit:
351 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
352 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
353 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
354 // CHECK1-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
355 // CHECK1:       .omp.final.then:
356 // CHECK1-NEXT:    store i32 1000, ptr [[I]], align 4
357 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
358 // CHECK1:       .omp.final.done:
359 // CHECK1-NEXT:    ret void
360 //
361 //
362 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.omp_outlined.omp_outlined
363 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] {
364 // CHECK1-NEXT:  entry:
365 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
366 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
367 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
368 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
369 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
370 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
371 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
372 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
373 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
374 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
375 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
376 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
377 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
378 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
379 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
380 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
381 // CHECK1-NEXT:    store i32 999, ptr [[DOTOMP_UB]], align 4
382 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
383 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
384 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
385 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
386 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
387 // CHECK1-NEXT:    store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
388 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
389 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
390 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
391 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
392 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
393 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
394 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 999
395 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
396 // CHECK1:       cond.true:
397 // CHECK1-NEXT:    br label [[COND_END:%.*]]
398 // CHECK1:       cond.false:
399 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
400 // CHECK1-NEXT:    br label [[COND_END]]
401 // CHECK1:       cond.end:
402 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
403 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
404 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
405 // CHECK1-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
406 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
407 // CHECK1:       omp.inner.for.cond:
408 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]
409 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]
410 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
411 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
412 // CHECK1:       omp.inner.for.body:
413 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
414 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
415 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
416 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
417 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
418 // CHECK1:       omp.body.continue:
419 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
420 // CHECK1:       omp.inner.for.inc:
421 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
422 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
423 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
424 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
425 // CHECK1:       omp.inner.for.end:
426 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
427 // CHECK1:       omp.loop.exit:
428 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]])
429 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
430 // CHECK1-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
431 // CHECK1-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
432 // CHECK1:       .omp.final.then:
433 // CHECK1-NEXT:    store i32 1000, ptr [[I]], align 4
434 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
435 // CHECK1:       .omp.final.done:
436 // CHECK1-NEXT:    ret void
437 //
438 //
439 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
440 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] comdat {
441 // CHECK1-NEXT:  entry:
442 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
443 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
444 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
445 // CHECK1-NEXT:    store i32 3, ptr [[TMP0]], align 4
446 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
447 // CHECK1-NEXT:    store i32 0, ptr [[TMP1]], align 4
448 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
449 // CHECK1-NEXT:    store ptr null, ptr [[TMP2]], align 8
450 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
451 // CHECK1-NEXT:    store ptr null, ptr [[TMP3]], align 8
452 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
453 // CHECK1-NEXT:    store ptr null, ptr [[TMP4]], align 8
454 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
455 // CHECK1-NEXT:    store ptr null, ptr [[TMP5]], align 8
456 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
457 // CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8
458 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
459 // CHECK1-NEXT:    store ptr null, ptr [[TMP7]], align 8
460 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
461 // CHECK1-NEXT:    store i64 1000, ptr [[TMP8]], align 8
462 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
463 // CHECK1-NEXT:    store i64 0, ptr [[TMP9]], align 8
464 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
465 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
466 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
467 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
468 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
469 // CHECK1-NEXT:    store i32 0, ptr [[TMP12]], align 4
470 // CHECK1-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29.region_id, ptr [[KERNEL_ARGS]])
471 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
472 // CHECK1-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
473 // CHECK1:       omp_offload.failed:
474 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29() #[[ATTR2]]
475 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
476 // CHECK1:       omp_offload.cont:
477 // CHECK1-NEXT:    ret i32 0
478 //
479 //
480 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29
481 // CHECK1-SAME: () #[[ATTR1]] {
482 // CHECK1-NEXT:  entry:
483 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29.omp_outlined)
484 // CHECK1-NEXT:    ret void
485 //
486 //
487 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29.omp_outlined
488 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
489 // CHECK1-NEXT:  entry:
490 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
491 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
492 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
493 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
494 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
495 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
496 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
497 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
498 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
499 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
500 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
501 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
502 // CHECK1-NEXT:    store i32 999, ptr [[DOTOMP_COMB_UB]], align 4
503 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
504 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
505 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
506 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
507 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
508 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
509 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 999
510 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
511 // CHECK1:       cond.true:
512 // CHECK1-NEXT:    br label [[COND_END:%.*]]
513 // CHECK1:       cond.false:
514 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
515 // CHECK1-NEXT:    br label [[COND_END]]
516 // CHECK1:       cond.end:
517 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
518 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
519 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
520 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
521 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
522 // CHECK1:       omp.inner.for.cond:
523 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]]
524 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP21]]
525 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
526 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
527 // CHECK1:       omp.inner.for.body:
528 // CHECK1-NEXT:    call void @__kmpc_push_proc_bind(ptr @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group [[ACC_GRP21]]
529 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP21]]
530 // CHECK1-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
531 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP21]]
532 // CHECK1-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
533 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP21]]
534 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
535 // CHECK1:       omp.inner.for.inc:
536 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
537 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP21]]
538 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
539 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
540 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
541 // CHECK1:       omp.inner.for.end:
542 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
543 // CHECK1:       omp.loop.exit:
544 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
545 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
546 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
547 // CHECK1-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
548 // CHECK1:       .omp.final.then:
549 // CHECK1-NEXT:    store i32 1000, ptr [[I]], align 4
550 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
551 // CHECK1:       .omp.final.done:
552 // CHECK1-NEXT:    ret void
553 //
554 //
555 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29.omp_outlined.omp_outlined
556 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] {
557 // CHECK1-NEXT:  entry:
558 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
559 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
560 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
561 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
562 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
563 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
564 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
565 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
566 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
567 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
568 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
569 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
570 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
571 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
572 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
573 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
574 // CHECK1-NEXT:    store i32 999, ptr [[DOTOMP_UB]], align 4
575 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
576 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
577 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
578 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
579 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
580 // CHECK1-NEXT:    store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
581 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
582 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
583 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
584 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
585 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
586 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
587 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 999
588 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
589 // CHECK1:       cond.true:
590 // CHECK1-NEXT:    br label [[COND_END:%.*]]
591 // CHECK1:       cond.false:
592 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
593 // CHECK1-NEXT:    br label [[COND_END]]
594 // CHECK1:       cond.end:
595 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
596 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
597 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
598 // CHECK1-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
599 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
600 // CHECK1:       omp.inner.for.cond:
601 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]]
602 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]]
603 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
604 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
605 // CHECK1:       omp.inner.for.body:
606 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
607 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
608 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
609 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]]
610 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
611 // CHECK1:       omp.body.continue:
612 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
613 // CHECK1:       omp.inner.for.inc:
614 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
615 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
616 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
617 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
618 // CHECK1:       omp.inner.for.end:
619 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
620 // CHECK1:       omp.loop.exit:
621 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]])
622 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
623 // CHECK1-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
624 // CHECK1-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
625 // CHECK1:       .omp.final.then:
626 // CHECK1-NEXT:    store i32 1000, ptr [[I]], align 4
627 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
628 // CHECK1:       .omp.final.done:
629 // CHECK1-NEXT:    ret void
630 //
631 //
632 // CHECK3-LABEL: define {{[^@]+}}@main
633 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
634 // CHECK3-NEXT:  entry:
635 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
636 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
637 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
638 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
639 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
640 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
641 // CHECK3-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
642 // CHECK3-NEXT:    [[DOTOMP_LB3:%.*]] = alloca i32, align 4
643 // CHECK3-NEXT:    [[DOTOMP_UB4:%.*]] = alloca i32, align 4
644 // CHECK3-NEXT:    [[DOTOMP_IV5:%.*]] = alloca i32, align 4
645 // CHECK3-NEXT:    [[I6:%.*]] = alloca i32, align 4
646 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
647 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
648 // CHECK3-NEXT:    store i32 999, ptr [[DOTOMP_UB]], align 4
649 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
650 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
651 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
652 // CHECK3:       omp.inner.for.cond:
653 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
654 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]
655 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
656 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
657 // CHECK3:       omp.inner.for.body:
658 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
659 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
660 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
661 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
662 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
663 // CHECK3:       omp.body.continue:
664 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
665 // CHECK3:       omp.inner.for.inc:
666 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
667 // CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
668 // CHECK3-NEXT:    store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
669 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
670 // CHECK3:       omp.inner.for.end:
671 // CHECK3-NEXT:    store i32 1000, ptr [[I]], align 4
672 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB3]], align 4
673 // CHECK3-NEXT:    store i32 999, ptr [[DOTOMP_UB4]], align 4
674 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB3]], align 4
675 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV5]], align 4
676 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND7:%.*]]
677 // CHECK3:       omp.inner.for.cond7:
678 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
679 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB4]], align 4, !llvm.access.group [[ACC_GRP6]]
680 // CHECK3-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
681 // CHECK3-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]]
682 // CHECK3:       omp.inner.for.body9:
683 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP6]]
684 // CHECK3-NEXT:    [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1
685 // CHECK3-NEXT:    [[ADD11:%.*]] = add nsw i32 0, [[MUL10]]
686 // CHECK3-NEXT:    store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP6]]
687 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE12:%.*]]
688 // CHECK3:       omp.body.continue12:
689 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC13:%.*]]
690 // CHECK3:       omp.inner.for.inc13:
691 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP6]]
692 // CHECK3-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1
693 // CHECK3-NEXT:    store i32 [[ADD14]], ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP6]]
694 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP7:![0-9]+]]
695 // CHECK3:       omp.inner.for.end15:
696 // CHECK3-NEXT:    store i32 1000, ptr [[I6]], align 4
697 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
698 // CHECK3-NEXT:    ret i32 [[CALL]]
699 //
700 //
701 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
702 // CHECK3-SAME: () #[[ATTR1:[0-9]+]] comdat {
703 // CHECK3-NEXT:  entry:
704 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
705 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
706 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
707 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
708 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
709 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
710 // CHECK3-NEXT:    store i32 999, ptr [[DOTOMP_UB]], align 4
711 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
712 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
713 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
714 // CHECK3:       omp.inner.for.cond:
715 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]
716 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]
717 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
718 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
719 // CHECK3:       omp.inner.for.body:
720 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
721 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
722 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
723 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
724 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
725 // CHECK3:       omp.body.continue:
726 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
727 // CHECK3:       omp.inner.for.inc:
728 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
729 // CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
730 // CHECK3-NEXT:    store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
731 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
732 // CHECK3:       omp.inner.for.end:
733 // CHECK3-NEXT:    store i32 1000, ptr [[I]], align 4
734 // CHECK3-NEXT:    ret i32 0
735 //
736