1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 10 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 12 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 13 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 15 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 16 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 17 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 18 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10 19 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 20 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10 21 22 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 23 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 24 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 25 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 26 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 27 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 28 // expected-no-diagnostics 29 #ifndef HEADER 30 #define HEADER 31 32 template <class T> 33 struct S { 34 T f; 35 S(T a) : f(a) {} 36 S() : f() {} 37 operator T() { return T(); } 38 ~S() {} 39 }; 40 41 template <typename T> 42 T tmain() { 43 S<T> test; 44 T t_var = T(); 45 T vec[] = {1, 2}; 46 S<T> s_arr[] = {1, 2}; 47 S<T> &var = test; 48 #pragma omp target 49 #pragma omp teams 50 #pragma omp distribute parallel for firstprivate(t_var, vec, s_arr, s_arr, var, var) 51 for (int i = 0; i < 2; ++i) { 52 vec[i] = t_var; 53 s_arr[i] = var; 54 } 55 return T(); 56 } 57 58 int main() { 59 static int svar; 60 volatile double g; 61 volatile double &g1 = g; 62 63 #ifdef LAMBDA 64 [&]() { 65 static float sfvar; 66 67 #pragma omp target 68 #pragma omp teams 69 #pragma omp distribute parallel for firstprivate(g, g1, svar, sfvar) 70 for (int i = 0; i < 2; ++i) { 71 72 // addr alloca's 73 74 // private alloca's 75 76 // transfer input parameters into addr alloca's 77 78 79 // init private alloca's with addr alloca's 80 // g 81 82 // g1 83 84 // svar 85 86 // sfvar 87 88 // pass firstprivate parameters to parallel outlined function 89 // g 90 91 // g1 92 93 // svar 94 95 // sfvar 96 97 98 99 // skip initial params 100 101 // addr alloca's 102 103 // private alloca's (only for 32-bit) 104 105 // transfer input parameters into addr alloca's 106 107 // prepare parameters for lambda 108 // g 109 110 // g1 111 112 // svar 113 114 // sfvar 115 116 g = 1; 117 g1 = 1; 118 svar = 3; 119 sfvar = 4.0; 120 121 // pass params to inner lambda 122 [&]() { 123 g = 2; 124 g1 = 2; 125 svar = 4; 126 sfvar = 8.0; 127 128 }(); 129 } 130 }(); 131 return 0; 132 #else 133 S<float> test; 134 int t_var = 0; 135 int vec[] = {1, 2}; 136 S<float> s_arr[] = {1, 2}; 137 S<float> &var = test; 138 139 #pragma omp target 140 #pragma omp teams 141 #pragma omp distribute parallel for firstprivate(t_var, vec, s_arr, s_arr, var, var, svar) 142 for (int i = 0; i < 2; ++i) { 143 vec[i] = t_var; 144 s_arr[i] = var; 145 } 146 return tmain<int>(); 147 #endif 148 } 149 150 151 152 153 // addr alloca's 154 155 // skip loop alloca's 156 157 // private alloca's 158 159 160 // init addr alloca's with input values 161 162 // init private alloca's with addr alloca's 163 // t-var 164 165 // vec 166 167 // s_arr 168 169 // var 170 171 // svar 172 173 // pass private alloca's to fork 174 // not dag to distinguish with S_VAR_CAST 175 176 // call destructors: var.. 177 178 // ..and s_arr 179 180 181 // By OpenMP specifications, 'firstprivate' applies to both distribute and parallel for. 182 // However, the support for 'firstprivate' of 'parallel' is only used when 'parallel' 183 // is found alone. Therefore we only have one 'firstprivate' support for 'parallel for' 184 // in combination 185 186 // addr alloca's 187 188 // skip loop alloca's 189 190 // private alloca's 191 192 193 // init addr alloca's with input values 194 195 // init private alloca's with addr alloca's 196 // vec 197 198 // s_arr 199 200 // var 201 202 203 // call destructors: var.. 204 205 // ..and s_arr 206 207 208 // template tmain with S_INT_TY 209 210 211 212 // addr alloca's 213 214 // skip loop alloca's 215 216 // private alloca's 217 218 219 // init addr alloca's with input values 220 221 // init private alloca's with addr alloca's 222 // t-var 223 224 // vec 225 226 // s_arr 227 228 // var 229 230 // pass private alloca's to fork 231 // not dag to distinguish with S_VAR_CAST 232 233 // call destructors: var.. 234 235 // ..and s_arr 236 237 238 // By OpenMP specifications, 'firstprivate' applies to both distribute and parallel for. 239 // However, the support for 'firstprivate' of 'parallel' is only used when 'parallel' 240 // is found alone. Therefore we only have one 'firstprivate' support for 'parallel for' 241 // in combination 242 243 // addr alloca's 244 245 // skip loop alloca's 246 247 // private alloca's 248 249 250 // init addr alloca's with input values 251 252 // init private alloca's with addr alloca's 253 // vec 254 255 // s_arr 256 257 // var 258 259 260 // call destructors: var.. 261 262 // ..and s_arr 263 264 265 #endif 266 // CHECK1-LABEL: define {{[^@]+}}@main 267 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 268 // CHECK1-NEXT: entry: 269 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 270 // CHECK1-NEXT: [[G:%.*]] = alloca double, align 8 271 // CHECK1-NEXT: [[G1:%.*]] = alloca ptr, align 8 272 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 273 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 274 // CHECK1-NEXT: store ptr [[G]], ptr [[G1]], align 8 275 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 276 // CHECK1-NEXT: store ptr [[G]], ptr [[TMP0]], align 8 277 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 278 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8 279 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8 280 // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) 281 // CHECK1-NEXT: ret i32 0 282 // 283 // 284 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 285 // CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { 286 // CHECK1-NEXT: entry: 287 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 288 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 289 // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 290 // CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8 291 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 292 // CHECK1-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 293 // CHECK1-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 294 // CHECK1-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 295 // CHECK1-NEXT: store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 296 // CHECK1-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 297 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8 298 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, ptr [[G_ADDR]], ptr [[TMP0]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]]) 299 // CHECK1-NEXT: ret void 300 // 301 // 302 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined 303 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { 304 // CHECK1-NEXT: entry: 305 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 306 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 307 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8 308 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca ptr, align 8 309 // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca ptr, align 8 310 // CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca ptr, align 8 311 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 312 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 313 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 314 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 315 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 316 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 317 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 318 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 319 // CHECK1-NEXT: [[G3:%.*]] = alloca double, align 8 320 // CHECK1-NEXT: [[G14:%.*]] = alloca double, align 8 321 // CHECK1-NEXT: [[_TMP5:%.*]] = alloca ptr, align 8 322 // CHECK1-NEXT: [[SVAR6:%.*]] = alloca i32, align 4 323 // CHECK1-NEXT: [[SFVAR7:%.*]] = alloca float, align 4 324 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 325 // CHECK1-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 326 // CHECK1-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 327 // CHECK1-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 328 // CHECK1-NEXT: [[SFVAR_CASTED:%.*]] = alloca i64, align 8 329 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 330 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 331 // CHECK1-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8 332 // CHECK1-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 8 333 // CHECK1-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 334 // CHECK1-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 335 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8 336 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8 337 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 338 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8 339 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 340 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 341 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8 342 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 343 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 344 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 345 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 346 // CHECK1-NEXT: [[TMP5:%.*]] = load double, ptr [[TMP0]], align 8 347 // CHECK1-NEXT: store double [[TMP5]], ptr [[G3]], align 8 348 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8 349 // CHECK1-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8 350 // CHECK1-NEXT: store double [[TMP7]], ptr [[G14]], align 8 351 // CHECK1-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 8 352 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP2]], align 4 353 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[SVAR6]], align 4 354 // CHECK1-NEXT: [[TMP9:%.*]] = load float, ptr [[TMP3]], align 4 355 // CHECK1-NEXT: store float [[TMP9]], ptr [[SFVAR7]], align 4 356 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 357 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 358 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 359 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 360 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 361 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 362 // CHECK1: cond.true: 363 // CHECK1-NEXT: br label [[COND_END:%.*]] 364 // CHECK1: cond.false: 365 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 366 // CHECK1-NEXT: br label [[COND_END]] 367 // CHECK1: cond.end: 368 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] 369 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 370 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 371 // CHECK1-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4 372 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 373 // CHECK1: omp.inner.for.cond: 374 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 375 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 376 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 377 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 378 // CHECK1: omp.inner.for.body: 379 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 380 // CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 381 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 382 // CHECK1-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 383 // CHECK1-NEXT: [[TMP21:%.*]] = load double, ptr [[G3]], align 8 384 // CHECK1-NEXT: store double [[TMP21]], ptr [[G_CASTED]], align 8 385 // CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[G_CASTED]], align 8 386 // CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[_TMP5]], align 8 387 // CHECK1-NEXT: [[TMP24:%.*]] = load volatile double, ptr [[TMP23]], align 8 388 // CHECK1-NEXT: store double [[TMP24]], ptr [[G1_CASTED]], align 8 389 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[G1_CASTED]], align 8 390 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[SVAR6]], align 4 391 // CHECK1-NEXT: store i32 [[TMP26]], ptr [[SVAR_CASTED]], align 4 392 // CHECK1-NEXT: [[TMP27:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8 393 // CHECK1-NEXT: [[TMP28:%.*]] = load float, ptr [[SFVAR7]], align 4 394 // CHECK1-NEXT: store float [[TMP28]], ptr [[SFVAR_CASTED]], align 4 395 // CHECK1-NEXT: [[TMP29:%.*]] = load i64, ptr [[SFVAR_CASTED]], align 8 396 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined, i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP25]], i64 [[TMP27]], i64 [[TMP29]]) 397 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 398 // CHECK1: omp.inner.for.inc: 399 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 400 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 401 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 402 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 403 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 404 // CHECK1: omp.inner.for.end: 405 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 406 // CHECK1: omp.loop.exit: 407 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP11]]) 408 // CHECK1-NEXT: ret void 409 // 410 // 411 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined 412 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2]] { 413 // CHECK1-NEXT: entry: 414 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 415 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 416 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 417 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 418 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 419 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 420 // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 421 // CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8 422 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 423 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 424 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 425 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 426 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 427 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 428 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 429 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 430 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 431 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 432 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 433 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 434 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 435 // CHECK1-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 436 // CHECK1-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 437 // CHECK1-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 438 // CHECK1-NEXT: store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 439 // CHECK1-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 440 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 441 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 442 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 443 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 444 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 445 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 446 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 447 // CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 448 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 449 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 450 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 451 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 452 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 453 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 454 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 455 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 456 // CHECK1: cond.true: 457 // CHECK1-NEXT: br label [[COND_END:%.*]] 458 // CHECK1: cond.false: 459 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 460 // CHECK1-NEXT: br label [[COND_END]] 461 // CHECK1: cond.end: 462 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 463 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 464 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 465 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 466 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 467 // CHECK1: omp.inner.for.cond: 468 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 469 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 470 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 471 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 472 // CHECK1: omp.inner.for.body: 473 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 474 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 475 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 476 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 477 // CHECK1-NEXT: store double 1.000000e+00, ptr [[G_ADDR]], align 8 478 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP]], align 8 479 // CHECK1-NEXT: store volatile double 1.000000e+00, ptr [[TMP10]], align 8 480 // CHECK1-NEXT: store i32 3, ptr [[SVAR_ADDR]], align 4 481 // CHECK1-NEXT: store float 4.000000e+00, ptr [[SFVAR_ADDR]], align 4 482 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 483 // CHECK1-NEXT: store ptr [[G_ADDR]], ptr [[TMP11]], align 8 484 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 485 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8 486 // CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 487 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 488 // CHECK1-NEXT: store ptr [[SVAR_ADDR]], ptr [[TMP14]], align 8 489 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3 490 // CHECK1-NEXT: store ptr [[SFVAR_ADDR]], ptr [[TMP15]], align 8 491 // CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) 492 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 493 // CHECK1: omp.body.continue: 494 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 495 // CHECK1: omp.inner.for.inc: 496 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 497 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP16]], 1 498 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 499 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 500 // CHECK1: omp.inner.for.end: 501 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 502 // CHECK1: omp.loop.exit: 503 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) 504 // CHECK1-NEXT: ret void 505 // 506 // 507 // CHECK3-LABEL: define {{[^@]+}}@main 508 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 509 // CHECK3-NEXT: entry: 510 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 511 // CHECK3-NEXT: [[G:%.*]] = alloca double, align 8 512 // CHECK3-NEXT: [[G1:%.*]] = alloca ptr, align 4 513 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 514 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 515 // CHECK3-NEXT: store ptr [[G]], ptr [[G1]], align 4 516 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 517 // CHECK3-NEXT: store ptr [[G]], ptr [[TMP0]], align 4 518 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 519 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4 520 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 4 521 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]]) 522 // CHECK3-NEXT: ret i32 0 523 // 524 // 525 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 526 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { 527 // CHECK3-NEXT: entry: 528 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4 529 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca ptr, align 4 530 // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 531 // CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4 532 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 533 // CHECK3-NEXT: [[G2:%.*]] = alloca double, align 8 534 // CHECK3-NEXT: [[G13:%.*]] = alloca double, align 8 535 // CHECK3-NEXT: [[_TMP4:%.*]] = alloca ptr, align 4 536 // CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4 537 // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 538 // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 539 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 540 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 541 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 542 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 543 // CHECK3-NEXT: [[TMP2:%.*]] = load double, ptr [[TMP0]], align 8 544 // CHECK3-NEXT: store double [[TMP2]], ptr [[G2]], align 8 545 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 546 // CHECK3-NEXT: [[TMP4:%.*]] = load volatile double, ptr [[TMP3]], align 4 547 // CHECK3-NEXT: store double [[TMP4]], ptr [[G13]], align 8 548 // CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4 549 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP4]], align 4 550 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, ptr [[G2]], ptr [[TMP5]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]]) 551 // CHECK3-NEXT: ret void 552 // 553 // 554 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined 555 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { 556 // CHECK3-NEXT: entry: 557 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 558 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 559 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4 560 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca ptr, align 4 561 // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca ptr, align 4 562 // CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca ptr, align 4 563 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 564 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 565 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 566 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 567 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 568 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 569 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 570 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 571 // CHECK3-NEXT: [[G3:%.*]] = alloca double, align 8 572 // CHECK3-NEXT: [[G14:%.*]] = alloca double, align 8 573 // CHECK3-NEXT: [[_TMP5:%.*]] = alloca ptr, align 4 574 // CHECK3-NEXT: [[SVAR6:%.*]] = alloca i32, align 4 575 // CHECK3-NEXT: [[SFVAR7:%.*]] = alloca float, align 4 576 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 577 // CHECK3-NEXT: [[G1_CASTED:%.*]] = alloca i32, align 4 578 // CHECK3-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 579 // CHECK3-NEXT: [[SFVAR_CASTED:%.*]] = alloca i32, align 4 580 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 581 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 582 // CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4 583 // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 584 // CHECK3-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 585 // CHECK3-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 586 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 587 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 588 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 589 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4 590 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 591 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 592 // CHECK3-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 4 593 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 594 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 595 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 596 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 597 // CHECK3-NEXT: [[TMP5:%.*]] = load double, ptr [[TMP0]], align 8 598 // CHECK3-NEXT: store double [[TMP5]], ptr [[G3]], align 8 599 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4 600 // CHECK3-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 4 601 // CHECK3-NEXT: store double [[TMP7]], ptr [[G14]], align 8 602 // CHECK3-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 4 603 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP2]], align 4 604 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[SVAR6]], align 4 605 // CHECK3-NEXT: [[TMP9:%.*]] = load float, ptr [[TMP3]], align 4 606 // CHECK3-NEXT: store float [[TMP9]], ptr [[SFVAR7]], align 4 607 // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 608 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 609 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 610 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 611 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 612 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 613 // CHECK3: cond.true: 614 // CHECK3-NEXT: br label [[COND_END:%.*]] 615 // CHECK3: cond.false: 616 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 617 // CHECK3-NEXT: br label [[COND_END]] 618 // CHECK3: cond.end: 619 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] 620 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 621 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 622 // CHECK3-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4 623 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 624 // CHECK3: omp.inner.for.cond: 625 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 626 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 627 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 628 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 629 // CHECK3: omp.inner.for.body: 630 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 631 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 632 // CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP5]], align 4 633 // CHECK3-NEXT: [[TMP20:%.*]] = load volatile double, ptr [[TMP19]], align 4 634 // CHECK3-NEXT: store double [[TMP20]], ptr [[G1_CASTED]], align 4 635 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[G1_CASTED]], align 4 636 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[SVAR6]], align 4 637 // CHECK3-NEXT: store i32 [[TMP22]], ptr [[SVAR_CASTED]], align 4 638 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 639 // CHECK3-NEXT: [[TMP24:%.*]] = load float, ptr [[SFVAR7]], align 4 640 // CHECK3-NEXT: store float [[TMP24]], ptr [[SFVAR_CASTED]], align 4 641 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, ptr [[SFVAR_CASTED]], align 4 642 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined, i32 [[TMP17]], i32 [[TMP18]], ptr [[G3]], i32 [[TMP21]], i32 [[TMP23]], i32 [[TMP25]]) 643 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 644 // CHECK3: omp.inner.for.inc: 645 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 646 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 647 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] 648 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 649 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 650 // CHECK3: omp.inner.for.end: 651 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 652 // CHECK3: omp.loop.exit: 653 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP11]]) 654 // CHECK3-NEXT: ret void 655 // 656 // 657 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined 658 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]], i32 noundef [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2]] { 659 // CHECK3-NEXT: entry: 660 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 661 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 662 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 663 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 664 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4 665 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca i32, align 4 666 // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 667 // CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4 668 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 669 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 670 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 671 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 672 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 673 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 674 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 675 // CHECK3-NEXT: [[G2:%.*]] = alloca double, align 8 676 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 677 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 678 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 679 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 680 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 681 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 682 // CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4 683 // CHECK3-NEXT: store i32 [[G1]], ptr [[G1_ADDR]], align 4 684 // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 685 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 686 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 687 // CHECK3-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 4 688 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 689 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 690 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 691 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 692 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4 693 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 694 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 695 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 696 // CHECK3-NEXT: [[TMP3:%.*]] = load double, ptr [[TMP0]], align 8 697 // CHECK3-NEXT: store double [[TMP3]], ptr [[G2]], align 8 698 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 699 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 700 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 701 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 702 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 703 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 704 // CHECK3: cond.true: 705 // CHECK3-NEXT: br label [[COND_END:%.*]] 706 // CHECK3: cond.false: 707 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 708 // CHECK3-NEXT: br label [[COND_END]] 709 // CHECK3: cond.end: 710 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 711 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 712 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 713 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 714 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 715 // CHECK3: omp.inner.for.cond: 716 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 717 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 718 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 719 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 720 // CHECK3: omp.inner.for.body: 721 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 722 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 723 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 724 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 725 // CHECK3-NEXT: store double 1.000000e+00, ptr [[G2]], align 8 726 // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP]], align 4 727 // CHECK3-NEXT: store volatile double 1.000000e+00, ptr [[TMP12]], align 4 728 // CHECK3-NEXT: store i32 3, ptr [[SVAR_ADDR]], align 4 729 // CHECK3-NEXT: store float 4.000000e+00, ptr [[SFVAR_ADDR]], align 4 730 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 731 // CHECK3-NEXT: store ptr [[G2]], ptr [[TMP13]], align 4 732 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 733 // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP]], align 4 734 // CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 4 735 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 736 // CHECK3-NEXT: store ptr [[SVAR_ADDR]], ptr [[TMP16]], align 4 737 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3 738 // CHECK3-NEXT: store ptr [[SFVAR_ADDR]], ptr [[TMP17]], align 4 739 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 4 dereferenceable(16) [[REF_TMP]]) 740 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 741 // CHECK3: omp.body.continue: 742 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 743 // CHECK3: omp.inner.for.inc: 744 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 745 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], 1 746 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 747 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 748 // CHECK3: omp.inner.for.end: 749 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 750 // CHECK3: omp.loop.exit: 751 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP5]]) 752 // CHECK3-NEXT: ret void 753 // 754 // 755 // CHECK8-LABEL: define {{[^@]+}}@main 756 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { 757 // CHECK8-NEXT: entry: 758 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 759 // CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 760 // CHECK8-NEXT: [[G1:%.*]] = alloca ptr, align 8 761 // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 762 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 763 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 764 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 765 // CHECK8-NEXT: [[VAR:%.*]] = alloca ptr, align 8 766 // CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 8 767 // CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 768 // CHECK8-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 769 // CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 770 // CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 771 // CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 772 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 773 // CHECK8-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 774 // CHECK8-NEXT: store i32 0, ptr [[RETVAL]], align 4 775 // CHECK8-NEXT: store ptr [[G]], ptr [[G1]], align 8 776 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 777 // CHECK8-NEXT: store i32 0, ptr [[T_VAR]], align 4 778 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false) 779 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00) 780 // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1 781 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) 782 // CHECK8-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 783 // CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 784 // CHECK8-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 785 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 786 // CHECK8-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 787 // CHECK8-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 788 // CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 789 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 790 // CHECK8-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 791 // CHECK8-NEXT: [[TMP5:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8 792 // CHECK8-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 793 // CHECK8-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8 794 // CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 795 // CHECK8-NEXT: store i64 [[TMP2]], ptr [[TMP8]], align 8 796 // CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 797 // CHECK8-NEXT: store i64 [[TMP2]], ptr [[TMP9]], align 8 798 // CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 799 // CHECK8-NEXT: store ptr null, ptr [[TMP10]], align 8 800 // CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 801 // CHECK8-NEXT: store ptr [[VEC]], ptr [[TMP11]], align 8 802 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 803 // CHECK8-NEXT: store ptr [[VEC]], ptr [[TMP12]], align 8 804 // CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 805 // CHECK8-NEXT: store ptr null, ptr [[TMP13]], align 8 806 // CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 807 // CHECK8-NEXT: store ptr [[S_ARR]], ptr [[TMP14]], align 8 808 // CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 809 // CHECK8-NEXT: store ptr [[S_ARR]], ptr [[TMP15]], align 8 810 // CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 811 // CHECK8-NEXT: store ptr null, ptr [[TMP16]], align 8 812 // CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 813 // CHECK8-NEXT: store ptr [[TMP6]], ptr [[TMP17]], align 8 814 // CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 815 // CHECK8-NEXT: store ptr [[TMP7]], ptr [[TMP18]], align 8 816 // CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 817 // CHECK8-NEXT: store ptr null, ptr [[TMP19]], align 8 818 // CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 819 // CHECK8-NEXT: store i64 [[TMP5]], ptr [[TMP20]], align 8 820 // CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 821 // CHECK8-NEXT: store i64 [[TMP5]], ptr [[TMP21]], align 8 822 // CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 823 // CHECK8-NEXT: store ptr null, ptr [[TMP22]], align 8 824 // CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 825 // CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 826 // CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 827 // CHECK8-NEXT: store i32 3, ptr [[TMP25]], align 4 828 // CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 829 // CHECK8-NEXT: store i32 5, ptr [[TMP26]], align 4 830 // CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 831 // CHECK8-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 8 832 // CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 833 // CHECK8-NEXT: store ptr [[TMP24]], ptr [[TMP28]], align 8 834 // CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 835 // CHECK8-NEXT: store ptr @.offload_sizes, ptr [[TMP29]], align 8 836 // CHECK8-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 837 // CHECK8-NEXT: store ptr @.offload_maptypes, ptr [[TMP30]], align 8 838 // CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 839 // CHECK8-NEXT: store ptr null, ptr [[TMP31]], align 8 840 // CHECK8-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 841 // CHECK8-NEXT: store ptr null, ptr [[TMP32]], align 8 842 // CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 843 // CHECK8-NEXT: store i64 2, ptr [[TMP33]], align 8 844 // CHECK8-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 845 // CHECK8-NEXT: store i64 0, ptr [[TMP34]], align 8 846 // CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 847 // CHECK8-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4 848 // CHECK8-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 849 // CHECK8-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP36]], align 4 850 // CHECK8-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 851 // CHECK8-NEXT: store i32 0, ptr [[TMP37]], align 4 852 // CHECK8-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.region_id, ptr [[KERNEL_ARGS]]) 853 // CHECK8-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 854 // CHECK8-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 855 // CHECK8: omp_offload.failed: 856 // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]], i64 [[TMP5]]) #[[ATTR4:[0-9]+]] 857 // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] 858 // CHECK8: omp_offload.cont: 859 // CHECK8-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 860 // CHECK8-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 861 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 862 // CHECK8-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 863 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 864 // CHECK8: arraydestroy.body: 865 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 866 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 867 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 868 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 869 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 870 // CHECK8: arraydestroy.done2: 871 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 872 // CHECK8-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 873 // CHECK8-NEXT: ret i32 [[TMP41]] 874 // 875 // 876 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 877 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 878 // CHECK8-NEXT: entry: 879 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 880 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 881 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 882 // CHECK8-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 883 // CHECK8-NEXT: ret void 884 // 885 // 886 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 887 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 888 // CHECK8-NEXT: entry: 889 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 890 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 891 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 892 // CHECK8-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 893 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 894 // CHECK8-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 895 // CHECK8-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 896 // CHECK8-NEXT: ret void 897 // 898 // 899 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 900 // CHECK8-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { 901 // CHECK8-NEXT: entry: 902 // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 903 // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 904 // CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 905 // CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 906 // CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 907 // CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 8 908 // CHECK8-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 909 // CHECK8-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 910 // CHECK8-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 911 // CHECK8-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 912 // CHECK8-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 913 // CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 914 // CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 915 // CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 916 // CHECK8-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 917 // CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 918 // CHECK8-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]]) 919 // CHECK8-NEXT: ret void 920 // 921 // 922 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.omp_outlined 923 // CHECK8-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { 924 // CHECK8-NEXT: entry: 925 // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 926 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 927 // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 928 // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 929 // CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 930 // CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 931 // CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca ptr, align 8 932 // CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 8 933 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 934 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 935 // CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 936 // CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 937 // CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 938 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 939 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 940 // CHECK8-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 941 // CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 942 // CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 943 // CHECK8-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 944 // CHECK8-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 945 // CHECK8-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 946 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 947 // CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 948 // CHECK8-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 949 // CHECK8-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 950 // CHECK8-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 951 // CHECK8-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 952 // CHECK8-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 953 // CHECK8-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 954 // CHECK8-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 955 // CHECK8-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 956 // CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 957 // CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 958 // CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 959 // CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 960 // CHECK8-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 961 // CHECK8-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 962 // CHECK8-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 963 // CHECK8-NEXT: store ptr [[TMP5]], ptr [[_TMP1]], align 8 964 // CHECK8-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 965 // CHECK8-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 966 // CHECK8-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 967 // CHECK8-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 968 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4 969 // CHECK8-NEXT: store i32 [[TMP6]], ptr [[T_VAR3]], align 4 970 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false) 971 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 972 // CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 973 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]] 974 // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 975 // CHECK8: omp.arraycpy.body: 976 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 977 // CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 978 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false) 979 // CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 980 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 981 // CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]] 982 // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] 983 // CHECK8: omp.arraycpy.done6: 984 // CHECK8-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8 985 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR7]], ptr align 4 [[TMP8]], i64 4, i1 false) 986 // CHECK8-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 8 987 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP4]], align 4 988 // CHECK8-NEXT: store i32 [[TMP9]], ptr [[SVAR9]], align 4 989 // CHECK8-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 990 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 991 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 992 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 993 // CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 994 // CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 995 // CHECK8: cond.true: 996 // CHECK8-NEXT: br label [[COND_END:%.*]] 997 // CHECK8: cond.false: 998 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 999 // CHECK8-NEXT: br label [[COND_END]] 1000 // CHECK8: cond.end: 1001 // CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] 1002 // CHECK8-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1003 // CHECK8-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1004 // CHECK8-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4 1005 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1006 // CHECK8: omp.inner.for.cond: 1007 // CHECK8-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1008 // CHECK8-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1009 // CHECK8-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 1010 // CHECK8-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1011 // CHECK8: omp.inner.for.cond.cleanup: 1012 // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1013 // CHECK8: omp.inner.for.body: 1014 // CHECK8-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1015 // CHECK8-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 1016 // CHECK8-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1017 // CHECK8-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 1018 // CHECK8-NEXT: [[TMP21:%.*]] = load i32, ptr [[T_VAR3]], align 4 1019 // CHECK8-NEXT: store i32 [[TMP21]], ptr [[T_VAR_CASTED]], align 4 1020 // CHECK8-NEXT: [[TMP22:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 1021 // CHECK8-NEXT: [[TMP23:%.*]] = load ptr, ptr [[_TMP8]], align 8 1022 // CHECK8-NEXT: [[TMP24:%.*]] = load i32, ptr [[SVAR9]], align 4 1023 // CHECK8-NEXT: store i32 [[TMP24]], ptr [[SVAR_CASTED]], align 4 1024 // CHECK8-NEXT: [[TMP25:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8 1025 // CHECK8-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.omp_outlined.omp_outlined, i64 [[TMP18]], i64 [[TMP20]], ptr [[VEC4]], i64 [[TMP22]], ptr [[S_ARR5]], ptr [[TMP23]], i64 [[TMP25]]) 1026 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1027 // CHECK8: omp.inner.for.inc: 1028 // CHECK8-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1029 // CHECK8-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1030 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] 1031 // CHECK8-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 1032 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] 1033 // CHECK8: omp.inner.for.end: 1034 // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1035 // CHECK8: omp.loop.exit: 1036 // CHECK8-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1037 // CHECK8-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4 1038 // CHECK8-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP29]]) 1039 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] 1040 // CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 1041 // CHECK8-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 1042 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1043 // CHECK8: arraydestroy.body: 1044 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1045 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1046 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1047 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 1048 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 1049 // CHECK8: arraydestroy.done12: 1050 // CHECK8-NEXT: ret void 1051 // 1052 // 1053 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.omp_outlined.omp_outlined 1054 // CHECK8-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] { 1055 // CHECK8-NEXT: entry: 1056 // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1057 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1058 // CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1059 // CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1060 // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 1061 // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1062 // CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 1063 // CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 1064 // CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 1065 // CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1066 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1067 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1068 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1069 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1070 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1071 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1072 // CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 1073 // CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 1074 // CHECK8-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1075 // CHECK8-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 1076 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 1077 // CHECK8-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1078 // CHECK8-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1079 // CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1080 // CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1081 // CHECK8-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 1082 // CHECK8-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 1083 // CHECK8-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 1084 // CHECK8-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 1085 // CHECK8-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 1086 // CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 1087 // CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 1088 // CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 1089 // CHECK8-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 1090 // CHECK8-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1091 // CHECK8-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1092 // CHECK8-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1093 // CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 1094 // CHECK8-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1095 // CHECK8-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32 1096 // CHECK8-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1097 // CHECK8-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 1098 // CHECK8-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1099 // CHECK8-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1100 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false) 1101 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 1102 // CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 1103 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 1104 // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1105 // CHECK8: omp.arraycpy.body: 1106 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1107 // CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1108 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false) 1109 // CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1110 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1111 // CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 1112 // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]] 1113 // CHECK8: omp.arraycpy.done5: 1114 // CHECK8-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 1115 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR6]], ptr align 4 [[TMP6]], i64 4, i1 false) 1116 // CHECK8-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 1117 // CHECK8-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1118 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1119 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1120 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1121 // CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 1122 // CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1123 // CHECK8: cond.true: 1124 // CHECK8-NEXT: br label [[COND_END:%.*]] 1125 // CHECK8: cond.false: 1126 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1127 // CHECK8-NEXT: br label [[COND_END]] 1128 // CHECK8: cond.end: 1129 // CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 1130 // CHECK8-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1131 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1132 // CHECK8-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 1133 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1134 // CHECK8: omp.inner.for.cond: 1135 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1136 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1137 // CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 1138 // CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1139 // CHECK8: omp.inner.for.cond.cleanup: 1140 // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1141 // CHECK8: omp.inner.for.body: 1142 // CHECK8-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1143 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 1144 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1145 // CHECK8-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1146 // CHECK8-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1147 // CHECK8-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 1148 // CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 1149 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] 1150 // CHECK8-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 1151 // CHECK8-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8 1152 // CHECK8-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 1153 // CHECK8-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 1154 // CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] 1155 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false) 1156 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1157 // CHECK8: omp.body.continue: 1158 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1159 // CHECK8: omp.inner.for.inc: 1160 // CHECK8-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1161 // CHECK8-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP19]], 1 1162 // CHECK8-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4 1163 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] 1164 // CHECK8: omp.inner.for.end: 1165 // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1166 // CHECK8: omp.loop.exit: 1167 // CHECK8-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1168 // CHECK8-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 1169 // CHECK8-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 1170 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] 1171 // CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 1172 // CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 1173 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1174 // CHECK8: arraydestroy.body: 1175 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1176 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1177 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1178 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 1179 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 1180 // CHECK8: arraydestroy.done13: 1181 // CHECK8-NEXT: ret void 1182 // 1183 // 1184 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1185 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1186 // CHECK8-NEXT: entry: 1187 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1188 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1189 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1190 // CHECK8-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1191 // CHECK8-NEXT: ret void 1192 // 1193 // 1194 // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1195 // CHECK8-SAME: () #[[ATTR1]] comdat { 1196 // CHECK8-NEXT: entry: 1197 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1198 // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1199 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1200 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1201 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1202 // CHECK8-NEXT: [[VAR:%.*]] = alloca ptr, align 8 1203 // CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1204 // CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1205 // CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 1206 // CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 1207 // CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 1208 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1209 // CHECK8-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1210 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1211 // CHECK8-NEXT: store i32 0, ptr [[T_VAR]], align 4 1212 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 1213 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 1214 // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 1215 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 1216 // CHECK8-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 1217 // CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 1218 // CHECK8-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 1219 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 1220 // CHECK8-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 1221 // CHECK8-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 1222 // CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 1223 // CHECK8-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 1224 // CHECK8-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 1225 // CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1226 // CHECK8-NEXT: store i64 [[TMP2]], ptr [[TMP6]], align 8 1227 // CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1228 // CHECK8-NEXT: store i64 [[TMP2]], ptr [[TMP7]], align 8 1229 // CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1230 // CHECK8-NEXT: store ptr null, ptr [[TMP8]], align 8 1231 // CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1232 // CHECK8-NEXT: store ptr [[VEC]], ptr [[TMP9]], align 8 1233 // CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1234 // CHECK8-NEXT: store ptr [[VEC]], ptr [[TMP10]], align 8 1235 // CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1236 // CHECK8-NEXT: store ptr null, ptr [[TMP11]], align 8 1237 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1238 // CHECK8-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 8 1239 // CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1240 // CHECK8-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 8 1241 // CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1242 // CHECK8-NEXT: store ptr null, ptr [[TMP14]], align 8 1243 // CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1244 // CHECK8-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 8 1245 // CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1246 // CHECK8-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 8 1247 // CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1248 // CHECK8-NEXT: store ptr null, ptr [[TMP17]], align 8 1249 // CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1250 // CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1251 // CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1252 // CHECK8-NEXT: store i32 3, ptr [[TMP20]], align 4 1253 // CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1254 // CHECK8-NEXT: store i32 4, ptr [[TMP21]], align 4 1255 // CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1256 // CHECK8-NEXT: store ptr [[TMP18]], ptr [[TMP22]], align 8 1257 // CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1258 // CHECK8-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8 1259 // CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1260 // CHECK8-NEXT: store ptr @.offload_sizes.1, ptr [[TMP24]], align 8 1261 // CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1262 // CHECK8-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP25]], align 8 1263 // CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1264 // CHECK8-NEXT: store ptr null, ptr [[TMP26]], align 8 1265 // CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1266 // CHECK8-NEXT: store ptr null, ptr [[TMP27]], align 8 1267 // CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1268 // CHECK8-NEXT: store i64 2, ptr [[TMP28]], align 8 1269 // CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1270 // CHECK8-NEXT: store i64 0, ptr [[TMP29]], align 8 1271 // CHECK8-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1272 // CHECK8-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4 1273 // CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1274 // CHECK8-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 1275 // CHECK8-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1276 // CHECK8-NEXT: store i32 0, ptr [[TMP32]], align 4 1277 // CHECK8-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.region_id, ptr [[KERNEL_ARGS]]) 1278 // CHECK8-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 1279 // CHECK8-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1280 // CHECK8: omp_offload.failed: 1281 // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]] 1282 // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] 1283 // CHECK8: omp_offload.cont: 1284 // CHECK8-NEXT: store i32 0, ptr [[RETVAL]], align 4 1285 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1286 // CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 1287 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1288 // CHECK8: arraydestroy.body: 1289 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1290 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1291 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1292 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1293 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1294 // CHECK8: arraydestroy.done2: 1295 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 1296 // CHECK8-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 1297 // CHECK8-NEXT: ret i32 [[TMP36]] 1298 // 1299 // 1300 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1301 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1302 // CHECK8-NEXT: entry: 1303 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1304 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1305 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1306 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1307 // CHECK8-NEXT: store float 0.000000e+00, ptr [[F]], align 4 1308 // CHECK8-NEXT: ret void 1309 // 1310 // 1311 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1312 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1313 // CHECK8-NEXT: entry: 1314 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1315 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1316 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1317 // CHECK8-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1318 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1319 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1320 // CHECK8-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1321 // CHECK8-NEXT: store float [[TMP0]], ptr [[F]], align 4 1322 // CHECK8-NEXT: ret void 1323 // 1324 // 1325 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1326 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1327 // CHECK8-NEXT: entry: 1328 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1329 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1330 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1331 // CHECK8-NEXT: ret void 1332 // 1333 // 1334 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1335 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1336 // CHECK8-NEXT: entry: 1337 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1338 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1339 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1340 // CHECK8-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1341 // CHECK8-NEXT: ret void 1342 // 1343 // 1344 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1345 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1346 // CHECK8-NEXT: entry: 1347 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1348 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1349 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1350 // CHECK8-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1351 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1352 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1353 // CHECK8-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 1354 // CHECK8-NEXT: ret void 1355 // 1356 // 1357 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48 1358 // CHECK8-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 1359 // CHECK8-NEXT: entry: 1360 // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1361 // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 1362 // CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 1363 // CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 1364 // CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1365 // CHECK8-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 1366 // CHECK8-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 1367 // CHECK8-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 1368 // CHECK8-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 1369 // CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 1370 // CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 1371 // CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 1372 // CHECK8-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 1373 // CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 1374 // CHECK8-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]]) 1375 // CHECK8-NEXT: ret void 1376 // 1377 // 1378 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined 1379 // CHECK8-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 1380 // CHECK8-NEXT: entry: 1381 // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1382 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1383 // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 1384 // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 1385 // CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 1386 // CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 1387 // CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1388 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1389 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1390 // CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 1391 // CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1392 // CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1393 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1394 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1395 // CHECK8-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 1396 // CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 1397 // CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 1398 // CHECK8-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1399 // CHECK8-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 1400 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 1401 // CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1402 // CHECK8-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1403 // CHECK8-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1404 // CHECK8-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 1405 // CHECK8-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 1406 // CHECK8-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 1407 // CHECK8-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 1408 // CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 1409 // CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 1410 // CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 1411 // CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 1412 // CHECK8-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 1413 // CHECK8-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 1414 // CHECK8-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8 1415 // CHECK8-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1416 // CHECK8-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1417 // CHECK8-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1418 // CHECK8-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1419 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 1420 // CHECK8-NEXT: store i32 [[TMP5]], ptr [[T_VAR3]], align 4 1421 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false) 1422 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 1423 // CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 1424 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]] 1425 // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1426 // CHECK8: omp.arraycpy.body: 1427 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1428 // CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1429 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false) 1430 // CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1431 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1432 // CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 1433 // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] 1434 // CHECK8: omp.arraycpy.done6: 1435 // CHECK8-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 8 1436 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR7]], ptr align 4 [[TMP7]], i64 4, i1 false) 1437 // CHECK8-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 8 1438 // CHECK8-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1439 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 1440 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1441 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1442 // CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 1443 // CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1444 // CHECK8: cond.true: 1445 // CHECK8-NEXT: br label [[COND_END:%.*]] 1446 // CHECK8: cond.false: 1447 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1448 // CHECK8-NEXT: br label [[COND_END]] 1449 // CHECK8: cond.end: 1450 // CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 1451 // CHECK8-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1452 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1453 // CHECK8-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 1454 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1455 // CHECK8: omp.inner.for.cond: 1456 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1457 // CHECK8-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1458 // CHECK8-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 1459 // CHECK8-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1460 // CHECK8: omp.inner.for.cond.cleanup: 1461 // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1462 // CHECK8: omp.inner.for.body: 1463 // CHECK8-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1464 // CHECK8-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 1465 // CHECK8-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1466 // CHECK8-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 1467 // CHECK8-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR3]], align 4 1468 // CHECK8-NEXT: store i32 [[TMP19]], ptr [[T_VAR_CASTED]], align 4 1469 // CHECK8-NEXT: [[TMP20:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 1470 // CHECK8-NEXT: [[TMP21:%.*]] = load ptr, ptr [[_TMP8]], align 8 1471 // CHECK8-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined.omp_outlined, i64 [[TMP16]], i64 [[TMP18]], ptr [[VEC4]], i64 [[TMP20]], ptr [[S_ARR5]], ptr [[TMP21]]) 1472 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1473 // CHECK8: omp.inner.for.inc: 1474 // CHECK8-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1475 // CHECK8-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1476 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] 1477 // CHECK8-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 1478 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] 1479 // CHECK8: omp.inner.for.end: 1480 // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1481 // CHECK8: omp.loop.exit: 1482 // CHECK8-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1483 // CHECK8-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4 1484 // CHECK8-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP25]]) 1485 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] 1486 // CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 1487 // CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 1488 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1489 // CHECK8: arraydestroy.body: 1490 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1491 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1492 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1493 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 1494 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 1495 // CHECK8: arraydestroy.done11: 1496 // CHECK8-NEXT: ret void 1497 // 1498 // 1499 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined.omp_outlined 1500 // CHECK8-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 1501 // CHECK8-NEXT: entry: 1502 // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1503 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1504 // CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1505 // CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1506 // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 1507 // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1508 // CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 1509 // CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 1510 // CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 8 1511 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1512 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1513 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1514 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1515 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1516 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1517 // CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 1518 // CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 1519 // CHECK8-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1520 // CHECK8-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 1521 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 1522 // CHECK8-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1523 // CHECK8-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1524 // CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1525 // CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1526 // CHECK8-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 1527 // CHECK8-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 1528 // CHECK8-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 1529 // CHECK8-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 1530 // CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 1531 // CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 1532 // CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 1533 // CHECK8-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 1534 // CHECK8-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1535 // CHECK8-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1536 // CHECK8-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 1537 // CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 1538 // CHECK8-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 1539 // CHECK8-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32 1540 // CHECK8-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 1541 // CHECK8-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 1542 // CHECK8-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1543 // CHECK8-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1544 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false) 1545 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 1546 // CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 1547 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 1548 // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1549 // CHECK8: omp.arraycpy.body: 1550 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1551 // CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1552 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false) 1553 // CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1554 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1555 // CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 1556 // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]] 1557 // CHECK8: omp.arraycpy.done5: 1558 // CHECK8-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 1559 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR6]], ptr align 4 [[TMP6]], i64 4, i1 false) 1560 // CHECK8-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 1561 // CHECK8-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1562 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 1563 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1564 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1565 // CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 1566 // CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1567 // CHECK8: cond.true: 1568 // CHECK8-NEXT: br label [[COND_END:%.*]] 1569 // CHECK8: cond.false: 1570 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1571 // CHECK8-NEXT: br label [[COND_END]] 1572 // CHECK8: cond.end: 1573 // CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 1574 // CHECK8-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1575 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1576 // CHECK8-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 1577 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1578 // CHECK8: omp.inner.for.cond: 1579 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1580 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1581 // CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 1582 // CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1583 // CHECK8: omp.inner.for.cond.cleanup: 1584 // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1585 // CHECK8: omp.inner.for.body: 1586 // CHECK8-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1587 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 1588 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1589 // CHECK8-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1590 // CHECK8-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1591 // CHECK8-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 1592 // CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 1593 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] 1594 // CHECK8-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 1595 // CHECK8-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8 1596 // CHECK8-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 1597 // CHECK8-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 1598 // CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] 1599 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false) 1600 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1601 // CHECK8: omp.body.continue: 1602 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1603 // CHECK8: omp.inner.for.inc: 1604 // CHECK8-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1605 // CHECK8-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP19]], 1 1606 // CHECK8-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4 1607 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]] 1608 // CHECK8: omp.inner.for.end: 1609 // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1610 // CHECK8: omp.loop.exit: 1611 // CHECK8-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1612 // CHECK8-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 1613 // CHECK8-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 1614 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] 1615 // CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 1616 // CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 1617 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1618 // CHECK8: arraydestroy.body: 1619 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1620 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1621 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1622 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 1623 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 1624 // CHECK8: arraydestroy.done13: 1625 // CHECK8-NEXT: ret void 1626 // 1627 // 1628 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1629 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1630 // CHECK8-NEXT: entry: 1631 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1632 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1633 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1634 // CHECK8-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1635 // CHECK8-NEXT: ret void 1636 // 1637 // 1638 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1639 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1640 // CHECK8-NEXT: entry: 1641 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1642 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1643 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1644 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1645 // CHECK8-NEXT: store i32 0, ptr [[F]], align 4 1646 // CHECK8-NEXT: ret void 1647 // 1648 // 1649 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1650 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1651 // CHECK8-NEXT: entry: 1652 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1653 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1654 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1655 // CHECK8-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1656 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1657 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1658 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1659 // CHECK8-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1660 // CHECK8-NEXT: ret void 1661 // 1662 // 1663 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1664 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1665 // CHECK8-NEXT: entry: 1666 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1667 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1668 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1669 // CHECK8-NEXT: ret void 1670 // 1671 // 1672 // CHECK10-LABEL: define {{[^@]+}}@main 1673 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { 1674 // CHECK10-NEXT: entry: 1675 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1676 // CHECK10-NEXT: [[G:%.*]] = alloca double, align 8 1677 // CHECK10-NEXT: [[G1:%.*]] = alloca ptr, align 4 1678 // CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1679 // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1680 // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1681 // CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1682 // CHECK10-NEXT: [[VAR:%.*]] = alloca ptr, align 4 1683 // CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1684 // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1685 // CHECK10-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 1686 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 1687 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 1688 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 1689 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1690 // CHECK10-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1691 // CHECK10-NEXT: store i32 0, ptr [[RETVAL]], align 4 1692 // CHECK10-NEXT: store ptr [[G]], ptr [[G1]], align 4 1693 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1694 // CHECK10-NEXT: store i32 0, ptr [[T_VAR]], align 4 1695 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false) 1696 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00) 1697 // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 1 1698 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) 1699 // CHECK10-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 1700 // CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 1701 // CHECK10-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 1702 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 1703 // CHECK10-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 1704 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1705 // CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 1706 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 1707 // CHECK10-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 1708 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 1709 // CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 1710 // CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4 1711 // CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1712 // CHECK10-NEXT: store i32 [[TMP2]], ptr [[TMP8]], align 4 1713 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1714 // CHECK10-NEXT: store i32 [[TMP2]], ptr [[TMP9]], align 4 1715 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1716 // CHECK10-NEXT: store ptr null, ptr [[TMP10]], align 4 1717 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1718 // CHECK10-NEXT: store ptr [[VEC]], ptr [[TMP11]], align 4 1719 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1720 // CHECK10-NEXT: store ptr [[VEC]], ptr [[TMP12]], align 4 1721 // CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1722 // CHECK10-NEXT: store ptr null, ptr [[TMP13]], align 4 1723 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1724 // CHECK10-NEXT: store ptr [[S_ARR]], ptr [[TMP14]], align 4 1725 // CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1726 // CHECK10-NEXT: store ptr [[S_ARR]], ptr [[TMP15]], align 4 1727 // CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1728 // CHECK10-NEXT: store ptr null, ptr [[TMP16]], align 4 1729 // CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1730 // CHECK10-NEXT: store ptr [[TMP6]], ptr [[TMP17]], align 4 1731 // CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1732 // CHECK10-NEXT: store ptr [[TMP7]], ptr [[TMP18]], align 4 1733 // CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1734 // CHECK10-NEXT: store ptr null, ptr [[TMP19]], align 4 1735 // CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1736 // CHECK10-NEXT: store i32 [[TMP5]], ptr [[TMP20]], align 4 1737 // CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1738 // CHECK10-NEXT: store i32 [[TMP5]], ptr [[TMP21]], align 4 1739 // CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1740 // CHECK10-NEXT: store ptr null, ptr [[TMP22]], align 4 1741 // CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1742 // CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1743 // CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1744 // CHECK10-NEXT: store i32 3, ptr [[TMP25]], align 4 1745 // CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1746 // CHECK10-NEXT: store i32 5, ptr [[TMP26]], align 4 1747 // CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1748 // CHECK10-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 4 1749 // CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1750 // CHECK10-NEXT: store ptr [[TMP24]], ptr [[TMP28]], align 4 1751 // CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1752 // CHECK10-NEXT: store ptr @.offload_sizes, ptr [[TMP29]], align 4 1753 // CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1754 // CHECK10-NEXT: store ptr @.offload_maptypes, ptr [[TMP30]], align 4 1755 // CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1756 // CHECK10-NEXT: store ptr null, ptr [[TMP31]], align 4 1757 // CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1758 // CHECK10-NEXT: store ptr null, ptr [[TMP32]], align 4 1759 // CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1760 // CHECK10-NEXT: store i64 2, ptr [[TMP33]], align 8 1761 // CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1762 // CHECK10-NEXT: store i64 0, ptr [[TMP34]], align 8 1763 // CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1764 // CHECK10-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4 1765 // CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1766 // CHECK10-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP36]], align 4 1767 // CHECK10-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1768 // CHECK10-NEXT: store i32 0, ptr [[TMP37]], align 4 1769 // CHECK10-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.region_id, ptr [[KERNEL_ARGS]]) 1770 // CHECK10-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 1771 // CHECK10-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1772 // CHECK10: omp_offload.failed: 1773 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]], i32 [[TMP5]]) #[[ATTR4:[0-9]+]] 1774 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] 1775 // CHECK10: omp_offload.cont: 1776 // CHECK10-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1777 // CHECK10-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 1778 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1779 // CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1780 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1781 // CHECK10: arraydestroy.body: 1782 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1783 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1784 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1785 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1786 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1787 // CHECK10: arraydestroy.done2: 1788 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 1789 // CHECK10-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 1790 // CHECK10-NEXT: ret i32 [[TMP41]] 1791 // 1792 // 1793 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1794 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1795 // CHECK10-NEXT: entry: 1796 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1797 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1798 // CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1799 // CHECK10-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1800 // CHECK10-NEXT: ret void 1801 // 1802 // 1803 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1804 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1805 // CHECK10-NEXT: entry: 1806 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1807 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1808 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1809 // CHECK10-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1810 // CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1811 // CHECK10-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1812 // CHECK10-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1813 // CHECK10-NEXT: ret void 1814 // 1815 // 1816 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 1817 // CHECK10-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { 1818 // CHECK10-NEXT: entry: 1819 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1820 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1821 // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1822 // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1823 // CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 1824 // CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1825 // CHECK10-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1826 // CHECK10-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1827 // CHECK10-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1828 // CHECK10-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1829 // CHECK10-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 1830 // CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1831 // CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1832 // CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1833 // CHECK10-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 1834 // CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 1835 // CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]]) 1836 // CHECK10-NEXT: ret void 1837 // 1838 // 1839 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.omp_outlined 1840 // CHECK10-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { 1841 // CHECK10-NEXT: entry: 1842 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1843 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1844 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 1845 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1846 // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1847 // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1848 // CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca ptr, align 4 1849 // CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1850 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 1851 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1852 // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 1853 // CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1854 // CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1855 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1856 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1857 // CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 1858 // CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 1859 // CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 1860 // CHECK10-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1861 // CHECK10-NEXT: [[_TMP8:%.*]] = alloca ptr, align 4 1862 // CHECK10-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 1863 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 1864 // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1865 // CHECK10-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 1866 // CHECK10-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1867 // CHECK10-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1868 // CHECK10-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1869 // CHECK10-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1870 // CHECK10-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1871 // CHECK10-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1872 // CHECK10-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 1873 // CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 1874 // CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1875 // CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1876 // CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1877 // CHECK10-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 1878 // CHECK10-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 1879 // CHECK10-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 1880 // CHECK10-NEXT: store ptr [[TMP5]], ptr [[_TMP1]], align 4 1881 // CHECK10-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 1882 // CHECK10-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 1883 // CHECK10-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1884 // CHECK10-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1885 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4 1886 // CHECK10-NEXT: store i32 [[TMP6]], ptr [[T_VAR3]], align 4 1887 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false) 1888 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 1889 // CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1890 // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]] 1891 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1892 // CHECK10: omp.arraycpy.body: 1893 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1894 // CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1895 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false) 1896 // CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1897 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1898 // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]] 1899 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] 1900 // CHECK10: omp.arraycpy.done6: 1901 // CHECK10-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 4 1902 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR7]], ptr align 4 [[TMP8]], i32 4, i1 false) 1903 // CHECK10-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 4 1904 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP4]], align 4 1905 // CHECK10-NEXT: store i32 [[TMP9]], ptr [[SVAR9]], align 4 1906 // CHECK10-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1907 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 1908 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1909 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1910 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 1911 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1912 // CHECK10: cond.true: 1913 // CHECK10-NEXT: br label [[COND_END:%.*]] 1914 // CHECK10: cond.false: 1915 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1916 // CHECK10-NEXT: br label [[COND_END]] 1917 // CHECK10: cond.end: 1918 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] 1919 // CHECK10-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 1920 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1921 // CHECK10-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4 1922 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1923 // CHECK10: omp.inner.for.cond: 1924 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1925 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1926 // CHECK10-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 1927 // CHECK10-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1928 // CHECK10: omp.inner.for.cond.cleanup: 1929 // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1930 // CHECK10: omp.inner.for.body: 1931 // CHECK10-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 1932 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 1933 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR3]], align 4 1934 // CHECK10-NEXT: store i32 [[TMP19]], ptr [[T_VAR_CASTED]], align 4 1935 // CHECK10-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1936 // CHECK10-NEXT: [[TMP21:%.*]] = load ptr, ptr [[_TMP8]], align 4 1937 // CHECK10-NEXT: [[TMP22:%.*]] = load i32, ptr [[SVAR9]], align 4 1938 // CHECK10-NEXT: store i32 [[TMP22]], ptr [[SVAR_CASTED]], align 4 1939 // CHECK10-NEXT: [[TMP23:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 1940 // CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.omp_outlined.omp_outlined, i32 [[TMP17]], i32 [[TMP18]], ptr [[VEC4]], i32 [[TMP20]], ptr [[S_ARR5]], ptr [[TMP21]], i32 [[TMP23]]) 1941 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1942 // CHECK10: omp.inner.for.inc: 1943 // CHECK10-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1944 // CHECK10-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1945 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] 1946 // CHECK10-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 1947 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 1948 // CHECK10: omp.inner.for.end: 1949 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1950 // CHECK10: omp.loop.exit: 1951 // CHECK10-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1952 // CHECK10-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4 1953 // CHECK10-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP27]]) 1954 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] 1955 // CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 1956 // CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 1957 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1958 // CHECK10: arraydestroy.body: 1959 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1960 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1961 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1962 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 1963 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 1964 // CHECK10: arraydestroy.done12: 1965 // CHECK10-NEXT: ret void 1966 // 1967 // 1968 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.omp_outlined.omp_outlined 1969 // CHECK10-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] { 1970 // CHECK10-NEXT: entry: 1971 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1972 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1973 // CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 1974 // CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 1975 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1976 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1977 // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1978 // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1979 // CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 1980 // CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 4 1981 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1982 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1983 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1984 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1985 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1986 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1987 // CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 1988 // CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 1989 // CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1990 // CHECK10-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 1991 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 1992 // CHECK10-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1993 // CHECK10-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1994 // CHECK10-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 1995 // CHECK10-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 1996 // CHECK10-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1997 // CHECK10-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1998 // CHECK10-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1999 // CHECK10-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 2000 // CHECK10-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 2001 // CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 2002 // CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 2003 // CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 2004 // CHECK10-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 2005 // CHECK10-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2006 // CHECK10-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2007 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 2008 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 2009 // CHECK10-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4 2010 // CHECK10-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 2011 // CHECK10-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2012 // CHECK10-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2013 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) 2014 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 2015 // CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 2016 // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 2017 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2018 // CHECK10: omp.arraycpy.body: 2019 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2020 // CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2021 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false) 2022 // CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2023 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2024 // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 2025 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 2026 // CHECK10: omp.arraycpy.done4: 2027 // CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 2028 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR5]], ptr align 4 [[TMP6]], i32 4, i1 false) 2029 // CHECK10-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 2030 // CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2031 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 2032 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2033 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2034 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 2035 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2036 // CHECK10: cond.true: 2037 // CHECK10-NEXT: br label [[COND_END:%.*]] 2038 // CHECK10: cond.false: 2039 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2040 // CHECK10-NEXT: br label [[COND_END]] 2041 // CHECK10: cond.end: 2042 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 2043 // CHECK10-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2044 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2045 // CHECK10-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 2046 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2047 // CHECK10: omp.inner.for.cond: 2048 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2049 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2050 // CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 2051 // CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2052 // CHECK10: omp.inner.for.cond.cleanup: 2053 // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2054 // CHECK10: omp.inner.for.body: 2055 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2056 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 2057 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2058 // CHECK10-NEXT: store i32 [[ADD]], ptr [[I]], align 4 2059 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 2060 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 2061 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]] 2062 // CHECK10-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 2063 // CHECK10-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4 2064 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 2065 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] 2066 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false) 2067 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2068 // CHECK10: omp.body.continue: 2069 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2070 // CHECK10: omp.inner.for.inc: 2071 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2072 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1 2073 // CHECK10-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4 2074 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 2075 // CHECK10: omp.inner.for.end: 2076 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2077 // CHECK10: omp.loop.exit: 2078 // CHECK10-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2079 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 2080 // CHECK10-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 2081 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 2082 // CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 2083 // CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 2084 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2085 // CHECK10: arraydestroy.body: 2086 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2087 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2088 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2089 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 2090 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 2091 // CHECK10: arraydestroy.done11: 2092 // CHECK10-NEXT: ret void 2093 // 2094 // 2095 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2096 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2097 // CHECK10-NEXT: entry: 2098 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2099 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2100 // CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2101 // CHECK10-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 2102 // CHECK10-NEXT: ret void 2103 // 2104 // 2105 // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2106 // CHECK10-SAME: () #[[ATTR1]] comdat { 2107 // CHECK10-NEXT: entry: 2108 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2109 // CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2110 // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2111 // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2112 // CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2113 // CHECK10-NEXT: [[VAR:%.*]] = alloca ptr, align 4 2114 // CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 4 2115 // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2116 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 2117 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 2118 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 2119 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2120 // CHECK10-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2121 // CHECK10-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 2122 // CHECK10-NEXT: store i32 0, ptr [[T_VAR]], align 4 2123 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 2124 // CHECK10-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 2125 // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 2126 // CHECK10-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 2127 // CHECK10-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 2128 // CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 2129 // CHECK10-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 2130 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 2131 // CHECK10-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 2132 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 2133 // CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 2134 // CHECK10-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 2135 // CHECK10-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 2136 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2137 // CHECK10-NEXT: store i32 [[TMP2]], ptr [[TMP6]], align 4 2138 // CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2139 // CHECK10-NEXT: store i32 [[TMP2]], ptr [[TMP7]], align 4 2140 // CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2141 // CHECK10-NEXT: store ptr null, ptr [[TMP8]], align 4 2142 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2143 // CHECK10-NEXT: store ptr [[VEC]], ptr [[TMP9]], align 4 2144 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2145 // CHECK10-NEXT: store ptr [[VEC]], ptr [[TMP10]], align 4 2146 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2147 // CHECK10-NEXT: store ptr null, ptr [[TMP11]], align 4 2148 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2149 // CHECK10-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 4 2150 // CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2151 // CHECK10-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 4 2152 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2153 // CHECK10-NEXT: store ptr null, ptr [[TMP14]], align 4 2154 // CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2155 // CHECK10-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 4 2156 // CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2157 // CHECK10-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 4 2158 // CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2159 // CHECK10-NEXT: store ptr null, ptr [[TMP17]], align 4 2160 // CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2161 // CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2162 // CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2163 // CHECK10-NEXT: store i32 3, ptr [[TMP20]], align 4 2164 // CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2165 // CHECK10-NEXT: store i32 4, ptr [[TMP21]], align 4 2166 // CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2167 // CHECK10-NEXT: store ptr [[TMP18]], ptr [[TMP22]], align 4 2168 // CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2169 // CHECK10-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4 2170 // CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2171 // CHECK10-NEXT: store ptr @.offload_sizes.1, ptr [[TMP24]], align 4 2172 // CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2173 // CHECK10-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP25]], align 4 2174 // CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 2175 // CHECK10-NEXT: store ptr null, ptr [[TMP26]], align 4 2176 // CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 2177 // CHECK10-NEXT: store ptr null, ptr [[TMP27]], align 4 2178 // CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 2179 // CHECK10-NEXT: store i64 2, ptr [[TMP28]], align 8 2180 // CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 2181 // CHECK10-NEXT: store i64 0, ptr [[TMP29]], align 8 2182 // CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 2183 // CHECK10-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4 2184 // CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 2185 // CHECK10-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 2186 // CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 2187 // CHECK10-NEXT: store i32 0, ptr [[TMP32]], align 4 2188 // CHECK10-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.region_id, ptr [[KERNEL_ARGS]]) 2189 // CHECK10-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 2190 // CHECK10-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2191 // CHECK10: omp_offload.failed: 2192 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]] 2193 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] 2194 // CHECK10: omp_offload.cont: 2195 // CHECK10-NEXT: store i32 0, ptr [[RETVAL]], align 4 2196 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 2197 // CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 2198 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2199 // CHECK10: arraydestroy.body: 2200 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2201 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2202 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2203 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2204 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 2205 // CHECK10: arraydestroy.done2: 2206 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 2207 // CHECK10-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 2208 // CHECK10-NEXT: ret i32 [[TMP36]] 2209 // 2210 // 2211 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2212 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2213 // CHECK10-NEXT: entry: 2214 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2215 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2216 // CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2217 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2218 // CHECK10-NEXT: store float 0.000000e+00, ptr [[F]], align 4 2219 // CHECK10-NEXT: ret void 2220 // 2221 // 2222 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2223 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2224 // CHECK10-NEXT: entry: 2225 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2226 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2227 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2228 // CHECK10-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2229 // CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2230 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2231 // CHECK10-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2232 // CHECK10-NEXT: store float [[TMP0]], ptr [[F]], align 4 2233 // CHECK10-NEXT: ret void 2234 // 2235 // 2236 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2237 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2238 // CHECK10-NEXT: entry: 2239 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2240 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2241 // CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2242 // CHECK10-NEXT: ret void 2243 // 2244 // 2245 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2246 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2247 // CHECK10-NEXT: entry: 2248 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2249 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2250 // CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2251 // CHECK10-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2252 // CHECK10-NEXT: ret void 2253 // 2254 // 2255 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2256 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2257 // CHECK10-NEXT: entry: 2258 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2259 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2260 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2261 // CHECK10-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2262 // CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2263 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2264 // CHECK10-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 2265 // CHECK10-NEXT: ret void 2266 // 2267 // 2268 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48 2269 // CHECK10-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 2270 // CHECK10-NEXT: entry: 2271 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2272 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 2273 // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 2274 // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 2275 // CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 4 2276 // CHECK10-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 2277 // CHECK10-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 2278 // CHECK10-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 2279 // CHECK10-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 2280 // CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 2281 // CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 2282 // CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 2283 // CHECK10-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 2284 // CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 2285 // CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]]) 2286 // CHECK10-NEXT: ret void 2287 // 2288 // 2289 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined 2290 // CHECK10-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 2291 // CHECK10-NEXT: entry: 2292 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2293 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2294 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 2295 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 2296 // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 2297 // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 2298 // CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 4 2299 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 2300 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2301 // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 2302 // CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2303 // CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2304 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2305 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2306 // CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 2307 // CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 2308 // CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 2309 // CHECK10-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2310 // CHECK10-NEXT: [[_TMP8:%.*]] = alloca ptr, align 4 2311 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 2312 // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2313 // CHECK10-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2314 // CHECK10-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2315 // CHECK10-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 2316 // CHECK10-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 2317 // CHECK10-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 2318 // CHECK10-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 2319 // CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 2320 // CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 2321 // CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 2322 // CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 2323 // CHECK10-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 2324 // CHECK10-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 2325 // CHECK10-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 4 2326 // CHECK10-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 2327 // CHECK10-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 2328 // CHECK10-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2329 // CHECK10-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2330 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 2331 // CHECK10-NEXT: store i32 [[TMP5]], ptr [[T_VAR3]], align 4 2332 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false) 2333 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 2334 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 2335 // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]] 2336 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2337 // CHECK10: omp.arraycpy.body: 2338 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2339 // CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2340 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false) 2341 // CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2342 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2343 // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 2344 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] 2345 // CHECK10: omp.arraycpy.done6: 2346 // CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 4 2347 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR7]], ptr align 4 [[TMP7]], i32 4, i1 false) 2348 // CHECK10-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 4 2349 // CHECK10-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2350 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 2351 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2352 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2353 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 2354 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2355 // CHECK10: cond.true: 2356 // CHECK10-NEXT: br label [[COND_END:%.*]] 2357 // CHECK10: cond.false: 2358 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2359 // CHECK10-NEXT: br label [[COND_END]] 2360 // CHECK10: cond.end: 2361 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 2362 // CHECK10-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 2363 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2364 // CHECK10-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 2365 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2366 // CHECK10: omp.inner.for.cond: 2367 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2368 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2369 // CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 2370 // CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2371 // CHECK10: omp.inner.for.cond.cleanup: 2372 // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2373 // CHECK10: omp.inner.for.body: 2374 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 2375 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 2376 // CHECK10-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR3]], align 4 2377 // CHECK10-NEXT: store i32 [[TMP17]], ptr [[T_VAR_CASTED]], align 4 2378 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 2379 // CHECK10-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP8]], align 4 2380 // CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined.omp_outlined, i32 [[TMP15]], i32 [[TMP16]], ptr [[VEC4]], i32 [[TMP18]], ptr [[S_ARR5]], ptr [[TMP19]]) 2381 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2382 // CHECK10: omp.inner.for.inc: 2383 // CHECK10-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2384 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2385 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] 2386 // CHECK10-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 2387 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 2388 // CHECK10: omp.inner.for.end: 2389 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2390 // CHECK10: omp.loop.exit: 2391 // CHECK10-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2392 // CHECK10-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4 2393 // CHECK10-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP23]]) 2394 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] 2395 // CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 2396 // CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 2397 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2398 // CHECK10: arraydestroy.body: 2399 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2400 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2401 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2402 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 2403 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 2404 // CHECK10: arraydestroy.done11: 2405 // CHECK10-NEXT: ret void 2406 // 2407 // 2408 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined.omp_outlined 2409 // CHECK10-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 2410 // CHECK10-NEXT: entry: 2411 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2412 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2413 // CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 2414 // CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 2415 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 2416 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2417 // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 2418 // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 2419 // CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 4 2420 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2421 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2422 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2423 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2424 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2425 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2426 // CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 2427 // CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 2428 // CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2429 // CHECK10-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 2430 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 2431 // CHECK10-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2432 // CHECK10-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2433 // CHECK10-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 2434 // CHECK10-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 2435 // CHECK10-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 2436 // CHECK10-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 2437 // CHECK10-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 2438 // CHECK10-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 2439 // CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 2440 // CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 2441 // CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 2442 // CHECK10-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 2443 // CHECK10-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2444 // CHECK10-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2445 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 2446 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 2447 // CHECK10-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4 2448 // CHECK10-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 2449 // CHECK10-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2450 // CHECK10-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2451 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) 2452 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 2453 // CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 2454 // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 2455 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2456 // CHECK10: omp.arraycpy.body: 2457 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2458 // CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2459 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false) 2460 // CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2461 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2462 // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 2463 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 2464 // CHECK10: omp.arraycpy.done4: 2465 // CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 2466 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR5]], ptr align 4 [[TMP6]], i32 4, i1 false) 2467 // CHECK10-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 2468 // CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2469 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 2470 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2471 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2472 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 2473 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2474 // CHECK10: cond.true: 2475 // CHECK10-NEXT: br label [[COND_END:%.*]] 2476 // CHECK10: cond.false: 2477 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2478 // CHECK10-NEXT: br label [[COND_END]] 2479 // CHECK10: cond.end: 2480 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 2481 // CHECK10-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2482 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2483 // CHECK10-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 2484 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2485 // CHECK10: omp.inner.for.cond: 2486 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2487 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2488 // CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 2489 // CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2490 // CHECK10: omp.inner.for.cond.cleanup: 2491 // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2492 // CHECK10: omp.inner.for.body: 2493 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2494 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 2495 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2496 // CHECK10-NEXT: store i32 [[ADD]], ptr [[I]], align 4 2497 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 2498 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 2499 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]] 2500 // CHECK10-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 2501 // CHECK10-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4 2502 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 2503 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] 2504 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false) 2505 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2506 // CHECK10: omp.body.continue: 2507 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2508 // CHECK10: omp.inner.for.inc: 2509 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2510 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1 2511 // CHECK10-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4 2512 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 2513 // CHECK10: omp.inner.for.end: 2514 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2515 // CHECK10: omp.loop.exit: 2516 // CHECK10-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2517 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 2518 // CHECK10-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) 2519 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 2520 // CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 2521 // CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 2522 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2523 // CHECK10: arraydestroy.body: 2524 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2525 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2526 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2527 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 2528 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 2529 // CHECK10: arraydestroy.done11: 2530 // CHECK10-NEXT: ret void 2531 // 2532 // 2533 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2534 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2535 // CHECK10-NEXT: entry: 2536 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2537 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2538 // CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2539 // CHECK10-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 2540 // CHECK10-NEXT: ret void 2541 // 2542 // 2543 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2544 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2545 // CHECK10-NEXT: entry: 2546 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2547 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2548 // CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2549 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2550 // CHECK10-NEXT: store i32 0, ptr [[F]], align 4 2551 // CHECK10-NEXT: ret void 2552 // 2553 // 2554 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2555 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2556 // CHECK10-NEXT: entry: 2557 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2558 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2559 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2560 // CHECK10-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2561 // CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2562 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 2563 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2564 // CHECK10-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 2565 // CHECK10-NEXT: ret void 2566 // 2567 // 2568 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2569 // CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2570 // CHECK10-NEXT: entry: 2571 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2572 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2573 // CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2574 // CHECK10-NEXT: ret void 2575 // 2576